feat: add display UI with splash screen, dashboard, and RSSI sparkline
Implement full SSD1306 OLED display support: - Splash screen on boot (1.5s) with project name, version, board - Dashboard showing radio state, config, counters, RSSI/SNR - RSSI history sparkline (64-sample ring buffer, 2px-wide bars) - DisplayOn/DisplayOff host commands routed via dedicated channel - Pure render functions against generic DrawTarget (no hardware coupling) - Display on/off control bypasses radio task entirely Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
This commit is contained in:
17624 files changed
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+174
@@ -0,0 +1,174 @@
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pub use nrf51_pac as pac;
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/// The maximum buffer size that the EasyDMA can send/recv in one operation.
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pub const EASY_DMA_SIZE: usize = (1 << 14) - 1;
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pub const FLASH_SIZE: usize = 128 * 1024;
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embassy_hal_internal::peripherals! {
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// RTC
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RTC0,
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RTC1,
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// WDT
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WDT,
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// NVMC
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NVMC,
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// RNG
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RNG,
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// UARTE
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UART0,
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// SPI/TWI
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TWI0,
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SPI0,
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// ADC
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ADC,
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// TIMER
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TIMER0,
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TIMER1,
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TIMER2,
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// GPIOTE
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GPIOTE_CH0,
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GPIOTE_CH1,
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GPIOTE_CH2,
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GPIOTE_CH3,
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// PPI
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PPI_CH0,
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PPI_CH1,
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PPI_CH2,
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PPI_CH3,
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PPI_CH4,
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PPI_CH5,
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PPI_CH6,
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PPI_CH7,
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PPI_CH8,
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PPI_CH9,
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PPI_CH10,
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PPI_CH11,
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PPI_CH12,
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PPI_CH13,
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PPI_CH14,
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PPI_CH15,
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PPI_GROUP0,
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PPI_GROUP1,
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PPI_GROUP2,
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PPI_GROUP3,
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// GPIO port 0
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P0_00,
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P0_01,
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P0_02,
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P0_03,
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P0_04,
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P0_05,
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P0_06,
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P0_07,
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P0_08,
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P0_09,
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P0_10,
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P0_11,
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P0_12,
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P0_13,
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P0_14,
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P0_15,
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P0_16,
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P0_17,
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P0_18,
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P0_19,
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P0_20,
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P0_21,
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P0_22,
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P0_23,
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P0_24,
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P0_25,
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P0_26,
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P0_27,
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P0_28,
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P0_29,
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P0_30,
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P0_31,
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// TEMP
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TEMP,
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// Radio
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RADIO,
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}
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impl_timer!(TIMER0, TIMER0, TIMER0);
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impl_timer!(TIMER1, TIMER1, TIMER1);
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impl_timer!(TIMER2, TIMER2, TIMER2);
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impl_rng!(RNG, RNG, RNG);
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impl_pin!(P0_00, 0, 0);
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impl_pin!(P0_01, 0, 1);
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impl_pin!(P0_02, 0, 2);
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impl_pin!(P0_03, 0, 3);
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impl_pin!(P0_04, 0, 4);
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impl_pin!(P0_05, 0, 5);
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impl_pin!(P0_06, 0, 6);
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impl_pin!(P0_07, 0, 7);
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impl_pin!(P0_08, 0, 8);
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impl_pin!(P0_09, 0, 9);
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impl_pin!(P0_10, 0, 10);
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impl_pin!(P0_11, 0, 11);
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impl_pin!(P0_12, 0, 12);
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impl_pin!(P0_13, 0, 13);
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impl_pin!(P0_14, 0, 14);
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impl_pin!(P0_15, 0, 15);
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impl_pin!(P0_16, 0, 16);
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impl_pin!(P0_17, 0, 17);
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impl_pin!(P0_18, 0, 18);
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impl_pin!(P0_19, 0, 19);
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impl_pin!(P0_20, 0, 20);
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impl_pin!(P0_21, 0, 21);
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impl_pin!(P0_22, 0, 22);
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impl_pin!(P0_23, 0, 23);
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impl_pin!(P0_24, 0, 24);
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impl_pin!(P0_25, 0, 25);
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impl_pin!(P0_26, 0, 26);
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impl_pin!(P0_27, 0, 27);
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impl_pin!(P0_28, 0, 28);
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impl_pin!(P0_29, 0, 29);
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impl_pin!(P0_30, 0, 30);
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impl_pin!(P0_31, 0, 31);
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impl_radio!(RADIO, RADIO, RADIO);
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embassy_hal_internal::interrupt_mod!(
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POWER_CLOCK,
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RADIO,
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UART0,
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SPI0_TWI0,
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SPI1_TWI1,
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GPIOTE,
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ADC,
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TIMER0,
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TIMER1,
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TIMER2,
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RTC0,
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TEMP,
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RNG,
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ECB,
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CCM_AAR,
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WDT,
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RTC1,
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QDEC,
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LPCOMP,
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SWI0,
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SWI1,
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SWI2,
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SWI3,
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SWI4,
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SWI5,
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);
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+249
@@ -0,0 +1,249 @@
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pub use nrf52805_pac as pac;
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/// The maximum buffer size that the EasyDMA can send/recv in one operation.
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pub const EASY_DMA_SIZE: usize = (1 << 14) - 1;
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pub const FORCE_COPY_BUFFER_SIZE: usize = 256;
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pub const FLASH_SIZE: usize = 192 * 1024;
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pub const RESET_PIN: u32 = 21;
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pub const APPROTECT_MIN_BUILD_CODE: u8 = b'B';
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embassy_hal_internal::peripherals! {
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// RTC
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RTC0,
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RTC1,
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// WDT
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WDT,
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// NVMC
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NVMC,
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// RNG
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RNG,
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// UARTE
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UARTE0,
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// SPI/TWI
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TWI0,
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SPI0,
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// SAADC
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SAADC,
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// TIMER
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TIMER0,
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TIMER1,
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TIMER2,
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// GPIOTE
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GPIOTE_CH0,
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GPIOTE_CH1,
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GPIOTE_CH2,
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GPIOTE_CH3,
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GPIOTE_CH4,
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GPIOTE_CH5,
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GPIOTE_CH6,
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GPIOTE_CH7,
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// PPI
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PPI_CH0,
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PPI_CH1,
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PPI_CH2,
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PPI_CH3,
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PPI_CH4,
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PPI_CH5,
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PPI_CH6,
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PPI_CH7,
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PPI_CH8,
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PPI_CH9,
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PPI_CH10,
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PPI_CH11,
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PPI_CH12,
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PPI_CH13,
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PPI_CH14,
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PPI_CH15,
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PPI_CH16,
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PPI_CH17,
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PPI_CH18,
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PPI_CH19,
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PPI_CH20,
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PPI_CH21,
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PPI_CH22,
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PPI_CH23,
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PPI_CH24,
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PPI_CH25,
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PPI_CH26,
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PPI_CH27,
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PPI_CH28,
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PPI_CH29,
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PPI_CH30,
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PPI_CH31,
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PPI_GROUP0,
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PPI_GROUP1,
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PPI_GROUP2,
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PPI_GROUP3,
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PPI_GROUP4,
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PPI_GROUP5,
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// GPIO port 0
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P0_00,
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P0_01,
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P0_02,
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P0_03,
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P0_04,
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P0_05,
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P0_06,
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P0_07,
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P0_08,
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P0_09,
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P0_10,
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P0_11,
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P0_12,
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P0_13,
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P0_14,
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P0_15,
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P0_16,
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P0_17,
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P0_18,
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P0_19,
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P0_20,
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#[cfg(feature="reset-pin-as-gpio")]
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P0_21,
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P0_22,
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P0_23,
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P0_24,
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P0_25,
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P0_26,
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P0_27,
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P0_28,
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P0_29,
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P0_30,
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P0_31,
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// TEMP
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TEMP,
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// QDEC
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QDEC,
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// Radio
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RADIO,
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// EGU
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EGU0,
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EGU1,
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}
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impl_uarte!(UARTE0, UARTE0, UARTE0_UART0);
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impl_spim!(SPI0, SPIM0, SPIM0_SPIS0_SPI0);
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impl_spis!(SPI0, SPIS0, SPIM0_SPIS0_SPI0);
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impl_twim!(TWI0, TWIM0, TWIM0_TWIS0_TWI0);
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impl_twis!(TWI0, TWIS0, TWIM0_TWIS0_TWI0);
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impl_qdec!(QDEC, QDEC, QDEC);
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impl_rng!(RNG, RNG, RNG);
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impl_timer!(TIMER0, TIMER0, TIMER0);
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impl_timer!(TIMER1, TIMER1, TIMER1);
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impl_timer!(TIMER2, TIMER2, TIMER2);
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impl_pin!(P0_00, 0, 0);
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impl_pin!(P0_01, 0, 1);
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impl_pin!(P0_02, 0, 2);
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impl_pin!(P0_03, 0, 3);
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impl_pin!(P0_04, 0, 4);
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impl_pin!(P0_05, 0, 5);
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impl_pin!(P0_06, 0, 6);
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impl_pin!(P0_07, 0, 7);
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impl_pin!(P0_08, 0, 8);
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impl_pin!(P0_09, 0, 9);
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impl_pin!(P0_10, 0, 10);
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impl_pin!(P0_11, 0, 11);
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impl_pin!(P0_12, 0, 12);
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impl_pin!(P0_13, 0, 13);
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impl_pin!(P0_14, 0, 14);
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impl_pin!(P0_15, 0, 15);
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impl_pin!(P0_16, 0, 16);
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impl_pin!(P0_17, 0, 17);
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impl_pin!(P0_18, 0, 18);
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impl_pin!(P0_19, 0, 19);
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impl_pin!(P0_20, 0, 20);
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#[cfg(feature = "reset-pin-as-gpio")]
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impl_pin!(P0_21, 0, 21);
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impl_pin!(P0_22, 0, 22);
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impl_pin!(P0_23, 0, 23);
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impl_pin!(P0_24, 0, 24);
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impl_pin!(P0_25, 0, 25);
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impl_pin!(P0_26, 0, 26);
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impl_pin!(P0_27, 0, 27);
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impl_pin!(P0_28, 0, 28);
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impl_pin!(P0_29, 0, 29);
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impl_pin!(P0_30, 0, 30);
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impl_pin!(P0_31, 0, 31);
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impl_ppi_channel!(PPI_CH0, 0 => configurable);
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impl_ppi_channel!(PPI_CH1, 1 => configurable);
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impl_ppi_channel!(PPI_CH2, 2 => configurable);
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impl_ppi_channel!(PPI_CH3, 3 => configurable);
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impl_ppi_channel!(PPI_CH4, 4 => configurable);
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impl_ppi_channel!(PPI_CH5, 5 => configurable);
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impl_ppi_channel!(PPI_CH6, 6 => configurable);
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impl_ppi_channel!(PPI_CH7, 7 => configurable);
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impl_ppi_channel!(PPI_CH8, 8 => configurable);
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impl_ppi_channel!(PPI_CH9, 9 => configurable);
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impl_ppi_channel!(PPI_CH20, 20 => static);
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impl_ppi_channel!(PPI_CH21, 21 => static);
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impl_ppi_channel!(PPI_CH22, 22 => static);
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impl_ppi_channel!(PPI_CH23, 23 => static);
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impl_ppi_channel!(PPI_CH24, 24 => static);
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impl_ppi_channel!(PPI_CH25, 25 => static);
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impl_ppi_channel!(PPI_CH26, 26 => static);
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impl_ppi_channel!(PPI_CH27, 27 => static);
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impl_ppi_channel!(PPI_CH28, 28 => static);
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impl_ppi_channel!(PPI_CH29, 29 => static);
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impl_ppi_channel!(PPI_CH30, 30 => static);
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impl_ppi_channel!(PPI_CH31, 31 => static);
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impl_saadc_input!(P0_04, ANALOG_INPUT2);
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impl_saadc_input!(P0_05, ANALOG_INPUT3);
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impl_radio!(RADIO, RADIO, RADIO);
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impl_egu!(EGU0, EGU0, SWI0_EGU0);
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impl_egu!(EGU1, EGU1, SWI1_EGU1);
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embassy_hal_internal::interrupt_mod!(
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POWER_CLOCK,
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RADIO,
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UARTE0_UART0,
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TWIM0_TWIS0_TWI0,
|
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SPIM0_SPIS0_SPI0,
|
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GPIOTE,
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SAADC,
|
||||
TIMER0,
|
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TIMER1,
|
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TIMER2,
|
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RTC0,
|
||||
TEMP,
|
||||
RNG,
|
||||
ECB,
|
||||
CCM_AAR,
|
||||
WDT,
|
||||
RTC1,
|
||||
QDEC,
|
||||
SWI0_EGU0,
|
||||
SWI1_EGU1,
|
||||
SWI2,
|
||||
SWI3,
|
||||
SWI4,
|
||||
SWI5,
|
||||
);
|
||||
+278
@@ -0,0 +1,278 @@
|
||||
pub use nrf52810_pac as pac;
|
||||
|
||||
/// The maximum buffer size that the EasyDMA can send/recv in one operation.
|
||||
pub const EASY_DMA_SIZE: usize = (1 << 10) - 1;
|
||||
pub const FORCE_COPY_BUFFER_SIZE: usize = 256;
|
||||
|
||||
pub const FLASH_SIZE: usize = 192 * 1024;
|
||||
|
||||
pub const RESET_PIN: u32 = 21;
|
||||
pub const APPROTECT_MIN_BUILD_CODE: u8 = b'E';
|
||||
|
||||
embassy_hal_internal::peripherals! {
|
||||
// RTC
|
||||
RTC0,
|
||||
RTC1,
|
||||
|
||||
// WDT
|
||||
WDT,
|
||||
|
||||
// NVMC
|
||||
NVMC,
|
||||
|
||||
// RNG
|
||||
RNG,
|
||||
|
||||
// UARTE
|
||||
UARTE0,
|
||||
|
||||
// SPI/TWI
|
||||
TWI0,
|
||||
SPI0,
|
||||
|
||||
// SAADC
|
||||
SAADC,
|
||||
|
||||
// PWM
|
||||
PWM0,
|
||||
|
||||
// TIMER
|
||||
TIMER0,
|
||||
TIMER1,
|
||||
TIMER2,
|
||||
|
||||
// GPIOTE
|
||||
GPIOTE_CH0,
|
||||
GPIOTE_CH1,
|
||||
GPIOTE_CH2,
|
||||
GPIOTE_CH3,
|
||||
GPIOTE_CH4,
|
||||
GPIOTE_CH5,
|
||||
GPIOTE_CH6,
|
||||
GPIOTE_CH7,
|
||||
|
||||
// PPI
|
||||
PPI_CH0,
|
||||
PPI_CH1,
|
||||
PPI_CH2,
|
||||
PPI_CH3,
|
||||
PPI_CH4,
|
||||
PPI_CH5,
|
||||
PPI_CH6,
|
||||
PPI_CH7,
|
||||
PPI_CH8,
|
||||
PPI_CH9,
|
||||
PPI_CH10,
|
||||
PPI_CH11,
|
||||
PPI_CH12,
|
||||
PPI_CH13,
|
||||
PPI_CH14,
|
||||
PPI_CH15,
|
||||
PPI_CH16,
|
||||
PPI_CH17,
|
||||
PPI_CH18,
|
||||
PPI_CH19,
|
||||
PPI_CH20,
|
||||
PPI_CH21,
|
||||
PPI_CH22,
|
||||
PPI_CH23,
|
||||
PPI_CH24,
|
||||
PPI_CH25,
|
||||
PPI_CH26,
|
||||
PPI_CH27,
|
||||
PPI_CH28,
|
||||
PPI_CH29,
|
||||
PPI_CH30,
|
||||
PPI_CH31,
|
||||
|
||||
PPI_GROUP0,
|
||||
PPI_GROUP1,
|
||||
PPI_GROUP2,
|
||||
PPI_GROUP3,
|
||||
PPI_GROUP4,
|
||||
PPI_GROUP5,
|
||||
|
||||
// GPIO port 0
|
||||
P0_00,
|
||||
P0_01,
|
||||
P0_02,
|
||||
P0_03,
|
||||
P0_04,
|
||||
P0_05,
|
||||
P0_06,
|
||||
P0_07,
|
||||
P0_08,
|
||||
P0_09,
|
||||
P0_10,
|
||||
P0_11,
|
||||
P0_12,
|
||||
P0_13,
|
||||
P0_14,
|
||||
P0_15,
|
||||
P0_16,
|
||||
P0_17,
|
||||
P0_18,
|
||||
P0_19,
|
||||
P0_20,
|
||||
#[cfg(feature="reset-pin-as-gpio")]
|
||||
P0_21,
|
||||
P0_22,
|
||||
P0_23,
|
||||
P0_24,
|
||||
P0_25,
|
||||
P0_26,
|
||||
P0_27,
|
||||
P0_28,
|
||||
P0_29,
|
||||
P0_30,
|
||||
P0_31,
|
||||
|
||||
// TEMP
|
||||
TEMP,
|
||||
|
||||
// QDEC
|
||||
QDEC,
|
||||
|
||||
// PDM
|
||||
PDM,
|
||||
|
||||
// Radio
|
||||
RADIO,
|
||||
|
||||
// EGU
|
||||
EGU0,
|
||||
EGU1,
|
||||
}
|
||||
|
||||
impl_uarte!(UARTE0, UARTE0, UARTE0_UART0);
|
||||
|
||||
impl_spim!(SPI0, SPIM0, SPIM0_SPIS0_SPI0);
|
||||
|
||||
impl_spis!(SPI0, SPIS0, SPIM0_SPIS0_SPI0);
|
||||
|
||||
impl_twim!(TWI0, TWIM0, TWIM0_TWIS0_TWI0);
|
||||
|
||||
impl_twis!(TWI0, TWIS0, TWIM0_TWIS0_TWI0);
|
||||
|
||||
impl_pwm!(PWM0, PWM0, PWM0);
|
||||
|
||||
impl_pdm!(PDM, PDM, PDM);
|
||||
|
||||
impl_qdec!(QDEC, QDEC, QDEC);
|
||||
|
||||
impl_rng!(RNG, RNG, RNG);
|
||||
|
||||
impl_timer!(TIMER0, TIMER0, TIMER0);
|
||||
impl_timer!(TIMER1, TIMER1, TIMER1);
|
||||
impl_timer!(TIMER2, TIMER2, TIMER2);
|
||||
|
||||
impl_pin!(P0_00, 0, 0);
|
||||
impl_pin!(P0_01, 0, 1);
|
||||
impl_pin!(P0_02, 0, 2);
|
||||
impl_pin!(P0_03, 0, 3);
|
||||
impl_pin!(P0_04, 0, 4);
|
||||
impl_pin!(P0_05, 0, 5);
|
||||
impl_pin!(P0_06, 0, 6);
|
||||
impl_pin!(P0_07, 0, 7);
|
||||
impl_pin!(P0_08, 0, 8);
|
||||
impl_pin!(P0_09, 0, 9);
|
||||
impl_pin!(P0_10, 0, 10);
|
||||
impl_pin!(P0_11, 0, 11);
|
||||
impl_pin!(P0_12, 0, 12);
|
||||
impl_pin!(P0_13, 0, 13);
|
||||
impl_pin!(P0_14, 0, 14);
|
||||
impl_pin!(P0_15, 0, 15);
|
||||
impl_pin!(P0_16, 0, 16);
|
||||
impl_pin!(P0_17, 0, 17);
|
||||
impl_pin!(P0_18, 0, 18);
|
||||
impl_pin!(P0_19, 0, 19);
|
||||
impl_pin!(P0_20, 0, 20);
|
||||
#[cfg(feature = "reset-pin-as-gpio")]
|
||||
impl_pin!(P0_21, 0, 21);
|
||||
impl_pin!(P0_22, 0, 22);
|
||||
impl_pin!(P0_23, 0, 23);
|
||||
impl_pin!(P0_24, 0, 24);
|
||||
impl_pin!(P0_25, 0, 25);
|
||||
impl_pin!(P0_26, 0, 26);
|
||||
impl_pin!(P0_27, 0, 27);
|
||||
impl_pin!(P0_28, 0, 28);
|
||||
impl_pin!(P0_29, 0, 29);
|
||||
impl_pin!(P0_30, 0, 30);
|
||||
impl_pin!(P0_31, 0, 31);
|
||||
|
||||
impl_ppi_channel!(PPI_CH0, 0 => configurable);
|
||||
impl_ppi_channel!(PPI_CH1, 1 => configurable);
|
||||
impl_ppi_channel!(PPI_CH2, 2 => configurable);
|
||||
impl_ppi_channel!(PPI_CH3, 3 => configurable);
|
||||
impl_ppi_channel!(PPI_CH4, 4 => configurable);
|
||||
impl_ppi_channel!(PPI_CH5, 5 => configurable);
|
||||
impl_ppi_channel!(PPI_CH6, 6 => configurable);
|
||||
impl_ppi_channel!(PPI_CH7, 7 => configurable);
|
||||
impl_ppi_channel!(PPI_CH8, 8 => configurable);
|
||||
impl_ppi_channel!(PPI_CH9, 9 => configurable);
|
||||
impl_ppi_channel!(PPI_CH10, 10 => configurable);
|
||||
impl_ppi_channel!(PPI_CH11, 11 => configurable);
|
||||
impl_ppi_channel!(PPI_CH12, 12 => configurable);
|
||||
impl_ppi_channel!(PPI_CH13, 13 => configurable);
|
||||
impl_ppi_channel!(PPI_CH14, 14 => configurable);
|
||||
impl_ppi_channel!(PPI_CH15, 15 => configurable);
|
||||
impl_ppi_channel!(PPI_CH16, 16 => configurable);
|
||||
impl_ppi_channel!(PPI_CH17, 17 => configurable);
|
||||
impl_ppi_channel!(PPI_CH18, 18 => configurable);
|
||||
impl_ppi_channel!(PPI_CH19, 19 => configurable);
|
||||
impl_ppi_channel!(PPI_CH20, 20 => static);
|
||||
impl_ppi_channel!(PPI_CH21, 21 => static);
|
||||
impl_ppi_channel!(PPI_CH22, 22 => static);
|
||||
impl_ppi_channel!(PPI_CH23, 23 => static);
|
||||
impl_ppi_channel!(PPI_CH24, 24 => static);
|
||||
impl_ppi_channel!(PPI_CH25, 25 => static);
|
||||
impl_ppi_channel!(PPI_CH26, 26 => static);
|
||||
impl_ppi_channel!(PPI_CH27, 27 => static);
|
||||
impl_ppi_channel!(PPI_CH28, 28 => static);
|
||||
impl_ppi_channel!(PPI_CH29, 29 => static);
|
||||
impl_ppi_channel!(PPI_CH30, 30 => static);
|
||||
impl_ppi_channel!(PPI_CH31, 31 => static);
|
||||
|
||||
impl_saadc_input!(P0_02, ANALOG_INPUT0);
|
||||
impl_saadc_input!(P0_03, ANALOG_INPUT1);
|
||||
impl_saadc_input!(P0_04, ANALOG_INPUT2);
|
||||
impl_saadc_input!(P0_05, ANALOG_INPUT3);
|
||||
impl_saadc_input!(P0_28, ANALOG_INPUT4);
|
||||
impl_saadc_input!(P0_29, ANALOG_INPUT5);
|
||||
impl_saadc_input!(P0_30, ANALOG_INPUT6);
|
||||
impl_saadc_input!(P0_31, ANALOG_INPUT7);
|
||||
|
||||
impl_radio!(RADIO, RADIO, RADIO);
|
||||
|
||||
impl_egu!(EGU0, EGU0, SWI0_EGU0);
|
||||
impl_egu!(EGU1, EGU1, SWI1_EGU1);
|
||||
|
||||
embassy_hal_internal::interrupt_mod!(
|
||||
POWER_CLOCK,
|
||||
RADIO,
|
||||
UARTE0_UART0,
|
||||
TWIM0_TWIS0_TWI0,
|
||||
SPIM0_SPIS0_SPI0,
|
||||
GPIOTE,
|
||||
SAADC,
|
||||
TIMER0,
|
||||
TIMER1,
|
||||
TIMER2,
|
||||
RTC0,
|
||||
TEMP,
|
||||
RNG,
|
||||
ECB,
|
||||
CCM_AAR,
|
||||
WDT,
|
||||
RTC1,
|
||||
QDEC,
|
||||
COMP,
|
||||
SWI0_EGU0,
|
||||
SWI1_EGU1,
|
||||
SWI2,
|
||||
SWI3,
|
||||
SWI4,
|
||||
SWI5,
|
||||
PWM0,
|
||||
PDM,
|
||||
);
|
||||
+280
@@ -0,0 +1,280 @@
|
||||
pub use nrf52811_pac as pac;
|
||||
|
||||
/// The maximum buffer size that the EasyDMA can send/recv in one operation.
|
||||
pub const EASY_DMA_SIZE: usize = (1 << 14) - 1;
|
||||
pub const FORCE_COPY_BUFFER_SIZE: usize = 256;
|
||||
|
||||
pub const FLASH_SIZE: usize = 192 * 1024;
|
||||
|
||||
pub const RESET_PIN: u32 = 21;
|
||||
pub const APPROTECT_MIN_BUILD_CODE: u8 = b'B';
|
||||
|
||||
embassy_hal_internal::peripherals! {
|
||||
// RTC
|
||||
RTC0,
|
||||
RTC1,
|
||||
|
||||
// WDT
|
||||
WDT,
|
||||
|
||||
// NVMC
|
||||
NVMC,
|
||||
|
||||
// RNG
|
||||
RNG,
|
||||
|
||||
// UARTE
|
||||
UARTE0,
|
||||
|
||||
// SPI/TWI
|
||||
TWISPI0,
|
||||
SPI1,
|
||||
|
||||
// SAADC
|
||||
SAADC,
|
||||
|
||||
// PWM
|
||||
PWM0,
|
||||
|
||||
// TIMER
|
||||
TIMER0,
|
||||
TIMER1,
|
||||
TIMER2,
|
||||
|
||||
// GPIOTE
|
||||
GPIOTE_CH0,
|
||||
GPIOTE_CH1,
|
||||
GPIOTE_CH2,
|
||||
GPIOTE_CH3,
|
||||
GPIOTE_CH4,
|
||||
GPIOTE_CH5,
|
||||
GPIOTE_CH6,
|
||||
GPIOTE_CH7,
|
||||
|
||||
// PPI
|
||||
PPI_CH0,
|
||||
PPI_CH1,
|
||||
PPI_CH2,
|
||||
PPI_CH3,
|
||||
PPI_CH4,
|
||||
PPI_CH5,
|
||||
PPI_CH6,
|
||||
PPI_CH7,
|
||||
PPI_CH8,
|
||||
PPI_CH9,
|
||||
PPI_CH10,
|
||||
PPI_CH11,
|
||||
PPI_CH12,
|
||||
PPI_CH13,
|
||||
PPI_CH14,
|
||||
PPI_CH15,
|
||||
PPI_CH16,
|
||||
PPI_CH17,
|
||||
PPI_CH18,
|
||||
PPI_CH19,
|
||||
PPI_CH20,
|
||||
PPI_CH21,
|
||||
PPI_CH22,
|
||||
PPI_CH23,
|
||||
PPI_CH24,
|
||||
PPI_CH25,
|
||||
PPI_CH26,
|
||||
PPI_CH27,
|
||||
PPI_CH28,
|
||||
PPI_CH29,
|
||||
PPI_CH30,
|
||||
PPI_CH31,
|
||||
|
||||
PPI_GROUP0,
|
||||
PPI_GROUP1,
|
||||
PPI_GROUP2,
|
||||
PPI_GROUP3,
|
||||
PPI_GROUP4,
|
||||
PPI_GROUP5,
|
||||
|
||||
// GPIO port 0
|
||||
P0_00,
|
||||
P0_01,
|
||||
P0_02,
|
||||
P0_03,
|
||||
P0_04,
|
||||
P0_05,
|
||||
P0_06,
|
||||
P0_07,
|
||||
P0_08,
|
||||
P0_09,
|
||||
P0_10,
|
||||
P0_11,
|
||||
P0_12,
|
||||
P0_13,
|
||||
P0_14,
|
||||
P0_15,
|
||||
P0_16,
|
||||
P0_17,
|
||||
P0_18,
|
||||
P0_19,
|
||||
P0_20,
|
||||
#[cfg(feature="reset-pin-as-gpio")]
|
||||
P0_21,
|
||||
P0_22,
|
||||
P0_23,
|
||||
P0_24,
|
||||
P0_25,
|
||||
P0_26,
|
||||
P0_27,
|
||||
P0_28,
|
||||
P0_29,
|
||||
P0_30,
|
||||
P0_31,
|
||||
|
||||
// TEMP
|
||||
TEMP,
|
||||
|
||||
// QDEC
|
||||
QDEC,
|
||||
|
||||
// PDM
|
||||
PDM,
|
||||
|
||||
// Radio
|
||||
RADIO,
|
||||
|
||||
// EGU
|
||||
EGU0,
|
||||
EGU1,
|
||||
}
|
||||
|
||||
impl_uarte!(UARTE0, UARTE0, UARTE0_UART0);
|
||||
|
||||
impl_spim!(TWISPI0, SPIM0, TWIM0_TWIS0_TWI0_SPIM0_SPIS0_SPI0);
|
||||
impl_spim!(SPI1, SPIM1, SPIM1_SPIS1_SPI1);
|
||||
|
||||
impl_spis!(TWISPI0, SPIS0, TWIM0_TWIS0_TWI0_SPIM0_SPIS0_SPI0);
|
||||
impl_spis!(SPI1, SPIS1, SPIM1_SPIS1_SPI1);
|
||||
|
||||
impl_twim!(TWISPI0, TWIM0, TWIM0_TWIS0_TWI0_SPIM0_SPIS0_SPI0);
|
||||
|
||||
impl_twis!(TWISPI0, TWIS0, TWIM0_TWIS0_TWI0_SPIM0_SPIS0_SPI0);
|
||||
|
||||
impl_pwm!(PWM0, PWM0, PWM0);
|
||||
|
||||
impl_pdm!(PDM, PDM, PDM);
|
||||
|
||||
impl_qdec!(QDEC, QDEC, QDEC);
|
||||
|
||||
impl_rng!(RNG, RNG, RNG);
|
||||
|
||||
impl_timer!(TIMER0, TIMER0, TIMER0);
|
||||
impl_timer!(TIMER1, TIMER1, TIMER1);
|
||||
impl_timer!(TIMER2, TIMER2, TIMER2);
|
||||
|
||||
impl_pin!(P0_00, 0, 0);
|
||||
impl_pin!(P0_01, 0, 1);
|
||||
impl_pin!(P0_02, 0, 2);
|
||||
impl_pin!(P0_03, 0, 3);
|
||||
impl_pin!(P0_04, 0, 4);
|
||||
impl_pin!(P0_05, 0, 5);
|
||||
impl_pin!(P0_06, 0, 6);
|
||||
impl_pin!(P0_07, 0, 7);
|
||||
impl_pin!(P0_08, 0, 8);
|
||||
impl_pin!(P0_09, 0, 9);
|
||||
impl_pin!(P0_10, 0, 10);
|
||||
impl_pin!(P0_11, 0, 11);
|
||||
impl_pin!(P0_12, 0, 12);
|
||||
impl_pin!(P0_13, 0, 13);
|
||||
impl_pin!(P0_14, 0, 14);
|
||||
impl_pin!(P0_15, 0, 15);
|
||||
impl_pin!(P0_16, 0, 16);
|
||||
impl_pin!(P0_17, 0, 17);
|
||||
impl_pin!(P0_18, 0, 18);
|
||||
impl_pin!(P0_19, 0, 19);
|
||||
impl_pin!(P0_20, 0, 20);
|
||||
#[cfg(feature = "reset-pin-as-gpio")]
|
||||
impl_pin!(P0_21, 0, 21);
|
||||
impl_pin!(P0_22, 0, 22);
|
||||
impl_pin!(P0_23, 0, 23);
|
||||
impl_pin!(P0_24, 0, 24);
|
||||
impl_pin!(P0_25, 0, 25);
|
||||
impl_pin!(P0_26, 0, 26);
|
||||
impl_pin!(P0_27, 0, 27);
|
||||
impl_pin!(P0_28, 0, 28);
|
||||
impl_pin!(P0_29, 0, 29);
|
||||
impl_pin!(P0_30, 0, 30);
|
||||
impl_pin!(P0_31, 0, 31);
|
||||
|
||||
impl_ppi_channel!(PPI_CH0, 0 => configurable);
|
||||
impl_ppi_channel!(PPI_CH1, 1 => configurable);
|
||||
impl_ppi_channel!(PPI_CH2, 2 => configurable);
|
||||
impl_ppi_channel!(PPI_CH3, 3 => configurable);
|
||||
impl_ppi_channel!(PPI_CH4, 4 => configurable);
|
||||
impl_ppi_channel!(PPI_CH5, 5 => configurable);
|
||||
impl_ppi_channel!(PPI_CH6, 6 => configurable);
|
||||
impl_ppi_channel!(PPI_CH7, 7 => configurable);
|
||||
impl_ppi_channel!(PPI_CH8, 8 => configurable);
|
||||
impl_ppi_channel!(PPI_CH9, 9 => configurable);
|
||||
impl_ppi_channel!(PPI_CH10, 10 => configurable);
|
||||
impl_ppi_channel!(PPI_CH11, 11 => configurable);
|
||||
impl_ppi_channel!(PPI_CH12, 12 => configurable);
|
||||
impl_ppi_channel!(PPI_CH13, 13 => configurable);
|
||||
impl_ppi_channel!(PPI_CH14, 14 => configurable);
|
||||
impl_ppi_channel!(PPI_CH15, 15 => configurable);
|
||||
impl_ppi_channel!(PPI_CH16, 16 => configurable);
|
||||
impl_ppi_channel!(PPI_CH17, 17 => configurable);
|
||||
impl_ppi_channel!(PPI_CH18, 18 => configurable);
|
||||
impl_ppi_channel!(PPI_CH19, 19 => configurable);
|
||||
impl_ppi_channel!(PPI_CH20, 20 => static);
|
||||
impl_ppi_channel!(PPI_CH21, 21 => static);
|
||||
impl_ppi_channel!(PPI_CH22, 22 => static);
|
||||
impl_ppi_channel!(PPI_CH23, 23 => static);
|
||||
impl_ppi_channel!(PPI_CH24, 24 => static);
|
||||
impl_ppi_channel!(PPI_CH25, 25 => static);
|
||||
impl_ppi_channel!(PPI_CH26, 26 => static);
|
||||
impl_ppi_channel!(PPI_CH27, 27 => static);
|
||||
impl_ppi_channel!(PPI_CH28, 28 => static);
|
||||
impl_ppi_channel!(PPI_CH29, 29 => static);
|
||||
impl_ppi_channel!(PPI_CH30, 30 => static);
|
||||
impl_ppi_channel!(PPI_CH31, 31 => static);
|
||||
|
||||
impl_saadc_input!(P0_02, ANALOG_INPUT0);
|
||||
impl_saadc_input!(P0_03, ANALOG_INPUT1);
|
||||
impl_saadc_input!(P0_04, ANALOG_INPUT2);
|
||||
impl_saadc_input!(P0_05, ANALOG_INPUT3);
|
||||
impl_saadc_input!(P0_28, ANALOG_INPUT4);
|
||||
impl_saadc_input!(P0_29, ANALOG_INPUT5);
|
||||
impl_saadc_input!(P0_30, ANALOG_INPUT6);
|
||||
impl_saadc_input!(P0_31, ANALOG_INPUT7);
|
||||
|
||||
impl_radio!(RADIO, RADIO, RADIO);
|
||||
|
||||
impl_egu!(EGU0, EGU0, SWI0_EGU0);
|
||||
impl_egu!(EGU1, EGU1, SWI1_EGU1);
|
||||
|
||||
embassy_hal_internal::interrupt_mod!(
|
||||
POWER_CLOCK,
|
||||
RADIO,
|
||||
UARTE0_UART0,
|
||||
TWIM0_TWIS0_TWI0_SPIM0_SPIS0_SPI0,
|
||||
SPIM1_SPIS1_SPI1,
|
||||
GPIOTE,
|
||||
SAADC,
|
||||
TIMER0,
|
||||
TIMER1,
|
||||
TIMER2,
|
||||
RTC0,
|
||||
TEMP,
|
||||
RNG,
|
||||
ECB,
|
||||
CCM_AAR,
|
||||
WDT,
|
||||
RTC1,
|
||||
QDEC,
|
||||
COMP,
|
||||
SWI0_EGU0,
|
||||
SWI1_EGU1,
|
||||
SWI2,
|
||||
SWI3,
|
||||
SWI4,
|
||||
SWI5,
|
||||
PWM0,
|
||||
PDM,
|
||||
);
|
||||
+274
@@ -0,0 +1,274 @@
|
||||
pub use nrf52820_pac as pac;
|
||||
|
||||
/// The maximum buffer size that the EasyDMA can send/recv in one operation.
|
||||
pub const EASY_DMA_SIZE: usize = (1 << 15) - 1;
|
||||
pub const FORCE_COPY_BUFFER_SIZE: usize = 512;
|
||||
|
||||
pub const FLASH_SIZE: usize = 256 * 1024;
|
||||
|
||||
pub const RESET_PIN: u32 = 18;
|
||||
pub const APPROTECT_MIN_BUILD_CODE: u8 = b'D';
|
||||
|
||||
embassy_hal_internal::peripherals! {
|
||||
// USB
|
||||
USBD,
|
||||
|
||||
// RTC
|
||||
RTC0,
|
||||
RTC1,
|
||||
|
||||
// WDT
|
||||
WDT,
|
||||
|
||||
// NVMC
|
||||
NVMC,
|
||||
|
||||
// RNG
|
||||
RNG,
|
||||
|
||||
// UARTE
|
||||
UARTE0,
|
||||
|
||||
// SPI/TWI
|
||||
TWISPI0,
|
||||
TWISPI1,
|
||||
|
||||
// TIMER
|
||||
TIMER0,
|
||||
TIMER1,
|
||||
TIMER2,
|
||||
TIMER3,
|
||||
|
||||
// GPIOTE
|
||||
GPIOTE_CH0,
|
||||
GPIOTE_CH1,
|
||||
GPIOTE_CH2,
|
||||
GPIOTE_CH3,
|
||||
GPIOTE_CH4,
|
||||
GPIOTE_CH5,
|
||||
GPIOTE_CH6,
|
||||
GPIOTE_CH7,
|
||||
|
||||
// PPI
|
||||
PPI_CH0,
|
||||
PPI_CH1,
|
||||
PPI_CH2,
|
||||
PPI_CH3,
|
||||
PPI_CH4,
|
||||
PPI_CH5,
|
||||
PPI_CH6,
|
||||
PPI_CH7,
|
||||
PPI_CH8,
|
||||
PPI_CH9,
|
||||
PPI_CH10,
|
||||
PPI_CH11,
|
||||
PPI_CH12,
|
||||
PPI_CH13,
|
||||
PPI_CH14,
|
||||
PPI_CH15,
|
||||
PPI_CH16,
|
||||
PPI_CH17,
|
||||
PPI_CH18,
|
||||
PPI_CH19,
|
||||
PPI_CH20,
|
||||
PPI_CH21,
|
||||
PPI_CH22,
|
||||
PPI_CH23,
|
||||
PPI_CH24,
|
||||
PPI_CH25,
|
||||
PPI_CH26,
|
||||
PPI_CH27,
|
||||
PPI_CH28,
|
||||
PPI_CH29,
|
||||
PPI_CH30,
|
||||
PPI_CH31,
|
||||
|
||||
PPI_GROUP0,
|
||||
PPI_GROUP1,
|
||||
PPI_GROUP2,
|
||||
PPI_GROUP3,
|
||||
PPI_GROUP4,
|
||||
PPI_GROUP5,
|
||||
|
||||
// GPIO port 0
|
||||
P0_00,
|
||||
P0_01,
|
||||
P0_02,
|
||||
P0_03,
|
||||
P0_04,
|
||||
P0_05,
|
||||
P0_06,
|
||||
P0_07,
|
||||
P0_08,
|
||||
P0_09,
|
||||
P0_10,
|
||||
P0_11,
|
||||
P0_12,
|
||||
P0_13,
|
||||
P0_14,
|
||||
P0_15,
|
||||
P0_16,
|
||||
P0_17,
|
||||
#[cfg(feature="reset-pin-as-gpio")]
|
||||
P0_18,
|
||||
P0_19,
|
||||
P0_20,
|
||||
P0_21,
|
||||
P0_22,
|
||||
P0_23,
|
||||
P0_24,
|
||||
P0_25,
|
||||
P0_26,
|
||||
P0_27,
|
||||
P0_28,
|
||||
P0_29,
|
||||
P0_30,
|
||||
P0_31,
|
||||
|
||||
// TEMP
|
||||
TEMP,
|
||||
|
||||
// QDEC
|
||||
QDEC,
|
||||
|
||||
// Radio
|
||||
RADIO,
|
||||
|
||||
// EGU
|
||||
EGU0,
|
||||
EGU1,
|
||||
EGU2,
|
||||
EGU3,
|
||||
EGU4,
|
||||
EGU5,
|
||||
}
|
||||
|
||||
impl_usb!(USBD, USBD, USBD);
|
||||
|
||||
impl_uarte!(UARTE0, UARTE0, UARTE0_UART0);
|
||||
|
||||
impl_spim!(TWISPI0, SPIM0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
|
||||
impl_spim!(TWISPI1, SPIM1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
|
||||
|
||||
impl_spis!(TWISPI0, SPIS0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
|
||||
impl_spis!(TWISPI1, SPIS1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
|
||||
|
||||
impl_twim!(TWISPI0, TWIM0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
|
||||
impl_twim!(TWISPI1, TWIM1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
|
||||
|
||||
impl_twis!(TWISPI0, TWIS0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
|
||||
impl_twis!(TWISPI1, TWIS1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
|
||||
|
||||
impl_timer!(TIMER0, TIMER0, TIMER0);
|
||||
impl_timer!(TIMER1, TIMER1, TIMER1);
|
||||
impl_timer!(TIMER2, TIMER2, TIMER2);
|
||||
impl_timer!(TIMER3, TIMER3, TIMER3, extended);
|
||||
|
||||
impl_qdec!(QDEC, QDEC, QDEC);
|
||||
|
||||
impl_rng!(RNG, RNG, RNG);
|
||||
|
||||
impl_pin!(P0_00, 0, 0);
|
||||
impl_pin!(P0_01, 0, 1);
|
||||
impl_pin!(P0_02, 0, 2);
|
||||
impl_pin!(P0_03, 0, 3);
|
||||
impl_pin!(P0_04, 0, 4);
|
||||
impl_pin!(P0_05, 0, 5);
|
||||
impl_pin!(P0_06, 0, 6);
|
||||
impl_pin!(P0_07, 0, 7);
|
||||
impl_pin!(P0_08, 0, 8);
|
||||
impl_pin!(P0_09, 0, 9);
|
||||
impl_pin!(P0_10, 0, 10);
|
||||
impl_pin!(P0_11, 0, 11);
|
||||
impl_pin!(P0_12, 0, 12);
|
||||
impl_pin!(P0_13, 0, 13);
|
||||
impl_pin!(P0_14, 0, 14);
|
||||
impl_pin!(P0_15, 0, 15);
|
||||
impl_pin!(P0_16, 0, 16);
|
||||
impl_pin!(P0_17, 0, 17);
|
||||
#[cfg(feature = "reset-pin-as-gpio")]
|
||||
impl_pin!(P0_18, 0, 18);
|
||||
impl_pin!(P0_19, 0, 19);
|
||||
impl_pin!(P0_20, 0, 20);
|
||||
impl_pin!(P0_21, 0, 21);
|
||||
impl_pin!(P0_22, 0, 22);
|
||||
impl_pin!(P0_23, 0, 23);
|
||||
impl_pin!(P0_24, 0, 24);
|
||||
impl_pin!(P0_25, 0, 25);
|
||||
impl_pin!(P0_26, 0, 26);
|
||||
impl_pin!(P0_27, 0, 27);
|
||||
impl_pin!(P0_28, 0, 28);
|
||||
impl_pin!(P0_29, 0, 29);
|
||||
impl_pin!(P0_30, 0, 30);
|
||||
impl_pin!(P0_31, 0, 31);
|
||||
|
||||
impl_ppi_channel!(PPI_CH0, 0 => configurable);
|
||||
impl_ppi_channel!(PPI_CH1, 1 => configurable);
|
||||
impl_ppi_channel!(PPI_CH2, 2 => configurable);
|
||||
impl_ppi_channel!(PPI_CH3, 3 => configurable);
|
||||
impl_ppi_channel!(PPI_CH4, 4 => configurable);
|
||||
impl_ppi_channel!(PPI_CH5, 5 => configurable);
|
||||
impl_ppi_channel!(PPI_CH6, 6 => configurable);
|
||||
impl_ppi_channel!(PPI_CH7, 7 => configurable);
|
||||
impl_ppi_channel!(PPI_CH8, 8 => configurable);
|
||||
impl_ppi_channel!(PPI_CH9, 9 => configurable);
|
||||
impl_ppi_channel!(PPI_CH10, 10 => configurable);
|
||||
impl_ppi_channel!(PPI_CH11, 11 => configurable);
|
||||
impl_ppi_channel!(PPI_CH12, 12 => configurable);
|
||||
impl_ppi_channel!(PPI_CH13, 13 => configurable);
|
||||
impl_ppi_channel!(PPI_CH14, 14 => configurable);
|
||||
impl_ppi_channel!(PPI_CH15, 15 => configurable);
|
||||
impl_ppi_channel!(PPI_CH16, 16 => configurable);
|
||||
impl_ppi_channel!(PPI_CH17, 17 => configurable);
|
||||
impl_ppi_channel!(PPI_CH18, 18 => configurable);
|
||||
impl_ppi_channel!(PPI_CH19, 19 => configurable);
|
||||
impl_ppi_channel!(PPI_CH20, 20 => static);
|
||||
impl_ppi_channel!(PPI_CH21, 21 => static);
|
||||
impl_ppi_channel!(PPI_CH22, 22 => static);
|
||||
impl_ppi_channel!(PPI_CH23, 23 => static);
|
||||
impl_ppi_channel!(PPI_CH24, 24 => static);
|
||||
impl_ppi_channel!(PPI_CH25, 25 => static);
|
||||
impl_ppi_channel!(PPI_CH26, 26 => static);
|
||||
impl_ppi_channel!(PPI_CH27, 27 => static);
|
||||
impl_ppi_channel!(PPI_CH28, 28 => static);
|
||||
impl_ppi_channel!(PPI_CH29, 29 => static);
|
||||
impl_ppi_channel!(PPI_CH30, 30 => static);
|
||||
impl_ppi_channel!(PPI_CH31, 31 => static);
|
||||
|
||||
impl_radio!(RADIO, RADIO, RADIO);
|
||||
|
||||
impl_egu!(EGU0, EGU0, SWI0_EGU0);
|
||||
impl_egu!(EGU1, EGU1, SWI1_EGU1);
|
||||
impl_egu!(EGU2, EGU2, SWI2_EGU2);
|
||||
impl_egu!(EGU3, EGU3, SWI3_EGU3);
|
||||
impl_egu!(EGU4, EGU4, SWI4_EGU4);
|
||||
impl_egu!(EGU5, EGU5, SWI5_EGU5);
|
||||
|
||||
embassy_hal_internal::interrupt_mod!(
|
||||
POWER_CLOCK,
|
||||
RADIO,
|
||||
UARTE0_UART0,
|
||||
SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0,
|
||||
SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1,
|
||||
GPIOTE,
|
||||
TIMER0,
|
||||
TIMER1,
|
||||
TIMER2,
|
||||
RTC0,
|
||||
TEMP,
|
||||
RNG,
|
||||
ECB,
|
||||
CCM_AAR,
|
||||
WDT,
|
||||
RTC1,
|
||||
QDEC,
|
||||
COMP,
|
||||
SWI0_EGU0,
|
||||
SWI1_EGU1,
|
||||
SWI2_EGU2,
|
||||
SWI3_EGU3,
|
||||
SWI4_EGU4,
|
||||
SWI5_EGU5,
|
||||
TIMER3,
|
||||
USBD,
|
||||
);
|
||||
+325
@@ -0,0 +1,325 @@
|
||||
pub use nrf52832_pac as pac;
|
||||
|
||||
/// The maximum buffer size that the EasyDMA can send/recv in one operation.
|
||||
pub const EASY_DMA_SIZE: usize = (1 << 8) - 1;
|
||||
pub const FORCE_COPY_BUFFER_SIZE: usize = 255;
|
||||
|
||||
// There are two variants. We set the higher size to make the entire flash
|
||||
// usable in xxAA, but we'll probably split this in two cargi features later.
|
||||
// nrf52832xxAA = 512kb
|
||||
// nrf52832xxAB = 256kb
|
||||
pub const FLASH_SIZE: usize = 512 * 1024;
|
||||
|
||||
pub const RESET_PIN: u32 = 21;
|
||||
pub const APPROTECT_MIN_BUILD_CODE: u8 = b'G';
|
||||
|
||||
embassy_hal_internal::peripherals! {
|
||||
// RTC
|
||||
RTC0,
|
||||
RTC1,
|
||||
RTC2,
|
||||
|
||||
// WDT
|
||||
WDT,
|
||||
|
||||
// NVMC
|
||||
NVMC,
|
||||
|
||||
// RNG
|
||||
RNG,
|
||||
|
||||
// UARTE
|
||||
UARTE0,
|
||||
|
||||
// SPI/TWI
|
||||
TWISPI0,
|
||||
TWISPI1,
|
||||
SPI2,
|
||||
|
||||
// SAADC
|
||||
SAADC,
|
||||
|
||||
// PWM
|
||||
PWM0,
|
||||
PWM1,
|
||||
PWM2,
|
||||
|
||||
// TIMER
|
||||
TIMER0,
|
||||
TIMER1,
|
||||
TIMER2,
|
||||
TIMER3,
|
||||
TIMER4,
|
||||
|
||||
// GPIOTE
|
||||
GPIOTE_CH0,
|
||||
GPIOTE_CH1,
|
||||
GPIOTE_CH2,
|
||||
GPIOTE_CH3,
|
||||
GPIOTE_CH4,
|
||||
GPIOTE_CH5,
|
||||
GPIOTE_CH6,
|
||||
GPIOTE_CH7,
|
||||
|
||||
// PPI
|
||||
PPI_CH0,
|
||||
PPI_CH1,
|
||||
PPI_CH2,
|
||||
PPI_CH3,
|
||||
PPI_CH4,
|
||||
PPI_CH5,
|
||||
PPI_CH6,
|
||||
PPI_CH7,
|
||||
PPI_CH8,
|
||||
PPI_CH9,
|
||||
PPI_CH10,
|
||||
PPI_CH11,
|
||||
PPI_CH12,
|
||||
PPI_CH13,
|
||||
PPI_CH14,
|
||||
PPI_CH15,
|
||||
PPI_CH16,
|
||||
PPI_CH17,
|
||||
PPI_CH18,
|
||||
PPI_CH19,
|
||||
PPI_CH20,
|
||||
PPI_CH21,
|
||||
PPI_CH22,
|
||||
PPI_CH23,
|
||||
PPI_CH24,
|
||||
PPI_CH25,
|
||||
PPI_CH26,
|
||||
PPI_CH27,
|
||||
PPI_CH28,
|
||||
PPI_CH29,
|
||||
PPI_CH30,
|
||||
PPI_CH31,
|
||||
|
||||
PPI_GROUP0,
|
||||
PPI_GROUP1,
|
||||
PPI_GROUP2,
|
||||
PPI_GROUP3,
|
||||
PPI_GROUP4,
|
||||
PPI_GROUP5,
|
||||
|
||||
// GPIO port 0
|
||||
P0_00,
|
||||
P0_01,
|
||||
P0_02,
|
||||
P0_03,
|
||||
P0_04,
|
||||
P0_05,
|
||||
P0_06,
|
||||
P0_07,
|
||||
P0_08,
|
||||
#[cfg(feature = "nfc-pins-as-gpio")]
|
||||
P0_09,
|
||||
#[cfg(feature = "nfc-pins-as-gpio")]
|
||||
P0_10,
|
||||
P0_11,
|
||||
P0_12,
|
||||
P0_13,
|
||||
P0_14,
|
||||
P0_15,
|
||||
P0_16,
|
||||
P0_17,
|
||||
P0_18,
|
||||
P0_19,
|
||||
P0_20,
|
||||
#[cfg(feature="reset-pin-as-gpio")]
|
||||
P0_21,
|
||||
P0_22,
|
||||
P0_23,
|
||||
P0_24,
|
||||
P0_25,
|
||||
P0_26,
|
||||
P0_27,
|
||||
P0_28,
|
||||
P0_29,
|
||||
P0_30,
|
||||
P0_31,
|
||||
|
||||
// TEMP
|
||||
TEMP,
|
||||
|
||||
// QDEC
|
||||
QDEC,
|
||||
|
||||
// I2S
|
||||
I2S,
|
||||
|
||||
// PDM
|
||||
PDM,
|
||||
|
||||
// Radio
|
||||
RADIO,
|
||||
|
||||
// EGU
|
||||
EGU0,
|
||||
EGU1,
|
||||
EGU2,
|
||||
EGU3,
|
||||
EGU4,
|
||||
EGU5,
|
||||
}
|
||||
|
||||
impl_uarte!(UARTE0, UARTE0, UARTE0_UART0);
|
||||
|
||||
impl_spim!(TWISPI0, SPIM0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
|
||||
impl_spim!(TWISPI1, SPIM1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
|
||||
impl_spim!(SPI2, SPIM2, SPIM2_SPIS2_SPI2);
|
||||
|
||||
impl_spis!(TWISPI0, SPIS0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
|
||||
impl_spis!(TWISPI1, SPIS1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
|
||||
impl_spis!(SPI2, SPIS2, SPIM2_SPIS2_SPI2);
|
||||
|
||||
impl_twim!(TWISPI0, TWIM0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
|
||||
impl_twim!(TWISPI1, TWIM1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
|
||||
|
||||
impl_twis!(TWISPI0, TWIS0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
|
||||
impl_twis!(TWISPI1, TWIS1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
|
||||
|
||||
impl_pwm!(PWM0, PWM0, PWM0);
|
||||
impl_pwm!(PWM1, PWM1, PWM1);
|
||||
impl_pwm!(PWM2, PWM2, PWM2);
|
||||
|
||||
impl_pdm!(PDM, PDM, PDM);
|
||||
|
||||
impl_qdec!(QDEC, QDEC, QDEC);
|
||||
|
||||
impl_rng!(RNG, RNG, RNG);
|
||||
|
||||
impl_timer!(TIMER0, TIMER0, TIMER0);
|
||||
impl_timer!(TIMER1, TIMER1, TIMER1);
|
||||
impl_timer!(TIMER2, TIMER2, TIMER2);
|
||||
impl_timer!(TIMER3, TIMER3, TIMER3, extended);
|
||||
impl_timer!(TIMER4, TIMER4, TIMER4, extended);
|
||||
|
||||
impl_pin!(P0_00, 0, 0);
|
||||
impl_pin!(P0_01, 0, 1);
|
||||
impl_pin!(P0_02, 0, 2);
|
||||
impl_pin!(P0_03, 0, 3);
|
||||
impl_pin!(P0_04, 0, 4);
|
||||
impl_pin!(P0_05, 0, 5);
|
||||
impl_pin!(P0_06, 0, 6);
|
||||
impl_pin!(P0_07, 0, 7);
|
||||
impl_pin!(P0_08, 0, 8);
|
||||
#[cfg(feature = "nfc-pins-as-gpio")]
|
||||
impl_pin!(P0_09, 0, 9);
|
||||
#[cfg(feature = "nfc-pins-as-gpio")]
|
||||
impl_pin!(P0_10, 0, 10);
|
||||
impl_pin!(P0_11, 0, 11);
|
||||
impl_pin!(P0_12, 0, 12);
|
||||
impl_pin!(P0_13, 0, 13);
|
||||
impl_pin!(P0_14, 0, 14);
|
||||
impl_pin!(P0_15, 0, 15);
|
||||
impl_pin!(P0_16, 0, 16);
|
||||
impl_pin!(P0_17, 0, 17);
|
||||
impl_pin!(P0_18, 0, 18);
|
||||
impl_pin!(P0_19, 0, 19);
|
||||
impl_pin!(P0_20, 0, 20);
|
||||
#[cfg(feature = "reset-pin-as-gpio")]
|
||||
impl_pin!(P0_21, 0, 21);
|
||||
impl_pin!(P0_22, 0, 22);
|
||||
impl_pin!(P0_23, 0, 23);
|
||||
impl_pin!(P0_24, 0, 24);
|
||||
impl_pin!(P0_25, 0, 25);
|
||||
impl_pin!(P0_26, 0, 26);
|
||||
impl_pin!(P0_27, 0, 27);
|
||||
impl_pin!(P0_28, 0, 28);
|
||||
impl_pin!(P0_29, 0, 29);
|
||||
impl_pin!(P0_30, 0, 30);
|
||||
impl_pin!(P0_31, 0, 31);
|
||||
|
||||
impl_ppi_channel!(PPI_CH0, 0 => configurable);
|
||||
impl_ppi_channel!(PPI_CH1, 1 => configurable);
|
||||
impl_ppi_channel!(PPI_CH2, 2 => configurable);
|
||||
impl_ppi_channel!(PPI_CH3, 3 => configurable);
|
||||
impl_ppi_channel!(PPI_CH4, 4 => configurable);
|
||||
impl_ppi_channel!(PPI_CH5, 5 => configurable);
|
||||
impl_ppi_channel!(PPI_CH6, 6 => configurable);
|
||||
impl_ppi_channel!(PPI_CH7, 7 => configurable);
|
||||
impl_ppi_channel!(PPI_CH8, 8 => configurable);
|
||||
impl_ppi_channel!(PPI_CH9, 9 => configurable);
|
||||
impl_ppi_channel!(PPI_CH10, 10 => configurable);
|
||||
impl_ppi_channel!(PPI_CH11, 11 => configurable);
|
||||
impl_ppi_channel!(PPI_CH12, 12 => configurable);
|
||||
impl_ppi_channel!(PPI_CH13, 13 => configurable);
|
||||
impl_ppi_channel!(PPI_CH14, 14 => configurable);
|
||||
impl_ppi_channel!(PPI_CH15, 15 => configurable);
|
||||
impl_ppi_channel!(PPI_CH16, 16 => configurable);
|
||||
impl_ppi_channel!(PPI_CH17, 17 => configurable);
|
||||
impl_ppi_channel!(PPI_CH18, 18 => configurable);
|
||||
impl_ppi_channel!(PPI_CH19, 19 => configurable);
|
||||
impl_ppi_channel!(PPI_CH20, 20 => static);
|
||||
impl_ppi_channel!(PPI_CH21, 21 => static);
|
||||
impl_ppi_channel!(PPI_CH22, 22 => static);
|
||||
impl_ppi_channel!(PPI_CH23, 23 => static);
|
||||
impl_ppi_channel!(PPI_CH24, 24 => static);
|
||||
impl_ppi_channel!(PPI_CH25, 25 => static);
|
||||
impl_ppi_channel!(PPI_CH26, 26 => static);
|
||||
impl_ppi_channel!(PPI_CH27, 27 => static);
|
||||
impl_ppi_channel!(PPI_CH28, 28 => static);
|
||||
impl_ppi_channel!(PPI_CH29, 29 => static);
|
||||
impl_ppi_channel!(PPI_CH30, 30 => static);
|
||||
impl_ppi_channel!(PPI_CH31, 31 => static);
|
||||
|
||||
impl_saadc_input!(P0_02, ANALOG_INPUT0);
|
||||
impl_saadc_input!(P0_03, ANALOG_INPUT1);
|
||||
impl_saadc_input!(P0_04, ANALOG_INPUT2);
|
||||
impl_saadc_input!(P0_05, ANALOG_INPUT3);
|
||||
impl_saadc_input!(P0_28, ANALOG_INPUT4);
|
||||
impl_saadc_input!(P0_29, ANALOG_INPUT5);
|
||||
impl_saadc_input!(P0_30, ANALOG_INPUT6);
|
||||
impl_saadc_input!(P0_31, ANALOG_INPUT7);
|
||||
|
||||
impl_i2s!(I2S, I2S, I2S);
|
||||
|
||||
impl_radio!(RADIO, RADIO, RADIO);
|
||||
|
||||
impl_egu!(EGU0, EGU0, SWI0_EGU0);
|
||||
impl_egu!(EGU1, EGU1, SWI1_EGU1);
|
||||
impl_egu!(EGU2, EGU2, SWI2_EGU2);
|
||||
impl_egu!(EGU3, EGU3, SWI3_EGU3);
|
||||
impl_egu!(EGU4, EGU4, SWI4_EGU4);
|
||||
impl_egu!(EGU5, EGU5, SWI5_EGU5);
|
||||
|
||||
embassy_hal_internal::interrupt_mod!(
|
||||
POWER_CLOCK,
|
||||
RADIO,
|
||||
UARTE0_UART0,
|
||||
SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0,
|
||||
SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1,
|
||||
NFCT,
|
||||
GPIOTE,
|
||||
SAADC,
|
||||
TIMER0,
|
||||
TIMER1,
|
||||
TIMER2,
|
||||
RTC0,
|
||||
TEMP,
|
||||
RNG,
|
||||
ECB,
|
||||
CCM_AAR,
|
||||
WDT,
|
||||
RTC1,
|
||||
QDEC,
|
||||
COMP_LPCOMP,
|
||||
SWI0_EGU0,
|
||||
SWI1_EGU1,
|
||||
SWI2_EGU2,
|
||||
SWI3_EGU3,
|
||||
SWI4_EGU4,
|
||||
SWI5_EGU5,
|
||||
TIMER3,
|
||||
TIMER4,
|
||||
PWM0,
|
||||
PDM,
|
||||
MWU,
|
||||
PWM1,
|
||||
PWM2,
|
||||
SPIM2_SPIS2_SPI2,
|
||||
RTC2,
|
||||
FPU,
|
||||
I2S,
|
||||
);
|
||||
+371
@@ -0,0 +1,371 @@
|
||||
pub use nrf52833_pac as pac;
|
||||
|
||||
/// The maximum buffer size that the EasyDMA can send/recv in one operation.
|
||||
pub const EASY_DMA_SIZE: usize = (1 << 16) - 1;
|
||||
pub const FORCE_COPY_BUFFER_SIZE: usize = 512;
|
||||
|
||||
pub const FLASH_SIZE: usize = 512 * 1024;
|
||||
|
||||
pub const RESET_PIN: u32 = 18;
|
||||
pub const APPROTECT_MIN_BUILD_CODE: u8 = b'B';
|
||||
|
||||
embassy_hal_internal::peripherals! {
|
||||
// USB
|
||||
USBD,
|
||||
|
||||
// RTC
|
||||
RTC0,
|
||||
RTC1,
|
||||
RTC2,
|
||||
|
||||
// WDT
|
||||
WDT,
|
||||
|
||||
// NVMC
|
||||
NVMC,
|
||||
|
||||
// RNG
|
||||
RNG,
|
||||
|
||||
// UARTE
|
||||
UARTE0,
|
||||
UARTE1,
|
||||
|
||||
// SPI/TWI
|
||||
TWISPI0,
|
||||
TWISPI1,
|
||||
SPI2,
|
||||
SPI3,
|
||||
|
||||
// SAADC
|
||||
SAADC,
|
||||
|
||||
// PWM
|
||||
PWM0,
|
||||
PWM1,
|
||||
PWM2,
|
||||
PWM3,
|
||||
|
||||
// TIMER
|
||||
TIMER0,
|
||||
TIMER1,
|
||||
TIMER2,
|
||||
TIMER3,
|
||||
TIMER4,
|
||||
|
||||
// GPIOTE
|
||||
GPIOTE_CH0,
|
||||
GPIOTE_CH1,
|
||||
GPIOTE_CH2,
|
||||
GPIOTE_CH3,
|
||||
GPIOTE_CH4,
|
||||
GPIOTE_CH5,
|
||||
GPIOTE_CH6,
|
||||
GPIOTE_CH7,
|
||||
|
||||
// PPI
|
||||
PPI_CH0,
|
||||
PPI_CH1,
|
||||
PPI_CH2,
|
||||
PPI_CH3,
|
||||
PPI_CH4,
|
||||
PPI_CH5,
|
||||
PPI_CH6,
|
||||
PPI_CH7,
|
||||
PPI_CH8,
|
||||
PPI_CH9,
|
||||
PPI_CH10,
|
||||
PPI_CH11,
|
||||
PPI_CH12,
|
||||
PPI_CH13,
|
||||
PPI_CH14,
|
||||
PPI_CH15,
|
||||
PPI_CH16,
|
||||
PPI_CH17,
|
||||
PPI_CH18,
|
||||
PPI_CH19,
|
||||
PPI_CH20,
|
||||
PPI_CH21,
|
||||
PPI_CH22,
|
||||
PPI_CH23,
|
||||
PPI_CH24,
|
||||
PPI_CH25,
|
||||
PPI_CH26,
|
||||
PPI_CH27,
|
||||
PPI_CH28,
|
||||
PPI_CH29,
|
||||
PPI_CH30,
|
||||
PPI_CH31,
|
||||
|
||||
PPI_GROUP0,
|
||||
PPI_GROUP1,
|
||||
PPI_GROUP2,
|
||||
PPI_GROUP3,
|
||||
PPI_GROUP4,
|
||||
PPI_GROUP5,
|
||||
|
||||
// GPIO port 0
|
||||
P0_00,
|
||||
P0_01,
|
||||
P0_02,
|
||||
P0_03,
|
||||
P0_04,
|
||||
P0_05,
|
||||
P0_06,
|
||||
P0_07,
|
||||
P0_08,
|
||||
#[cfg(feature = "nfc-pins-as-gpio")]
|
||||
P0_09,
|
||||
#[cfg(feature = "nfc-pins-as-gpio")]
|
||||
P0_10,
|
||||
P0_11,
|
||||
P0_12,
|
||||
P0_13,
|
||||
P0_14,
|
||||
P0_15,
|
||||
P0_16,
|
||||
P0_17,
|
||||
#[cfg(feature="reset-pin-as-gpio")]
|
||||
P0_18,
|
||||
P0_19,
|
||||
P0_20,
|
||||
P0_21,
|
||||
P0_22,
|
||||
P0_23,
|
||||
P0_24,
|
||||
P0_25,
|
||||
P0_26,
|
||||
P0_27,
|
||||
P0_28,
|
||||
P0_29,
|
||||
P0_30,
|
||||
P0_31,
|
||||
|
||||
// GPIO port 1
|
||||
P1_00,
|
||||
P1_01,
|
||||
P1_02,
|
||||
P1_03,
|
||||
P1_04,
|
||||
P1_05,
|
||||
P1_06,
|
||||
P1_07,
|
||||
P1_08,
|
||||
P1_09,
|
||||
P1_10,
|
||||
P1_11,
|
||||
P1_12,
|
||||
P1_13,
|
||||
P1_14,
|
||||
P1_15,
|
||||
|
||||
// TEMP
|
||||
TEMP,
|
||||
|
||||
// QDEC
|
||||
QDEC,
|
||||
|
||||
// PDM
|
||||
PDM,
|
||||
|
||||
// I2S
|
||||
I2S,
|
||||
|
||||
// Radio
|
||||
RADIO,
|
||||
|
||||
// EGU
|
||||
EGU0,
|
||||
EGU1,
|
||||
EGU2,
|
||||
EGU3,
|
||||
EGU4,
|
||||
EGU5,
|
||||
}
|
||||
|
||||
impl_usb!(USBD, USBD, USBD);
|
||||
|
||||
impl_uarte!(UARTE0, UARTE0, UARTE0_UART0);
|
||||
impl_uarte!(UARTE1, UARTE1, UARTE1);
|
||||
|
||||
impl_spim!(TWISPI0, SPIM0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
|
||||
impl_spim!(TWISPI1, SPIM1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
|
||||
impl_spim!(SPI2, SPIM2, SPIM2_SPIS2_SPI2);
|
||||
impl_spim!(SPI3, SPIM3, SPIM3);
|
||||
|
||||
impl_spis!(TWISPI0, SPIS0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
|
||||
impl_spis!(TWISPI1, SPIS1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
|
||||
impl_spis!(SPI2, SPIS2, SPIM2_SPIS2_SPI2);
|
||||
|
||||
impl_twim!(TWISPI0, TWIM0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
|
||||
impl_twim!(TWISPI1, TWIM1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
|
||||
|
||||
impl_twis!(TWISPI0, TWIS0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
|
||||
impl_twis!(TWISPI1, TWIS1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
|
||||
|
||||
impl_pwm!(PWM0, PWM0, PWM0);
|
||||
impl_pwm!(PWM1, PWM1, PWM1);
|
||||
impl_pwm!(PWM2, PWM2, PWM2);
|
||||
impl_pwm!(PWM3, PWM3, PWM3);
|
||||
|
||||
impl_pdm!(PDM, PDM, PDM);
|
||||
|
||||
impl_qdec!(QDEC, QDEC, QDEC);
|
||||
|
||||
impl_rng!(RNG, RNG, RNG);
|
||||
|
||||
impl_timer!(TIMER0, TIMER0, TIMER0);
|
||||
impl_timer!(TIMER1, TIMER1, TIMER1);
|
||||
impl_timer!(TIMER2, TIMER2, TIMER2);
|
||||
impl_timer!(TIMER3, TIMER3, TIMER3, extended);
|
||||
impl_timer!(TIMER4, TIMER4, TIMER4, extended);
|
||||
|
||||
impl_pin!(P0_00, 0, 0);
|
||||
impl_pin!(P0_01, 0, 1);
|
||||
impl_pin!(P0_02, 0, 2);
|
||||
impl_pin!(P0_03, 0, 3);
|
||||
impl_pin!(P0_04, 0, 4);
|
||||
impl_pin!(P0_05, 0, 5);
|
||||
impl_pin!(P0_06, 0, 6);
|
||||
impl_pin!(P0_07, 0, 7);
|
||||
impl_pin!(P0_08, 0, 8);
|
||||
#[cfg(feature = "nfc-pins-as-gpio")]
|
||||
impl_pin!(P0_09, 0, 9);
|
||||
#[cfg(feature = "nfc-pins-as-gpio")]
|
||||
impl_pin!(P0_10, 0, 10);
|
||||
impl_pin!(P0_11, 0, 11);
|
||||
impl_pin!(P0_12, 0, 12);
|
||||
impl_pin!(P0_13, 0, 13);
|
||||
impl_pin!(P0_14, 0, 14);
|
||||
impl_pin!(P0_15, 0, 15);
|
||||
impl_pin!(P0_16, 0, 16);
|
||||
impl_pin!(P0_17, 0, 17);
|
||||
#[cfg(feature = "reset-pin-as-gpio")]
|
||||
impl_pin!(P0_18, 0, 18);
|
||||
impl_pin!(P0_19, 0, 19);
|
||||
impl_pin!(P0_20, 0, 20);
|
||||
impl_pin!(P0_21, 0, 21);
|
||||
impl_pin!(P0_22, 0, 22);
|
||||
impl_pin!(P0_23, 0, 23);
|
||||
impl_pin!(P0_24, 0, 24);
|
||||
impl_pin!(P0_25, 0, 25);
|
||||
impl_pin!(P0_26, 0, 26);
|
||||
impl_pin!(P0_27, 0, 27);
|
||||
impl_pin!(P0_28, 0, 28);
|
||||
impl_pin!(P0_29, 0, 29);
|
||||
impl_pin!(P0_30, 0, 30);
|
||||
impl_pin!(P0_31, 0, 31);
|
||||
|
||||
impl_pin!(P1_00, 1, 0);
|
||||
impl_pin!(P1_01, 1, 1);
|
||||
impl_pin!(P1_02, 1, 2);
|
||||
impl_pin!(P1_03, 1, 3);
|
||||
impl_pin!(P1_04, 1, 4);
|
||||
impl_pin!(P1_05, 1, 5);
|
||||
impl_pin!(P1_06, 1, 6);
|
||||
impl_pin!(P1_07, 1, 7);
|
||||
impl_pin!(P1_08, 1, 8);
|
||||
impl_pin!(P1_09, 1, 9);
|
||||
impl_pin!(P1_10, 1, 10);
|
||||
impl_pin!(P1_11, 1, 11);
|
||||
impl_pin!(P1_12, 1, 12);
|
||||
impl_pin!(P1_13, 1, 13);
|
||||
impl_pin!(P1_14, 1, 14);
|
||||
impl_pin!(P1_15, 1, 15);
|
||||
|
||||
impl_ppi_channel!(PPI_CH0, 0 => configurable);
|
||||
impl_ppi_channel!(PPI_CH1, 1 => configurable);
|
||||
impl_ppi_channel!(PPI_CH2, 2 => configurable);
|
||||
impl_ppi_channel!(PPI_CH3, 3 => configurable);
|
||||
impl_ppi_channel!(PPI_CH4, 4 => configurable);
|
||||
impl_ppi_channel!(PPI_CH5, 5 => configurable);
|
||||
impl_ppi_channel!(PPI_CH6, 6 => configurable);
|
||||
impl_ppi_channel!(PPI_CH7, 7 => configurable);
|
||||
impl_ppi_channel!(PPI_CH8, 8 => configurable);
|
||||
impl_ppi_channel!(PPI_CH9, 9 => configurable);
|
||||
impl_ppi_channel!(PPI_CH10, 10 => configurable);
|
||||
impl_ppi_channel!(PPI_CH11, 11 => configurable);
|
||||
impl_ppi_channel!(PPI_CH12, 12 => configurable);
|
||||
impl_ppi_channel!(PPI_CH13, 13 => configurable);
|
||||
impl_ppi_channel!(PPI_CH14, 14 => configurable);
|
||||
impl_ppi_channel!(PPI_CH15, 15 => configurable);
|
||||
impl_ppi_channel!(PPI_CH16, 16 => configurable);
|
||||
impl_ppi_channel!(PPI_CH17, 17 => configurable);
|
||||
impl_ppi_channel!(PPI_CH18, 18 => configurable);
|
||||
impl_ppi_channel!(PPI_CH19, 19 => configurable);
|
||||
impl_ppi_channel!(PPI_CH20, 20 => static);
|
||||
impl_ppi_channel!(PPI_CH21, 21 => static);
|
||||
impl_ppi_channel!(PPI_CH22, 22 => static);
|
||||
impl_ppi_channel!(PPI_CH23, 23 => static);
|
||||
impl_ppi_channel!(PPI_CH24, 24 => static);
|
||||
impl_ppi_channel!(PPI_CH25, 25 => static);
|
||||
impl_ppi_channel!(PPI_CH26, 26 => static);
|
||||
impl_ppi_channel!(PPI_CH27, 27 => static);
|
||||
impl_ppi_channel!(PPI_CH28, 28 => static);
|
||||
impl_ppi_channel!(PPI_CH29, 29 => static);
|
||||
impl_ppi_channel!(PPI_CH30, 30 => static);
|
||||
impl_ppi_channel!(PPI_CH31, 31 => static);
|
||||
|
||||
impl_saadc_input!(P0_02, ANALOG_INPUT0);
|
||||
impl_saadc_input!(P0_03, ANALOG_INPUT1);
|
||||
impl_saadc_input!(P0_04, ANALOG_INPUT2);
|
||||
impl_saadc_input!(P0_05, ANALOG_INPUT3);
|
||||
impl_saadc_input!(P0_28, ANALOG_INPUT4);
|
||||
impl_saadc_input!(P0_29, ANALOG_INPUT5);
|
||||
impl_saadc_input!(P0_30, ANALOG_INPUT6);
|
||||
impl_saadc_input!(P0_31, ANALOG_INPUT7);
|
||||
|
||||
impl_i2s!(I2S, I2S, I2S);
|
||||
|
||||
impl_radio!(RADIO, RADIO, RADIO);
|
||||
|
||||
impl_egu!(EGU0, EGU0, SWI0_EGU0);
|
||||
impl_egu!(EGU1, EGU1, SWI1_EGU1);
|
||||
impl_egu!(EGU2, EGU2, SWI2_EGU2);
|
||||
impl_egu!(EGU3, EGU3, SWI3_EGU3);
|
||||
impl_egu!(EGU4, EGU4, SWI4_EGU4);
|
||||
impl_egu!(EGU5, EGU5, SWI5_EGU5);
|
||||
|
||||
embassy_hal_internal::interrupt_mod!(
|
||||
POWER_CLOCK,
|
||||
RADIO,
|
||||
UARTE0_UART0,
|
||||
SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0,
|
||||
SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1,
|
||||
NFCT,
|
||||
GPIOTE,
|
||||
SAADC,
|
||||
TIMER0,
|
||||
TIMER1,
|
||||
TIMER2,
|
||||
RTC0,
|
||||
TEMP,
|
||||
RNG,
|
||||
ECB,
|
||||
CCM_AAR,
|
||||
WDT,
|
||||
RTC1,
|
||||
QDEC,
|
||||
COMP_LPCOMP,
|
||||
SWI0_EGU0,
|
||||
SWI1_EGU1,
|
||||
SWI2_EGU2,
|
||||
SWI3_EGU3,
|
||||
SWI4_EGU4,
|
||||
SWI5_EGU5,
|
||||
TIMER3,
|
||||
TIMER4,
|
||||
PWM0,
|
||||
PDM,
|
||||
MWU,
|
||||
PWM1,
|
||||
PWM2,
|
||||
SPIM2_SPIS2_SPI2,
|
||||
RTC2,
|
||||
FPU,
|
||||
USBD,
|
||||
UARTE1,
|
||||
PWM3,
|
||||
SPIM3,
|
||||
I2S,
|
||||
);
|
||||
+378
@@ -0,0 +1,378 @@
|
||||
pub use nrf52840_pac as pac;
|
||||
|
||||
/// The maximum buffer size that the EasyDMA can send/recv in one operation.
|
||||
pub const EASY_DMA_SIZE: usize = (1 << 16) - 1;
|
||||
pub const FORCE_COPY_BUFFER_SIZE: usize = 512;
|
||||
|
||||
pub const FLASH_SIZE: usize = 1024 * 1024;
|
||||
|
||||
pub const RESET_PIN: u32 = 18;
|
||||
pub const APPROTECT_MIN_BUILD_CODE: u8 = b'F';
|
||||
|
||||
embassy_hal_internal::peripherals! {
|
||||
// USB
|
||||
USBD,
|
||||
|
||||
// RTC
|
||||
RTC0,
|
||||
RTC1,
|
||||
RTC2,
|
||||
|
||||
// WDT
|
||||
WDT,
|
||||
|
||||
// NVMC
|
||||
NVMC,
|
||||
|
||||
// RNG
|
||||
RNG,
|
||||
|
||||
// QSPI
|
||||
QSPI,
|
||||
|
||||
// QDEC
|
||||
QDEC,
|
||||
|
||||
// UARTE
|
||||
UARTE0,
|
||||
UARTE1,
|
||||
|
||||
// SPI/TWI
|
||||
TWISPI0,
|
||||
TWISPI1,
|
||||
SPI2,
|
||||
SPI3,
|
||||
|
||||
// SAADC
|
||||
SAADC,
|
||||
|
||||
// PWM
|
||||
PWM0,
|
||||
PWM1,
|
||||
PWM2,
|
||||
PWM3,
|
||||
|
||||
// TIMER
|
||||
TIMER0,
|
||||
TIMER1,
|
||||
TIMER2,
|
||||
TIMER3,
|
||||
TIMER4,
|
||||
|
||||
// GPIOTE
|
||||
GPIOTE_CH0,
|
||||
GPIOTE_CH1,
|
||||
GPIOTE_CH2,
|
||||
GPIOTE_CH3,
|
||||
GPIOTE_CH4,
|
||||
GPIOTE_CH5,
|
||||
GPIOTE_CH6,
|
||||
GPIOTE_CH7,
|
||||
|
||||
// PPI
|
||||
PPI_CH0,
|
||||
PPI_CH1,
|
||||
PPI_CH2,
|
||||
PPI_CH3,
|
||||
PPI_CH4,
|
||||
PPI_CH5,
|
||||
PPI_CH6,
|
||||
PPI_CH7,
|
||||
PPI_CH8,
|
||||
PPI_CH9,
|
||||
PPI_CH10,
|
||||
PPI_CH11,
|
||||
PPI_CH12,
|
||||
PPI_CH13,
|
||||
PPI_CH14,
|
||||
PPI_CH15,
|
||||
PPI_CH16,
|
||||
PPI_CH17,
|
||||
PPI_CH18,
|
||||
PPI_CH19,
|
||||
PPI_CH20,
|
||||
PPI_CH21,
|
||||
PPI_CH22,
|
||||
PPI_CH23,
|
||||
PPI_CH24,
|
||||
PPI_CH25,
|
||||
PPI_CH26,
|
||||
PPI_CH27,
|
||||
PPI_CH28,
|
||||
PPI_CH29,
|
||||
PPI_CH30,
|
||||
PPI_CH31,
|
||||
|
||||
PPI_GROUP0,
|
||||
PPI_GROUP1,
|
||||
PPI_GROUP2,
|
||||
PPI_GROUP3,
|
||||
PPI_GROUP4,
|
||||
PPI_GROUP5,
|
||||
|
||||
// GPIO port 0
|
||||
P0_00,
|
||||
P0_01,
|
||||
P0_02,
|
||||
P0_03,
|
||||
P0_04,
|
||||
P0_05,
|
||||
P0_06,
|
||||
P0_07,
|
||||
P0_08,
|
||||
#[cfg(feature = "nfc-pins-as-gpio")]
|
||||
P0_09,
|
||||
#[cfg(feature = "nfc-pins-as-gpio")]
|
||||
P0_10,
|
||||
P0_11,
|
||||
P0_12,
|
||||
P0_13,
|
||||
P0_14,
|
||||
P0_15,
|
||||
P0_16,
|
||||
P0_17,
|
||||
#[cfg(feature="reset-pin-as-gpio")]
|
||||
P0_18,
|
||||
P0_19,
|
||||
P0_20,
|
||||
P0_21,
|
||||
P0_22,
|
||||
P0_23,
|
||||
P0_24,
|
||||
P0_25,
|
||||
P0_26,
|
||||
P0_27,
|
||||
P0_28,
|
||||
P0_29,
|
||||
P0_30,
|
||||
P0_31,
|
||||
|
||||
// GPIO port 1
|
||||
P1_00,
|
||||
P1_01,
|
||||
P1_02,
|
||||
P1_03,
|
||||
P1_04,
|
||||
P1_05,
|
||||
P1_06,
|
||||
P1_07,
|
||||
P1_08,
|
||||
P1_09,
|
||||
P1_10,
|
||||
P1_11,
|
||||
P1_12,
|
||||
P1_13,
|
||||
P1_14,
|
||||
P1_15,
|
||||
|
||||
// TEMP
|
||||
TEMP,
|
||||
|
||||
// PDM
|
||||
PDM,
|
||||
|
||||
// I2S
|
||||
I2S,
|
||||
|
||||
// Radio
|
||||
RADIO,
|
||||
|
||||
// EGU
|
||||
EGU0,
|
||||
EGU1,
|
||||
EGU2,
|
||||
EGU3,
|
||||
EGU4,
|
||||
EGU5,
|
||||
}
|
||||
|
||||
impl_usb!(USBD, USBD, USBD);
|
||||
|
||||
impl_uarte!(UARTE0, UARTE0, UARTE0_UART0);
|
||||
impl_uarte!(UARTE1, UARTE1, UARTE1);
|
||||
|
||||
impl_spim!(TWISPI0, SPIM0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
|
||||
impl_spim!(TWISPI1, SPIM1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
|
||||
impl_spim!(SPI2, SPIM2, SPIM2_SPIS2_SPI2);
|
||||
impl_spim!(SPI3, SPIM3, SPIM3);
|
||||
|
||||
impl_spis!(TWISPI0, SPIS0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
|
||||
impl_spis!(TWISPI1, SPIS1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
|
||||
impl_spis!(SPI2, SPIS2, SPIM2_SPIS2_SPI2);
|
||||
|
||||
impl_twim!(TWISPI0, TWIM0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
|
||||
impl_twim!(TWISPI1, TWIM1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
|
||||
|
||||
impl_twis!(TWISPI0, TWIS0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
|
||||
impl_twis!(TWISPI1, TWIS1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
|
||||
|
||||
impl_pwm!(PWM0, PWM0, PWM0);
|
||||
impl_pwm!(PWM1, PWM1, PWM1);
|
||||
impl_pwm!(PWM2, PWM2, PWM2);
|
||||
impl_pwm!(PWM3, PWM3, PWM3);
|
||||
|
||||
impl_timer!(TIMER0, TIMER0, TIMER0);
|
||||
impl_timer!(TIMER1, TIMER1, TIMER1);
|
||||
impl_timer!(TIMER2, TIMER2, TIMER2);
|
||||
impl_timer!(TIMER3, TIMER3, TIMER3, extended);
|
||||
impl_timer!(TIMER4, TIMER4, TIMER4, extended);
|
||||
|
||||
impl_qspi!(QSPI, QSPI, QSPI);
|
||||
|
||||
impl_pdm!(PDM, PDM, PDM);
|
||||
|
||||
impl_qdec!(QDEC, QDEC, QDEC);
|
||||
|
||||
impl_rng!(RNG, RNG, RNG);
|
||||
|
||||
impl_pin!(P0_00, 0, 0);
|
||||
impl_pin!(P0_01, 0, 1);
|
||||
impl_pin!(P0_02, 0, 2);
|
||||
impl_pin!(P0_03, 0, 3);
|
||||
impl_pin!(P0_04, 0, 4);
|
||||
impl_pin!(P0_05, 0, 5);
|
||||
impl_pin!(P0_06, 0, 6);
|
||||
impl_pin!(P0_07, 0, 7);
|
||||
impl_pin!(P0_08, 0, 8);
|
||||
#[cfg(feature = "nfc-pins-as-gpio")]
|
||||
impl_pin!(P0_09, 0, 9);
|
||||
#[cfg(feature = "nfc-pins-as-gpio")]
|
||||
impl_pin!(P0_10, 0, 10);
|
||||
impl_pin!(P0_11, 0, 11);
|
||||
impl_pin!(P0_12, 0, 12);
|
||||
impl_pin!(P0_13, 0, 13);
|
||||
impl_pin!(P0_14, 0, 14);
|
||||
impl_pin!(P0_15, 0, 15);
|
||||
impl_pin!(P0_16, 0, 16);
|
||||
impl_pin!(P0_17, 0, 17);
|
||||
#[cfg(feature = "reset-pin-as-gpio")]
|
||||
impl_pin!(P0_18, 0, 18);
|
||||
impl_pin!(P0_19, 0, 19);
|
||||
impl_pin!(P0_20, 0, 20);
|
||||
impl_pin!(P0_21, 0, 21);
|
||||
impl_pin!(P0_22, 0, 22);
|
||||
impl_pin!(P0_23, 0, 23);
|
||||
impl_pin!(P0_24, 0, 24);
|
||||
impl_pin!(P0_25, 0, 25);
|
||||
impl_pin!(P0_26, 0, 26);
|
||||
impl_pin!(P0_27, 0, 27);
|
||||
impl_pin!(P0_28, 0, 28);
|
||||
impl_pin!(P0_29, 0, 29);
|
||||
impl_pin!(P0_30, 0, 30);
|
||||
impl_pin!(P0_31, 0, 31);
|
||||
|
||||
impl_pin!(P1_00, 1, 0);
|
||||
impl_pin!(P1_01, 1, 1);
|
||||
impl_pin!(P1_02, 1, 2);
|
||||
impl_pin!(P1_03, 1, 3);
|
||||
impl_pin!(P1_04, 1, 4);
|
||||
impl_pin!(P1_05, 1, 5);
|
||||
impl_pin!(P1_06, 1, 6);
|
||||
impl_pin!(P1_07, 1, 7);
|
||||
impl_pin!(P1_08, 1, 8);
|
||||
impl_pin!(P1_09, 1, 9);
|
||||
impl_pin!(P1_10, 1, 10);
|
||||
impl_pin!(P1_11, 1, 11);
|
||||
impl_pin!(P1_12, 1, 12);
|
||||
impl_pin!(P1_13, 1, 13);
|
||||
impl_pin!(P1_14, 1, 14);
|
||||
impl_pin!(P1_15, 1, 15);
|
||||
|
||||
impl_ppi_channel!(PPI_CH0, 0 => configurable);
|
||||
impl_ppi_channel!(PPI_CH1, 1 => configurable);
|
||||
impl_ppi_channel!(PPI_CH2, 2 => configurable);
|
||||
impl_ppi_channel!(PPI_CH3, 3 => configurable);
|
||||
impl_ppi_channel!(PPI_CH4, 4 => configurable);
|
||||
impl_ppi_channel!(PPI_CH5, 5 => configurable);
|
||||
impl_ppi_channel!(PPI_CH6, 6 => configurable);
|
||||
impl_ppi_channel!(PPI_CH7, 7 => configurable);
|
||||
impl_ppi_channel!(PPI_CH8, 8 => configurable);
|
||||
impl_ppi_channel!(PPI_CH9, 9 => configurable);
|
||||
impl_ppi_channel!(PPI_CH10, 10 => configurable);
|
||||
impl_ppi_channel!(PPI_CH11, 11 => configurable);
|
||||
impl_ppi_channel!(PPI_CH12, 12 => configurable);
|
||||
impl_ppi_channel!(PPI_CH13, 13 => configurable);
|
||||
impl_ppi_channel!(PPI_CH14, 14 => configurable);
|
||||
impl_ppi_channel!(PPI_CH15, 15 => configurable);
|
||||
impl_ppi_channel!(PPI_CH16, 16 => configurable);
|
||||
impl_ppi_channel!(PPI_CH17, 17 => configurable);
|
||||
impl_ppi_channel!(PPI_CH18, 18 => configurable);
|
||||
impl_ppi_channel!(PPI_CH19, 19 => configurable);
|
||||
impl_ppi_channel!(PPI_CH20, 20 => static);
|
||||
impl_ppi_channel!(PPI_CH21, 21 => static);
|
||||
impl_ppi_channel!(PPI_CH22, 22 => static);
|
||||
impl_ppi_channel!(PPI_CH23, 23 => static);
|
||||
impl_ppi_channel!(PPI_CH24, 24 => static);
|
||||
impl_ppi_channel!(PPI_CH25, 25 => static);
|
||||
impl_ppi_channel!(PPI_CH26, 26 => static);
|
||||
impl_ppi_channel!(PPI_CH27, 27 => static);
|
||||
impl_ppi_channel!(PPI_CH28, 28 => static);
|
||||
impl_ppi_channel!(PPI_CH29, 29 => static);
|
||||
impl_ppi_channel!(PPI_CH30, 30 => static);
|
||||
impl_ppi_channel!(PPI_CH31, 31 => static);
|
||||
|
||||
impl_saadc_input!(P0_02, ANALOG_INPUT0);
|
||||
impl_saadc_input!(P0_03, ANALOG_INPUT1);
|
||||
impl_saadc_input!(P0_04, ANALOG_INPUT2);
|
||||
impl_saadc_input!(P0_05, ANALOG_INPUT3);
|
||||
impl_saadc_input!(P0_28, ANALOG_INPUT4);
|
||||
impl_saadc_input!(P0_29, ANALOG_INPUT5);
|
||||
impl_saadc_input!(P0_30, ANALOG_INPUT6);
|
||||
impl_saadc_input!(P0_31, ANALOG_INPUT7);
|
||||
|
||||
impl_i2s!(I2S, I2S, I2S);
|
||||
|
||||
impl_radio!(RADIO, RADIO, RADIO);
|
||||
|
||||
impl_egu!(EGU0, EGU0, SWI0_EGU0);
|
||||
impl_egu!(EGU1, EGU1, SWI1_EGU1);
|
||||
impl_egu!(EGU2, EGU2, SWI2_EGU2);
|
||||
impl_egu!(EGU3, EGU3, SWI3_EGU3);
|
||||
impl_egu!(EGU4, EGU4, SWI4_EGU4);
|
||||
impl_egu!(EGU5, EGU5, SWI5_EGU5);
|
||||
|
||||
embassy_hal_internal::interrupt_mod!(
|
||||
POWER_CLOCK,
|
||||
RADIO,
|
||||
UARTE0_UART0,
|
||||
SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0,
|
||||
SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1,
|
||||
NFCT,
|
||||
GPIOTE,
|
||||
SAADC,
|
||||
TIMER0,
|
||||
TIMER1,
|
||||
TIMER2,
|
||||
RTC0,
|
||||
TEMP,
|
||||
RNG,
|
||||
ECB,
|
||||
CCM_AAR,
|
||||
WDT,
|
||||
RTC1,
|
||||
QDEC,
|
||||
COMP_LPCOMP,
|
||||
SWI0_EGU0,
|
||||
SWI1_EGU1,
|
||||
SWI2_EGU2,
|
||||
SWI3_EGU3,
|
||||
SWI4_EGU4,
|
||||
SWI5_EGU5,
|
||||
TIMER3,
|
||||
TIMER4,
|
||||
PWM0,
|
||||
PDM,
|
||||
MWU,
|
||||
PWM1,
|
||||
PWM2,
|
||||
SPIM2_SPIS2_SPI2,
|
||||
RTC2,
|
||||
FPU,
|
||||
USBD,
|
||||
UARTE1,
|
||||
QSPI,
|
||||
CRYPTOCELL,
|
||||
PWM3,
|
||||
SPIM3,
|
||||
I2S,
|
||||
);
|
||||
+579
@@ -0,0 +1,579 @@
|
||||
/// Peripheral Access Crate
|
||||
#[allow(unused_imports)]
|
||||
#[rustfmt::skip]
|
||||
pub mod pac {
|
||||
// The nRF5340 has a secure and non-secure (NS) mode.
|
||||
// To avoid cfg spam, we remove _ns or _s suffixes here.
|
||||
|
||||
pub use nrf5340_app_pac::NVIC_PRIO_BITS;
|
||||
|
||||
#[cfg(feature="rt")]
|
||||
#[doc(no_inline)]
|
||||
pub use nrf5340_app_pac::interrupt;
|
||||
|
||||
#[doc(no_inline)]
|
||||
pub use nrf5340_app_pac::{
|
||||
Interrupt,
|
||||
Peripherals,
|
||||
|
||||
cache_s as cache,
|
||||
cachedata_s as cachedata,
|
||||
cacheinfo_s as cacheinfo,
|
||||
clock_ns as clock,
|
||||
comp_ns as comp,
|
||||
cryptocell_s as cryptocell,
|
||||
cti_s as cti,
|
||||
ctrlap_ns as ctrlap,
|
||||
dcnf_ns as dcnf,
|
||||
dppic_ns as dppic,
|
||||
egu0_ns as egu0,
|
||||
ficr_s as ficr,
|
||||
fpu_ns as fpu,
|
||||
gpiote0_s as gpiote,
|
||||
i2s0_ns as i2s0,
|
||||
ipc_ns as ipc,
|
||||
kmu_ns as kmu,
|
||||
lpcomp_ns as lpcomp,
|
||||
mutex_ns as mutex,
|
||||
nfct_ns as nfct,
|
||||
nvmc_ns as nvmc,
|
||||
oscillators_ns as oscillators,
|
||||
p0_ns as p0,
|
||||
pdm0_ns as pdm,
|
||||
power_ns as power,
|
||||
pwm0_ns as pwm0,
|
||||
qdec0_ns as qdec,
|
||||
qspi_ns as qspi,
|
||||
regulators_ns as regulators,
|
||||
reset_ns as reset,
|
||||
rtc0_ns as rtc0,
|
||||
saadc_ns as saadc,
|
||||
spim0_ns as spim0,
|
||||
spis0_ns as spis0,
|
||||
spu_s as spu,
|
||||
tad_s as tad,
|
||||
timer0_ns as timer0,
|
||||
twim0_ns as twim0,
|
||||
twis0_ns as twis0,
|
||||
uarte0_ns as uarte0,
|
||||
uicr_s as uicr,
|
||||
usbd_ns as usbd,
|
||||
usbregulator_ns as usbregulator,
|
||||
vmc_ns as vmc,
|
||||
wdt0_ns as wdt0,
|
||||
};
|
||||
|
||||
/// Non-Secure mode (NS) peripherals
|
||||
pub mod ns {
|
||||
#[cfg(feature = "nrf5340-app-ns")]
|
||||
#[doc(no_inline)]
|
||||
pub use nrf5340_app_pac::{
|
||||
CLOCK_NS as CLOCK,
|
||||
COMP_NS as COMP,
|
||||
CTRLAP_NS as CTRLAP,
|
||||
DCNF_NS as DCNF,
|
||||
DPPIC_NS as DPPIC,
|
||||
EGU0_NS as EGU0,
|
||||
EGU1_NS as EGU1,
|
||||
EGU2_NS as EGU2,
|
||||
EGU3_NS as EGU3,
|
||||
EGU4_NS as EGU4,
|
||||
EGU5_NS as EGU5,
|
||||
FPU_NS as FPU,
|
||||
GPIOTE1_NS as GPIOTE1,
|
||||
I2S0_NS as I2S0,
|
||||
IPC_NS as IPC,
|
||||
KMU_NS as KMU,
|
||||
LPCOMP_NS as LPCOMP,
|
||||
MUTEX_NS as MUTEX,
|
||||
NFCT_NS as NFCT,
|
||||
NVMC_NS as NVMC,
|
||||
OSCILLATORS_NS as OSCILLATORS,
|
||||
P0_NS as P0,
|
||||
P1_NS as P1,
|
||||
PDM0_NS as PDM0,
|
||||
POWER_NS as POWER,
|
||||
PWM0_NS as PWM0,
|
||||
PWM1_NS as PWM1,
|
||||
PWM2_NS as PWM2,
|
||||
PWM3_NS as PWM3,
|
||||
QDEC0_NS as QDEC0,
|
||||
QDEC1_NS as QDEC1,
|
||||
QSPI_NS as QSPI,
|
||||
REGULATORS_NS as REGULATORS,
|
||||
RESET_NS as RESET,
|
||||
RTC0_NS as RTC0,
|
||||
RTC1_NS as RTC1,
|
||||
SAADC_NS as SAADC,
|
||||
SPIM0_NS as SPIM0,
|
||||
SPIM1_NS as SPIM1,
|
||||
SPIM2_NS as SPIM2,
|
||||
SPIM3_NS as SPIM3,
|
||||
SPIM4_NS as SPIM4,
|
||||
SPIS0_NS as SPIS0,
|
||||
SPIS1_NS as SPIS1,
|
||||
SPIS2_NS as SPIS2,
|
||||
SPIS3_NS as SPIS3,
|
||||
TIMER0_NS as TIMER0,
|
||||
TIMER1_NS as TIMER1,
|
||||
TIMER2_NS as TIMER2,
|
||||
TWIM0_NS as TWIM0,
|
||||
TWIM1_NS as TWIM1,
|
||||
TWIM2_NS as TWIM2,
|
||||
TWIM3_NS as TWIM3,
|
||||
TWIS0_NS as TWIS0,
|
||||
TWIS1_NS as TWIS1,
|
||||
TWIS2_NS as TWIS2,
|
||||
TWIS3_NS as TWIS3,
|
||||
UARTE0_NS as UARTE0,
|
||||
UARTE1_NS as UARTE1,
|
||||
UARTE2_NS as UARTE2,
|
||||
UARTE3_NS as UARTE3,
|
||||
USBD_NS as USBD,
|
||||
USBREGULATOR_NS as USBREGULATOR,
|
||||
VMC_NS as VMC,
|
||||
WDT0_NS as WDT0,
|
||||
WDT1_NS as WDT1,
|
||||
};
|
||||
}
|
||||
|
||||
/// Secure mode (S) peripherals
|
||||
pub mod s {
|
||||
#[cfg(feature = "nrf5340-app-s")]
|
||||
#[doc(no_inline)]
|
||||
pub use nrf5340_app_pac::{
|
||||
CACHEDATA_S as CACHEDATA,
|
||||
CACHEINFO_S as CACHEINFO,
|
||||
CACHE_S as CACHE,
|
||||
CLOCK_S as CLOCK,
|
||||
COMP_S as COMP,
|
||||
CRYPTOCELL_S as CRYPTOCELL,
|
||||
CTI_S as CTI,
|
||||
CTRLAP_S as CTRLAP,
|
||||
DCNF_S as DCNF,
|
||||
DPPIC_S as DPPIC,
|
||||
EGU0_S as EGU0,
|
||||
EGU1_S as EGU1,
|
||||
EGU2_S as EGU2,
|
||||
EGU3_S as EGU3,
|
||||
EGU4_S as EGU4,
|
||||
EGU5_S as EGU5,
|
||||
FICR_S as FICR,
|
||||
FPU_S as FPU,
|
||||
GPIOTE0_S as GPIOTE0,
|
||||
I2S0_S as I2S0,
|
||||
IPC_S as IPC,
|
||||
KMU_S as KMU,
|
||||
LPCOMP_S as LPCOMP,
|
||||
MUTEX_S as MUTEX,
|
||||
NFCT_S as NFCT,
|
||||
NVMC_S as NVMC,
|
||||
OSCILLATORS_S as OSCILLATORS,
|
||||
P0_S as P0,
|
||||
P1_S as P1,
|
||||
PDM0_S as PDM0,
|
||||
POWER_S as POWER,
|
||||
PWM0_S as PWM0,
|
||||
PWM1_S as PWM1,
|
||||
PWM2_S as PWM2,
|
||||
PWM3_S as PWM3,
|
||||
QDEC0_S as QDEC0,
|
||||
QDEC1_S as QDEC1,
|
||||
QSPI_S as QSPI,
|
||||
REGULATORS_S as REGULATORS,
|
||||
RESET_S as RESET,
|
||||
RTC0_S as RTC0,
|
||||
RTC1_S as RTC1,
|
||||
SAADC_S as SAADC,
|
||||
SPIM0_S as SPIM0,
|
||||
SPIM1_S as SPIM1,
|
||||
SPIM2_S as SPIM2,
|
||||
SPIM3_S as SPIM3,
|
||||
SPIM4_S as SPIM4,
|
||||
SPIS0_S as SPIS0,
|
||||
SPIS1_S as SPIS1,
|
||||
SPIS2_S as SPIS2,
|
||||
SPIS3_S as SPIS3,
|
||||
SPU_S as SPU,
|
||||
TAD_S as TAD,
|
||||
TIMER0_S as TIMER0,
|
||||
TIMER1_S as TIMER1,
|
||||
TIMER2_S as TIMER2,
|
||||
TWIM0_S as TWIM0,
|
||||
TWIM1_S as TWIM1,
|
||||
TWIM2_S as TWIM2,
|
||||
TWIM3_S as TWIM3,
|
||||
TWIS0_S as TWIS0,
|
||||
TWIS1_S as TWIS1,
|
||||
TWIS2_S as TWIS2,
|
||||
TWIS3_S as TWIS3,
|
||||
UARTE0_S as UARTE0,
|
||||
UARTE1_S as UARTE1,
|
||||
UARTE2_S as UARTE2,
|
||||
UARTE3_S as UARTE3,
|
||||
UICR_S as UICR,
|
||||
USBD_S as USBD,
|
||||
USBREGULATOR_S as USBREGULATOR,
|
||||
VMC_S as VMC,
|
||||
WDT0_S as WDT0,
|
||||
WDT1_S as WDT1,
|
||||
};
|
||||
}
|
||||
|
||||
#[cfg(feature = "_ns")]
|
||||
pub use ns::*;
|
||||
#[cfg(feature = "_s")]
|
||||
pub use s::*;
|
||||
}
|
||||
|
||||
/// The maximum buffer size that the EasyDMA can send/recv in one operation.
|
||||
pub const EASY_DMA_SIZE: usize = (1 << 16) - 1;
|
||||
pub const FORCE_COPY_BUFFER_SIZE: usize = 1024;
|
||||
|
||||
pub const FLASH_SIZE: usize = 1024 * 1024;
|
||||
|
||||
embassy_hal_internal::peripherals! {
|
||||
// USB
|
||||
USBD,
|
||||
|
||||
// RTC
|
||||
RTC0,
|
||||
RTC1,
|
||||
|
||||
// WDT
|
||||
WDT,
|
||||
|
||||
// NVMC
|
||||
NVMC,
|
||||
|
||||
// UARTE, TWI & SPI
|
||||
SERIAL0,
|
||||
SERIAL1,
|
||||
SERIAL2,
|
||||
SERIAL3,
|
||||
|
||||
// SAADC
|
||||
SAADC,
|
||||
|
||||
// PWM
|
||||
PWM0,
|
||||
PWM1,
|
||||
PWM2,
|
||||
PWM3,
|
||||
|
||||
// TIMER
|
||||
TIMER0,
|
||||
TIMER1,
|
||||
TIMER2,
|
||||
|
||||
// QSPI
|
||||
QSPI,
|
||||
|
||||
// PDM
|
||||
PDM0,
|
||||
|
||||
// QDEC
|
||||
QDEC0,
|
||||
QDEC1,
|
||||
|
||||
// GPIOTE
|
||||
GPIOTE_CH0,
|
||||
GPIOTE_CH1,
|
||||
GPIOTE_CH2,
|
||||
GPIOTE_CH3,
|
||||
GPIOTE_CH4,
|
||||
GPIOTE_CH5,
|
||||
GPIOTE_CH6,
|
||||
GPIOTE_CH7,
|
||||
|
||||
// PPI
|
||||
PPI_CH0,
|
||||
PPI_CH1,
|
||||
PPI_CH2,
|
||||
PPI_CH3,
|
||||
PPI_CH4,
|
||||
PPI_CH5,
|
||||
PPI_CH6,
|
||||
PPI_CH7,
|
||||
PPI_CH8,
|
||||
PPI_CH9,
|
||||
PPI_CH10,
|
||||
PPI_CH11,
|
||||
PPI_CH12,
|
||||
PPI_CH13,
|
||||
PPI_CH14,
|
||||
PPI_CH15,
|
||||
PPI_CH16,
|
||||
PPI_CH17,
|
||||
PPI_CH18,
|
||||
PPI_CH19,
|
||||
PPI_CH20,
|
||||
PPI_CH21,
|
||||
PPI_CH22,
|
||||
PPI_CH23,
|
||||
PPI_CH24,
|
||||
PPI_CH25,
|
||||
PPI_CH26,
|
||||
PPI_CH27,
|
||||
PPI_CH28,
|
||||
PPI_CH29,
|
||||
PPI_CH30,
|
||||
PPI_CH31,
|
||||
|
||||
PPI_GROUP0,
|
||||
PPI_GROUP1,
|
||||
PPI_GROUP2,
|
||||
PPI_GROUP3,
|
||||
PPI_GROUP4,
|
||||
PPI_GROUP5,
|
||||
|
||||
// GPIO port 0
|
||||
P0_00,
|
||||
P0_01,
|
||||
#[cfg(feature = "nfc-pins-as-gpio")]
|
||||
P0_02,
|
||||
#[cfg(feature = "nfc-pins-as-gpio")]
|
||||
P0_03,
|
||||
P0_04,
|
||||
P0_05,
|
||||
P0_06,
|
||||
P0_07,
|
||||
P0_08,
|
||||
P0_09,
|
||||
P0_10,
|
||||
P0_11,
|
||||
P0_12,
|
||||
P0_13,
|
||||
P0_14,
|
||||
P0_15,
|
||||
P0_16,
|
||||
P0_17,
|
||||
P0_18,
|
||||
P0_19,
|
||||
P0_20,
|
||||
P0_21,
|
||||
P0_22,
|
||||
P0_23,
|
||||
P0_24,
|
||||
P0_25,
|
||||
P0_26,
|
||||
P0_27,
|
||||
P0_28,
|
||||
P0_29,
|
||||
P0_30,
|
||||
P0_31,
|
||||
|
||||
// GPIO port 1
|
||||
P1_00,
|
||||
P1_01,
|
||||
P1_02,
|
||||
P1_03,
|
||||
P1_04,
|
||||
P1_05,
|
||||
P1_06,
|
||||
P1_07,
|
||||
P1_08,
|
||||
P1_09,
|
||||
P1_10,
|
||||
P1_11,
|
||||
P1_12,
|
||||
P1_13,
|
||||
P1_14,
|
||||
P1_15,
|
||||
|
||||
// EGU
|
||||
EGU0,
|
||||
EGU1,
|
||||
EGU2,
|
||||
EGU3,
|
||||
EGU4,
|
||||
EGU5,
|
||||
}
|
||||
|
||||
impl_usb!(USBD, USBD, USBD);
|
||||
|
||||
impl_uarte!(SERIAL0, UARTE0, SERIAL0);
|
||||
impl_uarte!(SERIAL1, UARTE1, SERIAL1);
|
||||
impl_uarte!(SERIAL2, UARTE2, SERIAL2);
|
||||
impl_uarte!(SERIAL3, UARTE3, SERIAL3);
|
||||
|
||||
impl_spim!(SERIAL0, SPIM0, SERIAL0);
|
||||
impl_spim!(SERIAL1, SPIM1, SERIAL1);
|
||||
impl_spim!(SERIAL2, SPIM2, SERIAL2);
|
||||
impl_spim!(SERIAL3, SPIM3, SERIAL3);
|
||||
|
||||
impl_spis!(SERIAL0, SPIS0, SERIAL0);
|
||||
impl_spis!(SERIAL1, SPIS1, SERIAL1);
|
||||
impl_spis!(SERIAL2, SPIS2, SERIAL2);
|
||||
impl_spis!(SERIAL3, SPIS3, SERIAL3);
|
||||
|
||||
impl_twim!(SERIAL0, TWIM0, SERIAL0);
|
||||
impl_twim!(SERIAL1, TWIM1, SERIAL1);
|
||||
impl_twim!(SERIAL2, TWIM2, SERIAL2);
|
||||
impl_twim!(SERIAL3, TWIM3, SERIAL3);
|
||||
|
||||
impl_twis!(SERIAL0, TWIS0, SERIAL0);
|
||||
impl_twis!(SERIAL1, TWIS1, SERIAL1);
|
||||
impl_twis!(SERIAL2, TWIS2, SERIAL2);
|
||||
impl_twis!(SERIAL3, TWIS3, SERIAL3);
|
||||
|
||||
impl_pwm!(PWM0, PWM0, PWM0);
|
||||
impl_pwm!(PWM1, PWM1, PWM1);
|
||||
impl_pwm!(PWM2, PWM2, PWM2);
|
||||
impl_pwm!(PWM3, PWM3, PWM3);
|
||||
|
||||
impl_timer!(TIMER0, TIMER0, TIMER0);
|
||||
impl_timer!(TIMER1, TIMER1, TIMER1);
|
||||
impl_timer!(TIMER2, TIMER2, TIMER2);
|
||||
|
||||
impl_qspi!(QSPI, QSPI, QSPI);
|
||||
|
||||
impl_pdm!(PDM0, PDM0, PDM0);
|
||||
|
||||
impl_qdec!(QDEC0, QDEC0, QDEC0);
|
||||
impl_qdec!(QDEC1, QDEC1, QDEC1);
|
||||
|
||||
impl_pin!(P0_00, 0, 0);
|
||||
impl_pin!(P0_01, 0, 1);
|
||||
#[cfg(feature = "nfc-pins-as-gpio")]
|
||||
impl_pin!(P0_02, 0, 2);
|
||||
#[cfg(feature = "nfc-pins-as-gpio")]
|
||||
impl_pin!(P0_03, 0, 3);
|
||||
impl_pin!(P0_04, 0, 4);
|
||||
impl_pin!(P0_05, 0, 5);
|
||||
impl_pin!(P0_06, 0, 6);
|
||||
impl_pin!(P0_07, 0, 7);
|
||||
impl_pin!(P0_08, 0, 8);
|
||||
impl_pin!(P0_09, 0, 9);
|
||||
impl_pin!(P0_10, 0, 10);
|
||||
impl_pin!(P0_11, 0, 11);
|
||||
impl_pin!(P0_12, 0, 12);
|
||||
impl_pin!(P0_13, 0, 13);
|
||||
impl_pin!(P0_14, 0, 14);
|
||||
impl_pin!(P0_15, 0, 15);
|
||||
impl_pin!(P0_16, 0, 16);
|
||||
impl_pin!(P0_17, 0, 17);
|
||||
impl_pin!(P0_18, 0, 18);
|
||||
impl_pin!(P0_19, 0, 19);
|
||||
impl_pin!(P0_20, 0, 20);
|
||||
impl_pin!(P0_21, 0, 21);
|
||||
impl_pin!(P0_22, 0, 22);
|
||||
impl_pin!(P0_23, 0, 23);
|
||||
impl_pin!(P0_24, 0, 24);
|
||||
impl_pin!(P0_25, 0, 25);
|
||||
impl_pin!(P0_26, 0, 26);
|
||||
impl_pin!(P0_27, 0, 27);
|
||||
impl_pin!(P0_28, 0, 28);
|
||||
impl_pin!(P0_29, 0, 29);
|
||||
impl_pin!(P0_30, 0, 30);
|
||||
impl_pin!(P0_31, 0, 31);
|
||||
|
||||
impl_pin!(P1_00, 1, 0);
|
||||
impl_pin!(P1_01, 1, 1);
|
||||
impl_pin!(P1_02, 1, 2);
|
||||
impl_pin!(P1_03, 1, 3);
|
||||
impl_pin!(P1_04, 1, 4);
|
||||
impl_pin!(P1_05, 1, 5);
|
||||
impl_pin!(P1_06, 1, 6);
|
||||
impl_pin!(P1_07, 1, 7);
|
||||
impl_pin!(P1_08, 1, 8);
|
||||
impl_pin!(P1_09, 1, 9);
|
||||
impl_pin!(P1_10, 1, 10);
|
||||
impl_pin!(P1_11, 1, 11);
|
||||
impl_pin!(P1_12, 1, 12);
|
||||
impl_pin!(P1_13, 1, 13);
|
||||
impl_pin!(P1_14, 1, 14);
|
||||
impl_pin!(P1_15, 1, 15);
|
||||
|
||||
impl_ppi_channel!(PPI_CH0, 0 => configurable);
|
||||
impl_ppi_channel!(PPI_CH1, 1 => configurable);
|
||||
impl_ppi_channel!(PPI_CH2, 2 => configurable);
|
||||
impl_ppi_channel!(PPI_CH3, 3 => configurable);
|
||||
impl_ppi_channel!(PPI_CH4, 4 => configurable);
|
||||
impl_ppi_channel!(PPI_CH5, 5 => configurable);
|
||||
impl_ppi_channel!(PPI_CH6, 6 => configurable);
|
||||
impl_ppi_channel!(PPI_CH7, 7 => configurable);
|
||||
impl_ppi_channel!(PPI_CH8, 8 => configurable);
|
||||
impl_ppi_channel!(PPI_CH9, 9 => configurable);
|
||||
impl_ppi_channel!(PPI_CH10, 10 => configurable);
|
||||
impl_ppi_channel!(PPI_CH11, 11 => configurable);
|
||||
impl_ppi_channel!(PPI_CH12, 12 => configurable);
|
||||
impl_ppi_channel!(PPI_CH13, 13 => configurable);
|
||||
impl_ppi_channel!(PPI_CH14, 14 => configurable);
|
||||
impl_ppi_channel!(PPI_CH15, 15 => configurable);
|
||||
impl_ppi_channel!(PPI_CH16, 16 => configurable);
|
||||
impl_ppi_channel!(PPI_CH17, 17 => configurable);
|
||||
impl_ppi_channel!(PPI_CH18, 18 => configurable);
|
||||
impl_ppi_channel!(PPI_CH19, 19 => configurable);
|
||||
impl_ppi_channel!(PPI_CH20, 20 => configurable);
|
||||
impl_ppi_channel!(PPI_CH21, 21 => configurable);
|
||||
impl_ppi_channel!(PPI_CH22, 22 => configurable);
|
||||
impl_ppi_channel!(PPI_CH23, 23 => configurable);
|
||||
impl_ppi_channel!(PPI_CH24, 24 => configurable);
|
||||
impl_ppi_channel!(PPI_CH25, 25 => configurable);
|
||||
impl_ppi_channel!(PPI_CH26, 26 => configurable);
|
||||
impl_ppi_channel!(PPI_CH27, 27 => configurable);
|
||||
impl_ppi_channel!(PPI_CH28, 28 => configurable);
|
||||
impl_ppi_channel!(PPI_CH29, 29 => configurable);
|
||||
impl_ppi_channel!(PPI_CH30, 30 => configurable);
|
||||
impl_ppi_channel!(PPI_CH31, 31 => configurable);
|
||||
|
||||
impl_saadc_input!(P0_13, ANALOG_INPUT0);
|
||||
impl_saadc_input!(P0_14, ANALOG_INPUT1);
|
||||
impl_saadc_input!(P0_15, ANALOG_INPUT2);
|
||||
impl_saadc_input!(P0_16, ANALOG_INPUT3);
|
||||
impl_saadc_input!(P0_17, ANALOG_INPUT4);
|
||||
impl_saadc_input!(P0_18, ANALOG_INPUT5);
|
||||
impl_saadc_input!(P0_19, ANALOG_INPUT6);
|
||||
impl_saadc_input!(P0_20, ANALOG_INPUT7);
|
||||
|
||||
impl_egu!(EGU0, EGU0, EGU0);
|
||||
impl_egu!(EGU1, EGU1, EGU1);
|
||||
impl_egu!(EGU2, EGU2, EGU2);
|
||||
impl_egu!(EGU3, EGU3, EGU3);
|
||||
impl_egu!(EGU4, EGU4, EGU4);
|
||||
impl_egu!(EGU5, EGU5, EGU5);
|
||||
|
||||
embassy_hal_internal::interrupt_mod!(
|
||||
FPU,
|
||||
CACHE,
|
||||
SPU,
|
||||
CLOCK_POWER,
|
||||
SERIAL0,
|
||||
SERIAL1,
|
||||
SPIM4,
|
||||
SERIAL2,
|
||||
SERIAL3,
|
||||
GPIOTE0,
|
||||
SAADC,
|
||||
TIMER0,
|
||||
TIMER1,
|
||||
TIMER2,
|
||||
RTC0,
|
||||
RTC1,
|
||||
WDT0,
|
||||
WDT1,
|
||||
COMP_LPCOMP,
|
||||
EGU0,
|
||||
EGU1,
|
||||
EGU2,
|
||||
EGU3,
|
||||
EGU4,
|
||||
EGU5,
|
||||
PWM0,
|
||||
PWM1,
|
||||
PWM2,
|
||||
PWM3,
|
||||
PDM0,
|
||||
I2S0,
|
||||
IPC,
|
||||
QSPI,
|
||||
NFCT,
|
||||
GPIOTE1,
|
||||
QDEC0,
|
||||
QDEC1,
|
||||
USBD,
|
||||
USBREGULATOR,
|
||||
KMU,
|
||||
CRYPTOCELL,
|
||||
);
|
||||
+379
@@ -0,0 +1,379 @@
|
||||
/// Peripheral Access Crate
|
||||
#[allow(unused_imports)]
|
||||
#[rustfmt::skip]
|
||||
pub mod pac {
|
||||
// The nRF5340 has a secure and non-secure (NS) mode.
|
||||
// To avoid cfg spam, we remove _ns or _s suffixes here.
|
||||
|
||||
pub use nrf5340_net_pac::NVIC_PRIO_BITS;
|
||||
|
||||
#[cfg(feature="rt")]
|
||||
#[doc(no_inline)]
|
||||
pub use nrf5340_net_pac::interrupt;
|
||||
|
||||
#[doc(no_inline)]
|
||||
pub use nrf5340_net_pac::{
|
||||
Interrupt,
|
||||
Peripherals,
|
||||
|
||||
aar_ns as aar,
|
||||
acl_ns as acl,
|
||||
appmutex_ns as appmutex,
|
||||
ccm_ns as ccm,
|
||||
clock_ns as clock,
|
||||
cti_ns as cti,
|
||||
ctrlap_ns as ctrlap,
|
||||
dcnf_ns as dcnf,
|
||||
dppic_ns as dppic,
|
||||
ecb_ns as ecb,
|
||||
egu0_ns as egu0,
|
||||
ficr_ns as ficr,
|
||||
gpiote_ns as gpiote,
|
||||
ipc_ns as ipc,
|
||||
nvmc_ns as nvmc,
|
||||
p0_ns as p0,
|
||||
power_ns as power,
|
||||
radio_ns as radio,
|
||||
reset_ns as reset,
|
||||
rng_ns as rng,
|
||||
rtc0_ns as rtc0,
|
||||
spim0_ns as spim0,
|
||||
spis0_ns as spis0,
|
||||
swi0_ns as swi0,
|
||||
temp_ns as temp,
|
||||
timer0_ns as timer0,
|
||||
twim0_ns as twim0,
|
||||
twis0_ns as twis0,
|
||||
uarte0_ns as uarte0,
|
||||
uicr_ns as uicr,
|
||||
vmc_ns as vmc,
|
||||
vreqctrl_ns as vreqctrl,
|
||||
wdt_ns as wdt,
|
||||
|
||||
AAR_NS as AAR,
|
||||
ACL_NS as ACL,
|
||||
APPMUTEX_NS as APPMUTEX,
|
||||
APPMUTEX_S as APPMUTEX_S,
|
||||
CBP as CBP,
|
||||
CCM_NS as CCM,
|
||||
CLOCK_NS as CLOCK,
|
||||
CPUID as CPUID,
|
||||
CTI_NS as CTI,
|
||||
CTRLAP_NS as CTRLAP,
|
||||
DCB as DCB,
|
||||
DCNF_NS as DCNF,
|
||||
DPPIC_NS as DPPIC,
|
||||
DWT as DWT,
|
||||
ECB_NS as ECB,
|
||||
EGU0_NS as EGU0,
|
||||
FICR_NS as FICR,
|
||||
FPB as FPB,
|
||||
GPIOTE_NS as GPIOTE,
|
||||
IPC_NS as IPC,
|
||||
ITM as ITM,
|
||||
MPU as MPU,
|
||||
NVIC as NVIC,
|
||||
NVMC_NS as NVMC,
|
||||
P0_NS as P0,
|
||||
P1_NS as P1,
|
||||
POWER_NS as POWER,
|
||||
RADIO_NS as RADIO,
|
||||
RESET_NS as RESET,
|
||||
RNG_NS as RNG,
|
||||
RTC0_NS as RTC0,
|
||||
RTC1_NS as RTC1,
|
||||
SCB as SCB,
|
||||
SPIM0_NS as SPIM0,
|
||||
SPIS0_NS as SPIS0,
|
||||
SWI0_NS as SWI0,
|
||||
SWI1_NS as SWI1,
|
||||
SWI2_NS as SWI2,
|
||||
SWI3_NS as SWI3,
|
||||
SYST as SYST,
|
||||
TEMP_NS as TEMP,
|
||||
TIMER0_NS as TIMER0,
|
||||
TIMER1_NS as TIMER1,
|
||||
TIMER2_NS as TIMER2,
|
||||
TPIU as TPIU,
|
||||
TWIM0_NS as TWIM0,
|
||||
TWIS0_NS as TWIS0,
|
||||
UARTE0_NS as UARTE0,
|
||||
UICR_NS as UICR,
|
||||
VMC_NS as VMC,
|
||||
VREQCTRL_NS as VREQCTRL,
|
||||
WDT_NS as WDT,
|
||||
};
|
||||
|
||||
}
|
||||
|
||||
/// The maximum buffer size that the EasyDMA can send/recv in one operation.
|
||||
pub const EASY_DMA_SIZE: usize = (1 << 16) - 1;
|
||||
pub const FORCE_COPY_BUFFER_SIZE: usize = 1024;
|
||||
|
||||
pub const FLASH_SIZE: usize = 256 * 1024;
|
||||
|
||||
embassy_hal_internal::peripherals! {
|
||||
// RTC
|
||||
RTC0,
|
||||
RTC1,
|
||||
|
||||
// WDT
|
||||
WDT,
|
||||
|
||||
// NVMC
|
||||
NVMC,
|
||||
|
||||
// UARTE, TWI & SPI
|
||||
SERIAL0,
|
||||
SERIAL1,
|
||||
SERIAL2,
|
||||
SERIAL3,
|
||||
|
||||
// SAADC
|
||||
SAADC,
|
||||
|
||||
// RNG
|
||||
RNG,
|
||||
|
||||
// PWM
|
||||
PWM0,
|
||||
PWM1,
|
||||
PWM2,
|
||||
PWM3,
|
||||
|
||||
// TIMER
|
||||
TIMER0,
|
||||
TIMER1,
|
||||
TIMER2,
|
||||
|
||||
// GPIOTE
|
||||
GPIOTE_CH0,
|
||||
GPIOTE_CH1,
|
||||
GPIOTE_CH2,
|
||||
GPIOTE_CH3,
|
||||
GPIOTE_CH4,
|
||||
GPIOTE_CH5,
|
||||
GPIOTE_CH6,
|
||||
GPIOTE_CH7,
|
||||
|
||||
// PPI
|
||||
PPI_CH0,
|
||||
PPI_CH1,
|
||||
PPI_CH2,
|
||||
PPI_CH3,
|
||||
PPI_CH4,
|
||||
PPI_CH5,
|
||||
PPI_CH6,
|
||||
PPI_CH7,
|
||||
PPI_CH8,
|
||||
PPI_CH9,
|
||||
PPI_CH10,
|
||||
PPI_CH11,
|
||||
PPI_CH12,
|
||||
PPI_CH13,
|
||||
PPI_CH14,
|
||||
PPI_CH15,
|
||||
PPI_CH16,
|
||||
PPI_CH17,
|
||||
PPI_CH18,
|
||||
PPI_CH19,
|
||||
PPI_CH20,
|
||||
PPI_CH21,
|
||||
PPI_CH22,
|
||||
PPI_CH23,
|
||||
PPI_CH24,
|
||||
PPI_CH25,
|
||||
PPI_CH26,
|
||||
PPI_CH27,
|
||||
PPI_CH28,
|
||||
PPI_CH29,
|
||||
PPI_CH30,
|
||||
PPI_CH31,
|
||||
|
||||
PPI_GROUP0,
|
||||
PPI_GROUP1,
|
||||
PPI_GROUP2,
|
||||
PPI_GROUP3,
|
||||
PPI_GROUP4,
|
||||
PPI_GROUP5,
|
||||
|
||||
// GPIO port 0
|
||||
P0_00,
|
||||
P0_01,
|
||||
P0_02,
|
||||
P0_03,
|
||||
P0_04,
|
||||
P0_05,
|
||||
P0_06,
|
||||
P0_07,
|
||||
P0_08,
|
||||
P0_09,
|
||||
P0_10,
|
||||
P0_11,
|
||||
P0_12,
|
||||
P0_13,
|
||||
P0_14,
|
||||
P0_15,
|
||||
P0_16,
|
||||
P0_17,
|
||||
P0_18,
|
||||
P0_19,
|
||||
P0_20,
|
||||
P0_21,
|
||||
P0_22,
|
||||
P0_23,
|
||||
P0_24,
|
||||
P0_25,
|
||||
P0_26,
|
||||
P0_27,
|
||||
P0_28,
|
||||
P0_29,
|
||||
P0_30,
|
||||
P0_31,
|
||||
|
||||
// GPIO port 1
|
||||
P1_00,
|
||||
P1_01,
|
||||
P1_02,
|
||||
P1_03,
|
||||
P1_04,
|
||||
P1_05,
|
||||
P1_06,
|
||||
P1_07,
|
||||
P1_08,
|
||||
P1_09,
|
||||
P1_10,
|
||||
P1_11,
|
||||
P1_12,
|
||||
P1_13,
|
||||
P1_14,
|
||||
P1_15,
|
||||
|
||||
// Radio
|
||||
RADIO,
|
||||
|
||||
// EGU
|
||||
EGU0,
|
||||
}
|
||||
|
||||
impl_uarte!(SERIAL0, UARTE0, SERIAL0);
|
||||
impl_spim!(SERIAL0, SPIM0, SERIAL0);
|
||||
impl_spis!(SERIAL0, SPIS0, SERIAL0);
|
||||
impl_twim!(SERIAL0, TWIM0, SERIAL0);
|
||||
impl_twis!(SERIAL0, TWIS0, SERIAL0);
|
||||
|
||||
impl_timer!(TIMER0, TIMER0, TIMER0);
|
||||
impl_timer!(TIMER1, TIMER1, TIMER1);
|
||||
impl_timer!(TIMER2, TIMER2, TIMER2);
|
||||
|
||||
impl_rng!(RNG, RNG, RNG);
|
||||
|
||||
impl_pin!(P0_00, 0, 0);
|
||||
impl_pin!(P0_01, 0, 1);
|
||||
impl_pin!(P0_02, 0, 2);
|
||||
impl_pin!(P0_03, 0, 3);
|
||||
impl_pin!(P0_04, 0, 4);
|
||||
impl_pin!(P0_05, 0, 5);
|
||||
impl_pin!(P0_06, 0, 6);
|
||||
impl_pin!(P0_07, 0, 7);
|
||||
impl_pin!(P0_08, 0, 8);
|
||||
impl_pin!(P0_09, 0, 9);
|
||||
impl_pin!(P0_10, 0, 10);
|
||||
impl_pin!(P0_11, 0, 11);
|
||||
impl_pin!(P0_12, 0, 12);
|
||||
impl_pin!(P0_13, 0, 13);
|
||||
impl_pin!(P0_14, 0, 14);
|
||||
impl_pin!(P0_15, 0, 15);
|
||||
impl_pin!(P0_16, 0, 16);
|
||||
impl_pin!(P0_17, 0, 17);
|
||||
impl_pin!(P0_18, 0, 18);
|
||||
impl_pin!(P0_19, 0, 19);
|
||||
impl_pin!(P0_20, 0, 20);
|
||||
impl_pin!(P0_21, 0, 21);
|
||||
impl_pin!(P0_22, 0, 22);
|
||||
impl_pin!(P0_23, 0, 23);
|
||||
impl_pin!(P0_24, 0, 24);
|
||||
impl_pin!(P0_25, 0, 25);
|
||||
impl_pin!(P0_26, 0, 26);
|
||||
impl_pin!(P0_27, 0, 27);
|
||||
impl_pin!(P0_28, 0, 28);
|
||||
impl_pin!(P0_29, 0, 29);
|
||||
impl_pin!(P0_30, 0, 30);
|
||||
impl_pin!(P0_31, 0, 31);
|
||||
|
||||
impl_pin!(P1_00, 1, 0);
|
||||
impl_pin!(P1_01, 1, 1);
|
||||
impl_pin!(P1_02, 1, 2);
|
||||
impl_pin!(P1_03, 1, 3);
|
||||
impl_pin!(P1_04, 1, 4);
|
||||
impl_pin!(P1_05, 1, 5);
|
||||
impl_pin!(P1_06, 1, 6);
|
||||
impl_pin!(P1_07, 1, 7);
|
||||
impl_pin!(P1_08, 1, 8);
|
||||
impl_pin!(P1_09, 1, 9);
|
||||
impl_pin!(P1_10, 1, 10);
|
||||
impl_pin!(P1_11, 1, 11);
|
||||
impl_pin!(P1_12, 1, 12);
|
||||
impl_pin!(P1_13, 1, 13);
|
||||
impl_pin!(P1_14, 1, 14);
|
||||
impl_pin!(P1_15, 1, 15);
|
||||
|
||||
impl_ppi_channel!(PPI_CH0, 0 => configurable);
|
||||
impl_ppi_channel!(PPI_CH1, 1 => configurable);
|
||||
impl_ppi_channel!(PPI_CH2, 2 => configurable);
|
||||
impl_ppi_channel!(PPI_CH3, 3 => configurable);
|
||||
impl_ppi_channel!(PPI_CH4, 4 => configurable);
|
||||
impl_ppi_channel!(PPI_CH5, 5 => configurable);
|
||||
impl_ppi_channel!(PPI_CH6, 6 => configurable);
|
||||
impl_ppi_channel!(PPI_CH7, 7 => configurable);
|
||||
impl_ppi_channel!(PPI_CH8, 8 => configurable);
|
||||
impl_ppi_channel!(PPI_CH9, 9 => configurable);
|
||||
impl_ppi_channel!(PPI_CH10, 10 => configurable);
|
||||
impl_ppi_channel!(PPI_CH11, 11 => configurable);
|
||||
impl_ppi_channel!(PPI_CH12, 12 => configurable);
|
||||
impl_ppi_channel!(PPI_CH13, 13 => configurable);
|
||||
impl_ppi_channel!(PPI_CH14, 14 => configurable);
|
||||
impl_ppi_channel!(PPI_CH15, 15 => configurable);
|
||||
impl_ppi_channel!(PPI_CH16, 16 => configurable);
|
||||
impl_ppi_channel!(PPI_CH17, 17 => configurable);
|
||||
impl_ppi_channel!(PPI_CH18, 18 => configurable);
|
||||
impl_ppi_channel!(PPI_CH19, 19 => configurable);
|
||||
impl_ppi_channel!(PPI_CH20, 20 => configurable);
|
||||
impl_ppi_channel!(PPI_CH21, 21 => configurable);
|
||||
impl_ppi_channel!(PPI_CH22, 22 => configurable);
|
||||
impl_ppi_channel!(PPI_CH23, 23 => configurable);
|
||||
impl_ppi_channel!(PPI_CH24, 24 => configurable);
|
||||
impl_ppi_channel!(PPI_CH25, 25 => configurable);
|
||||
impl_ppi_channel!(PPI_CH26, 26 => configurable);
|
||||
impl_ppi_channel!(PPI_CH27, 27 => configurable);
|
||||
impl_ppi_channel!(PPI_CH28, 28 => configurable);
|
||||
impl_ppi_channel!(PPI_CH29, 29 => configurable);
|
||||
impl_ppi_channel!(PPI_CH30, 30 => configurable);
|
||||
impl_ppi_channel!(PPI_CH31, 31 => configurable);
|
||||
|
||||
impl_radio!(RADIO, RADIO, RADIO);
|
||||
|
||||
impl_egu!(EGU0, EGU0, EGU0);
|
||||
|
||||
embassy_hal_internal::interrupt_mod!(
|
||||
CLOCK_POWER,
|
||||
RADIO,
|
||||
RNG,
|
||||
GPIOTE,
|
||||
WDT,
|
||||
TIMER0,
|
||||
ECB,
|
||||
AAR_CCM,
|
||||
TEMP,
|
||||
RTC0,
|
||||
IPC,
|
||||
SERIAL0,
|
||||
EGU0,
|
||||
RTC1,
|
||||
TIMER1,
|
||||
TIMER2,
|
||||
SWI0,
|
||||
SWI1,
|
||||
SWI2,
|
||||
SWI3,
|
||||
);
|
||||
+430
@@ -0,0 +1,430 @@
|
||||
/// Peripheral Access Crate
|
||||
#[allow(unused_imports)]
|
||||
#[rustfmt::skip]
|
||||
pub mod pac {
|
||||
// The nRF9120 has a secure and non-secure (NS) mode.
|
||||
// To avoid cfg spam, we remove _ns or _s suffixes here.
|
||||
|
||||
pub use nrf9120_pac::NVIC_PRIO_BITS;
|
||||
|
||||
#[cfg(feature="rt")]
|
||||
#[doc(no_inline)]
|
||||
pub use nrf9120_pac::interrupt;
|
||||
|
||||
#[doc(no_inline)]
|
||||
pub use nrf9120_pac::{
|
||||
Interrupt,
|
||||
|
||||
cc_host_rgf_s as cc_host_rgf,
|
||||
clock_ns as clock,
|
||||
cryptocell_s as cryptocell,
|
||||
ctrl_ap_peri_s as ctrl_ap_peri,
|
||||
dppic_ns as dppic,
|
||||
egu0_ns as egu0,
|
||||
ficr_s as ficr,
|
||||
fpu_ns as fpu,
|
||||
gpiote0_s as gpiote,
|
||||
i2s_ns as i2s,
|
||||
ipc_ns as ipc,
|
||||
kmu_ns as kmu,
|
||||
nvmc_ns as nvmc,
|
||||
p0_ns as p0,
|
||||
pdm_ns as pdm,
|
||||
power_ns as power,
|
||||
pwm0_ns as pwm0,
|
||||
regulators_ns as regulators,
|
||||
rtc0_ns as rtc0,
|
||||
saadc_ns as saadc,
|
||||
spim0_ns as spim0,
|
||||
spis0_ns as spis0,
|
||||
spu_s as spu,
|
||||
tad_s as tad,
|
||||
timer0_ns as timer0,
|
||||
twim0_ns as twim0,
|
||||
twis0_ns as twis0,
|
||||
uarte0_ns as uarte0,
|
||||
uicr_s as uicr,
|
||||
vmc_ns as vmc,
|
||||
wdt_ns as wdt,
|
||||
};
|
||||
|
||||
/// Non-Secure mode (NS) peripherals
|
||||
pub mod ns {
|
||||
#[doc(no_inline)]
|
||||
pub use nrf9120_pac::{
|
||||
CLOCK_NS as CLOCK,
|
||||
DPPIC_NS as DPPIC,
|
||||
EGU0_NS as EGU0,
|
||||
EGU1_NS as EGU1,
|
||||
EGU2_NS as EGU2,
|
||||
EGU3_NS as EGU3,
|
||||
EGU4_NS as EGU4,
|
||||
EGU5_NS as EGU5,
|
||||
FPU_NS as FPU,
|
||||
GPIOTE1_NS as GPIOTE1,
|
||||
I2S_NS as I2S,
|
||||
IPC_NS as IPC,
|
||||
KMU_NS as KMU,
|
||||
NVMC_NS as NVMC,
|
||||
P0_NS as P0,
|
||||
PDM_NS as PDM,
|
||||
POWER_NS as POWER,
|
||||
PWM0_NS as PWM0,
|
||||
PWM1_NS as PWM1,
|
||||
PWM2_NS as PWM2,
|
||||
PWM3_NS as PWM3,
|
||||
REGULATORS_NS as REGULATORS,
|
||||
RTC0_NS as RTC0,
|
||||
RTC1_NS as RTC1,
|
||||
SAADC_NS as SAADC,
|
||||
SPIM0_NS as SPIM0,
|
||||
SPIM1_NS as SPIM1,
|
||||
SPIM2_NS as SPIM2,
|
||||
SPIM3_NS as SPIM3,
|
||||
SPIS0_NS as SPIS0,
|
||||
SPIS1_NS as SPIS1,
|
||||
SPIS2_NS as SPIS2,
|
||||
SPIS3_NS as SPIS3,
|
||||
TIMER0_NS as TIMER0,
|
||||
TIMER1_NS as TIMER1,
|
||||
TIMER2_NS as TIMER2,
|
||||
TWIM0_NS as TWIM0,
|
||||
TWIM1_NS as TWIM1,
|
||||
TWIM2_NS as TWIM2,
|
||||
TWIM3_NS as TWIM3,
|
||||
TWIS0_NS as TWIS0,
|
||||
TWIS1_NS as TWIS1,
|
||||
TWIS2_NS as TWIS2,
|
||||
TWIS3_NS as TWIS3,
|
||||
UARTE0_NS as UARTE0,
|
||||
UARTE1_NS as UARTE1,
|
||||
UARTE2_NS as UARTE2,
|
||||
UARTE3_NS as UARTE3,
|
||||
VMC_NS as VMC,
|
||||
WDT_NS as WDT,
|
||||
};
|
||||
}
|
||||
|
||||
/// Secure mode (S) peripherals
|
||||
pub mod s {
|
||||
#[doc(no_inline)]
|
||||
pub use nrf9120_pac::{
|
||||
CC_HOST_RGF_S as CC_HOST_RGF,
|
||||
CLOCK_S as CLOCK,
|
||||
CRYPTOCELL_S as CRYPTOCELL,
|
||||
CTRL_AP_PERI_S as CTRL_AP_PERI,
|
||||
DPPIC_S as DPPIC,
|
||||
EGU0_S as EGU0,
|
||||
EGU1_S as EGU1,
|
||||
EGU2_S as EGU2,
|
||||
EGU3_S as EGU3,
|
||||
EGU4_S as EGU4,
|
||||
EGU5_S as EGU5,
|
||||
FICR_S as FICR,
|
||||
FPU as FPU,
|
||||
GPIOTE0_S as GPIOTE0,
|
||||
I2S_S as I2S,
|
||||
IPC_S as IPC,
|
||||
KMU_S as KMU,
|
||||
NVMC_S as NVMC,
|
||||
P0_S as P0,
|
||||
PDM_S as PDM,
|
||||
POWER_S as POWER,
|
||||
PWM0_S as PWM0,
|
||||
PWM1_S as PWM1,
|
||||
PWM2_S as PWM2,
|
||||
PWM3_S as PWM3,
|
||||
REGULATORS_S as REGULATORS,
|
||||
RTC0_S as RTC0,
|
||||
RTC1_S as RTC1,
|
||||
SAADC_S as SAADC,
|
||||
SPIM0_S as SPIM0,
|
||||
SPIM1_S as SPIM1,
|
||||
SPIM2_S as SPIM2,
|
||||
SPIM3_S as SPIM3,
|
||||
SPIS0_S as SPIS0,
|
||||
SPIS1_S as SPIS1,
|
||||
SPIS2_S as SPIS2,
|
||||
SPIS3_S as SPIS3,
|
||||
SPU_S as SPU,
|
||||
TAD_S as TAD,
|
||||
TIMER0_S as TIMER0,
|
||||
TIMER1_S as TIMER1,
|
||||
TIMER2_S as TIMER2,
|
||||
TWIM0_S as TWIM0,
|
||||
TWIM1_S as TWIM1,
|
||||
TWIM2_S as TWIM2,
|
||||
TWIM3_S as TWIM3,
|
||||
TWIS0_S as TWIS0,
|
||||
TWIS1_S as TWIS1,
|
||||
TWIS2_S as TWIS2,
|
||||
TWIS3_S as TWIS3,
|
||||
UARTE0_S as UARTE0,
|
||||
UARTE1_S as UARTE1,
|
||||
UARTE2_S as UARTE2,
|
||||
UARTE3_S as UARTE3,
|
||||
UICR_S as UICR,
|
||||
VMC_S as VMC,
|
||||
WDT_S as WDT,
|
||||
};
|
||||
}
|
||||
|
||||
#[cfg(feature = "_ns")]
|
||||
pub use ns::*;
|
||||
#[cfg(feature = "_s")]
|
||||
pub use s::*;
|
||||
}
|
||||
|
||||
/// The maximum buffer size that the EasyDMA can send/recv in one operation.
|
||||
pub const EASY_DMA_SIZE: usize = (1 << 13) - 1;
|
||||
pub const FORCE_COPY_BUFFER_SIZE: usize = 1024;
|
||||
|
||||
pub const FLASH_SIZE: usize = 1024 * 1024;
|
||||
|
||||
embassy_hal_internal::peripherals! {
|
||||
// RTC
|
||||
RTC0,
|
||||
RTC1,
|
||||
|
||||
// WDT
|
||||
WDT,
|
||||
|
||||
// NVMC
|
||||
NVMC,
|
||||
|
||||
// UARTE, TWI & SPI
|
||||
SERIAL0,
|
||||
SERIAL1,
|
||||
SERIAL2,
|
||||
SERIAL3,
|
||||
|
||||
// SAADC
|
||||
SAADC,
|
||||
|
||||
// PWM
|
||||
PWM0,
|
||||
PWM1,
|
||||
PWM2,
|
||||
PWM3,
|
||||
|
||||
// TIMER
|
||||
TIMER0,
|
||||
TIMER1,
|
||||
TIMER2,
|
||||
|
||||
// GPIOTE
|
||||
GPIOTE_CH0,
|
||||
GPIOTE_CH1,
|
||||
GPIOTE_CH2,
|
||||
GPIOTE_CH3,
|
||||
GPIOTE_CH4,
|
||||
GPIOTE_CH5,
|
||||
GPIOTE_CH6,
|
||||
GPIOTE_CH7,
|
||||
|
||||
// PPI
|
||||
PPI_CH0,
|
||||
PPI_CH1,
|
||||
PPI_CH2,
|
||||
PPI_CH3,
|
||||
PPI_CH4,
|
||||
PPI_CH5,
|
||||
PPI_CH6,
|
||||
PPI_CH7,
|
||||
PPI_CH8,
|
||||
PPI_CH9,
|
||||
PPI_CH10,
|
||||
PPI_CH11,
|
||||
PPI_CH12,
|
||||
PPI_CH13,
|
||||
PPI_CH14,
|
||||
PPI_CH15,
|
||||
|
||||
PPI_GROUP0,
|
||||
PPI_GROUP1,
|
||||
PPI_GROUP2,
|
||||
PPI_GROUP3,
|
||||
PPI_GROUP4,
|
||||
PPI_GROUP5,
|
||||
|
||||
// GPIO port 0
|
||||
P0_00,
|
||||
P0_01,
|
||||
P0_02,
|
||||
P0_03,
|
||||
P0_04,
|
||||
P0_05,
|
||||
P0_06,
|
||||
P0_07,
|
||||
P0_08,
|
||||
P0_09,
|
||||
P0_10,
|
||||
P0_11,
|
||||
P0_12,
|
||||
P0_13,
|
||||
P0_14,
|
||||
P0_15,
|
||||
P0_16,
|
||||
P0_17,
|
||||
P0_18,
|
||||
P0_19,
|
||||
P0_20,
|
||||
P0_21,
|
||||
P0_22,
|
||||
P0_23,
|
||||
P0_24,
|
||||
P0_25,
|
||||
P0_26,
|
||||
P0_27,
|
||||
P0_28,
|
||||
P0_29,
|
||||
P0_30,
|
||||
P0_31,
|
||||
|
||||
// PDM
|
||||
PDM,
|
||||
|
||||
// EGU
|
||||
EGU0,
|
||||
EGU1,
|
||||
EGU2,
|
||||
EGU3,
|
||||
EGU4,
|
||||
EGU5,
|
||||
}
|
||||
|
||||
impl_uarte!(SERIAL0, UARTE0, SPIM0_SPIS0_TWIM0_TWIS0_UARTE0);
|
||||
impl_uarte!(SERIAL1, UARTE1, SPIM1_SPIS1_TWIM1_TWIS1_UARTE1);
|
||||
impl_uarte!(SERIAL2, UARTE2, SPIM2_SPIS2_TWIM2_TWIS2_UARTE2);
|
||||
impl_uarte!(SERIAL3, UARTE3, SPIM3_SPIS3_TWIM3_TWIS3_UARTE3);
|
||||
|
||||
impl_spim!(SERIAL0, SPIM0, SPIM0_SPIS0_TWIM0_TWIS0_UARTE0);
|
||||
impl_spim!(SERIAL1, SPIM1, SPIM1_SPIS1_TWIM1_TWIS1_UARTE1);
|
||||
impl_spim!(SERIAL2, SPIM2, SPIM2_SPIS2_TWIM2_TWIS2_UARTE2);
|
||||
impl_spim!(SERIAL3, SPIM3, SPIM3_SPIS3_TWIM3_TWIS3_UARTE3);
|
||||
|
||||
impl_spis!(SERIAL0, SPIS0, SPIM0_SPIS0_TWIM0_TWIS0_UARTE0);
|
||||
impl_spis!(SERIAL1, SPIS1, SPIM1_SPIS1_TWIM1_TWIS1_UARTE1);
|
||||
impl_spis!(SERIAL2, SPIS2, SPIM2_SPIS2_TWIM2_TWIS2_UARTE2);
|
||||
impl_spis!(SERIAL3, SPIS3, SPIM3_SPIS3_TWIM3_TWIS3_UARTE3);
|
||||
|
||||
impl_twim!(SERIAL0, TWIM0, SPIM0_SPIS0_TWIM0_TWIS0_UARTE0);
|
||||
impl_twim!(SERIAL1, TWIM1, SPIM1_SPIS1_TWIM1_TWIS1_UARTE1);
|
||||
impl_twim!(SERIAL2, TWIM2, SPIM2_SPIS2_TWIM2_TWIS2_UARTE2);
|
||||
impl_twim!(SERIAL3, TWIM3, SPIM3_SPIS3_TWIM3_TWIS3_UARTE3);
|
||||
|
||||
impl_twis!(SERIAL0, TWIS0, SPIM0_SPIS0_TWIM0_TWIS0_UARTE0);
|
||||
impl_twis!(SERIAL1, TWIS1, SPIM1_SPIS1_TWIM1_TWIS1_UARTE1);
|
||||
impl_twis!(SERIAL2, TWIS2, SPIM2_SPIS2_TWIM2_TWIS2_UARTE2);
|
||||
impl_twis!(SERIAL3, TWIS3, SPIM3_SPIS3_TWIM3_TWIS3_UARTE3);
|
||||
|
||||
impl_pwm!(PWM0, PWM0, PWM0);
|
||||
impl_pwm!(PWM1, PWM1, PWM1);
|
||||
impl_pwm!(PWM2, PWM2, PWM2);
|
||||
impl_pwm!(PWM3, PWM3, PWM3);
|
||||
|
||||
impl_pdm!(PDM, PDM, PDM);
|
||||
|
||||
impl_timer!(TIMER0, TIMER0, TIMER0);
|
||||
impl_timer!(TIMER1, TIMER1, TIMER1);
|
||||
impl_timer!(TIMER2, TIMER2, TIMER2);
|
||||
|
||||
impl_pin!(P0_00, 0, 0);
|
||||
impl_pin!(P0_01, 0, 1);
|
||||
impl_pin!(P0_02, 0, 2);
|
||||
impl_pin!(P0_03, 0, 3);
|
||||
impl_pin!(P0_04, 0, 4);
|
||||
impl_pin!(P0_05, 0, 5);
|
||||
impl_pin!(P0_06, 0, 6);
|
||||
impl_pin!(P0_07, 0, 7);
|
||||
impl_pin!(P0_08, 0, 8);
|
||||
impl_pin!(P0_09, 0, 9);
|
||||
impl_pin!(P0_10, 0, 10);
|
||||
impl_pin!(P0_11, 0, 11);
|
||||
impl_pin!(P0_12, 0, 12);
|
||||
impl_pin!(P0_13, 0, 13);
|
||||
impl_pin!(P0_14, 0, 14);
|
||||
impl_pin!(P0_15, 0, 15);
|
||||
impl_pin!(P0_16, 0, 16);
|
||||
impl_pin!(P0_17, 0, 17);
|
||||
impl_pin!(P0_18, 0, 18);
|
||||
impl_pin!(P0_19, 0, 19);
|
||||
impl_pin!(P0_20, 0, 20);
|
||||
impl_pin!(P0_21, 0, 21);
|
||||
impl_pin!(P0_22, 0, 22);
|
||||
impl_pin!(P0_23, 0, 23);
|
||||
impl_pin!(P0_24, 0, 24);
|
||||
impl_pin!(P0_25, 0, 25);
|
||||
impl_pin!(P0_26, 0, 26);
|
||||
impl_pin!(P0_27, 0, 27);
|
||||
impl_pin!(P0_28, 0, 28);
|
||||
impl_pin!(P0_29, 0, 29);
|
||||
impl_pin!(P0_30, 0, 30);
|
||||
impl_pin!(P0_31, 0, 31);
|
||||
|
||||
impl_ppi_channel!(PPI_CH0, 0 => configurable);
|
||||
impl_ppi_channel!(PPI_CH1, 1 => configurable);
|
||||
impl_ppi_channel!(PPI_CH2, 2 => configurable);
|
||||
impl_ppi_channel!(PPI_CH3, 3 => configurable);
|
||||
impl_ppi_channel!(PPI_CH4, 4 => configurable);
|
||||
impl_ppi_channel!(PPI_CH5, 5 => configurable);
|
||||
impl_ppi_channel!(PPI_CH6, 6 => configurable);
|
||||
impl_ppi_channel!(PPI_CH7, 7 => configurable);
|
||||
impl_ppi_channel!(PPI_CH8, 8 => configurable);
|
||||
impl_ppi_channel!(PPI_CH9, 9 => configurable);
|
||||
impl_ppi_channel!(PPI_CH10, 10 => configurable);
|
||||
impl_ppi_channel!(PPI_CH11, 11 => configurable);
|
||||
impl_ppi_channel!(PPI_CH12, 12 => configurable);
|
||||
impl_ppi_channel!(PPI_CH13, 13 => configurable);
|
||||
impl_ppi_channel!(PPI_CH14, 14 => configurable);
|
||||
impl_ppi_channel!(PPI_CH15, 15 => configurable);
|
||||
|
||||
impl_saadc_input!(P0_13, ANALOG_INPUT0);
|
||||
impl_saadc_input!(P0_14, ANALOG_INPUT1);
|
||||
impl_saadc_input!(P0_15, ANALOG_INPUT2);
|
||||
impl_saadc_input!(P0_16, ANALOG_INPUT3);
|
||||
impl_saadc_input!(P0_17, ANALOG_INPUT4);
|
||||
impl_saadc_input!(P0_18, ANALOG_INPUT5);
|
||||
impl_saadc_input!(P0_19, ANALOG_INPUT6);
|
||||
impl_saadc_input!(P0_20, ANALOG_INPUT7);
|
||||
|
||||
impl_egu!(EGU0, EGU0, EGU0);
|
||||
impl_egu!(EGU1, EGU1, EGU1);
|
||||
impl_egu!(EGU2, EGU2, EGU2);
|
||||
impl_egu!(EGU3, EGU3, EGU3);
|
||||
impl_egu!(EGU4, EGU4, EGU4);
|
||||
impl_egu!(EGU5, EGU5, EGU5);
|
||||
|
||||
embassy_hal_internal::interrupt_mod!(
|
||||
SPU,
|
||||
CLOCK_POWER,
|
||||
SPIM0_SPIS0_TWIM0_TWIS0_UARTE0,
|
||||
SPIM1_SPIS1_TWIM1_TWIS1_UARTE1,
|
||||
SPIM2_SPIS2_TWIM2_TWIS2_UARTE2,
|
||||
SPIM3_SPIS3_TWIM3_TWIS3_UARTE3,
|
||||
GPIOTE0,
|
||||
SAADC,
|
||||
TIMER0,
|
||||
TIMER1,
|
||||
TIMER2,
|
||||
RTC0,
|
||||
RTC1,
|
||||
WDT,
|
||||
EGU0,
|
||||
EGU1,
|
||||
EGU2,
|
||||
EGU3,
|
||||
EGU4,
|
||||
EGU5,
|
||||
PWM0,
|
||||
PWM1,
|
||||
PWM2,
|
||||
PDM,
|
||||
PWM3,
|
||||
I2S,
|
||||
IPC,
|
||||
FPU,
|
||||
GPIOTE1,
|
||||
KMU,
|
||||
CRYPTOCELL,
|
||||
);
|
||||
+430
@@ -0,0 +1,430 @@
|
||||
/// Peripheral Access Crate
|
||||
#[allow(unused_imports)]
|
||||
#[rustfmt::skip]
|
||||
pub mod pac {
|
||||
// The nRF9160 has a secure and non-secure (NS) mode.
|
||||
// To avoid cfg spam, we remove _ns or _s suffixes here.
|
||||
|
||||
pub use nrf9160_pac::NVIC_PRIO_BITS;
|
||||
|
||||
#[cfg(feature="rt")]
|
||||
#[doc(no_inline)]
|
||||
pub use nrf9160_pac::interrupt;
|
||||
|
||||
#[doc(no_inline)]
|
||||
pub use nrf9160_pac::{
|
||||
Interrupt,
|
||||
|
||||
cc_host_rgf_s as cc_host_rgf,
|
||||
clock_ns as clock,
|
||||
cryptocell_s as cryptocell,
|
||||
ctrl_ap_peri_s as ctrl_ap_peri,
|
||||
dppic_ns as dppic,
|
||||
egu0_ns as egu0,
|
||||
ficr_s as ficr,
|
||||
fpu_ns as fpu,
|
||||
gpiote0_s as gpiote,
|
||||
i2s_ns as i2s,
|
||||
ipc_ns as ipc,
|
||||
kmu_ns as kmu,
|
||||
nvmc_ns as nvmc,
|
||||
p0_ns as p0,
|
||||
pdm_ns as pdm,
|
||||
power_ns as power,
|
||||
pwm0_ns as pwm0,
|
||||
regulators_ns as regulators,
|
||||
rtc0_ns as rtc0,
|
||||
saadc_ns as saadc,
|
||||
spim0_ns as spim0,
|
||||
spis0_ns as spis0,
|
||||
spu_s as spu,
|
||||
tad_s as tad,
|
||||
timer0_ns as timer0,
|
||||
twim0_ns as twim0,
|
||||
twis0_ns as twis0,
|
||||
uarte0_ns as uarte0,
|
||||
uicr_s as uicr,
|
||||
vmc_ns as vmc,
|
||||
wdt_ns as wdt,
|
||||
};
|
||||
|
||||
/// Non-Secure mode (NS) peripherals
|
||||
pub mod ns {
|
||||
#[doc(no_inline)]
|
||||
pub use nrf9160_pac::{
|
||||
CLOCK_NS as CLOCK,
|
||||
DPPIC_NS as DPPIC,
|
||||
EGU0_NS as EGU0,
|
||||
EGU1_NS as EGU1,
|
||||
EGU2_NS as EGU2,
|
||||
EGU3_NS as EGU3,
|
||||
EGU4_NS as EGU4,
|
||||
EGU5_NS as EGU5,
|
||||
FPU_NS as FPU,
|
||||
GPIOTE1_NS as GPIOTE1,
|
||||
I2S_NS as I2S,
|
||||
IPC_NS as IPC,
|
||||
KMU_NS as KMU,
|
||||
NVMC_NS as NVMC,
|
||||
P0_NS as P0,
|
||||
PDM_NS as PDM,
|
||||
POWER_NS as POWER,
|
||||
PWM0_NS as PWM0,
|
||||
PWM1_NS as PWM1,
|
||||
PWM2_NS as PWM2,
|
||||
PWM3_NS as PWM3,
|
||||
REGULATORS_NS as REGULATORS,
|
||||
RTC0_NS as RTC0,
|
||||
RTC1_NS as RTC1,
|
||||
SAADC_NS as SAADC,
|
||||
SPIM0_NS as SPIM0,
|
||||
SPIM1_NS as SPIM1,
|
||||
SPIM2_NS as SPIM2,
|
||||
SPIM3_NS as SPIM3,
|
||||
SPIS0_NS as SPIS0,
|
||||
SPIS1_NS as SPIS1,
|
||||
SPIS2_NS as SPIS2,
|
||||
SPIS3_NS as SPIS3,
|
||||
TIMER0_NS as TIMER0,
|
||||
TIMER1_NS as TIMER1,
|
||||
TIMER2_NS as TIMER2,
|
||||
TWIM0_NS as TWIM0,
|
||||
TWIM1_NS as TWIM1,
|
||||
TWIM2_NS as TWIM2,
|
||||
TWIM3_NS as TWIM3,
|
||||
TWIS0_NS as TWIS0,
|
||||
TWIS1_NS as TWIS1,
|
||||
TWIS2_NS as TWIS2,
|
||||
TWIS3_NS as TWIS3,
|
||||
UARTE0_NS as UARTE0,
|
||||
UARTE1_NS as UARTE1,
|
||||
UARTE2_NS as UARTE2,
|
||||
UARTE3_NS as UARTE3,
|
||||
VMC_NS as VMC,
|
||||
WDT_NS as WDT,
|
||||
};
|
||||
}
|
||||
|
||||
/// Secure mode (S) peripherals
|
||||
pub mod s {
|
||||
#[doc(no_inline)]
|
||||
pub use nrf9160_pac::{
|
||||
CC_HOST_RGF_S as CC_HOST_RGF,
|
||||
CLOCK_S as CLOCK,
|
||||
CRYPTOCELL_S as CRYPTOCELL,
|
||||
CTRL_AP_PERI_S as CTRL_AP_PERI,
|
||||
DPPIC_S as DPPIC,
|
||||
EGU0_S as EGU0,
|
||||
EGU1_S as EGU1,
|
||||
EGU2_S as EGU2,
|
||||
EGU3_S as EGU3,
|
||||
EGU4_S as EGU4,
|
||||
EGU5_S as EGU5,
|
||||
FICR_S as FICR,
|
||||
FPU_S as FPU,
|
||||
GPIOTE0_S as GPIOTE0,
|
||||
I2S_S as I2S,
|
||||
IPC_S as IPC,
|
||||
KMU_S as KMU,
|
||||
NVMC_S as NVMC,
|
||||
P0_S as P0,
|
||||
PDM_S as PDM,
|
||||
POWER_S as POWER,
|
||||
PWM0_S as PWM0,
|
||||
PWM1_S as PWM1,
|
||||
PWM2_S as PWM2,
|
||||
PWM3_S as PWM3,
|
||||
REGULATORS_S as REGULATORS,
|
||||
RTC0_S as RTC0,
|
||||
RTC1_S as RTC1,
|
||||
SAADC_S as SAADC,
|
||||
SPIM0_S as SPIM0,
|
||||
SPIM1_S as SPIM1,
|
||||
SPIM2_S as SPIM2,
|
||||
SPIM3_S as SPIM3,
|
||||
SPIS0_S as SPIS0,
|
||||
SPIS1_S as SPIS1,
|
||||
SPIS2_S as SPIS2,
|
||||
SPIS3_S as SPIS3,
|
||||
SPU_S as SPU,
|
||||
TAD_S as TAD,
|
||||
TIMER0_S as TIMER0,
|
||||
TIMER1_S as TIMER1,
|
||||
TIMER2_S as TIMER2,
|
||||
TWIM0_S as TWIM0,
|
||||
TWIM1_S as TWIM1,
|
||||
TWIM2_S as TWIM2,
|
||||
TWIM3_S as TWIM3,
|
||||
TWIS0_S as TWIS0,
|
||||
TWIS1_S as TWIS1,
|
||||
TWIS2_S as TWIS2,
|
||||
TWIS3_S as TWIS3,
|
||||
UARTE0_S as UARTE0,
|
||||
UARTE1_S as UARTE1,
|
||||
UARTE2_S as UARTE2,
|
||||
UARTE3_S as UARTE3,
|
||||
UICR_S as UICR,
|
||||
VMC_S as VMC,
|
||||
WDT_S as WDT,
|
||||
};
|
||||
}
|
||||
|
||||
#[cfg(feature = "_ns")]
|
||||
pub use ns::*;
|
||||
#[cfg(feature = "_s")]
|
||||
pub use s::*;
|
||||
}
|
||||
|
||||
/// The maximum buffer size that the EasyDMA can send/recv in one operation.
|
||||
pub const EASY_DMA_SIZE: usize = (1 << 13) - 1;
|
||||
pub const FORCE_COPY_BUFFER_SIZE: usize = 1024;
|
||||
|
||||
pub const FLASH_SIZE: usize = 1024 * 1024;
|
||||
|
||||
embassy_hal_internal::peripherals! {
|
||||
// RTC
|
||||
RTC0,
|
||||
RTC1,
|
||||
|
||||
// WDT
|
||||
WDT,
|
||||
|
||||
// NVMC
|
||||
NVMC,
|
||||
|
||||
// UARTE, TWI & SPI
|
||||
SERIAL0,
|
||||
SERIAL1,
|
||||
SERIAL2,
|
||||
SERIAL3,
|
||||
|
||||
// SAADC
|
||||
SAADC,
|
||||
|
||||
// PWM
|
||||
PWM0,
|
||||
PWM1,
|
||||
PWM2,
|
||||
PWM3,
|
||||
|
||||
// TIMER
|
||||
TIMER0,
|
||||
TIMER1,
|
||||
TIMER2,
|
||||
|
||||
// GPIOTE
|
||||
GPIOTE_CH0,
|
||||
GPIOTE_CH1,
|
||||
GPIOTE_CH2,
|
||||
GPIOTE_CH3,
|
||||
GPIOTE_CH4,
|
||||
GPIOTE_CH5,
|
||||
GPIOTE_CH6,
|
||||
GPIOTE_CH7,
|
||||
|
||||
// PPI
|
||||
PPI_CH0,
|
||||
PPI_CH1,
|
||||
PPI_CH2,
|
||||
PPI_CH3,
|
||||
PPI_CH4,
|
||||
PPI_CH5,
|
||||
PPI_CH6,
|
||||
PPI_CH7,
|
||||
PPI_CH8,
|
||||
PPI_CH9,
|
||||
PPI_CH10,
|
||||
PPI_CH11,
|
||||
PPI_CH12,
|
||||
PPI_CH13,
|
||||
PPI_CH14,
|
||||
PPI_CH15,
|
||||
|
||||
PPI_GROUP0,
|
||||
PPI_GROUP1,
|
||||
PPI_GROUP2,
|
||||
PPI_GROUP3,
|
||||
PPI_GROUP4,
|
||||
PPI_GROUP5,
|
||||
|
||||
// GPIO port 0
|
||||
P0_00,
|
||||
P0_01,
|
||||
P0_02,
|
||||
P0_03,
|
||||
P0_04,
|
||||
P0_05,
|
||||
P0_06,
|
||||
P0_07,
|
||||
P0_08,
|
||||
P0_09,
|
||||
P0_10,
|
||||
P0_11,
|
||||
P0_12,
|
||||
P0_13,
|
||||
P0_14,
|
||||
P0_15,
|
||||
P0_16,
|
||||
P0_17,
|
||||
P0_18,
|
||||
P0_19,
|
||||
P0_20,
|
||||
P0_21,
|
||||
P0_22,
|
||||
P0_23,
|
||||
P0_24,
|
||||
P0_25,
|
||||
P0_26,
|
||||
P0_27,
|
||||
P0_28,
|
||||
P0_29,
|
||||
P0_30,
|
||||
P0_31,
|
||||
|
||||
// PDM
|
||||
PDM,
|
||||
|
||||
// EGU
|
||||
EGU0,
|
||||
EGU1,
|
||||
EGU2,
|
||||
EGU3,
|
||||
EGU4,
|
||||
EGU5,
|
||||
}
|
||||
|
||||
impl_uarte!(SERIAL0, UARTE0, UARTE0_SPIM0_SPIS0_TWIM0_TWIS0);
|
||||
impl_uarte!(SERIAL1, UARTE1, UARTE1_SPIM1_SPIS1_TWIM1_TWIS1);
|
||||
impl_uarte!(SERIAL2, UARTE2, UARTE2_SPIM2_SPIS2_TWIM2_TWIS2);
|
||||
impl_uarte!(SERIAL3, UARTE3, UARTE3_SPIM3_SPIS3_TWIM3_TWIS3);
|
||||
|
||||
impl_spim!(SERIAL0, SPIM0, UARTE0_SPIM0_SPIS0_TWIM0_TWIS0);
|
||||
impl_spim!(SERIAL1, SPIM1, UARTE1_SPIM1_SPIS1_TWIM1_TWIS1);
|
||||
impl_spim!(SERIAL2, SPIM2, UARTE2_SPIM2_SPIS2_TWIM2_TWIS2);
|
||||
impl_spim!(SERIAL3, SPIM3, UARTE3_SPIM3_SPIS3_TWIM3_TWIS3);
|
||||
|
||||
impl_spis!(SERIAL0, SPIS0, UARTE0_SPIM0_SPIS0_TWIM0_TWIS0);
|
||||
impl_spis!(SERIAL1, SPIS1, UARTE1_SPIM1_SPIS1_TWIM1_TWIS1);
|
||||
impl_spis!(SERIAL2, SPIS2, UARTE2_SPIM2_SPIS2_TWIM2_TWIS2);
|
||||
impl_spis!(SERIAL3, SPIS3, UARTE3_SPIM3_SPIS3_TWIM3_TWIS3);
|
||||
|
||||
impl_twim!(SERIAL0, TWIM0, UARTE0_SPIM0_SPIS0_TWIM0_TWIS0);
|
||||
impl_twim!(SERIAL1, TWIM1, UARTE1_SPIM1_SPIS1_TWIM1_TWIS1);
|
||||
impl_twim!(SERIAL2, TWIM2, UARTE2_SPIM2_SPIS2_TWIM2_TWIS2);
|
||||
impl_twim!(SERIAL3, TWIM3, UARTE3_SPIM3_SPIS3_TWIM3_TWIS3);
|
||||
|
||||
impl_twis!(SERIAL0, TWIS0, UARTE0_SPIM0_SPIS0_TWIM0_TWIS0);
|
||||
impl_twis!(SERIAL1, TWIS1, UARTE1_SPIM1_SPIS1_TWIM1_TWIS1);
|
||||
impl_twis!(SERIAL2, TWIS2, UARTE2_SPIM2_SPIS2_TWIM2_TWIS2);
|
||||
impl_twis!(SERIAL3, TWIS3, UARTE3_SPIM3_SPIS3_TWIM3_TWIS3);
|
||||
|
||||
impl_pwm!(PWM0, PWM0, PWM0);
|
||||
impl_pwm!(PWM1, PWM1, PWM1);
|
||||
impl_pwm!(PWM2, PWM2, PWM2);
|
||||
impl_pwm!(PWM3, PWM3, PWM3);
|
||||
|
||||
impl_pdm!(PDM, PDM, PDM);
|
||||
|
||||
impl_timer!(TIMER0, TIMER0, TIMER0);
|
||||
impl_timer!(TIMER1, TIMER1, TIMER1);
|
||||
impl_timer!(TIMER2, TIMER2, TIMER2);
|
||||
|
||||
impl_pin!(P0_00, 0, 0);
|
||||
impl_pin!(P0_01, 0, 1);
|
||||
impl_pin!(P0_02, 0, 2);
|
||||
impl_pin!(P0_03, 0, 3);
|
||||
impl_pin!(P0_04, 0, 4);
|
||||
impl_pin!(P0_05, 0, 5);
|
||||
impl_pin!(P0_06, 0, 6);
|
||||
impl_pin!(P0_07, 0, 7);
|
||||
impl_pin!(P0_08, 0, 8);
|
||||
impl_pin!(P0_09, 0, 9);
|
||||
impl_pin!(P0_10, 0, 10);
|
||||
impl_pin!(P0_11, 0, 11);
|
||||
impl_pin!(P0_12, 0, 12);
|
||||
impl_pin!(P0_13, 0, 13);
|
||||
impl_pin!(P0_14, 0, 14);
|
||||
impl_pin!(P0_15, 0, 15);
|
||||
impl_pin!(P0_16, 0, 16);
|
||||
impl_pin!(P0_17, 0, 17);
|
||||
impl_pin!(P0_18, 0, 18);
|
||||
impl_pin!(P0_19, 0, 19);
|
||||
impl_pin!(P0_20, 0, 20);
|
||||
impl_pin!(P0_21, 0, 21);
|
||||
impl_pin!(P0_22, 0, 22);
|
||||
impl_pin!(P0_23, 0, 23);
|
||||
impl_pin!(P0_24, 0, 24);
|
||||
impl_pin!(P0_25, 0, 25);
|
||||
impl_pin!(P0_26, 0, 26);
|
||||
impl_pin!(P0_27, 0, 27);
|
||||
impl_pin!(P0_28, 0, 28);
|
||||
impl_pin!(P0_29, 0, 29);
|
||||
impl_pin!(P0_30, 0, 30);
|
||||
impl_pin!(P0_31, 0, 31);
|
||||
|
||||
impl_ppi_channel!(PPI_CH0, 0 => configurable);
|
||||
impl_ppi_channel!(PPI_CH1, 1 => configurable);
|
||||
impl_ppi_channel!(PPI_CH2, 2 => configurable);
|
||||
impl_ppi_channel!(PPI_CH3, 3 => configurable);
|
||||
impl_ppi_channel!(PPI_CH4, 4 => configurable);
|
||||
impl_ppi_channel!(PPI_CH5, 5 => configurable);
|
||||
impl_ppi_channel!(PPI_CH6, 6 => configurable);
|
||||
impl_ppi_channel!(PPI_CH7, 7 => configurable);
|
||||
impl_ppi_channel!(PPI_CH8, 8 => configurable);
|
||||
impl_ppi_channel!(PPI_CH9, 9 => configurable);
|
||||
impl_ppi_channel!(PPI_CH10, 10 => configurable);
|
||||
impl_ppi_channel!(PPI_CH11, 11 => configurable);
|
||||
impl_ppi_channel!(PPI_CH12, 12 => configurable);
|
||||
impl_ppi_channel!(PPI_CH13, 13 => configurable);
|
||||
impl_ppi_channel!(PPI_CH14, 14 => configurable);
|
||||
impl_ppi_channel!(PPI_CH15, 15 => configurable);
|
||||
|
||||
impl_saadc_input!(P0_13, ANALOG_INPUT0);
|
||||
impl_saadc_input!(P0_14, ANALOG_INPUT1);
|
||||
impl_saadc_input!(P0_15, ANALOG_INPUT2);
|
||||
impl_saadc_input!(P0_16, ANALOG_INPUT3);
|
||||
impl_saadc_input!(P0_17, ANALOG_INPUT4);
|
||||
impl_saadc_input!(P0_18, ANALOG_INPUT5);
|
||||
impl_saadc_input!(P0_19, ANALOG_INPUT6);
|
||||
impl_saadc_input!(P0_20, ANALOG_INPUT7);
|
||||
|
||||
impl_egu!(EGU0, EGU0, EGU0);
|
||||
impl_egu!(EGU1, EGU1, EGU1);
|
||||
impl_egu!(EGU2, EGU2, EGU2);
|
||||
impl_egu!(EGU3, EGU3, EGU3);
|
||||
impl_egu!(EGU4, EGU4, EGU4);
|
||||
impl_egu!(EGU5, EGU5, EGU5);
|
||||
|
||||
embassy_hal_internal::interrupt_mod!(
|
||||
SPU,
|
||||
CLOCK_POWER,
|
||||
UARTE0_SPIM0_SPIS0_TWIM0_TWIS0,
|
||||
UARTE1_SPIM1_SPIS1_TWIM1_TWIS1,
|
||||
UARTE2_SPIM2_SPIS2_TWIM2_TWIS2,
|
||||
UARTE3_SPIM3_SPIS3_TWIM3_TWIS3,
|
||||
GPIOTE0,
|
||||
SAADC,
|
||||
TIMER0,
|
||||
TIMER1,
|
||||
TIMER2,
|
||||
RTC0,
|
||||
RTC1,
|
||||
WDT,
|
||||
EGU0,
|
||||
EGU1,
|
||||
EGU2,
|
||||
EGU3,
|
||||
EGU4,
|
||||
EGU5,
|
||||
PWM0,
|
||||
PWM1,
|
||||
PWM2,
|
||||
PDM,
|
||||
PWM3,
|
||||
I2S,
|
||||
IPC,
|
||||
FPU,
|
||||
GPIOTE1,
|
||||
KMU,
|
||||
CRYPTOCELL,
|
||||
);
|
||||
Reference in new issue
Block a user