feat: add display UI with splash screen, dashboard, and RSSI sparkline
Implement full SSD1306 OLED display support: - Splash screen on boot (1.5s) with project name, version, board - Dashboard showing radio state, config, counters, RSSI/SNR - RSSI history sparkline (64-sample ring buffer, 2px-wide bars) - DisplayOn/DisplayOff host commands routed via dedicated channel - Pure render functions against generic DrawTarget (no hardware coupling) - Display on/off control bypasses radio task entirely Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
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//! Pulse Width Modulation (PWM) driver.
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#![macro_use]
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use core::sync::atomic::{compiler_fence, Ordering};
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use embassy_hal_internal::{into_ref, PeripheralRef};
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use crate::gpio::{convert_drive, AnyPin, OutputDrive, Pin as GpioPin, PselBits, SealedPin as _};
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use crate::ppi::{Event, Task};
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use crate::util::slice_in_ram_or;
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use crate::{interrupt, pac, Peripheral};
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/// SimplePwm is the traditional pwm interface you're probably used to, allowing
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/// to simply set a duty cycle across up to four channels.
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pub struct SimplePwm<'d, T: Instance> {
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_peri: PeripheralRef<'d, T>,
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duty: [u16; 4],
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ch0: Option<PeripheralRef<'d, AnyPin>>,
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ch1: Option<PeripheralRef<'d, AnyPin>>,
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ch2: Option<PeripheralRef<'d, AnyPin>>,
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ch3: Option<PeripheralRef<'d, AnyPin>>,
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}
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/// SequencePwm allows you to offload the updating of a sequence of duty cycles
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/// to up to four channels, as well as repeat that sequence n times.
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pub struct SequencePwm<'d, T: Instance> {
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_peri: PeripheralRef<'d, T>,
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ch0: Option<PeripheralRef<'d, AnyPin>>,
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ch1: Option<PeripheralRef<'d, AnyPin>>,
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ch2: Option<PeripheralRef<'d, AnyPin>>,
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ch3: Option<PeripheralRef<'d, AnyPin>>,
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}
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/// PWM error
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#[derive(Debug, Clone, Copy, PartialEq, Eq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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#[non_exhaustive]
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pub enum Error {
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/// Max Sequence size is 32767
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SequenceTooLong,
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/// Min Sequence count is 1
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SequenceTimesAtLeastOne,
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/// EasyDMA can only read from data memory, read only buffers in flash will fail.
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BufferNotInRAM,
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}
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const MAX_SEQUENCE_LEN: usize = 32767;
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/// The used pwm clock frequency
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pub const PWM_CLK_HZ: u32 = 16_000_000;
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impl<'d, T: Instance> SequencePwm<'d, T> {
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/// Create a new 1-channel PWM
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#[allow(unused_unsafe)]
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pub fn new_1ch(
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pwm: impl Peripheral<P = T> + 'd,
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ch0: impl Peripheral<P = impl GpioPin> + 'd,
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config: Config,
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) -> Result<Self, Error> {
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into_ref!(ch0);
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Self::new_inner(pwm, Some(ch0.map_into()), None, None, None, config)
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}
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/// Create a new 2-channel PWM
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#[allow(unused_unsafe)]
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pub fn new_2ch(
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pwm: impl Peripheral<P = T> + 'd,
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ch0: impl Peripheral<P = impl GpioPin> + 'd,
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ch1: impl Peripheral<P = impl GpioPin> + 'd,
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config: Config,
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) -> Result<Self, Error> {
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into_ref!(ch0, ch1);
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Self::new_inner(pwm, Some(ch0.map_into()), Some(ch1.map_into()), None, None, config)
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}
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/// Create a new 3-channel PWM
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#[allow(unused_unsafe)]
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pub fn new_3ch(
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pwm: impl Peripheral<P = T> + 'd,
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ch0: impl Peripheral<P = impl GpioPin> + 'd,
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ch1: impl Peripheral<P = impl GpioPin> + 'd,
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ch2: impl Peripheral<P = impl GpioPin> + 'd,
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config: Config,
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) -> Result<Self, Error> {
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into_ref!(ch0, ch1, ch2);
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Self::new_inner(
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pwm,
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Some(ch0.map_into()),
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Some(ch1.map_into()),
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Some(ch2.map_into()),
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None,
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config,
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)
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}
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/// Create a new 4-channel PWM
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#[allow(unused_unsafe)]
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pub fn new_4ch(
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pwm: impl Peripheral<P = T> + 'd,
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ch0: impl Peripheral<P = impl GpioPin> + 'd,
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ch1: impl Peripheral<P = impl GpioPin> + 'd,
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ch2: impl Peripheral<P = impl GpioPin> + 'd,
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ch3: impl Peripheral<P = impl GpioPin> + 'd,
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config: Config,
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) -> Result<Self, Error> {
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into_ref!(ch0, ch1, ch2, ch3);
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Self::new_inner(
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pwm,
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Some(ch0.map_into()),
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Some(ch1.map_into()),
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Some(ch2.map_into()),
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Some(ch3.map_into()),
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config,
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)
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}
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fn new_inner(
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_pwm: impl Peripheral<P = T> + 'd,
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ch0: Option<PeripheralRef<'d, AnyPin>>,
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ch1: Option<PeripheralRef<'d, AnyPin>>,
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ch2: Option<PeripheralRef<'d, AnyPin>>,
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ch3: Option<PeripheralRef<'d, AnyPin>>,
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config: Config,
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) -> Result<Self, Error> {
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into_ref!(_pwm);
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let r = T::regs();
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if let Some(pin) = &ch0 {
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pin.set_low();
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pin.conf()
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.write(|w| w.dir().output().drive().variant(convert_drive(config.ch0_drive)));
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}
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if let Some(pin) = &ch1 {
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pin.set_low();
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pin.conf()
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.write(|w| w.dir().output().drive().variant(convert_drive(config.ch1_drive)));
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}
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if let Some(pin) = &ch2 {
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pin.set_low();
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pin.conf()
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.write(|w| w.dir().output().drive().variant(convert_drive(config.ch2_drive)));
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}
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if let Some(pin) = &ch3 {
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pin.set_low();
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pin.conf()
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.write(|w| w.dir().output().drive().variant(convert_drive(config.ch3_drive)));
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}
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r.psel.out[0].write(|w| unsafe { w.bits(ch0.psel_bits()) });
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r.psel.out[1].write(|w| unsafe { w.bits(ch1.psel_bits()) });
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r.psel.out[2].write(|w| unsafe { w.bits(ch2.psel_bits()) });
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r.psel.out[3].write(|w| unsafe { w.bits(ch3.psel_bits()) });
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// Disable all interrupts
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r.intenclr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
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r.shorts.reset();
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r.events_stopped.reset();
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r.events_loopsdone.reset();
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r.events_seqend[0].reset();
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r.events_seqend[1].reset();
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r.events_pwmperiodend.reset();
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r.events_seqstarted[0].reset();
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r.events_seqstarted[1].reset();
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r.decoder.write(|w| {
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w.load().bits(config.sequence_load as u8);
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w.mode().refresh_count()
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});
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r.mode.write(|w| match config.counter_mode {
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CounterMode::UpAndDown => w.updown().up_and_down(),
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CounterMode::Up => w.updown().up(),
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});
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r.prescaler.write(|w| w.prescaler().bits(config.prescaler as u8));
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r.countertop.write(|w| unsafe { w.countertop().bits(config.max_duty) });
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Ok(Self {
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_peri: _pwm,
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ch0,
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ch1,
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ch2,
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ch3,
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})
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}
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/// Returns reference to `Stopped` event endpoint for PPI.
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#[inline(always)]
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pub fn event_stopped(&self) -> Event<'d> {
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let r = T::regs();
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Event::from_reg(&r.events_stopped)
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}
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/// Returns reference to `LoopsDone` event endpoint for PPI.
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#[inline(always)]
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pub fn event_loops_done(&self) -> Event<'d> {
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let r = T::regs();
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Event::from_reg(&r.events_loopsdone)
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}
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/// Returns reference to `PwmPeriodEnd` event endpoint for PPI.
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#[inline(always)]
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pub fn event_pwm_period_end(&self) -> Event<'d> {
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let r = T::regs();
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Event::from_reg(&r.events_pwmperiodend)
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}
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/// Returns reference to `Seq0 End` event endpoint for PPI.
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#[inline(always)]
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pub fn event_seq_end(&self) -> Event<'d> {
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let r = T::regs();
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Event::from_reg(&r.events_seqend[0])
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}
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/// Returns reference to `Seq1 End` event endpoint for PPI.
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#[inline(always)]
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pub fn event_seq1_end(&self) -> Event<'d> {
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let r = T::regs();
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Event::from_reg(&r.events_seqend[1])
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}
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/// Returns reference to `Seq0 Started` event endpoint for PPI.
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#[inline(always)]
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pub fn event_seq0_started(&self) -> Event<'d> {
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let r = T::regs();
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Event::from_reg(&r.events_seqstarted[0])
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}
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/// Returns reference to `Seq1 Started` event endpoint for PPI.
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#[inline(always)]
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pub fn event_seq1_started(&self) -> Event<'d> {
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let r = T::regs();
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Event::from_reg(&r.events_seqstarted[1])
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}
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/// Returns reference to `Seq0 Start` task endpoint for PPI.
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/// # Safety
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///
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/// Interacting with the sequence while it runs puts it in an unknown state
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#[inline(always)]
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pub unsafe fn task_start_seq0(&self) -> Task<'d> {
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let r = T::regs();
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Task::from_reg(&r.tasks_seqstart[0])
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}
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/// Returns reference to `Seq1 Started` task endpoint for PPI.
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/// # Safety
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///
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/// Interacting with the sequence while it runs puts it in an unknown state
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#[inline(always)]
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pub unsafe fn task_start_seq1(&self) -> Task<'d> {
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let r = T::regs();
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Task::from_reg(&r.tasks_seqstart[1])
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}
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/// Returns reference to `NextStep` task endpoint for PPI.
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/// # Safety
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///
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/// Interacting with the sequence while it runs puts it in an unknown state
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#[inline(always)]
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pub unsafe fn task_next_step(&self) -> Task<'d> {
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let r = T::regs();
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Task::from_reg(&r.tasks_nextstep)
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}
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/// Returns reference to `Stop` task endpoint for PPI.
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/// # Safety
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///
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/// Interacting with the sequence while it runs puts it in an unknown state
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#[inline(always)]
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pub unsafe fn task_stop(&self) -> Task<'d> {
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let r = T::regs();
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Task::from_reg(&r.tasks_stop)
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}
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}
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impl<'a, T: Instance> Drop for SequencePwm<'a, T> {
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fn drop(&mut self) {
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let r = T::regs();
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if let Some(pin) = &self.ch0 {
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pin.set_low();
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pin.conf().reset();
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r.psel.out[0].reset();
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}
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if let Some(pin) = &self.ch1 {
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pin.set_low();
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pin.conf().reset();
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r.psel.out[1].reset();
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}
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if let Some(pin) = &self.ch2 {
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pin.set_low();
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pin.conf().reset();
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r.psel.out[2].reset();
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}
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if let Some(pin) = &self.ch3 {
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pin.set_low();
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pin.conf().reset();
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r.psel.out[3].reset();
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}
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}
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}
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/// Configuration for the PWM as a whole.
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#[non_exhaustive]
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pub struct Config {
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/// Selects up mode or up-and-down mode for the counter
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pub counter_mode: CounterMode,
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/// Top value to be compared against buffer values
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pub max_duty: u16,
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/// Configuration for PWM_CLK
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pub prescaler: Prescaler,
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/// How a sequence is read from RAM and is spread to the compare register
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pub sequence_load: SequenceLoad,
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/// Drive strength for the channel 0 line.
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pub ch0_drive: OutputDrive,
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/// Drive strength for the channel 1 line.
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pub ch1_drive: OutputDrive,
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/// Drive strength for the channel 2 line.
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pub ch2_drive: OutputDrive,
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/// Drive strength for the channel 3 line.
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pub ch3_drive: OutputDrive,
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}
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impl Default for Config {
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fn default() -> Config {
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Config {
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counter_mode: CounterMode::Up,
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max_duty: 1000,
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prescaler: Prescaler::Div16,
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sequence_load: SequenceLoad::Common,
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ch0_drive: OutputDrive::Standard,
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ch1_drive: OutputDrive::Standard,
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ch2_drive: OutputDrive::Standard,
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ch3_drive: OutputDrive::Standard,
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}
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}
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}
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/// Configuration per sequence
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#[non_exhaustive]
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#[derive(Clone)]
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pub struct SequenceConfig {
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/// Number of PWM periods to delay between each sequence sample
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pub refresh: u32,
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/// Number of PWM periods after the sequence ends before starting the next sequence
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pub end_delay: u32,
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}
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impl Default for SequenceConfig {
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fn default() -> SequenceConfig {
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SequenceConfig {
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refresh: 0,
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end_delay: 0,
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}
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}
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}
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/// A composition of a sequence buffer and its configuration.
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#[non_exhaustive]
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pub struct Sequence<'s> {
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/// The words comprising the sequence. Must not exceed 32767 words.
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pub words: &'s [u16],
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/// Configuration associated with the sequence.
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pub config: SequenceConfig,
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}
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impl<'s> Sequence<'s> {
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/// Create a new `Sequence`
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pub fn new(words: &'s [u16], config: SequenceConfig) -> Self {
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Self { words, config }
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}
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}
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/// A single sequence that can be started and stopped.
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/// Takes one sequence along with its configuration.
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#[non_exhaustive]
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pub struct SingleSequencer<'d, 's, T: Instance> {
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sequencer: Sequencer<'d, 's, T>,
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}
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impl<'d, 's, T: Instance> SingleSequencer<'d, 's, T> {
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/// Create a new sequencer
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pub fn new(pwm: &'s mut SequencePwm<'d, T>, words: &'s [u16], config: SequenceConfig) -> Self {
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Self {
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sequencer: Sequencer::new(pwm, Sequence::new(words, config), None),
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}
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}
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/// Start or restart playback.
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#[inline(always)]
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pub fn start(&self, times: SingleSequenceMode) -> Result<(), Error> {
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let (start_seq, times) = match times {
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SingleSequenceMode::Times(n) if n == 1 => (StartSequence::One, SequenceMode::Loop(1)),
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SingleSequenceMode::Times(n) if n & 1 == 1 => (StartSequence::One, SequenceMode::Loop((n / 2) + 1)),
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SingleSequenceMode::Times(n) => (StartSequence::Zero, SequenceMode::Loop(n / 2)),
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SingleSequenceMode::Infinite => (StartSequence::Zero, SequenceMode::Infinite),
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};
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self.sequencer.start(start_seq, times)
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}
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/// Stop playback. Disables the peripheral. Does NOT clear the last duty
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/// cycle from the pin. Returns any sequences previously provided to
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/// `start` so that they may be further mutated.
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#[inline(always)]
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pub fn stop(&self) {
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self.sequencer.stop();
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}
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}
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||||
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||||
/// A composition of sequences that can be started and stopped.
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/// Takes at least one sequence along with its configuration.
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/// Optionally takes a second sequence and its configuration.
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/// In the case where no second sequence is provided then the first sequence
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/// is used.
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#[non_exhaustive]
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pub struct Sequencer<'d, 's, T: Instance> {
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_pwm: &'s mut SequencePwm<'d, T>,
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||||
sequence0: Sequence<'s>,
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||||
sequence1: Option<Sequence<'s>>,
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||||
}
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||||
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impl<'d, 's, T: Instance> Sequencer<'d, 's, T> {
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||||
/// Create a new double sequence. In the absence of sequence 1, sequence 0
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||||
/// will be used twice in the one loop.
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pub fn new(pwm: &'s mut SequencePwm<'d, T>, sequence0: Sequence<'s>, sequence1: Option<Sequence<'s>>) -> Self {
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||||
Sequencer {
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||||
_pwm: pwm,
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||||
sequence0,
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||||
sequence1,
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||||
}
|
||||
}
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||||
|
||||
/// Start or restart playback. The sequence mode applies to both sequences combined as one.
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||||
#[inline(always)]
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||||
pub fn start(&self, start_seq: StartSequence, times: SequenceMode) -> Result<(), Error> {
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||||
let sequence0 = &self.sequence0;
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||||
let alt_sequence = self.sequence1.as_ref().unwrap_or(&self.sequence0);
|
||||
|
||||
slice_in_ram_or(sequence0.words, Error::BufferNotInRAM)?;
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||||
slice_in_ram_or(alt_sequence.words, Error::BufferNotInRAM)?;
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||||
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||||
if sequence0.words.len() > MAX_SEQUENCE_LEN || alt_sequence.words.len() > MAX_SEQUENCE_LEN {
|
||||
return Err(Error::SequenceTooLong);
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||||
}
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||||
|
||||
if let SequenceMode::Loop(0) = times {
|
||||
return Err(Error::SequenceTimesAtLeastOne);
|
||||
}
|
||||
|
||||
self.stop();
|
||||
|
||||
let r = T::regs();
|
||||
|
||||
r.seq0.refresh.write(|w| unsafe { w.bits(sequence0.config.refresh) });
|
||||
r.seq0.enddelay.write(|w| unsafe { w.bits(sequence0.config.end_delay) });
|
||||
r.seq0.ptr.write(|w| unsafe { w.bits(sequence0.words.as_ptr() as u32) });
|
||||
r.seq0.cnt.write(|w| unsafe { w.bits(sequence0.words.len() as u32) });
|
||||
|
||||
r.seq1.refresh.write(|w| unsafe { w.bits(alt_sequence.config.refresh) });
|
||||
r.seq1
|
||||
.enddelay
|
||||
.write(|w| unsafe { w.bits(alt_sequence.config.end_delay) });
|
||||
r.seq1
|
||||
.ptr
|
||||
.write(|w| unsafe { w.bits(alt_sequence.words.as_ptr() as u32) });
|
||||
r.seq1.cnt.write(|w| unsafe { w.bits(alt_sequence.words.len() as u32) });
|
||||
|
||||
r.enable.write(|w| w.enable().enabled());
|
||||
|
||||
// defensive before seqstart
|
||||
compiler_fence(Ordering::SeqCst);
|
||||
|
||||
let seqstart_index = if start_seq == StartSequence::One { 1 } else { 0 };
|
||||
|
||||
match times {
|
||||
// just the one time, no loop count
|
||||
SequenceMode::Loop(n) => {
|
||||
r.loop_.write(|w| unsafe { w.cnt().bits(n) });
|
||||
}
|
||||
// to play infinitely, repeat the sequence one time, then have loops done self trigger seq0 again
|
||||
SequenceMode::Infinite => {
|
||||
r.loop_.write(|w| unsafe { w.cnt().bits(0x1) });
|
||||
r.shorts.write(|w| w.loopsdone_seqstart0().enabled());
|
||||
}
|
||||
}
|
||||
|
||||
// tasks_seqstart() doesn't exist in all svds so write its bit instead
|
||||
r.tasks_seqstart[seqstart_index].write(|w| unsafe { w.bits(0x01) });
|
||||
|
||||
Ok(())
|
||||
}
|
||||
|
||||
/// Stop playback. Disables the peripheral. Does NOT clear the last duty
|
||||
/// cycle from the pin. Returns any sequences previously provided to
|
||||
/// `start` so that they may be further mutated.
|
||||
#[inline(always)]
|
||||
pub fn stop(&self) {
|
||||
let r = T::regs();
|
||||
|
||||
r.shorts.reset();
|
||||
|
||||
compiler_fence(Ordering::SeqCst);
|
||||
|
||||
// tasks_stop() doesn't exist in all svds so write its bit instead
|
||||
r.tasks_stop.write(|w| unsafe { w.bits(0x01) });
|
||||
|
||||
r.enable.write(|w| w.enable().disabled());
|
||||
}
|
||||
}
|
||||
|
||||
impl<'d, 's, T: Instance> Drop for Sequencer<'d, 's, T> {
|
||||
fn drop(&mut self) {
|
||||
self.stop();
|
||||
}
|
||||
}
|
||||
|
||||
/// How many times to run a single sequence
|
||||
#[derive(Debug, Eq, PartialEq, Clone, Copy)]
|
||||
pub enum SingleSequenceMode {
|
||||
/// Run a single sequence n Times total.
|
||||
Times(u16),
|
||||
/// Repeat until `stop` is called.
|
||||
Infinite,
|
||||
}
|
||||
|
||||
/// Which sequence to start a loop with
|
||||
#[derive(Debug, Eq, PartialEq, Clone, Copy)]
|
||||
pub enum StartSequence {
|
||||
/// Start with Sequence 0
|
||||
Zero,
|
||||
/// Start with Sequence 1
|
||||
One,
|
||||
}
|
||||
|
||||
/// How many loops to run two sequences
|
||||
#[derive(Debug, Eq, PartialEq, Clone, Copy)]
|
||||
pub enum SequenceMode {
|
||||
/// Run two sequences n loops i.e. (n * (seq0 + seq1.unwrap_or(seq0)))
|
||||
Loop(u16),
|
||||
/// Repeat until `stop` is called.
|
||||
Infinite,
|
||||
}
|
||||
|
||||
/// PWM Base clock is system clock (16MHz) divided by prescaler
|
||||
#[derive(Debug, Eq, PartialEq, Clone, Copy)]
|
||||
pub enum Prescaler {
|
||||
/// Divide by 1
|
||||
Div1,
|
||||
/// Divide by 2
|
||||
Div2,
|
||||
/// Divide by 4
|
||||
Div4,
|
||||
/// Divide by 8
|
||||
Div8,
|
||||
/// Divide by 16
|
||||
Div16,
|
||||
/// Divide by 32
|
||||
Div32,
|
||||
/// Divide by 64
|
||||
Div64,
|
||||
/// Divide by 128
|
||||
Div128,
|
||||
}
|
||||
|
||||
/// How the sequence values are distributed across the channels
|
||||
#[derive(Debug, Eq, PartialEq, Clone, Copy)]
|
||||
pub enum SequenceLoad {
|
||||
/// Provided sequence will be used across all channels
|
||||
Common,
|
||||
/// Provided sequence contains grouped values for each channel ex:
|
||||
/// [ch0_0_and_ch1_0, ch2_0_and_ch3_0, ... ch0_n_and_ch1_n, ch2_n_and_ch3_n]
|
||||
Grouped,
|
||||
/// Provided sequence contains individual values for each channel ex:
|
||||
/// [ch0_0, ch1_0, ch2_0, ch3_0... ch0_n, ch1_n, ch2_n, ch3_n]
|
||||
Individual,
|
||||
/// Similar to Individual mode, but only three channels are used. The fourth
|
||||
/// value is loaded into the pulse generator counter as its top value.
|
||||
Waveform,
|
||||
}
|
||||
|
||||
/// Selects up mode or up-and-down mode for the counter
|
||||
#[derive(Debug, Eq, PartialEq, Clone, Copy)]
|
||||
pub enum CounterMode {
|
||||
/// Up counter (edge-aligned PWM duty cycle)
|
||||
Up,
|
||||
/// Up and down counter (center-aligned PWM duty cycle)
|
||||
UpAndDown,
|
||||
}
|
||||
|
||||
impl<'d, T: Instance> SimplePwm<'d, T> {
|
||||
/// Create a new 1-channel PWM
|
||||
#[allow(unused_unsafe)]
|
||||
pub fn new_1ch(pwm: impl Peripheral<P = T> + 'd, ch0: impl Peripheral<P = impl GpioPin> + 'd) -> Self {
|
||||
unsafe {
|
||||
into_ref!(ch0);
|
||||
Self::new_inner(pwm, Some(ch0.map_into()), None, None, None)
|
||||
}
|
||||
}
|
||||
|
||||
/// Create a new 2-channel PWM
|
||||
#[allow(unused_unsafe)]
|
||||
pub fn new_2ch(
|
||||
pwm: impl Peripheral<P = T> + 'd,
|
||||
ch0: impl Peripheral<P = impl GpioPin> + 'd,
|
||||
ch1: impl Peripheral<P = impl GpioPin> + 'd,
|
||||
) -> Self {
|
||||
into_ref!(ch0, ch1);
|
||||
Self::new_inner(pwm, Some(ch0.map_into()), Some(ch1.map_into()), None, None)
|
||||
}
|
||||
|
||||
/// Create a new 3-channel PWM
|
||||
#[allow(unused_unsafe)]
|
||||
pub fn new_3ch(
|
||||
pwm: impl Peripheral<P = T> + 'd,
|
||||
ch0: impl Peripheral<P = impl GpioPin> + 'd,
|
||||
ch1: impl Peripheral<P = impl GpioPin> + 'd,
|
||||
ch2: impl Peripheral<P = impl GpioPin> + 'd,
|
||||
) -> Self {
|
||||
unsafe {
|
||||
into_ref!(ch0, ch1, ch2);
|
||||
Self::new_inner(
|
||||
pwm,
|
||||
Some(ch0.map_into()),
|
||||
Some(ch1.map_into()),
|
||||
Some(ch2.map_into()),
|
||||
None,
|
||||
)
|
||||
}
|
||||
}
|
||||
|
||||
/// Create a new 4-channel PWM
|
||||
#[allow(unused_unsafe)]
|
||||
pub fn new_4ch(
|
||||
pwm: impl Peripheral<P = T> + 'd,
|
||||
ch0: impl Peripheral<P = impl GpioPin> + 'd,
|
||||
ch1: impl Peripheral<P = impl GpioPin> + 'd,
|
||||
ch2: impl Peripheral<P = impl GpioPin> + 'd,
|
||||
ch3: impl Peripheral<P = impl GpioPin> + 'd,
|
||||
) -> Self {
|
||||
unsafe {
|
||||
into_ref!(ch0, ch1, ch2, ch3);
|
||||
Self::new_inner(
|
||||
pwm,
|
||||
Some(ch0.map_into()),
|
||||
Some(ch1.map_into()),
|
||||
Some(ch2.map_into()),
|
||||
Some(ch3.map_into()),
|
||||
)
|
||||
}
|
||||
}
|
||||
|
||||
fn new_inner(
|
||||
_pwm: impl Peripheral<P = T> + 'd,
|
||||
ch0: Option<PeripheralRef<'d, AnyPin>>,
|
||||
ch1: Option<PeripheralRef<'d, AnyPin>>,
|
||||
ch2: Option<PeripheralRef<'d, AnyPin>>,
|
||||
ch3: Option<PeripheralRef<'d, AnyPin>>,
|
||||
) -> Self {
|
||||
into_ref!(_pwm);
|
||||
|
||||
let r = T::regs();
|
||||
|
||||
if let Some(pin) = &ch0 {
|
||||
pin.set_low();
|
||||
pin.conf().write(|w| w.dir().output());
|
||||
}
|
||||
if let Some(pin) = &ch1 {
|
||||
pin.set_low();
|
||||
pin.conf().write(|w| w.dir().output());
|
||||
}
|
||||
if let Some(pin) = &ch2 {
|
||||
pin.set_low();
|
||||
pin.conf().write(|w| w.dir().output());
|
||||
}
|
||||
if let Some(pin) = &ch3 {
|
||||
pin.set_low();
|
||||
pin.conf().write(|w| w.dir().output());
|
||||
}
|
||||
|
||||
// if NoPin provided writes disconnected (top bit 1) 0x80000000 else
|
||||
// writes pin number ex 13 (0x0D) which is connected (top bit 0)
|
||||
r.psel.out[0].write(|w| unsafe { w.bits(ch0.psel_bits()) });
|
||||
r.psel.out[1].write(|w| unsafe { w.bits(ch1.psel_bits()) });
|
||||
r.psel.out[2].write(|w| unsafe { w.bits(ch2.psel_bits()) });
|
||||
r.psel.out[3].write(|w| unsafe { w.bits(ch3.psel_bits()) });
|
||||
|
||||
let pwm = Self {
|
||||
_peri: _pwm,
|
||||
ch0,
|
||||
ch1,
|
||||
ch2,
|
||||
ch3,
|
||||
duty: [0; 4],
|
||||
};
|
||||
|
||||
// Disable all interrupts
|
||||
r.intenclr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
|
||||
r.shorts.reset();
|
||||
|
||||
// Enable
|
||||
r.enable.write(|w| w.enable().enabled());
|
||||
|
||||
r.seq0.ptr.write(|w| unsafe { w.bits((pwm.duty).as_ptr() as u32) });
|
||||
|
||||
r.seq0.cnt.write(|w| unsafe { w.bits(4) });
|
||||
r.seq0.refresh.write(|w| unsafe { w.bits(0) });
|
||||
r.seq0.enddelay.write(|w| unsafe { w.bits(0) });
|
||||
|
||||
r.decoder.write(|w| {
|
||||
w.load().individual();
|
||||
w.mode().refresh_count()
|
||||
});
|
||||
r.mode.write(|w| w.updown().up());
|
||||
r.prescaler.write(|w| w.prescaler().div_16());
|
||||
r.countertop.write(|w| unsafe { w.countertop().bits(1000) });
|
||||
r.loop_.write(|w| w.cnt().disabled());
|
||||
|
||||
pwm
|
||||
}
|
||||
|
||||
/// Returns the enable state of the pwm counter
|
||||
#[inline(always)]
|
||||
pub fn is_enabled(&self) -> bool {
|
||||
let r = T::regs();
|
||||
r.enable.read().enable().bit_is_set()
|
||||
}
|
||||
|
||||
/// Enables the PWM generator.
|
||||
#[inline(always)]
|
||||
pub fn enable(&self) {
|
||||
let r = T::regs();
|
||||
r.enable.write(|w| w.enable().enabled());
|
||||
}
|
||||
|
||||
/// Disables the PWM generator. Does NOT clear the last duty cycle from the pin.
|
||||
#[inline(always)]
|
||||
pub fn disable(&self) {
|
||||
let r = T::regs();
|
||||
r.enable.write(|w| w.enable().disabled());
|
||||
}
|
||||
|
||||
/// Returns the current duty of the channel
|
||||
pub fn duty(&self, channel: usize) -> u16 {
|
||||
self.duty[channel]
|
||||
}
|
||||
|
||||
/// Sets duty cycle (15 bit) for a PWM channel.
|
||||
pub fn set_duty(&mut self, channel: usize, duty: u16) {
|
||||
let r = T::regs();
|
||||
|
||||
self.duty[channel] = duty & 0x7FFF;
|
||||
|
||||
// reload ptr in case self was moved
|
||||
r.seq0.ptr.write(|w| unsafe { w.bits((self.duty).as_ptr() as u32) });
|
||||
|
||||
// defensive before seqstart
|
||||
compiler_fence(Ordering::SeqCst);
|
||||
|
||||
r.events_seqend[0].reset();
|
||||
|
||||
// tasks_seqstart() doesn't exist in all svds so write its bit instead
|
||||
r.tasks_seqstart[0].write(|w| unsafe { w.bits(1) });
|
||||
|
||||
// defensive wait until waveform is loaded after seqstart so set_duty
|
||||
// can't be called again while dma is still reading
|
||||
if self.is_enabled() {
|
||||
while r.events_seqend[0].read().bits() == 0 {}
|
||||
}
|
||||
}
|
||||
|
||||
/// Sets the PWM clock prescaler.
|
||||
#[inline(always)]
|
||||
pub fn set_prescaler(&self, div: Prescaler) {
|
||||
T::regs().prescaler.write(|w| w.prescaler().bits(div as u8));
|
||||
}
|
||||
|
||||
/// Gets the PWM clock prescaler.
|
||||
#[inline(always)]
|
||||
pub fn prescaler(&self) -> Prescaler {
|
||||
match T::regs().prescaler.read().prescaler().bits() {
|
||||
0 => Prescaler::Div1,
|
||||
1 => Prescaler::Div2,
|
||||
2 => Prescaler::Div4,
|
||||
3 => Prescaler::Div8,
|
||||
4 => Prescaler::Div16,
|
||||
5 => Prescaler::Div32,
|
||||
6 => Prescaler::Div64,
|
||||
7 => Prescaler::Div128,
|
||||
_ => unreachable!(),
|
||||
}
|
||||
}
|
||||
|
||||
/// Sets the maximum duty cycle value.
|
||||
#[inline(always)]
|
||||
pub fn set_max_duty(&self, duty: u16) {
|
||||
T::regs()
|
||||
.countertop
|
||||
.write(|w| unsafe { w.countertop().bits(duty.min(32767u16)) });
|
||||
}
|
||||
|
||||
/// Returns the maximum duty cycle value.
|
||||
#[inline(always)]
|
||||
pub fn max_duty(&self) -> u16 {
|
||||
T::regs().countertop.read().countertop().bits()
|
||||
}
|
||||
|
||||
/// Sets the PWM output frequency.
|
||||
#[inline(always)]
|
||||
pub fn set_period(&self, freq: u32) {
|
||||
let clk = PWM_CLK_HZ >> (self.prescaler() as u8);
|
||||
let duty = clk / freq;
|
||||
self.set_max_duty(duty.min(32767) as u16);
|
||||
}
|
||||
|
||||
/// Returns the PWM output frequency.
|
||||
#[inline(always)]
|
||||
pub fn period(&self) -> u32 {
|
||||
let clk = PWM_CLK_HZ >> (self.prescaler() as u8);
|
||||
let max_duty = self.max_duty() as u32;
|
||||
clk / max_duty
|
||||
}
|
||||
|
||||
/// Sets the PWM-Channel0 output drive strength
|
||||
#[inline(always)]
|
||||
pub fn set_ch0_drive(&self, drive: OutputDrive) {
|
||||
if let Some(pin) = &self.ch0 {
|
||||
pin.conf().modify(|_, w| w.drive().variant(convert_drive(drive)));
|
||||
}
|
||||
}
|
||||
|
||||
/// Sets the PWM-Channel1 output drive strength
|
||||
#[inline(always)]
|
||||
pub fn set_ch1_drive(&self, drive: OutputDrive) {
|
||||
if let Some(pin) = &self.ch1 {
|
||||
pin.conf().modify(|_, w| w.drive().variant(convert_drive(drive)));
|
||||
}
|
||||
}
|
||||
|
||||
/// Sets the PWM-Channel2 output drive strength
|
||||
#[inline(always)]
|
||||
pub fn set_ch2_drive(&self, drive: OutputDrive) {
|
||||
if let Some(pin) = &self.ch2 {
|
||||
pin.conf().modify(|_, w| w.drive().variant(convert_drive(drive)));
|
||||
}
|
||||
}
|
||||
|
||||
/// Sets the PWM-Channel3 output drive strength
|
||||
#[inline(always)]
|
||||
pub fn set_ch3_drive(&self, drive: OutputDrive) {
|
||||
if let Some(pin) = &self.ch3 {
|
||||
pin.conf().modify(|_, w| w.drive().variant(convert_drive(drive)));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl<'a, T: Instance> Drop for SimplePwm<'a, T> {
|
||||
fn drop(&mut self) {
|
||||
let r = T::regs();
|
||||
|
||||
self.disable();
|
||||
|
||||
if let Some(pin) = &self.ch0 {
|
||||
pin.set_low();
|
||||
pin.conf().reset();
|
||||
r.psel.out[0].reset();
|
||||
}
|
||||
if let Some(pin) = &self.ch1 {
|
||||
pin.set_low();
|
||||
pin.conf().reset();
|
||||
r.psel.out[1].reset();
|
||||
}
|
||||
if let Some(pin) = &self.ch2 {
|
||||
pin.set_low();
|
||||
pin.conf().reset();
|
||||
r.psel.out[2].reset();
|
||||
}
|
||||
if let Some(pin) = &self.ch3 {
|
||||
pin.set_low();
|
||||
pin.conf().reset();
|
||||
r.psel.out[3].reset();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pub(crate) trait SealedInstance {
|
||||
fn regs() -> &'static pac::pwm0::RegisterBlock;
|
||||
}
|
||||
|
||||
/// PWM peripheral instance.
|
||||
#[allow(private_bounds)]
|
||||
pub trait Instance: Peripheral<P = Self> + SealedInstance + 'static {
|
||||
/// Interrupt for this peripheral.
|
||||
type Interrupt: interrupt::typelevel::Interrupt;
|
||||
}
|
||||
|
||||
macro_rules! impl_pwm {
|
||||
($type:ident, $pac_type:ident, $irq:ident) => {
|
||||
impl crate::pwm::SealedInstance for peripherals::$type {
|
||||
fn regs() -> &'static pac::pwm0::RegisterBlock {
|
||||
unsafe { &*pac::$pac_type::ptr() }
|
||||
}
|
||||
}
|
||||
impl crate::pwm::Instance for peripherals::$type {
|
||||
type Interrupt = crate::interrupt::typelevel::$irq;
|
||||
}
|
||||
};
|
||||
}
|
||||
Reference in new issue
Block a user