feat: add display UI with splash screen, dashboard, and RSSI sparkline

Implement full SSD1306 OLED display support:
- Splash screen on boot (1.5s) with project name, version, board
- Dashboard showing radio state, config, counters, RSSI/SNR
- RSSI history sparkline (64-sample ring buffer, 2px-wide bars)
- DisplayOn/DisplayOff host commands routed via dedicated channel
- Pure render functions against generic DrawTarget (no hardware coupling)
- Display on/off control bypasses radio task entirely

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>

vendor/embedded-hal-0.2.7/src/blocking/can.rs

@@ -0,0 +1,17 @@
+//! Blocking CAN API
+
+/// A blocking CAN interface that is able to transmit and receive frames.
+pub trait Can {
+    /// Associated frame type.
+    type Frame: crate::can::Frame;
+
+    /// Associated error type.
+    type Error: crate::can::Error;
+
+    /// Puts a frame in the transmit buffer. Blocks until space is available in
+    /// the transmit buffer.
+    fn transmit(&mut self, frame: &Self::Frame) -> Result<(), Self::Error>;
+
+    /// Blocks until a frame was received or an error occured.
+    fn receive(&mut self) -> Result<Self::Frame, Self::Error>;
+}

vendor/embedded-hal-0.2.7/src/blocking/delay.rs

@@ -0,0 +1,26 @@
+//! Delays
+//!
+//! # What's the difference between these traits and the `timer::CountDown` trait?
+//!
+//! The `Timer` trait provides a *non-blocking* timer abstraction and it's meant to be used to build
+//! higher level abstractions like I/O operations with timeouts. OTOH, these delays traits only
+//! provide *blocking* functionality. Note that you can also use the `timer::CountDown` trait to
+//! implement blocking delays.
+
+/// Millisecond delay
+///
+/// `UXX` denotes the range type of the delay time. `UXX` can be `u8`, `u16`, etc. A single type can
+/// implement this trait for different types of `UXX`.
+pub trait DelayMs<UXX> {
+    /// Pauses execution for `ms` milliseconds
+    fn delay_ms(&mut self, ms: UXX);
+}
+
+/// Microsecond delay
+///
+/// `UXX` denotes the range type of the delay time. `UXX` can be `u8`, `u16`, etc. A single type can
+/// implement this trait for different types of `UXX`.
+pub trait DelayUs<UXX> {
+    /// Pauses execution for `us` microseconds
+    fn delay_us(&mut self, us: UXX);
+}

vendor/embedded-hal-0.2.7/src/blocking/i2c.rs

@@ -0,0 +1,297 @@
+//! Blocking I2C API
+//!
+//! This API supports 7-bit and 10-bit addresses. Traits feature an `AddressMode`
+//! marker type parameter. Two implementation of the `AddressMode` exist:
+//! `SevenBitAddress` and `TenBitAddress`.
+//!
+//! Through this marker types it is possible to implement each address mode for
+//! the traits independently in `embedded-hal` implementations and device drivers
+//! can depend only on the mode that they support.
+//!
+//! Additionally, the I2C 10-bit address mode has been developed to be fully
+//! backwards compatible with the 7-bit address mode. This allows for a
+//! software-emulated 10-bit addressing implementation if the address mode
+//! is not supported by the hardware.
+//!
+//! Since 7-bit addressing is the mode of the majority of I2C devices,
+//! `SevenBitAddress` has been set as default mode and thus can be omitted if desired.
+//!
+//! ## Examples
+//!
+//! ### `embedded-hal` implementation for an MCU
+//! Here is an example of an embedded-hal implementation of the `Write` trait
+//! for both modes:
+//! ```
+//! # use embedded_hal::blocking::i2c::{SevenBitAddress, TenBitAddress, Write};
+//! /// I2C0 hardware peripheral which supports both 7-bit and 10-bit addressing.
+//! pub struct I2c0;
+//!
+//! impl Write<SevenBitAddress> for I2c0
+//! {
+//! #   type Error = ();
+//! #
+//!     fn write(&mut self, addr: u8, output: &[u8]) -> Result<(), Self::Error> {
+//!         // ...
+//! #       Ok(())
+//!     }
+//! }
+//!
+//! impl Write<TenBitAddress> for I2c0
+//! {
+//! #   type Error = ();
+//! #
+//!     fn write(&mut self, addr: u16, output: &[u8]) -> Result<(), Self::Error> {
+//!         // ...
+//! #       Ok(())
+//!     }
+//! }
+//! ```
+//!
+//! ### Device driver compatible only with 7-bit addresses
+//!
+//! For demonstration purposes the address mode parameter has been omitted in this example.
+//!
+//! ```
+//! # use embedded_hal::blocking::i2c::WriteRead;
+//! const ADDR: u8  = 0x15;
+//! # const TEMP_REGISTER: u8 = 0x1;
+//! pub struct TemperatureSensorDriver<I2C> {
+//!     i2c: I2C,
+//! }
+//!
+//! impl<I2C, E> TemperatureSensorDriver<I2C>
+//! where
+//!     I2C: WriteRead<Error = E>,
+//! {
+//!     pub fn read_temperature(&mut self) -> Result<u8, E> {
+//!         let mut temp = [0];
+//!         self.i2c
+//!             .write_read(ADDR, &[TEMP_REGISTER], &mut temp)
+//!             .and(Ok(temp[0]))
+//!     }
+//! }
+//! ```
+//!
+//! ### Device driver compatible only with 10-bit addresses
+//!
+//! ```
+//! # use embedded_hal::blocking::i2c::{TenBitAddress, WriteRead};
+//! const ADDR: u16  = 0x158;
+//! # const TEMP_REGISTER: u8 = 0x1;
+//! pub struct TemperatureSensorDriver<I2C> {
+//!     i2c: I2C,
+//! }
+//!
+//! impl<I2C, E> TemperatureSensorDriver<I2C>
+//! where
+//!     I2C: WriteRead<TenBitAddress, Error = E>,
+//! {
+//!     pub fn read_temperature(&mut self) -> Result<u8, E> {
+//!         let mut temp = [0];
+//!         self.i2c
+//!             .write_read(ADDR, &[TEMP_REGISTER], &mut temp)
+//!             .and(Ok(temp[0]))
+//!     }
+//! }
+//! ```
+
+use crate::private;
+
+impl private::Sealed for SevenBitAddress {}
+impl private::Sealed for TenBitAddress {}
+
+/// Address mode (7-bit / 10-bit)
+///
+/// Note: This trait is sealed and should not be implemented outside of this crate.
+pub trait AddressMode: private::Sealed {}
+
+/// 7-bit address mode type
+pub type SevenBitAddress = u8;
+
+/// 10-bit address mode type
+pub type TenBitAddress = u16;
+
+impl AddressMode for SevenBitAddress {}
+
+impl AddressMode for TenBitAddress {}
+
+/// Blocking read
+pub trait Read<A: AddressMode = SevenBitAddress> {
+    /// Error type
+    type Error;
+
+    /// Reads enough bytes from slave with `address` to fill `buffer`
+    ///
+    /// # I2C Events (contract)
+    ///
+    /// ``` text
+    /// Master: ST SAD+R        MAK    MAK ...    NMAK SP
+    /// Slave:           SAK B0     B1     ... BN
+    /// ```
+    ///
+    /// Where
+    ///
+    /// - `ST` = start condition
+    /// - `SAD+R` = slave address followed by bit 1 to indicate reading
+    /// - `SAK` = slave acknowledge
+    /// - `Bi` = ith byte of data
+    /// - `MAK` = master acknowledge
+    /// - `NMAK` = master no acknowledge
+    /// - `SP` = stop condition
+    fn read(&mut self, address: A, buffer: &mut [u8]) -> Result<(), Self::Error>;
+}
+
+/// Blocking write
+pub trait Write<A: AddressMode = SevenBitAddress> {
+    /// Error type
+    type Error;
+
+    /// Writes bytes to slave with address `address`
+    ///
+    /// # I2C Events (contract)
+    ///
+    /// ``` text
+    /// Master: ST SAD+W     B0     B1     ... BN     SP
+    /// Slave:           SAK    SAK    SAK ...    SAK
+    /// ```
+    ///
+    /// Where
+    ///
+    /// - `ST` = start condition
+    /// - `SAD+W` = slave address followed by bit 0 to indicate writing
+    /// - `SAK` = slave acknowledge
+    /// - `Bi` = ith byte of data
+    /// - `SP` = stop condition
+    fn write(&mut self, address: A, bytes: &[u8]) -> Result<(), Self::Error>;
+}
+
+/// Blocking write (iterator version)
+pub trait WriteIter<A: AddressMode = SevenBitAddress> {
+    /// Error type
+    type Error;
+
+    /// Writes bytes to slave with address `address`
+    ///
+    /// # I2C Events (contract)
+    ///
+    /// Same as `Write`
+    fn write<B>(&mut self, address: A, bytes: B) -> Result<(), Self::Error>
+    where
+        B: IntoIterator<Item = u8>;
+}
+
+/// Blocking write + read
+pub trait WriteRead<A: AddressMode = SevenBitAddress> {
+    /// Error type
+    type Error;
+
+    /// Writes bytes to slave with address `address` and then reads enough bytes to fill `buffer` *in a
+    /// single transaction*
+    ///
+    /// # I2C Events (contract)
+    ///
+    /// ``` text
+    /// Master: ST SAD+W     O0     O1     ... OM     SR SAD+R        MAK    MAK ...    NMAK SP
+    /// Slave:           SAK    SAK    SAK ...    SAK          SAK I0     I1     ... IN
+    /// ```
+    ///
+    /// Where
+    ///
+    /// - `ST` = start condition
+    /// - `SAD+W` = slave address followed by bit 0 to indicate writing
+    /// - `SAK` = slave acknowledge
+    /// - `Oi` = ith outgoing byte of data
+    /// - `SR` = repeated start condition
+    /// - `SAD+R` = slave address followed by bit 1 to indicate reading
+    /// - `Ii` = ith incoming byte of data
+    /// - `MAK` = master acknowledge
+    /// - `NMAK` = master no acknowledge
+    /// - `SP` = stop condition
+    fn write_read(
+        &mut self,
+        address: A,
+        bytes: &[u8],
+        buffer: &mut [u8],
+    ) -> Result<(), Self::Error>;
+}
+
+/// Blocking write (iterator version) + read
+pub trait WriteIterRead<A: AddressMode = SevenBitAddress> {
+    /// Error type
+    type Error;
+
+    /// Writes bytes to slave with address `address` and then reads enough bytes to fill `buffer` *in a
+    /// single transaction*
+    ///
+    /// # I2C Events (contract)
+    ///
+    /// Same as the `WriteRead` trait
+    fn write_iter_read<B>(
+        &mut self,
+        address: A,
+        bytes: B,
+        buffer: &mut [u8],
+    ) -> Result<(), Self::Error>
+    where
+        B: IntoIterator<Item = u8>;
+}
+
+/// Transactional I2C operation.
+///
+/// Several operations can be combined as part of a transaction.
+#[derive(Debug, PartialEq)]
+pub enum Operation<'a> {
+    /// Read data into the provided buffer
+    Read(&'a mut [u8]),
+    /// Write data from the provided buffer
+    Write(&'a [u8]),
+}
+
+/// Transactional I2C interface.
+///
+/// This allows combining operations within an I2C transaction.
+pub trait Transactional<A: AddressMode = SevenBitAddress> {
+    /// Error type
+    type Error;
+
+    /// Execute the provided operations on the I2C bus.
+    ///
+    /// Transaction contract:
+    /// - Before executing the first operation an ST is sent automatically. This is followed by SAD+R/W as appropriate.
+    /// - Data from adjacent operations of the same type are sent after each other without an SP or SR.
+    /// - Between adjacent operations of a different type an SR and SAD+R/W is sent.
+    /// - After executing the last operation an SP is sent automatically.
+    /// - If the last operation is a `Read` the master does not send an acknowledge for the last byte.
+    ///
+    /// - `ST` = start condition
+    /// - `SAD+R/W` = slave address followed by bit 1 to indicate reading or 0 to indicate writing
+    /// - `SR` = repeated start condition
+    /// - `SP` = stop condition
+    fn exec<'a>(&mut self, address: A, operations: &mut [Operation<'a>])
+        -> Result<(), Self::Error>;
+}
+
+/// Transactional I2C interface (iterator version).
+///
+/// This allows combining operation within an I2C transaction.
+pub trait TransactionalIter<A: AddressMode = SevenBitAddress> {
+    /// Error type
+    type Error;
+
+    /// Execute the provided operations on the I2C bus (iterator version).
+    ///
+    /// Transaction contract:
+    /// - Before executing the first operation an ST is sent automatically. This is followed by SAD+R/W as appropriate.
+    /// - Data from adjacent operations of the same type are sent after each other without an SP or SR.
+    /// - Between adjacent operations of a different type an SR and SAD+R/W is sent.
+    /// - After executing the last operation an SP is sent automatically.
+    /// - If the last operation is a `Read` the master does not send an acknowledge for the last byte.
+    ///
+    /// - `ST` = start condition
+    /// - `SAD+R/W` = slave address followed by bit 1 to indicate reading or 0 to indicate writing
+    /// - `SR` = repeated start condition
+    /// - `SP` = stop condition
+    fn exec_iter<'a, O>(&mut self, address: A, operations: O) -> Result<(), Self::Error>
+    where
+        O: IntoIterator<Item = Operation<'a>>;
+}

vendor/embedded-hal-0.2.7/src/blocking/mod.rs

@@ -0,0 +1,12 @@
+//! Blocking API
+//!
+//! In some cases it's possible to implement these blocking traits on top of one of the core HAL
+//! traits. To save boilerplate when that's the case a `Default` marker trait may be provided.
+//! Implementing that marker trait will opt in your type into a blanket implementation.
+
+pub mod can;
+pub mod delay;
+pub mod i2c;
+pub mod rng;
+pub mod serial;
+pub mod spi;

vendor/embedded-hal-0.2.7/src/blocking/rng.rs

@@ -0,0 +1,19 @@
+//! Blocking hardware random number generator
+
+/// Blocking read
+///
+/// *This trait is available if embedded-hal is built with the `"unproven"` feature.*
+#[cfg(feature = "unproven")]
+pub trait Read {
+    /// Error type
+    type Error;
+
+    /// Reads enough bytes from hardware random number generator to fill `buffer`
+    ///
+    /// If any error is encountered then this function immediately returns. The contents of buf are
+    /// unspecified in this case.
+    ///
+    /// If this function returns an error, it is unspecified how many bytes it has read, but it
+    /// will never read more than would be necessary to completely fill the buffer.
+    fn read(&mut self, buffer: &mut [u8]) -> Result<(), Self::Error>;
+}

vendor/embedded-hal-0.2.7/src/blocking/serial.rs

@@ -0,0 +1,54 @@
+//! Blocking serial API
+
+/// Write half of a serial interface (blocking variant)
+pub trait Write<Word> {
+    /// The type of error that can occur when writing
+    type Error;
+
+    /// Writes a slice, blocking until everything has been written
+    ///
+    /// An implementation can choose to buffer the write, returning `Ok(())`
+    /// after the complete slice has been written to a buffer, but before all
+    /// words have been sent via the serial interface. To make sure that
+    /// everything has been sent, call [`bflush`] after this function returns.
+    ///
+    /// [`bflush`]: #tymethod.bflush
+    fn bwrite_all(&mut self, buffer: &[Word]) -> Result<(), Self::Error>;
+
+    /// Block until the serial interface has sent all buffered words
+    fn bflush(&mut self) -> Result<(), Self::Error>;
+}
+
+/// Blocking serial write
+pub mod write {
+    /// Marker trait to opt into default blocking write implementation
+    ///
+    /// Implementers of [`serial::Write`] can implement this marker trait
+    /// for their type. Doing so will automatically provide the default
+    /// implementation of [`blocking::serial::Write`] for the type.
+    ///
+    /// [`serial::Write`]: ../../serial/trait.Write.html
+    /// [`blocking::serial::Write`]: ../trait.Write.html
+    pub trait Default<Word>: ::serial::Write<Word> {}
+
+    impl<S, Word> ::blocking::serial::Write<Word> for S
+    where
+        S: Default<Word>,
+        Word: Clone,
+    {
+        type Error = S::Error;
+
+        fn bwrite_all(&mut self, buffer: &[Word]) -> Result<(), Self::Error> {
+            for word in buffer {
+                block!(self.write(word.clone()))?;
+            }
+
+            Ok(())
+        }
+
+        fn bflush(&mut self) -> Result<(), Self::Error> {
+            block!(self.flush())?;
+            Ok(())
+        }
+    }
+}

vendor/embedded-hal-0.2.7/src/blocking/spi.rs

@@ -0,0 +1,127 @@
+//! Blocking SPI API
+
+/// Blocking transfer
+pub trait Transfer<W> {
+    /// Error type
+    type Error;
+
+    /// Sends `words` to the slave. Returns the `words` received from the slave
+    fn transfer<'w>(&mut self, words: &'w mut [W]) -> Result<&'w [W], Self::Error>;
+}
+
+/// Blocking write
+pub trait Write<W> {
+    /// Error type
+    type Error;
+
+    /// Sends `words` to the slave, ignoring all the incoming words
+    fn write(&mut self, words: &[W]) -> Result<(), Self::Error>;
+}
+
+/// Blocking write (iterator version)
+#[cfg(feature = "unproven")]
+pub trait WriteIter<W> {
+    /// Error type
+    type Error;
+
+    /// Sends `words` to the slave, ignoring all the incoming words
+    fn write_iter<WI>(&mut self, words: WI) -> Result<(), Self::Error>
+    where
+        WI: IntoIterator<Item = W>;
+}
+
+/// Blocking transfer
+pub mod transfer {
+    /// Default implementation of `blocking::spi::Transfer<W>` for implementers of
+    /// `spi::FullDuplex<W>`
+    pub trait Default<W>: ::spi::FullDuplex<W> {}
+
+    impl<W, S> ::blocking::spi::Transfer<W> for S
+    where
+        S: Default<W>,
+        W: Clone,
+    {
+        type Error = S::Error;
+
+        fn transfer<'w>(&mut self, words: &'w mut [W]) -> Result<&'w [W], S::Error> {
+            for word in words.iter_mut() {
+                block!(self.send(word.clone()))?;
+                *word = block!(self.read())?;
+            }
+
+            Ok(words)
+        }
+    }
+}
+
+/// Blocking write
+pub mod write {
+    /// Default implementation of `blocking::spi::Write<W>` for implementers of `spi::FullDuplex<W>`
+    pub trait Default<W>: ::spi::FullDuplex<W> {}
+
+    impl<W, S> ::blocking::spi::Write<W> for S
+    where
+        S: Default<W>,
+        W: Clone,
+    {
+        type Error = S::Error;
+
+        fn write(&mut self, words: &[W]) -> Result<(), S::Error> {
+            for word in words {
+                block!(self.send(word.clone()))?;
+                block!(self.read())?;
+            }
+
+            Ok(())
+        }
+    }
+}
+
+/// Blocking write (iterator version)
+#[cfg(feature = "unproven")]
+pub mod write_iter {
+    /// Default implementation of `blocking::spi::WriteIter<W>` for implementers of
+    /// `spi::FullDuplex<W>`
+    pub trait Default<W>: ::spi::FullDuplex<W> {}
+
+    impl<W, S> ::blocking::spi::WriteIter<W> for S
+    where
+        S: Default<W>,
+        W: Clone,
+    {
+        type Error = S::Error;
+
+        fn write_iter<WI>(&mut self, words: WI) -> Result<(), S::Error>
+        where
+            WI: IntoIterator<Item = W>,
+        {
+            for word in words.into_iter() {
+                block!(self.send(word.clone()))?;
+                block!(self.read())?;
+            }
+
+            Ok(())
+        }
+    }
+}
+
+/// Operation for transactional SPI trait
+///
+/// This allows composition of SPI operations into a single bus transaction
+#[derive(Debug, PartialEq)]
+pub enum Operation<'a, W: 'static> {
+    /// Write data from the provided buffer, discarding read data
+    Write(&'a [W]),
+    /// Write data out while reading data into the provided buffer
+    Transfer(&'a mut [W]),
+}
+
+/// Transactional trait allows multiple actions to be executed
+/// as part of a single SPI transaction
+pub trait Transactional<W: 'static> {
+    /// Associated error type
+    type Error;
+
+    /// Execute the provided transactions
+    fn exec<'a>(&mut self, operations: &mut [Operation<'a, W>]) -> Result<(), Self::Error>;
+}