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feat: add display UI with splash screen, dashboard, and RSSI sparkline

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Implement full SSD1306 OLED display support:
- Splash screen on boot (1.5s) with project name, version, board
- Dashboard showing radio state, config, counters, RSSI/SNR
- RSSI history sparkline (64-sample ring buffer, 2px-wide bars)
- DisplayOn/DisplayOff host commands routed via dedicated channel
- Pure render functions against generic DrawTarget (no hardware coupling)
- Display on/off control bypasses radio task entirely

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
This commit is contained in:
swaitsandClaude Opus 4.6 committed 2026-03-29 20:42:54 -06:00
1 parent 7064110293
commit 3102fc747a
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+4564928 -38
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vendor/embedded-hal-async/.cargo-checksum.json
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{"files":{".cargo_vcs_info.json":"0f0a7a97a38c96c2dc518d8b119024163e9e44632c5e5fbd583e47ad0924b135","CHANGELOG.md":"78de5a99b560a201d076658b68cba5a07e2466aa8eff7b014c0aad6d185eca97","Cargo.toml":"c6f69c49e82d20b35408239bce633c42d638afb7d9f60a8b21ed3926c0189bd4","Cargo.toml.orig":"d7770241941f94c1f83902abd7a5f5ca9b5aa6239e24bd72f4d780645d2cf806","LICENSE-APACHE":"a60eea817514531668d7e00765731449fe14d059d3249e0bc93b36de45f759f2","LICENSE-MIT":"b32b47118594bca5e21a37d64d9924bff856bf4f688c482b417cc5e885d6e7bf","README.md":"3eb8268c40c943923a7e68b905803319b040af7729fce01a16805166d71c9517","build.rs":"ac03d95758d32c6fd09226cccfee2071c2c6d5e6e3e8866e5820b08871ff43c7","src/delay.rs":"0b1d2dec5ac83270d796d320311b56a0cb6b9b2070d56a99c6d0599d91727609","src/digital.rs":"c41e57013db6eadbd4741f8b24cd270fb8df8f4f1bb9ebff03eb1707416e7343","src/i2c.rs":"c0b9163d90d7f0b0d25a70ae03792c07fce1f20cf005e206ea82947854a7134f","src/lib.rs":"1611d308f5d435c28bfb5eb4ab57d52a180d478739feebd5a6a858a17a8b86a5","src/spi.rs":"983ac9da3a493452009e4c16bfb4774580d8253fbacc9611c03f398982e1d173"},"package":"0c4c685bbef7fe13c3c6dd4da26841ed3980ef33e841cddfa15ce8a8fb3f1884"}
vendor/embedded-hal-async/.cargo_vcs_info.json
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{
"git": {
"sha1": "f8c79fee1df1900ee59e90160729edfa16a99b63"
},
"path_in_vcs": "embedded-hal-async"
}
vendor/embedded-hal-async/CHANGELOG.md
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# Change Log
All notable changes to this project will be documented in this file.
The format is based on [Keep a Changelog](http://keepachangelog.com/)
and this project adheres to [Semantic Versioning](http://semver.org/).
## [Unreleased]
No unreleased changes yet.
## [v1.0.0] - 2023-12-28
- Updated `embedded-hal` to version `1.0.0`.
## [v1.0.0-rc.3] - 2023-12-14
- Updated `embedded-hal` to version `1.0.0-rc.3`.
## [v1.0.0-rc.2] - 2023-11-28
- Updated `embedded-hal` to version `1.0.0-rc.2`.
- Minor document fixes.
- Add #[inline] hints to most of `embedded-hal-async` functions.
- delay: Rename `DelayUs` to `DelayNs`
- delay: Add `DelayNs::delay_ns()`
- delay: Add default impls of `delay_ms` and `delay_us` based on `delay_ns`.
- spi: Rename `Operation::DelayUs` to `Operation::DelayNs`, with nanosecond precision.
- Use `feature()` on nightly toolchains only. This adds support for 1.75 beta and stable.
## [v1.0.0-rc.1] - 2023-08-15
- Updated `embedded-hal` to version `1.0.0-rc.1`.
- Add optional `defmt` 0.3 support.
- Remove serial traits, the replacement is the `embedded-io` crate.
- Added `+ ?Sized` to all blanket impls.
- Moved `ExclusiveDevice` to `embedded-hal-bus`.
## [v0.2.0-alpha.2] - 2023-07-04
### Added
- spi: added `Operation::DelayUs(u32)`.
### Changed
- Updated `embedded-hal` to version `1.0.0-alpha.11`.
- spi: removed redundant lifetime annotations. Note that recent nightlies care about them and require impls to match, so you might have to adjust them.
### Removed
- spi: removed read-only and write-only traits.
## [v0.2.0-alpha.1] - 2023-04-04
### Added
- Added a `serial::Write` trait.
### Changed
- Updated `embedded-hal` to version `1.0.0-alpha.10`.
- delay: make infallible.
- i2c: remove `_iter()` methods.
- i2c: add default implementations for all methods based on `transaction()`.
- spi: SpiDevice transaction now takes an operation slice instead of a closure
## [v0.2.0-alpha.0] - 2022-11-23
- Switch all traits to use [`async_fn_in_trait`](https://blog.rust-lang.org/inside-rust/2022/11/17/async-fn-in-trait-nightly.html) (AFIT). Requires `nightly-2022-11-22` or newer.
## [v0.1.0-alpha.3] - 2022-10-26
- Fix build on newer Rust nightlies.
## [v0.1.0-alpha.2] - 2022-09-28
### Added
- spi: added a transaction helper macro as a workaround for the raw pointer workaround.
### Changed
- Updated `embedded-hal` to version `1.0.0-alpha.9`.
## [v0.1.0-alpha.1] - 2022-05-24
### Changed
- spi: device helper methods (`read`, `write`, `transfer`...) are now default methods in `SpiDevice` instead of an `SpiDeviceExt` extension trait.
- spi: the `SpiDevice::transaction` closure now gets a raw pointer to the `SpiBus` to work around Rust borrow checker limitations.
- spi: the `SpiDevice` trait is now unsafe to implement due to the raw pointer workaround.
## [v0.1.0-alpha.0] - 2022-04-17
First release to crates.io
[Unreleased]: https://github.com/rust-embedded/embedded-hal/compare/embedded-hal-async-v1.0.0...HEAD
[v1.0.0]: https://github.com/rust-embedded/embedded-hal/compare/embedded-hal-async-v1.0.0-rc.3...embedded-hal-async-v1.0.0
[v1.0.0-rc.3]: https://github.com/rust-embedded/embedded-hal/compare/embedded-hal-async-v1.0.0-rc.2...embedded-hal-async-v1.0.0-rc.3
[v1.0.0-rc.2]: https://github.com/rust-embedded/embedded-hal/compare/embedded-hal-async-v1.0.0-rc.1...embedded-hal-async-v1.0.0-rc.2
[v1.0.0-rc.1]: https://github.com/rust-embedded/embedded-hal/compare/embedded-hal-async-v0.2.0-alpha.2...embedded-hal-async-v1.0.0-rc.1
[v0.2.0-alpha.2]: https://github.com/rust-embedded/embedded-hal/compare/embedded-hal-async-v0.2.0-alpha.1...embedded-hal-async-v0.2.0-alpha.2
[v0.2.0-alpha.1]: https://github.com/rust-embedded/embedded-hal/compare/embedded-hal-async-v0.2.0-alpha.0...embedded-hal-async-v0.2.0-alpha.1
[v0.2.0-alpha.0]: https://github.com/rust-embedded/embedded-hal/compare/embedded-hal-async-v0.1.0-alpha.3...embedded-hal-async-v0.2.0-alpha.0
[v0.1.0-alpha.3]: https://github.com/rust-embedded/embedded-hal/compare/embedded-hal-async-v0.1.0-alpha.2...embedded-hal-async-v0.1.0-alpha.3
[v0.1.0-alpha.2]: https://github.com/rust-embedded/embedded-hal/compare/embedded-hal-async-v0.1.0-alpha.1...embedded-hal-async-v0.1.0-alpha.2
[v0.1.0-alpha.1]: https://github.com/rust-embedded/embedded-hal/compare/embedded-hal-async-v0.1.0-alpha.0...embedded-hal-async-v0.1.0-alpha.1
[v0.1.0-alpha.0]: https://github.com/rust-embedded/embedded-hal/tree/embedded-hal-async-v0.1.0-alpha.0
vendor/embedded-hal-async/Cargo.toml
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# THIS FILE IS AUTOMATICALLY GENERATED BY CARGO
#
# When uploading crates to the registry Cargo will automatically
# "normalize" Cargo.toml files for maximal compatibility
# with all versions of Cargo and also rewrite `path` dependencies
# to registry (e.g., crates.io) dependencies.
#
# If you are reading this file be aware that the original Cargo.toml
# will likely look very different (and much more reasonable).
# See Cargo.toml.orig for the original contents.
[package]
edition = "2021"
rust-version = "1.75"
name = "embedded-hal-async"
version = "1.0.0"
authors = ["The Embedded HAL Team and Contributors <embedded-hal@teams.rust-embedded.org>"]
description = "An asynchronous Hardware Abstraction Layer (HAL) for embedded systems"
documentation = "https://docs.rs/embedded-hal-async"
readme = "README.md"
keywords = [
"hal",
"IO",
]
categories = [
"asynchronous",
"embedded",
"hardware-support",
"no-std",
]
license = "MIT OR Apache-2.0"
repository = "https://github.com/rust-embedded/embedded-hal"
[dependencies.defmt-03]
version = "0.3"
optional = true
package = "defmt"
[dependencies.embedded-hal]
version = "1.0.0"
[features]
defmt-03 = [
"dep:defmt-03",
"embedded-hal/defmt-03",
]
vendor/embedded-hal-async/LICENSE-APACHE
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Apache License
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vendor/embedded-hal-async/LICENSE-MIT
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Copyright (c) 2021-2022 The Rust embedded HAL team and contributors.
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
vendor/embedded-hal-async/README.md
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[![crates.io](https://img.shields.io/crates/d/embedded-hal-async.svg)](https://crates.io/crates/embedded-hal-async)
[![crates.io](https://img.shields.io/crates/v/embedded-hal-async.svg)](https://crates.io/crates/embedded-hal-async)
[![Documentation](https://docs.rs/embedded-hal-async/badge.svg)](https://docs.rs/embedded-hal-async)
# `embedded-hal-async`
An asynchronous Hardware Abstraction Layer (HAL) for embedded systems.
This crate contains asynchronous versions of the [`embedded-hal`](https://crates.io/crates/embedded-hal) traits and shares its scope and [design goals](https://docs.rs/embedded-hal/latest/embedded_hal/#design-goals).
This project is developed and maintained by the [HAL team](https://github.com/rust-embedded/wg#the-hal-team).
## Serial/UART traits
There is no serial traits in `embedded-hal-async`. Instead, use [`embedded-io-async`](https://crates.io/crates/embedded-io-async).
A serial port is essentially a byte-oriented stream, and that's what `embedded-io-async` models. Sharing the traits
with all byte streams has some advantages. For example, it allows generic code providing a command-line interface
or a console to operate either on hardware serial ports or on virtual ones like Telnet or USB CDC-ACM.
## Optional Cargo features
- **`defmt-03`**: Derive `defmt::Format` from `defmt` 0.3 for enums and structs.
## Minimum Supported Rust Version (MSRV)
This crate is guaranteed to compile on stable Rust 1.75 and up. It *might*
compile with older versions but that may change in any new patch release.
See [here](../docs/msrv.md) for details on how the MSRV may be upgraded.
## License
Licensed under either of
- Apache License, Version 2.0 ([LICENSE-APACHE](LICENSE-APACHE) or
<http://www.apache.org/licenses/LICENSE-2.0>)
- MIT license ([LICENSE-MIT](LICENSE-MIT) or <http://opensource.org/licenses/MIT>)
at your option.
### Contribution
Unless you explicitly state otherwise, any contribution intentionally submitted
for inclusion in the work by you, as defined in the Apache-2.0 license, shall be
dual licensed as above, without any additional terms or conditions.
vendor/embedded-hal-async/build.rs
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use std::env;
use std::ffi::OsString;
use std::process::Command;
fn main() {
println!("cargo:rerun-if-changed=build.rs");
let rustc = env::var_os("RUSTC").unwrap_or_else(|| OsString::from("rustc"));
let output = Command::new(rustc)
.arg("--version")
.output()
.expect("failed to run `rustc --version`");
if String::from_utf8_lossy(&output.stdout).contains("nightly") {
println!("cargo:rustc-cfg=nightly");
}
}
vendor/embedded-hal-async/src/delay.rs
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//! Delays.
/// Delay with up to nanosecond precision.
pub trait DelayNs {
/// Pauses execution for at minimum `ns` nanoseconds. Pause can be longer
/// if the implementation requires it due to precision/timing issues.
async fn delay_ns(&mut self, ns: u32);
/// Pauses execution for at minimum `us` microseconds. Pause can be longer
/// if the implementation requires it due to precision/timing issues.
async fn delay_us(&mut self, mut us: u32) {
while us > 4_294_967 {
us -= 4_294_967;
self.delay_ns(4_294_967_000).await;
}
self.delay_ns(us * 1_000).await;
}
/// Pauses execution for at minimum `ms` milliseconds. Pause can be longer
/// if the implementation requires it due to precision/timing issues.
#[inline]
async fn delay_ms(&mut self, mut ms: u32) {
while ms > 4294 {
ms -= 4294;
self.delay_ns(4_294_000_000).await;
}
self.delay_ns(ms * 1_000_000).await;
}
}
impl<T> DelayNs for &mut T
where
T: DelayNs + ?Sized,
{
#[inline]
async fn delay_ns(&mut self, ns: u32) {
T::delay_ns(self, ns).await;
}
#[inline]
async fn delay_us(&mut self, us: u32) {
T::delay_us(self, us).await;
}
#[inline]
async fn delay_ms(&mut self, ms: u32) {
T::delay_ms(self, ms).await;
}
}
vendor/embedded-hal-async/src/digital.rs
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//! Asynchronous digital I/O.
//!
//! # Example
//!
//! ```rust
//! # use embedded_hal_async::digital::Wait;
//! /// Asynchronously wait until the `ready_pin` becomes high.
//! async fn wait_until_ready<P>(ready_pin: &mut P)
//! where
//! P: Wait,
//! {
//! ready_pin
//! .wait_for_high()
//! .await
//! .expect("failed to await input pin")
//! }
//! ```
/// Asynchronously wait for GPIO pin state.
pub trait Wait: embedded_hal::digital::ErrorType {
/// Wait until the pin is high. If it is already high, return immediately.
///
/// # Note for implementers
/// The pin may have switched back to low before the task was run after
/// being woken. The future should still resolve in that case.
async fn wait_for_high(&mut self) -> Result<(), Self::Error>;
/// Wait until the pin is low. If it is already low, return immediately.
///
/// # Note for implementers
/// The pin may have switched back to high before the task was run after
/// being woken. The future should still resolve in that case.
async fn wait_for_low(&mut self) -> Result<(), Self::Error>;
/// Wait for the pin to undergo a transition from low to high.
///
/// If the pin is already high, this does *not* return immediately, it'll wait for the
/// pin to go low and then high again.
async fn wait_for_rising_edge(&mut self) -> Result<(), Self::Error>;
/// Wait for the pin to undergo a transition from high to low.
///
/// If the pin is already low, this does *not* return immediately, it'll wait for the
/// pin to go high and then low again.
async fn wait_for_falling_edge(&mut self) -> Result<(), Self::Error>;
/// Wait for the pin to undergo any transition, i.e low to high OR high to low.
async fn wait_for_any_edge(&mut self) -> Result<(), Self::Error>;
}
impl<T: Wait + ?Sized> Wait for &mut T {
#[inline]
async fn wait_for_high(&mut self) -> Result<(), Self::Error> {
T::wait_for_high(self).await
}
#[inline]
async fn wait_for_low(&mut self) -> Result<(), Self::Error> {
T::wait_for_low(self).await
}
#[inline]
async fn wait_for_rising_edge(&mut self) -> Result<(), Self::Error> {
T::wait_for_rising_edge(self).await
}
#[inline]
async fn wait_for_falling_edge(&mut self) -> Result<(), Self::Error> {
T::wait_for_falling_edge(self).await
}
#[inline]
async fn wait_for_any_edge(&mut self) -> Result<(), Self::Error> {
T::wait_for_any_edge(self).await
}
}
vendor/embedded-hal-async/src/i2c.rs
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//! Async I2C API.
//!
//! This API supports 7-bit and 10-bit addresses. Traits feature an `AddressMode`
//! marker type parameter. Two implementation of the `AddressMode` exist:
//! `SevenBitAddress` and `TenBitAddress`.
//!
//! Through this marker types it is possible to implement each address mode for
//! the traits independently in `embedded-hal` implementations and device drivers
//! can depend only on the mode that they support.
//!
//! Additionally, the I2C 10-bit address mode has been developed to be fully
//! backwards compatible with the 7-bit address mode. This allows for a
//! software-emulated 10-bit addressing implementation if the address mode
//! is not supported by the hardware.
//!
//! Since 7-bit addressing is the mode of the majority of I2C devices,
//! `SevenBitAddress` has been set as default mode and thus can be omitted if desired.
pub use embedded_hal::i2c::Operation;
pub use embedded_hal::i2c::{
AddressMode, Error, ErrorKind, ErrorType, NoAcknowledgeSource, SevenBitAddress, TenBitAddress,
};
/// Async I2c.
pub trait I2c<A: AddressMode = SevenBitAddress>: ErrorType {
/// Reads enough bytes from slave with `address` to fill `buffer`.
///
/// # I2C Events (contract)
///
/// ``` text
/// Master: ST SAD+R MAK MAK ... NMAK SP
/// Slave: SAK B0 B1 ... BN
/// ```
///
/// Where
///
/// - `ST` = start condition
/// - `SAD+R` = slave address followed by bit 1 to indicate reading
/// - `SAK` = slave acknowledge
/// - `Bi` = ith byte of data
/// - `MAK` = master acknowledge
/// - `NMAK` = master no acknowledge
/// - `SP` = stop condition
#[inline]
async fn read(&mut self, address: A, read: &mut [u8]) -> Result<(), Self::Error> {
self.transaction(address, &mut [Operation::Read(read)])
.await
}
/// Writes bytes to slave with address `address`.
///
/// # I2C Events (contract)
///
/// ``` text
/// Master: ST SAD+W B0 B1 ... BN SP
/// Slave: SAK SAK SAK ... SAK
/// ```
///
/// Where
///
/// - `ST` = start condition
/// - `SAD+W` = slave address followed by bit 0 to indicate writing
/// - `SAK` = slave acknowledge
/// - `Bi` = ith byte of data
/// - `SP` = stop condition
#[inline]
async fn write(&mut self, address: A, write: &[u8]) -> Result<(), Self::Error> {
self.transaction(address, &mut [Operation::Write(write)])
.await
}
/// Writes bytes to slave with address `address` and then reads enough bytes to fill `read` *in a
/// single transaction*.
///
/// # I2C Events (contract)
///
/// ``` text
/// Master: ST SAD+W O0 O1 ... OM SR SAD+R MAK MAK ... NMAK SP
/// Slave: SAK SAK SAK ... SAK SAK I0 I1 ... IN
/// ```
///
/// Where
///
/// - `ST` = start condition
/// - `SAD+W` = slave address followed by bit 0 to indicate writing
/// - `SAK` = slave acknowledge
/// - `Oi` = ith outgoing byte of data
/// - `SR` = repeated start condition
/// - `SAD+R` = slave address followed by bit 1 to indicate reading
/// - `Ii` = ith incoming byte of data
/// - `MAK` = master acknowledge
/// - `NMAK` = master no acknowledge
/// - `SP` = stop condition
#[inline]
async fn write_read(
&mut self,
address: A,
write: &[u8],
read: &mut [u8],
) -> Result<(), Self::Error> {
self.transaction(
address,
&mut [Operation::Write(write), Operation::Read(read)],
)
.await
}
/// Execute the provided operations on the I2C bus as a single transaction.
///
/// Transaction contract:
/// - Before executing the first operation an ST is sent automatically. This is followed by SAD+R/W as appropriate.
/// - Data from adjacent operations of the same type are sent after each other without an SP or SR.
/// - Between adjacent operations of a different type an SR and SAD+R/W is sent.
/// - After executing the last operation an SP is sent automatically.
/// - If the last operation is a `Read` the master does not send an acknowledge for the last byte.
///
/// - `ST` = start condition
/// - `SAD+R/W` = slave address followed by bit 1 to indicate reading or 0 to indicate writing
/// - `SR` = repeated start condition
/// - `SP` = stop condition
async fn transaction(
&mut self,
address: A,
operations: &mut [Operation<'_>],
) -> Result<(), Self::Error>;
}
impl<A: AddressMode, T: I2c<A> + ?Sized> I2c<A> for &mut T {
#[inline]
async fn read(&mut self, address: A, read: &mut [u8]) -> Result<(), Self::Error> {
T::read(self, address, read).await
}
#[inline]
async fn write(&mut self, address: A, write: &[u8]) -> Result<(), Self::Error> {
T::write(self, address, write).await
}
#[inline]
async fn write_read(
&mut self,
address: A,
write: &[u8],
read: &mut [u8],
) -> Result<(), Self::Error> {
T::write_read(self, address, write, read).await
}
#[inline]
async fn transaction(
&mut self,
address: A,
operations: &mut [Operation<'_>],
) -> Result<(), Self::Error> {
T::transaction(self, address, operations).await
}
}
vendor/embedded-hal-async/src/lib.rs
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#![doc = include_str!("../README.md")]
#![warn(missing_docs)]
#![no_std]
// disable warning for already-stabilized features.
// Needed to pass CI, because we deny warnings.
// We don't immediately remove them to not immediately break older nightlies.
// When all features are stable, we'll remove them.
#![cfg_attr(nightly, allow(stable_features, unknown_lints))]
#![cfg_attr(nightly, feature(async_fn_in_trait, impl_trait_projections))]
#![allow(async_fn_in_trait)]
pub mod delay;
pub mod digital;
pub mod i2c;
pub mod spi;
vendor/embedded-hal-async/src/spi.rs
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//! SPI master mode traits.
pub use embedded_hal::spi::{
Error, ErrorKind, ErrorType, Mode, Operation, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3,
};
/// SPI device trait.
///
/// `SpiDevice` represents ownership over a single SPI device on a (possibly shared) bus, selected
/// with a CS (Chip Select) pin.
///
/// See [the docs on embedded-hal](embedded_hal::spi) for important information on SPI Bus vs Device traits.
pub trait SpiDevice<Word: Copy + 'static = u8>: ErrorType {
/// Perform a transaction against the device.
///
/// - Locks the bus
/// - Asserts the CS (Chip Select) pin.
/// - Performs all the operations.
/// - [Flushes](SpiBus::flush) the bus.
/// - Deasserts the CS pin.
/// - Unlocks the bus.
///
/// The locking mechanism is implementation-defined. The only requirement is it must prevent two
/// transactions from executing concurrently against the same bus. Examples of implementations are:
/// critical sections, blocking mutexes, returning an error or panicking if the bus is already busy.
///
/// On bus errors the implementation should try to deassert CS.
/// If an error occurs while deasserting CS the bus error should take priority as the return value.
async fn transaction(
&mut self,
operations: &mut [Operation<'_, Word>],
) -> Result<(), Self::Error>;
/// Do a read within a transaction.
///
/// This is a convenience method equivalent to `device.read_transaction(&mut [buf])`.
///
/// See also: [`SpiDevice::transaction`], [`SpiDevice::read`]
#[inline]
async fn read(&mut self, buf: &mut [Word]) -> Result<(), Self::Error> {
self.transaction(&mut [Operation::Read(buf)]).await
}
/// Do a write within a transaction.
///
/// This is a convenience method equivalent to `device.write_transaction(&mut [buf])`.
///
/// See also: [`SpiDevice::transaction`], [`SpiDevice::write`]
#[inline]
async fn write(&mut self, buf: &[Word]) -> Result<(), Self::Error> {
self.transaction(&mut [Operation::Write(buf)]).await
}
/// Do a transfer within a transaction.
///
/// This is a convenience method equivalent to `device.transaction(&mut [Operation::Transfer(read, write)])`.
///
/// See also: [`SpiDevice::transaction`], [`SpiBus::transfer`]
#[inline]
async fn transfer(&mut self, read: &mut [Word], write: &[Word]) -> Result<(), Self::Error> {
self.transaction(&mut [Operation::Transfer(read, write)])
.await
}
/// Do an in-place transfer within a transaction.
///
/// This is a convenience method equivalent to `device.transaction(&mut [Operation::TransferInPlace(buf)])`.
///
/// See also: [`SpiDevice::transaction`], [`SpiBus::transfer_in_place`]
#[inline]
async fn transfer_in_place(&mut self, buf: &mut [Word]) -> Result<(), Self::Error> {
self.transaction(&mut [Operation::TransferInPlace(buf)])
.await
}
}
impl<Word: Copy + 'static, T: SpiDevice<Word> + ?Sized> SpiDevice<Word> for &mut T {
#[inline]
async fn transaction(
&mut self,
operations: &mut [Operation<'_, Word>],
) -> Result<(), Self::Error> {
T::transaction(self, operations).await
}
#[inline]
async fn read(&mut self, buf: &mut [Word]) -> Result<(), Self::Error> {
T::read(self, buf).await
}
#[inline]
async fn write(&mut self, buf: &[Word]) -> Result<(), Self::Error> {
T::write(self, buf).await
}
#[inline]
async fn transfer(&mut self, read: &mut [Word], write: &[Word]) -> Result<(), Self::Error> {
T::transfer(self, read, write).await
}
#[inline]
async fn transfer_in_place(&mut self, buf: &mut [Word]) -> Result<(), Self::Error> {
T::transfer_in_place(self, buf).await
}
}
/// SPI bus.
///
/// `SpiBus` represents **exclusive ownership** over the whole SPI bus, with SCK, MOSI and MISO pins.
///
/// See [the docs on embedded-hal][embedded_hal::spi] for important information on SPI Bus vs Device traits.
pub trait SpiBus<Word: 'static + Copy = u8>: ErrorType {
/// Read `words` from the slave.
///
/// The word value sent on MOSI during reading is implementation-defined,
/// typically `0x00`, `0xFF`, or configurable.
///
/// Implementations are allowed to return before the operation is
/// complete. See [the docs on embedded-hal][embedded_hal::spi] for details on flushing.
async fn read(&mut self, words: &mut [Word]) -> Result<(), Self::Error>;
/// Write `words` to the slave, ignoring all the incoming words.
///
/// Implementations are allowed to return before the operation is
/// complete. See [the docs on embedded-hal][embedded_hal::spi] for details on flushing.
async fn write(&mut self, words: &[Word]) -> Result<(), Self::Error>;
/// Write and read simultaneously. `write` is written to the slave on MOSI and
/// words received on MISO are stored in `read`.
///
/// It is allowed for `read` and `write` to have different lengths, even zero length.
/// The transfer runs for `max(read.len(), write.len())` words. If `read` is shorter,
/// incoming words after `read` has been filled will be discarded. If `write` is shorter,
/// the value of words sent in MOSI after all `write` has been sent is implementation-defined,
/// typically `0x00`, `0xFF`, or configurable.
///
/// Implementations are allowed to return before the operation is
/// complete. See [the docs on embedded-hal][embedded_hal::spi] for details on flushing.
async fn transfer(&mut self, read: &mut [Word], write: &[Word]) -> Result<(), Self::Error>;
/// Write and read simultaneously. The contents of `words` are
/// written to the slave, and the received words are stored into the same
/// `words` buffer, overwriting it.
///
/// Implementations are allowed to return before the operation is
/// complete. See [the docs on embedded-hal][embedded_hal::spi] for details on flushing.
async fn transfer_in_place(&mut self, words: &mut [Word]) -> Result<(), Self::Error>;
/// Wait until all operations have completed and the bus is idle.
///
/// See [the docs on embedded-hal][embedded_hal::spi] for information on flushing.
async fn flush(&mut self) -> Result<(), Self::Error>;
}
impl<T: SpiBus<Word> + ?Sized, Word: 'static + Copy> SpiBus<Word> for &mut T {
#[inline]
async fn read(&mut self, words: &mut [Word]) -> Result<(), Self::Error> {
T::read(self, words).await
}
#[inline]
async fn write(&mut self, words: &[Word]) -> Result<(), Self::Error> {
T::write(self, words).await
}
#[inline]
async fn transfer(&mut self, read: &mut [Word], write: &[Word]) -> Result<(), Self::Error> {
T::transfer(self, read, write).await
}
#[inline]
async fn transfer_in_place(&mut self, words: &mut [Word]) -> Result<(), Self::Error> {
T::transfer_in_place(self, words).await
}
#[inline]
async fn flush(&mut self) -> Result<(), Self::Error> {
T::flush(self).await
}
}