feat: add display UI with splash screen, dashboard, and RSSI sparkline

Implement full SSD1306 OLED display support:
- Splash screen on boot (1.5s) with project name, version, board
- Dashboard showing radio state, config, counters, RSSI/SNR
- RSSI history sparkline (64-sample ring buffer, 2px-wide bars)
- DisplayOn/DisplayOff host commands routed via dedicated channel
- Pure render functions against generic DrawTarget (no hardware coupling)
- Display on/off control bypasses radio task entirely

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>

vendor/embedded-hal-async/src/delay.rs

@@ -0,0 +1,49 @@
+//! Delays.
+
+/// Delay with up to nanosecond precision.
+pub trait DelayNs {
+    /// Pauses execution for at minimum `ns` nanoseconds. Pause can be longer
+    /// if the implementation requires it due to precision/timing issues.
+    async fn delay_ns(&mut self, ns: u32);
+
+    /// Pauses execution for at minimum `us` microseconds. Pause can be longer
+    /// if the implementation requires it due to precision/timing issues.
+    async fn delay_us(&mut self, mut us: u32) {
+        while us > 4_294_967 {
+            us -= 4_294_967;
+            self.delay_ns(4_294_967_000).await;
+        }
+        self.delay_ns(us * 1_000).await;
+    }
+
+    /// Pauses execution for at minimum `ms` milliseconds. Pause can be longer
+    /// if the implementation requires it due to precision/timing issues.
+    #[inline]
+    async fn delay_ms(&mut self, mut ms: u32) {
+        while ms > 4294 {
+            ms -= 4294;
+            self.delay_ns(4_294_000_000).await;
+        }
+        self.delay_ns(ms * 1_000_000).await;
+    }
+}
+
+impl<T> DelayNs for &mut T
+where
+    T: DelayNs + ?Sized,
+{
+    #[inline]
+    async fn delay_ns(&mut self, ns: u32) {
+        T::delay_ns(self, ns).await;
+    }
+
+    #[inline]
+    async fn delay_us(&mut self, us: u32) {
+        T::delay_us(self, us).await;
+    }
+
+    #[inline]
+    async fn delay_ms(&mut self, ms: u32) {
+        T::delay_ms(self, ms).await;
+    }
+}

vendor/embedded-hal-async/src/digital.rs

@@ -0,0 +1,76 @@
+//! Asynchronous digital I/O.
+//!
+//! # Example
+//!
+//! ```rust
+//! # use embedded_hal_async::digital::Wait;
+//! /// Asynchronously wait until the `ready_pin` becomes high.
+//! async fn wait_until_ready<P>(ready_pin: &mut P)
+//! where
+//!     P: Wait,
+//! {
+//!     ready_pin
+//!         .wait_for_high()
+//!         .await
+//!         .expect("failed to await input pin")
+//! }
+//! ```
+
+/// Asynchronously wait for GPIO pin state.
+pub trait Wait: embedded_hal::digital::ErrorType {
+    /// Wait until the pin is high. If it is already high, return immediately.
+    ///
+    /// # Note for implementers
+    /// The pin may have switched back to low before the task was run after
+    /// being woken. The future should still resolve in that case.
+    async fn wait_for_high(&mut self) -> Result<(), Self::Error>;
+
+    /// Wait until the pin is low. If it is already low, return immediately.
+    ///
+    /// # Note for implementers
+    /// The pin may have switched back to high before the task was run after
+    /// being woken. The future should still resolve in that case.
+    async fn wait_for_low(&mut self) -> Result<(), Self::Error>;
+
+    /// Wait for the pin to undergo a transition from low to high.
+    ///
+    /// If the pin is already high, this does *not* return immediately, it'll wait for the
+    /// pin to go low and then high again.
+    async fn wait_for_rising_edge(&mut self) -> Result<(), Self::Error>;
+
+    /// Wait for the pin to undergo a transition from high to low.
+    ///
+    /// If the pin is already low, this does *not* return immediately, it'll wait for the
+    /// pin to go high and then low again.
+    async fn wait_for_falling_edge(&mut self) -> Result<(), Self::Error>;
+
+    /// Wait for the pin to undergo any transition, i.e low to high OR high to low.
+    async fn wait_for_any_edge(&mut self) -> Result<(), Self::Error>;
+}
+
+impl<T: Wait + ?Sized> Wait for &mut T {
+    #[inline]
+    async fn wait_for_high(&mut self) -> Result<(), Self::Error> {
+        T::wait_for_high(self).await
+    }
+
+    #[inline]
+    async fn wait_for_low(&mut self) -> Result<(), Self::Error> {
+        T::wait_for_low(self).await
+    }
+
+    #[inline]
+    async fn wait_for_rising_edge(&mut self) -> Result<(), Self::Error> {
+        T::wait_for_rising_edge(self).await
+    }
+
+    #[inline]
+    async fn wait_for_falling_edge(&mut self) -> Result<(), Self::Error> {
+        T::wait_for_falling_edge(self).await
+    }
+
+    #[inline]
+    async fn wait_for_any_edge(&mut self) -> Result<(), Self::Error> {
+        T::wait_for_any_edge(self).await
+    }
+}

vendor/embedded-hal-async/src/i2c.rs

@@ -0,0 +1,157 @@
+//! Async I2C API.
+//!
+//! This API supports 7-bit and 10-bit addresses. Traits feature an `AddressMode`
+//! marker type parameter. Two implementation of the `AddressMode` exist:
+//! `SevenBitAddress` and `TenBitAddress`.
+//!
+//! Through this marker types it is possible to implement each address mode for
+//! the traits independently in `embedded-hal` implementations and device drivers
+//! can depend only on the mode that they support.
+//!
+//! Additionally, the I2C 10-bit address mode has been developed to be fully
+//! backwards compatible with the 7-bit address mode. This allows for a
+//! software-emulated 10-bit addressing implementation if the address mode
+//! is not supported by the hardware.
+//!
+//! Since 7-bit addressing is the mode of the majority of I2C devices,
+//! `SevenBitAddress` has been set as default mode and thus can be omitted if desired.
+
+pub use embedded_hal::i2c::Operation;
+pub use embedded_hal::i2c::{
+    AddressMode, Error, ErrorKind, ErrorType, NoAcknowledgeSource, SevenBitAddress, TenBitAddress,
+};
+
+/// Async I2c.
+pub trait I2c<A: AddressMode = SevenBitAddress>: ErrorType {
+    /// Reads enough bytes from slave with `address` to fill `buffer`.
+    ///
+    /// # I2C Events (contract)
+    ///
+    /// ``` text
+    /// Master: ST SAD+R        MAK    MAK ...    NMAK SP
+    /// Slave:           SAK B0     B1     ... BN
+    /// ```
+    ///
+    /// Where
+    ///
+    /// - `ST` = start condition
+    /// - `SAD+R` = slave address followed by bit 1 to indicate reading
+    /// - `SAK` = slave acknowledge
+    /// - `Bi` = ith byte of data
+    /// - `MAK` = master acknowledge
+    /// - `NMAK` = master no acknowledge
+    /// - `SP` = stop condition
+    #[inline]
+    async fn read(&mut self, address: A, read: &mut [u8]) -> Result<(), Self::Error> {
+        self.transaction(address, &mut [Operation::Read(read)])
+            .await
+    }
+
+    /// Writes bytes to slave with address `address`.
+    ///
+    /// # I2C Events (contract)
+    ///
+    /// ``` text
+    /// Master: ST SAD+W     B0     B1     ... BN     SP
+    /// Slave:           SAK    SAK    SAK ...    SAK
+    /// ```
+    ///
+    /// Where
+    ///
+    /// - `ST` = start condition
+    /// - `SAD+W` = slave address followed by bit 0 to indicate writing
+    /// - `SAK` = slave acknowledge
+    /// - `Bi` = ith byte of data
+    /// - `SP` = stop condition
+    #[inline]
+    async fn write(&mut self, address: A, write: &[u8]) -> Result<(), Self::Error> {
+        self.transaction(address, &mut [Operation::Write(write)])
+            .await
+    }
+
+    /// Writes bytes to slave with address `address` and then reads enough bytes to fill `read` *in a
+    /// single transaction*.
+    ///
+    /// # I2C Events (contract)
+    ///
+    /// ``` text
+    /// Master: ST SAD+W     O0     O1     ... OM     SR SAD+R        MAK    MAK ...    NMAK SP
+    /// Slave:           SAK    SAK    SAK ...    SAK          SAK I0     I1     ... IN
+    /// ```
+    ///
+    /// Where
+    ///
+    /// - `ST` = start condition
+    /// - `SAD+W` = slave address followed by bit 0 to indicate writing
+    /// - `SAK` = slave acknowledge
+    /// - `Oi` = ith outgoing byte of data
+    /// - `SR` = repeated start condition
+    /// - `SAD+R` = slave address followed by bit 1 to indicate reading
+    /// - `Ii` = ith incoming byte of data
+    /// - `MAK` = master acknowledge
+    /// - `NMAK` = master no acknowledge
+    /// - `SP` = stop condition
+    #[inline]
+    async fn write_read(
+        &mut self,
+        address: A,
+        write: &[u8],
+        read: &mut [u8],
+    ) -> Result<(), Self::Error> {
+        self.transaction(
+            address,
+            &mut [Operation::Write(write), Operation::Read(read)],
+        )
+        .await
+    }
+
+    /// Execute the provided operations on the I2C bus as a single transaction.
+    ///
+    /// Transaction contract:
+    /// - Before executing the first operation an ST is sent automatically. This is followed by SAD+R/W as appropriate.
+    /// - Data from adjacent operations of the same type are sent after each other without an SP or SR.
+    /// - Between adjacent operations of a different type an SR and SAD+R/W is sent.
+    /// - After executing the last operation an SP is sent automatically.
+    /// - If the last operation is a `Read` the master does not send an acknowledge for the last byte.
+    ///
+    /// - `ST` = start condition
+    /// - `SAD+R/W` = slave address followed by bit 1 to indicate reading or 0 to indicate writing
+    /// - `SR` = repeated start condition
+    /// - `SP` = stop condition
+    async fn transaction(
+        &mut self,
+        address: A,
+        operations: &mut [Operation<'_>],
+    ) -> Result<(), Self::Error>;
+}
+
+impl<A: AddressMode, T: I2c<A> + ?Sized> I2c<A> for &mut T {
+    #[inline]
+    async fn read(&mut self, address: A, read: &mut [u8]) -> Result<(), Self::Error> {
+        T::read(self, address, read).await
+    }
+
+    #[inline]
+    async fn write(&mut self, address: A, write: &[u8]) -> Result<(), Self::Error> {
+        T::write(self, address, write).await
+    }
+
+    #[inline]
+    async fn write_read(
+        &mut self,
+        address: A,
+        write: &[u8],
+        read: &mut [u8],
+    ) -> Result<(), Self::Error> {
+        T::write_read(self, address, write, read).await
+    }
+
+    #[inline]
+    async fn transaction(
+        &mut self,
+        address: A,
+        operations: &mut [Operation<'_>],
+    ) -> Result<(), Self::Error> {
+        T::transaction(self, address, operations).await
+    }
+}

vendor/embedded-hal-async/src/lib.rs

@@ -0,0 +1,15 @@
+#![doc = include_str!("../README.md")]
+#![warn(missing_docs)]
+#![no_std]
+// disable warning for already-stabilized features.
+// Needed to pass CI, because we deny warnings.
+// We don't immediately remove them to not immediately break older nightlies.
+// When all features are stable, we'll remove them.
+#![cfg_attr(nightly, allow(stable_features, unknown_lints))]
+#![cfg_attr(nightly, feature(async_fn_in_trait, impl_trait_projections))]
+#![allow(async_fn_in_trait)]
+
+pub mod delay;
+pub mod digital;
+pub mod i2c;
+pub mod spi;

vendor/embedded-hal-async/src/spi.rs

@@ -0,0 +1,180 @@
+//! SPI master mode traits.
+
+pub use embedded_hal::spi::{
+    Error, ErrorKind, ErrorType, Mode, Operation, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3,
+};
+
+/// SPI device trait.
+///
+/// `SpiDevice` represents ownership over a single SPI device on a (possibly shared) bus, selected
+/// with a CS (Chip Select) pin.
+///
+/// See [the docs on embedded-hal](embedded_hal::spi) for important information on SPI Bus vs Device traits.
+pub trait SpiDevice<Word: Copy + 'static = u8>: ErrorType {
+    /// Perform a transaction against the device.
+    ///
+    /// - Locks the bus
+    /// - Asserts the CS (Chip Select) pin.
+    /// - Performs all the operations.
+    /// - [Flushes](SpiBus::flush) the bus.
+    /// - Deasserts the CS pin.
+    /// - Unlocks the bus.
+    ///
+    /// The locking mechanism is implementation-defined. The only requirement is it must prevent two
+    /// transactions from executing concurrently against the same bus. Examples of implementations are:
+    /// critical sections, blocking mutexes, returning an error or panicking if the bus is already busy.
+    ///
+    /// On bus errors the implementation should try to deassert CS.
+    /// If an error occurs while deasserting CS the bus error should take priority as the return value.
+    async fn transaction(
+        &mut self,
+        operations: &mut [Operation<'_, Word>],
+    ) -> Result<(), Self::Error>;
+
+    /// Do a read within a transaction.
+    ///
+    /// This is a convenience method equivalent to `device.read_transaction(&mut [buf])`.
+    ///
+    /// See also: [`SpiDevice::transaction`], [`SpiDevice::read`]
+    #[inline]
+    async fn read(&mut self, buf: &mut [Word]) -> Result<(), Self::Error> {
+        self.transaction(&mut [Operation::Read(buf)]).await
+    }
+
+    /// Do a write within a transaction.
+    ///
+    /// This is a convenience method equivalent to `device.write_transaction(&mut [buf])`.
+    ///
+    /// See also: [`SpiDevice::transaction`], [`SpiDevice::write`]
+    #[inline]
+    async fn write(&mut self, buf: &[Word]) -> Result<(), Self::Error> {
+        self.transaction(&mut [Operation::Write(buf)]).await
+    }
+
+    /// Do a transfer within a transaction.
+    ///
+    /// This is a convenience method equivalent to `device.transaction(&mut [Operation::Transfer(read, write)])`.
+    ///
+    /// See also: [`SpiDevice::transaction`], [`SpiBus::transfer`]
+    #[inline]
+    async fn transfer(&mut self, read: &mut [Word], write: &[Word]) -> Result<(), Self::Error> {
+        self.transaction(&mut [Operation::Transfer(read, write)])
+            .await
+    }
+
+    /// Do an in-place transfer within a transaction.
+    ///
+    /// This is a convenience method equivalent to `device.transaction(&mut [Operation::TransferInPlace(buf)])`.
+    ///
+    /// See also: [`SpiDevice::transaction`], [`SpiBus::transfer_in_place`]
+    #[inline]
+    async fn transfer_in_place(&mut self, buf: &mut [Word]) -> Result<(), Self::Error> {
+        self.transaction(&mut [Operation::TransferInPlace(buf)])
+            .await
+    }
+}
+
+impl<Word: Copy + 'static, T: SpiDevice<Word> + ?Sized> SpiDevice<Word> for &mut T {
+    #[inline]
+    async fn transaction(
+        &mut self,
+        operations: &mut [Operation<'_, Word>],
+    ) -> Result<(), Self::Error> {
+        T::transaction(self, operations).await
+    }
+
+    #[inline]
+    async fn read(&mut self, buf: &mut [Word]) -> Result<(), Self::Error> {
+        T::read(self, buf).await
+    }
+
+    #[inline]
+    async fn write(&mut self, buf: &[Word]) -> Result<(), Self::Error> {
+        T::write(self, buf).await
+    }
+
+    #[inline]
+    async fn transfer(&mut self, read: &mut [Word], write: &[Word]) -> Result<(), Self::Error> {
+        T::transfer(self, read, write).await
+    }
+
+    #[inline]
+    async fn transfer_in_place(&mut self, buf: &mut [Word]) -> Result<(), Self::Error> {
+        T::transfer_in_place(self, buf).await
+    }
+}
+
+/// SPI bus.
+///
+/// `SpiBus` represents **exclusive ownership** over the whole SPI bus, with SCK, MOSI and MISO pins.
+///
+/// See [the docs on embedded-hal][embedded_hal::spi] for important information on SPI Bus vs Device traits.
+pub trait SpiBus<Word: 'static + Copy = u8>: ErrorType {
+    /// Read `words` from the slave.
+    ///
+    /// The word value sent on MOSI during reading is implementation-defined,
+    /// typically `0x00`, `0xFF`, or configurable.
+    ///
+    /// Implementations are allowed to return before the operation is
+    /// complete. See [the docs on embedded-hal][embedded_hal::spi] for details on flushing.
+    async fn read(&mut self, words: &mut [Word]) -> Result<(), Self::Error>;
+
+    /// Write `words` to the slave, ignoring all the incoming words.
+    ///
+    /// Implementations are allowed to return before the operation is
+    /// complete. See [the docs on embedded-hal][embedded_hal::spi] for details on flushing.
+    async fn write(&mut self, words: &[Word]) -> Result<(), Self::Error>;
+
+    /// Write and read simultaneously. `write` is written to the slave on MOSI and
+    /// words received on MISO are stored in `read`.
+    ///
+    /// It is allowed for `read` and `write` to have different lengths, even zero length.
+    /// The transfer runs for `max(read.len(), write.len())` words. If `read` is shorter,
+    /// incoming words after `read` has been filled will be discarded. If `write` is shorter,
+    /// the value of words sent in MOSI after all `write` has been sent is implementation-defined,
+    /// typically `0x00`, `0xFF`, or configurable.
+    ///
+    /// Implementations are allowed to return before the operation is
+    /// complete. See [the docs on embedded-hal][embedded_hal::spi] for details on flushing.
+    async fn transfer(&mut self, read: &mut [Word], write: &[Word]) -> Result<(), Self::Error>;
+
+    /// Write and read simultaneously. The contents of `words` are
+    /// written to the slave, and the received words are stored into the same
+    /// `words` buffer, overwriting it.
+    ///
+    /// Implementations are allowed to return before the operation is
+    /// complete. See [the docs on embedded-hal][embedded_hal::spi] for details on flushing.
+    async fn transfer_in_place(&mut self, words: &mut [Word]) -> Result<(), Self::Error>;
+
+    /// Wait until all operations have completed and the bus is idle.
+    ///
+    /// See [the docs on embedded-hal][embedded_hal::spi] for information on flushing.
+    async fn flush(&mut self) -> Result<(), Self::Error>;
+}
+
+impl<T: SpiBus<Word> + ?Sized, Word: 'static + Copy> SpiBus<Word> for &mut T {
+    #[inline]
+    async fn read(&mut self, words: &mut [Word]) -> Result<(), Self::Error> {
+        T::read(self, words).await
+    }
+
+    #[inline]
+    async fn write(&mut self, words: &[Word]) -> Result<(), Self::Error> {
+        T::write(self, words).await
+    }
+
+    #[inline]
+    async fn transfer(&mut self, read: &mut [Word], write: &[Word]) -> Result<(), Self::Error> {
+        T::transfer(self, read, write).await
+    }
+
+    #[inline]
+    async fn transfer_in_place(&mut self, words: &mut [Word]) -> Result<(), Self::Error> {
+        T::transfer_in_place(self, words).await
+    }
+
+    #[inline]
+    async fn flush(&mut self) -> Result<(), Self::Error> {
+        T::flush(self).await
+    }
+}