feat: add display UI with splash screen, dashboard, and RSSI sparkline
Implement full SSD1306 OLED display support: - Splash screen on boot (1.5s) with project name, version, board - Dashboard showing radio state, config, counters, RSSI/SNR - RSSI history sparkline (64-sample ring buffer, 2px-wide bars) - DisplayOn/DisplayOff host commands routed via dedicated channel - Pure render functions against generic DrawTarget (no hardware coupling) - Display on/off control bypasses radio task entirely Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
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//! Low-power I2C driver
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use fugit::HertzU32;
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use crate::{
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gpio::lp_io::LowPowerOutputOpenDrain,
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peripherals::{LP_CLKRST, LP_I2C0},
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};
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const LP_I2C_FILTER_CYC_NUM_DEF: u8 = 7;
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/// I2C-specific transmission errors
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#[derive(Debug, Clone, Copy, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum Error {
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/// The transmission exceeded the FIFO size.
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ExceedingFifo,
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/// The acknowledgment check failed.
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AckCheckFailed,
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/// A timeout occurred during transmission.
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TimeOut,
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/// The arbitration for the bus was lost.
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ArbitrationLost,
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/// The execution of the I2C command was incomplete.
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ExecIncomplete,
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/// The number of commands issued exceeded the limit.
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CommandNrExceeded,
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/// The response received from the I2C device was invalid.
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InvalidResponse,
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}
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#[allow(unused)]
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enum OperationType {
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Write = 0,
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Read = 1,
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}
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#[allow(unused)]
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#[derive(Eq, PartialEq, Copy, Clone)]
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enum Ack {
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Ack,
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Nack,
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}
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#[derive(PartialEq)]
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#[allow(unused)]
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enum Command {
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Start,
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Stop,
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End,
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Write {
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/// This bit is to set an expected ACK value for the transmitter.
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ack_exp: Ack,
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/// Enables checking the ACK value received against the ack_exp
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/// value.
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ack_check_en: bool,
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/// Length of data (in bytes) to be written. The maximum length is
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/// 255, while the minimum is 1.
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length: u8,
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},
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Read {
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/// Indicates whether the receiver will send an ACK after this byte
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/// has been received.
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ack_value: Ack,
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/// Length of data (in bytes) to be read. The maximum length is 255,
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/// while the minimum is 1.
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length: u8,
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},
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}
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// https://github.com/espressif/esp-idf/blob/master/components/ulp/lp_core/lp_core_i2c.c#L122
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// TX/RX RAM size is 16*8 bit
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// TX RX FIFO has 16 bit depth
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// The clock source of APB_CLK in LP_I2C is CLK_AON_FAST.
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// Configure LP_I2C_SCLK_SEL to select the clock source for I2C_SCLK.
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// When LP_I2C_SCLK_SEL is 0, select CLK_ROOT_FAST as clock source,
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// and when LP_I2C_SCLK_SEL is 1, select CLK _XTALD2 as the clock source.
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// Configure LP_EXT_I2C_CK_EN high to enable the clock source of I2C_SCLK.
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// Adjust the timing registers accordingly when the clock frequency changes.
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/// Represents a Low-Power I2C peripheral.
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pub struct LpI2c {
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i2c: LP_I2C0,
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}
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impl LpI2c {
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/// Creates a new instance of the `LpI2c` peripheral.
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pub fn new(
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i2c: LP_I2C0,
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_sda: LowPowerOutputOpenDrain<'_, 6>,
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_scl: LowPowerOutputOpenDrain<'_, 7>,
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frequency: HertzU32,
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) -> Self {
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let me = Self { i2c };
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// Configure LP I2C GPIOs
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// Initialize IO Pins
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let lp_io = unsafe { &*crate::peripherals::LP_IO::PTR };
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let lp_aon = unsafe { &*crate::peripherals::LP_AON::PTR };
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let lp_peri = unsafe { &*crate::peripherals::LP_PERI::PTR };
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unsafe {
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// FIXME: use GPIO APIs to configure pins
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lp_aon
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.gpio_mux()
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.modify(|r, w| w.sel().bits(r.sel().bits() | (1 << 6)));
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lp_aon
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.gpio_mux()
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.modify(|r, w| w.sel().bits(r.sel().bits() | (1 << 7)));
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lp_io.gpio(6).modify(|_, w| w.mcu_sel().bits(1)); // TODO
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lp_io.gpio(7).modify(|_, w| w.mcu_sel().bits(1));
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// Set output mode to Normal
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lp_io.pin(6).modify(|_, w| w.pad_driver().set_bit());
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// Enable output (writing to write-1-to-set register, then internally the
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// `GPIO_OUT_REG` will be set)
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lp_io
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.out_enable_w1ts()
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.write(|w| w.enable_w1ts().bits(1 << 6));
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// Enable input
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lp_io.gpio(6).modify(|_, w| w.fun_ie().set_bit());
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// Disable pulldown (enable internal weak pull-down)
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lp_io.gpio(6).modify(|_, w| w.fun_wpd().clear_bit());
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// Enable pullup
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lp_io.gpio(6).modify(|_, w| w.fun_wpu().set_bit());
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// Same process for SCL pin
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lp_io.pin(7).modify(|_, w| w.pad_driver().set_bit());
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// Enable output (writing to write-1-to-set register, then internally the
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// `GPIO_OUT_REG` will be set)
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lp_io
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.out_enable_w1ts()
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.write(|w| w.enable_w1ts().bits(1 << 7));
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// Enable input
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lp_io.gpio(7).modify(|_, w| w.fun_ie().set_bit());
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// Disable pulldown (enable internal weak pull-down)
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lp_io.gpio(7).modify(|_, w| w.fun_wpd().clear_bit());
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// Enable pullup
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lp_io.gpio(7).modify(|_, w| w.fun_wpu().set_bit());
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// Select LP I2C function for the SDA and SCL pins
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lp_io.gpio(6).modify(|_, w| w.mcu_sel().bits(1));
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lp_io.gpio(7).modify(|_, w| w.mcu_sel().bits(1));
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}
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// Initialize LP I2C HAL */
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me.i2c.clk_conf().modify(|_, w| w.sclk_active().set_bit());
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// Enable LP I2C controller clock
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lp_peri
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.clk_en()
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.modify(|_, w| w.lp_ext_i2c_ck_en().set_bit());
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lp_peri
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.reset_en()
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.modify(|_, w| w.lp_ext_i2c_reset_en().set_bit());
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lp_peri
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.reset_en()
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.modify(|_, w| w.lp_ext_i2c_reset_en().clear_bit());
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// Set LP I2C source clock
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unsafe { &*LP_CLKRST::PTR }
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.lpperi()
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.modify(|_, w| w.lp_i2c_clk_sel().clear_bit());
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// Initialize LP I2C Master mode
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me.i2c.ctr().modify(|_, w| unsafe {
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// Clear register
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w.bits(0);
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// Use open drain output for SDA and SCL
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w.sda_force_out().set_bit();
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w.scl_force_out().set_bit();
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// Ensure that clock is enabled
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w.clk_en().set_bit()
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});
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// First, reset the fifo buffers
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me.i2c.fifo_conf().modify(|_, w| w.nonfifo_en().clear_bit());
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me.i2c.ctr().modify(|_, w| {
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w.tx_lsb_first().clear_bit();
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w.rx_lsb_first().clear_bit()
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});
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me.reset_fifo();
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// Set LP I2C source clock
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unsafe { &*LP_CLKRST::PTR }
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.lpperi()
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.modify(|_, w| w.lp_i2c_clk_sel().clear_bit());
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// Configure LP I2C timing paramters. source_clk is ignored for LP_I2C in this
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// call
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let source_clk = 16_000_000;
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let bus_freq = frequency.raw();
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let clkm_div: u32 = source_clk / (bus_freq * 1024) + 1;
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let sclk_freq: u32 = source_clk / clkm_div;
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let half_cycle: u32 = sclk_freq / bus_freq / 2;
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// SCL
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let scl_low = half_cycle;
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// default, scl_wait_high < scl_high
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// Make 80KHz as a boundary here, because when working at lower frequency, too
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// much scl_wait_high will faster the frequency according to some
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// hardware behaviors.
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let scl_wait_high = if bus_freq >= 80 * 1000 {
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half_cycle / 2 - 2
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} else {
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half_cycle / 4
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};
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let scl_high = half_cycle - scl_wait_high;
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let sda_hold = half_cycle / 4;
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let sda_sample = half_cycle / 2; // TODO + scl_wait_high;
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let setup = half_cycle;
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let hold = half_cycle;
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// default we set the timeout value to about 10 bus cycles
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// log(20*half_cycle)/log(2) = log(half_cycle)/log(2) + log(20)/log(2)
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let tout = (4 * 8 - (5 * half_cycle).leading_zeros()) + 2;
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// According to the Technical Reference Manual, the following timings must be
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// subtracted by 1. However, according to the practical measurement and
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// some hardware behaviour, if wait_high_period and scl_high minus one.
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// The SCL frequency would be a little higher than expected. Therefore, the
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// solution here is not to minus scl_high as well as scl_wait high, and
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// the frequency will be absolutely accurate to all frequency
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// to some extent.
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let scl_low_period = scl_low - 1;
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let scl_high_period = scl_high;
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let scl_wait_high_period = scl_wait_high;
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// sda sample
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let sda_hold_time = sda_hold - 1;
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let sda_sample_time = sda_sample - 1;
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// setup
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let scl_rstart_setup_time = setup - 1;
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let scl_stop_setup_time = setup - 1;
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// hold
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let scl_start_hold_time = hold - 1;
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let scl_stop_hold_time = hold - 1;
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let time_out_value = tout;
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let time_out_en = true;
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// Write data to registers
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unsafe {
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me.i2c.clk_conf().modify(|_, w| {
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w.sclk_sel().clear_bit();
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w.sclk_div_num().bits((clkm_div - 1) as u8)
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});
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// scl period
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me.i2c
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.scl_low_period()
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.write(|w| w.scl_low_period().bits(scl_low_period as u16));
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me.i2c.scl_high_period().write(|w| {
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w.scl_high_period().bits(scl_high_period as u16);
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w.scl_wait_high_period().bits(scl_wait_high_period as u8)
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});
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// sda sample
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me.i2c
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.sda_hold()
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.write(|w| w.time().bits(sda_hold_time as u16));
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me.i2c
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.sda_sample()
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.write(|w| w.time().bits(sda_sample_time as u16));
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// setup
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me.i2c
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.scl_rstart_setup()
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.write(|w| w.time().bits(scl_rstart_setup_time as u16));
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me.i2c
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.scl_stop_setup()
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.write(|w| w.time().bits(scl_stop_setup_time as u16));
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// hold
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me.i2c
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.scl_start_hold()
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.write(|w| w.time().bits(scl_start_hold_time as u16));
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me.i2c
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.scl_stop_hold()
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.write(|w| w.time().bits(scl_stop_hold_time as u16));
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me.i2c.to().write(|w| {
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w.time_out_en().bit(time_out_en);
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w.time_out_value().bits(time_out_value.try_into().unwrap())
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});
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}
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// Enable SDA and SCL filtering. This configuration matches the HP I2C filter
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// config
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me.i2c
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.filter_cfg()
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.modify(|_, w| unsafe { w.sda_filter_thres().bits(LP_I2C_FILTER_CYC_NUM_DEF) });
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me.i2c
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.filter_cfg()
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.modify(|_, w| unsafe { w.scl_filter_thres().bits(LP_I2C_FILTER_CYC_NUM_DEF) });
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me.i2c
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.filter_cfg()
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.modify(|_, w| w.sda_filter_en().set_bit());
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me.i2c
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.filter_cfg()
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.modify(|_, w| w.scl_filter_en().set_bit());
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// Configure the I2C master to send a NACK when the Rx FIFO count is full
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me.i2c.ctr().modify(|_, w| w.rx_full_ack_level().set_bit());
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// Synchronize the config register values to the LP I2C peripheral clock
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me.lp_i2c_update();
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me
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}
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/// Update I2C configuration
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fn lp_i2c_update(&self) {
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self.i2c.ctr().modify(|_, w| w.conf_upgate().set_bit());
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}
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/// Resets the transmit and receive FIFO buffers.
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fn reset_fifo(&self) {
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self.i2c
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.fifo_conf()
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.modify(|_, w| w.tx_fifo_rst().set_bit());
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self.i2c
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.fifo_conf()
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.modify(|_, w| w.tx_fifo_rst().clear_bit());
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self.i2c
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.fifo_conf()
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.modify(|_, w| w.rx_fifo_rst().set_bit());
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self.i2c
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.fifo_conf()
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.modify(|_, w| w.rx_fifo_rst().clear_bit());
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}
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}
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Vendored
+2295
File diff suppressed because it is too large.
Load diff
Vendored
+11
@@ -0,0 +1,11 @@
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//! # Inter-Integrated Circuit (I2C)
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//!
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//! I2C is a serial, synchronous, multi-device, half-duplex communication
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//! protocol that allows co-existence of multiple masters and slaves on the
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//! same bus. I2C uses two bidirectional open-drain lines: serial data line
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//! (SDA) and serial clock line (SCL), pulled up by resistors.
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pub mod master;
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#[cfg(lp_i2c0)]
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pub mod lp_i2c;
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