feat: add display UI with splash screen, dashboard, and RSSI sparkline

Implement full SSD1306 OLED display support:
- Splash screen on boot (1.5s) with project name, version, board
- Dashboard showing radio state, config, counters, RSSI/SNR
- RSSI history sparkline (64-sample ring buffer, 2px-wide bars)
- DisplayOn/DisplayOff host commands routed via dedicated channel
- Pure render functions against generic DrawTarget (no hardware coupling)
- Display on/off control bypasses radio task entirely

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
This commit is contained in:
swaitsandClaude Opus 4.6 committed 2026-03-29 20:42:54 -06:00
1 parent 7064110293
commit 3102fc747a
17624 files changed
+4564928 -38

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[device]
name = "esp32"
arch = "xtensa"
cores = "multi_core"
peripherals = [
# Peripherals available in the PAC:
"aes",
"apb_ctrl",
"bb",
"dport",
"efuse",
"flash_encryption",
"frc_timer",
"gpio",
"gpio_sd",
"hinf",
"i2c0",
"i2c1",
"i2s0",
"i2s1",
"io_mux",
"ledc",
"mcpwm0",
"mcpwm1",
"nrx",
"pcnt",
"rmt",
"rng",
"rsa",
"rtc_cntl",
"rtc_i2c",
"rtc_io",
"sdhost",
"sens",
"sha",
"slc",
"slchost",
"spi0",
"spi1",
"spi2",
"spi3",
"timg0",
"timg1",
"twai0",
"uart0",
"uart1",
"uart2",
"uhci0",
"uhci1",
]
symbols = [
# Additional peripherals defined by us (the developers):
"adc",
"dac",
"pdma",
"phy",
"bt",
"wifi",
"psram",
"timg_timer1",
"touch",
"large_intr_status",
# ROM capabilities
"rom_crc_le",
"rom_crc_be",
"rom_md5_bsd",
# Wakeup SOC based on ESP-IDF:
"pm_support_ext0_wakeup",
"pm_support_ext1_wakeup",
"pm_support_touch_sensor_wakeup",
"ulp_supported",
]
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[device]
name = "esp32c2"
arch = "riscv"
cores = "single_core"
peripherals = [
# Peripherals available in the PAC:
"apb_ctrl",
"apb_saradc",
"assist_debug",
"dma",
"ecc",
"efuse",
"extmem",
"gpio",
"i2c0",
"interrupt_core0",
"io_mux",
"ledc",
"rng",
"rtc_cntl",
"sensitive",
"sha",
"spi0",
"spi1",
"spi2",
"system",
"systimer",
"timg0",
"uart0",
"uart1",
"xts_aes",
]
symbols = [
# Additional peripherals defined by us (the developers):
"adc",
"assist_debug_sp_monitor",
"gdma",
"phy",
"bt",
"wifi",
# ROM capabilities
"rom_crc_le",
"rom_crc_be",
"rom_md5_mbedtls",
# Wakeup SOC based on ESP-IDF:
"pm_support_wifi_wakeup",
"pm_support_bt_wakeup",
"uart_support_wakeup_int",
"gpio_support_deepsleep_wakeup",
]
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[device]
name = "esp32c3"
arch = "riscv"
cores = "single_core"
peripherals = [
# Peripherals available in the PAC:
"aes",
"apb_ctrl",
"apb_saradc",
"assist_debug",
"dma",
"ds",
"efuse",
"extmem",
"gpio",
"gpio_sd",
"hmac",
"i2c0",
"i2s0",
"interrupt_core0",
"io_mux",
"ledc",
"rmt",
"rng",
"rsa",
"rtc_cntl",
"sensitive",
"sha",
"spi0",
"spi1",
"spi2",
"system",
"systimer",
"timg0",
"timg1",
"twai0",
"uart0",
"uart1",
"uhci0",
"uhci1",
"usb_device",
"xts_aes",
]
symbols = [
# Additional peripherals defined by us (the developers):
"adc",
"assist_debug_sp_monitor",
"assist_debug_region_monitor",
"gdma",
"phy",
"bt",
"wifi",
# ROM capabilities
"rom_crc_le",
"rom_crc_be",
"rom_md5_bsd",
# Wakeup SOC based on ESP-IDF:
"pm_support_wifi_wakeup",
"pm_support_bt_wakeup",
"uart_support_wakeup_int",
"gpio_support_deepsleep_wakeup",
]
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[device]
name = "esp32c6"
arch = "riscv"
cores = "single_core"
peripherals = [
# Peripherals available in the PAC:
"aes",
"apb_saradc",
"assist_debug",
"atomic",
"dma",
"ds",
"ecc",
"efuse",
"extmem",
"gpio",
"gpio_sd",
"hinf",
"hmac",
"hp_apm",
"hp_sys",
"i2c0",
"i2s0",
"interrupt_core0",
"intpri",
"io_mux",
"ledc",
"lp_ana",
"lp_aon",
"lp_apm",
"lp_apm0",
"lp_clkrst",
"lp_i2c0",
"lp_i2c_ana_mst",
"lp_io",
"lp_peri",
"lp_tee",
"lp_timer",
"lp_uart",
"lp_wdt",
"mcpwm0",
"mem_monitor",
"otp_debug",
"parl_io",
"pau",
"pcnt",
"pcr",
"pmu",
"rmt",
"rng",
"rsa",
"sha",
"slchost",
"soc_etm",
"spi0",
"spi1",
"spi2",
"systimer",
"tee",
"timg0",
"timg1",
"trace0",
"twai0",
"twai1",
"uart0",
"uart1",
"uhci0",
"usb_device",
]
symbols = [
# Additional peripherals defined by us (the developers):
"adc",
"assist_debug_sp_monitor",
"assist_debug_region_monitor",
"gdma",
"large_intr_status",
"plic",
"phy",
"bt",
"wifi",
"ieee802154",
"lp_core",
# ROM capabilities
"rom_crc_le",
"rom_crc_be",
"rom_md5_bsd",
# Wakeup SOC based on ESP-IDF:
"pm_support_wifi_wakeup",
"pm_support_beacon_wakeup",
"pm_support_bt_wakeup",
"gpio_support_deepsleep_wakeup",
"uart_support_wakeup_int",
"pm_support_ext1_wakeup",
]
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[device]
name = "esp32h2"
arch = "riscv"
cores = "single_core"
peripherals = [
# Peripherals available in the PAC:
"aes",
"apb_saradc",
"assist_debug",
"dma",
"ds",
"ecc",
"efuse",
"gpio",
"gpio_sd",
"hmac",
"hp_apm",
"hp_sys",
"i2c0",
"i2c1",
"i2s0",
"interrupt_core0",
"intpri",
"io_mux",
"ledc",
"lp_ana",
"lp_aon",
"lp_apm",
"lp_clkrst",
"lp_peri",
"lp_timer",
"lp_wdt",
"mcpwm0",
"mem_monitor",
"modem_lpcon",
"modem_syscon",
"otp_debug",
"parl_io",
"pau",
"pcnt",
"pcr",
"pmu",
"rmt",
"rng",
"rsa",
"sha",
"soc_etm",
"spi0",
"spi1",
"spi2",
"systimer",
"tee",
"timg0",
"timg1",
"trace0",
"twai0",
"uart0",
"uart1",
"uhci0",
"usb_device",
]
symbols = [
# Additional peripherals defined by us (the developers):
"adc",
"assist_debug_sp_monitor",
"assist_debug_region_monitor",
"gdma",
"plic",
"phy",
"bt",
"ieee802154",
# ROM capabilities
"rom_crc_le",
"rom_crc_be",
"rom_md5_bsd",
]
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[device]
name = "esp32p4"
arch = "riscv"
cores = "multi_core"
peripherals = [
# Peripherals available in the PAC:
# "adc",
# "aes",
# "assist_debug",
# "axi_dma",
# "axi_icm",
# "bitscrambler",
# "cache",
# "dma",
# "ds",
# "ecc",
# "ecdsa",
"efuse",
# "gpio_sd",
"gpio",
# "h264_dma",
# "h264",
# "hmac",
# "hp_sys_clkrst",
"hp_sys",
# "i2c0",
# "i2c1",
# "i2s0",
# "i2s1",
# "i2s2",
# "i3c_mst_mem",
# "i3c_mst",
# "i3c_slv",
"interrupt_core0",
"interrupt_core1",
"io_mux",
# "isp",
# "jpeg",
# "lcd_cam",
# "ledc",
# "lp_adc",
# "lp_ana_peri",
# "lp_aon_clkrst",
# "lp_gpio",
# "lp_huk",
# "lp_i2c_ana_mst",
# "lp_i2c0",
# "lp_i2s0",
# "lp_intr",
# "lp_io_mux",
# "lp_peri",
# "lp_sys",
# "lp_timer",
# "lp_touch",
# "lp_tsens",
# "lp_uart",
# "lp_wdt",
# "mcpwm0",
# "mcpwm1",
# "mipi_csi_bridge",
# "mipi_csi_host",
# "mipi_dsi_bridge",
# "mipi_dsi_host",
# "parl_io",
# "pau",
# "pcnt",
# "pmu",
# "ppa",
# "pvt",
# "rmt",
# "rsa",
# "sdhost",
# "sha",
# "soc_etm",
# "spi0",
# "spi1",
# "spi2",
# "spi3",
# "systimer",
# "timg0",
# "timg1",
# "trace0",
# "trace1",
# "twai0",
# "twai1",
# "twai2",
# "uart0",
# "uhci0",
# "usb_device",
# "usb_wrap",
]
symbols = [
# Additional peripherals defined by us (the developers):
"clic",
"very_large_intr_status",
]
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[device]
name = "esp32s2"
arch = "xtensa"
cores = "single_core"
peripherals = [
# Peripherals available in the PAC:
"aes",
"apb_saradc",
"dedicated_gpio",
"ds",
"efuse",
"extmem",
"gpio",
"gpio_sd",
"hmac",
"i2c0",
"i2c1",
"i2s0",
"interrupt_core0",
"io_mux",
"ledc",
"pcnt",
"pms",
"rmt",
"rng",
"rsa",
"rtc_cntl",
"rtc_i2c",
"rtc_io",
"sens",
"sha",
"spi0",
"spi1",
"spi2",
"spi3",
"system",
"systimer",
"timg0",
"timg1",
"twai0",
"uart0",
"uart1",
"uhci0",
"usb0",
"usb_wrap",
"xts_aes",
]
symbols = [
# Additional peripherals defined by us (the developers):
"adc",
"dac",
"pdma",
"phy",
"wifi",
"psram",
"ulp_riscv_core",
"timg_timer1",
"large_intr_status",
# ROM capabilities
"rom_crc_le",
"rom_md5_bsd",
# Wakeup SOC based on ESP-IDF:
"pm_support_ext0_wakeup",
"pm_support_ext1_wakeup",
"pm_support_touch_sensor_wakeup",
"pm_support_wifi_wakeup",
"uart_support_wakeup_int",
"ulp_supported",
"riscv_coproc_supported",
]
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[device]
name = "esp32s3"
arch = "xtensa"
cores = "multi_core"
peripherals = [
# Peripherals available in the PAC:
"aes",
"apb_ctrl",
"apb_saradc",
"assist_debug",
"dma",
"ds",
"efuse",
"extmem",
"gpio",
"gpio_sd",
"hmac",
"i2c0",
"i2c1",
"i2s0",
"i2s1",
"interrupt_core0",
"interrupt_core1",
"io_mux",
"lcd_cam",
"ledc",
"mcpwm0",
"mcpwm1",
"pcnt",
"peri_backup",
"rmt",
"rng",
"rsa",
"rtc_cntl",
"rtc_i2c",
"rtc_io",
"sens",
"sensitive",
"sha",
"spi0",
"spi1",
"spi2",
"spi3",
"system",
"systimer",
"timg0",
"timg1",
"twai0",
"uart0",
"uart1",
"uart2",
"uhci0",
"uhci1",
"usb0",
"usb_device",
"usb_wrap",
"wcl",
"xts_aes",
]
symbols = [
# Additional peripherals defined by us (the developers):
"adc",
"assist_debug_region_monitor",
"gdma",
"phy",
"bt",
"wifi",
"psram",
"octal_psram",
"ulp_riscv_core",
"timg_timer1",
"very_large_intr_status",
# ROM capabilities
"rom_crc_le",
"rom_crc_be",
"rom_md5_bsd",
# Wakeup SOC based on ESP-IDF:
"pm_support_ext0_wakeup",
"pm_support_ext1_wakeup",
"pm_support_touch_sensor_wakeup",
"pm_support_wifi_wakeup",
"pm_support_bt_wakeup",
"uart_support_wakeup_int",
"ulp_supported",
"riscv_coproc_supported",
]