feat: add display UI with splash screen, dashboard, and RSSI sparkline

Implement full SSD1306 OLED display support:
- Splash screen on boot (1.5s) with project name, version, board
- Dashboard showing radio state, config, counters, RSSI/SNR
- RSSI history sparkline (64-sample ring buffer, 2px-wide bars)
- DisplayOn/DisplayOff host commands routed via dedicated channel
- Pure render functions against generic DrawTarget (no hardware coupling)
- Display on/off control bypasses radio task entirely

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>

vendor/esp32s3/src/apb_saradc/apb_saradc1_data_status.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `APB_SARADC1_DATA_STATUS` reader"]
+pub type R = crate::R<APB_SARADC1_DATA_STATUS_SPEC>;
+#[doc = "Field `SARADC1_DATA` reader - apbsaradc sample data"]
+pub type SARADC1_DATA_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:16 - apbsaradc sample data"]
+    #[inline(always)]
+    pub fn saradc1_data(&self) -> SARADC1_DATA_R {
+        SARADC1_DATA_R::new(self.bits & 0x0001_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("APB_SARADC1_DATA_STATUS")
+            .field("saradc1_data", &self.saradc1_data())
+            .finish()
+    }
+}
+#[doc = "get apb saradc sample data\n\nYou can [`read`](crate::Reg::read) this register and get [`apb_saradc1_data_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct APB_SARADC1_DATA_STATUS_SPEC;
+impl crate::RegisterSpec for APB_SARADC1_DATA_STATUS_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`apb_saradc1_data_status::R`](R) reader structure"]
+impl crate::Readable for APB_SARADC1_DATA_STATUS_SPEC {}
+#[doc = "`reset()` method sets APB_SARADC1_DATA_STATUS to value 0"]
+impl crate::Resettable for APB_SARADC1_DATA_STATUS_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/apb_saradc/apb_saradc2_data_status.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `APB_SARADC2_DATA_STATUS` reader"]
+pub type R = crate::R<APB_SARADC2_DATA_STATUS_SPEC>;
+#[doc = "Field `SARADC2_DATA` reader - apb saradc2 sample data"]
+pub type SARADC2_DATA_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:16 - apb saradc2 sample data"]
+    #[inline(always)]
+    pub fn saradc2_data(&self) -> SARADC2_DATA_R {
+        SARADC2_DATA_R::new(self.bits & 0x0001_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("APB_SARADC2_DATA_STATUS")
+            .field("saradc2_data", &self.saradc2_data())
+            .finish()
+    }
+}
+#[doc = "get apb saradc2 sample data\n\nYou can [`read`](crate::Reg::read) this register and get [`apb_saradc2_data_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct APB_SARADC2_DATA_STATUS_SPEC;
+impl crate::RegisterSpec for APB_SARADC2_DATA_STATUS_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`apb_saradc2_data_status::R`](R) reader structure"]
+impl crate::Readable for APB_SARADC2_DATA_STATUS_SPEC {}
+#[doc = "`reset()` method sets APB_SARADC2_DATA_STATUS to value 0"]
+impl crate::Resettable for APB_SARADC2_DATA_STATUS_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/apb_saradc/arb_ctrl.rs

@@ -0,0 +1,152 @@
+#[doc = "Register `ARB_CTRL` reader"]
+pub type R = crate::R<ARB_CTRL_SPEC>;
+#[doc = "Register `ARB_CTRL` writer"]
+pub type W = crate::W<ARB_CTRL_SPEC>;
+#[doc = "Field `APB_FORCE` reader - adc2 arbiter force to enableapb controller"]
+pub type APB_FORCE_R = crate::BitReader;
+#[doc = "Field `APB_FORCE` writer - adc2 arbiter force to enableapb controller"]
+pub type APB_FORCE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RTC_FORCE` reader - adc2 arbiter force to enable rtc controller"]
+pub type RTC_FORCE_R = crate::BitReader;
+#[doc = "Field `RTC_FORCE` writer - adc2 arbiter force to enable rtc controller"]
+pub type RTC_FORCE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `WIFI_FORCE` reader - adc2 arbiter force to enable wifi controller"]
+pub type WIFI_FORCE_R = crate::BitReader;
+#[doc = "Field `WIFI_FORCE` writer - adc2 arbiter force to enable wifi controller"]
+pub type WIFI_FORCE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `GRANT_FORCE` reader - adc2 arbiter force grant"]
+pub type GRANT_FORCE_R = crate::BitReader;
+#[doc = "Field `GRANT_FORCE` writer - adc2 arbiter force grant"]
+pub type GRANT_FORCE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `APB_PRIORITY` reader - Set adc2 arbiterapb priority"]
+pub type APB_PRIORITY_R = crate::FieldReader;
+#[doc = "Field `APB_PRIORITY` writer - Set adc2 arbiterapb priority"]
+pub type APB_PRIORITY_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `RTC_PRIORITY` reader - Set adc2 arbiter rtc priority"]
+pub type RTC_PRIORITY_R = crate::FieldReader;
+#[doc = "Field `RTC_PRIORITY` writer - Set adc2 arbiter rtc priority"]
+pub type RTC_PRIORITY_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `WIFI_PRIORITY` reader - Set adc2 arbiter wifi priority"]
+pub type WIFI_PRIORITY_R = crate::FieldReader;
+#[doc = "Field `WIFI_PRIORITY` writer - Set adc2 arbiter wifi priority"]
+pub type WIFI_PRIORITY_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `FIX_PRIORITY` reader - adc2 arbiter uses fixed priority"]
+pub type FIX_PRIORITY_R = crate::BitReader;
+#[doc = "Field `FIX_PRIORITY` writer - adc2 arbiter uses fixed priority"]
+pub type FIX_PRIORITY_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 2 - adc2 arbiter force to enableapb controller"]
+    #[inline(always)]
+    pub fn apb_force(&self) -> APB_FORCE_R {
+        APB_FORCE_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - adc2 arbiter force to enable rtc controller"]
+    #[inline(always)]
+    pub fn rtc_force(&self) -> RTC_FORCE_R {
+        RTC_FORCE_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - adc2 arbiter force to enable wifi controller"]
+    #[inline(always)]
+    pub fn wifi_force(&self) -> WIFI_FORCE_R {
+        WIFI_FORCE_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - adc2 arbiter force grant"]
+    #[inline(always)]
+    pub fn grant_force(&self) -> GRANT_FORCE_R {
+        GRANT_FORCE_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bits 6:7 - Set adc2 arbiterapb priority"]
+    #[inline(always)]
+    pub fn apb_priority(&self) -> APB_PRIORITY_R {
+        APB_PRIORITY_R::new(((self.bits >> 6) & 3) as u8)
+    }
+    #[doc = "Bits 8:9 - Set adc2 arbiter rtc priority"]
+    #[inline(always)]
+    pub fn rtc_priority(&self) -> RTC_PRIORITY_R {
+        RTC_PRIORITY_R::new(((self.bits >> 8) & 3) as u8)
+    }
+    #[doc = "Bits 10:11 - Set adc2 arbiter wifi priority"]
+    #[inline(always)]
+    pub fn wifi_priority(&self) -> WIFI_PRIORITY_R {
+        WIFI_PRIORITY_R::new(((self.bits >> 10) & 3) as u8)
+    }
+    #[doc = "Bit 12 - adc2 arbiter uses fixed priority"]
+    #[inline(always)]
+    pub fn fix_priority(&self) -> FIX_PRIORITY_R {
+        FIX_PRIORITY_R::new(((self.bits >> 12) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("ARB_CTRL")
+            .field("apb_force", &self.apb_force())
+            .field("rtc_force", &self.rtc_force())
+            .field("wifi_force", &self.wifi_force())
+            .field("grant_force", &self.grant_force())
+            .field("apb_priority", &self.apb_priority())
+            .field("rtc_priority", &self.rtc_priority())
+            .field("wifi_priority", &self.wifi_priority())
+            .field("fix_priority", &self.fix_priority())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 2 - adc2 arbiter force to enableapb controller"]
+    #[inline(always)]
+    pub fn apb_force(&mut self) -> APB_FORCE_W<ARB_CTRL_SPEC> {
+        APB_FORCE_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - adc2 arbiter force to enable rtc controller"]
+    #[inline(always)]
+    pub fn rtc_force(&mut self) -> RTC_FORCE_W<ARB_CTRL_SPEC> {
+        RTC_FORCE_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - adc2 arbiter force to enable wifi controller"]
+    #[inline(always)]
+    pub fn wifi_force(&mut self) -> WIFI_FORCE_W<ARB_CTRL_SPEC> {
+        WIFI_FORCE_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - adc2 arbiter force grant"]
+    #[inline(always)]
+    pub fn grant_force(&mut self) -> GRANT_FORCE_W<ARB_CTRL_SPEC> {
+        GRANT_FORCE_W::new(self, 5)
+    }
+    #[doc = "Bits 6:7 - Set adc2 arbiterapb priority"]
+    #[inline(always)]
+    pub fn apb_priority(&mut self) -> APB_PRIORITY_W<ARB_CTRL_SPEC> {
+        APB_PRIORITY_W::new(self, 6)
+    }
+    #[doc = "Bits 8:9 - Set adc2 arbiter rtc priority"]
+    #[inline(always)]
+    pub fn rtc_priority(&mut self) -> RTC_PRIORITY_W<ARB_CTRL_SPEC> {
+        RTC_PRIORITY_W::new(self, 8)
+    }
+    #[doc = "Bits 10:11 - Set adc2 arbiter wifi priority"]
+    #[inline(always)]
+    pub fn wifi_priority(&mut self) -> WIFI_PRIORITY_W<ARB_CTRL_SPEC> {
+        WIFI_PRIORITY_W::new(self, 10)
+    }
+    #[doc = "Bit 12 - adc2 arbiter uses fixed priority"]
+    #[inline(always)]
+    pub fn fix_priority(&mut self) -> FIX_PRIORITY_W<ARB_CTRL_SPEC> {
+        FIX_PRIORITY_W::new(self, 12)
+    }
+}
+#[doc = "configure apb saradc arbit\n\nYou can [`read`](crate::Reg::read) this register and get [`arb_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`arb_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ARB_CTRL_SPEC;
+impl crate::RegisterSpec for ARB_CTRL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`arb_ctrl::R`](R) reader structure"]
+impl crate::Readable for ARB_CTRL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`arb_ctrl::W`](W) writer structure"]
+impl crate::Writable for ARB_CTRL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets ARB_CTRL to value 0x0900"]
+impl crate::Resettable for ARB_CTRL_SPEC {
+    const RESET_VALUE: u32 = 0x0900;
+}

vendor/esp32s3/src/apb_saradc/clkm_conf.rs

@@ -0,0 +1,107 @@
+#[doc = "Register `CLKM_CONF` reader"]
+pub type R = crate::R<CLKM_CONF_SPEC>;
+#[doc = "Register `CLKM_CONF` writer"]
+pub type W = crate::W<CLKM_CONF_SPEC>;
+#[doc = "Field `CLKM_DIV_NUM` reader - Integral clock divider value"]
+pub type CLKM_DIV_NUM_R = crate::FieldReader;
+#[doc = "Field `CLKM_DIV_NUM` writer - Integral clock divider value"]
+pub type CLKM_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+#[doc = "Field `CLKM_DIV_B` reader - Fractional clock divider numerator value"]
+pub type CLKM_DIV_B_R = crate::FieldReader;
+#[doc = "Field `CLKM_DIV_B` writer - Fractional clock divider numerator value"]
+pub type CLKM_DIV_B_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
+#[doc = "Field `CLKM_DIV_A` reader - Fractional clock divider denominator value"]
+pub type CLKM_DIV_A_R = crate::FieldReader;
+#[doc = "Field `CLKM_DIV_A` writer - Fractional clock divider denominator value"]
+pub type CLKM_DIV_A_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
+#[doc = "Field `CLK_EN` reader - no public"]
+pub type CLK_EN_R = crate::BitReader;
+#[doc = "Field `CLK_EN` writer - no public"]
+pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CLK_SEL` reader - Set this bit to enable clk_apll"]
+pub type CLK_SEL_R = crate::FieldReader;
+#[doc = "Field `CLK_SEL` writer - Set this bit to enable clk_apll"]
+pub type CLK_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+impl R {
+    #[doc = "Bits 0:7 - Integral clock divider value"]
+    #[inline(always)]
+    pub fn clkm_div_num(&self) -> CLKM_DIV_NUM_R {
+        CLKM_DIV_NUM_R::new((self.bits & 0xff) as u8)
+    }
+    #[doc = "Bits 8:13 - Fractional clock divider numerator value"]
+    #[inline(always)]
+    pub fn clkm_div_b(&self) -> CLKM_DIV_B_R {
+        CLKM_DIV_B_R::new(((self.bits >> 8) & 0x3f) as u8)
+    }
+    #[doc = "Bits 14:19 - Fractional clock divider denominator value"]
+    #[inline(always)]
+    pub fn clkm_div_a(&self) -> CLKM_DIV_A_R {
+        CLKM_DIV_A_R::new(((self.bits >> 14) & 0x3f) as u8)
+    }
+    #[doc = "Bit 20 - no public"]
+    #[inline(always)]
+    pub fn clk_en(&self) -> CLK_EN_R {
+        CLK_EN_R::new(((self.bits >> 20) & 1) != 0)
+    }
+    #[doc = "Bits 21:22 - Set this bit to enable clk_apll"]
+    #[inline(always)]
+    pub fn clk_sel(&self) -> CLK_SEL_R {
+        CLK_SEL_R::new(((self.bits >> 21) & 3) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CLKM_CONF")
+            .field("clkm_div_num", &self.clkm_div_num())
+            .field("clkm_div_b", &self.clkm_div_b())
+            .field("clkm_div_a", &self.clkm_div_a())
+            .field("clk_en", &self.clk_en())
+            .field("clk_sel", &self.clk_sel())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - Integral clock divider value"]
+    #[inline(always)]
+    pub fn clkm_div_num(&mut self) -> CLKM_DIV_NUM_W<CLKM_CONF_SPEC> {
+        CLKM_DIV_NUM_W::new(self, 0)
+    }
+    #[doc = "Bits 8:13 - Fractional clock divider numerator value"]
+    #[inline(always)]
+    pub fn clkm_div_b(&mut self) -> CLKM_DIV_B_W<CLKM_CONF_SPEC> {
+        CLKM_DIV_B_W::new(self, 8)
+    }
+    #[doc = "Bits 14:19 - Fractional clock divider denominator value"]
+    #[inline(always)]
+    pub fn clkm_div_a(&mut self) -> CLKM_DIV_A_W<CLKM_CONF_SPEC> {
+        CLKM_DIV_A_W::new(self, 14)
+    }
+    #[doc = "Bit 20 - no public"]
+    #[inline(always)]
+    pub fn clk_en(&mut self) -> CLK_EN_W<CLKM_CONF_SPEC> {
+        CLK_EN_W::new(self, 20)
+    }
+    #[doc = "Bits 21:22 - Set this bit to enable clk_apll"]
+    #[inline(always)]
+    pub fn clk_sel(&mut self) -> CLK_SEL_W<CLKM_CONF_SPEC> {
+        CLK_SEL_W::new(self, 21)
+    }
+}
+#[doc = "configure apb saradc clock\n\nYou can [`read`](crate::Reg::read) this register and get [`clkm_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkm_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CLKM_CONF_SPEC;
+impl crate::RegisterSpec for CLKM_CONF_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`clkm_conf::R`](R) reader structure"]
+impl crate::Readable for CLKM_CONF_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`clkm_conf::W`](W) writer structure"]
+impl crate::Writable for CLKM_CONF_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CLKM_CONF to value 0x04"]
+impl crate::Resettable for CLKM_CONF_SPEC {
+    const RESET_VALUE: u32 = 0x04;
+}

vendor/esp32s3/src/apb_saradc/ctrl.rs

@@ -0,0 +1,242 @@
+#[doc = "Register `CTRL` reader"]
+pub type R = crate::R<CTRL_SPEC>;
+#[doc = "Register `CTRL` writer"]
+pub type W = crate::W<CTRL_SPEC>;
+#[doc = "Field `START_FORCE` reader - enable start saradc by sw"]
+pub type START_FORCE_R = crate::BitReader;
+#[doc = "Field `START_FORCE` writer - enable start saradc by sw"]
+pub type START_FORCE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `START` reader - start saradc by sw"]
+pub type START_R = crate::BitReader;
+#[doc = "Field `START` writer - start saradc by sw"]
+pub type START_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `WORK_MODE` reader - 0: single mode, 1: double mode, 2: alternate mode"]
+pub type WORK_MODE_R = crate::FieldReader;
+#[doc = "Field `WORK_MODE` writer - 0: single mode, 1: double mode, 2: alternate mode"]
+pub type WORK_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `SAR_SEL` reader - 0: SAR1, 1: SAR2, only work for single SAR mode"]
+pub type SAR_SEL_R = crate::BitReader;
+#[doc = "Field `SAR_SEL` writer - 0: SAR1, 1: SAR2, only work for single SAR mode"]
+pub type SAR_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_CLK_GATED` reader - enable SAR CLK gate when saradc idle"]
+pub type SAR_CLK_GATED_R = crate::BitReader;
+#[doc = "Field `SAR_CLK_GATED` writer - enable SAR CLK gate when saradc idle"]
+pub type SAR_CLK_GATED_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_CLK_DIV` reader - SAR clock divider"]
+pub type SAR_CLK_DIV_R = crate::FieldReader;
+#[doc = "Field `SAR_CLK_DIV` writer - SAR clock divider"]
+pub type SAR_CLK_DIV_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+#[doc = "Field `SAR1_PATT_LEN` reader - 0 ~ 15 means length 1 ~ 16"]
+pub type SAR1_PATT_LEN_R = crate::FieldReader;
+#[doc = "Field `SAR1_PATT_LEN` writer - 0 ~ 15 means length 1 ~ 16"]
+pub type SAR1_PATT_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `SAR2_PATT_LEN` reader - 0 ~ 15 means length 1 ~ 16"]
+pub type SAR2_PATT_LEN_R = crate::FieldReader;
+#[doc = "Field `SAR2_PATT_LEN` writer - 0 ~ 15 means length 1 ~ 16"]
+pub type SAR2_PATT_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `SAR1_PATT_P_CLEAR` reader - clear the pointer of pattern table for DIG ADC1 CTRL"]
+pub type SAR1_PATT_P_CLEAR_R = crate::BitReader;
+#[doc = "Field `SAR1_PATT_P_CLEAR` writer - clear the pointer of pattern table for DIG ADC1 CTRL"]
+pub type SAR1_PATT_P_CLEAR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR2_PATT_P_CLEAR` reader - clear the pointer of pattern table for DIG ADC2 CTRL"]
+pub type SAR2_PATT_P_CLEAR_R = crate::BitReader;
+#[doc = "Field `SAR2_PATT_P_CLEAR` writer - clear the pointer of pattern table for DIG ADC2 CTRL"]
+pub type SAR2_PATT_P_CLEAR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DATA_SAR_SEL` reader - 1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the resolution should not be larger than 11 bits."]
+pub type DATA_SAR_SEL_R = crate::BitReader;
+#[doc = "Field `DATA_SAR_SEL` writer - 1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the resolution should not be larger than 11 bits."]
+pub type DATA_SAR_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DATA_TO_I2S` reader - 1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix"]
+pub type DATA_TO_I2S_R = crate::BitReader;
+#[doc = "Field `DATA_TO_I2S` writer - 1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix"]
+pub type DATA_TO_I2S_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `XPD_SAR_FORCE` reader - force option to xpd sar blocks"]
+pub type XPD_SAR_FORCE_R = crate::FieldReader;
+#[doc = "Field `XPD_SAR_FORCE` writer - force option to xpd sar blocks"]
+pub type XPD_SAR_FORCE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `WAIT_ARB_CYCLE` reader - wait arbit signal stable after sar_done"]
+pub type WAIT_ARB_CYCLE_R = crate::FieldReader;
+#[doc = "Field `WAIT_ARB_CYCLE` writer - wait arbit signal stable after sar_done"]
+pub type WAIT_ARB_CYCLE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+impl R {
+    #[doc = "Bit 0 - enable start saradc by sw"]
+    #[inline(always)]
+    pub fn start_force(&self) -> START_FORCE_R {
+        START_FORCE_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - start saradc by sw"]
+    #[inline(always)]
+    pub fn start(&self) -> START_R {
+        START_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bits 3:4 - 0: single mode, 1: double mode, 2: alternate mode"]
+    #[inline(always)]
+    pub fn work_mode(&self) -> WORK_MODE_R {
+        WORK_MODE_R::new(((self.bits >> 3) & 3) as u8)
+    }
+    #[doc = "Bit 5 - 0: SAR1, 1: SAR2, only work for single SAR mode"]
+    #[inline(always)]
+    pub fn sar_sel(&self) -> SAR_SEL_R {
+        SAR_SEL_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - enable SAR CLK gate when saradc idle"]
+    #[inline(always)]
+    pub fn sar_clk_gated(&self) -> SAR_CLK_GATED_R {
+        SAR_CLK_GATED_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bits 7:14 - SAR clock divider"]
+    #[inline(always)]
+    pub fn sar_clk_div(&self) -> SAR_CLK_DIV_R {
+        SAR_CLK_DIV_R::new(((self.bits >> 7) & 0xff) as u8)
+    }
+    #[doc = "Bits 15:18 - 0 ~ 15 means length 1 ~ 16"]
+    #[inline(always)]
+    pub fn sar1_patt_len(&self) -> SAR1_PATT_LEN_R {
+        SAR1_PATT_LEN_R::new(((self.bits >> 15) & 0x0f) as u8)
+    }
+    #[doc = "Bits 19:22 - 0 ~ 15 means length 1 ~ 16"]
+    #[inline(always)]
+    pub fn sar2_patt_len(&self) -> SAR2_PATT_LEN_R {
+        SAR2_PATT_LEN_R::new(((self.bits >> 19) & 0x0f) as u8)
+    }
+    #[doc = "Bit 23 - clear the pointer of pattern table for DIG ADC1 CTRL"]
+    #[inline(always)]
+    pub fn sar1_patt_p_clear(&self) -> SAR1_PATT_P_CLEAR_R {
+        SAR1_PATT_P_CLEAR_R::new(((self.bits >> 23) & 1) != 0)
+    }
+    #[doc = "Bit 24 - clear the pointer of pattern table for DIG ADC2 CTRL"]
+    #[inline(always)]
+    pub fn sar2_patt_p_clear(&self) -> SAR2_PATT_P_CLEAR_R {
+        SAR2_PATT_P_CLEAR_R::new(((self.bits >> 24) & 1) != 0)
+    }
+    #[doc = "Bit 25 - 1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the resolution should not be larger than 11 bits."]
+    #[inline(always)]
+    pub fn data_sar_sel(&self) -> DATA_SAR_SEL_R {
+        DATA_SAR_SEL_R::new(((self.bits >> 25) & 1) != 0)
+    }
+    #[doc = "Bit 26 - 1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix"]
+    #[inline(always)]
+    pub fn data_to_i2s(&self) -> DATA_TO_I2S_R {
+        DATA_TO_I2S_R::new(((self.bits >> 26) & 1) != 0)
+    }
+    #[doc = "Bits 27:28 - force option to xpd sar blocks"]
+    #[inline(always)]
+    pub fn xpd_sar_force(&self) -> XPD_SAR_FORCE_R {
+        XPD_SAR_FORCE_R::new(((self.bits >> 27) & 3) as u8)
+    }
+    #[doc = "Bits 30:31 - wait arbit signal stable after sar_done"]
+    #[inline(always)]
+    pub fn wait_arb_cycle(&self) -> WAIT_ARB_CYCLE_R {
+        WAIT_ARB_CYCLE_R::new(((self.bits >> 30) & 3) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CTRL")
+            .field("start_force", &self.start_force())
+            .field("start", &self.start())
+            .field("work_mode", &self.work_mode())
+            .field("sar_sel", &self.sar_sel())
+            .field("sar_clk_gated", &self.sar_clk_gated())
+            .field("sar_clk_div", &self.sar_clk_div())
+            .field("sar1_patt_len", &self.sar1_patt_len())
+            .field("sar2_patt_len", &self.sar2_patt_len())
+            .field("sar1_patt_p_clear", &self.sar1_patt_p_clear())
+            .field("sar2_patt_p_clear", &self.sar2_patt_p_clear())
+            .field("data_sar_sel", &self.data_sar_sel())
+            .field("data_to_i2s", &self.data_to_i2s())
+            .field("xpd_sar_force", &self.xpd_sar_force())
+            .field("wait_arb_cycle", &self.wait_arb_cycle())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - enable start saradc by sw"]
+    #[inline(always)]
+    pub fn start_force(&mut self) -> START_FORCE_W<CTRL_SPEC> {
+        START_FORCE_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - start saradc by sw"]
+    #[inline(always)]
+    pub fn start(&mut self) -> START_W<CTRL_SPEC> {
+        START_W::new(self, 1)
+    }
+    #[doc = "Bits 3:4 - 0: single mode, 1: double mode, 2: alternate mode"]
+    #[inline(always)]
+    pub fn work_mode(&mut self) -> WORK_MODE_W<CTRL_SPEC> {
+        WORK_MODE_W::new(self, 3)
+    }
+    #[doc = "Bit 5 - 0: SAR1, 1: SAR2, only work for single SAR mode"]
+    #[inline(always)]
+    pub fn sar_sel(&mut self) -> SAR_SEL_W<CTRL_SPEC> {
+        SAR_SEL_W::new(self, 5)
+    }
+    #[doc = "Bit 6 - enable SAR CLK gate when saradc idle"]
+    #[inline(always)]
+    pub fn sar_clk_gated(&mut self) -> SAR_CLK_GATED_W<CTRL_SPEC> {
+        SAR_CLK_GATED_W::new(self, 6)
+    }
+    #[doc = "Bits 7:14 - SAR clock divider"]
+    #[inline(always)]
+    pub fn sar_clk_div(&mut self) -> SAR_CLK_DIV_W<CTRL_SPEC> {
+        SAR_CLK_DIV_W::new(self, 7)
+    }
+    #[doc = "Bits 15:18 - 0 ~ 15 means length 1 ~ 16"]
+    #[inline(always)]
+    pub fn sar1_patt_len(&mut self) -> SAR1_PATT_LEN_W<CTRL_SPEC> {
+        SAR1_PATT_LEN_W::new(self, 15)
+    }
+    #[doc = "Bits 19:22 - 0 ~ 15 means length 1 ~ 16"]
+    #[inline(always)]
+    pub fn sar2_patt_len(&mut self) -> SAR2_PATT_LEN_W<CTRL_SPEC> {
+        SAR2_PATT_LEN_W::new(self, 19)
+    }
+    #[doc = "Bit 23 - clear the pointer of pattern table for DIG ADC1 CTRL"]
+    #[inline(always)]
+    pub fn sar1_patt_p_clear(&mut self) -> SAR1_PATT_P_CLEAR_W<CTRL_SPEC> {
+        SAR1_PATT_P_CLEAR_W::new(self, 23)
+    }
+    #[doc = "Bit 24 - clear the pointer of pattern table for DIG ADC2 CTRL"]
+    #[inline(always)]
+    pub fn sar2_patt_p_clear(&mut self) -> SAR2_PATT_P_CLEAR_W<CTRL_SPEC> {
+        SAR2_PATT_P_CLEAR_W::new(self, 24)
+    }
+    #[doc = "Bit 25 - 1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the resolution should not be larger than 11 bits."]
+    #[inline(always)]
+    pub fn data_sar_sel(&mut self) -> DATA_SAR_SEL_W<CTRL_SPEC> {
+        DATA_SAR_SEL_W::new(self, 25)
+    }
+    #[doc = "Bit 26 - 1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix"]
+    #[inline(always)]
+    pub fn data_to_i2s(&mut self) -> DATA_TO_I2S_W<CTRL_SPEC> {
+        DATA_TO_I2S_W::new(self, 26)
+    }
+    #[doc = "Bits 27:28 - force option to xpd sar blocks"]
+    #[inline(always)]
+    pub fn xpd_sar_force(&mut self) -> XPD_SAR_FORCE_W<CTRL_SPEC> {
+        XPD_SAR_FORCE_W::new(self, 27)
+    }
+    #[doc = "Bits 30:31 - wait arbit signal stable after sar_done"]
+    #[inline(always)]
+    pub fn wait_arb_cycle(&mut self) -> WAIT_ARB_CYCLE_W<CTRL_SPEC> {
+        WAIT_ARB_CYCLE_W::new(self, 30)
+    }
+}
+#[doc = "configure apb saradc controller\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CTRL_SPEC;
+impl crate::RegisterSpec for CTRL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"]
+impl crate::Readable for CTRL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
+impl crate::Writable for CTRL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CTRL to value 0x407f_8240"]
+impl crate::Resettable for CTRL_SPEC {
+    const RESET_VALUE: u32 = 0x407f_8240;
+}

vendor/esp32s3/src/apb_saradc/ctrl2.rs

@@ -0,0 +1,137 @@
+#[doc = "Register `CTRL2` reader"]
+pub type R = crate::R<CTRL2_SPEC>;
+#[doc = "Register `CTRL2` writer"]
+pub type W = crate::W<CTRL2_SPEC>;
+#[doc = "Field `MEAS_NUM_LIMIT` reader - enable apb saradc limit the sample num"]
+pub type MEAS_NUM_LIMIT_R = crate::BitReader;
+#[doc = "Field `MEAS_NUM_LIMIT` writer - enable apb saradc limit the sample num"]
+pub type MEAS_NUM_LIMIT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `MAX_MEAS_NUM` reader - max conversion number"]
+pub type MAX_MEAS_NUM_R = crate::FieldReader;
+#[doc = "Field `MAX_MEAS_NUM` writer - max conversion number"]
+pub type MAX_MEAS_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+#[doc = "Field `SAR1_INV` reader - 1: data to DIG ADC1 CTRL is inverted, otherwise not"]
+pub type SAR1_INV_R = crate::BitReader;
+#[doc = "Field `SAR1_INV` writer - 1: data to DIG ADC1 CTRL is inverted, otherwise not"]
+pub type SAR1_INV_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR2_INV` reader - 1: data to DIG ADC2 CTRL is inverted, otherwise not"]
+pub type SAR2_INV_R = crate::BitReader;
+#[doc = "Field `SAR2_INV` writer - 1: data to DIG ADC2 CTRL is inverted, otherwise not"]
+pub type SAR2_INV_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER_SEL` reader - 1: select saradc timer 0: i2s_ws trigger"]
+pub type TIMER_SEL_R = crate::BitReader;
+#[doc = "Field `TIMER_SEL` writer - 1: select saradc timer 0: i2s_ws trigger"]
+pub type TIMER_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER_TARGET` reader - to set saradc timer target"]
+pub type TIMER_TARGET_R = crate::FieldReader<u16>;
+#[doc = "Field `TIMER_TARGET` writer - to set saradc timer target"]
+pub type TIMER_TARGET_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
+#[doc = "Field `TIMER_EN` reader - to enable saradc timer trigger"]
+pub type TIMER_EN_R = crate::BitReader;
+#[doc = "Field `TIMER_EN` writer - to enable saradc timer trigger"]
+pub type TIMER_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - enable apb saradc limit the sample num"]
+    #[inline(always)]
+    pub fn meas_num_limit(&self) -> MEAS_NUM_LIMIT_R {
+        MEAS_NUM_LIMIT_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bits 1:8 - max conversion number"]
+    #[inline(always)]
+    pub fn max_meas_num(&self) -> MAX_MEAS_NUM_R {
+        MAX_MEAS_NUM_R::new(((self.bits >> 1) & 0xff) as u8)
+    }
+    #[doc = "Bit 9 - 1: data to DIG ADC1 CTRL is inverted, otherwise not"]
+    #[inline(always)]
+    pub fn sar1_inv(&self) -> SAR1_INV_R {
+        SAR1_INV_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 10 - 1: data to DIG ADC2 CTRL is inverted, otherwise not"]
+    #[inline(always)]
+    pub fn sar2_inv(&self) -> SAR2_INV_R {
+        SAR2_INV_R::new(((self.bits >> 10) & 1) != 0)
+    }
+    #[doc = "Bit 11 - 1: select saradc timer 0: i2s_ws trigger"]
+    #[inline(always)]
+    pub fn timer_sel(&self) -> TIMER_SEL_R {
+        TIMER_SEL_R::new(((self.bits >> 11) & 1) != 0)
+    }
+    #[doc = "Bits 12:23 - to set saradc timer target"]
+    #[inline(always)]
+    pub fn timer_target(&self) -> TIMER_TARGET_R {
+        TIMER_TARGET_R::new(((self.bits >> 12) & 0x0fff) as u16)
+    }
+    #[doc = "Bit 24 - to enable saradc timer trigger"]
+    #[inline(always)]
+    pub fn timer_en(&self) -> TIMER_EN_R {
+        TIMER_EN_R::new(((self.bits >> 24) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CTRL2")
+            .field("meas_num_limit", &self.meas_num_limit())
+            .field("max_meas_num", &self.max_meas_num())
+            .field("sar1_inv", &self.sar1_inv())
+            .field("sar2_inv", &self.sar2_inv())
+            .field("timer_sel", &self.timer_sel())
+            .field("timer_target", &self.timer_target())
+            .field("timer_en", &self.timer_en())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - enable apb saradc limit the sample num"]
+    #[inline(always)]
+    pub fn meas_num_limit(&mut self) -> MEAS_NUM_LIMIT_W<CTRL2_SPEC> {
+        MEAS_NUM_LIMIT_W::new(self, 0)
+    }
+    #[doc = "Bits 1:8 - max conversion number"]
+    #[inline(always)]
+    pub fn max_meas_num(&mut self) -> MAX_MEAS_NUM_W<CTRL2_SPEC> {
+        MAX_MEAS_NUM_W::new(self, 1)
+    }
+    #[doc = "Bit 9 - 1: data to DIG ADC1 CTRL is inverted, otherwise not"]
+    #[inline(always)]
+    pub fn sar1_inv(&mut self) -> SAR1_INV_W<CTRL2_SPEC> {
+        SAR1_INV_W::new(self, 9)
+    }
+    #[doc = "Bit 10 - 1: data to DIG ADC2 CTRL is inverted, otherwise not"]
+    #[inline(always)]
+    pub fn sar2_inv(&mut self) -> SAR2_INV_W<CTRL2_SPEC> {
+        SAR2_INV_W::new(self, 10)
+    }
+    #[doc = "Bit 11 - 1: select saradc timer 0: i2s_ws trigger"]
+    #[inline(always)]
+    pub fn timer_sel(&mut self) -> TIMER_SEL_W<CTRL2_SPEC> {
+        TIMER_SEL_W::new(self, 11)
+    }
+    #[doc = "Bits 12:23 - to set saradc timer target"]
+    #[inline(always)]
+    pub fn timer_target(&mut self) -> TIMER_TARGET_W<CTRL2_SPEC> {
+        TIMER_TARGET_W::new(self, 12)
+    }
+    #[doc = "Bit 24 - to enable saradc timer trigger"]
+    #[inline(always)]
+    pub fn timer_en(&mut self) -> TIMER_EN_W<CTRL2_SPEC> {
+        TIMER_EN_W::new(self, 24)
+    }
+}
+#[doc = "configure apb saradc controller\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CTRL2_SPEC;
+impl crate::RegisterSpec for CTRL2_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`ctrl2::R`](R) reader structure"]
+impl crate::Readable for CTRL2_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`ctrl2::W`](W) writer structure"]
+impl crate::Writable for CTRL2_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CTRL2 to value 0xa1fe"]
+impl crate::Resettable for CTRL2_SPEC {
+    const RESET_VALUE: u32 = 0xa1fe;
+}

vendor/esp32s3/src/apb_saradc/ctrl_date.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `CTRL_DATE` reader"]
+pub type R = crate::R<CTRL_DATE_SPEC>;
+#[doc = "Register `CTRL_DATE` writer"]
+pub type W = crate::W<CTRL_DATE_SPEC>;
+#[doc = "Field `DATE` reader - version"]
+pub type DATE_R = crate::FieldReader<u32>;
+#[doc = "Field `DATE` writer - version"]
+pub type DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - version"]
+    #[inline(always)]
+    pub fn date(&self) -> DATE_R {
+        DATE_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CTRL_DATE")
+            .field("date", &self.date())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - version"]
+    #[inline(always)]
+    pub fn date(&mut self) -> DATE_W<CTRL_DATE_SPEC> {
+        DATE_W::new(self, 0)
+    }
+}
+#[doc = "version\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl_date::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl_date::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CTRL_DATE_SPEC;
+impl crate::RegisterSpec for CTRL_DATE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`ctrl_date::R`](R) reader structure"]
+impl crate::Readable for CTRL_DATE_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`ctrl_date::W`](W) writer structure"]
+impl crate::Writable for CTRL_DATE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CTRL_DATE to value 0x0210_1180"]
+impl crate::Resettable for CTRL_DATE_SPEC {
+    const RESET_VALUE: u32 = 0x0210_1180;
+}

vendor/esp32s3/src/apb_saradc/dma_conf.rs

@@ -0,0 +1,77 @@
+#[doc = "Register `DMA_CONF` reader"]
+pub type R = crate::R<DMA_CONF_SPEC>;
+#[doc = "Register `DMA_CONF` writer"]
+pub type W = crate::W<DMA_CONF_SPEC>;
+#[doc = "Field `ADC_EOF_NUM` reader - the dma_in_suc_eof gen when sample cnt = spi_eof_num"]
+pub type ADC_EOF_NUM_R = crate::FieldReader<u16>;
+#[doc = "Field `ADC_EOF_NUM` writer - the dma_in_suc_eof gen when sample cnt = spi_eof_num"]
+pub type ADC_EOF_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
+#[doc = "Field `ADC_RESET_FSM` reader - reset_apb_adc_state"]
+pub type ADC_RESET_FSM_R = crate::BitReader;
+#[doc = "Field `ADC_RESET_FSM` writer - reset_apb_adc_state"]
+pub type ADC_RESET_FSM_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ADC_TRANS` reader - enable apb_adc use spi_dma"]
+pub type ADC_TRANS_R = crate::BitReader;
+#[doc = "Field `ADC_TRANS` writer - enable apb_adc use spi_dma"]
+pub type ADC_TRANS_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 0:15 - the dma_in_suc_eof gen when sample cnt = spi_eof_num"]
+    #[inline(always)]
+    pub fn adc_eof_num(&self) -> ADC_EOF_NUM_R {
+        ADC_EOF_NUM_R::new((self.bits & 0xffff) as u16)
+    }
+    #[doc = "Bit 30 - reset_apb_adc_state"]
+    #[inline(always)]
+    pub fn adc_reset_fsm(&self) -> ADC_RESET_FSM_R {
+        ADC_RESET_FSM_R::new(((self.bits >> 30) & 1) != 0)
+    }
+    #[doc = "Bit 31 - enable apb_adc use spi_dma"]
+    #[inline(always)]
+    pub fn adc_trans(&self) -> ADC_TRANS_R {
+        ADC_TRANS_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DMA_CONF")
+            .field("adc_eof_num", &self.adc_eof_num())
+            .field("adc_reset_fsm", &self.adc_reset_fsm())
+            .field("adc_trans", &self.adc_trans())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:15 - the dma_in_suc_eof gen when sample cnt = spi_eof_num"]
+    #[inline(always)]
+    pub fn adc_eof_num(&mut self) -> ADC_EOF_NUM_W<DMA_CONF_SPEC> {
+        ADC_EOF_NUM_W::new(self, 0)
+    }
+    #[doc = "Bit 30 - reset_apb_adc_state"]
+    #[inline(always)]
+    pub fn adc_reset_fsm(&mut self) -> ADC_RESET_FSM_W<DMA_CONF_SPEC> {
+        ADC_RESET_FSM_W::new(self, 30)
+    }
+    #[doc = "Bit 31 - enable apb_adc use spi_dma"]
+    #[inline(always)]
+    pub fn adc_trans(&mut self) -> ADC_TRANS_W<DMA_CONF_SPEC> {
+        ADC_TRANS_W::new(self, 31)
+    }
+}
+#[doc = "configure apb saradc dma\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DMA_CONF_SPEC;
+impl crate::RegisterSpec for DMA_CONF_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`dma_conf::R`](R) reader structure"]
+impl crate::Readable for DMA_CONF_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`dma_conf::W`](W) writer structure"]
+impl crate::Writable for DMA_CONF_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DMA_CONF to value 0xff"]
+impl crate::Resettable for DMA_CONF_SPEC {
+    const RESET_VALUE: u32 = 0xff;
+}

vendor/esp32s3/src/apb_saradc/filter_ctrl0.rs

@@ -0,0 +1,77 @@
+#[doc = "Register `FILTER_CTRL0` reader"]
+pub type R = crate::R<FILTER_CTRL0_SPEC>;
+#[doc = "Register `FILTER_CTRL0` writer"]
+pub type W = crate::W<FILTER_CTRL0_SPEC>;
+#[doc = "Field `FILTER_CHANNEL1` reader - configure the filter1 channel"]
+pub type FILTER_CHANNEL1_R = crate::FieldReader;
+#[doc = "Field `FILTER_CHANNEL1` writer - configure the filter1 channel"]
+pub type FILTER_CHANNEL1_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
+#[doc = "Field `FILTER_CHANNEL0` reader - configure the filter0 channel"]
+pub type FILTER_CHANNEL0_R = crate::FieldReader;
+#[doc = "Field `FILTER_CHANNEL0` writer - configure the filter0 channel"]
+pub type FILTER_CHANNEL0_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
+#[doc = "Field `FILTER_RESET` reader - enable apb_adc1_filter"]
+pub type FILTER_RESET_R = crate::BitReader;
+#[doc = "Field `FILTER_RESET` writer - enable apb_adc1_filter"]
+pub type FILTER_RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 14:18 - configure the filter1 channel"]
+    #[inline(always)]
+    pub fn filter_channel1(&self) -> FILTER_CHANNEL1_R {
+        FILTER_CHANNEL1_R::new(((self.bits >> 14) & 0x1f) as u8)
+    }
+    #[doc = "Bits 19:23 - configure the filter0 channel"]
+    #[inline(always)]
+    pub fn filter_channel0(&self) -> FILTER_CHANNEL0_R {
+        FILTER_CHANNEL0_R::new(((self.bits >> 19) & 0x1f) as u8)
+    }
+    #[doc = "Bit 31 - enable apb_adc1_filter"]
+    #[inline(always)]
+    pub fn filter_reset(&self) -> FILTER_RESET_R {
+        FILTER_RESET_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("FILTER_CTRL0")
+            .field("filter_channel1", &self.filter_channel1())
+            .field("filter_channel0", &self.filter_channel0())
+            .field("filter_reset", &self.filter_reset())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 14:18 - configure the filter1 channel"]
+    #[inline(always)]
+    pub fn filter_channel1(&mut self) -> FILTER_CHANNEL1_W<FILTER_CTRL0_SPEC> {
+        FILTER_CHANNEL1_W::new(self, 14)
+    }
+    #[doc = "Bits 19:23 - configure the filter0 channel"]
+    #[inline(always)]
+    pub fn filter_channel0(&mut self) -> FILTER_CHANNEL0_W<FILTER_CTRL0_SPEC> {
+        FILTER_CHANNEL0_W::new(self, 19)
+    }
+    #[doc = "Bit 31 - enable apb_adc1_filter"]
+    #[inline(always)]
+    pub fn filter_reset(&mut self) -> FILTER_RESET_W<FILTER_CTRL0_SPEC> {
+        FILTER_RESET_W::new(self, 31)
+    }
+}
+#[doc = "configure apb saradc arbit\n\nYou can [`read`](crate::Reg::read) this register and get [`filter_ctrl0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`filter_ctrl0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct FILTER_CTRL0_SPEC;
+impl crate::RegisterSpec for FILTER_CTRL0_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`filter_ctrl0::R`](R) reader structure"]
+impl crate::Readable for FILTER_CTRL0_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`filter_ctrl0::W`](W) writer structure"]
+impl crate::Writable for FILTER_CTRL0_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets FILTER_CTRL0 to value 0x006b_4000"]
+impl crate::Resettable for FILTER_CTRL0_SPEC {
+    const RESET_VALUE: u32 = 0x006b_4000;
+}

vendor/esp32s3/src/apb_saradc/filter_ctrl1.rs

@@ -0,0 +1,62 @@
+#[doc = "Register `FILTER_CTRL1` reader"]
+pub type R = crate::R<FILTER_CTRL1_SPEC>;
+#[doc = "Register `FILTER_CTRL1` writer"]
+pub type W = crate::W<FILTER_CTRL1_SPEC>;
+#[doc = "Field `FILTER_FACTOR1` reader - apb saradc factor1"]
+pub type FILTER_FACTOR1_R = crate::FieldReader;
+#[doc = "Field `FILTER_FACTOR1` writer - apb saradc factor1"]
+pub type FILTER_FACTOR1_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `FILTER_FACTOR0` reader - apb saradc factor0"]
+pub type FILTER_FACTOR0_R = crate::FieldReader;
+#[doc = "Field `FILTER_FACTOR0` writer - apb saradc factor0"]
+pub type FILTER_FACTOR0_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+impl R {
+    #[doc = "Bits 26:28 - apb saradc factor1"]
+    #[inline(always)]
+    pub fn filter_factor1(&self) -> FILTER_FACTOR1_R {
+        FILTER_FACTOR1_R::new(((self.bits >> 26) & 7) as u8)
+    }
+    #[doc = "Bits 29:31 - apb saradc factor0"]
+    #[inline(always)]
+    pub fn filter_factor0(&self) -> FILTER_FACTOR0_R {
+        FILTER_FACTOR0_R::new(((self.bits >> 29) & 7) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("FILTER_CTRL1")
+            .field("filter_factor1", &self.filter_factor1())
+            .field("filter_factor0", &self.filter_factor0())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 26:28 - apb saradc factor1"]
+    #[inline(always)]
+    pub fn filter_factor1(&mut self) -> FILTER_FACTOR1_W<FILTER_CTRL1_SPEC> {
+        FILTER_FACTOR1_W::new(self, 26)
+    }
+    #[doc = "Bits 29:31 - apb saradc factor0"]
+    #[inline(always)]
+    pub fn filter_factor0(&mut self) -> FILTER_FACTOR0_W<FILTER_CTRL1_SPEC> {
+        FILTER_FACTOR0_W::new(self, 29)
+    }
+}
+#[doc = "configure saradc filter\n\nYou can [`read`](crate::Reg::read) this register and get [`filter_ctrl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`filter_ctrl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct FILTER_CTRL1_SPEC;
+impl crate::RegisterSpec for FILTER_CTRL1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`filter_ctrl1::R`](R) reader structure"]
+impl crate::Readable for FILTER_CTRL1_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`filter_ctrl1::W`](W) writer structure"]
+impl crate::Writable for FILTER_CTRL1_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets FILTER_CTRL1 to value 0"]
+impl crate::Resettable for FILTER_CTRL1_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/apb_saradc/fsm_wait.rs

@@ -0,0 +1,77 @@
+#[doc = "Register `FSM_WAIT` reader"]
+pub type R = crate::R<FSM_WAIT_SPEC>;
+#[doc = "Register `FSM_WAIT` writer"]
+pub type W = crate::W<FSM_WAIT_SPEC>;
+#[doc = "Field `XPD_WAIT` reader - the cycle which saradc controller in xpd state"]
+pub type XPD_WAIT_R = crate::FieldReader;
+#[doc = "Field `XPD_WAIT` writer - the cycle which saradc controller in xpd state"]
+pub type XPD_WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+#[doc = "Field `RSTB_WAIT` reader - the cycle which saradc controller in rst state"]
+pub type RSTB_WAIT_R = crate::FieldReader;
+#[doc = "Field `RSTB_WAIT` writer - the cycle which saradc controller in rst state"]
+pub type RSTB_WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+#[doc = "Field `STANDBY_WAIT` reader - the cycle which saradc controller in standby state"]
+pub type STANDBY_WAIT_R = crate::FieldReader;
+#[doc = "Field `STANDBY_WAIT` writer - the cycle which saradc controller in standby state"]
+pub type STANDBY_WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+impl R {
+    #[doc = "Bits 0:7 - the cycle which saradc controller in xpd state"]
+    #[inline(always)]
+    pub fn xpd_wait(&self) -> XPD_WAIT_R {
+        XPD_WAIT_R::new((self.bits & 0xff) as u8)
+    }
+    #[doc = "Bits 8:15 - the cycle which saradc controller in rst state"]
+    #[inline(always)]
+    pub fn rstb_wait(&self) -> RSTB_WAIT_R {
+        RSTB_WAIT_R::new(((self.bits >> 8) & 0xff) as u8)
+    }
+    #[doc = "Bits 16:23 - the cycle which saradc controller in standby state"]
+    #[inline(always)]
+    pub fn standby_wait(&self) -> STANDBY_WAIT_R {
+        STANDBY_WAIT_R::new(((self.bits >> 16) & 0xff) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("FSM_WAIT")
+            .field("xpd_wait", &self.xpd_wait())
+            .field("rstb_wait", &self.rstb_wait())
+            .field("standby_wait", &self.standby_wait())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - the cycle which saradc controller in xpd state"]
+    #[inline(always)]
+    pub fn xpd_wait(&mut self) -> XPD_WAIT_W<FSM_WAIT_SPEC> {
+        XPD_WAIT_W::new(self, 0)
+    }
+    #[doc = "Bits 8:15 - the cycle which saradc controller in rst state"]
+    #[inline(always)]
+    pub fn rstb_wait(&mut self) -> RSTB_WAIT_W<FSM_WAIT_SPEC> {
+        RSTB_WAIT_W::new(self, 8)
+    }
+    #[doc = "Bits 16:23 - the cycle which saradc controller in standby state"]
+    #[inline(always)]
+    pub fn standby_wait(&mut self) -> STANDBY_WAIT_W<FSM_WAIT_SPEC> {
+        STANDBY_WAIT_W::new(self, 16)
+    }
+}
+#[doc = "configure apb saradc fsm\n\nYou can [`read`](crate::Reg::read) this register and get [`fsm_wait::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fsm_wait::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct FSM_WAIT_SPEC;
+impl crate::RegisterSpec for FSM_WAIT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`fsm_wait::R`](R) reader structure"]
+impl crate::Readable for FSM_WAIT_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`fsm_wait::W`](W) writer structure"]
+impl crate::Writable for FSM_WAIT_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets FSM_WAIT to value 0x00ff_0808"]
+impl crate::Resettable for FSM_WAIT_SPEC {
+    const RESET_VALUE: u32 = 0x00ff_0808;
+}

vendor/esp32s3/src/apb_saradc/int_clr.rs

@@ -0,0 +1,67 @@
+#[doc = "Register `INT_CLR` writer"]
+pub type W = crate::W<INT_CLR_SPEC>;
+#[doc = "Field `THRES1_LOW` writer - interrupt of thres1 low"]
+pub type THRES1_LOW_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `THRES0_LOW` writer - interrupt of thres0 low"]
+pub type THRES0_LOW_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `THRES1_HIGH` writer - interrupt of thres1 high"]
+pub type THRES1_HIGH_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `THRES0_HIGH` writer - interrupt of thres0 high"]
+pub type THRES0_HIGH_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `ADC2_DONE` writer - interrupt of sar2 done"]
+pub type ADC2_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `ADC1_DONE` writer - interrupt of sar1 done"]
+pub type ADC1_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "(not readable)")
+    }
+}
+impl W {
+    #[doc = "Bit 26 - interrupt of thres1 low"]
+    #[inline(always)]
+    pub fn thres1_low(&mut self) -> THRES1_LOW_W<INT_CLR_SPEC> {
+        THRES1_LOW_W::new(self, 26)
+    }
+    #[doc = "Bit 27 - interrupt of thres0 low"]
+    #[inline(always)]
+    pub fn thres0_low(&mut self) -> THRES0_LOW_W<INT_CLR_SPEC> {
+        THRES0_LOW_W::new(self, 27)
+    }
+    #[doc = "Bit 28 - interrupt of thres1 high"]
+    #[inline(always)]
+    pub fn thres1_high(&mut self) -> THRES1_HIGH_W<INT_CLR_SPEC> {
+        THRES1_HIGH_W::new(self, 28)
+    }
+    #[doc = "Bit 29 - interrupt of thres0 high"]
+    #[inline(always)]
+    pub fn thres0_high(&mut self) -> THRES0_HIGH_W<INT_CLR_SPEC> {
+        THRES0_HIGH_W::new(self, 29)
+    }
+    #[doc = "Bit 30 - interrupt of sar2 done"]
+    #[inline(always)]
+    pub fn adc2_done(&mut self) -> ADC2_DONE_W<INT_CLR_SPEC> {
+        ADC2_DONE_W::new(self, 30)
+    }
+    #[doc = "Bit 31 - interrupt of sar1 done"]
+    #[inline(always)]
+    pub fn adc1_done(&mut self) -> ADC1_DONE_W<INT_CLR_SPEC> {
+        ADC1_DONE_W::new(self, 31)
+    }
+}
+#[doc = "clear interrupt\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct INT_CLR_SPEC;
+impl crate::RegisterSpec for INT_CLR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
+impl crate::Writable for INT_CLR_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xfc00_0000;
+}
+#[doc = "`reset()` method sets INT_CLR to value 0"]
+impl crate::Resettable for INT_CLR_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/apb_saradc/int_ena.rs

@@ -0,0 +1,122 @@
+#[doc = "Register `INT_ENA` reader"]
+pub type R = crate::R<INT_ENA_SPEC>;
+#[doc = "Register `INT_ENA` writer"]
+pub type W = crate::W<INT_ENA_SPEC>;
+#[doc = "Field `THRES1_LOW` reader - interrupt of thres1 low"]
+pub type THRES1_LOW_R = crate::BitReader;
+#[doc = "Field `THRES1_LOW` writer - interrupt of thres1 low"]
+pub type THRES1_LOW_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `THRES0_LOW` reader - interrupt of thres0 low"]
+pub type THRES0_LOW_R = crate::BitReader;
+#[doc = "Field `THRES0_LOW` writer - interrupt of thres0 low"]
+pub type THRES0_LOW_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `THRES1_HIGH` reader - interrupt of thres1 high"]
+pub type THRES1_HIGH_R = crate::BitReader;
+#[doc = "Field `THRES1_HIGH` writer - interrupt of thres1 high"]
+pub type THRES1_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `THRES0_HIGH` reader - interrupt of thres0 high"]
+pub type THRES0_HIGH_R = crate::BitReader;
+#[doc = "Field `THRES0_HIGH` writer - interrupt of thres0 high"]
+pub type THRES0_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ADC2_DONE` reader - interrupt of sar2 done"]
+pub type ADC2_DONE_R = crate::BitReader;
+#[doc = "Field `ADC2_DONE` writer - interrupt of sar2 done"]
+pub type ADC2_DONE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ADC1_DONE` reader - interrupt of sar1 done"]
+pub type ADC1_DONE_R = crate::BitReader;
+#[doc = "Field `ADC1_DONE` writer - interrupt of sar1 done"]
+pub type ADC1_DONE_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 26 - interrupt of thres1 low"]
+    #[inline(always)]
+    pub fn thres1_low(&self) -> THRES1_LOW_R {
+        THRES1_LOW_R::new(((self.bits >> 26) & 1) != 0)
+    }
+    #[doc = "Bit 27 - interrupt of thres0 low"]
+    #[inline(always)]
+    pub fn thres0_low(&self) -> THRES0_LOW_R {
+        THRES0_LOW_R::new(((self.bits >> 27) & 1) != 0)
+    }
+    #[doc = "Bit 28 - interrupt of thres1 high"]
+    #[inline(always)]
+    pub fn thres1_high(&self) -> THRES1_HIGH_R {
+        THRES1_HIGH_R::new(((self.bits >> 28) & 1) != 0)
+    }
+    #[doc = "Bit 29 - interrupt of thres0 high"]
+    #[inline(always)]
+    pub fn thres0_high(&self) -> THRES0_HIGH_R {
+        THRES0_HIGH_R::new(((self.bits >> 29) & 1) != 0)
+    }
+    #[doc = "Bit 30 - interrupt of sar2 done"]
+    #[inline(always)]
+    pub fn adc2_done(&self) -> ADC2_DONE_R {
+        ADC2_DONE_R::new(((self.bits >> 30) & 1) != 0)
+    }
+    #[doc = "Bit 31 - interrupt of sar1 done"]
+    #[inline(always)]
+    pub fn adc1_done(&self) -> ADC1_DONE_R {
+        ADC1_DONE_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("INT_ENA")
+            .field("thres1_low", &self.thres1_low())
+            .field("thres0_low", &self.thres0_low())
+            .field("thres1_high", &self.thres1_high())
+            .field("thres0_high", &self.thres0_high())
+            .field("adc2_done", &self.adc2_done())
+            .field("adc1_done", &self.adc1_done())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 26 - interrupt of thres1 low"]
+    #[inline(always)]
+    pub fn thres1_low(&mut self) -> THRES1_LOW_W<INT_ENA_SPEC> {
+        THRES1_LOW_W::new(self, 26)
+    }
+    #[doc = "Bit 27 - interrupt of thres0 low"]
+    #[inline(always)]
+    pub fn thres0_low(&mut self) -> THRES0_LOW_W<INT_ENA_SPEC> {
+        THRES0_LOW_W::new(self, 27)
+    }
+    #[doc = "Bit 28 - interrupt of thres1 high"]
+    #[inline(always)]
+    pub fn thres1_high(&mut self) -> THRES1_HIGH_W<INT_ENA_SPEC> {
+        THRES1_HIGH_W::new(self, 28)
+    }
+    #[doc = "Bit 29 - interrupt of thres0 high"]
+    #[inline(always)]
+    pub fn thres0_high(&mut self) -> THRES0_HIGH_W<INT_ENA_SPEC> {
+        THRES0_HIGH_W::new(self, 29)
+    }
+    #[doc = "Bit 30 - interrupt of sar2 done"]
+    #[inline(always)]
+    pub fn adc2_done(&mut self) -> ADC2_DONE_W<INT_ENA_SPEC> {
+        ADC2_DONE_W::new(self, 30)
+    }
+    #[doc = "Bit 31 - interrupt of sar1 done"]
+    #[inline(always)]
+    pub fn adc1_done(&mut self) -> ADC1_DONE_W<INT_ENA_SPEC> {
+        ADC1_DONE_W::new(self, 31)
+    }
+}
+#[doc = "enable interrupt\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct INT_ENA_SPEC;
+impl crate::RegisterSpec for INT_ENA_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"]
+impl crate::Readable for INT_ENA_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"]
+impl crate::Writable for INT_ENA_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets INT_ENA to value 0"]
+impl crate::Resettable for INT_ENA_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/apb_saradc/int_raw.rs

@@ -0,0 +1,70 @@
+#[doc = "Register `INT_RAW` reader"]
+pub type R = crate::R<INT_RAW_SPEC>;
+#[doc = "Field `THRES1_LOW` reader - interrupt of thres1 low"]
+pub type THRES1_LOW_R = crate::BitReader;
+#[doc = "Field `THRES0_LOW` reader - interrupt of thres0 low"]
+pub type THRES0_LOW_R = crate::BitReader;
+#[doc = "Field `THRES1_HIGH` reader - interrupt of thres1 high"]
+pub type THRES1_HIGH_R = crate::BitReader;
+#[doc = "Field `THRES0_HIGH` reader - interrupt of thres0 high"]
+pub type THRES0_HIGH_R = crate::BitReader;
+#[doc = "Field `ADC2_DONE` reader - interrupt of sar2 done"]
+pub type ADC2_DONE_R = crate::BitReader;
+#[doc = "Field `ADC1_DONE` reader - interrupt of sar1 done"]
+pub type ADC1_DONE_R = crate::BitReader;
+impl R {
+    #[doc = "Bit 26 - interrupt of thres1 low"]
+    #[inline(always)]
+    pub fn thres1_low(&self) -> THRES1_LOW_R {
+        THRES1_LOW_R::new(((self.bits >> 26) & 1) != 0)
+    }
+    #[doc = "Bit 27 - interrupt of thres0 low"]
+    #[inline(always)]
+    pub fn thres0_low(&self) -> THRES0_LOW_R {
+        THRES0_LOW_R::new(((self.bits >> 27) & 1) != 0)
+    }
+    #[doc = "Bit 28 - interrupt of thres1 high"]
+    #[inline(always)]
+    pub fn thres1_high(&self) -> THRES1_HIGH_R {
+        THRES1_HIGH_R::new(((self.bits >> 28) & 1) != 0)
+    }
+    #[doc = "Bit 29 - interrupt of thres0 high"]
+    #[inline(always)]
+    pub fn thres0_high(&self) -> THRES0_HIGH_R {
+        THRES0_HIGH_R::new(((self.bits >> 29) & 1) != 0)
+    }
+    #[doc = "Bit 30 - interrupt of sar2 done"]
+    #[inline(always)]
+    pub fn adc2_done(&self) -> ADC2_DONE_R {
+        ADC2_DONE_R::new(((self.bits >> 30) & 1) != 0)
+    }
+    #[doc = "Bit 31 - interrupt of sar1 done"]
+    #[inline(always)]
+    pub fn adc1_done(&self) -> ADC1_DONE_R {
+        ADC1_DONE_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("INT_RAW")
+            .field("thres1_low", &self.thres1_low())
+            .field("thres0_low", &self.thres0_low())
+            .field("thres1_high", &self.thres1_high())
+            .field("thres0_high", &self.thres0_high())
+            .field("adc2_done", &self.adc2_done())
+            .field("adc1_done", &self.adc1_done())
+            .finish()
+    }
+}
+#[doc = "raw of interrupt\n\nYou can [`read`](crate::Reg::read) this register and get [`int_raw::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct INT_RAW_SPEC;
+impl crate::RegisterSpec for INT_RAW_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"]
+impl crate::Readable for INT_RAW_SPEC {}
+#[doc = "`reset()` method sets INT_RAW to value 0"]
+impl crate::Resettable for INT_RAW_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/apb_saradc/int_st.rs

@@ -0,0 +1,70 @@
+#[doc = "Register `INT_ST` reader"]
+pub type R = crate::R<INT_ST_SPEC>;
+#[doc = "Field `THRES1_LOW` reader - interrupt of thres1 low"]
+pub type THRES1_LOW_R = crate::BitReader;
+#[doc = "Field `THRES0_LOW` reader - interrupt of thres0 low"]
+pub type THRES0_LOW_R = crate::BitReader;
+#[doc = "Field `THRES1_HIGH` reader - interrupt of thres1 high"]
+pub type THRES1_HIGH_R = crate::BitReader;
+#[doc = "Field `THRES0_HIGH` reader - interrupt of thres0 high"]
+pub type THRES0_HIGH_R = crate::BitReader;
+#[doc = "Field `ADC2_DONE` reader - interrupt of sar2 done"]
+pub type ADC2_DONE_R = crate::BitReader;
+#[doc = "Field `ADC1_DONE` reader - interrupt of sar1 done"]
+pub type ADC1_DONE_R = crate::BitReader;
+impl R {
+    #[doc = "Bit 26 - interrupt of thres1 low"]
+    #[inline(always)]
+    pub fn thres1_low(&self) -> THRES1_LOW_R {
+        THRES1_LOW_R::new(((self.bits >> 26) & 1) != 0)
+    }
+    #[doc = "Bit 27 - interrupt of thres0 low"]
+    #[inline(always)]
+    pub fn thres0_low(&self) -> THRES0_LOW_R {
+        THRES0_LOW_R::new(((self.bits >> 27) & 1) != 0)
+    }
+    #[doc = "Bit 28 - interrupt of thres1 high"]
+    #[inline(always)]
+    pub fn thres1_high(&self) -> THRES1_HIGH_R {
+        THRES1_HIGH_R::new(((self.bits >> 28) & 1) != 0)
+    }
+    #[doc = "Bit 29 - interrupt of thres0 high"]
+    #[inline(always)]
+    pub fn thres0_high(&self) -> THRES0_HIGH_R {
+        THRES0_HIGH_R::new(((self.bits >> 29) & 1) != 0)
+    }
+    #[doc = "Bit 30 - interrupt of sar2 done"]
+    #[inline(always)]
+    pub fn adc2_done(&self) -> ADC2_DONE_R {
+        ADC2_DONE_R::new(((self.bits >> 30) & 1) != 0)
+    }
+    #[doc = "Bit 31 - interrupt of sar1 done"]
+    #[inline(always)]
+    pub fn adc1_done(&self) -> ADC1_DONE_R {
+        ADC1_DONE_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("INT_ST")
+            .field("thres1_low", &self.thres1_low())
+            .field("thres0_low", &self.thres0_low())
+            .field("thres1_high", &self.thres1_high())
+            .field("thres0_high", &self.thres0_high())
+            .field("adc2_done", &self.adc2_done())
+            .field("adc1_done", &self.adc1_done())
+            .finish()
+    }
+}
+#[doc = "state of interrupt\n\nYou can [`read`](crate::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct INT_ST_SPEC;
+impl crate::RegisterSpec for INT_ST_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`int_st::R`](R) reader structure"]
+impl crate::Readable for INT_ST_SPEC {}
+#[doc = "`reset()` method sets INT_ST to value 0"]
+impl crate::Resettable for INT_ST_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/apb_saradc/sar1_patt_tab1.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `SAR1_PATT_TAB1` reader"]
+pub type R = crate::R<SAR1_PATT_TAB1_SPEC>;
+#[doc = "Register `SAR1_PATT_TAB1` writer"]
+pub type W = crate::W<SAR1_PATT_TAB1_SPEC>;
+#[doc = "Field `SAR1_PATT_TAB1` reader - item 0 ~ 3 for pattern table 1 (each item 6bit)"]
+pub type SAR1_PATT_TAB1_R = crate::FieldReader<u32>;
+#[doc = "Field `SAR1_PATT_TAB1` writer - item 0 ~ 3 for pattern table 1 (each item 6bit)"]
+pub type SAR1_PATT_TAB1_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
+impl R {
+    #[doc = "Bits 0:23 - item 0 ~ 3 for pattern table 1 (each item 6bit)"]
+    #[inline(always)]
+    pub fn sar1_patt_tab1(&self) -> SAR1_PATT_TAB1_R {
+        SAR1_PATT_TAB1_R::new(self.bits & 0x00ff_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR1_PATT_TAB1")
+            .field("sar1_patt_tab1", &self.sar1_patt_tab1())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:23 - item 0 ~ 3 for pattern table 1 (each item 6bit)"]
+    #[inline(always)]
+    pub fn sar1_patt_tab1(&mut self) -> SAR1_PATT_TAB1_W<SAR1_PATT_TAB1_SPEC> {
+        SAR1_PATT_TAB1_W::new(self, 0)
+    }
+}
+#[doc = "configure apb saradc pattern table\n\nYou can [`read`](crate::Reg::read) this register and get [`sar1_patt_tab1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar1_patt_tab1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR1_PATT_TAB1_SPEC;
+impl crate::RegisterSpec for SAR1_PATT_TAB1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar1_patt_tab1::R`](R) reader structure"]
+impl crate::Readable for SAR1_PATT_TAB1_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sar1_patt_tab1::W`](W) writer structure"]
+impl crate::Writable for SAR1_PATT_TAB1_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SAR1_PATT_TAB1 to value 0"]
+impl crate::Resettable for SAR1_PATT_TAB1_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/apb_saradc/sar1_patt_tab2.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `SAR1_PATT_TAB2` reader"]
+pub type R = crate::R<SAR1_PATT_TAB2_SPEC>;
+#[doc = "Register `SAR1_PATT_TAB2` writer"]
+pub type W = crate::W<SAR1_PATT_TAB2_SPEC>;
+#[doc = "Field `SAR1_PATT_TAB2` reader - Item 4 ~ 7 for pattern table 1 (each item 6bit)"]
+pub type SAR1_PATT_TAB2_R = crate::FieldReader<u32>;
+#[doc = "Field `SAR1_PATT_TAB2` writer - Item 4 ~ 7 for pattern table 1 (each item 6bit)"]
+pub type SAR1_PATT_TAB2_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
+impl R {
+    #[doc = "Bits 0:23 - Item 4 ~ 7 for pattern table 1 (each item 6bit)"]
+    #[inline(always)]
+    pub fn sar1_patt_tab2(&self) -> SAR1_PATT_TAB2_R {
+        SAR1_PATT_TAB2_R::new(self.bits & 0x00ff_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR1_PATT_TAB2")
+            .field("sar1_patt_tab2", &self.sar1_patt_tab2())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:23 - Item 4 ~ 7 for pattern table 1 (each item 6bit)"]
+    #[inline(always)]
+    pub fn sar1_patt_tab2(&mut self) -> SAR1_PATT_TAB2_W<SAR1_PATT_TAB2_SPEC> {
+        SAR1_PATT_TAB2_W::new(self, 0)
+    }
+}
+#[doc = "configure apb saradc pattern table\n\nYou can [`read`](crate::Reg::read) this register and get [`sar1_patt_tab2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar1_patt_tab2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR1_PATT_TAB2_SPEC;
+impl crate::RegisterSpec for SAR1_PATT_TAB2_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar1_patt_tab2::R`](R) reader structure"]
+impl crate::Readable for SAR1_PATT_TAB2_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sar1_patt_tab2::W`](W) writer structure"]
+impl crate::Writable for SAR1_PATT_TAB2_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SAR1_PATT_TAB2 to value 0"]
+impl crate::Resettable for SAR1_PATT_TAB2_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/apb_saradc/sar1_patt_tab3.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `SAR1_PATT_TAB3` reader"]
+pub type R = crate::R<SAR1_PATT_TAB3_SPEC>;
+#[doc = "Register `SAR1_PATT_TAB3` writer"]
+pub type W = crate::W<SAR1_PATT_TAB3_SPEC>;
+#[doc = "Field `SAR1_PATT_TAB3` reader - Item 8 ~ 11 for pattern table 1 (each item 6bit)"]
+pub type SAR1_PATT_TAB3_R = crate::FieldReader<u32>;
+#[doc = "Field `SAR1_PATT_TAB3` writer - Item 8 ~ 11 for pattern table 1 (each item 6bit)"]
+pub type SAR1_PATT_TAB3_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
+impl R {
+    #[doc = "Bits 0:23 - Item 8 ~ 11 for pattern table 1 (each item 6bit)"]
+    #[inline(always)]
+    pub fn sar1_patt_tab3(&self) -> SAR1_PATT_TAB3_R {
+        SAR1_PATT_TAB3_R::new(self.bits & 0x00ff_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR1_PATT_TAB3")
+            .field("sar1_patt_tab3", &self.sar1_patt_tab3())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:23 - Item 8 ~ 11 for pattern table 1 (each item 6bit)"]
+    #[inline(always)]
+    pub fn sar1_patt_tab3(&mut self) -> SAR1_PATT_TAB3_W<SAR1_PATT_TAB3_SPEC> {
+        SAR1_PATT_TAB3_W::new(self, 0)
+    }
+}
+#[doc = "configure apb saradc pattern table\n\nYou can [`read`](crate::Reg::read) this register and get [`sar1_patt_tab3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar1_patt_tab3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR1_PATT_TAB3_SPEC;
+impl crate::RegisterSpec for SAR1_PATT_TAB3_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar1_patt_tab3::R`](R) reader structure"]
+impl crate::Readable for SAR1_PATT_TAB3_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sar1_patt_tab3::W`](W) writer structure"]
+impl crate::Writable for SAR1_PATT_TAB3_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SAR1_PATT_TAB3 to value 0"]
+impl crate::Resettable for SAR1_PATT_TAB3_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/apb_saradc/sar1_patt_tab4.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `SAR1_PATT_TAB4` reader"]
+pub type R = crate::R<SAR1_PATT_TAB4_SPEC>;
+#[doc = "Register `SAR1_PATT_TAB4` writer"]
+pub type W = crate::W<SAR1_PATT_TAB4_SPEC>;
+#[doc = "Field `SAR1_PATT_TAB4` reader - Item 12 ~ 15 for pattern table 1 (each item 6bit)"]
+pub type SAR1_PATT_TAB4_R = crate::FieldReader<u32>;
+#[doc = "Field `SAR1_PATT_TAB4` writer - Item 12 ~ 15 for pattern table 1 (each item 6bit)"]
+pub type SAR1_PATT_TAB4_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
+impl R {
+    #[doc = "Bits 0:23 - Item 12 ~ 15 for pattern table 1 (each item 6bit)"]
+    #[inline(always)]
+    pub fn sar1_patt_tab4(&self) -> SAR1_PATT_TAB4_R {
+        SAR1_PATT_TAB4_R::new(self.bits & 0x00ff_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR1_PATT_TAB4")
+            .field("sar1_patt_tab4", &self.sar1_patt_tab4())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:23 - Item 12 ~ 15 for pattern table 1 (each item 6bit)"]
+    #[inline(always)]
+    pub fn sar1_patt_tab4(&mut self) -> SAR1_PATT_TAB4_W<SAR1_PATT_TAB4_SPEC> {
+        SAR1_PATT_TAB4_W::new(self, 0)
+    }
+}
+#[doc = "configure apb saradc pattern table\n\nYou can [`read`](crate::Reg::read) this register and get [`sar1_patt_tab4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar1_patt_tab4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR1_PATT_TAB4_SPEC;
+impl crate::RegisterSpec for SAR1_PATT_TAB4_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar1_patt_tab4::R`](R) reader structure"]
+impl crate::Readable for SAR1_PATT_TAB4_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sar1_patt_tab4::W`](W) writer structure"]
+impl crate::Writable for SAR1_PATT_TAB4_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SAR1_PATT_TAB4 to value 0"]
+impl crate::Resettable for SAR1_PATT_TAB4_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/apb_saradc/sar1_status.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `SAR1_STATUS` reader"]
+pub type R = crate::R<SAR1_STATUS_SPEC>;
+#[doc = "Field `SAR1_STATUS` reader - saradc1 status"]
+pub type SAR1_STATUS_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - saradc1 status"]
+    #[inline(always)]
+    pub fn sar1_status(&self) -> SAR1_STATUS_R {
+        SAR1_STATUS_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR1_STATUS")
+            .field("sar1_status", &self.sar1_status())
+            .finish()
+    }
+}
+#[doc = "saradc1 status for debug\n\nYou can [`read`](crate::Reg::read) this register and get [`sar1_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR1_STATUS_SPEC;
+impl crate::RegisterSpec for SAR1_STATUS_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar1_status::R`](R) reader structure"]
+impl crate::Readable for SAR1_STATUS_SPEC {}
+#[doc = "`reset()` method sets SAR1_STATUS to value 0"]
+impl crate::Resettable for SAR1_STATUS_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/apb_saradc/sar2_patt_tab1.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `SAR2_PATT_TAB1` reader"]
+pub type R = crate::R<SAR2_PATT_TAB1_SPEC>;
+#[doc = "Register `SAR2_PATT_TAB1` writer"]
+pub type W = crate::W<SAR2_PATT_TAB1_SPEC>;
+#[doc = "Field `SAR2_PATT_TAB1` reader - item 0 ~ 3 for pattern table 2 (each item 6bit)"]
+pub type SAR2_PATT_TAB1_R = crate::FieldReader<u32>;
+#[doc = "Field `SAR2_PATT_TAB1` writer - item 0 ~ 3 for pattern table 2 (each item 6bit)"]
+pub type SAR2_PATT_TAB1_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
+impl R {
+    #[doc = "Bits 0:23 - item 0 ~ 3 for pattern table 2 (each item 6bit)"]
+    #[inline(always)]
+    pub fn sar2_patt_tab1(&self) -> SAR2_PATT_TAB1_R {
+        SAR2_PATT_TAB1_R::new(self.bits & 0x00ff_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR2_PATT_TAB1")
+            .field("sar2_patt_tab1", &self.sar2_patt_tab1())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:23 - item 0 ~ 3 for pattern table 2 (each item 6bit)"]
+    #[inline(always)]
+    pub fn sar2_patt_tab1(&mut self) -> SAR2_PATT_TAB1_W<SAR2_PATT_TAB1_SPEC> {
+        SAR2_PATT_TAB1_W::new(self, 0)
+    }
+}
+#[doc = "configure apb saradc pattern table\n\nYou can [`read`](crate::Reg::read) this register and get [`sar2_patt_tab1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar2_patt_tab1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR2_PATT_TAB1_SPEC;
+impl crate::RegisterSpec for SAR2_PATT_TAB1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar2_patt_tab1::R`](R) reader structure"]
+impl crate::Readable for SAR2_PATT_TAB1_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sar2_patt_tab1::W`](W) writer structure"]
+impl crate::Writable for SAR2_PATT_TAB1_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SAR2_PATT_TAB1 to value 0"]
+impl crate::Resettable for SAR2_PATT_TAB1_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/apb_saradc/sar2_patt_tab2.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `SAR2_PATT_TAB2` reader"]
+pub type R = crate::R<SAR2_PATT_TAB2_SPEC>;
+#[doc = "Register `SAR2_PATT_TAB2` writer"]
+pub type W = crate::W<SAR2_PATT_TAB2_SPEC>;
+#[doc = "Field `SAR2_PATT_TAB2` reader - Item 4 ~ 7 for pattern table 2 (each item 6bit)"]
+pub type SAR2_PATT_TAB2_R = crate::FieldReader<u32>;
+#[doc = "Field `SAR2_PATT_TAB2` writer - Item 4 ~ 7 for pattern table 2 (each item 6bit)"]
+pub type SAR2_PATT_TAB2_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
+impl R {
+    #[doc = "Bits 0:23 - Item 4 ~ 7 for pattern table 2 (each item 6bit)"]
+    #[inline(always)]
+    pub fn sar2_patt_tab2(&self) -> SAR2_PATT_TAB2_R {
+        SAR2_PATT_TAB2_R::new(self.bits & 0x00ff_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR2_PATT_TAB2")
+            .field("sar2_patt_tab2", &self.sar2_patt_tab2())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:23 - Item 4 ~ 7 for pattern table 2 (each item 6bit)"]
+    #[inline(always)]
+    pub fn sar2_patt_tab2(&mut self) -> SAR2_PATT_TAB2_W<SAR2_PATT_TAB2_SPEC> {
+        SAR2_PATT_TAB2_W::new(self, 0)
+    }
+}
+#[doc = "configure apb saradc pattern table\n\nYou can [`read`](crate::Reg::read) this register and get [`sar2_patt_tab2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar2_patt_tab2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR2_PATT_TAB2_SPEC;
+impl crate::RegisterSpec for SAR2_PATT_TAB2_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar2_patt_tab2::R`](R) reader structure"]
+impl crate::Readable for SAR2_PATT_TAB2_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sar2_patt_tab2::W`](W) writer structure"]
+impl crate::Writable for SAR2_PATT_TAB2_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SAR2_PATT_TAB2 to value 0"]
+impl crate::Resettable for SAR2_PATT_TAB2_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/apb_saradc/sar2_patt_tab3.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `SAR2_PATT_TAB3` reader"]
+pub type R = crate::R<SAR2_PATT_TAB3_SPEC>;
+#[doc = "Register `SAR2_PATT_TAB3` writer"]
+pub type W = crate::W<SAR2_PATT_TAB3_SPEC>;
+#[doc = "Field `SAR2_PATT_TAB3` reader - Item 8 ~ 11 for pattern table 2 (each item 6bit)"]
+pub type SAR2_PATT_TAB3_R = crate::FieldReader<u32>;
+#[doc = "Field `SAR2_PATT_TAB3` writer - Item 8 ~ 11 for pattern table 2 (each item 6bit)"]
+pub type SAR2_PATT_TAB3_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
+impl R {
+    #[doc = "Bits 0:23 - Item 8 ~ 11 for pattern table 2 (each item 6bit)"]
+    #[inline(always)]
+    pub fn sar2_patt_tab3(&self) -> SAR2_PATT_TAB3_R {
+        SAR2_PATT_TAB3_R::new(self.bits & 0x00ff_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR2_PATT_TAB3")
+            .field("sar2_patt_tab3", &self.sar2_patt_tab3())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:23 - Item 8 ~ 11 for pattern table 2 (each item 6bit)"]
+    #[inline(always)]
+    pub fn sar2_patt_tab3(&mut self) -> SAR2_PATT_TAB3_W<SAR2_PATT_TAB3_SPEC> {
+        SAR2_PATT_TAB3_W::new(self, 0)
+    }
+}
+#[doc = "configure apb saradc pattern table\n\nYou can [`read`](crate::Reg::read) this register and get [`sar2_patt_tab3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar2_patt_tab3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR2_PATT_TAB3_SPEC;
+impl crate::RegisterSpec for SAR2_PATT_TAB3_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar2_patt_tab3::R`](R) reader structure"]
+impl crate::Readable for SAR2_PATT_TAB3_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sar2_patt_tab3::W`](W) writer structure"]
+impl crate::Writable for SAR2_PATT_TAB3_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SAR2_PATT_TAB3 to value 0"]
+impl crate::Resettable for SAR2_PATT_TAB3_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/apb_saradc/sar2_patt_tab4.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `SAR2_PATT_TAB4` reader"]
+pub type R = crate::R<SAR2_PATT_TAB4_SPEC>;
+#[doc = "Register `SAR2_PATT_TAB4` writer"]
+pub type W = crate::W<SAR2_PATT_TAB4_SPEC>;
+#[doc = "Field `SAR2_PATT_TAB4` reader - Item 12 ~ 15 for pattern table 2 (each item 6bit)"]
+pub type SAR2_PATT_TAB4_R = crate::FieldReader<u32>;
+#[doc = "Field `SAR2_PATT_TAB4` writer - Item 12 ~ 15 for pattern table 2 (each item 6bit)"]
+pub type SAR2_PATT_TAB4_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
+impl R {
+    #[doc = "Bits 0:23 - Item 12 ~ 15 for pattern table 2 (each item 6bit)"]
+    #[inline(always)]
+    pub fn sar2_patt_tab4(&self) -> SAR2_PATT_TAB4_R {
+        SAR2_PATT_TAB4_R::new(self.bits & 0x00ff_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR2_PATT_TAB4")
+            .field("sar2_patt_tab4", &self.sar2_patt_tab4())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:23 - Item 12 ~ 15 for pattern table 2 (each item 6bit)"]
+    #[inline(always)]
+    pub fn sar2_patt_tab4(&mut self) -> SAR2_PATT_TAB4_W<SAR2_PATT_TAB4_SPEC> {
+        SAR2_PATT_TAB4_W::new(self, 0)
+    }
+}
+#[doc = "configure apb saradc pattern table\n\nYou can [`read`](crate::Reg::read) this register and get [`sar2_patt_tab4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar2_patt_tab4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR2_PATT_TAB4_SPEC;
+impl crate::RegisterSpec for SAR2_PATT_TAB4_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar2_patt_tab4::R`](R) reader structure"]
+impl crate::Readable for SAR2_PATT_TAB4_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sar2_patt_tab4::W`](W) writer structure"]
+impl crate::Writable for SAR2_PATT_TAB4_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SAR2_PATT_TAB4 to value 0"]
+impl crate::Resettable for SAR2_PATT_TAB4_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/apb_saradc/sar2_status.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `SAR2_STATUS` reader"]
+pub type R = crate::R<SAR2_STATUS_SPEC>;
+#[doc = "Field `SAR2_STATUS` reader - saradc2 status"]
+pub type SAR2_STATUS_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - saradc2 status"]
+    #[inline(always)]
+    pub fn sar2_status(&self) -> SAR2_STATUS_R {
+        SAR2_STATUS_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR2_STATUS")
+            .field("sar2_status", &self.sar2_status())
+            .finish()
+    }
+}
+#[doc = "saradc2 status for debug\n\nYou can [`read`](crate::Reg::read) this register and get [`sar2_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR2_STATUS_SPEC;
+impl crate::RegisterSpec for SAR2_STATUS_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar2_status::R`](R) reader structure"]
+impl crate::Readable for SAR2_STATUS_SPEC {}
+#[doc = "`reset()` method sets SAR2_STATUS to value 0"]
+impl crate::Resettable for SAR2_STATUS_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/apb_saradc/thres0_ctrl.rs

@@ -0,0 +1,77 @@
+#[doc = "Register `THRES0_CTRL` reader"]
+pub type R = crate::R<THRES0_CTRL_SPEC>;
+#[doc = "Register `THRES0_CTRL` writer"]
+pub type W = crate::W<THRES0_CTRL_SPEC>;
+#[doc = "Field `THRES0_CHANNEL` reader - configure which channel thres0 monitor"]
+pub type THRES0_CHANNEL_R = crate::FieldReader;
+#[doc = "Field `THRES0_CHANNEL` writer - configure which channel thres0 monitor"]
+pub type THRES0_CHANNEL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
+#[doc = "Field `THRES0_HIGH` reader - thres0 monitor high thres"]
+pub type THRES0_HIGH_R = crate::FieldReader<u16>;
+#[doc = "Field `THRES0_HIGH` writer - thres0 monitor high thres"]
+pub type THRES0_HIGH_W<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>;
+#[doc = "Field `THRES0_LOW` reader - thres0 monitor low thres"]
+pub type THRES0_LOW_R = crate::FieldReader<u16>;
+#[doc = "Field `THRES0_LOW` writer - thres0 monitor low thres"]
+pub type THRES0_LOW_W<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>;
+impl R {
+    #[doc = "Bits 0:4 - configure which channel thres0 monitor"]
+    #[inline(always)]
+    pub fn thres0_channel(&self) -> THRES0_CHANNEL_R {
+        THRES0_CHANNEL_R::new((self.bits & 0x1f) as u8)
+    }
+    #[doc = "Bits 5:17 - thres0 monitor high thres"]
+    #[inline(always)]
+    pub fn thres0_high(&self) -> THRES0_HIGH_R {
+        THRES0_HIGH_R::new(((self.bits >> 5) & 0x1fff) as u16)
+    }
+    #[doc = "Bits 18:30 - thres0 monitor low thres"]
+    #[inline(always)]
+    pub fn thres0_low(&self) -> THRES0_LOW_R {
+        THRES0_LOW_R::new(((self.bits >> 18) & 0x1fff) as u16)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("THRES0_CTRL")
+            .field("thres0_channel", &self.thres0_channel())
+            .field("thres0_high", &self.thres0_high())
+            .field("thres0_low", &self.thres0_low())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:4 - configure which channel thres0 monitor"]
+    #[inline(always)]
+    pub fn thres0_channel(&mut self) -> THRES0_CHANNEL_W<THRES0_CTRL_SPEC> {
+        THRES0_CHANNEL_W::new(self, 0)
+    }
+    #[doc = "Bits 5:17 - thres0 monitor high thres"]
+    #[inline(always)]
+    pub fn thres0_high(&mut self) -> THRES0_HIGH_W<THRES0_CTRL_SPEC> {
+        THRES0_HIGH_W::new(self, 5)
+    }
+    #[doc = "Bits 18:30 - thres0 monitor low thres"]
+    #[inline(always)]
+    pub fn thres0_low(&mut self) -> THRES0_LOW_W<THRES0_CTRL_SPEC> {
+        THRES0_LOW_W::new(self, 18)
+    }
+}
+#[doc = "configure apb saradc thres monitor\n\nYou can [`read`](crate::Reg::read) this register and get [`thres0_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`thres0_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct THRES0_CTRL_SPEC;
+impl crate::RegisterSpec for THRES0_CTRL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`thres0_ctrl::R`](R) reader structure"]
+impl crate::Readable for THRES0_CTRL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`thres0_ctrl::W`](W) writer structure"]
+impl crate::Writable for THRES0_CTRL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets THRES0_CTRL to value 0x0003_ffed"]
+impl crate::Resettable for THRES0_CTRL_SPEC {
+    const RESET_VALUE: u32 = 0x0003_ffed;
+}

vendor/esp32s3/src/apb_saradc/thres1_ctrl.rs

@@ -0,0 +1,77 @@
+#[doc = "Register `THRES1_CTRL` reader"]
+pub type R = crate::R<THRES1_CTRL_SPEC>;
+#[doc = "Register `THRES1_CTRL` writer"]
+pub type W = crate::W<THRES1_CTRL_SPEC>;
+#[doc = "Field `THRES1_CHANNEL` reader - configure which channel thres0 monitor"]
+pub type THRES1_CHANNEL_R = crate::FieldReader;
+#[doc = "Field `THRES1_CHANNEL` writer - configure which channel thres0 monitor"]
+pub type THRES1_CHANNEL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
+#[doc = "Field `THRES1_HIGH` reader - thres1 monitor high thres"]
+pub type THRES1_HIGH_R = crate::FieldReader<u16>;
+#[doc = "Field `THRES1_HIGH` writer - thres1 monitor high thres"]
+pub type THRES1_HIGH_W<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>;
+#[doc = "Field `THRES1_LOW` reader - thres1 monitor low thres"]
+pub type THRES1_LOW_R = crate::FieldReader<u16>;
+#[doc = "Field `THRES1_LOW` writer - thres1 monitor low thres"]
+pub type THRES1_LOW_W<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>;
+impl R {
+    #[doc = "Bits 0:4 - configure which channel thres0 monitor"]
+    #[inline(always)]
+    pub fn thres1_channel(&self) -> THRES1_CHANNEL_R {
+        THRES1_CHANNEL_R::new((self.bits & 0x1f) as u8)
+    }
+    #[doc = "Bits 5:17 - thres1 monitor high thres"]
+    #[inline(always)]
+    pub fn thres1_high(&self) -> THRES1_HIGH_R {
+        THRES1_HIGH_R::new(((self.bits >> 5) & 0x1fff) as u16)
+    }
+    #[doc = "Bits 18:30 - thres1 monitor low thres"]
+    #[inline(always)]
+    pub fn thres1_low(&self) -> THRES1_LOW_R {
+        THRES1_LOW_R::new(((self.bits >> 18) & 0x1fff) as u16)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("THRES1_CTRL")
+            .field("thres1_channel", &self.thres1_channel())
+            .field("thres1_high", &self.thres1_high())
+            .field("thres1_low", &self.thres1_low())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:4 - configure which channel thres0 monitor"]
+    #[inline(always)]
+    pub fn thres1_channel(&mut self) -> THRES1_CHANNEL_W<THRES1_CTRL_SPEC> {
+        THRES1_CHANNEL_W::new(self, 0)
+    }
+    #[doc = "Bits 5:17 - thres1 monitor high thres"]
+    #[inline(always)]
+    pub fn thres1_high(&mut self) -> THRES1_HIGH_W<THRES1_CTRL_SPEC> {
+        THRES1_HIGH_W::new(self, 5)
+    }
+    #[doc = "Bits 18:30 - thres1 monitor low thres"]
+    #[inline(always)]
+    pub fn thres1_low(&mut self) -> THRES1_LOW_W<THRES1_CTRL_SPEC> {
+        THRES1_LOW_W::new(self, 18)
+    }
+}
+#[doc = "configure apb saradc thres monitor\n\nYou can [`read`](crate::Reg::read) this register and get [`thres1_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`thres1_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct THRES1_CTRL_SPEC;
+impl crate::RegisterSpec for THRES1_CTRL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`thres1_ctrl::R`](R) reader structure"]
+impl crate::Readable for THRES1_CTRL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`thres1_ctrl::W`](W) writer structure"]
+impl crate::Writable for THRES1_CTRL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets THRES1_CTRL to value 0x0003_ffed"]
+impl crate::Resettable for THRES1_CTRL_SPEC {
+    const RESET_VALUE: u32 = 0x0003_ffed;
+}

vendor/esp32s3/src/apb_saradc/thres_ctrl.rs

@@ -0,0 +1,107 @@
+#[doc = "Register `THRES_CTRL` reader"]
+pub type R = crate::R<THRES_CTRL_SPEC>;
+#[doc = "Register `THRES_CTRL` writer"]
+pub type W = crate::W<THRES_CTRL_SPEC>;
+#[doc = "Field `THRES_ALL_EN` reader - enable thres0 to monitor all channel"]
+pub type THRES_ALL_EN_R = crate::BitReader;
+#[doc = "Field `THRES_ALL_EN` writer - enable thres0 to monitor all channel"]
+pub type THRES_ALL_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `THRES3_EN` reader - no public"]
+pub type THRES3_EN_R = crate::BitReader;
+#[doc = "Field `THRES3_EN` writer - no public"]
+pub type THRES3_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `THRES2_EN` reader - no public"]
+pub type THRES2_EN_R = crate::BitReader;
+#[doc = "Field `THRES2_EN` writer - no public"]
+pub type THRES2_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `THRES1_EN` reader - enable thres1"]
+pub type THRES1_EN_R = crate::BitReader;
+#[doc = "Field `THRES1_EN` writer - enable thres1"]
+pub type THRES1_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `THRES0_EN` reader - enable thres0"]
+pub type THRES0_EN_R = crate::BitReader;
+#[doc = "Field `THRES0_EN` writer - enable thres0"]
+pub type THRES0_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 27 - enable thres0 to monitor all channel"]
+    #[inline(always)]
+    pub fn thres_all_en(&self) -> THRES_ALL_EN_R {
+        THRES_ALL_EN_R::new(((self.bits >> 27) & 1) != 0)
+    }
+    #[doc = "Bit 28 - no public"]
+    #[inline(always)]
+    pub fn thres3_en(&self) -> THRES3_EN_R {
+        THRES3_EN_R::new(((self.bits >> 28) & 1) != 0)
+    }
+    #[doc = "Bit 29 - no public"]
+    #[inline(always)]
+    pub fn thres2_en(&self) -> THRES2_EN_R {
+        THRES2_EN_R::new(((self.bits >> 29) & 1) != 0)
+    }
+    #[doc = "Bit 30 - enable thres1"]
+    #[inline(always)]
+    pub fn thres1_en(&self) -> THRES1_EN_R {
+        THRES1_EN_R::new(((self.bits >> 30) & 1) != 0)
+    }
+    #[doc = "Bit 31 - enable thres0"]
+    #[inline(always)]
+    pub fn thres0_en(&self) -> THRES0_EN_R {
+        THRES0_EN_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("THRES_CTRL")
+            .field("thres_all_en", &self.thres_all_en())
+            .field("thres3_en", &self.thres3_en())
+            .field("thres2_en", &self.thres2_en())
+            .field("thres1_en", &self.thres1_en())
+            .field("thres0_en", &self.thres0_en())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 27 - enable thres0 to monitor all channel"]
+    #[inline(always)]
+    pub fn thres_all_en(&mut self) -> THRES_ALL_EN_W<THRES_CTRL_SPEC> {
+        THRES_ALL_EN_W::new(self, 27)
+    }
+    #[doc = "Bit 28 - no public"]
+    #[inline(always)]
+    pub fn thres3_en(&mut self) -> THRES3_EN_W<THRES_CTRL_SPEC> {
+        THRES3_EN_W::new(self, 28)
+    }
+    #[doc = "Bit 29 - no public"]
+    #[inline(always)]
+    pub fn thres2_en(&mut self) -> THRES2_EN_W<THRES_CTRL_SPEC> {
+        THRES2_EN_W::new(self, 29)
+    }
+    #[doc = "Bit 30 - enable thres1"]
+    #[inline(always)]
+    pub fn thres1_en(&mut self) -> THRES1_EN_W<THRES_CTRL_SPEC> {
+        THRES1_EN_W::new(self, 30)
+    }
+    #[doc = "Bit 31 - enable thres0"]
+    #[inline(always)]
+    pub fn thres0_en(&mut self) -> THRES0_EN_W<THRES_CTRL_SPEC> {
+        THRES0_EN_W::new(self, 31)
+    }
+}
+#[doc = "configure thres monitor enable\n\nYou can [`read`](crate::Reg::read) this register and get [`thres_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`thres_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct THRES_CTRL_SPEC;
+impl crate::RegisterSpec for THRES_CTRL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`thres_ctrl::R`](R) reader structure"]
+impl crate::Readable for THRES_CTRL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`thres_ctrl::W`](W) writer structure"]
+impl crate::Writable for THRES_CTRL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets THRES_CTRL to value 0"]
+impl crate::Resettable for THRES_CTRL_SPEC {
+    const RESET_VALUE: u32 = 0;
+}