feat: add display UI with splash screen, dashboard, and RSSI sparkline

Implement full SSD1306 OLED display support:
- Splash screen on boot (1.5s) with project name, version, board
- Dashboard showing radio state, config, counters, RSSI/SNR
- RSSI history sparkline (64-sample ring buffer, 2px-wide bars)
- DisplayOn/DisplayOff host commands routed via dedicated channel
- Pure render functions against generic DrawTarget (no hardware coupling)
- Display on/off control bypasses radio task entirely

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>

vendor/esp32s3/src/assist_debug/core_0_area_dram0_0_max.rs

@@ -0,0 +1,49 @@
+#[doc = "Register `CORE_0_AREA_DRAM0_0_MAX` reader"]
+pub type R = crate::R<CORE_0_AREA_DRAM0_0_MAX_SPEC>;
+#[doc = "Register `CORE_0_AREA_DRAM0_0_MAX` writer"]
+pub type W = crate::W<CORE_0_AREA_DRAM0_0_MAX_SPEC>;
+#[doc = "Field `CORE_0_AREA_DRAM0_0_MAX` reader - Core0 dram0 region0 end addr"]
+pub type CORE_0_AREA_DRAM0_0_MAX_R = crate::FieldReader<u32>;
+#[doc = "Field `CORE_0_AREA_DRAM0_0_MAX` writer - Core0 dram0 region0 end addr"]
+pub type CORE_0_AREA_DRAM0_0_MAX_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - Core0 dram0 region0 end addr"]
+    #[inline(always)]
+    pub fn core_0_area_dram0_0_max(&self) -> CORE_0_AREA_DRAM0_0_MAX_R {
+        CORE_0_AREA_DRAM0_0_MAX_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_0_AREA_DRAM0_0_MAX")
+            .field("core_0_area_dram0_0_max", &self.core_0_area_dram0_0_max())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Core0 dram0 region0 end addr"]
+    #[inline(always)]
+    pub fn core_0_area_dram0_0_max(
+        &mut self,
+    ) -> CORE_0_AREA_DRAM0_0_MAX_W<CORE_0_AREA_DRAM0_0_MAX_SPEC> {
+        CORE_0_AREA_DRAM0_0_MAX_W::new(self, 0)
+    }
+}
+#[doc = "core0 dram0 region0 addr configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_area_dram0_0_max::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_area_dram0_0_max::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_0_AREA_DRAM0_0_MAX_SPEC;
+impl crate::RegisterSpec for CORE_0_AREA_DRAM0_0_MAX_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_0_area_dram0_0_max::R`](R) reader structure"]
+impl crate::Readable for CORE_0_AREA_DRAM0_0_MAX_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`core_0_area_dram0_0_max::W`](W) writer structure"]
+impl crate::Writable for CORE_0_AREA_DRAM0_0_MAX_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CORE_0_AREA_DRAM0_0_MAX to value 0"]
+impl crate::Resettable for CORE_0_AREA_DRAM0_0_MAX_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/core_0_area_dram0_0_min.rs

@@ -0,0 +1,49 @@
+#[doc = "Register `CORE_0_AREA_DRAM0_0_MIN` reader"]
+pub type R = crate::R<CORE_0_AREA_DRAM0_0_MIN_SPEC>;
+#[doc = "Register `CORE_0_AREA_DRAM0_0_MIN` writer"]
+pub type W = crate::W<CORE_0_AREA_DRAM0_0_MIN_SPEC>;
+#[doc = "Field `CORE_0_AREA_DRAM0_0_MIN` reader - Core0 dram0 region0 start addr"]
+pub type CORE_0_AREA_DRAM0_0_MIN_R = crate::FieldReader<u32>;
+#[doc = "Field `CORE_0_AREA_DRAM0_0_MIN` writer - Core0 dram0 region0 start addr"]
+pub type CORE_0_AREA_DRAM0_0_MIN_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - Core0 dram0 region0 start addr"]
+    #[inline(always)]
+    pub fn core_0_area_dram0_0_min(&self) -> CORE_0_AREA_DRAM0_0_MIN_R {
+        CORE_0_AREA_DRAM0_0_MIN_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_0_AREA_DRAM0_0_MIN")
+            .field("core_0_area_dram0_0_min", &self.core_0_area_dram0_0_min())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Core0 dram0 region0 start addr"]
+    #[inline(always)]
+    pub fn core_0_area_dram0_0_min(
+        &mut self,
+    ) -> CORE_0_AREA_DRAM0_0_MIN_W<CORE_0_AREA_DRAM0_0_MIN_SPEC> {
+        CORE_0_AREA_DRAM0_0_MIN_W::new(self, 0)
+    }
+}
+#[doc = "core0 dram0 region0 addr configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_area_dram0_0_min::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_area_dram0_0_min::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_0_AREA_DRAM0_0_MIN_SPEC;
+impl crate::RegisterSpec for CORE_0_AREA_DRAM0_0_MIN_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_0_area_dram0_0_min::R`](R) reader structure"]
+impl crate::Readable for CORE_0_AREA_DRAM0_0_MIN_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`core_0_area_dram0_0_min::W`](W) writer structure"]
+impl crate::Writable for CORE_0_AREA_DRAM0_0_MIN_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CORE_0_AREA_DRAM0_0_MIN to value 0xffff_ffff"]
+impl crate::Resettable for CORE_0_AREA_DRAM0_0_MIN_SPEC {
+    const RESET_VALUE: u32 = 0xffff_ffff;
+}

vendor/esp32s3/src/assist_debug/core_0_area_dram0_1_max.rs

@@ -0,0 +1,49 @@
+#[doc = "Register `CORE_0_AREA_DRAM0_1_MAX` reader"]
+pub type R = crate::R<CORE_0_AREA_DRAM0_1_MAX_SPEC>;
+#[doc = "Register `CORE_0_AREA_DRAM0_1_MAX` writer"]
+pub type W = crate::W<CORE_0_AREA_DRAM0_1_MAX_SPEC>;
+#[doc = "Field `CORE_0_AREA_DRAM0_1_MAX` reader - Core0 dram0 region1 end addr"]
+pub type CORE_0_AREA_DRAM0_1_MAX_R = crate::FieldReader<u32>;
+#[doc = "Field `CORE_0_AREA_DRAM0_1_MAX` writer - Core0 dram0 region1 end addr"]
+pub type CORE_0_AREA_DRAM0_1_MAX_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - Core0 dram0 region1 end addr"]
+    #[inline(always)]
+    pub fn core_0_area_dram0_1_max(&self) -> CORE_0_AREA_DRAM0_1_MAX_R {
+        CORE_0_AREA_DRAM0_1_MAX_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_0_AREA_DRAM0_1_MAX")
+            .field("core_0_area_dram0_1_max", &self.core_0_area_dram0_1_max())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Core0 dram0 region1 end addr"]
+    #[inline(always)]
+    pub fn core_0_area_dram0_1_max(
+        &mut self,
+    ) -> CORE_0_AREA_DRAM0_1_MAX_W<CORE_0_AREA_DRAM0_1_MAX_SPEC> {
+        CORE_0_AREA_DRAM0_1_MAX_W::new(self, 0)
+    }
+}
+#[doc = "core0 dram0 region1 addr configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_area_dram0_1_max::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_area_dram0_1_max::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_0_AREA_DRAM0_1_MAX_SPEC;
+impl crate::RegisterSpec for CORE_0_AREA_DRAM0_1_MAX_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_0_area_dram0_1_max::R`](R) reader structure"]
+impl crate::Readable for CORE_0_AREA_DRAM0_1_MAX_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`core_0_area_dram0_1_max::W`](W) writer structure"]
+impl crate::Writable for CORE_0_AREA_DRAM0_1_MAX_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CORE_0_AREA_DRAM0_1_MAX to value 0"]
+impl crate::Resettable for CORE_0_AREA_DRAM0_1_MAX_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/core_0_area_dram0_1_min.rs

@@ -0,0 +1,49 @@
+#[doc = "Register `CORE_0_AREA_DRAM0_1_MIN` reader"]
+pub type R = crate::R<CORE_0_AREA_DRAM0_1_MIN_SPEC>;
+#[doc = "Register `CORE_0_AREA_DRAM0_1_MIN` writer"]
+pub type W = crate::W<CORE_0_AREA_DRAM0_1_MIN_SPEC>;
+#[doc = "Field `CORE_0_AREA_DRAM0_1_MIN` reader - Core0 dram0 region1 start addr"]
+pub type CORE_0_AREA_DRAM0_1_MIN_R = crate::FieldReader<u32>;
+#[doc = "Field `CORE_0_AREA_DRAM0_1_MIN` writer - Core0 dram0 region1 start addr"]
+pub type CORE_0_AREA_DRAM0_1_MIN_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - Core0 dram0 region1 start addr"]
+    #[inline(always)]
+    pub fn core_0_area_dram0_1_min(&self) -> CORE_0_AREA_DRAM0_1_MIN_R {
+        CORE_0_AREA_DRAM0_1_MIN_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_0_AREA_DRAM0_1_MIN")
+            .field("core_0_area_dram0_1_min", &self.core_0_area_dram0_1_min())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Core0 dram0 region1 start addr"]
+    #[inline(always)]
+    pub fn core_0_area_dram0_1_min(
+        &mut self,
+    ) -> CORE_0_AREA_DRAM0_1_MIN_W<CORE_0_AREA_DRAM0_1_MIN_SPEC> {
+        CORE_0_AREA_DRAM0_1_MIN_W::new(self, 0)
+    }
+}
+#[doc = "core0 dram0 region1 addr configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_area_dram0_1_min::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_area_dram0_1_min::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_0_AREA_DRAM0_1_MIN_SPEC;
+impl crate::RegisterSpec for CORE_0_AREA_DRAM0_1_MIN_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_0_area_dram0_1_min::R`](R) reader structure"]
+impl crate::Readable for CORE_0_AREA_DRAM0_1_MIN_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`core_0_area_dram0_1_min::W`](W) writer structure"]
+impl crate::Writable for CORE_0_AREA_DRAM0_1_MIN_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CORE_0_AREA_DRAM0_1_MIN to value 0xffff_ffff"]
+impl crate::Resettable for CORE_0_AREA_DRAM0_1_MIN_SPEC {
+    const RESET_VALUE: u32 = 0xffff_ffff;
+}

vendor/esp32s3/src/assist_debug/core_0_area_pc.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `CORE_0_AREA_PC` reader"]
+pub type R = crate::R<CORE_0_AREA_PC_SPEC>;
+#[doc = "Field `CORE_0_AREA_PC` reader - the PC when first touch region monitor interrupt"]
+pub type CORE_0_AREA_PC_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - the PC when first touch region monitor interrupt"]
+    #[inline(always)]
+    pub fn core_0_area_pc(&self) -> CORE_0_AREA_PC_R {
+        CORE_0_AREA_PC_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_0_AREA_PC")
+            .field("core_0_area_pc", &self.core_0_area_pc())
+            .finish()
+    }
+}
+#[doc = "core0 area pc status register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_area_pc::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_0_AREA_PC_SPEC;
+impl crate::RegisterSpec for CORE_0_AREA_PC_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_0_area_pc::R`](R) reader structure"]
+impl crate::Readable for CORE_0_AREA_PC_SPEC {}
+#[doc = "`reset()` method sets CORE_0_AREA_PC to value 0"]
+impl crate::Resettable for CORE_0_AREA_PC_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/core_0_area_pif_0_max.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `CORE_0_AREA_PIF_0_MAX` reader"]
+pub type R = crate::R<CORE_0_AREA_PIF_0_MAX_SPEC>;
+#[doc = "Register `CORE_0_AREA_PIF_0_MAX` writer"]
+pub type W = crate::W<CORE_0_AREA_PIF_0_MAX_SPEC>;
+#[doc = "Field `CORE_0_AREA_PIF_0_MAX` reader - Core0 PIF region0 end addr"]
+pub type CORE_0_AREA_PIF_0_MAX_R = crate::FieldReader<u32>;
+#[doc = "Field `CORE_0_AREA_PIF_0_MAX` writer - Core0 PIF region0 end addr"]
+pub type CORE_0_AREA_PIF_0_MAX_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - Core0 PIF region0 end addr"]
+    #[inline(always)]
+    pub fn core_0_area_pif_0_max(&self) -> CORE_0_AREA_PIF_0_MAX_R {
+        CORE_0_AREA_PIF_0_MAX_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_0_AREA_PIF_0_MAX")
+            .field("core_0_area_pif_0_max", &self.core_0_area_pif_0_max())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Core0 PIF region0 end addr"]
+    #[inline(always)]
+    pub fn core_0_area_pif_0_max(&mut self) -> CORE_0_AREA_PIF_0_MAX_W<CORE_0_AREA_PIF_0_MAX_SPEC> {
+        CORE_0_AREA_PIF_0_MAX_W::new(self, 0)
+    }
+}
+#[doc = "core0 PIF region0 addr configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_area_pif_0_max::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_area_pif_0_max::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_0_AREA_PIF_0_MAX_SPEC;
+impl crate::RegisterSpec for CORE_0_AREA_PIF_0_MAX_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_0_area_pif_0_max::R`](R) reader structure"]
+impl crate::Readable for CORE_0_AREA_PIF_0_MAX_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`core_0_area_pif_0_max::W`](W) writer structure"]
+impl crate::Writable for CORE_0_AREA_PIF_0_MAX_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CORE_0_AREA_PIF_0_MAX to value 0"]
+impl crate::Resettable for CORE_0_AREA_PIF_0_MAX_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/core_0_area_pif_0_min.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `CORE_0_AREA_PIF_0_MIN` reader"]
+pub type R = crate::R<CORE_0_AREA_PIF_0_MIN_SPEC>;
+#[doc = "Register `CORE_0_AREA_PIF_0_MIN` writer"]
+pub type W = crate::W<CORE_0_AREA_PIF_0_MIN_SPEC>;
+#[doc = "Field `CORE_0_AREA_PIF_0_MIN` reader - Core0 PIF region0 start addr"]
+pub type CORE_0_AREA_PIF_0_MIN_R = crate::FieldReader<u32>;
+#[doc = "Field `CORE_0_AREA_PIF_0_MIN` writer - Core0 PIF region0 start addr"]
+pub type CORE_0_AREA_PIF_0_MIN_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - Core0 PIF region0 start addr"]
+    #[inline(always)]
+    pub fn core_0_area_pif_0_min(&self) -> CORE_0_AREA_PIF_0_MIN_R {
+        CORE_0_AREA_PIF_0_MIN_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_0_AREA_PIF_0_MIN")
+            .field("core_0_area_pif_0_min", &self.core_0_area_pif_0_min())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Core0 PIF region0 start addr"]
+    #[inline(always)]
+    pub fn core_0_area_pif_0_min(&mut self) -> CORE_0_AREA_PIF_0_MIN_W<CORE_0_AREA_PIF_0_MIN_SPEC> {
+        CORE_0_AREA_PIF_0_MIN_W::new(self, 0)
+    }
+}
+#[doc = "core0 PIF region0 addr configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_area_pif_0_min::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_area_pif_0_min::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_0_AREA_PIF_0_MIN_SPEC;
+impl crate::RegisterSpec for CORE_0_AREA_PIF_0_MIN_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_0_area_pif_0_min::R`](R) reader structure"]
+impl crate::Readable for CORE_0_AREA_PIF_0_MIN_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`core_0_area_pif_0_min::W`](W) writer structure"]
+impl crate::Writable for CORE_0_AREA_PIF_0_MIN_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CORE_0_AREA_PIF_0_MIN to value 0xffff_ffff"]
+impl crate::Resettable for CORE_0_AREA_PIF_0_MIN_SPEC {
+    const RESET_VALUE: u32 = 0xffff_ffff;
+}

vendor/esp32s3/src/assist_debug/core_0_area_pif_1_max.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `CORE_0_AREA_PIF_1_MAX` reader"]
+pub type R = crate::R<CORE_0_AREA_PIF_1_MAX_SPEC>;
+#[doc = "Register `CORE_0_AREA_PIF_1_MAX` writer"]
+pub type W = crate::W<CORE_0_AREA_PIF_1_MAX_SPEC>;
+#[doc = "Field `CORE_0_AREA_PIF_1_MAX` reader - Core0 PIF region1 end addr"]
+pub type CORE_0_AREA_PIF_1_MAX_R = crate::FieldReader<u32>;
+#[doc = "Field `CORE_0_AREA_PIF_1_MAX` writer - Core0 PIF region1 end addr"]
+pub type CORE_0_AREA_PIF_1_MAX_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - Core0 PIF region1 end addr"]
+    #[inline(always)]
+    pub fn core_0_area_pif_1_max(&self) -> CORE_0_AREA_PIF_1_MAX_R {
+        CORE_0_AREA_PIF_1_MAX_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_0_AREA_PIF_1_MAX")
+            .field("core_0_area_pif_1_max", &self.core_0_area_pif_1_max())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Core0 PIF region1 end addr"]
+    #[inline(always)]
+    pub fn core_0_area_pif_1_max(&mut self) -> CORE_0_AREA_PIF_1_MAX_W<CORE_0_AREA_PIF_1_MAX_SPEC> {
+        CORE_0_AREA_PIF_1_MAX_W::new(self, 0)
+    }
+}
+#[doc = "core0 PIF region1 addr configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_area_pif_1_max::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_area_pif_1_max::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_0_AREA_PIF_1_MAX_SPEC;
+impl crate::RegisterSpec for CORE_0_AREA_PIF_1_MAX_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_0_area_pif_1_max::R`](R) reader structure"]
+impl crate::Readable for CORE_0_AREA_PIF_1_MAX_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`core_0_area_pif_1_max::W`](W) writer structure"]
+impl crate::Writable for CORE_0_AREA_PIF_1_MAX_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CORE_0_AREA_PIF_1_MAX to value 0"]
+impl crate::Resettable for CORE_0_AREA_PIF_1_MAX_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/core_0_area_pif_1_min.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `CORE_0_AREA_PIF_1_MIN` reader"]
+pub type R = crate::R<CORE_0_AREA_PIF_1_MIN_SPEC>;
+#[doc = "Register `CORE_0_AREA_PIF_1_MIN` writer"]
+pub type W = crate::W<CORE_0_AREA_PIF_1_MIN_SPEC>;
+#[doc = "Field `CORE_0_AREA_PIF_1_MIN` reader - Core0 PIF region1 start addr"]
+pub type CORE_0_AREA_PIF_1_MIN_R = crate::FieldReader<u32>;
+#[doc = "Field `CORE_0_AREA_PIF_1_MIN` writer - Core0 PIF region1 start addr"]
+pub type CORE_0_AREA_PIF_1_MIN_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - Core0 PIF region1 start addr"]
+    #[inline(always)]
+    pub fn core_0_area_pif_1_min(&self) -> CORE_0_AREA_PIF_1_MIN_R {
+        CORE_0_AREA_PIF_1_MIN_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_0_AREA_PIF_1_MIN")
+            .field("core_0_area_pif_1_min", &self.core_0_area_pif_1_min())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Core0 PIF region1 start addr"]
+    #[inline(always)]
+    pub fn core_0_area_pif_1_min(&mut self) -> CORE_0_AREA_PIF_1_MIN_W<CORE_0_AREA_PIF_1_MIN_SPEC> {
+        CORE_0_AREA_PIF_1_MIN_W::new(self, 0)
+    }
+}
+#[doc = "core0 PIF region1 addr configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_area_pif_1_min::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_area_pif_1_min::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_0_AREA_PIF_1_MIN_SPEC;
+impl crate::RegisterSpec for CORE_0_AREA_PIF_1_MIN_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_0_area_pif_1_min::R`](R) reader structure"]
+impl crate::Readable for CORE_0_AREA_PIF_1_MIN_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`core_0_area_pif_1_min::W`](W) writer structure"]
+impl crate::Writable for CORE_0_AREA_PIF_1_MIN_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CORE_0_AREA_PIF_1_MIN to value 0xffff_ffff"]
+impl crate::Resettable for CORE_0_AREA_PIF_1_MIN_SPEC {
+    const RESET_VALUE: u32 = 0xffff_ffff;
+}

vendor/esp32s3/src/assist_debug/core_0_area_sp.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `CORE_0_AREA_SP` reader"]
+pub type R = crate::R<CORE_0_AREA_SP_SPEC>;
+#[doc = "Field `CORE_0_AREA_SP` reader - the stackpointer when first touch region monitor interrupt"]
+pub type CORE_0_AREA_SP_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - the stackpointer when first touch region monitor interrupt"]
+    #[inline(always)]
+    pub fn core_0_area_sp(&self) -> CORE_0_AREA_SP_R {
+        CORE_0_AREA_SP_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_0_AREA_SP")
+            .field("core_0_area_sp", &self.core_0_area_sp())
+            .finish()
+    }
+}
+#[doc = "core0 area sp status register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_area_sp::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_0_AREA_SP_SPEC;
+impl crate::RegisterSpec for CORE_0_AREA_SP_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_0_area_sp::R`](R) reader structure"]
+impl crate::Readable for CORE_0_AREA_SP_SPEC {}
+#[doc = "`reset()` method sets CORE_0_AREA_SP to value 0xffff_ffff"]
+impl crate::Resettable for CORE_0_AREA_SP_SPEC {
+    const RESET_VALUE: u32 = 0xffff_ffff;
+}

vendor/esp32s3/src/assist_debug/core_0_dram0_exception_monitor_0.rs

@@ -0,0 +1,44 @@
+#[doc = "Register `CORE_0_DRAM0_EXCEPTION_MONITOR_0` reader"]
+pub type R = crate::R<CORE_0_DRAM0_EXCEPTION_MONITOR_0_SPEC>;
+#[doc = "Field `CORE_0_DRAM0_RECORDING_ADDR_0` reader - The first dram0's addr\\[25:4\\] status when trigger DRAM busy interrupt"]
+pub type CORE_0_DRAM0_RECORDING_ADDR_0_R = crate::FieldReader<u32>;
+#[doc = "Field `CORE_0_DRAM0_RECORDING_WR_0` reader - The first dram0's wr status when trigger DRAM busy interrupt"]
+pub type CORE_0_DRAM0_RECORDING_WR_0_R = crate::BitReader;
+impl R {
+    #[doc = "Bits 0:21 - The first dram0's addr\\[25:4\\] status when trigger DRAM busy interrupt"]
+    #[inline(always)]
+    pub fn core_0_dram0_recording_addr_0(&self) -> CORE_0_DRAM0_RECORDING_ADDR_0_R {
+        CORE_0_DRAM0_RECORDING_ADDR_0_R::new(self.bits & 0x003f_ffff)
+    }
+    #[doc = "Bit 22 - The first dram0's wr status when trigger DRAM busy interrupt"]
+    #[inline(always)]
+    pub fn core_0_dram0_recording_wr_0(&self) -> CORE_0_DRAM0_RECORDING_WR_0_R {
+        CORE_0_DRAM0_RECORDING_WR_0_R::new(((self.bits >> 22) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_0_DRAM0_EXCEPTION_MONITOR_0")
+            .field(
+                "core_0_dram0_recording_addr_0",
+                &self.core_0_dram0_recording_addr_0(),
+            )
+            .field(
+                "core_0_dram0_recording_wr_0",
+                &self.core_0_dram0_recording_wr_0(),
+            )
+            .finish()
+    }
+}
+#[doc = "core0 bus busy status regsiter\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_dram0_exception_monitor_0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_0_DRAM0_EXCEPTION_MONITOR_0_SPEC;
+impl crate::RegisterSpec for CORE_0_DRAM0_EXCEPTION_MONITOR_0_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_0_dram0_exception_monitor_0::R`](R) reader structure"]
+impl crate::Readable for CORE_0_DRAM0_EXCEPTION_MONITOR_0_SPEC {}
+#[doc = "`reset()` method sets CORE_0_DRAM0_EXCEPTION_MONITOR_0 to value 0"]
+impl crate::Resettable for CORE_0_DRAM0_EXCEPTION_MONITOR_0_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/core_0_dram0_exception_monitor_1.rs

@@ -0,0 +1,33 @@
+#[doc = "Register `CORE_0_DRAM0_EXCEPTION_MONITOR_1` reader"]
+pub type R = crate::R<CORE_0_DRAM0_EXCEPTION_MONITOR_1_SPEC>;
+#[doc = "Field `CORE_0_DRAM0_RECORDING_BYTEEN_0` reader - The first dram0's byteen status when trigger DRAM busy interrupt"]
+pub type CORE_0_DRAM0_RECORDING_BYTEEN_0_R = crate::FieldReader<u16>;
+impl R {
+    #[doc = "Bits 0:15 - The first dram0's byteen status when trigger DRAM busy interrupt"]
+    #[inline(always)]
+    pub fn core_0_dram0_recording_byteen_0(&self) -> CORE_0_DRAM0_RECORDING_BYTEEN_0_R {
+        CORE_0_DRAM0_RECORDING_BYTEEN_0_R::new((self.bits & 0xffff) as u16)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_0_DRAM0_EXCEPTION_MONITOR_1")
+            .field(
+                "core_0_dram0_recording_byteen_0",
+                &self.core_0_dram0_recording_byteen_0(),
+            )
+            .finish()
+    }
+}
+#[doc = "core0 bus busy status regsiter\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_dram0_exception_monitor_1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_0_DRAM0_EXCEPTION_MONITOR_1_SPEC;
+impl crate::RegisterSpec for CORE_0_DRAM0_EXCEPTION_MONITOR_1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_0_dram0_exception_monitor_1::R`](R) reader structure"]
+impl crate::Readable for CORE_0_DRAM0_EXCEPTION_MONITOR_1_SPEC {}
+#[doc = "`reset()` method sets CORE_0_DRAM0_EXCEPTION_MONITOR_1 to value 0"]
+impl crate::Resettable for CORE_0_DRAM0_EXCEPTION_MONITOR_1_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/core_0_dram0_exception_monitor_2.rs

@@ -0,0 +1,33 @@
+#[doc = "Register `CORE_0_DRAM0_EXCEPTION_MONITOR_2` reader"]
+pub type R = crate::R<CORE_0_DRAM0_EXCEPTION_MONITOR_2_SPEC>;
+#[doc = "Field `CORE_0_DRAM0_RECORDING_PC_0` reader - The first dram0's PC status when trigger DRAM busy interrupt"]
+pub type CORE_0_DRAM0_RECORDING_PC_0_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - The first dram0's PC status when trigger DRAM busy interrupt"]
+    #[inline(always)]
+    pub fn core_0_dram0_recording_pc_0(&self) -> CORE_0_DRAM0_RECORDING_PC_0_R {
+        CORE_0_DRAM0_RECORDING_PC_0_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_0_DRAM0_EXCEPTION_MONITOR_2")
+            .field(
+                "core_0_dram0_recording_pc_0",
+                &self.core_0_dram0_recording_pc_0(),
+            )
+            .finish()
+    }
+}
+#[doc = "core0 bus busy status regsiter\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_dram0_exception_monitor_2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_0_DRAM0_EXCEPTION_MONITOR_2_SPEC;
+impl crate::RegisterSpec for CORE_0_DRAM0_EXCEPTION_MONITOR_2_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_0_dram0_exception_monitor_2::R`](R) reader structure"]
+impl crate::Readable for CORE_0_DRAM0_EXCEPTION_MONITOR_2_SPEC {}
+#[doc = "`reset()` method sets CORE_0_DRAM0_EXCEPTION_MONITOR_2 to value 0xffff_ffff"]
+impl crate::Resettable for CORE_0_DRAM0_EXCEPTION_MONITOR_2_SPEC {
+    const RESET_VALUE: u32 = 0xffff_ffff;
+}

vendor/esp32s3/src/assist_debug/core_0_dram0_exception_monitor_3.rs

@@ -0,0 +1,44 @@
+#[doc = "Register `CORE_0_DRAM0_EXCEPTION_MONITOR_3` reader"]
+pub type R = crate::R<CORE_0_DRAM0_EXCEPTION_MONITOR_3_SPEC>;
+#[doc = "Field `CORE_0_DRAM0_RECORDING_ADDR_1` reader - The second dram0's addr\\[25:4\\] status when trigger DRAM busy interrupt"]
+pub type CORE_0_DRAM0_RECORDING_ADDR_1_R = crate::FieldReader<u32>;
+#[doc = "Field `CORE_0_DRAM0_RECORDING_WR_1` reader - The second dram0's wr status when trigger DRAM busy interrupt"]
+pub type CORE_0_DRAM0_RECORDING_WR_1_R = crate::BitReader;
+impl R {
+    #[doc = "Bits 0:21 - The second dram0's addr\\[25:4\\] status when trigger DRAM busy interrupt"]
+    #[inline(always)]
+    pub fn core_0_dram0_recording_addr_1(&self) -> CORE_0_DRAM0_RECORDING_ADDR_1_R {
+        CORE_0_DRAM0_RECORDING_ADDR_1_R::new(self.bits & 0x003f_ffff)
+    }
+    #[doc = "Bit 22 - The second dram0's wr status when trigger DRAM busy interrupt"]
+    #[inline(always)]
+    pub fn core_0_dram0_recording_wr_1(&self) -> CORE_0_DRAM0_RECORDING_WR_1_R {
+        CORE_0_DRAM0_RECORDING_WR_1_R::new(((self.bits >> 22) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_0_DRAM0_EXCEPTION_MONITOR_3")
+            .field(
+                "core_0_dram0_recording_addr_1",
+                &self.core_0_dram0_recording_addr_1(),
+            )
+            .field(
+                "core_0_dram0_recording_wr_1",
+                &self.core_0_dram0_recording_wr_1(),
+            )
+            .finish()
+    }
+}
+#[doc = "core0 bus busy status regsiter\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_dram0_exception_monitor_3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_0_DRAM0_EXCEPTION_MONITOR_3_SPEC;
+impl crate::RegisterSpec for CORE_0_DRAM0_EXCEPTION_MONITOR_3_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_0_dram0_exception_monitor_3::R`](R) reader structure"]
+impl crate::Readable for CORE_0_DRAM0_EXCEPTION_MONITOR_3_SPEC {}
+#[doc = "`reset()` method sets CORE_0_DRAM0_EXCEPTION_MONITOR_3 to value 0"]
+impl crate::Resettable for CORE_0_DRAM0_EXCEPTION_MONITOR_3_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/core_0_dram0_exception_monitor_4.rs

@@ -0,0 +1,33 @@
+#[doc = "Register `CORE_0_DRAM0_EXCEPTION_MONITOR_4` reader"]
+pub type R = crate::R<CORE_0_DRAM0_EXCEPTION_MONITOR_4_SPEC>;
+#[doc = "Field `CORE_0_DRAM0_RECORDING_BYTEEN_1` reader - The second dram0's byteen status when trigger DRAM busy interrupt"]
+pub type CORE_0_DRAM0_RECORDING_BYTEEN_1_R = crate::FieldReader<u16>;
+impl R {
+    #[doc = "Bits 0:15 - The second dram0's byteen status when trigger DRAM busy interrupt"]
+    #[inline(always)]
+    pub fn core_0_dram0_recording_byteen_1(&self) -> CORE_0_DRAM0_RECORDING_BYTEEN_1_R {
+        CORE_0_DRAM0_RECORDING_BYTEEN_1_R::new((self.bits & 0xffff) as u16)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_0_DRAM0_EXCEPTION_MONITOR_4")
+            .field(
+                "core_0_dram0_recording_byteen_1",
+                &self.core_0_dram0_recording_byteen_1(),
+            )
+            .finish()
+    }
+}
+#[doc = "core0 bus busy configuration regsiter\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_dram0_exception_monitor_4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_0_DRAM0_EXCEPTION_MONITOR_4_SPEC;
+impl crate::RegisterSpec for CORE_0_DRAM0_EXCEPTION_MONITOR_4_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_0_dram0_exception_monitor_4::R`](R) reader structure"]
+impl crate::Readable for CORE_0_DRAM0_EXCEPTION_MONITOR_4_SPEC {}
+#[doc = "`reset()` method sets CORE_0_DRAM0_EXCEPTION_MONITOR_4 to value 0"]
+impl crate::Resettable for CORE_0_DRAM0_EXCEPTION_MONITOR_4_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/core_0_dram0_exception_monitor_5.rs

@@ -0,0 +1,33 @@
+#[doc = "Register `CORE_0_DRAM0_EXCEPTION_MONITOR_5` reader"]
+pub type R = crate::R<CORE_0_DRAM0_EXCEPTION_MONITOR_5_SPEC>;
+#[doc = "Field `CORE_0_DRAM0_RECORDING_PC_1` reader - The second dram0's PC status when trigger DRAM busy interrupt"]
+pub type CORE_0_DRAM0_RECORDING_PC_1_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - The second dram0's PC status when trigger DRAM busy interrupt"]
+    #[inline(always)]
+    pub fn core_0_dram0_recording_pc_1(&self) -> CORE_0_DRAM0_RECORDING_PC_1_R {
+        CORE_0_DRAM0_RECORDING_PC_1_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_0_DRAM0_EXCEPTION_MONITOR_5")
+            .field(
+                "core_0_dram0_recording_pc_1",
+                &self.core_0_dram0_recording_pc_1(),
+            )
+            .finish()
+    }
+}
+#[doc = "core0 bus busy configuration regsiter\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_dram0_exception_monitor_5::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_0_DRAM0_EXCEPTION_MONITOR_5_SPEC;
+impl crate::RegisterSpec for CORE_0_DRAM0_EXCEPTION_MONITOR_5_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_0_dram0_exception_monitor_5::R`](R) reader structure"]
+impl crate::Readable for CORE_0_DRAM0_EXCEPTION_MONITOR_5_SPEC {}
+#[doc = "`reset()` method sets CORE_0_DRAM0_EXCEPTION_MONITOR_5 to value 0xffff_ffff"]
+impl crate::Resettable for CORE_0_DRAM0_EXCEPTION_MONITOR_5_SPEC {
+    const RESET_VALUE: u32 = 0xffff_ffff;
+}

vendor/esp32s3/src/assist_debug/core_0_intr_clr.rs

@@ -0,0 +1,242 @@
+#[doc = "Register `CORE_0_INTR_CLR` reader"]
+pub type R = crate::R<CORE_0_INTR_CLR_SPEC>;
+#[doc = "Register `CORE_0_INTR_CLR` writer"]
+pub type W = crate::W<CORE_0_INTR_CLR_SPEC>;
+#[doc = "Field `CORE_0_AREA_DRAM0_0_RD_CLR` reader - Core0 dram0 area0 read monitor interrupt clr"]
+pub type CORE_0_AREA_DRAM0_0_RD_CLR_R = crate::BitReader;
+#[doc = "Field `CORE_0_AREA_DRAM0_0_RD_CLR` writer - Core0 dram0 area0 read monitor interrupt clr"]
+pub type CORE_0_AREA_DRAM0_0_RD_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_0_AREA_DRAM0_0_WR_CLR` reader - Core0 dram0 area0 write monitor interrupt clr"]
+pub type CORE_0_AREA_DRAM0_0_WR_CLR_R = crate::BitReader;
+#[doc = "Field `CORE_0_AREA_DRAM0_0_WR_CLR` writer - Core0 dram0 area0 write monitor interrupt clr"]
+pub type CORE_0_AREA_DRAM0_0_WR_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_0_AREA_DRAM0_1_RD_CLR` reader - Core0 dram0 area1 read monitor interrupt clr"]
+pub type CORE_0_AREA_DRAM0_1_RD_CLR_R = crate::BitReader;
+#[doc = "Field `CORE_0_AREA_DRAM0_1_RD_CLR` writer - Core0 dram0 area1 read monitor interrupt clr"]
+pub type CORE_0_AREA_DRAM0_1_RD_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_0_AREA_DRAM0_1_WR_CLR` reader - Core0 dram0 area1 write monitor interrupt clr"]
+pub type CORE_0_AREA_DRAM0_1_WR_CLR_R = crate::BitReader;
+#[doc = "Field `CORE_0_AREA_DRAM0_1_WR_CLR` writer - Core0 dram0 area1 write monitor interrupt clr"]
+pub type CORE_0_AREA_DRAM0_1_WR_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_0_AREA_PIF_0_RD_CLR` reader - Core0 PIF area0 read monitor interrupt clr"]
+pub type CORE_0_AREA_PIF_0_RD_CLR_R = crate::BitReader;
+#[doc = "Field `CORE_0_AREA_PIF_0_RD_CLR` writer - Core0 PIF area0 read monitor interrupt clr"]
+pub type CORE_0_AREA_PIF_0_RD_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_0_AREA_PIF_0_WR_CLR` reader - Core0 PIF area0 write monitor interrupt clr"]
+pub type CORE_0_AREA_PIF_0_WR_CLR_R = crate::BitReader;
+#[doc = "Field `CORE_0_AREA_PIF_0_WR_CLR` writer - Core0 PIF area0 write monitor interrupt clr"]
+pub type CORE_0_AREA_PIF_0_WR_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_0_AREA_PIF_1_RD_CLR` reader - Core0 PIF area1 read monitor interrupt clr"]
+pub type CORE_0_AREA_PIF_1_RD_CLR_R = crate::BitReader;
+#[doc = "Field `CORE_0_AREA_PIF_1_RD_CLR` writer - Core0 PIF area1 read monitor interrupt clr"]
+pub type CORE_0_AREA_PIF_1_RD_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_0_AREA_PIF_1_WR_CLR` reader - Core0 PIF area1 write monitor interrupt clr"]
+pub type CORE_0_AREA_PIF_1_WR_CLR_R = crate::BitReader;
+#[doc = "Field `CORE_0_AREA_PIF_1_WR_CLR` writer - Core0 PIF area1 write monitor interrupt clr"]
+pub type CORE_0_AREA_PIF_1_WR_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_0_SP_SPILL_MIN_CLR` reader - Core0 stackpoint overflow monitor interrupt clr"]
+pub type CORE_0_SP_SPILL_MIN_CLR_R = crate::BitReader;
+#[doc = "Field `CORE_0_SP_SPILL_MIN_CLR` writer - Core0 stackpoint overflow monitor interrupt clr"]
+pub type CORE_0_SP_SPILL_MIN_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_0_SP_SPILL_MAX_CLR` reader - Core0 stackpoint underflow monitor interrupt clr"]
+pub type CORE_0_SP_SPILL_MAX_CLR_R = crate::BitReader;
+#[doc = "Field `CORE_0_SP_SPILL_MAX_CLR` writer - Core0 stackpoint underflow monitor interrupt clr"]
+pub type CORE_0_SP_SPILL_MAX_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_0_IRAM0_EXCEPTION_MONITOR_CLR` reader - IBUS busy monitor interrupt clr"]
+pub type CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_R = crate::BitReader;
+#[doc = "Field `CORE_0_IRAM0_EXCEPTION_MONITOR_CLR` writer - IBUS busy monitor interrupt clr"]
+pub type CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_0_DRAM0_EXCEPTION_MONITOR_CLR` reader - DBUS busy monitor interrupt clr"]
+pub type CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_R = crate::BitReader;
+#[doc = "Field `CORE_0_DRAM0_EXCEPTION_MONITOR_CLR` writer - DBUS busy monitor interrupt clr"]
+pub type CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Core0 dram0 area0 read monitor interrupt clr"]
+    #[inline(always)]
+    pub fn core_0_area_dram0_0_rd_clr(&self) -> CORE_0_AREA_DRAM0_0_RD_CLR_R {
+        CORE_0_AREA_DRAM0_0_RD_CLR_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Core0 dram0 area0 write monitor interrupt clr"]
+    #[inline(always)]
+    pub fn core_0_area_dram0_0_wr_clr(&self) -> CORE_0_AREA_DRAM0_0_WR_CLR_R {
+        CORE_0_AREA_DRAM0_0_WR_CLR_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Core0 dram0 area1 read monitor interrupt clr"]
+    #[inline(always)]
+    pub fn core_0_area_dram0_1_rd_clr(&self) -> CORE_0_AREA_DRAM0_1_RD_CLR_R {
+        CORE_0_AREA_DRAM0_1_RD_CLR_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Core0 dram0 area1 write monitor interrupt clr"]
+    #[inline(always)]
+    pub fn core_0_area_dram0_1_wr_clr(&self) -> CORE_0_AREA_DRAM0_1_WR_CLR_R {
+        CORE_0_AREA_DRAM0_1_WR_CLR_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Core0 PIF area0 read monitor interrupt clr"]
+    #[inline(always)]
+    pub fn core_0_area_pif_0_rd_clr(&self) -> CORE_0_AREA_PIF_0_RD_CLR_R {
+        CORE_0_AREA_PIF_0_RD_CLR_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - Core0 PIF area0 write monitor interrupt clr"]
+    #[inline(always)]
+    pub fn core_0_area_pif_0_wr_clr(&self) -> CORE_0_AREA_PIF_0_WR_CLR_R {
+        CORE_0_AREA_PIF_0_WR_CLR_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - Core0 PIF area1 read monitor interrupt clr"]
+    #[inline(always)]
+    pub fn core_0_area_pif_1_rd_clr(&self) -> CORE_0_AREA_PIF_1_RD_CLR_R {
+        CORE_0_AREA_PIF_1_RD_CLR_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - Core0 PIF area1 write monitor interrupt clr"]
+    #[inline(always)]
+    pub fn core_0_area_pif_1_wr_clr(&self) -> CORE_0_AREA_PIF_1_WR_CLR_R {
+        CORE_0_AREA_PIF_1_WR_CLR_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - Core0 stackpoint overflow monitor interrupt clr"]
+    #[inline(always)]
+    pub fn core_0_sp_spill_min_clr(&self) -> CORE_0_SP_SPILL_MIN_CLR_R {
+        CORE_0_SP_SPILL_MIN_CLR_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - Core0 stackpoint underflow monitor interrupt clr"]
+    #[inline(always)]
+    pub fn core_0_sp_spill_max_clr(&self) -> CORE_0_SP_SPILL_MAX_CLR_R {
+        CORE_0_SP_SPILL_MAX_CLR_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 10 - IBUS busy monitor interrupt clr"]
+    #[inline(always)]
+    pub fn core_0_iram0_exception_monitor_clr(&self) -> CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_R {
+        CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_R::new(((self.bits >> 10) & 1) != 0)
+    }
+    #[doc = "Bit 11 - DBUS busy monitor interrupt clr"]
+    #[inline(always)]
+    pub fn core_0_dram0_exception_monitor_clr(&self) -> CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_R {
+        CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_R::new(((self.bits >> 11) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_0_INTR_CLR")
+            .field(
+                "core_0_area_dram0_0_rd_clr",
+                &self.core_0_area_dram0_0_rd_clr(),
+            )
+            .field(
+                "core_0_area_dram0_0_wr_clr",
+                &self.core_0_area_dram0_0_wr_clr(),
+            )
+            .field(
+                "core_0_area_dram0_1_rd_clr",
+                &self.core_0_area_dram0_1_rd_clr(),
+            )
+            .field(
+                "core_0_area_dram0_1_wr_clr",
+                &self.core_0_area_dram0_1_wr_clr(),
+            )
+            .field("core_0_area_pif_0_rd_clr", &self.core_0_area_pif_0_rd_clr())
+            .field("core_0_area_pif_0_wr_clr", &self.core_0_area_pif_0_wr_clr())
+            .field("core_0_area_pif_1_rd_clr", &self.core_0_area_pif_1_rd_clr())
+            .field("core_0_area_pif_1_wr_clr", &self.core_0_area_pif_1_wr_clr())
+            .field("core_0_sp_spill_min_clr", &self.core_0_sp_spill_min_clr())
+            .field("core_0_sp_spill_max_clr", &self.core_0_sp_spill_max_clr())
+            .field(
+                "core_0_iram0_exception_monitor_clr",
+                &self.core_0_iram0_exception_monitor_clr(),
+            )
+            .field(
+                "core_0_dram0_exception_monitor_clr",
+                &self.core_0_dram0_exception_monitor_clr(),
+            )
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Core0 dram0 area0 read monitor interrupt clr"]
+    #[inline(always)]
+    pub fn core_0_area_dram0_0_rd_clr(
+        &mut self,
+    ) -> CORE_0_AREA_DRAM0_0_RD_CLR_W<CORE_0_INTR_CLR_SPEC> {
+        CORE_0_AREA_DRAM0_0_RD_CLR_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - Core0 dram0 area0 write monitor interrupt clr"]
+    #[inline(always)]
+    pub fn core_0_area_dram0_0_wr_clr(
+        &mut self,
+    ) -> CORE_0_AREA_DRAM0_0_WR_CLR_W<CORE_0_INTR_CLR_SPEC> {
+        CORE_0_AREA_DRAM0_0_WR_CLR_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - Core0 dram0 area1 read monitor interrupt clr"]
+    #[inline(always)]
+    pub fn core_0_area_dram0_1_rd_clr(
+        &mut self,
+    ) -> CORE_0_AREA_DRAM0_1_RD_CLR_W<CORE_0_INTR_CLR_SPEC> {
+        CORE_0_AREA_DRAM0_1_RD_CLR_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - Core0 dram0 area1 write monitor interrupt clr"]
+    #[inline(always)]
+    pub fn core_0_area_dram0_1_wr_clr(
+        &mut self,
+    ) -> CORE_0_AREA_DRAM0_1_WR_CLR_W<CORE_0_INTR_CLR_SPEC> {
+        CORE_0_AREA_DRAM0_1_WR_CLR_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - Core0 PIF area0 read monitor interrupt clr"]
+    #[inline(always)]
+    pub fn core_0_area_pif_0_rd_clr(&mut self) -> CORE_0_AREA_PIF_0_RD_CLR_W<CORE_0_INTR_CLR_SPEC> {
+        CORE_0_AREA_PIF_0_RD_CLR_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - Core0 PIF area0 write monitor interrupt clr"]
+    #[inline(always)]
+    pub fn core_0_area_pif_0_wr_clr(&mut self) -> CORE_0_AREA_PIF_0_WR_CLR_W<CORE_0_INTR_CLR_SPEC> {
+        CORE_0_AREA_PIF_0_WR_CLR_W::new(self, 5)
+    }
+    #[doc = "Bit 6 - Core0 PIF area1 read monitor interrupt clr"]
+    #[inline(always)]
+    pub fn core_0_area_pif_1_rd_clr(&mut self) -> CORE_0_AREA_PIF_1_RD_CLR_W<CORE_0_INTR_CLR_SPEC> {
+        CORE_0_AREA_PIF_1_RD_CLR_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - Core0 PIF area1 write monitor interrupt clr"]
+    #[inline(always)]
+    pub fn core_0_area_pif_1_wr_clr(&mut self) -> CORE_0_AREA_PIF_1_WR_CLR_W<CORE_0_INTR_CLR_SPEC> {
+        CORE_0_AREA_PIF_1_WR_CLR_W::new(self, 7)
+    }
+    #[doc = "Bit 8 - Core0 stackpoint overflow monitor interrupt clr"]
+    #[inline(always)]
+    pub fn core_0_sp_spill_min_clr(&mut self) -> CORE_0_SP_SPILL_MIN_CLR_W<CORE_0_INTR_CLR_SPEC> {
+        CORE_0_SP_SPILL_MIN_CLR_W::new(self, 8)
+    }
+    #[doc = "Bit 9 - Core0 stackpoint underflow monitor interrupt clr"]
+    #[inline(always)]
+    pub fn core_0_sp_spill_max_clr(&mut self) -> CORE_0_SP_SPILL_MAX_CLR_W<CORE_0_INTR_CLR_SPEC> {
+        CORE_0_SP_SPILL_MAX_CLR_W::new(self, 9)
+    }
+    #[doc = "Bit 10 - IBUS busy monitor interrupt clr"]
+    #[inline(always)]
+    pub fn core_0_iram0_exception_monitor_clr(
+        &mut self,
+    ) -> CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_W<CORE_0_INTR_CLR_SPEC> {
+        CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_W::new(self, 10)
+    }
+    #[doc = "Bit 11 - DBUS busy monitor interrupt clr"]
+    #[inline(always)]
+    pub fn core_0_dram0_exception_monitor_clr(
+        &mut self,
+    ) -> CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_W<CORE_0_INTR_CLR_SPEC> {
+        CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_W::new(self, 11)
+    }
+}
+#[doc = "core0 monitor interrupt clr register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_intr_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_intr_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_0_INTR_CLR_SPEC;
+impl crate::RegisterSpec for CORE_0_INTR_CLR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_0_intr_clr::R`](R) reader structure"]
+impl crate::Readable for CORE_0_INTR_CLR_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`core_0_intr_clr::W`](W) writer structure"]
+impl crate::Writable for CORE_0_INTR_CLR_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CORE_0_INTR_CLR to value 0"]
+impl crate::Resettable for CORE_0_INTR_CLR_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/core_0_intr_ena.rs

@@ -0,0 +1,276 @@
+#[doc = "Register `CORE_0_INTR_ENA` reader"]
+pub type R = crate::R<CORE_0_INTR_ENA_SPEC>;
+#[doc = "Register `CORE_0_INTR_ENA` writer"]
+pub type W = crate::W<CORE_0_INTR_ENA_SPEC>;
+#[doc = "Field `CORE_0_AREA_DRAM0_0_RD_INTR_ENA` reader - Core0 dram0 area0 read monitor interrupt enable"]
+pub type CORE_0_AREA_DRAM0_0_RD_INTR_ENA_R = crate::BitReader;
+#[doc = "Field `CORE_0_AREA_DRAM0_0_RD_INTR_ENA` writer - Core0 dram0 area0 read monitor interrupt enable"]
+pub type CORE_0_AREA_DRAM0_0_RD_INTR_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_0_AREA_DRAM0_0_WR_INTR_ENA` reader - Core0 dram0 area0 write monitor interrupt enable"]
+pub type CORE_0_AREA_DRAM0_0_WR_INTR_ENA_R = crate::BitReader;
+#[doc = "Field `CORE_0_AREA_DRAM0_0_WR_INTR_ENA` writer - Core0 dram0 area0 write monitor interrupt enable"]
+pub type CORE_0_AREA_DRAM0_0_WR_INTR_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_0_AREA_DRAM0_1_RD_INTR_ENA` reader - Core0 dram0 area1 read monitor interrupt enable"]
+pub type CORE_0_AREA_DRAM0_1_RD_INTR_ENA_R = crate::BitReader;
+#[doc = "Field `CORE_0_AREA_DRAM0_1_RD_INTR_ENA` writer - Core0 dram0 area1 read monitor interrupt enable"]
+pub type CORE_0_AREA_DRAM0_1_RD_INTR_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_0_AREA_DRAM0_1_WR_INTR_ENA` reader - Core0 dram0 area1 write monitor interrupt enable"]
+pub type CORE_0_AREA_DRAM0_1_WR_INTR_ENA_R = crate::BitReader;
+#[doc = "Field `CORE_0_AREA_DRAM0_1_WR_INTR_ENA` writer - Core0 dram0 area1 write monitor interrupt enable"]
+pub type CORE_0_AREA_DRAM0_1_WR_INTR_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_0_AREA_PIF_0_RD_INTR_ENA` reader - Core0 PIF area0 read monitor interrupt enable"]
+pub type CORE_0_AREA_PIF_0_RD_INTR_ENA_R = crate::BitReader;
+#[doc = "Field `CORE_0_AREA_PIF_0_RD_INTR_ENA` writer - Core0 PIF area0 read monitor interrupt enable"]
+pub type CORE_0_AREA_PIF_0_RD_INTR_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_0_AREA_PIF_0_WR_INTR_ENA` reader - Core0 PIF area0 write monitor interrupt enable"]
+pub type CORE_0_AREA_PIF_0_WR_INTR_ENA_R = crate::BitReader;
+#[doc = "Field `CORE_0_AREA_PIF_0_WR_INTR_ENA` writer - Core0 PIF area0 write monitor interrupt enable"]
+pub type CORE_0_AREA_PIF_0_WR_INTR_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_0_AREA_PIF_1_RD_INTR_ENA` reader - Core0 PIF area1 read monitor interrupt enable"]
+pub type CORE_0_AREA_PIF_1_RD_INTR_ENA_R = crate::BitReader;
+#[doc = "Field `CORE_0_AREA_PIF_1_RD_INTR_ENA` writer - Core0 PIF area1 read monitor interrupt enable"]
+pub type CORE_0_AREA_PIF_1_RD_INTR_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_0_AREA_PIF_1_WR_INTR_ENA` reader - Core0 PIF area1 write monitor interrupt enable"]
+pub type CORE_0_AREA_PIF_1_WR_INTR_ENA_R = crate::BitReader;
+#[doc = "Field `CORE_0_AREA_PIF_1_WR_INTR_ENA` writer - Core0 PIF area1 write monitor interrupt enable"]
+pub type CORE_0_AREA_PIF_1_WR_INTR_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_0_SP_SPILL_MIN_INTR_ENA` reader - Core0 stackpoint overflow monitor interrupt enable"]
+pub type CORE_0_SP_SPILL_MIN_INTR_ENA_R = crate::BitReader;
+#[doc = "Field `CORE_0_SP_SPILL_MIN_INTR_ENA` writer - Core0 stackpoint overflow monitor interrupt enable"]
+pub type CORE_0_SP_SPILL_MIN_INTR_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_0_SP_SPILL_MAX_INTR_ENA` reader - Core0 stackpoint underflow monitor interrupt enable"]
+pub type CORE_0_SP_SPILL_MAX_INTR_ENA_R = crate::BitReader;
+#[doc = "Field `CORE_0_SP_SPILL_MAX_INTR_ENA` writer - Core0 stackpoint underflow monitor interrupt enable"]
+pub type CORE_0_SP_SPILL_MAX_INTR_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA` reader - IBUS busy monitor interrupt enable"]
+pub type CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_R = crate::BitReader;
+#[doc = "Field `CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA` writer - IBUS busy monitor interrupt enable"]
+pub type CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA` reader - DBUS busy monitor interrupt enbale"]
+pub type CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_R = crate::BitReader;
+#[doc = "Field `CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA` writer - DBUS busy monitor interrupt enbale"]
+pub type CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Core0 dram0 area0 read monitor interrupt enable"]
+    #[inline(always)]
+    pub fn core_0_area_dram0_0_rd_intr_ena(&self) -> CORE_0_AREA_DRAM0_0_RD_INTR_ENA_R {
+        CORE_0_AREA_DRAM0_0_RD_INTR_ENA_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Core0 dram0 area0 write monitor interrupt enable"]
+    #[inline(always)]
+    pub fn core_0_area_dram0_0_wr_intr_ena(&self) -> CORE_0_AREA_DRAM0_0_WR_INTR_ENA_R {
+        CORE_0_AREA_DRAM0_0_WR_INTR_ENA_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Core0 dram0 area1 read monitor interrupt enable"]
+    #[inline(always)]
+    pub fn core_0_area_dram0_1_rd_intr_ena(&self) -> CORE_0_AREA_DRAM0_1_RD_INTR_ENA_R {
+        CORE_0_AREA_DRAM0_1_RD_INTR_ENA_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Core0 dram0 area1 write monitor interrupt enable"]
+    #[inline(always)]
+    pub fn core_0_area_dram0_1_wr_intr_ena(&self) -> CORE_0_AREA_DRAM0_1_WR_INTR_ENA_R {
+        CORE_0_AREA_DRAM0_1_WR_INTR_ENA_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Core0 PIF area0 read monitor interrupt enable"]
+    #[inline(always)]
+    pub fn core_0_area_pif_0_rd_intr_ena(&self) -> CORE_0_AREA_PIF_0_RD_INTR_ENA_R {
+        CORE_0_AREA_PIF_0_RD_INTR_ENA_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - Core0 PIF area0 write monitor interrupt enable"]
+    #[inline(always)]
+    pub fn core_0_area_pif_0_wr_intr_ena(&self) -> CORE_0_AREA_PIF_0_WR_INTR_ENA_R {
+        CORE_0_AREA_PIF_0_WR_INTR_ENA_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - Core0 PIF area1 read monitor interrupt enable"]
+    #[inline(always)]
+    pub fn core_0_area_pif_1_rd_intr_ena(&self) -> CORE_0_AREA_PIF_1_RD_INTR_ENA_R {
+        CORE_0_AREA_PIF_1_RD_INTR_ENA_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - Core0 PIF area1 write monitor interrupt enable"]
+    #[inline(always)]
+    pub fn core_0_area_pif_1_wr_intr_ena(&self) -> CORE_0_AREA_PIF_1_WR_INTR_ENA_R {
+        CORE_0_AREA_PIF_1_WR_INTR_ENA_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - Core0 stackpoint overflow monitor interrupt enable"]
+    #[inline(always)]
+    pub fn core_0_sp_spill_min_intr_ena(&self) -> CORE_0_SP_SPILL_MIN_INTR_ENA_R {
+        CORE_0_SP_SPILL_MIN_INTR_ENA_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - Core0 stackpoint underflow monitor interrupt enable"]
+    #[inline(always)]
+    pub fn core_0_sp_spill_max_intr_ena(&self) -> CORE_0_SP_SPILL_MAX_INTR_ENA_R {
+        CORE_0_SP_SPILL_MAX_INTR_ENA_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 10 - IBUS busy monitor interrupt enable"]
+    #[inline(always)]
+    pub fn core_0_iram0_exception_monitor_intr_ena(
+        &self,
+    ) -> CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_R {
+        CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_R::new(((self.bits >> 10) & 1) != 0)
+    }
+    #[doc = "Bit 11 - DBUS busy monitor interrupt enbale"]
+    #[inline(always)]
+    pub fn core_0_dram0_exception_monitor_intr_ena(
+        &self,
+    ) -> CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_R {
+        CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_R::new(((self.bits >> 11) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_0_INTR_ENA")
+            .field(
+                "core_0_area_dram0_0_rd_intr_ena",
+                &self.core_0_area_dram0_0_rd_intr_ena(),
+            )
+            .field(
+                "core_0_area_dram0_0_wr_intr_ena",
+                &self.core_0_area_dram0_0_wr_intr_ena(),
+            )
+            .field(
+                "core_0_area_dram0_1_rd_intr_ena",
+                &self.core_0_area_dram0_1_rd_intr_ena(),
+            )
+            .field(
+                "core_0_area_dram0_1_wr_intr_ena",
+                &self.core_0_area_dram0_1_wr_intr_ena(),
+            )
+            .field(
+                "core_0_area_pif_0_rd_intr_ena",
+                &self.core_0_area_pif_0_rd_intr_ena(),
+            )
+            .field(
+                "core_0_area_pif_0_wr_intr_ena",
+                &self.core_0_area_pif_0_wr_intr_ena(),
+            )
+            .field(
+                "core_0_area_pif_1_rd_intr_ena",
+                &self.core_0_area_pif_1_rd_intr_ena(),
+            )
+            .field(
+                "core_0_area_pif_1_wr_intr_ena",
+                &self.core_0_area_pif_1_wr_intr_ena(),
+            )
+            .field(
+                "core_0_sp_spill_min_intr_ena",
+                &self.core_0_sp_spill_min_intr_ena(),
+            )
+            .field(
+                "core_0_sp_spill_max_intr_ena",
+                &self.core_0_sp_spill_max_intr_ena(),
+            )
+            .field(
+                "core_0_iram0_exception_monitor_intr_ena",
+                &self.core_0_iram0_exception_monitor_intr_ena(),
+            )
+            .field(
+                "core_0_dram0_exception_monitor_intr_ena",
+                &self.core_0_dram0_exception_monitor_intr_ena(),
+            )
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Core0 dram0 area0 read monitor interrupt enable"]
+    #[inline(always)]
+    pub fn core_0_area_dram0_0_rd_intr_ena(
+        &mut self,
+    ) -> CORE_0_AREA_DRAM0_0_RD_INTR_ENA_W<CORE_0_INTR_ENA_SPEC> {
+        CORE_0_AREA_DRAM0_0_RD_INTR_ENA_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - Core0 dram0 area0 write monitor interrupt enable"]
+    #[inline(always)]
+    pub fn core_0_area_dram0_0_wr_intr_ena(
+        &mut self,
+    ) -> CORE_0_AREA_DRAM0_0_WR_INTR_ENA_W<CORE_0_INTR_ENA_SPEC> {
+        CORE_0_AREA_DRAM0_0_WR_INTR_ENA_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - Core0 dram0 area1 read monitor interrupt enable"]
+    #[inline(always)]
+    pub fn core_0_area_dram0_1_rd_intr_ena(
+        &mut self,
+    ) -> CORE_0_AREA_DRAM0_1_RD_INTR_ENA_W<CORE_0_INTR_ENA_SPEC> {
+        CORE_0_AREA_DRAM0_1_RD_INTR_ENA_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - Core0 dram0 area1 write monitor interrupt enable"]
+    #[inline(always)]
+    pub fn core_0_area_dram0_1_wr_intr_ena(
+        &mut self,
+    ) -> CORE_0_AREA_DRAM0_1_WR_INTR_ENA_W<CORE_0_INTR_ENA_SPEC> {
+        CORE_0_AREA_DRAM0_1_WR_INTR_ENA_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - Core0 PIF area0 read monitor interrupt enable"]
+    #[inline(always)]
+    pub fn core_0_area_pif_0_rd_intr_ena(
+        &mut self,
+    ) -> CORE_0_AREA_PIF_0_RD_INTR_ENA_W<CORE_0_INTR_ENA_SPEC> {
+        CORE_0_AREA_PIF_0_RD_INTR_ENA_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - Core0 PIF area0 write monitor interrupt enable"]
+    #[inline(always)]
+    pub fn core_0_area_pif_0_wr_intr_ena(
+        &mut self,
+    ) -> CORE_0_AREA_PIF_0_WR_INTR_ENA_W<CORE_0_INTR_ENA_SPEC> {
+        CORE_0_AREA_PIF_0_WR_INTR_ENA_W::new(self, 5)
+    }
+    #[doc = "Bit 6 - Core0 PIF area1 read monitor interrupt enable"]
+    #[inline(always)]
+    pub fn core_0_area_pif_1_rd_intr_ena(
+        &mut self,
+    ) -> CORE_0_AREA_PIF_1_RD_INTR_ENA_W<CORE_0_INTR_ENA_SPEC> {
+        CORE_0_AREA_PIF_1_RD_INTR_ENA_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - Core0 PIF area1 write monitor interrupt enable"]
+    #[inline(always)]
+    pub fn core_0_area_pif_1_wr_intr_ena(
+        &mut self,
+    ) -> CORE_0_AREA_PIF_1_WR_INTR_ENA_W<CORE_0_INTR_ENA_SPEC> {
+        CORE_0_AREA_PIF_1_WR_INTR_ENA_W::new(self, 7)
+    }
+    #[doc = "Bit 8 - Core0 stackpoint overflow monitor interrupt enable"]
+    #[inline(always)]
+    pub fn core_0_sp_spill_min_intr_ena(
+        &mut self,
+    ) -> CORE_0_SP_SPILL_MIN_INTR_ENA_W<CORE_0_INTR_ENA_SPEC> {
+        CORE_0_SP_SPILL_MIN_INTR_ENA_W::new(self, 8)
+    }
+    #[doc = "Bit 9 - Core0 stackpoint underflow monitor interrupt enable"]
+    #[inline(always)]
+    pub fn core_0_sp_spill_max_intr_ena(
+        &mut self,
+    ) -> CORE_0_SP_SPILL_MAX_INTR_ENA_W<CORE_0_INTR_ENA_SPEC> {
+        CORE_0_SP_SPILL_MAX_INTR_ENA_W::new(self, 9)
+    }
+    #[doc = "Bit 10 - IBUS busy monitor interrupt enable"]
+    #[inline(always)]
+    pub fn core_0_iram0_exception_monitor_intr_ena(
+        &mut self,
+    ) -> CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_W<CORE_0_INTR_ENA_SPEC> {
+        CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_W::new(self, 10)
+    }
+    #[doc = "Bit 11 - DBUS busy monitor interrupt enbale"]
+    #[inline(always)]
+    pub fn core_0_dram0_exception_monitor_intr_ena(
+        &mut self,
+    ) -> CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_W<CORE_0_INTR_ENA_SPEC> {
+        CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_W::new(self, 11)
+    }
+}
+#[doc = "core0 monitor interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_intr_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_intr_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_0_INTR_ENA_SPEC;
+impl crate::RegisterSpec for CORE_0_INTR_ENA_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_0_intr_ena::R`](R) reader structure"]
+impl crate::Readable for CORE_0_INTR_ENA_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`core_0_intr_ena::W`](W) writer structure"]
+impl crate::Writable for CORE_0_INTR_ENA_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CORE_0_INTR_ENA to value 0"]
+impl crate::Resettable for CORE_0_INTR_ENA_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/core_0_intr_raw.rs

@@ -0,0 +1,136 @@
+#[doc = "Register `CORE_0_INTR_RAW` reader"]
+pub type R = crate::R<CORE_0_INTR_RAW_SPEC>;
+#[doc = "Field `CORE_0_AREA_DRAM0_0_RD_RAW` reader - Core0 dram0 area0 read monitor interrupt status"]
+pub type CORE_0_AREA_DRAM0_0_RD_RAW_R = crate::BitReader;
+#[doc = "Field `CORE_0_AREA_DRAM0_0_WR_RAW` reader - Core0 dram0 area0 write monitor interrupt status"]
+pub type CORE_0_AREA_DRAM0_0_WR_RAW_R = crate::BitReader;
+#[doc = "Field `CORE_0_AREA_DRAM0_1_RD_RAW` reader - Core0 dram0 area1 read monitor interrupt status"]
+pub type CORE_0_AREA_DRAM0_1_RD_RAW_R = crate::BitReader;
+#[doc = "Field `CORE_0_AREA_DRAM0_1_WR_RAW` reader - Core0 dram0 area1 write monitor interrupt status"]
+pub type CORE_0_AREA_DRAM0_1_WR_RAW_R = crate::BitReader;
+#[doc = "Field `CORE_0_AREA_PIF_0_RD_RAW` reader - Core0 PIF area0 read monitor interrupt status"]
+pub type CORE_0_AREA_PIF_0_RD_RAW_R = crate::BitReader;
+#[doc = "Field `CORE_0_AREA_PIF_0_WR_RAW` reader - Core0 PIF area0 write monitor interrupt status"]
+pub type CORE_0_AREA_PIF_0_WR_RAW_R = crate::BitReader;
+#[doc = "Field `CORE_0_AREA_PIF_1_RD_RAW` reader - Core0 PIF area1 read monitor interrupt status"]
+pub type CORE_0_AREA_PIF_1_RD_RAW_R = crate::BitReader;
+#[doc = "Field `CORE_0_AREA_PIF_1_WR_RAW` reader - Core0 PIF area1 write monitor interrupt status"]
+pub type CORE_0_AREA_PIF_1_WR_RAW_R = crate::BitReader;
+#[doc = "Field `CORE_0_SP_SPILL_MIN_RAW` reader - Core0 stackpoint overflow monitor interrupt status"]
+pub type CORE_0_SP_SPILL_MIN_RAW_R = crate::BitReader;
+#[doc = "Field `CORE_0_SP_SPILL_MAX_RAW` reader - Core0 stackpoint underflow monitor interrupt status"]
+pub type CORE_0_SP_SPILL_MAX_RAW_R = crate::BitReader;
+#[doc = "Field `CORE_0_IRAM0_EXCEPTION_MONITOR_RAW` reader - IBUS busy monitor interrupt status"]
+pub type CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_R = crate::BitReader;
+#[doc = "Field `CORE_0_DRAM0_EXCEPTION_MONITOR_RAW` reader - DBUS busy monitor initerrupt status"]
+pub type CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_R = crate::BitReader;
+impl R {
+    #[doc = "Bit 0 - Core0 dram0 area0 read monitor interrupt status"]
+    #[inline(always)]
+    pub fn core_0_area_dram0_0_rd_raw(&self) -> CORE_0_AREA_DRAM0_0_RD_RAW_R {
+        CORE_0_AREA_DRAM0_0_RD_RAW_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Core0 dram0 area0 write monitor interrupt status"]
+    #[inline(always)]
+    pub fn core_0_area_dram0_0_wr_raw(&self) -> CORE_0_AREA_DRAM0_0_WR_RAW_R {
+        CORE_0_AREA_DRAM0_0_WR_RAW_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Core0 dram0 area1 read monitor interrupt status"]
+    #[inline(always)]
+    pub fn core_0_area_dram0_1_rd_raw(&self) -> CORE_0_AREA_DRAM0_1_RD_RAW_R {
+        CORE_0_AREA_DRAM0_1_RD_RAW_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Core0 dram0 area1 write monitor interrupt status"]
+    #[inline(always)]
+    pub fn core_0_area_dram0_1_wr_raw(&self) -> CORE_0_AREA_DRAM0_1_WR_RAW_R {
+        CORE_0_AREA_DRAM0_1_WR_RAW_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Core0 PIF area0 read monitor interrupt status"]
+    #[inline(always)]
+    pub fn core_0_area_pif_0_rd_raw(&self) -> CORE_0_AREA_PIF_0_RD_RAW_R {
+        CORE_0_AREA_PIF_0_RD_RAW_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - Core0 PIF area0 write monitor interrupt status"]
+    #[inline(always)]
+    pub fn core_0_area_pif_0_wr_raw(&self) -> CORE_0_AREA_PIF_0_WR_RAW_R {
+        CORE_0_AREA_PIF_0_WR_RAW_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - Core0 PIF area1 read monitor interrupt status"]
+    #[inline(always)]
+    pub fn core_0_area_pif_1_rd_raw(&self) -> CORE_0_AREA_PIF_1_RD_RAW_R {
+        CORE_0_AREA_PIF_1_RD_RAW_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - Core0 PIF area1 write monitor interrupt status"]
+    #[inline(always)]
+    pub fn core_0_area_pif_1_wr_raw(&self) -> CORE_0_AREA_PIF_1_WR_RAW_R {
+        CORE_0_AREA_PIF_1_WR_RAW_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - Core0 stackpoint overflow monitor interrupt status"]
+    #[inline(always)]
+    pub fn core_0_sp_spill_min_raw(&self) -> CORE_0_SP_SPILL_MIN_RAW_R {
+        CORE_0_SP_SPILL_MIN_RAW_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - Core0 stackpoint underflow monitor interrupt status"]
+    #[inline(always)]
+    pub fn core_0_sp_spill_max_raw(&self) -> CORE_0_SP_SPILL_MAX_RAW_R {
+        CORE_0_SP_SPILL_MAX_RAW_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 10 - IBUS busy monitor interrupt status"]
+    #[inline(always)]
+    pub fn core_0_iram0_exception_monitor_raw(&self) -> CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_R {
+        CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_R::new(((self.bits >> 10) & 1) != 0)
+    }
+    #[doc = "Bit 11 - DBUS busy monitor initerrupt status"]
+    #[inline(always)]
+    pub fn core_0_dram0_exception_monitor_raw(&self) -> CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_R {
+        CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_R::new(((self.bits >> 11) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_0_INTR_RAW")
+            .field(
+                "core_0_area_dram0_0_rd_raw",
+                &self.core_0_area_dram0_0_rd_raw(),
+            )
+            .field(
+                "core_0_area_dram0_0_wr_raw",
+                &self.core_0_area_dram0_0_wr_raw(),
+            )
+            .field(
+                "core_0_area_dram0_1_rd_raw",
+                &self.core_0_area_dram0_1_rd_raw(),
+            )
+            .field(
+                "core_0_area_dram0_1_wr_raw",
+                &self.core_0_area_dram0_1_wr_raw(),
+            )
+            .field("core_0_area_pif_0_rd_raw", &self.core_0_area_pif_0_rd_raw())
+            .field("core_0_area_pif_0_wr_raw", &self.core_0_area_pif_0_wr_raw())
+            .field("core_0_area_pif_1_rd_raw", &self.core_0_area_pif_1_rd_raw())
+            .field("core_0_area_pif_1_wr_raw", &self.core_0_area_pif_1_wr_raw())
+            .field("core_0_sp_spill_min_raw", &self.core_0_sp_spill_min_raw())
+            .field("core_0_sp_spill_max_raw", &self.core_0_sp_spill_max_raw())
+            .field(
+                "core_0_iram0_exception_monitor_raw",
+                &self.core_0_iram0_exception_monitor_raw(),
+            )
+            .field(
+                "core_0_dram0_exception_monitor_raw",
+                &self.core_0_dram0_exception_monitor_raw(),
+            )
+            .finish()
+    }
+}
+#[doc = "core0 monitor interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_intr_raw::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_0_INTR_RAW_SPEC;
+impl crate::RegisterSpec for CORE_0_INTR_RAW_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_0_intr_raw::R`](R) reader structure"]
+impl crate::Readable for CORE_0_INTR_RAW_SPEC {}
+#[doc = "`reset()` method sets CORE_0_INTR_RAW to value 0"]
+impl crate::Resettable for CORE_0_INTR_RAW_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/core_0_iram0_exception_monitor_0.rs

@@ -0,0 +1,55 @@
+#[doc = "Register `CORE_0_IRAM0_EXCEPTION_MONITOR_0` reader"]
+pub type R = crate::R<CORE_0_IRAM0_EXCEPTION_MONITOR_0_SPEC>;
+#[doc = "Field `CORE_0_IRAM0_RECORDING_ADDR_0` reader - The first iram0's addr\\[25:2\\] status when trigger IRAM busy interrupt"]
+pub type CORE_0_IRAM0_RECORDING_ADDR_0_R = crate::FieldReader<u32>;
+#[doc = "Field `CORE_0_IRAM0_RECORDING_WR_0` reader - The first iram0's wr status when trigger IRAM busy interrupt"]
+pub type CORE_0_IRAM0_RECORDING_WR_0_R = crate::BitReader;
+#[doc = "Field `CORE_0_IRAM0_RECORDING_LOADSTORE_0` reader - The first iram0's loadstore status when trigger IRAM busy interrupt"]
+pub type CORE_0_IRAM0_RECORDING_LOADSTORE_0_R = crate::BitReader;
+impl R {
+    #[doc = "Bits 0:23 - The first iram0's addr\\[25:2\\] status when trigger IRAM busy interrupt"]
+    #[inline(always)]
+    pub fn core_0_iram0_recording_addr_0(&self) -> CORE_0_IRAM0_RECORDING_ADDR_0_R {
+        CORE_0_IRAM0_RECORDING_ADDR_0_R::new(self.bits & 0x00ff_ffff)
+    }
+    #[doc = "Bit 24 - The first iram0's wr status when trigger IRAM busy interrupt"]
+    #[inline(always)]
+    pub fn core_0_iram0_recording_wr_0(&self) -> CORE_0_IRAM0_RECORDING_WR_0_R {
+        CORE_0_IRAM0_RECORDING_WR_0_R::new(((self.bits >> 24) & 1) != 0)
+    }
+    #[doc = "Bit 25 - The first iram0's loadstore status when trigger IRAM busy interrupt"]
+    #[inline(always)]
+    pub fn core_0_iram0_recording_loadstore_0(&self) -> CORE_0_IRAM0_RECORDING_LOADSTORE_0_R {
+        CORE_0_IRAM0_RECORDING_LOADSTORE_0_R::new(((self.bits >> 25) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_0_IRAM0_EXCEPTION_MONITOR_0")
+            .field(
+                "core_0_iram0_recording_addr_0",
+                &self.core_0_iram0_recording_addr_0(),
+            )
+            .field(
+                "core_0_iram0_recording_wr_0",
+                &self.core_0_iram0_recording_wr_0(),
+            )
+            .field(
+                "core_0_iram0_recording_loadstore_0",
+                &self.core_0_iram0_recording_loadstore_0(),
+            )
+            .finish()
+    }
+}
+#[doc = "core0 bus busy status regsiter\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_iram0_exception_monitor_0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_0_IRAM0_EXCEPTION_MONITOR_0_SPEC;
+impl crate::RegisterSpec for CORE_0_IRAM0_EXCEPTION_MONITOR_0_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_0_iram0_exception_monitor_0::R`](R) reader structure"]
+impl crate::Readable for CORE_0_IRAM0_EXCEPTION_MONITOR_0_SPEC {}
+#[doc = "`reset()` method sets CORE_0_IRAM0_EXCEPTION_MONITOR_0 to value 0"]
+impl crate::Resettable for CORE_0_IRAM0_EXCEPTION_MONITOR_0_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/core_0_iram0_exception_monitor_1.rs

@@ -0,0 +1,55 @@
+#[doc = "Register `CORE_0_IRAM0_EXCEPTION_MONITOR_1` reader"]
+pub type R = crate::R<CORE_0_IRAM0_EXCEPTION_MONITOR_1_SPEC>;
+#[doc = "Field `CORE_0_IRAM0_RECORDING_ADDR_1` reader - The second iram0's addr\\[25:2\\] status when trigger IRAM busy interrupt"]
+pub type CORE_0_IRAM0_RECORDING_ADDR_1_R = crate::FieldReader<u32>;
+#[doc = "Field `CORE_0_IRAM0_RECORDING_WR_1` reader - The second iram0's wr status when trigger IRAM busy interrupt"]
+pub type CORE_0_IRAM0_RECORDING_WR_1_R = crate::BitReader;
+#[doc = "Field `CORE_0_IRAM0_RECORDING_LOADSTORE_1` reader - The second iram0's loadstore status when trigger IRAM busy interrupt"]
+pub type CORE_0_IRAM0_RECORDING_LOADSTORE_1_R = crate::BitReader;
+impl R {
+    #[doc = "Bits 0:23 - The second iram0's addr\\[25:2\\] status when trigger IRAM busy interrupt"]
+    #[inline(always)]
+    pub fn core_0_iram0_recording_addr_1(&self) -> CORE_0_IRAM0_RECORDING_ADDR_1_R {
+        CORE_0_IRAM0_RECORDING_ADDR_1_R::new(self.bits & 0x00ff_ffff)
+    }
+    #[doc = "Bit 24 - The second iram0's wr status when trigger IRAM busy interrupt"]
+    #[inline(always)]
+    pub fn core_0_iram0_recording_wr_1(&self) -> CORE_0_IRAM0_RECORDING_WR_1_R {
+        CORE_0_IRAM0_RECORDING_WR_1_R::new(((self.bits >> 24) & 1) != 0)
+    }
+    #[doc = "Bit 25 - The second iram0's loadstore status when trigger IRAM busy interrupt"]
+    #[inline(always)]
+    pub fn core_0_iram0_recording_loadstore_1(&self) -> CORE_0_IRAM0_RECORDING_LOADSTORE_1_R {
+        CORE_0_IRAM0_RECORDING_LOADSTORE_1_R::new(((self.bits >> 25) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_0_IRAM0_EXCEPTION_MONITOR_1")
+            .field(
+                "core_0_iram0_recording_addr_1",
+                &self.core_0_iram0_recording_addr_1(),
+            )
+            .field(
+                "core_0_iram0_recording_wr_1",
+                &self.core_0_iram0_recording_wr_1(),
+            )
+            .field(
+                "core_0_iram0_recording_loadstore_1",
+                &self.core_0_iram0_recording_loadstore_1(),
+            )
+            .finish()
+    }
+}
+#[doc = "core0 bus busy status regsiter\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_iram0_exception_monitor_1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_0_IRAM0_EXCEPTION_MONITOR_1_SPEC;
+impl crate::RegisterSpec for CORE_0_IRAM0_EXCEPTION_MONITOR_1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_0_iram0_exception_monitor_1::R`](R) reader structure"]
+impl crate::Readable for CORE_0_IRAM0_EXCEPTION_MONITOR_1_SPEC {}
+#[doc = "`reset()` method sets CORE_0_IRAM0_EXCEPTION_MONITOR_1 to value 0"]
+impl crate::Resettable for CORE_0_IRAM0_EXCEPTION_MONITOR_1_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/core_0_montr_ena.rs

@@ -0,0 +1,250 @@
+#[doc = "Register `CORE_0_MONTR_ENA` reader"]
+pub type R = crate::R<CORE_0_MONTR_ENA_SPEC>;
+#[doc = "Register `CORE_0_MONTR_ENA` writer"]
+pub type W = crate::W<CORE_0_MONTR_ENA_SPEC>;
+#[doc = "Field `CORE_0_AREA_DRAM0_0_RD_ENA` reader - Core0 dram0 area0 read monitor enable"]
+pub type CORE_0_AREA_DRAM0_0_RD_ENA_R = crate::BitReader;
+#[doc = "Field `CORE_0_AREA_DRAM0_0_RD_ENA` writer - Core0 dram0 area0 read monitor enable"]
+pub type CORE_0_AREA_DRAM0_0_RD_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_0_AREA_DRAM0_0_WR_ENA` reader - Core0 dram0 area0 write monitor enable"]
+pub type CORE_0_AREA_DRAM0_0_WR_ENA_R = crate::BitReader;
+#[doc = "Field `CORE_0_AREA_DRAM0_0_WR_ENA` writer - Core0 dram0 area0 write monitor enable"]
+pub type CORE_0_AREA_DRAM0_0_WR_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_0_AREA_DRAM0_1_RD_ENA` reader - Core0 dram0 area1 read monitor enable"]
+pub type CORE_0_AREA_DRAM0_1_RD_ENA_R = crate::BitReader;
+#[doc = "Field `CORE_0_AREA_DRAM0_1_RD_ENA` writer - Core0 dram0 area1 read monitor enable"]
+pub type CORE_0_AREA_DRAM0_1_RD_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_0_AREA_DRAM0_1_WR_ENA` reader - Core0 dram0 area1 write monitor enable"]
+pub type CORE_0_AREA_DRAM0_1_WR_ENA_R = crate::BitReader;
+#[doc = "Field `CORE_0_AREA_DRAM0_1_WR_ENA` writer - Core0 dram0 area1 write monitor enable"]
+pub type CORE_0_AREA_DRAM0_1_WR_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_0_AREA_PIF_0_RD_ENA` reader - Core0 PIF area0 read monitor enable"]
+pub type CORE_0_AREA_PIF_0_RD_ENA_R = crate::BitReader;
+#[doc = "Field `CORE_0_AREA_PIF_0_RD_ENA` writer - Core0 PIF area0 read monitor enable"]
+pub type CORE_0_AREA_PIF_0_RD_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_0_AREA_PIF_0_WR_ENA` reader - Core0 PIF area0 write monitor enable"]
+pub type CORE_0_AREA_PIF_0_WR_ENA_R = crate::BitReader;
+#[doc = "Field `CORE_0_AREA_PIF_0_WR_ENA` writer - Core0 PIF area0 write monitor enable"]
+pub type CORE_0_AREA_PIF_0_WR_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_0_AREA_PIF_1_RD_ENA` reader - Core0 PIF area1 read monitor enable"]
+pub type CORE_0_AREA_PIF_1_RD_ENA_R = crate::BitReader;
+#[doc = "Field `CORE_0_AREA_PIF_1_RD_ENA` writer - Core0 PIF area1 read monitor enable"]
+pub type CORE_0_AREA_PIF_1_RD_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_0_AREA_PIF_1_WR_ENA` reader - Core0 PIF area1 write monitor enable"]
+pub type CORE_0_AREA_PIF_1_WR_ENA_R = crate::BitReader;
+#[doc = "Field `CORE_0_AREA_PIF_1_WR_ENA` writer - Core0 PIF area1 write monitor enable"]
+pub type CORE_0_AREA_PIF_1_WR_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_0_SP_SPILL_MIN_ENA` reader - Core0 stackpoint overflow monitor enable"]
+pub type CORE_0_SP_SPILL_MIN_ENA_R = crate::BitReader;
+#[doc = "Field `CORE_0_SP_SPILL_MIN_ENA` writer - Core0 stackpoint overflow monitor enable"]
+pub type CORE_0_SP_SPILL_MIN_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_0_SP_SPILL_MAX_ENA` reader - Core0 stackpoint underflow monitor enable"]
+pub type CORE_0_SP_SPILL_MAX_ENA_R = crate::BitReader;
+#[doc = "Field `CORE_0_SP_SPILL_MAX_ENA` writer - Core0 stackpoint underflow monitor enable"]
+pub type CORE_0_SP_SPILL_MAX_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_0_IRAM0_EXCEPTION_MONITOR_ENA` reader - IBUS busy monitor enable"]
+pub type CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_R = crate::BitReader;
+#[doc = "Field `CORE_0_IRAM0_EXCEPTION_MONITOR_ENA` writer - IBUS busy monitor enable"]
+pub type CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_0_DRAM0_EXCEPTION_MONITOR_ENA` reader - DBUS busy monitor enbale"]
+pub type CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_R = crate::BitReader;
+#[doc = "Field `CORE_0_DRAM0_EXCEPTION_MONITOR_ENA` writer - DBUS busy monitor enbale"]
+pub type CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Core0 dram0 area0 read monitor enable"]
+    #[inline(always)]
+    pub fn core_0_area_dram0_0_rd_ena(&self) -> CORE_0_AREA_DRAM0_0_RD_ENA_R {
+        CORE_0_AREA_DRAM0_0_RD_ENA_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Core0 dram0 area0 write monitor enable"]
+    #[inline(always)]
+    pub fn core_0_area_dram0_0_wr_ena(&self) -> CORE_0_AREA_DRAM0_0_WR_ENA_R {
+        CORE_0_AREA_DRAM0_0_WR_ENA_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Core0 dram0 area1 read monitor enable"]
+    #[inline(always)]
+    pub fn core_0_area_dram0_1_rd_ena(&self) -> CORE_0_AREA_DRAM0_1_RD_ENA_R {
+        CORE_0_AREA_DRAM0_1_RD_ENA_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Core0 dram0 area1 write monitor enable"]
+    #[inline(always)]
+    pub fn core_0_area_dram0_1_wr_ena(&self) -> CORE_0_AREA_DRAM0_1_WR_ENA_R {
+        CORE_0_AREA_DRAM0_1_WR_ENA_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Core0 PIF area0 read monitor enable"]
+    #[inline(always)]
+    pub fn core_0_area_pif_0_rd_ena(&self) -> CORE_0_AREA_PIF_0_RD_ENA_R {
+        CORE_0_AREA_PIF_0_RD_ENA_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - Core0 PIF area0 write monitor enable"]
+    #[inline(always)]
+    pub fn core_0_area_pif_0_wr_ena(&self) -> CORE_0_AREA_PIF_0_WR_ENA_R {
+        CORE_0_AREA_PIF_0_WR_ENA_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - Core0 PIF area1 read monitor enable"]
+    #[inline(always)]
+    pub fn core_0_area_pif_1_rd_ena(&self) -> CORE_0_AREA_PIF_1_RD_ENA_R {
+        CORE_0_AREA_PIF_1_RD_ENA_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - Core0 PIF area1 write monitor enable"]
+    #[inline(always)]
+    pub fn core_0_area_pif_1_wr_ena(&self) -> CORE_0_AREA_PIF_1_WR_ENA_R {
+        CORE_0_AREA_PIF_1_WR_ENA_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - Core0 stackpoint overflow monitor enable"]
+    #[inline(always)]
+    pub fn core_0_sp_spill_min_ena(&self) -> CORE_0_SP_SPILL_MIN_ENA_R {
+        CORE_0_SP_SPILL_MIN_ENA_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - Core0 stackpoint underflow monitor enable"]
+    #[inline(always)]
+    pub fn core_0_sp_spill_max_ena(&self) -> CORE_0_SP_SPILL_MAX_ENA_R {
+        CORE_0_SP_SPILL_MAX_ENA_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 10 - IBUS busy monitor enable"]
+    #[inline(always)]
+    pub fn core_0_iram0_exception_monitor_ena(&self) -> CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_R {
+        CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_R::new(((self.bits >> 10) & 1) != 0)
+    }
+    #[doc = "Bit 11 - DBUS busy monitor enbale"]
+    #[inline(always)]
+    pub fn core_0_dram0_exception_monitor_ena(&self) -> CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_R {
+        CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_R::new(((self.bits >> 11) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_0_MONTR_ENA")
+            .field(
+                "core_0_area_dram0_0_rd_ena",
+                &self.core_0_area_dram0_0_rd_ena(),
+            )
+            .field(
+                "core_0_area_dram0_0_wr_ena",
+                &self.core_0_area_dram0_0_wr_ena(),
+            )
+            .field(
+                "core_0_area_dram0_1_rd_ena",
+                &self.core_0_area_dram0_1_rd_ena(),
+            )
+            .field(
+                "core_0_area_dram0_1_wr_ena",
+                &self.core_0_area_dram0_1_wr_ena(),
+            )
+            .field("core_0_area_pif_0_rd_ena", &self.core_0_area_pif_0_rd_ena())
+            .field("core_0_area_pif_0_wr_ena", &self.core_0_area_pif_0_wr_ena())
+            .field("core_0_area_pif_1_rd_ena", &self.core_0_area_pif_1_rd_ena())
+            .field("core_0_area_pif_1_wr_ena", &self.core_0_area_pif_1_wr_ena())
+            .field("core_0_sp_spill_min_ena", &self.core_0_sp_spill_min_ena())
+            .field("core_0_sp_spill_max_ena", &self.core_0_sp_spill_max_ena())
+            .field(
+                "core_0_iram0_exception_monitor_ena",
+                &self.core_0_iram0_exception_monitor_ena(),
+            )
+            .field(
+                "core_0_dram0_exception_monitor_ena",
+                &self.core_0_dram0_exception_monitor_ena(),
+            )
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Core0 dram0 area0 read monitor enable"]
+    #[inline(always)]
+    pub fn core_0_area_dram0_0_rd_ena(
+        &mut self,
+    ) -> CORE_0_AREA_DRAM0_0_RD_ENA_W<CORE_0_MONTR_ENA_SPEC> {
+        CORE_0_AREA_DRAM0_0_RD_ENA_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - Core0 dram0 area0 write monitor enable"]
+    #[inline(always)]
+    pub fn core_0_area_dram0_0_wr_ena(
+        &mut self,
+    ) -> CORE_0_AREA_DRAM0_0_WR_ENA_W<CORE_0_MONTR_ENA_SPEC> {
+        CORE_0_AREA_DRAM0_0_WR_ENA_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - Core0 dram0 area1 read monitor enable"]
+    #[inline(always)]
+    pub fn core_0_area_dram0_1_rd_ena(
+        &mut self,
+    ) -> CORE_0_AREA_DRAM0_1_RD_ENA_W<CORE_0_MONTR_ENA_SPEC> {
+        CORE_0_AREA_DRAM0_1_RD_ENA_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - Core0 dram0 area1 write monitor enable"]
+    #[inline(always)]
+    pub fn core_0_area_dram0_1_wr_ena(
+        &mut self,
+    ) -> CORE_0_AREA_DRAM0_1_WR_ENA_W<CORE_0_MONTR_ENA_SPEC> {
+        CORE_0_AREA_DRAM0_1_WR_ENA_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - Core0 PIF area0 read monitor enable"]
+    #[inline(always)]
+    pub fn core_0_area_pif_0_rd_ena(
+        &mut self,
+    ) -> CORE_0_AREA_PIF_0_RD_ENA_W<CORE_0_MONTR_ENA_SPEC> {
+        CORE_0_AREA_PIF_0_RD_ENA_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - Core0 PIF area0 write monitor enable"]
+    #[inline(always)]
+    pub fn core_0_area_pif_0_wr_ena(
+        &mut self,
+    ) -> CORE_0_AREA_PIF_0_WR_ENA_W<CORE_0_MONTR_ENA_SPEC> {
+        CORE_0_AREA_PIF_0_WR_ENA_W::new(self, 5)
+    }
+    #[doc = "Bit 6 - Core0 PIF area1 read monitor enable"]
+    #[inline(always)]
+    pub fn core_0_area_pif_1_rd_ena(
+        &mut self,
+    ) -> CORE_0_AREA_PIF_1_RD_ENA_W<CORE_0_MONTR_ENA_SPEC> {
+        CORE_0_AREA_PIF_1_RD_ENA_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - Core0 PIF area1 write monitor enable"]
+    #[inline(always)]
+    pub fn core_0_area_pif_1_wr_ena(
+        &mut self,
+    ) -> CORE_0_AREA_PIF_1_WR_ENA_W<CORE_0_MONTR_ENA_SPEC> {
+        CORE_0_AREA_PIF_1_WR_ENA_W::new(self, 7)
+    }
+    #[doc = "Bit 8 - Core0 stackpoint overflow monitor enable"]
+    #[inline(always)]
+    pub fn core_0_sp_spill_min_ena(&mut self) -> CORE_0_SP_SPILL_MIN_ENA_W<CORE_0_MONTR_ENA_SPEC> {
+        CORE_0_SP_SPILL_MIN_ENA_W::new(self, 8)
+    }
+    #[doc = "Bit 9 - Core0 stackpoint underflow monitor enable"]
+    #[inline(always)]
+    pub fn core_0_sp_spill_max_ena(&mut self) -> CORE_0_SP_SPILL_MAX_ENA_W<CORE_0_MONTR_ENA_SPEC> {
+        CORE_0_SP_SPILL_MAX_ENA_W::new(self, 9)
+    }
+    #[doc = "Bit 10 - IBUS busy monitor enable"]
+    #[inline(always)]
+    pub fn core_0_iram0_exception_monitor_ena(
+        &mut self,
+    ) -> CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_W<CORE_0_MONTR_ENA_SPEC> {
+        CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_W::new(self, 10)
+    }
+    #[doc = "Bit 11 - DBUS busy monitor enbale"]
+    #[inline(always)]
+    pub fn core_0_dram0_exception_monitor_ena(
+        &mut self,
+    ) -> CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_W<CORE_0_MONTR_ENA_SPEC> {
+        CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_W::new(self, 11)
+    }
+}
+#[doc = "core0 monitor enable configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_montr_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_montr_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_0_MONTR_ENA_SPEC;
+impl crate::RegisterSpec for CORE_0_MONTR_ENA_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_0_montr_ena::R`](R) reader structure"]
+impl crate::Readable for CORE_0_MONTR_ENA_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`core_0_montr_ena::W`](W) writer structure"]
+impl crate::Writable for CORE_0_MONTR_ENA_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CORE_0_MONTR_ENA to value 0"]
+impl crate::Resettable for CORE_0_MONTR_ENA_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/core_0_rcd_pdebugdata.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `CORE_0_RCD_PDEBUGDATA` reader"]
+pub type R = crate::R<CORE_0_RCD_PDEBUGDATA_SPEC>;
+#[doc = "Field `CORE_0_RCD_PDEBUGDATA` reader - core0_pdebugdata"]
+pub type CORE_0_RCD_PDEBUGDATA_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - core0_pdebugdata"]
+    #[inline(always)]
+    pub fn core_0_rcd_pdebugdata(&self) -> CORE_0_RCD_PDEBUGDATA_R {
+        CORE_0_RCD_PDEBUGDATA_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_0_RCD_PDEBUGDATA")
+            .field("core_0_rcd_pdebugdata", &self.core_0_rcd_pdebugdata())
+            .finish()
+    }
+}
+#[doc = "core0 pdebug status register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_rcd_pdebugdata::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_0_RCD_PDEBUGDATA_SPEC;
+impl crate::RegisterSpec for CORE_0_RCD_PDEBUGDATA_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_0_rcd_pdebugdata::R`](R) reader structure"]
+impl crate::Readable for CORE_0_RCD_PDEBUGDATA_SPEC {}
+#[doc = "`reset()` method sets CORE_0_RCD_PDEBUGDATA to value 0"]
+impl crate::Resettable for CORE_0_RCD_PDEBUGDATA_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/core_0_rcd_pdebugenable.rs

@@ -0,0 +1,49 @@
+#[doc = "Register `CORE_0_RCD_PDEBUGENABLE` reader"]
+pub type R = crate::R<CORE_0_RCD_PDEBUGENABLE_SPEC>;
+#[doc = "Register `CORE_0_RCD_PDEBUGENABLE` writer"]
+pub type W = crate::W<CORE_0_RCD_PDEBUGENABLE_SPEC>;
+#[doc = "Field `CORE_0_RCD_PDEBUGENABLE` reader - Core0 Pdebugenable,set 1 to open core0 Pdebug interface,then can get core0 PC"]
+pub type CORE_0_RCD_PDEBUGENABLE_R = crate::BitReader;
+#[doc = "Field `CORE_0_RCD_PDEBUGENABLE` writer - Core0 Pdebugenable,set 1 to open core0 Pdebug interface,then can get core0 PC"]
+pub type CORE_0_RCD_PDEBUGENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Core0 Pdebugenable,set 1 to open core0 Pdebug interface,then can get core0 PC"]
+    #[inline(always)]
+    pub fn core_0_rcd_pdebugenable(&self) -> CORE_0_RCD_PDEBUGENABLE_R {
+        CORE_0_RCD_PDEBUGENABLE_R::new((self.bits & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_0_RCD_PDEBUGENABLE")
+            .field("core_0_rcd_pdebugenable", &self.core_0_rcd_pdebugenable())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Core0 Pdebugenable,set 1 to open core0 Pdebug interface,then can get core0 PC"]
+    #[inline(always)]
+    pub fn core_0_rcd_pdebugenable(
+        &mut self,
+    ) -> CORE_0_RCD_PDEBUGENABLE_W<CORE_0_RCD_PDEBUGENABLE_SPEC> {
+        CORE_0_RCD_PDEBUGENABLE_W::new(self, 0)
+    }
+}
+#[doc = "core0 pdebug configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_rcd_pdebugenable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_rcd_pdebugenable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_0_RCD_PDEBUGENABLE_SPEC;
+impl crate::RegisterSpec for CORE_0_RCD_PDEBUGENABLE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_0_rcd_pdebugenable::R`](R) reader structure"]
+impl crate::Readable for CORE_0_RCD_PDEBUGENABLE_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`core_0_rcd_pdebugenable::W`](W) writer structure"]
+impl crate::Writable for CORE_0_RCD_PDEBUGENABLE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CORE_0_RCD_PDEBUGENABLE to value 0"]
+impl crate::Resettable for CORE_0_RCD_PDEBUGENABLE_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/core_0_rcd_pdebuginst.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `CORE_0_RCD_PDEBUGINST` reader"]
+pub type R = crate::R<CORE_0_RCD_PDEBUGINST_SPEC>;
+#[doc = "Field `CORE_0_RCD_PDEBUGINST` reader - core0 pdebuginst"]
+pub type CORE_0_RCD_PDEBUGINST_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - core0 pdebuginst"]
+    #[inline(always)]
+    pub fn core_0_rcd_pdebuginst(&self) -> CORE_0_RCD_PDEBUGINST_R {
+        CORE_0_RCD_PDEBUGINST_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_0_RCD_PDEBUGINST")
+            .field("core_0_rcd_pdebuginst", &self.core_0_rcd_pdebuginst())
+            .finish()
+    }
+}
+#[doc = "core0 pdebug status register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_rcd_pdebuginst::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_0_RCD_PDEBUGINST_SPEC;
+impl crate::RegisterSpec for CORE_0_RCD_PDEBUGINST_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_0_rcd_pdebuginst::R`](R) reader structure"]
+impl crate::Readable for CORE_0_RCD_PDEBUGINST_SPEC {}
+#[doc = "`reset()` method sets CORE_0_RCD_PDEBUGINST to value 0"]
+impl crate::Resettable for CORE_0_RCD_PDEBUGINST_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/core_0_rcd_pdebugls0addr.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `CORE_0_RCD_PDEBUGLS0ADDR` reader"]
+pub type R = crate::R<CORE_0_RCD_PDEBUGLS0ADDR_SPEC>;
+#[doc = "Field `CORE_0_RCD_PDEBUGLS0ADDR` reader - core0_pdebug_s0addr"]
+pub type CORE_0_RCD_PDEBUGLS0ADDR_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - core0_pdebug_s0addr"]
+    #[inline(always)]
+    pub fn core_0_rcd_pdebugls0addr(&self) -> CORE_0_RCD_PDEBUGLS0ADDR_R {
+        CORE_0_RCD_PDEBUGLS0ADDR_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_0_RCD_PDEBUGLS0ADDR")
+            .field("core_0_rcd_pdebugls0addr", &self.core_0_rcd_pdebugls0addr())
+            .finish()
+    }
+}
+#[doc = "core0 pdebug status register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_rcd_pdebugls0addr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_0_RCD_PDEBUGLS0ADDR_SPEC;
+impl crate::RegisterSpec for CORE_0_RCD_PDEBUGLS0ADDR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_0_rcd_pdebugls0addr::R`](R) reader structure"]
+impl crate::Readable for CORE_0_RCD_PDEBUGLS0ADDR_SPEC {}
+#[doc = "`reset()` method sets CORE_0_RCD_PDEBUGLS0ADDR to value 0"]
+impl crate::Resettable for CORE_0_RCD_PDEBUGLS0ADDR_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/core_0_rcd_pdebugls0data.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `CORE_0_RCD_PDEBUGLS0DATA` reader"]
+pub type R = crate::R<CORE_0_RCD_PDEBUGLS0DATA_SPEC>;
+#[doc = "Field `CORE_0_RCD_PDEBUGLS0DATA` reader - core0_pdebug_s0data"]
+pub type CORE_0_RCD_PDEBUGLS0DATA_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - core0_pdebug_s0data"]
+    #[inline(always)]
+    pub fn core_0_rcd_pdebugls0data(&self) -> CORE_0_RCD_PDEBUGLS0DATA_R {
+        CORE_0_RCD_PDEBUGLS0DATA_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_0_RCD_PDEBUGLS0DATA")
+            .field("core_0_rcd_pdebugls0data", &self.core_0_rcd_pdebugls0data())
+            .finish()
+    }
+}
+#[doc = "core0 pdebug status register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_rcd_pdebugls0data::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_0_RCD_PDEBUGLS0DATA_SPEC;
+impl crate::RegisterSpec for CORE_0_RCD_PDEBUGLS0DATA_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_0_rcd_pdebugls0data::R`](R) reader structure"]
+impl crate::Readable for CORE_0_RCD_PDEBUGLS0DATA_SPEC {}
+#[doc = "`reset()` method sets CORE_0_RCD_PDEBUGLS0DATA to value 0"]
+impl crate::Resettable for CORE_0_RCD_PDEBUGLS0DATA_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/core_0_rcd_pdebugls0stat.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `CORE_0_RCD_PDEBUGLS0STAT` reader"]
+pub type R = crate::R<CORE_0_RCD_PDEBUGLS0STAT_SPEC>;
+#[doc = "Field `CORE_0_RCD_PDEBUGLS0STAT` reader - core0_pdebug_s0stat"]
+pub type CORE_0_RCD_PDEBUGLS0STAT_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - core0_pdebug_s0stat"]
+    #[inline(always)]
+    pub fn core_0_rcd_pdebugls0stat(&self) -> CORE_0_RCD_PDEBUGLS0STAT_R {
+        CORE_0_RCD_PDEBUGLS0STAT_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_0_RCD_PDEBUGLS0STAT")
+            .field("core_0_rcd_pdebugls0stat", &self.core_0_rcd_pdebugls0stat())
+            .finish()
+    }
+}
+#[doc = "core0 pdebug status register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_rcd_pdebugls0stat::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_0_RCD_PDEBUGLS0STAT_SPEC;
+impl crate::RegisterSpec for CORE_0_RCD_PDEBUGLS0STAT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_0_rcd_pdebugls0stat::R`](R) reader structure"]
+impl crate::Readable for CORE_0_RCD_PDEBUGLS0STAT_SPEC {}
+#[doc = "`reset()` method sets CORE_0_RCD_PDEBUGLS0STAT to value 0"]
+impl crate::Resettable for CORE_0_RCD_PDEBUGLS0STAT_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/core_0_rcd_pdebugpc.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `CORE_0_RCD_PDEBUGPC` reader"]
+pub type R = crate::R<CORE_0_RCD_PDEBUGPC_SPEC>;
+#[doc = "Field `CORE_0_RCD_PDEBUGPC` reader - core0_pdebugPC"]
+pub type CORE_0_RCD_PDEBUGPC_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - core0_pdebugPC"]
+    #[inline(always)]
+    pub fn core_0_rcd_pdebugpc(&self) -> CORE_0_RCD_PDEBUGPC_R {
+        CORE_0_RCD_PDEBUGPC_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_0_RCD_PDEBUGPC")
+            .field("core_0_rcd_pdebugpc", &self.core_0_rcd_pdebugpc())
+            .finish()
+    }
+}
+#[doc = "core0 pdebug status register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_rcd_pdebugpc::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_0_RCD_PDEBUGPC_SPEC;
+impl crate::RegisterSpec for CORE_0_RCD_PDEBUGPC_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_0_rcd_pdebugpc::R`](R) reader structure"]
+impl crate::Readable for CORE_0_RCD_PDEBUGPC_SPEC {}
+#[doc = "`reset()` method sets CORE_0_RCD_PDEBUGPC to value 0"]
+impl crate::Resettable for CORE_0_RCD_PDEBUGPC_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/core_0_rcd_pdebugstatus.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `CORE_0_RCD_PDEBUGSTATUS` reader"]
+pub type R = crate::R<CORE_0_RCD_PDEBUGSTATUS_SPEC>;
+#[doc = "Field `CORE_0_RCD_PDEBUGSTATUS` reader - core0 pdebugstatus"]
+pub type CORE_0_RCD_PDEBUGSTATUS_R = crate::FieldReader;
+impl R {
+    #[doc = "Bits 0:7 - core0 pdebugstatus"]
+    #[inline(always)]
+    pub fn core_0_rcd_pdebugstatus(&self) -> CORE_0_RCD_PDEBUGSTATUS_R {
+        CORE_0_RCD_PDEBUGSTATUS_R::new((self.bits & 0xff) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_0_RCD_PDEBUGSTATUS")
+            .field("core_0_rcd_pdebugstatus", &self.core_0_rcd_pdebugstatus())
+            .finish()
+    }
+}
+#[doc = "core0 pdebug status register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_rcd_pdebugstatus::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_0_RCD_PDEBUGSTATUS_SPEC;
+impl crate::RegisterSpec for CORE_0_RCD_PDEBUGSTATUS_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_0_rcd_pdebugstatus::R`](R) reader structure"]
+impl crate::Readable for CORE_0_RCD_PDEBUGSTATUS_SPEC {}
+#[doc = "`reset()` method sets CORE_0_RCD_PDEBUGSTATUS to value 0"]
+impl crate::Resettable for CORE_0_RCD_PDEBUGSTATUS_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/core_0_rcd_recording.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `CORE_0_RCD_RECORDING` reader"]
+pub type R = crate::R<CORE_0_RCD_RECORDING_SPEC>;
+#[doc = "Register `CORE_0_RCD_RECORDING` writer"]
+pub type W = crate::W<CORE_0_RCD_RECORDING_SPEC>;
+#[doc = "Field `CORE_0_RCD_RECORDING` reader - Pdebug record enable,set 1 to record core0 pdebug interface signal"]
+pub type CORE_0_RCD_RECORDING_R = crate::BitReader;
+#[doc = "Field `CORE_0_RCD_RECORDING` writer - Pdebug record enable,set 1 to record core0 pdebug interface signal"]
+pub type CORE_0_RCD_RECORDING_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Pdebug record enable,set 1 to record core0 pdebug interface signal"]
+    #[inline(always)]
+    pub fn core_0_rcd_recording(&self) -> CORE_0_RCD_RECORDING_R {
+        CORE_0_RCD_RECORDING_R::new((self.bits & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_0_RCD_RECORDING")
+            .field("core_0_rcd_recording", &self.core_0_rcd_recording())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Pdebug record enable,set 1 to record core0 pdebug interface signal"]
+    #[inline(always)]
+    pub fn core_0_rcd_recording(&mut self) -> CORE_0_RCD_RECORDING_W<CORE_0_RCD_RECORDING_SPEC> {
+        CORE_0_RCD_RECORDING_W::new(self, 0)
+    }
+}
+#[doc = "core0 pdebug status register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_rcd_recording::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_rcd_recording::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_0_RCD_RECORDING_SPEC;
+impl crate::RegisterSpec for CORE_0_RCD_RECORDING_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_0_rcd_recording::R`](R) reader structure"]
+impl crate::Readable for CORE_0_RCD_RECORDING_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`core_0_rcd_recording::W`](W) writer structure"]
+impl crate::Writable for CORE_0_RCD_RECORDING_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CORE_0_RCD_RECORDING to value 0"]
+impl crate::Resettable for CORE_0_RCD_RECORDING_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/core_0_rcd_sp.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `CORE_0_RCD_SP` reader"]
+pub type R = crate::R<CORE_0_RCD_SP_SPEC>;
+#[doc = "Field `CORE_0_RCD_SP` reader - core0_stack pointer"]
+pub type CORE_0_RCD_SP_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - core0_stack pointer"]
+    #[inline(always)]
+    pub fn core_0_rcd_sp(&self) -> CORE_0_RCD_SP_R {
+        CORE_0_RCD_SP_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_0_RCD_SP")
+            .field("core_0_rcd_sp", &self.core_0_rcd_sp())
+            .finish()
+    }
+}
+#[doc = "core0 pdebug status register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_rcd_sp::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_0_RCD_SP_SPEC;
+impl crate::RegisterSpec for CORE_0_RCD_SP_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_0_rcd_sp::R`](R) reader structure"]
+impl crate::Readable for CORE_0_RCD_SP_SPEC {}
+#[doc = "`reset()` method sets CORE_0_RCD_SP to value 0"]
+impl crate::Resettable for CORE_0_RCD_SP_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/core_0_sp_max.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `CORE_0_SP_MAX` reader"]
+pub type R = crate::R<CORE_0_SP_MAX_SPEC>;
+#[doc = "Register `CORE_0_SP_MAX` writer"]
+pub type W = crate::W<CORE_0_SP_MAX_SPEC>;
+#[doc = "Field `CORE_0_SP_MAX` reader - stack max value"]
+pub type CORE_0_SP_MAX_R = crate::FieldReader<u32>;
+#[doc = "Field `CORE_0_SP_MAX` writer - stack max value"]
+pub type CORE_0_SP_MAX_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - stack max value"]
+    #[inline(always)]
+    pub fn core_0_sp_max(&self) -> CORE_0_SP_MAX_R {
+        CORE_0_SP_MAX_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_0_SP_MAX")
+            .field("core_0_sp_max", &self.core_0_sp_max())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - stack max value"]
+    #[inline(always)]
+    pub fn core_0_sp_max(&mut self) -> CORE_0_SP_MAX_W<CORE_0_SP_MAX_SPEC> {
+        CORE_0_SP_MAX_W::new(self, 0)
+    }
+}
+#[doc = "core0 sp region configuration regsiter\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_sp_max::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_sp_max::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_0_SP_MAX_SPEC;
+impl crate::RegisterSpec for CORE_0_SP_MAX_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_0_sp_max::R`](R) reader structure"]
+impl crate::Readable for CORE_0_SP_MAX_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`core_0_sp_max::W`](W) writer structure"]
+impl crate::Writable for CORE_0_SP_MAX_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CORE_0_SP_MAX to value 0xffff_ffff"]
+impl crate::Resettable for CORE_0_SP_MAX_SPEC {
+    const RESET_VALUE: u32 = 0xffff_ffff;
+}

vendor/esp32s3/src/assist_debug/core_0_sp_min.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `CORE_0_SP_MIN` reader"]
+pub type R = crate::R<CORE_0_SP_MIN_SPEC>;
+#[doc = "Register `CORE_0_SP_MIN` writer"]
+pub type W = crate::W<CORE_0_SP_MIN_SPEC>;
+#[doc = "Field `CORE_0_SP_MIN` reader - stack min value"]
+pub type CORE_0_SP_MIN_R = crate::FieldReader<u32>;
+#[doc = "Field `CORE_0_SP_MIN` writer - stack min value"]
+pub type CORE_0_SP_MIN_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - stack min value"]
+    #[inline(always)]
+    pub fn core_0_sp_min(&self) -> CORE_0_SP_MIN_R {
+        CORE_0_SP_MIN_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_0_SP_MIN")
+            .field("core_0_sp_min", &self.core_0_sp_min())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - stack min value"]
+    #[inline(always)]
+    pub fn core_0_sp_min(&mut self) -> CORE_0_SP_MIN_W<CORE_0_SP_MIN_SPEC> {
+        CORE_0_SP_MIN_W::new(self, 0)
+    }
+}
+#[doc = "core0 sp region configuration regsiter\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_sp_min::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_sp_min::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_0_SP_MIN_SPEC;
+impl crate::RegisterSpec for CORE_0_SP_MIN_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_0_sp_min::R`](R) reader structure"]
+impl crate::Readable for CORE_0_SP_MIN_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`core_0_sp_min::W`](W) writer structure"]
+impl crate::Writable for CORE_0_SP_MIN_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CORE_0_SP_MIN to value 0"]
+impl crate::Resettable for CORE_0_SP_MIN_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/core_0_sp_pc.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `CORE_0_SP_PC` reader"]
+pub type R = crate::R<CORE_0_SP_PC_SPEC>;
+#[doc = "Field `CORE_0_SP_PC` reader - the PC when first touch stack monitor interrupt"]
+pub type CORE_0_SP_PC_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - the PC when first touch stack monitor interrupt"]
+    #[inline(always)]
+    pub fn core_0_sp_pc(&self) -> CORE_0_SP_PC_R {
+        CORE_0_SP_PC_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_0_SP_PC")
+            .field("core_0_sp_pc", &self.core_0_sp_pc())
+            .finish()
+    }
+}
+#[doc = "core0 sp pc status register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_sp_pc::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_0_SP_PC_SPEC;
+impl crate::RegisterSpec for CORE_0_SP_PC_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_0_sp_pc::R`](R) reader structure"]
+impl crate::Readable for CORE_0_SP_PC_SPEC {}
+#[doc = "`reset()` method sets CORE_0_SP_PC to value 0"]
+impl crate::Resettable for CORE_0_SP_PC_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/core_0_sp_unstable.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `CORE_0_SP_UNSTABLE` reader"]
+pub type R = crate::R<CORE_0_SP_UNSTABLE_SPEC>;
+#[doc = "Register `CORE_0_SP_UNSTABLE` writer"]
+pub type W = crate::W<CORE_0_SP_UNSTABLE_SPEC>;
+#[doc = "Field `CORE_0_SP_UNSTABLE` reader - unstable period when window change,during this period no check stackpointer"]
+pub type CORE_0_SP_UNSTABLE_R = crate::FieldReader;
+#[doc = "Field `CORE_0_SP_UNSTABLE` writer - unstable period when window change,during this period no check stackpointer"]
+pub type CORE_0_SP_UNSTABLE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+impl R {
+    #[doc = "Bits 0:7 - unstable period when window change,during this period no check stackpointer"]
+    #[inline(always)]
+    pub fn core_0_sp_unstable(&self) -> CORE_0_SP_UNSTABLE_R {
+        CORE_0_SP_UNSTABLE_R::new((self.bits & 0xff) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_0_SP_UNSTABLE")
+            .field("core_0_sp_unstable", &self.core_0_sp_unstable())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - unstable period when window change,during this period no check stackpointer"]
+    #[inline(always)]
+    pub fn core_0_sp_unstable(&mut self) -> CORE_0_SP_UNSTABLE_W<CORE_0_SP_UNSTABLE_SPEC> {
+        CORE_0_SP_UNSTABLE_W::new(self, 0)
+    }
+}
+#[doc = "core0 sp unstable configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_sp_unstable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_sp_unstable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_0_SP_UNSTABLE_SPEC;
+impl crate::RegisterSpec for CORE_0_SP_UNSTABLE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_0_sp_unstable::R`](R) reader structure"]
+impl crate::Readable for CORE_0_SP_UNSTABLE_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`core_0_sp_unstable::W`](W) writer structure"]
+impl crate::Writable for CORE_0_SP_UNSTABLE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CORE_0_SP_UNSTABLE to value 0x0b"]
+impl crate::Resettable for CORE_0_SP_UNSTABLE_SPEC {
+    const RESET_VALUE: u32 = 0x0b;
+}

vendor/esp32s3/src/assist_debug/core_1_area_dram0_0_max.rs

@@ -0,0 +1,49 @@
+#[doc = "Register `CORE_1_AREA_DRAM0_0_MAX` reader"]
+pub type R = crate::R<CORE_1_AREA_DRAM0_0_MAX_SPEC>;
+#[doc = "Register `CORE_1_AREA_DRAM0_0_MAX` writer"]
+pub type W = crate::W<CORE_1_AREA_DRAM0_0_MAX_SPEC>;
+#[doc = "Field `CORE_1_AREA_DRAM0_0_MAX` reader - Core1 dram0 region0 end addr"]
+pub type CORE_1_AREA_DRAM0_0_MAX_R = crate::FieldReader<u32>;
+#[doc = "Field `CORE_1_AREA_DRAM0_0_MAX` writer - Core1 dram0 region0 end addr"]
+pub type CORE_1_AREA_DRAM0_0_MAX_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - Core1 dram0 region0 end addr"]
+    #[inline(always)]
+    pub fn core_1_area_dram0_0_max(&self) -> CORE_1_AREA_DRAM0_0_MAX_R {
+        CORE_1_AREA_DRAM0_0_MAX_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_1_AREA_DRAM0_0_MAX")
+            .field("core_1_area_dram0_0_max", &self.core_1_area_dram0_0_max())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Core1 dram0 region0 end addr"]
+    #[inline(always)]
+    pub fn core_1_area_dram0_0_max(
+        &mut self,
+    ) -> CORE_1_AREA_DRAM0_0_MAX_W<CORE_1_AREA_DRAM0_0_MAX_SPEC> {
+        CORE_1_AREA_DRAM0_0_MAX_W::new(self, 0)
+    }
+}
+#[doc = "Core1 dram0 region0 addr configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_area_dram0_0_max::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_1_area_dram0_0_max::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_1_AREA_DRAM0_0_MAX_SPEC;
+impl crate::RegisterSpec for CORE_1_AREA_DRAM0_0_MAX_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_1_area_dram0_0_max::R`](R) reader structure"]
+impl crate::Readable for CORE_1_AREA_DRAM0_0_MAX_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`core_1_area_dram0_0_max::W`](W) writer structure"]
+impl crate::Writable for CORE_1_AREA_DRAM0_0_MAX_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CORE_1_AREA_DRAM0_0_MAX to value 0"]
+impl crate::Resettable for CORE_1_AREA_DRAM0_0_MAX_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/core_1_area_dram0_0_min.rs

@@ -0,0 +1,49 @@
+#[doc = "Register `CORE_1_AREA_DRAM0_0_MIN` reader"]
+pub type R = crate::R<CORE_1_AREA_DRAM0_0_MIN_SPEC>;
+#[doc = "Register `CORE_1_AREA_DRAM0_0_MIN` writer"]
+pub type W = crate::W<CORE_1_AREA_DRAM0_0_MIN_SPEC>;
+#[doc = "Field `CORE_1_AREA_DRAM0_0_MIN` reader - Core1 dram0 region0 start addr"]
+pub type CORE_1_AREA_DRAM0_0_MIN_R = crate::FieldReader<u32>;
+#[doc = "Field `CORE_1_AREA_DRAM0_0_MIN` writer - Core1 dram0 region0 start addr"]
+pub type CORE_1_AREA_DRAM0_0_MIN_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - Core1 dram0 region0 start addr"]
+    #[inline(always)]
+    pub fn core_1_area_dram0_0_min(&self) -> CORE_1_AREA_DRAM0_0_MIN_R {
+        CORE_1_AREA_DRAM0_0_MIN_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_1_AREA_DRAM0_0_MIN")
+            .field("core_1_area_dram0_0_min", &self.core_1_area_dram0_0_min())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Core1 dram0 region0 start addr"]
+    #[inline(always)]
+    pub fn core_1_area_dram0_0_min(
+        &mut self,
+    ) -> CORE_1_AREA_DRAM0_0_MIN_W<CORE_1_AREA_DRAM0_0_MIN_SPEC> {
+        CORE_1_AREA_DRAM0_0_MIN_W::new(self, 0)
+    }
+}
+#[doc = "Core1 dram0 region0 addr configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_area_dram0_0_min::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_1_area_dram0_0_min::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_1_AREA_DRAM0_0_MIN_SPEC;
+impl crate::RegisterSpec for CORE_1_AREA_DRAM0_0_MIN_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_1_area_dram0_0_min::R`](R) reader structure"]
+impl crate::Readable for CORE_1_AREA_DRAM0_0_MIN_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`core_1_area_dram0_0_min::W`](W) writer structure"]
+impl crate::Writable for CORE_1_AREA_DRAM0_0_MIN_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CORE_1_AREA_DRAM0_0_MIN to value 0xffff_ffff"]
+impl crate::Resettable for CORE_1_AREA_DRAM0_0_MIN_SPEC {
+    const RESET_VALUE: u32 = 0xffff_ffff;
+}

vendor/esp32s3/src/assist_debug/core_1_area_dram0_1_max.rs

@@ -0,0 +1,49 @@
+#[doc = "Register `CORE_1_AREA_DRAM0_1_MAX` reader"]
+pub type R = crate::R<CORE_1_AREA_DRAM0_1_MAX_SPEC>;
+#[doc = "Register `CORE_1_AREA_DRAM0_1_MAX` writer"]
+pub type W = crate::W<CORE_1_AREA_DRAM0_1_MAX_SPEC>;
+#[doc = "Field `CORE_1_AREA_DRAM0_1_MAX` reader - Core1 dram0 region1 end addr"]
+pub type CORE_1_AREA_DRAM0_1_MAX_R = crate::FieldReader<u32>;
+#[doc = "Field `CORE_1_AREA_DRAM0_1_MAX` writer - Core1 dram0 region1 end addr"]
+pub type CORE_1_AREA_DRAM0_1_MAX_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - Core1 dram0 region1 end addr"]
+    #[inline(always)]
+    pub fn core_1_area_dram0_1_max(&self) -> CORE_1_AREA_DRAM0_1_MAX_R {
+        CORE_1_AREA_DRAM0_1_MAX_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_1_AREA_DRAM0_1_MAX")
+            .field("core_1_area_dram0_1_max", &self.core_1_area_dram0_1_max())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Core1 dram0 region1 end addr"]
+    #[inline(always)]
+    pub fn core_1_area_dram0_1_max(
+        &mut self,
+    ) -> CORE_1_AREA_DRAM0_1_MAX_W<CORE_1_AREA_DRAM0_1_MAX_SPEC> {
+        CORE_1_AREA_DRAM0_1_MAX_W::new(self, 0)
+    }
+}
+#[doc = "Core1 dram0 region1 addr configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_area_dram0_1_max::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_1_area_dram0_1_max::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_1_AREA_DRAM0_1_MAX_SPEC;
+impl crate::RegisterSpec for CORE_1_AREA_DRAM0_1_MAX_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_1_area_dram0_1_max::R`](R) reader structure"]
+impl crate::Readable for CORE_1_AREA_DRAM0_1_MAX_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`core_1_area_dram0_1_max::W`](W) writer structure"]
+impl crate::Writable for CORE_1_AREA_DRAM0_1_MAX_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CORE_1_AREA_DRAM0_1_MAX to value 0"]
+impl crate::Resettable for CORE_1_AREA_DRAM0_1_MAX_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/core_1_area_dram0_1_min.rs

@@ -0,0 +1,49 @@
+#[doc = "Register `CORE_1_AREA_DRAM0_1_MIN` reader"]
+pub type R = crate::R<CORE_1_AREA_DRAM0_1_MIN_SPEC>;
+#[doc = "Register `CORE_1_AREA_DRAM0_1_MIN` writer"]
+pub type W = crate::W<CORE_1_AREA_DRAM0_1_MIN_SPEC>;
+#[doc = "Field `CORE_1_AREA_DRAM0_1_MIN` reader - Core1 dram0 region1 start addr"]
+pub type CORE_1_AREA_DRAM0_1_MIN_R = crate::FieldReader<u32>;
+#[doc = "Field `CORE_1_AREA_DRAM0_1_MIN` writer - Core1 dram0 region1 start addr"]
+pub type CORE_1_AREA_DRAM0_1_MIN_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - Core1 dram0 region1 start addr"]
+    #[inline(always)]
+    pub fn core_1_area_dram0_1_min(&self) -> CORE_1_AREA_DRAM0_1_MIN_R {
+        CORE_1_AREA_DRAM0_1_MIN_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_1_AREA_DRAM0_1_MIN")
+            .field("core_1_area_dram0_1_min", &self.core_1_area_dram0_1_min())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Core1 dram0 region1 start addr"]
+    #[inline(always)]
+    pub fn core_1_area_dram0_1_min(
+        &mut self,
+    ) -> CORE_1_AREA_DRAM0_1_MIN_W<CORE_1_AREA_DRAM0_1_MIN_SPEC> {
+        CORE_1_AREA_DRAM0_1_MIN_W::new(self, 0)
+    }
+}
+#[doc = "Core1 dram0 region1 addr configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_area_dram0_1_min::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_1_area_dram0_1_min::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_1_AREA_DRAM0_1_MIN_SPEC;
+impl crate::RegisterSpec for CORE_1_AREA_DRAM0_1_MIN_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_1_area_dram0_1_min::R`](R) reader structure"]
+impl crate::Readable for CORE_1_AREA_DRAM0_1_MIN_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`core_1_area_dram0_1_min::W`](W) writer structure"]
+impl crate::Writable for CORE_1_AREA_DRAM0_1_MIN_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CORE_1_AREA_DRAM0_1_MIN to value 0xffff_ffff"]
+impl crate::Resettable for CORE_1_AREA_DRAM0_1_MIN_SPEC {
+    const RESET_VALUE: u32 = 0xffff_ffff;
+}

vendor/esp32s3/src/assist_debug/core_1_area_pc.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `CORE_1_AREA_PC` reader"]
+pub type R = crate::R<CORE_1_AREA_PC_SPEC>;
+#[doc = "Field `CORE_1_AREA_PC` reader - the stackpointer when first touch region monitor interrupt"]
+pub type CORE_1_AREA_PC_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - the stackpointer when first touch region monitor interrupt"]
+    #[inline(always)]
+    pub fn core_1_area_pc(&self) -> CORE_1_AREA_PC_R {
+        CORE_1_AREA_PC_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_1_AREA_PC")
+            .field("core_1_area_pc", &self.core_1_area_pc())
+            .finish()
+    }
+}
+#[doc = "Core1 area sp status register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_area_pc::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_1_AREA_PC_SPEC;
+impl crate::RegisterSpec for CORE_1_AREA_PC_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_1_area_pc::R`](R) reader structure"]
+impl crate::Readable for CORE_1_AREA_PC_SPEC {}
+#[doc = "`reset()` method sets CORE_1_AREA_PC to value 0"]
+impl crate::Resettable for CORE_1_AREA_PC_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/core_1_area_pif_0_max.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `CORE_1_AREA_PIF_0_MAX` reader"]
+pub type R = crate::R<CORE_1_AREA_PIF_0_MAX_SPEC>;
+#[doc = "Register `CORE_1_AREA_PIF_0_MAX` writer"]
+pub type W = crate::W<CORE_1_AREA_PIF_0_MAX_SPEC>;
+#[doc = "Field `CORE_1_AREA_PIF_0_MAX` reader - Core1 PIF region0 end addr"]
+pub type CORE_1_AREA_PIF_0_MAX_R = crate::FieldReader<u32>;
+#[doc = "Field `CORE_1_AREA_PIF_0_MAX` writer - Core1 PIF region0 end addr"]
+pub type CORE_1_AREA_PIF_0_MAX_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - Core1 PIF region0 end addr"]
+    #[inline(always)]
+    pub fn core_1_area_pif_0_max(&self) -> CORE_1_AREA_PIF_0_MAX_R {
+        CORE_1_AREA_PIF_0_MAX_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_1_AREA_PIF_0_MAX")
+            .field("core_1_area_pif_0_max", &self.core_1_area_pif_0_max())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Core1 PIF region0 end addr"]
+    #[inline(always)]
+    pub fn core_1_area_pif_0_max(&mut self) -> CORE_1_AREA_PIF_0_MAX_W<CORE_1_AREA_PIF_0_MAX_SPEC> {
+        CORE_1_AREA_PIF_0_MAX_W::new(self, 0)
+    }
+}
+#[doc = "Core1 PIF region0 addr configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_area_pif_0_max::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_1_area_pif_0_max::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_1_AREA_PIF_0_MAX_SPEC;
+impl crate::RegisterSpec for CORE_1_AREA_PIF_0_MAX_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_1_area_pif_0_max::R`](R) reader structure"]
+impl crate::Readable for CORE_1_AREA_PIF_0_MAX_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`core_1_area_pif_0_max::W`](W) writer structure"]
+impl crate::Writable for CORE_1_AREA_PIF_0_MAX_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CORE_1_AREA_PIF_0_MAX to value 0"]
+impl crate::Resettable for CORE_1_AREA_PIF_0_MAX_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/core_1_area_pif_0_min.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `CORE_1_AREA_PIF_0_MIN` reader"]
+pub type R = crate::R<CORE_1_AREA_PIF_0_MIN_SPEC>;
+#[doc = "Register `CORE_1_AREA_PIF_0_MIN` writer"]
+pub type W = crate::W<CORE_1_AREA_PIF_0_MIN_SPEC>;
+#[doc = "Field `CORE_1_AREA_PIF_0_MIN` reader - Core1 PIF region0 start addr"]
+pub type CORE_1_AREA_PIF_0_MIN_R = crate::FieldReader<u32>;
+#[doc = "Field `CORE_1_AREA_PIF_0_MIN` writer - Core1 PIF region0 start addr"]
+pub type CORE_1_AREA_PIF_0_MIN_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - Core1 PIF region0 start addr"]
+    #[inline(always)]
+    pub fn core_1_area_pif_0_min(&self) -> CORE_1_AREA_PIF_0_MIN_R {
+        CORE_1_AREA_PIF_0_MIN_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_1_AREA_PIF_0_MIN")
+            .field("core_1_area_pif_0_min", &self.core_1_area_pif_0_min())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Core1 PIF region0 start addr"]
+    #[inline(always)]
+    pub fn core_1_area_pif_0_min(&mut self) -> CORE_1_AREA_PIF_0_MIN_W<CORE_1_AREA_PIF_0_MIN_SPEC> {
+        CORE_1_AREA_PIF_0_MIN_W::new(self, 0)
+    }
+}
+#[doc = "Core1 PIF region0 addr configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_area_pif_0_min::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_1_area_pif_0_min::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_1_AREA_PIF_0_MIN_SPEC;
+impl crate::RegisterSpec for CORE_1_AREA_PIF_0_MIN_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_1_area_pif_0_min::R`](R) reader structure"]
+impl crate::Readable for CORE_1_AREA_PIF_0_MIN_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`core_1_area_pif_0_min::W`](W) writer structure"]
+impl crate::Writable for CORE_1_AREA_PIF_0_MIN_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CORE_1_AREA_PIF_0_MIN to value 0xffff_ffff"]
+impl crate::Resettable for CORE_1_AREA_PIF_0_MIN_SPEC {
+    const RESET_VALUE: u32 = 0xffff_ffff;
+}

vendor/esp32s3/src/assist_debug/core_1_area_pif_1_max.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `CORE_1_AREA_PIF_1_MAX` reader"]
+pub type R = crate::R<CORE_1_AREA_PIF_1_MAX_SPEC>;
+#[doc = "Register `CORE_1_AREA_PIF_1_MAX` writer"]
+pub type W = crate::W<CORE_1_AREA_PIF_1_MAX_SPEC>;
+#[doc = "Field `CORE_1_AREA_PIF_1_MAX` reader - Core1 PIF region1 end addr"]
+pub type CORE_1_AREA_PIF_1_MAX_R = crate::FieldReader<u32>;
+#[doc = "Field `CORE_1_AREA_PIF_1_MAX` writer - Core1 PIF region1 end addr"]
+pub type CORE_1_AREA_PIF_1_MAX_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - Core1 PIF region1 end addr"]
+    #[inline(always)]
+    pub fn core_1_area_pif_1_max(&self) -> CORE_1_AREA_PIF_1_MAX_R {
+        CORE_1_AREA_PIF_1_MAX_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_1_AREA_PIF_1_MAX")
+            .field("core_1_area_pif_1_max", &self.core_1_area_pif_1_max())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Core1 PIF region1 end addr"]
+    #[inline(always)]
+    pub fn core_1_area_pif_1_max(&mut self) -> CORE_1_AREA_PIF_1_MAX_W<CORE_1_AREA_PIF_1_MAX_SPEC> {
+        CORE_1_AREA_PIF_1_MAX_W::new(self, 0)
+    }
+}
+#[doc = "Core1 PIF region1 addr configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_area_pif_1_max::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_1_area_pif_1_max::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_1_AREA_PIF_1_MAX_SPEC;
+impl crate::RegisterSpec for CORE_1_AREA_PIF_1_MAX_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_1_area_pif_1_max::R`](R) reader structure"]
+impl crate::Readable for CORE_1_AREA_PIF_1_MAX_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`core_1_area_pif_1_max::W`](W) writer structure"]
+impl crate::Writable for CORE_1_AREA_PIF_1_MAX_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CORE_1_AREA_PIF_1_MAX to value 0"]
+impl crate::Resettable for CORE_1_AREA_PIF_1_MAX_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/core_1_area_pif_1_min.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `CORE_1_AREA_PIF_1_MIN` reader"]
+pub type R = crate::R<CORE_1_AREA_PIF_1_MIN_SPEC>;
+#[doc = "Register `CORE_1_AREA_PIF_1_MIN` writer"]
+pub type W = crate::W<CORE_1_AREA_PIF_1_MIN_SPEC>;
+#[doc = "Field `CORE_1_AREA_PIF_1_MIN` reader - Core1 PIF region1 start addr"]
+pub type CORE_1_AREA_PIF_1_MIN_R = crate::FieldReader<u32>;
+#[doc = "Field `CORE_1_AREA_PIF_1_MIN` writer - Core1 PIF region1 start addr"]
+pub type CORE_1_AREA_PIF_1_MIN_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - Core1 PIF region1 start addr"]
+    #[inline(always)]
+    pub fn core_1_area_pif_1_min(&self) -> CORE_1_AREA_PIF_1_MIN_R {
+        CORE_1_AREA_PIF_1_MIN_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_1_AREA_PIF_1_MIN")
+            .field("core_1_area_pif_1_min", &self.core_1_area_pif_1_min())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Core1 PIF region1 start addr"]
+    #[inline(always)]
+    pub fn core_1_area_pif_1_min(&mut self) -> CORE_1_AREA_PIF_1_MIN_W<CORE_1_AREA_PIF_1_MIN_SPEC> {
+        CORE_1_AREA_PIF_1_MIN_W::new(self, 0)
+    }
+}
+#[doc = "Core1 PIF region1 addr configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_area_pif_1_min::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_1_area_pif_1_min::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_1_AREA_PIF_1_MIN_SPEC;
+impl crate::RegisterSpec for CORE_1_AREA_PIF_1_MIN_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_1_area_pif_1_min::R`](R) reader structure"]
+impl crate::Readable for CORE_1_AREA_PIF_1_MIN_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`core_1_area_pif_1_min::W`](W) writer structure"]
+impl crate::Writable for CORE_1_AREA_PIF_1_MIN_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CORE_1_AREA_PIF_1_MIN to value 0xffff_ffff"]
+impl crate::Resettable for CORE_1_AREA_PIF_1_MIN_SPEC {
+    const RESET_VALUE: u32 = 0xffff_ffff;
+}

vendor/esp32s3/src/assist_debug/core_1_area_sp.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `CORE_1_AREA_SP` reader"]
+pub type R = crate::R<CORE_1_AREA_SP_SPEC>;
+#[doc = "Field `CORE_1_AREA_SP` reader - the PC when first touch region monitor interrupt"]
+pub type CORE_1_AREA_SP_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - the PC when first touch region monitor interrupt"]
+    #[inline(always)]
+    pub fn core_1_area_sp(&self) -> CORE_1_AREA_SP_R {
+        CORE_1_AREA_SP_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_1_AREA_SP")
+            .field("core_1_area_sp", &self.core_1_area_sp())
+            .finish()
+    }
+}
+#[doc = "Core1 area pc status register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_area_sp::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_1_AREA_SP_SPEC;
+impl crate::RegisterSpec for CORE_1_AREA_SP_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_1_area_sp::R`](R) reader structure"]
+impl crate::Readable for CORE_1_AREA_SP_SPEC {}
+#[doc = "`reset()` method sets CORE_1_AREA_SP to value 0"]
+impl crate::Resettable for CORE_1_AREA_SP_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/core_1_dram0_exception_monitor_0.rs

@@ -0,0 +1,44 @@
+#[doc = "Register `CORE_1_DRAM0_EXCEPTION_MONITOR_0` reader"]
+pub type R = crate::R<CORE_1_DRAM0_EXCEPTION_MONITOR_0_SPEC>;
+#[doc = "Field `CORE_1_DRAM0_RECORDING_ADDR_0` reader - The first dram0's addr\\[25:4\\] status when trigger DRAM busy interrupt"]
+pub type CORE_1_DRAM0_RECORDING_ADDR_0_R = crate::FieldReader<u32>;
+#[doc = "Field `CORE_1_DRAM0_RECORDING_WR_0` reader - The first dram0's wr status when trigger DRAM busy interrupt"]
+pub type CORE_1_DRAM0_RECORDING_WR_0_R = crate::BitReader;
+impl R {
+    #[doc = "Bits 0:21 - The first dram0's addr\\[25:4\\] status when trigger DRAM busy interrupt"]
+    #[inline(always)]
+    pub fn core_1_dram0_recording_addr_0(&self) -> CORE_1_DRAM0_RECORDING_ADDR_0_R {
+        CORE_1_DRAM0_RECORDING_ADDR_0_R::new(self.bits & 0x003f_ffff)
+    }
+    #[doc = "Bit 22 - The first dram0's wr status when trigger DRAM busy interrupt"]
+    #[inline(always)]
+    pub fn core_1_dram0_recording_wr_0(&self) -> CORE_1_DRAM0_RECORDING_WR_0_R {
+        CORE_1_DRAM0_RECORDING_WR_0_R::new(((self.bits >> 22) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_1_DRAM0_EXCEPTION_MONITOR_0")
+            .field(
+                "core_1_dram0_recording_addr_0",
+                &self.core_1_dram0_recording_addr_0(),
+            )
+            .field(
+                "core_1_dram0_recording_wr_0",
+                &self.core_1_dram0_recording_wr_0(),
+            )
+            .finish()
+    }
+}
+#[doc = "Core1 bus busy status regsiter\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_dram0_exception_monitor_0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_1_DRAM0_EXCEPTION_MONITOR_0_SPEC;
+impl crate::RegisterSpec for CORE_1_DRAM0_EXCEPTION_MONITOR_0_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_1_dram0_exception_monitor_0::R`](R) reader structure"]
+impl crate::Readable for CORE_1_DRAM0_EXCEPTION_MONITOR_0_SPEC {}
+#[doc = "`reset()` method sets CORE_1_DRAM0_EXCEPTION_MONITOR_0 to value 0"]
+impl crate::Resettable for CORE_1_DRAM0_EXCEPTION_MONITOR_0_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/core_1_dram0_exception_monitor_1.rs

@@ -0,0 +1,33 @@
+#[doc = "Register `CORE_1_DRAM0_EXCEPTION_MONITOR_1` reader"]
+pub type R = crate::R<CORE_1_DRAM0_EXCEPTION_MONITOR_1_SPEC>;
+#[doc = "Field `CORE_1_DRAM0_RECORDING_BYTEEN_0` reader - The first dram0's byteen status when trigger DRAM busy interrupt"]
+pub type CORE_1_DRAM0_RECORDING_BYTEEN_0_R = crate::FieldReader<u16>;
+impl R {
+    #[doc = "Bits 0:15 - The first dram0's byteen status when trigger DRAM busy interrupt"]
+    #[inline(always)]
+    pub fn core_1_dram0_recording_byteen_0(&self) -> CORE_1_DRAM0_RECORDING_BYTEEN_0_R {
+        CORE_1_DRAM0_RECORDING_BYTEEN_0_R::new((self.bits & 0xffff) as u16)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_1_DRAM0_EXCEPTION_MONITOR_1")
+            .field(
+                "core_1_dram0_recording_byteen_0",
+                &self.core_1_dram0_recording_byteen_0(),
+            )
+            .finish()
+    }
+}
+#[doc = "Core1 bus busy status regsiter\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_dram0_exception_monitor_1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_1_DRAM0_EXCEPTION_MONITOR_1_SPEC;
+impl crate::RegisterSpec for CORE_1_DRAM0_EXCEPTION_MONITOR_1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_1_dram0_exception_monitor_1::R`](R) reader structure"]
+impl crate::Readable for CORE_1_DRAM0_EXCEPTION_MONITOR_1_SPEC {}
+#[doc = "`reset()` method sets CORE_1_DRAM0_EXCEPTION_MONITOR_1 to value 0"]
+impl crate::Resettable for CORE_1_DRAM0_EXCEPTION_MONITOR_1_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/core_1_dram0_exception_monitor_2.rs

@@ -0,0 +1,33 @@
+#[doc = "Register `CORE_1_DRAM0_EXCEPTION_MONITOR_2` reader"]
+pub type R = crate::R<CORE_1_DRAM0_EXCEPTION_MONITOR_2_SPEC>;
+#[doc = "Field `CORE_1_DRAM0_RECORDING_PC_0` reader - The first dram0's PC status when trigger DRAM busy interrupt"]
+pub type CORE_1_DRAM0_RECORDING_PC_0_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - The first dram0's PC status when trigger DRAM busy interrupt"]
+    #[inline(always)]
+    pub fn core_1_dram0_recording_pc_0(&self) -> CORE_1_DRAM0_RECORDING_PC_0_R {
+        CORE_1_DRAM0_RECORDING_PC_0_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_1_DRAM0_EXCEPTION_MONITOR_2")
+            .field(
+                "core_1_dram0_recording_pc_0",
+                &self.core_1_dram0_recording_pc_0(),
+            )
+            .finish()
+    }
+}
+#[doc = "Core1 bus busy status regsiter\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_dram0_exception_monitor_2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_1_DRAM0_EXCEPTION_MONITOR_2_SPEC;
+impl crate::RegisterSpec for CORE_1_DRAM0_EXCEPTION_MONITOR_2_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_1_dram0_exception_monitor_2::R`](R) reader structure"]
+impl crate::Readable for CORE_1_DRAM0_EXCEPTION_MONITOR_2_SPEC {}
+#[doc = "`reset()` method sets CORE_1_DRAM0_EXCEPTION_MONITOR_2 to value 0xffff_ffff"]
+impl crate::Resettable for CORE_1_DRAM0_EXCEPTION_MONITOR_2_SPEC {
+    const RESET_VALUE: u32 = 0xffff_ffff;
+}

vendor/esp32s3/src/assist_debug/core_1_dram0_exception_monitor_3.rs

@@ -0,0 +1,44 @@
+#[doc = "Register `CORE_1_DRAM0_EXCEPTION_MONITOR_3` reader"]
+pub type R = crate::R<CORE_1_DRAM0_EXCEPTION_MONITOR_3_SPEC>;
+#[doc = "Field `CORE_1_DRAM0_RECORDING_ADDR_1` reader - The second dram0's addr\\[25:4\\] status when trigger DRAM busy interrupt"]
+pub type CORE_1_DRAM0_RECORDING_ADDR_1_R = crate::FieldReader<u32>;
+#[doc = "Field `CORE_1_DRAM0_RECORDING_WR_1` reader - The second dram0's wr status when trigger DRAM busy interrupt"]
+pub type CORE_1_DRAM0_RECORDING_WR_1_R = crate::BitReader;
+impl R {
+    #[doc = "Bits 0:21 - The second dram0's addr\\[25:4\\] status when trigger DRAM busy interrupt"]
+    #[inline(always)]
+    pub fn core_1_dram0_recording_addr_1(&self) -> CORE_1_DRAM0_RECORDING_ADDR_1_R {
+        CORE_1_DRAM0_RECORDING_ADDR_1_R::new(self.bits & 0x003f_ffff)
+    }
+    #[doc = "Bit 22 - The second dram0's wr status when trigger DRAM busy interrupt"]
+    #[inline(always)]
+    pub fn core_1_dram0_recording_wr_1(&self) -> CORE_1_DRAM0_RECORDING_WR_1_R {
+        CORE_1_DRAM0_RECORDING_WR_1_R::new(((self.bits >> 22) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_1_DRAM0_EXCEPTION_MONITOR_3")
+            .field(
+                "core_1_dram0_recording_addr_1",
+                &self.core_1_dram0_recording_addr_1(),
+            )
+            .field(
+                "core_1_dram0_recording_wr_1",
+                &self.core_1_dram0_recording_wr_1(),
+            )
+            .finish()
+    }
+}
+#[doc = "Core1 bus busy status regsiter\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_dram0_exception_monitor_3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_1_DRAM0_EXCEPTION_MONITOR_3_SPEC;
+impl crate::RegisterSpec for CORE_1_DRAM0_EXCEPTION_MONITOR_3_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_1_dram0_exception_monitor_3::R`](R) reader structure"]
+impl crate::Readable for CORE_1_DRAM0_EXCEPTION_MONITOR_3_SPEC {}
+#[doc = "`reset()` method sets CORE_1_DRAM0_EXCEPTION_MONITOR_3 to value 0"]
+impl crate::Resettable for CORE_1_DRAM0_EXCEPTION_MONITOR_3_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/core_1_dram0_exception_monitor_4.rs

@@ -0,0 +1,33 @@
+#[doc = "Register `CORE_1_DRAM0_EXCEPTION_MONITOR_4` reader"]
+pub type R = crate::R<CORE_1_DRAM0_EXCEPTION_MONITOR_4_SPEC>;
+#[doc = "Field `CORE_1_DRAM0_RECORDING_BYTEEN_1` reader - The second dram0's byteen status when trigger DRAM busy interrupt"]
+pub type CORE_1_DRAM0_RECORDING_BYTEEN_1_R = crate::FieldReader<u16>;
+impl R {
+    #[doc = "Bits 0:15 - The second dram0's byteen status when trigger DRAM busy interrupt"]
+    #[inline(always)]
+    pub fn core_1_dram0_recording_byteen_1(&self) -> CORE_1_DRAM0_RECORDING_BYTEEN_1_R {
+        CORE_1_DRAM0_RECORDING_BYTEEN_1_R::new((self.bits & 0xffff) as u16)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_1_DRAM0_EXCEPTION_MONITOR_4")
+            .field(
+                "core_1_dram0_recording_byteen_1",
+                &self.core_1_dram0_recording_byteen_1(),
+            )
+            .finish()
+    }
+}
+#[doc = "Core1 bus busy status regsiter\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_dram0_exception_monitor_4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_1_DRAM0_EXCEPTION_MONITOR_4_SPEC;
+impl crate::RegisterSpec for CORE_1_DRAM0_EXCEPTION_MONITOR_4_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_1_dram0_exception_monitor_4::R`](R) reader structure"]
+impl crate::Readable for CORE_1_DRAM0_EXCEPTION_MONITOR_4_SPEC {}
+#[doc = "`reset()` method sets CORE_1_DRAM0_EXCEPTION_MONITOR_4 to value 0"]
+impl crate::Resettable for CORE_1_DRAM0_EXCEPTION_MONITOR_4_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/core_1_dram0_exception_monitor_5.rs

@@ -0,0 +1,33 @@
+#[doc = "Register `CORE_1_DRAM0_EXCEPTION_MONITOR_5` reader"]
+pub type R = crate::R<CORE_1_DRAM0_EXCEPTION_MONITOR_5_SPEC>;
+#[doc = "Field `CORE_1_DRAM0_RECORDING_PC_1` reader - The second dram0's PC status when trigger DRAM busy interrupt"]
+pub type CORE_1_DRAM0_RECORDING_PC_1_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - The second dram0's PC status when trigger DRAM busy interrupt"]
+    #[inline(always)]
+    pub fn core_1_dram0_recording_pc_1(&self) -> CORE_1_DRAM0_RECORDING_PC_1_R {
+        CORE_1_DRAM0_RECORDING_PC_1_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_1_DRAM0_EXCEPTION_MONITOR_5")
+            .field(
+                "core_1_dram0_recording_pc_1",
+                &self.core_1_dram0_recording_pc_1(),
+            )
+            .finish()
+    }
+}
+#[doc = "Core1 bus busy status regsiter\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_dram0_exception_monitor_5::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_1_DRAM0_EXCEPTION_MONITOR_5_SPEC;
+impl crate::RegisterSpec for CORE_1_DRAM0_EXCEPTION_MONITOR_5_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_1_dram0_exception_monitor_5::R`](R) reader structure"]
+impl crate::Readable for CORE_1_DRAM0_EXCEPTION_MONITOR_5_SPEC {}
+#[doc = "`reset()` method sets CORE_1_DRAM0_EXCEPTION_MONITOR_5 to value 0xffff_ffff"]
+impl crate::Resettable for CORE_1_DRAM0_EXCEPTION_MONITOR_5_SPEC {
+    const RESET_VALUE: u32 = 0xffff_ffff;
+}

vendor/esp32s3/src/assist_debug/core_1_intr_clr.rs

@@ -0,0 +1,242 @@
+#[doc = "Register `CORE_1_INTR_CLR` reader"]
+pub type R = crate::R<CORE_1_INTR_CLR_SPEC>;
+#[doc = "Register `CORE_1_INTR_CLR` writer"]
+pub type W = crate::W<CORE_1_INTR_CLR_SPEC>;
+#[doc = "Field `CORE_1_AREA_DRAM0_0_RD_CLR` reader - Core1 dram0 area0 read monitor interrupt clr"]
+pub type CORE_1_AREA_DRAM0_0_RD_CLR_R = crate::BitReader;
+#[doc = "Field `CORE_1_AREA_DRAM0_0_RD_CLR` writer - Core1 dram0 area0 read monitor interrupt clr"]
+pub type CORE_1_AREA_DRAM0_0_RD_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_1_AREA_DRAM0_0_WR_CLR` reader - Core1 dram0 area0 write monitor interrupt clr"]
+pub type CORE_1_AREA_DRAM0_0_WR_CLR_R = crate::BitReader;
+#[doc = "Field `CORE_1_AREA_DRAM0_0_WR_CLR` writer - Core1 dram0 area0 write monitor interrupt clr"]
+pub type CORE_1_AREA_DRAM0_0_WR_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_1_AREA_DRAM0_1_RD_CLR` reader - Core1 dram0 area1 read monitor interrupt clr"]
+pub type CORE_1_AREA_DRAM0_1_RD_CLR_R = crate::BitReader;
+#[doc = "Field `CORE_1_AREA_DRAM0_1_RD_CLR` writer - Core1 dram0 area1 read monitor interrupt clr"]
+pub type CORE_1_AREA_DRAM0_1_RD_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_1_AREA_DRAM0_1_WR_CLR` reader - Core1 dram0 area1 write monitor interrupt clr"]
+pub type CORE_1_AREA_DRAM0_1_WR_CLR_R = crate::BitReader;
+#[doc = "Field `CORE_1_AREA_DRAM0_1_WR_CLR` writer - Core1 dram0 area1 write monitor interrupt clr"]
+pub type CORE_1_AREA_DRAM0_1_WR_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_1_AREA_PIF_0_RD_CLR` reader - Core1 PIF area0 read monitor interrupt clr"]
+pub type CORE_1_AREA_PIF_0_RD_CLR_R = crate::BitReader;
+#[doc = "Field `CORE_1_AREA_PIF_0_RD_CLR` writer - Core1 PIF area0 read monitor interrupt clr"]
+pub type CORE_1_AREA_PIF_0_RD_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_1_AREA_PIF_0_WR_CLR` reader - Core1 PIF area0 write monitor interrupt clr"]
+pub type CORE_1_AREA_PIF_0_WR_CLR_R = crate::BitReader;
+#[doc = "Field `CORE_1_AREA_PIF_0_WR_CLR` writer - Core1 PIF area0 write monitor interrupt clr"]
+pub type CORE_1_AREA_PIF_0_WR_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_1_AREA_PIF_1_RD_CLR` reader - Core1 PIF area1 read monitor interrupt clr"]
+pub type CORE_1_AREA_PIF_1_RD_CLR_R = crate::BitReader;
+#[doc = "Field `CORE_1_AREA_PIF_1_RD_CLR` writer - Core1 PIF area1 read monitor interrupt clr"]
+pub type CORE_1_AREA_PIF_1_RD_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_1_AREA_PIF_1_WR_CLR` reader - Core1 PIF area1 write monitor interrupt clr"]
+pub type CORE_1_AREA_PIF_1_WR_CLR_R = crate::BitReader;
+#[doc = "Field `CORE_1_AREA_PIF_1_WR_CLR` writer - Core1 PIF area1 write monitor interrupt clr"]
+pub type CORE_1_AREA_PIF_1_WR_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_1_SP_SPILL_MIN_CLR` reader - Core1 stackpoint overflow monitor interrupt clr"]
+pub type CORE_1_SP_SPILL_MIN_CLR_R = crate::BitReader;
+#[doc = "Field `CORE_1_SP_SPILL_MIN_CLR` writer - Core1 stackpoint overflow monitor interrupt clr"]
+pub type CORE_1_SP_SPILL_MIN_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_1_SP_SPILL_MAX_CLR` reader - Core1 stackpoint underflow monitor interrupt clr"]
+pub type CORE_1_SP_SPILL_MAX_CLR_R = crate::BitReader;
+#[doc = "Field `CORE_1_SP_SPILL_MAX_CLR` writer - Core1 stackpoint underflow monitor interrupt clr"]
+pub type CORE_1_SP_SPILL_MAX_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_1_IRAM0_EXCEPTION_MONITOR_CLR` reader - IBUS busy monitor interrupt clr"]
+pub type CORE_1_IRAM0_EXCEPTION_MONITOR_CLR_R = crate::BitReader;
+#[doc = "Field `CORE_1_IRAM0_EXCEPTION_MONITOR_CLR` writer - IBUS busy monitor interrupt clr"]
+pub type CORE_1_IRAM0_EXCEPTION_MONITOR_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_1_DRAM0_EXCEPTION_MONITOR_CLR` reader - DBUS busy monitor interrupt clr"]
+pub type CORE_1_DRAM0_EXCEPTION_MONITOR_CLR_R = crate::BitReader;
+#[doc = "Field `CORE_1_DRAM0_EXCEPTION_MONITOR_CLR` writer - DBUS busy monitor interrupt clr"]
+pub type CORE_1_DRAM0_EXCEPTION_MONITOR_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Core1 dram0 area0 read monitor interrupt clr"]
+    #[inline(always)]
+    pub fn core_1_area_dram0_0_rd_clr(&self) -> CORE_1_AREA_DRAM0_0_RD_CLR_R {
+        CORE_1_AREA_DRAM0_0_RD_CLR_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Core1 dram0 area0 write monitor interrupt clr"]
+    #[inline(always)]
+    pub fn core_1_area_dram0_0_wr_clr(&self) -> CORE_1_AREA_DRAM0_0_WR_CLR_R {
+        CORE_1_AREA_DRAM0_0_WR_CLR_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Core1 dram0 area1 read monitor interrupt clr"]
+    #[inline(always)]
+    pub fn core_1_area_dram0_1_rd_clr(&self) -> CORE_1_AREA_DRAM0_1_RD_CLR_R {
+        CORE_1_AREA_DRAM0_1_RD_CLR_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Core1 dram0 area1 write monitor interrupt clr"]
+    #[inline(always)]
+    pub fn core_1_area_dram0_1_wr_clr(&self) -> CORE_1_AREA_DRAM0_1_WR_CLR_R {
+        CORE_1_AREA_DRAM0_1_WR_CLR_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Core1 PIF area0 read monitor interrupt clr"]
+    #[inline(always)]
+    pub fn core_1_area_pif_0_rd_clr(&self) -> CORE_1_AREA_PIF_0_RD_CLR_R {
+        CORE_1_AREA_PIF_0_RD_CLR_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - Core1 PIF area0 write monitor interrupt clr"]
+    #[inline(always)]
+    pub fn core_1_area_pif_0_wr_clr(&self) -> CORE_1_AREA_PIF_0_WR_CLR_R {
+        CORE_1_AREA_PIF_0_WR_CLR_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - Core1 PIF area1 read monitor interrupt clr"]
+    #[inline(always)]
+    pub fn core_1_area_pif_1_rd_clr(&self) -> CORE_1_AREA_PIF_1_RD_CLR_R {
+        CORE_1_AREA_PIF_1_RD_CLR_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - Core1 PIF area1 write monitor interrupt clr"]
+    #[inline(always)]
+    pub fn core_1_area_pif_1_wr_clr(&self) -> CORE_1_AREA_PIF_1_WR_CLR_R {
+        CORE_1_AREA_PIF_1_WR_CLR_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - Core1 stackpoint overflow monitor interrupt clr"]
+    #[inline(always)]
+    pub fn core_1_sp_spill_min_clr(&self) -> CORE_1_SP_SPILL_MIN_CLR_R {
+        CORE_1_SP_SPILL_MIN_CLR_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - Core1 stackpoint underflow monitor interrupt clr"]
+    #[inline(always)]
+    pub fn core_1_sp_spill_max_clr(&self) -> CORE_1_SP_SPILL_MAX_CLR_R {
+        CORE_1_SP_SPILL_MAX_CLR_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 10 - IBUS busy monitor interrupt clr"]
+    #[inline(always)]
+    pub fn core_1_iram0_exception_monitor_clr(&self) -> CORE_1_IRAM0_EXCEPTION_MONITOR_CLR_R {
+        CORE_1_IRAM0_EXCEPTION_MONITOR_CLR_R::new(((self.bits >> 10) & 1) != 0)
+    }
+    #[doc = "Bit 11 - DBUS busy monitor interrupt clr"]
+    #[inline(always)]
+    pub fn core_1_dram0_exception_monitor_clr(&self) -> CORE_1_DRAM0_EXCEPTION_MONITOR_CLR_R {
+        CORE_1_DRAM0_EXCEPTION_MONITOR_CLR_R::new(((self.bits >> 11) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_1_INTR_CLR")
+            .field(
+                "core_1_area_dram0_0_rd_clr",
+                &self.core_1_area_dram0_0_rd_clr(),
+            )
+            .field(
+                "core_1_area_dram0_0_wr_clr",
+                &self.core_1_area_dram0_0_wr_clr(),
+            )
+            .field(
+                "core_1_area_dram0_1_rd_clr",
+                &self.core_1_area_dram0_1_rd_clr(),
+            )
+            .field(
+                "core_1_area_dram0_1_wr_clr",
+                &self.core_1_area_dram0_1_wr_clr(),
+            )
+            .field("core_1_area_pif_0_rd_clr", &self.core_1_area_pif_0_rd_clr())
+            .field("core_1_area_pif_0_wr_clr", &self.core_1_area_pif_0_wr_clr())
+            .field("core_1_area_pif_1_rd_clr", &self.core_1_area_pif_1_rd_clr())
+            .field("core_1_area_pif_1_wr_clr", &self.core_1_area_pif_1_wr_clr())
+            .field("core_1_sp_spill_min_clr", &self.core_1_sp_spill_min_clr())
+            .field("core_1_sp_spill_max_clr", &self.core_1_sp_spill_max_clr())
+            .field(
+                "core_1_iram0_exception_monitor_clr",
+                &self.core_1_iram0_exception_monitor_clr(),
+            )
+            .field(
+                "core_1_dram0_exception_monitor_clr",
+                &self.core_1_dram0_exception_monitor_clr(),
+            )
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Core1 dram0 area0 read monitor interrupt clr"]
+    #[inline(always)]
+    pub fn core_1_area_dram0_0_rd_clr(
+        &mut self,
+    ) -> CORE_1_AREA_DRAM0_0_RD_CLR_W<CORE_1_INTR_CLR_SPEC> {
+        CORE_1_AREA_DRAM0_0_RD_CLR_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - Core1 dram0 area0 write monitor interrupt clr"]
+    #[inline(always)]
+    pub fn core_1_area_dram0_0_wr_clr(
+        &mut self,
+    ) -> CORE_1_AREA_DRAM0_0_WR_CLR_W<CORE_1_INTR_CLR_SPEC> {
+        CORE_1_AREA_DRAM0_0_WR_CLR_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - Core1 dram0 area1 read monitor interrupt clr"]
+    #[inline(always)]
+    pub fn core_1_area_dram0_1_rd_clr(
+        &mut self,
+    ) -> CORE_1_AREA_DRAM0_1_RD_CLR_W<CORE_1_INTR_CLR_SPEC> {
+        CORE_1_AREA_DRAM0_1_RD_CLR_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - Core1 dram0 area1 write monitor interrupt clr"]
+    #[inline(always)]
+    pub fn core_1_area_dram0_1_wr_clr(
+        &mut self,
+    ) -> CORE_1_AREA_DRAM0_1_WR_CLR_W<CORE_1_INTR_CLR_SPEC> {
+        CORE_1_AREA_DRAM0_1_WR_CLR_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - Core1 PIF area0 read monitor interrupt clr"]
+    #[inline(always)]
+    pub fn core_1_area_pif_0_rd_clr(&mut self) -> CORE_1_AREA_PIF_0_RD_CLR_W<CORE_1_INTR_CLR_SPEC> {
+        CORE_1_AREA_PIF_0_RD_CLR_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - Core1 PIF area0 write monitor interrupt clr"]
+    #[inline(always)]
+    pub fn core_1_area_pif_0_wr_clr(&mut self) -> CORE_1_AREA_PIF_0_WR_CLR_W<CORE_1_INTR_CLR_SPEC> {
+        CORE_1_AREA_PIF_0_WR_CLR_W::new(self, 5)
+    }
+    #[doc = "Bit 6 - Core1 PIF area1 read monitor interrupt clr"]
+    #[inline(always)]
+    pub fn core_1_area_pif_1_rd_clr(&mut self) -> CORE_1_AREA_PIF_1_RD_CLR_W<CORE_1_INTR_CLR_SPEC> {
+        CORE_1_AREA_PIF_1_RD_CLR_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - Core1 PIF area1 write monitor interrupt clr"]
+    #[inline(always)]
+    pub fn core_1_area_pif_1_wr_clr(&mut self) -> CORE_1_AREA_PIF_1_WR_CLR_W<CORE_1_INTR_CLR_SPEC> {
+        CORE_1_AREA_PIF_1_WR_CLR_W::new(self, 7)
+    }
+    #[doc = "Bit 8 - Core1 stackpoint overflow monitor interrupt clr"]
+    #[inline(always)]
+    pub fn core_1_sp_spill_min_clr(&mut self) -> CORE_1_SP_SPILL_MIN_CLR_W<CORE_1_INTR_CLR_SPEC> {
+        CORE_1_SP_SPILL_MIN_CLR_W::new(self, 8)
+    }
+    #[doc = "Bit 9 - Core1 stackpoint underflow monitor interrupt clr"]
+    #[inline(always)]
+    pub fn core_1_sp_spill_max_clr(&mut self) -> CORE_1_SP_SPILL_MAX_CLR_W<CORE_1_INTR_CLR_SPEC> {
+        CORE_1_SP_SPILL_MAX_CLR_W::new(self, 9)
+    }
+    #[doc = "Bit 10 - IBUS busy monitor interrupt clr"]
+    #[inline(always)]
+    pub fn core_1_iram0_exception_monitor_clr(
+        &mut self,
+    ) -> CORE_1_IRAM0_EXCEPTION_MONITOR_CLR_W<CORE_1_INTR_CLR_SPEC> {
+        CORE_1_IRAM0_EXCEPTION_MONITOR_CLR_W::new(self, 10)
+    }
+    #[doc = "Bit 11 - DBUS busy monitor interrupt clr"]
+    #[inline(always)]
+    pub fn core_1_dram0_exception_monitor_clr(
+        &mut self,
+    ) -> CORE_1_DRAM0_EXCEPTION_MONITOR_CLR_W<CORE_1_INTR_CLR_SPEC> {
+        CORE_1_DRAM0_EXCEPTION_MONITOR_CLR_W::new(self, 11)
+    }
+}
+#[doc = "Core1 monitor interrupt clr register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_intr_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_1_intr_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_1_INTR_CLR_SPEC;
+impl crate::RegisterSpec for CORE_1_INTR_CLR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_1_intr_clr::R`](R) reader structure"]
+impl crate::Readable for CORE_1_INTR_CLR_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`core_1_intr_clr::W`](W) writer structure"]
+impl crate::Writable for CORE_1_INTR_CLR_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CORE_1_INTR_CLR to value 0"]
+impl crate::Resettable for CORE_1_INTR_CLR_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/core_1_intr_ena.rs

@@ -0,0 +1,276 @@
+#[doc = "Register `CORE_1_INTR_ENA` reader"]
+pub type R = crate::R<CORE_1_INTR_ENA_SPEC>;
+#[doc = "Register `CORE_1_INTR_ENA` writer"]
+pub type W = crate::W<CORE_1_INTR_ENA_SPEC>;
+#[doc = "Field `CORE_1_AREA_DRAM0_0_RD_INTR_ENA` reader - Core1 dram0 area0 read monitor interrupt enable"]
+pub type CORE_1_AREA_DRAM0_0_RD_INTR_ENA_R = crate::BitReader;
+#[doc = "Field `CORE_1_AREA_DRAM0_0_RD_INTR_ENA` writer - Core1 dram0 area0 read monitor interrupt enable"]
+pub type CORE_1_AREA_DRAM0_0_RD_INTR_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_1_AREA_DRAM0_0_WR_INTR_ENA` reader - Core1 dram0 area0 write monitor interrupt enable"]
+pub type CORE_1_AREA_DRAM0_0_WR_INTR_ENA_R = crate::BitReader;
+#[doc = "Field `CORE_1_AREA_DRAM0_0_WR_INTR_ENA` writer - Core1 dram0 area0 write monitor interrupt enable"]
+pub type CORE_1_AREA_DRAM0_0_WR_INTR_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_1_AREA_DRAM0_1_RD_INTR_ENA` reader - Core1 dram0 area1 read monitor interrupt enable"]
+pub type CORE_1_AREA_DRAM0_1_RD_INTR_ENA_R = crate::BitReader;
+#[doc = "Field `CORE_1_AREA_DRAM0_1_RD_INTR_ENA` writer - Core1 dram0 area1 read monitor interrupt enable"]
+pub type CORE_1_AREA_DRAM0_1_RD_INTR_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_1_AREA_DRAM0_1_WR_INTR_ENA` reader - Core1 dram0 area1 write monitor interrupt enable"]
+pub type CORE_1_AREA_DRAM0_1_WR_INTR_ENA_R = crate::BitReader;
+#[doc = "Field `CORE_1_AREA_DRAM0_1_WR_INTR_ENA` writer - Core1 dram0 area1 write monitor interrupt enable"]
+pub type CORE_1_AREA_DRAM0_1_WR_INTR_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_1_AREA_PIF_0_RD_INTR_ENA` reader - Core1 PIF area0 read monitor interrupt enable"]
+pub type CORE_1_AREA_PIF_0_RD_INTR_ENA_R = crate::BitReader;
+#[doc = "Field `CORE_1_AREA_PIF_0_RD_INTR_ENA` writer - Core1 PIF area0 read monitor interrupt enable"]
+pub type CORE_1_AREA_PIF_0_RD_INTR_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_1_AREA_PIF_0_WR_INTR_ENA` reader - Core1 PIF area0 write monitor interrupt enable"]
+pub type CORE_1_AREA_PIF_0_WR_INTR_ENA_R = crate::BitReader;
+#[doc = "Field `CORE_1_AREA_PIF_0_WR_INTR_ENA` writer - Core1 PIF area0 write monitor interrupt enable"]
+pub type CORE_1_AREA_PIF_0_WR_INTR_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_1_AREA_PIF_1_RD_INTR_ENA` reader - Core1 PIF area1 read monitor interrupt enable"]
+pub type CORE_1_AREA_PIF_1_RD_INTR_ENA_R = crate::BitReader;
+#[doc = "Field `CORE_1_AREA_PIF_1_RD_INTR_ENA` writer - Core1 PIF area1 read monitor interrupt enable"]
+pub type CORE_1_AREA_PIF_1_RD_INTR_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_1_AREA_PIF_1_WR_INTR_ENA` reader - Core1 PIF area1 write monitor interrupt enable"]
+pub type CORE_1_AREA_PIF_1_WR_INTR_ENA_R = crate::BitReader;
+#[doc = "Field `CORE_1_AREA_PIF_1_WR_INTR_ENA` writer - Core1 PIF area1 write monitor interrupt enable"]
+pub type CORE_1_AREA_PIF_1_WR_INTR_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_1_SP_SPILL_MIN_INTR_ENA` reader - Core1 stackpoint overflow monitor interrupt enable"]
+pub type CORE_1_SP_SPILL_MIN_INTR_ENA_R = crate::BitReader;
+#[doc = "Field `CORE_1_SP_SPILL_MIN_INTR_ENA` writer - Core1 stackpoint overflow monitor interrupt enable"]
+pub type CORE_1_SP_SPILL_MIN_INTR_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_1_SP_SPILL_MAX_INTR_ENA` reader - Core1 stackpoint underflow monitor interrupt enable"]
+pub type CORE_1_SP_SPILL_MAX_INTR_ENA_R = crate::BitReader;
+#[doc = "Field `CORE_1_SP_SPILL_MAX_INTR_ENA` writer - Core1 stackpoint underflow monitor interrupt enable"]
+pub type CORE_1_SP_SPILL_MAX_INTR_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_1_IRAM0_EXCEPTION_MONITOR_INTR_ENA` reader - IBUS busy monitor interrupt enable"]
+pub type CORE_1_IRAM0_EXCEPTION_MONITOR_INTR_ENA_R = crate::BitReader;
+#[doc = "Field `CORE_1_IRAM0_EXCEPTION_MONITOR_INTR_ENA` writer - IBUS busy monitor interrupt enable"]
+pub type CORE_1_IRAM0_EXCEPTION_MONITOR_INTR_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_1_DRAM0_EXCEPTION_MONITOR_INTR_ENA` reader - DBUS busy monitor interrupt enbale"]
+pub type CORE_1_DRAM0_EXCEPTION_MONITOR_INTR_ENA_R = crate::BitReader;
+#[doc = "Field `CORE_1_DRAM0_EXCEPTION_MONITOR_INTR_ENA` writer - DBUS busy monitor interrupt enbale"]
+pub type CORE_1_DRAM0_EXCEPTION_MONITOR_INTR_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Core1 dram0 area0 read monitor interrupt enable"]
+    #[inline(always)]
+    pub fn core_1_area_dram0_0_rd_intr_ena(&self) -> CORE_1_AREA_DRAM0_0_RD_INTR_ENA_R {
+        CORE_1_AREA_DRAM0_0_RD_INTR_ENA_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Core1 dram0 area0 write monitor interrupt enable"]
+    #[inline(always)]
+    pub fn core_1_area_dram0_0_wr_intr_ena(&self) -> CORE_1_AREA_DRAM0_0_WR_INTR_ENA_R {
+        CORE_1_AREA_DRAM0_0_WR_INTR_ENA_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Core1 dram0 area1 read monitor interrupt enable"]
+    #[inline(always)]
+    pub fn core_1_area_dram0_1_rd_intr_ena(&self) -> CORE_1_AREA_DRAM0_1_RD_INTR_ENA_R {
+        CORE_1_AREA_DRAM0_1_RD_INTR_ENA_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Core1 dram0 area1 write monitor interrupt enable"]
+    #[inline(always)]
+    pub fn core_1_area_dram0_1_wr_intr_ena(&self) -> CORE_1_AREA_DRAM0_1_WR_INTR_ENA_R {
+        CORE_1_AREA_DRAM0_1_WR_INTR_ENA_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Core1 PIF area0 read monitor interrupt enable"]
+    #[inline(always)]
+    pub fn core_1_area_pif_0_rd_intr_ena(&self) -> CORE_1_AREA_PIF_0_RD_INTR_ENA_R {
+        CORE_1_AREA_PIF_0_RD_INTR_ENA_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - Core1 PIF area0 write monitor interrupt enable"]
+    #[inline(always)]
+    pub fn core_1_area_pif_0_wr_intr_ena(&self) -> CORE_1_AREA_PIF_0_WR_INTR_ENA_R {
+        CORE_1_AREA_PIF_0_WR_INTR_ENA_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - Core1 PIF area1 read monitor interrupt enable"]
+    #[inline(always)]
+    pub fn core_1_area_pif_1_rd_intr_ena(&self) -> CORE_1_AREA_PIF_1_RD_INTR_ENA_R {
+        CORE_1_AREA_PIF_1_RD_INTR_ENA_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - Core1 PIF area1 write monitor interrupt enable"]
+    #[inline(always)]
+    pub fn core_1_area_pif_1_wr_intr_ena(&self) -> CORE_1_AREA_PIF_1_WR_INTR_ENA_R {
+        CORE_1_AREA_PIF_1_WR_INTR_ENA_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - Core1 stackpoint overflow monitor interrupt enable"]
+    #[inline(always)]
+    pub fn core_1_sp_spill_min_intr_ena(&self) -> CORE_1_SP_SPILL_MIN_INTR_ENA_R {
+        CORE_1_SP_SPILL_MIN_INTR_ENA_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - Core1 stackpoint underflow monitor interrupt enable"]
+    #[inline(always)]
+    pub fn core_1_sp_spill_max_intr_ena(&self) -> CORE_1_SP_SPILL_MAX_INTR_ENA_R {
+        CORE_1_SP_SPILL_MAX_INTR_ENA_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 10 - IBUS busy monitor interrupt enable"]
+    #[inline(always)]
+    pub fn core_1_iram0_exception_monitor_intr_ena(
+        &self,
+    ) -> CORE_1_IRAM0_EXCEPTION_MONITOR_INTR_ENA_R {
+        CORE_1_IRAM0_EXCEPTION_MONITOR_INTR_ENA_R::new(((self.bits >> 10) & 1) != 0)
+    }
+    #[doc = "Bit 11 - DBUS busy monitor interrupt enbale"]
+    #[inline(always)]
+    pub fn core_1_dram0_exception_monitor_intr_ena(
+        &self,
+    ) -> CORE_1_DRAM0_EXCEPTION_MONITOR_INTR_ENA_R {
+        CORE_1_DRAM0_EXCEPTION_MONITOR_INTR_ENA_R::new(((self.bits >> 11) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_1_INTR_ENA")
+            .field(
+                "core_1_area_dram0_0_rd_intr_ena",
+                &self.core_1_area_dram0_0_rd_intr_ena(),
+            )
+            .field(
+                "core_1_area_dram0_0_wr_intr_ena",
+                &self.core_1_area_dram0_0_wr_intr_ena(),
+            )
+            .field(
+                "core_1_area_dram0_1_rd_intr_ena",
+                &self.core_1_area_dram0_1_rd_intr_ena(),
+            )
+            .field(
+                "core_1_area_dram0_1_wr_intr_ena",
+                &self.core_1_area_dram0_1_wr_intr_ena(),
+            )
+            .field(
+                "core_1_area_pif_0_rd_intr_ena",
+                &self.core_1_area_pif_0_rd_intr_ena(),
+            )
+            .field(
+                "core_1_area_pif_0_wr_intr_ena",
+                &self.core_1_area_pif_0_wr_intr_ena(),
+            )
+            .field(
+                "core_1_area_pif_1_rd_intr_ena",
+                &self.core_1_area_pif_1_rd_intr_ena(),
+            )
+            .field(
+                "core_1_area_pif_1_wr_intr_ena",
+                &self.core_1_area_pif_1_wr_intr_ena(),
+            )
+            .field(
+                "core_1_sp_spill_min_intr_ena",
+                &self.core_1_sp_spill_min_intr_ena(),
+            )
+            .field(
+                "core_1_sp_spill_max_intr_ena",
+                &self.core_1_sp_spill_max_intr_ena(),
+            )
+            .field(
+                "core_1_iram0_exception_monitor_intr_ena",
+                &self.core_1_iram0_exception_monitor_intr_ena(),
+            )
+            .field(
+                "core_1_dram0_exception_monitor_intr_ena",
+                &self.core_1_dram0_exception_monitor_intr_ena(),
+            )
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Core1 dram0 area0 read monitor interrupt enable"]
+    #[inline(always)]
+    pub fn core_1_area_dram0_0_rd_intr_ena(
+        &mut self,
+    ) -> CORE_1_AREA_DRAM0_0_RD_INTR_ENA_W<CORE_1_INTR_ENA_SPEC> {
+        CORE_1_AREA_DRAM0_0_RD_INTR_ENA_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - Core1 dram0 area0 write monitor interrupt enable"]
+    #[inline(always)]
+    pub fn core_1_area_dram0_0_wr_intr_ena(
+        &mut self,
+    ) -> CORE_1_AREA_DRAM0_0_WR_INTR_ENA_W<CORE_1_INTR_ENA_SPEC> {
+        CORE_1_AREA_DRAM0_0_WR_INTR_ENA_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - Core1 dram0 area1 read monitor interrupt enable"]
+    #[inline(always)]
+    pub fn core_1_area_dram0_1_rd_intr_ena(
+        &mut self,
+    ) -> CORE_1_AREA_DRAM0_1_RD_INTR_ENA_W<CORE_1_INTR_ENA_SPEC> {
+        CORE_1_AREA_DRAM0_1_RD_INTR_ENA_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - Core1 dram0 area1 write monitor interrupt enable"]
+    #[inline(always)]
+    pub fn core_1_area_dram0_1_wr_intr_ena(
+        &mut self,
+    ) -> CORE_1_AREA_DRAM0_1_WR_INTR_ENA_W<CORE_1_INTR_ENA_SPEC> {
+        CORE_1_AREA_DRAM0_1_WR_INTR_ENA_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - Core1 PIF area0 read monitor interrupt enable"]
+    #[inline(always)]
+    pub fn core_1_area_pif_0_rd_intr_ena(
+        &mut self,
+    ) -> CORE_1_AREA_PIF_0_RD_INTR_ENA_W<CORE_1_INTR_ENA_SPEC> {
+        CORE_1_AREA_PIF_0_RD_INTR_ENA_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - Core1 PIF area0 write monitor interrupt enable"]
+    #[inline(always)]
+    pub fn core_1_area_pif_0_wr_intr_ena(
+        &mut self,
+    ) -> CORE_1_AREA_PIF_0_WR_INTR_ENA_W<CORE_1_INTR_ENA_SPEC> {
+        CORE_1_AREA_PIF_0_WR_INTR_ENA_W::new(self, 5)
+    }
+    #[doc = "Bit 6 - Core1 PIF area1 read monitor interrupt enable"]
+    #[inline(always)]
+    pub fn core_1_area_pif_1_rd_intr_ena(
+        &mut self,
+    ) -> CORE_1_AREA_PIF_1_RD_INTR_ENA_W<CORE_1_INTR_ENA_SPEC> {
+        CORE_1_AREA_PIF_1_RD_INTR_ENA_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - Core1 PIF area1 write monitor interrupt enable"]
+    #[inline(always)]
+    pub fn core_1_area_pif_1_wr_intr_ena(
+        &mut self,
+    ) -> CORE_1_AREA_PIF_1_WR_INTR_ENA_W<CORE_1_INTR_ENA_SPEC> {
+        CORE_1_AREA_PIF_1_WR_INTR_ENA_W::new(self, 7)
+    }
+    #[doc = "Bit 8 - Core1 stackpoint overflow monitor interrupt enable"]
+    #[inline(always)]
+    pub fn core_1_sp_spill_min_intr_ena(
+        &mut self,
+    ) -> CORE_1_SP_SPILL_MIN_INTR_ENA_W<CORE_1_INTR_ENA_SPEC> {
+        CORE_1_SP_SPILL_MIN_INTR_ENA_W::new(self, 8)
+    }
+    #[doc = "Bit 9 - Core1 stackpoint underflow monitor interrupt enable"]
+    #[inline(always)]
+    pub fn core_1_sp_spill_max_intr_ena(
+        &mut self,
+    ) -> CORE_1_SP_SPILL_MAX_INTR_ENA_W<CORE_1_INTR_ENA_SPEC> {
+        CORE_1_SP_SPILL_MAX_INTR_ENA_W::new(self, 9)
+    }
+    #[doc = "Bit 10 - IBUS busy monitor interrupt enable"]
+    #[inline(always)]
+    pub fn core_1_iram0_exception_monitor_intr_ena(
+        &mut self,
+    ) -> CORE_1_IRAM0_EXCEPTION_MONITOR_INTR_ENA_W<CORE_1_INTR_ENA_SPEC> {
+        CORE_1_IRAM0_EXCEPTION_MONITOR_INTR_ENA_W::new(self, 10)
+    }
+    #[doc = "Bit 11 - DBUS busy monitor interrupt enbale"]
+    #[inline(always)]
+    pub fn core_1_dram0_exception_monitor_intr_ena(
+        &mut self,
+    ) -> CORE_1_DRAM0_EXCEPTION_MONITOR_INTR_ENA_W<CORE_1_INTR_ENA_SPEC> {
+        CORE_1_DRAM0_EXCEPTION_MONITOR_INTR_ENA_W::new(self, 11)
+    }
+}
+#[doc = "Core1 monitor interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_intr_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_1_intr_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_1_INTR_ENA_SPEC;
+impl crate::RegisterSpec for CORE_1_INTR_ENA_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_1_intr_ena::R`](R) reader structure"]
+impl crate::Readable for CORE_1_INTR_ENA_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`core_1_intr_ena::W`](W) writer structure"]
+impl crate::Writable for CORE_1_INTR_ENA_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CORE_1_INTR_ENA to value 0"]
+impl crate::Resettable for CORE_1_INTR_ENA_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/core_1_intr_raw.rs

@@ -0,0 +1,136 @@
+#[doc = "Register `CORE_1_INTR_RAW` reader"]
+pub type R = crate::R<CORE_1_INTR_RAW_SPEC>;
+#[doc = "Field `CORE_1_AREA_DRAM0_0_RD_RAW` reader - Core1 dram0 area0 read monitor interrupt status"]
+pub type CORE_1_AREA_DRAM0_0_RD_RAW_R = crate::BitReader;
+#[doc = "Field `CORE_1_AREA_DRAM0_0_WR_RAW` reader - Core1 dram0 area0 write monitor interrupt status"]
+pub type CORE_1_AREA_DRAM0_0_WR_RAW_R = crate::BitReader;
+#[doc = "Field `CORE_1_AREA_DRAM0_1_RD_RAW` reader - Core1 dram0 area1 read monitor interrupt status"]
+pub type CORE_1_AREA_DRAM0_1_RD_RAW_R = crate::BitReader;
+#[doc = "Field `CORE_1_AREA_DRAM0_1_WR_RAW` reader - Core1 dram0 area1 write monitor interrupt status"]
+pub type CORE_1_AREA_DRAM0_1_WR_RAW_R = crate::BitReader;
+#[doc = "Field `CORE_1_AREA_PIF_0_RD_RAW` reader - Core1 PIF area0 read monitor interrupt status"]
+pub type CORE_1_AREA_PIF_0_RD_RAW_R = crate::BitReader;
+#[doc = "Field `CORE_1_AREA_PIF_0_WR_RAW` reader - Core1 PIF area0 write monitor interrupt status"]
+pub type CORE_1_AREA_PIF_0_WR_RAW_R = crate::BitReader;
+#[doc = "Field `CORE_1_AREA_PIF_1_RD_RAW` reader - Core1 PIF area1 read monitor interrupt status"]
+pub type CORE_1_AREA_PIF_1_RD_RAW_R = crate::BitReader;
+#[doc = "Field `CORE_1_AREA_PIF_1_WR_RAW` reader - Core1 PIF area1 write monitor interrupt status"]
+pub type CORE_1_AREA_PIF_1_WR_RAW_R = crate::BitReader;
+#[doc = "Field `CORE_1_SP_SPILL_MIN_RAW` reader - Core1 stackpoint overflow monitor interrupt status"]
+pub type CORE_1_SP_SPILL_MIN_RAW_R = crate::BitReader;
+#[doc = "Field `CORE_1_SP_SPILL_MAX_RAW` reader - Core1 stackpoint underflow monitor interrupt status"]
+pub type CORE_1_SP_SPILL_MAX_RAW_R = crate::BitReader;
+#[doc = "Field `CORE_1_IRAM0_EXCEPTION_MONITOR_RAW` reader - IBUS busy monitor interrupt status"]
+pub type CORE_1_IRAM0_EXCEPTION_MONITOR_RAW_R = crate::BitReader;
+#[doc = "Field `CORE_1_DRAM0_EXCEPTION_MONITOR_RAW` reader - DBUS busy monitor initerrupt status"]
+pub type CORE_1_DRAM0_EXCEPTION_MONITOR_RAW_R = crate::BitReader;
+impl R {
+    #[doc = "Bit 0 - Core1 dram0 area0 read monitor interrupt status"]
+    #[inline(always)]
+    pub fn core_1_area_dram0_0_rd_raw(&self) -> CORE_1_AREA_DRAM0_0_RD_RAW_R {
+        CORE_1_AREA_DRAM0_0_RD_RAW_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Core1 dram0 area0 write monitor interrupt status"]
+    #[inline(always)]
+    pub fn core_1_area_dram0_0_wr_raw(&self) -> CORE_1_AREA_DRAM0_0_WR_RAW_R {
+        CORE_1_AREA_DRAM0_0_WR_RAW_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Core1 dram0 area1 read monitor interrupt status"]
+    #[inline(always)]
+    pub fn core_1_area_dram0_1_rd_raw(&self) -> CORE_1_AREA_DRAM0_1_RD_RAW_R {
+        CORE_1_AREA_DRAM0_1_RD_RAW_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Core1 dram0 area1 write monitor interrupt status"]
+    #[inline(always)]
+    pub fn core_1_area_dram0_1_wr_raw(&self) -> CORE_1_AREA_DRAM0_1_WR_RAW_R {
+        CORE_1_AREA_DRAM0_1_WR_RAW_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Core1 PIF area0 read monitor interrupt status"]
+    #[inline(always)]
+    pub fn core_1_area_pif_0_rd_raw(&self) -> CORE_1_AREA_PIF_0_RD_RAW_R {
+        CORE_1_AREA_PIF_0_RD_RAW_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - Core1 PIF area0 write monitor interrupt status"]
+    #[inline(always)]
+    pub fn core_1_area_pif_0_wr_raw(&self) -> CORE_1_AREA_PIF_0_WR_RAW_R {
+        CORE_1_AREA_PIF_0_WR_RAW_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - Core1 PIF area1 read monitor interrupt status"]
+    #[inline(always)]
+    pub fn core_1_area_pif_1_rd_raw(&self) -> CORE_1_AREA_PIF_1_RD_RAW_R {
+        CORE_1_AREA_PIF_1_RD_RAW_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - Core1 PIF area1 write monitor interrupt status"]
+    #[inline(always)]
+    pub fn core_1_area_pif_1_wr_raw(&self) -> CORE_1_AREA_PIF_1_WR_RAW_R {
+        CORE_1_AREA_PIF_1_WR_RAW_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - Core1 stackpoint overflow monitor interrupt status"]
+    #[inline(always)]
+    pub fn core_1_sp_spill_min_raw(&self) -> CORE_1_SP_SPILL_MIN_RAW_R {
+        CORE_1_SP_SPILL_MIN_RAW_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - Core1 stackpoint underflow monitor interrupt status"]
+    #[inline(always)]
+    pub fn core_1_sp_spill_max_raw(&self) -> CORE_1_SP_SPILL_MAX_RAW_R {
+        CORE_1_SP_SPILL_MAX_RAW_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 10 - IBUS busy monitor interrupt status"]
+    #[inline(always)]
+    pub fn core_1_iram0_exception_monitor_raw(&self) -> CORE_1_IRAM0_EXCEPTION_MONITOR_RAW_R {
+        CORE_1_IRAM0_EXCEPTION_MONITOR_RAW_R::new(((self.bits >> 10) & 1) != 0)
+    }
+    #[doc = "Bit 11 - DBUS busy monitor initerrupt status"]
+    #[inline(always)]
+    pub fn core_1_dram0_exception_monitor_raw(&self) -> CORE_1_DRAM0_EXCEPTION_MONITOR_RAW_R {
+        CORE_1_DRAM0_EXCEPTION_MONITOR_RAW_R::new(((self.bits >> 11) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_1_INTR_RAW")
+            .field(
+                "core_1_area_dram0_0_rd_raw",
+                &self.core_1_area_dram0_0_rd_raw(),
+            )
+            .field(
+                "core_1_area_dram0_0_wr_raw",
+                &self.core_1_area_dram0_0_wr_raw(),
+            )
+            .field(
+                "core_1_area_dram0_1_rd_raw",
+                &self.core_1_area_dram0_1_rd_raw(),
+            )
+            .field(
+                "core_1_area_dram0_1_wr_raw",
+                &self.core_1_area_dram0_1_wr_raw(),
+            )
+            .field("core_1_area_pif_0_rd_raw", &self.core_1_area_pif_0_rd_raw())
+            .field("core_1_area_pif_0_wr_raw", &self.core_1_area_pif_0_wr_raw())
+            .field("core_1_area_pif_1_rd_raw", &self.core_1_area_pif_1_rd_raw())
+            .field("core_1_area_pif_1_wr_raw", &self.core_1_area_pif_1_wr_raw())
+            .field("core_1_sp_spill_min_raw", &self.core_1_sp_spill_min_raw())
+            .field("core_1_sp_spill_max_raw", &self.core_1_sp_spill_max_raw())
+            .field(
+                "core_1_iram0_exception_monitor_raw",
+                &self.core_1_iram0_exception_monitor_raw(),
+            )
+            .field(
+                "core_1_dram0_exception_monitor_raw",
+                &self.core_1_dram0_exception_monitor_raw(),
+            )
+            .finish()
+    }
+}
+#[doc = "Core1 monitor interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_intr_raw::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_1_INTR_RAW_SPEC;
+impl crate::RegisterSpec for CORE_1_INTR_RAW_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_1_intr_raw::R`](R) reader structure"]
+impl crate::Readable for CORE_1_INTR_RAW_SPEC {}
+#[doc = "`reset()` method sets CORE_1_INTR_RAW to value 0"]
+impl crate::Resettable for CORE_1_INTR_RAW_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/core_1_iram0_exception_monitor_0.rs

@@ -0,0 +1,55 @@
+#[doc = "Register `CORE_1_IRAM0_EXCEPTION_MONITOR_0` reader"]
+pub type R = crate::R<CORE_1_IRAM0_EXCEPTION_MONITOR_0_SPEC>;
+#[doc = "Field `CORE_1_IRAM0_RECORDING_ADDR_0` reader - The first iram0's addr\\[25:2\\] status when trigger IRAM busy interrupt"]
+pub type CORE_1_IRAM0_RECORDING_ADDR_0_R = crate::FieldReader<u32>;
+#[doc = "Field `CORE_1_IRAM0_RECORDING_WR_0` reader - The first iram0's wr status when trigger IRAM busy interrupt"]
+pub type CORE_1_IRAM0_RECORDING_WR_0_R = crate::BitReader;
+#[doc = "Field `CORE_1_IRAM0_RECORDING_LOADSTORE_0` reader - The first iram0's loadstore status when trigger IRAM busy interrupt"]
+pub type CORE_1_IRAM0_RECORDING_LOADSTORE_0_R = crate::BitReader;
+impl R {
+    #[doc = "Bits 0:23 - The first iram0's addr\\[25:2\\] status when trigger IRAM busy interrupt"]
+    #[inline(always)]
+    pub fn core_1_iram0_recording_addr_0(&self) -> CORE_1_IRAM0_RECORDING_ADDR_0_R {
+        CORE_1_IRAM0_RECORDING_ADDR_0_R::new(self.bits & 0x00ff_ffff)
+    }
+    #[doc = "Bit 24 - The first iram0's wr status when trigger IRAM busy interrupt"]
+    #[inline(always)]
+    pub fn core_1_iram0_recording_wr_0(&self) -> CORE_1_IRAM0_RECORDING_WR_0_R {
+        CORE_1_IRAM0_RECORDING_WR_0_R::new(((self.bits >> 24) & 1) != 0)
+    }
+    #[doc = "Bit 25 - The first iram0's loadstore status when trigger IRAM busy interrupt"]
+    #[inline(always)]
+    pub fn core_1_iram0_recording_loadstore_0(&self) -> CORE_1_IRAM0_RECORDING_LOADSTORE_0_R {
+        CORE_1_IRAM0_RECORDING_LOADSTORE_0_R::new(((self.bits >> 25) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_1_IRAM0_EXCEPTION_MONITOR_0")
+            .field(
+                "core_1_iram0_recording_addr_0",
+                &self.core_1_iram0_recording_addr_0(),
+            )
+            .field(
+                "core_1_iram0_recording_wr_0",
+                &self.core_1_iram0_recording_wr_0(),
+            )
+            .field(
+                "core_1_iram0_recording_loadstore_0",
+                &self.core_1_iram0_recording_loadstore_0(),
+            )
+            .finish()
+    }
+}
+#[doc = "Core1 bus busy status regsiter\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_iram0_exception_monitor_0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_1_IRAM0_EXCEPTION_MONITOR_0_SPEC;
+impl crate::RegisterSpec for CORE_1_IRAM0_EXCEPTION_MONITOR_0_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_1_iram0_exception_monitor_0::R`](R) reader structure"]
+impl crate::Readable for CORE_1_IRAM0_EXCEPTION_MONITOR_0_SPEC {}
+#[doc = "`reset()` method sets CORE_1_IRAM0_EXCEPTION_MONITOR_0 to value 0"]
+impl crate::Resettable for CORE_1_IRAM0_EXCEPTION_MONITOR_0_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/core_1_iram0_exception_monitor_1.rs

@@ -0,0 +1,55 @@
+#[doc = "Register `CORE_1_IRAM0_EXCEPTION_MONITOR_1` reader"]
+pub type R = crate::R<CORE_1_IRAM0_EXCEPTION_MONITOR_1_SPEC>;
+#[doc = "Field `CORE_1_IRAM0_RECORDING_ADDR_1` reader - The second iram0's addr\\[25:2\\] status when trigger IRAM busy interrupt"]
+pub type CORE_1_IRAM0_RECORDING_ADDR_1_R = crate::FieldReader<u32>;
+#[doc = "Field `CORE_1_IRAM0_RECORDING_WR_1` reader - The second iram0's wr status when trigger IRAM busy interrupt"]
+pub type CORE_1_IRAM0_RECORDING_WR_1_R = crate::BitReader;
+#[doc = "Field `CORE_1_IRAM0_RECORDING_LOADSTORE_1` reader - The second iram0's loadstore status when trigger IRAM busy interrupt"]
+pub type CORE_1_IRAM0_RECORDING_LOADSTORE_1_R = crate::BitReader;
+impl R {
+    #[doc = "Bits 0:23 - The second iram0's addr\\[25:2\\] status when trigger IRAM busy interrupt"]
+    #[inline(always)]
+    pub fn core_1_iram0_recording_addr_1(&self) -> CORE_1_IRAM0_RECORDING_ADDR_1_R {
+        CORE_1_IRAM0_RECORDING_ADDR_1_R::new(self.bits & 0x00ff_ffff)
+    }
+    #[doc = "Bit 24 - The second iram0's wr status when trigger IRAM busy interrupt"]
+    #[inline(always)]
+    pub fn core_1_iram0_recording_wr_1(&self) -> CORE_1_IRAM0_RECORDING_WR_1_R {
+        CORE_1_IRAM0_RECORDING_WR_1_R::new(((self.bits >> 24) & 1) != 0)
+    }
+    #[doc = "Bit 25 - The second iram0's loadstore status when trigger IRAM busy interrupt"]
+    #[inline(always)]
+    pub fn core_1_iram0_recording_loadstore_1(&self) -> CORE_1_IRAM0_RECORDING_LOADSTORE_1_R {
+        CORE_1_IRAM0_RECORDING_LOADSTORE_1_R::new(((self.bits >> 25) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_1_IRAM0_EXCEPTION_MONITOR_1")
+            .field(
+                "core_1_iram0_recording_addr_1",
+                &self.core_1_iram0_recording_addr_1(),
+            )
+            .field(
+                "core_1_iram0_recording_wr_1",
+                &self.core_1_iram0_recording_wr_1(),
+            )
+            .field(
+                "core_1_iram0_recording_loadstore_1",
+                &self.core_1_iram0_recording_loadstore_1(),
+            )
+            .finish()
+    }
+}
+#[doc = "Core1 bus busy status regsiter\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_iram0_exception_monitor_1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_1_IRAM0_EXCEPTION_MONITOR_1_SPEC;
+impl crate::RegisterSpec for CORE_1_IRAM0_EXCEPTION_MONITOR_1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_1_iram0_exception_monitor_1::R`](R) reader structure"]
+impl crate::Readable for CORE_1_IRAM0_EXCEPTION_MONITOR_1_SPEC {}
+#[doc = "`reset()` method sets CORE_1_IRAM0_EXCEPTION_MONITOR_1 to value 0"]
+impl crate::Resettable for CORE_1_IRAM0_EXCEPTION_MONITOR_1_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/core_1_montr_ena.rs

@@ -0,0 +1,250 @@
+#[doc = "Register `CORE_1_MONTR_ENA` reader"]
+pub type R = crate::R<CORE_1_MONTR_ENA_SPEC>;
+#[doc = "Register `CORE_1_MONTR_ENA` writer"]
+pub type W = crate::W<CORE_1_MONTR_ENA_SPEC>;
+#[doc = "Field `CORE_1_AREA_DRAM0_0_RD_ENA` reader - Core1 dram0 area0 read monitor enable"]
+pub type CORE_1_AREA_DRAM0_0_RD_ENA_R = crate::BitReader;
+#[doc = "Field `CORE_1_AREA_DRAM0_0_RD_ENA` writer - Core1 dram0 area0 read monitor enable"]
+pub type CORE_1_AREA_DRAM0_0_RD_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_1_AREA_DRAM0_0_WR_ENA` reader - Core1 dram0 area0 write monitor enable"]
+pub type CORE_1_AREA_DRAM0_0_WR_ENA_R = crate::BitReader;
+#[doc = "Field `CORE_1_AREA_DRAM0_0_WR_ENA` writer - Core1 dram0 area0 write monitor enable"]
+pub type CORE_1_AREA_DRAM0_0_WR_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_1_AREA_DRAM0_1_RD_ENA` reader - Core1 dram0 area1 read monitor enable"]
+pub type CORE_1_AREA_DRAM0_1_RD_ENA_R = crate::BitReader;
+#[doc = "Field `CORE_1_AREA_DRAM0_1_RD_ENA` writer - Core1 dram0 area1 read monitor enable"]
+pub type CORE_1_AREA_DRAM0_1_RD_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_1_AREA_DRAM0_1_WR_ENA` reader - Core1 dram0 area1 write monitor enable"]
+pub type CORE_1_AREA_DRAM0_1_WR_ENA_R = crate::BitReader;
+#[doc = "Field `CORE_1_AREA_DRAM0_1_WR_ENA` writer - Core1 dram0 area1 write monitor enable"]
+pub type CORE_1_AREA_DRAM0_1_WR_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_1_AREA_PIF_0_RD_ENA` reader - Core1 PIF area0 read monitor enable"]
+pub type CORE_1_AREA_PIF_0_RD_ENA_R = crate::BitReader;
+#[doc = "Field `CORE_1_AREA_PIF_0_RD_ENA` writer - Core1 PIF area0 read monitor enable"]
+pub type CORE_1_AREA_PIF_0_RD_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_1_AREA_PIF_0_WR_ENA` reader - Core1 PIF area0 write monitor enable"]
+pub type CORE_1_AREA_PIF_0_WR_ENA_R = crate::BitReader;
+#[doc = "Field `CORE_1_AREA_PIF_0_WR_ENA` writer - Core1 PIF area0 write monitor enable"]
+pub type CORE_1_AREA_PIF_0_WR_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_1_AREA_PIF_1_RD_ENA` reader - Core1 PIF area1 read monitor enable"]
+pub type CORE_1_AREA_PIF_1_RD_ENA_R = crate::BitReader;
+#[doc = "Field `CORE_1_AREA_PIF_1_RD_ENA` writer - Core1 PIF area1 read monitor enable"]
+pub type CORE_1_AREA_PIF_1_RD_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_1_AREA_PIF_1_WR_ENA` reader - Core1 PIF area1 write monitor enable"]
+pub type CORE_1_AREA_PIF_1_WR_ENA_R = crate::BitReader;
+#[doc = "Field `CORE_1_AREA_PIF_1_WR_ENA` writer - Core1 PIF area1 write monitor enable"]
+pub type CORE_1_AREA_PIF_1_WR_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_1_SP_SPILL_MIN_ENA` reader - Core1 stackpoint overflow monitor enable"]
+pub type CORE_1_SP_SPILL_MIN_ENA_R = crate::BitReader;
+#[doc = "Field `CORE_1_SP_SPILL_MIN_ENA` writer - Core1 stackpoint overflow monitor enable"]
+pub type CORE_1_SP_SPILL_MIN_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_1_SP_SPILL_MAX_ENA` reader - Core1 stackpoint underflow monitor enable"]
+pub type CORE_1_SP_SPILL_MAX_ENA_R = crate::BitReader;
+#[doc = "Field `CORE_1_SP_SPILL_MAX_ENA` writer - Core1 stackpoint underflow monitor enable"]
+pub type CORE_1_SP_SPILL_MAX_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_1_IRAM0_EXCEPTION_MONITOR_ENA` reader - IBUS busy monitor enable"]
+pub type CORE_1_IRAM0_EXCEPTION_MONITOR_ENA_R = crate::BitReader;
+#[doc = "Field `CORE_1_IRAM0_EXCEPTION_MONITOR_ENA` writer - IBUS busy monitor enable"]
+pub type CORE_1_IRAM0_EXCEPTION_MONITOR_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CORE_1_DRAM0_EXCEPTION_MONITOR_ENA` reader - DBUS busy monitor enbale"]
+pub type CORE_1_DRAM0_EXCEPTION_MONITOR_ENA_R = crate::BitReader;
+#[doc = "Field `CORE_1_DRAM0_EXCEPTION_MONITOR_ENA` writer - DBUS busy monitor enbale"]
+pub type CORE_1_DRAM0_EXCEPTION_MONITOR_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Core1 dram0 area0 read monitor enable"]
+    #[inline(always)]
+    pub fn core_1_area_dram0_0_rd_ena(&self) -> CORE_1_AREA_DRAM0_0_RD_ENA_R {
+        CORE_1_AREA_DRAM0_0_RD_ENA_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Core1 dram0 area0 write monitor enable"]
+    #[inline(always)]
+    pub fn core_1_area_dram0_0_wr_ena(&self) -> CORE_1_AREA_DRAM0_0_WR_ENA_R {
+        CORE_1_AREA_DRAM0_0_WR_ENA_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Core1 dram0 area1 read monitor enable"]
+    #[inline(always)]
+    pub fn core_1_area_dram0_1_rd_ena(&self) -> CORE_1_AREA_DRAM0_1_RD_ENA_R {
+        CORE_1_AREA_DRAM0_1_RD_ENA_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Core1 dram0 area1 write monitor enable"]
+    #[inline(always)]
+    pub fn core_1_area_dram0_1_wr_ena(&self) -> CORE_1_AREA_DRAM0_1_WR_ENA_R {
+        CORE_1_AREA_DRAM0_1_WR_ENA_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Core1 PIF area0 read monitor enable"]
+    #[inline(always)]
+    pub fn core_1_area_pif_0_rd_ena(&self) -> CORE_1_AREA_PIF_0_RD_ENA_R {
+        CORE_1_AREA_PIF_0_RD_ENA_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - Core1 PIF area0 write monitor enable"]
+    #[inline(always)]
+    pub fn core_1_area_pif_0_wr_ena(&self) -> CORE_1_AREA_PIF_0_WR_ENA_R {
+        CORE_1_AREA_PIF_0_WR_ENA_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - Core1 PIF area1 read monitor enable"]
+    #[inline(always)]
+    pub fn core_1_area_pif_1_rd_ena(&self) -> CORE_1_AREA_PIF_1_RD_ENA_R {
+        CORE_1_AREA_PIF_1_RD_ENA_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - Core1 PIF area1 write monitor enable"]
+    #[inline(always)]
+    pub fn core_1_area_pif_1_wr_ena(&self) -> CORE_1_AREA_PIF_1_WR_ENA_R {
+        CORE_1_AREA_PIF_1_WR_ENA_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - Core1 stackpoint overflow monitor enable"]
+    #[inline(always)]
+    pub fn core_1_sp_spill_min_ena(&self) -> CORE_1_SP_SPILL_MIN_ENA_R {
+        CORE_1_SP_SPILL_MIN_ENA_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - Core1 stackpoint underflow monitor enable"]
+    #[inline(always)]
+    pub fn core_1_sp_spill_max_ena(&self) -> CORE_1_SP_SPILL_MAX_ENA_R {
+        CORE_1_SP_SPILL_MAX_ENA_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 10 - IBUS busy monitor enable"]
+    #[inline(always)]
+    pub fn core_1_iram0_exception_monitor_ena(&self) -> CORE_1_IRAM0_EXCEPTION_MONITOR_ENA_R {
+        CORE_1_IRAM0_EXCEPTION_MONITOR_ENA_R::new(((self.bits >> 10) & 1) != 0)
+    }
+    #[doc = "Bit 11 - DBUS busy monitor enbale"]
+    #[inline(always)]
+    pub fn core_1_dram0_exception_monitor_ena(&self) -> CORE_1_DRAM0_EXCEPTION_MONITOR_ENA_R {
+        CORE_1_DRAM0_EXCEPTION_MONITOR_ENA_R::new(((self.bits >> 11) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_1_MONTR_ENA")
+            .field(
+                "core_1_area_dram0_0_rd_ena",
+                &self.core_1_area_dram0_0_rd_ena(),
+            )
+            .field(
+                "core_1_area_dram0_0_wr_ena",
+                &self.core_1_area_dram0_0_wr_ena(),
+            )
+            .field(
+                "core_1_area_dram0_1_rd_ena",
+                &self.core_1_area_dram0_1_rd_ena(),
+            )
+            .field(
+                "core_1_area_dram0_1_wr_ena",
+                &self.core_1_area_dram0_1_wr_ena(),
+            )
+            .field("core_1_area_pif_0_rd_ena", &self.core_1_area_pif_0_rd_ena())
+            .field("core_1_area_pif_0_wr_ena", &self.core_1_area_pif_0_wr_ena())
+            .field("core_1_area_pif_1_rd_ena", &self.core_1_area_pif_1_rd_ena())
+            .field("core_1_area_pif_1_wr_ena", &self.core_1_area_pif_1_wr_ena())
+            .field("core_1_sp_spill_min_ena", &self.core_1_sp_spill_min_ena())
+            .field("core_1_sp_spill_max_ena", &self.core_1_sp_spill_max_ena())
+            .field(
+                "core_1_iram0_exception_monitor_ena",
+                &self.core_1_iram0_exception_monitor_ena(),
+            )
+            .field(
+                "core_1_dram0_exception_monitor_ena",
+                &self.core_1_dram0_exception_monitor_ena(),
+            )
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Core1 dram0 area0 read monitor enable"]
+    #[inline(always)]
+    pub fn core_1_area_dram0_0_rd_ena(
+        &mut self,
+    ) -> CORE_1_AREA_DRAM0_0_RD_ENA_W<CORE_1_MONTR_ENA_SPEC> {
+        CORE_1_AREA_DRAM0_0_RD_ENA_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - Core1 dram0 area0 write monitor enable"]
+    #[inline(always)]
+    pub fn core_1_area_dram0_0_wr_ena(
+        &mut self,
+    ) -> CORE_1_AREA_DRAM0_0_WR_ENA_W<CORE_1_MONTR_ENA_SPEC> {
+        CORE_1_AREA_DRAM0_0_WR_ENA_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - Core1 dram0 area1 read monitor enable"]
+    #[inline(always)]
+    pub fn core_1_area_dram0_1_rd_ena(
+        &mut self,
+    ) -> CORE_1_AREA_DRAM0_1_RD_ENA_W<CORE_1_MONTR_ENA_SPEC> {
+        CORE_1_AREA_DRAM0_1_RD_ENA_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - Core1 dram0 area1 write monitor enable"]
+    #[inline(always)]
+    pub fn core_1_area_dram0_1_wr_ena(
+        &mut self,
+    ) -> CORE_1_AREA_DRAM0_1_WR_ENA_W<CORE_1_MONTR_ENA_SPEC> {
+        CORE_1_AREA_DRAM0_1_WR_ENA_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - Core1 PIF area0 read monitor enable"]
+    #[inline(always)]
+    pub fn core_1_area_pif_0_rd_ena(
+        &mut self,
+    ) -> CORE_1_AREA_PIF_0_RD_ENA_W<CORE_1_MONTR_ENA_SPEC> {
+        CORE_1_AREA_PIF_0_RD_ENA_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - Core1 PIF area0 write monitor enable"]
+    #[inline(always)]
+    pub fn core_1_area_pif_0_wr_ena(
+        &mut self,
+    ) -> CORE_1_AREA_PIF_0_WR_ENA_W<CORE_1_MONTR_ENA_SPEC> {
+        CORE_1_AREA_PIF_0_WR_ENA_W::new(self, 5)
+    }
+    #[doc = "Bit 6 - Core1 PIF area1 read monitor enable"]
+    #[inline(always)]
+    pub fn core_1_area_pif_1_rd_ena(
+        &mut self,
+    ) -> CORE_1_AREA_PIF_1_RD_ENA_W<CORE_1_MONTR_ENA_SPEC> {
+        CORE_1_AREA_PIF_1_RD_ENA_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - Core1 PIF area1 write monitor enable"]
+    #[inline(always)]
+    pub fn core_1_area_pif_1_wr_ena(
+        &mut self,
+    ) -> CORE_1_AREA_PIF_1_WR_ENA_W<CORE_1_MONTR_ENA_SPEC> {
+        CORE_1_AREA_PIF_1_WR_ENA_W::new(self, 7)
+    }
+    #[doc = "Bit 8 - Core1 stackpoint overflow monitor enable"]
+    #[inline(always)]
+    pub fn core_1_sp_spill_min_ena(&mut self) -> CORE_1_SP_SPILL_MIN_ENA_W<CORE_1_MONTR_ENA_SPEC> {
+        CORE_1_SP_SPILL_MIN_ENA_W::new(self, 8)
+    }
+    #[doc = "Bit 9 - Core1 stackpoint underflow monitor enable"]
+    #[inline(always)]
+    pub fn core_1_sp_spill_max_ena(&mut self) -> CORE_1_SP_SPILL_MAX_ENA_W<CORE_1_MONTR_ENA_SPEC> {
+        CORE_1_SP_SPILL_MAX_ENA_W::new(self, 9)
+    }
+    #[doc = "Bit 10 - IBUS busy monitor enable"]
+    #[inline(always)]
+    pub fn core_1_iram0_exception_monitor_ena(
+        &mut self,
+    ) -> CORE_1_IRAM0_EXCEPTION_MONITOR_ENA_W<CORE_1_MONTR_ENA_SPEC> {
+        CORE_1_IRAM0_EXCEPTION_MONITOR_ENA_W::new(self, 10)
+    }
+    #[doc = "Bit 11 - DBUS busy monitor enbale"]
+    #[inline(always)]
+    pub fn core_1_dram0_exception_monitor_ena(
+        &mut self,
+    ) -> CORE_1_DRAM0_EXCEPTION_MONITOR_ENA_W<CORE_1_MONTR_ENA_SPEC> {
+        CORE_1_DRAM0_EXCEPTION_MONITOR_ENA_W::new(self, 11)
+    }
+}
+#[doc = "Core1 monitor enable configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_montr_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_1_montr_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_1_MONTR_ENA_SPEC;
+impl crate::RegisterSpec for CORE_1_MONTR_ENA_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_1_montr_ena::R`](R) reader structure"]
+impl crate::Readable for CORE_1_MONTR_ENA_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`core_1_montr_ena::W`](W) writer structure"]
+impl crate::Writable for CORE_1_MONTR_ENA_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CORE_1_MONTR_ENA to value 0"]
+impl crate::Resettable for CORE_1_MONTR_ENA_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/core_1_rcd_pdebugdata.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `CORE_1_RCD_PDEBUGDATA` reader"]
+pub type R = crate::R<CORE_1_RCD_PDEBUGDATA_SPEC>;
+#[doc = "Field `CORE_1_RCD_PDEBUGDATA` reader - Core1_pdebugdata"]
+pub type CORE_1_RCD_PDEBUGDATA_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - Core1_pdebugdata"]
+    #[inline(always)]
+    pub fn core_1_rcd_pdebugdata(&self) -> CORE_1_RCD_PDEBUGDATA_R {
+        CORE_1_RCD_PDEBUGDATA_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_1_RCD_PDEBUGDATA")
+            .field("core_1_rcd_pdebugdata", &self.core_1_rcd_pdebugdata())
+            .finish()
+    }
+}
+#[doc = "Core1 pdebug status register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_rcd_pdebugdata::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_1_RCD_PDEBUGDATA_SPEC;
+impl crate::RegisterSpec for CORE_1_RCD_PDEBUGDATA_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_1_rcd_pdebugdata::R`](R) reader structure"]
+impl crate::Readable for CORE_1_RCD_PDEBUGDATA_SPEC {}
+#[doc = "`reset()` method sets CORE_1_RCD_PDEBUGDATA to value 0"]
+impl crate::Resettable for CORE_1_RCD_PDEBUGDATA_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/core_1_rcd_pdebugenable.rs

@@ -0,0 +1,49 @@
+#[doc = "Register `CORE_1_RCD_PDEBUGENABLE` reader"]
+pub type R = crate::R<CORE_1_RCD_PDEBUGENABLE_SPEC>;
+#[doc = "Register `CORE_1_RCD_PDEBUGENABLE` writer"]
+pub type W = crate::W<CORE_1_RCD_PDEBUGENABLE_SPEC>;
+#[doc = "Field `CORE_1_RCD_PDEBUGENABLE` reader - Core1 Pdebugenable,set 1 to open Core1 Pdebug interface, then can get Core1 PC"]
+pub type CORE_1_RCD_PDEBUGENABLE_R = crate::BitReader;
+#[doc = "Field `CORE_1_RCD_PDEBUGENABLE` writer - Core1 Pdebugenable,set 1 to open Core1 Pdebug interface, then can get Core1 PC"]
+pub type CORE_1_RCD_PDEBUGENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Core1 Pdebugenable,set 1 to open Core1 Pdebug interface, then can get Core1 PC"]
+    #[inline(always)]
+    pub fn core_1_rcd_pdebugenable(&self) -> CORE_1_RCD_PDEBUGENABLE_R {
+        CORE_1_RCD_PDEBUGENABLE_R::new((self.bits & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_1_RCD_PDEBUGENABLE")
+            .field("core_1_rcd_pdebugenable", &self.core_1_rcd_pdebugenable())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Core1 Pdebugenable,set 1 to open Core1 Pdebug interface, then can get Core1 PC"]
+    #[inline(always)]
+    pub fn core_1_rcd_pdebugenable(
+        &mut self,
+    ) -> CORE_1_RCD_PDEBUGENABLE_W<CORE_1_RCD_PDEBUGENABLE_SPEC> {
+        CORE_1_RCD_PDEBUGENABLE_W::new(self, 0)
+    }
+}
+#[doc = "Core1 pdebug configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_rcd_pdebugenable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_1_rcd_pdebugenable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_1_RCD_PDEBUGENABLE_SPEC;
+impl crate::RegisterSpec for CORE_1_RCD_PDEBUGENABLE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_1_rcd_pdebugenable::R`](R) reader structure"]
+impl crate::Readable for CORE_1_RCD_PDEBUGENABLE_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`core_1_rcd_pdebugenable::W`](W) writer structure"]
+impl crate::Writable for CORE_1_RCD_PDEBUGENABLE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CORE_1_RCD_PDEBUGENABLE to value 0"]
+impl crate::Resettable for CORE_1_RCD_PDEBUGENABLE_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/core_1_rcd_pdebuginst.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `CORE_1_RCD_PDEBUGINST` reader"]
+pub type R = crate::R<CORE_1_RCD_PDEBUGINST_SPEC>;
+#[doc = "Field `CORE_1_RCD_PDEBUGINST` reader - Core1 pdebuginst"]
+pub type CORE_1_RCD_PDEBUGINST_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - Core1 pdebuginst"]
+    #[inline(always)]
+    pub fn core_1_rcd_pdebuginst(&self) -> CORE_1_RCD_PDEBUGINST_R {
+        CORE_1_RCD_PDEBUGINST_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_1_RCD_PDEBUGINST")
+            .field("core_1_rcd_pdebuginst", &self.core_1_rcd_pdebuginst())
+            .finish()
+    }
+}
+#[doc = "Core1 pdebug status register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_rcd_pdebuginst::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_1_RCD_PDEBUGINST_SPEC;
+impl crate::RegisterSpec for CORE_1_RCD_PDEBUGINST_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_1_rcd_pdebuginst::R`](R) reader structure"]
+impl crate::Readable for CORE_1_RCD_PDEBUGINST_SPEC {}
+#[doc = "`reset()` method sets CORE_1_RCD_PDEBUGINST to value 0"]
+impl crate::Resettable for CORE_1_RCD_PDEBUGINST_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/core_1_rcd_pdebugls0addr.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `CORE_1_RCD_PDEBUGLS0ADDR` reader"]
+pub type R = crate::R<CORE_1_RCD_PDEBUGLS0ADDR_SPEC>;
+#[doc = "Field `CORE_1_RCD_PDEBUGLS0ADDR` reader - Core1_pdebug_s0addr"]
+pub type CORE_1_RCD_PDEBUGLS0ADDR_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - Core1_pdebug_s0addr"]
+    #[inline(always)]
+    pub fn core_1_rcd_pdebugls0addr(&self) -> CORE_1_RCD_PDEBUGLS0ADDR_R {
+        CORE_1_RCD_PDEBUGLS0ADDR_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_1_RCD_PDEBUGLS0ADDR")
+            .field("core_1_rcd_pdebugls0addr", &self.core_1_rcd_pdebugls0addr())
+            .finish()
+    }
+}
+#[doc = "Core1 pdebug status register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_rcd_pdebugls0addr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_1_RCD_PDEBUGLS0ADDR_SPEC;
+impl crate::RegisterSpec for CORE_1_RCD_PDEBUGLS0ADDR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_1_rcd_pdebugls0addr::R`](R) reader structure"]
+impl crate::Readable for CORE_1_RCD_PDEBUGLS0ADDR_SPEC {}
+#[doc = "`reset()` method sets CORE_1_RCD_PDEBUGLS0ADDR to value 0"]
+impl crate::Resettable for CORE_1_RCD_PDEBUGLS0ADDR_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/core_1_rcd_pdebugls0data.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `CORE_1_RCD_PDEBUGLS0DATA` reader"]
+pub type R = crate::R<CORE_1_RCD_PDEBUGLS0DATA_SPEC>;
+#[doc = "Field `CORE_1_RCD_PDEBUGLS0DATA` reader - Core1_pdebug_s0data"]
+pub type CORE_1_RCD_PDEBUGLS0DATA_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - Core1_pdebug_s0data"]
+    #[inline(always)]
+    pub fn core_1_rcd_pdebugls0data(&self) -> CORE_1_RCD_PDEBUGLS0DATA_R {
+        CORE_1_RCD_PDEBUGLS0DATA_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_1_RCD_PDEBUGLS0DATA")
+            .field("core_1_rcd_pdebugls0data", &self.core_1_rcd_pdebugls0data())
+            .finish()
+    }
+}
+#[doc = "Core1 pdebug status register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_rcd_pdebugls0data::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_1_RCD_PDEBUGLS0DATA_SPEC;
+impl crate::RegisterSpec for CORE_1_RCD_PDEBUGLS0DATA_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_1_rcd_pdebugls0data::R`](R) reader structure"]
+impl crate::Readable for CORE_1_RCD_PDEBUGLS0DATA_SPEC {}
+#[doc = "`reset()` method sets CORE_1_RCD_PDEBUGLS0DATA to value 0"]
+impl crate::Resettable for CORE_1_RCD_PDEBUGLS0DATA_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/core_1_rcd_pdebugls0stat.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `CORE_1_RCD_PDEBUGLS0STAT` reader"]
+pub type R = crate::R<CORE_1_RCD_PDEBUGLS0STAT_SPEC>;
+#[doc = "Field `CORE_1_RCD_PDEBUGLS0STAT` reader - Core1_pdebug_s0stat"]
+pub type CORE_1_RCD_PDEBUGLS0STAT_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - Core1_pdebug_s0stat"]
+    #[inline(always)]
+    pub fn core_1_rcd_pdebugls0stat(&self) -> CORE_1_RCD_PDEBUGLS0STAT_R {
+        CORE_1_RCD_PDEBUGLS0STAT_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_1_RCD_PDEBUGLS0STAT")
+            .field("core_1_rcd_pdebugls0stat", &self.core_1_rcd_pdebugls0stat())
+            .finish()
+    }
+}
+#[doc = "Core1 pdebug status register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_rcd_pdebugls0stat::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_1_RCD_PDEBUGLS0STAT_SPEC;
+impl crate::RegisterSpec for CORE_1_RCD_PDEBUGLS0STAT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_1_rcd_pdebugls0stat::R`](R) reader structure"]
+impl crate::Readable for CORE_1_RCD_PDEBUGLS0STAT_SPEC {}
+#[doc = "`reset()` method sets CORE_1_RCD_PDEBUGLS0STAT to value 0"]
+impl crate::Resettable for CORE_1_RCD_PDEBUGLS0STAT_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/core_1_rcd_pdebugpc.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `CORE_1_RCD_PDEBUGPC` reader"]
+pub type R = crate::R<CORE_1_RCD_PDEBUGPC_SPEC>;
+#[doc = "Field `CORE_1_RCD_PDEBUGPC` reader - Core1_pdebugPC"]
+pub type CORE_1_RCD_PDEBUGPC_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - Core1_pdebugPC"]
+    #[inline(always)]
+    pub fn core_1_rcd_pdebugpc(&self) -> CORE_1_RCD_PDEBUGPC_R {
+        CORE_1_RCD_PDEBUGPC_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_1_RCD_PDEBUGPC")
+            .field("core_1_rcd_pdebugpc", &self.core_1_rcd_pdebugpc())
+            .finish()
+    }
+}
+#[doc = "Core1 pdebug status register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_rcd_pdebugpc::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_1_RCD_PDEBUGPC_SPEC;
+impl crate::RegisterSpec for CORE_1_RCD_PDEBUGPC_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_1_rcd_pdebugpc::R`](R) reader structure"]
+impl crate::Readable for CORE_1_RCD_PDEBUGPC_SPEC {}
+#[doc = "`reset()` method sets CORE_1_RCD_PDEBUGPC to value 0"]
+impl crate::Resettable for CORE_1_RCD_PDEBUGPC_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/core_1_rcd_pdebugstatus.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `CORE_1_RCD_PDEBUGSTATUS` reader"]
+pub type R = crate::R<CORE_1_RCD_PDEBUGSTATUS_SPEC>;
+#[doc = "Field `CORE_1_RCD_PDEBUGSTATUS` reader - Core1 pdebugstatus"]
+pub type CORE_1_RCD_PDEBUGSTATUS_R = crate::FieldReader;
+impl R {
+    #[doc = "Bits 0:7 - Core1 pdebugstatus"]
+    #[inline(always)]
+    pub fn core_1_rcd_pdebugstatus(&self) -> CORE_1_RCD_PDEBUGSTATUS_R {
+        CORE_1_RCD_PDEBUGSTATUS_R::new((self.bits & 0xff) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_1_RCD_PDEBUGSTATUS")
+            .field("core_1_rcd_pdebugstatus", &self.core_1_rcd_pdebugstatus())
+            .finish()
+    }
+}
+#[doc = "Core1 pdebug status register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_rcd_pdebugstatus::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_1_RCD_PDEBUGSTATUS_SPEC;
+impl crate::RegisterSpec for CORE_1_RCD_PDEBUGSTATUS_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_1_rcd_pdebugstatus::R`](R) reader structure"]
+impl crate::Readable for CORE_1_RCD_PDEBUGSTATUS_SPEC {}
+#[doc = "`reset()` method sets CORE_1_RCD_PDEBUGSTATUS to value 0"]
+impl crate::Resettable for CORE_1_RCD_PDEBUGSTATUS_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/core_1_rcd_recording.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `CORE_1_RCD_RECORDING` reader"]
+pub type R = crate::R<CORE_1_RCD_RECORDING_SPEC>;
+#[doc = "Register `CORE_1_RCD_RECORDING` writer"]
+pub type W = crate::W<CORE_1_RCD_RECORDING_SPEC>;
+#[doc = "Field `CORE_1_RCD_RECORDING` reader - Pdebug record enable,set 1 to record Core1 pdebug interface signal"]
+pub type CORE_1_RCD_RECORDING_R = crate::BitReader;
+#[doc = "Field `CORE_1_RCD_RECORDING` writer - Pdebug record enable,set 1 to record Core1 pdebug interface signal"]
+pub type CORE_1_RCD_RECORDING_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Pdebug record enable,set 1 to record Core1 pdebug interface signal"]
+    #[inline(always)]
+    pub fn core_1_rcd_recording(&self) -> CORE_1_RCD_RECORDING_R {
+        CORE_1_RCD_RECORDING_R::new((self.bits & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_1_RCD_RECORDING")
+            .field("core_1_rcd_recording", &self.core_1_rcd_recording())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Pdebug record enable,set 1 to record Core1 pdebug interface signal"]
+    #[inline(always)]
+    pub fn core_1_rcd_recording(&mut self) -> CORE_1_RCD_RECORDING_W<CORE_1_RCD_RECORDING_SPEC> {
+        CORE_1_RCD_RECORDING_W::new(self, 0)
+    }
+}
+#[doc = "Core1 pdebug status register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_rcd_recording::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_1_rcd_recording::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_1_RCD_RECORDING_SPEC;
+impl crate::RegisterSpec for CORE_1_RCD_RECORDING_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_1_rcd_recording::R`](R) reader structure"]
+impl crate::Readable for CORE_1_RCD_RECORDING_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`core_1_rcd_recording::W`](W) writer structure"]
+impl crate::Writable for CORE_1_RCD_RECORDING_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CORE_1_RCD_RECORDING to value 0"]
+impl crate::Resettable for CORE_1_RCD_RECORDING_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/core_1_rcd_sp.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `CORE_1_RCD_SP` reader"]
+pub type R = crate::R<CORE_1_RCD_SP_SPEC>;
+#[doc = "Field `CORE_1_RCD_SP` reader - Core1_stack pointer"]
+pub type CORE_1_RCD_SP_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - Core1_stack pointer"]
+    #[inline(always)]
+    pub fn core_1_rcd_sp(&self) -> CORE_1_RCD_SP_R {
+        CORE_1_RCD_SP_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_1_RCD_SP")
+            .field("core_1_rcd_sp", &self.core_1_rcd_sp())
+            .finish()
+    }
+}
+#[doc = "Core1 pdebug status register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_rcd_sp::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_1_RCD_SP_SPEC;
+impl crate::RegisterSpec for CORE_1_RCD_SP_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_1_rcd_sp::R`](R) reader structure"]
+impl crate::Readable for CORE_1_RCD_SP_SPEC {}
+#[doc = "`reset()` method sets CORE_1_RCD_SP to value 0"]
+impl crate::Resettable for CORE_1_RCD_SP_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/core_1_sp_max.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `CORE_1_SP_MAX` reader"]
+pub type R = crate::R<CORE_1_SP_MAX_SPEC>;
+#[doc = "Register `CORE_1_SP_MAX` writer"]
+pub type W = crate::W<CORE_1_SP_MAX_SPEC>;
+#[doc = "Field `CORE_1_SP_MAX` reader - stack max value"]
+pub type CORE_1_SP_MAX_R = crate::FieldReader<u32>;
+#[doc = "Field `CORE_1_SP_MAX` writer - stack max value"]
+pub type CORE_1_SP_MAX_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - stack max value"]
+    #[inline(always)]
+    pub fn core_1_sp_max(&self) -> CORE_1_SP_MAX_R {
+        CORE_1_SP_MAX_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_1_SP_MAX")
+            .field("core_1_sp_max", &self.core_1_sp_max())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - stack max value"]
+    #[inline(always)]
+    pub fn core_1_sp_max(&mut self) -> CORE_1_SP_MAX_W<CORE_1_SP_MAX_SPEC> {
+        CORE_1_SP_MAX_W::new(self, 0)
+    }
+}
+#[doc = "Core1 sp region configuration regsiter\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_sp_max::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_1_sp_max::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_1_SP_MAX_SPEC;
+impl crate::RegisterSpec for CORE_1_SP_MAX_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_1_sp_max::R`](R) reader structure"]
+impl crate::Readable for CORE_1_SP_MAX_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`core_1_sp_max::W`](W) writer structure"]
+impl crate::Writable for CORE_1_SP_MAX_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CORE_1_SP_MAX to value 0xffff_ffff"]
+impl crate::Resettable for CORE_1_SP_MAX_SPEC {
+    const RESET_VALUE: u32 = 0xffff_ffff;
+}

vendor/esp32s3/src/assist_debug/core_1_sp_min.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `CORE_1_SP_MIN` reader"]
+pub type R = crate::R<CORE_1_SP_MIN_SPEC>;
+#[doc = "Register `CORE_1_SP_MIN` writer"]
+pub type W = crate::W<CORE_1_SP_MIN_SPEC>;
+#[doc = "Field `CORE_1_SP_MIN` reader - stack min value"]
+pub type CORE_1_SP_MIN_R = crate::FieldReader<u32>;
+#[doc = "Field `CORE_1_SP_MIN` writer - stack min value"]
+pub type CORE_1_SP_MIN_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - stack min value"]
+    #[inline(always)]
+    pub fn core_1_sp_min(&self) -> CORE_1_SP_MIN_R {
+        CORE_1_SP_MIN_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_1_SP_MIN")
+            .field("core_1_sp_min", &self.core_1_sp_min())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - stack min value"]
+    #[inline(always)]
+    pub fn core_1_sp_min(&mut self) -> CORE_1_SP_MIN_W<CORE_1_SP_MIN_SPEC> {
+        CORE_1_SP_MIN_W::new(self, 0)
+    }
+}
+#[doc = "Core1 sp region configuration regsiter\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_sp_min::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_1_sp_min::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_1_SP_MIN_SPEC;
+impl crate::RegisterSpec for CORE_1_SP_MIN_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_1_sp_min::R`](R) reader structure"]
+impl crate::Readable for CORE_1_SP_MIN_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`core_1_sp_min::W`](W) writer structure"]
+impl crate::Writable for CORE_1_SP_MIN_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CORE_1_SP_MIN to value 0"]
+impl crate::Resettable for CORE_1_SP_MIN_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/core_1_sp_pc.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `CORE_1_SP_PC` reader"]
+pub type R = crate::R<CORE_1_SP_PC_SPEC>;
+#[doc = "Field `CORE_1_SP_PC` reader - the PC when first touch stack monitor interrupt"]
+pub type CORE_1_SP_PC_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - the PC when first touch stack monitor interrupt"]
+    #[inline(always)]
+    pub fn core_1_sp_pc(&self) -> CORE_1_SP_PC_R {
+        CORE_1_SP_PC_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_1_SP_PC")
+            .field("core_1_sp_pc", &self.core_1_sp_pc())
+            .finish()
+    }
+}
+#[doc = "Core1 sp pc status register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_sp_pc::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_1_SP_PC_SPEC;
+impl crate::RegisterSpec for CORE_1_SP_PC_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_1_sp_pc::R`](R) reader structure"]
+impl crate::Readable for CORE_1_SP_PC_SPEC {}
+#[doc = "`reset()` method sets CORE_1_SP_PC to value 0"]
+impl crate::Resettable for CORE_1_SP_PC_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/core_1_sp_unstable.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `CORE_1_SP_UNSTABLE` reader"]
+pub type R = crate::R<CORE_1_SP_UNSTABLE_SPEC>;
+#[doc = "Register `CORE_1_SP_UNSTABLE` writer"]
+pub type W = crate::W<CORE_1_SP_UNSTABLE_SPEC>;
+#[doc = "Field `CORE_1_SP_UNSTABLE` reader - unstable period when window change,during this period no check stackpointer"]
+pub type CORE_1_SP_UNSTABLE_R = crate::FieldReader;
+#[doc = "Field `CORE_1_SP_UNSTABLE` writer - unstable period when window change,during this period no check stackpointer"]
+pub type CORE_1_SP_UNSTABLE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+impl R {
+    #[doc = "Bits 0:7 - unstable period when window change,during this period no check stackpointer"]
+    #[inline(always)]
+    pub fn core_1_sp_unstable(&self) -> CORE_1_SP_UNSTABLE_R {
+        CORE_1_SP_UNSTABLE_R::new((self.bits & 0xff) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_1_SP_UNSTABLE")
+            .field("core_1_sp_unstable", &self.core_1_sp_unstable())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - unstable period when window change,during this period no check stackpointer"]
+    #[inline(always)]
+    pub fn core_1_sp_unstable(&mut self) -> CORE_1_SP_UNSTABLE_W<CORE_1_SP_UNSTABLE_SPEC> {
+        CORE_1_SP_UNSTABLE_W::new(self, 0)
+    }
+}
+#[doc = "Core1 sp unstable configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_sp_unstable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_1_sp_unstable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_1_SP_UNSTABLE_SPEC;
+impl crate::RegisterSpec for CORE_1_SP_UNSTABLE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_1_sp_unstable::R`](R) reader structure"]
+impl crate::Readable for CORE_1_SP_UNSTABLE_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`core_1_sp_unstable::W`](W) writer structure"]
+impl crate::Writable for CORE_1_SP_UNSTABLE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CORE_1_SP_UNSTABLE to value 0x0b"]
+impl crate::Resettable for CORE_1_SP_UNSTABLE_SPEC {
+    const RESET_VALUE: u32 = 0x0b;
+}

vendor/esp32s3/src/assist_debug/core_x_iram0_dram0_exception_monitor_0.rs

@@ -0,0 +1,52 @@
+#[doc = "Register `CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0` reader"]
+pub type R = crate::R<CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_SPEC>;
+#[doc = "Register `CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0` writer"]
+pub type W = crate::W<CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_SPEC>;
+#[doc = "Field `CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0` reader - busy monitor window cycle"]
+pub type CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_R = crate::FieldReader<u32>;
+#[doc = "Field `CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0` writer - busy monitor window cycle"]
+pub type CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>;
+impl R {
+    #[doc = "Bits 0:19 - busy monitor window cycle"]
+    #[inline(always)]
+    pub fn core_x_iram0_dram0_limit_cycle_0(&self) -> CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_R {
+        CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_R::new(self.bits & 0x000f_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0")
+            .field(
+                "core_x_iram0_dram0_limit_cycle_0",
+                &self.core_x_iram0_dram0_limit_cycle_0(),
+            )
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:19 - busy monitor window cycle"]
+    #[inline(always)]
+    pub fn core_x_iram0_dram0_limit_cycle_0(
+        &mut self,
+    ) -> CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_W<CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_SPEC> {
+        CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_W::new(self, 0)
+    }
+}
+#[doc = "bus busy configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_x_iram0_dram0_exception_monitor_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_x_iram0_dram0_exception_monitor_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_SPEC;
+impl crate::RegisterSpec for CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_x_iram0_dram0_exception_monitor_0::R`](R) reader structure"]
+impl crate::Readable for CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`core_x_iram0_dram0_exception_monitor_0::W`](W) writer structure"]
+impl crate::Writable for CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0 to value 0x000f_ffff"]
+impl crate::Resettable for CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_SPEC {
+    const RESET_VALUE: u32 = 0x000f_ffff;
+}

vendor/esp32s3/src/assist_debug/core_x_iram0_dram0_exception_monitor_1.rs

@@ -0,0 +1,52 @@
+#[doc = "Register `CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1` reader"]
+pub type R = crate::R<CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_SPEC>;
+#[doc = "Register `CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1` writer"]
+pub type W = crate::W<CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_SPEC>;
+#[doc = "Field `CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1` reader - non busy cycle,for example: when cycle=100 and cycle=10,it means that in 100 cycle, if busy access success time less than 10, it will trigger interrutpt"]
+pub type CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_R = crate::FieldReader<u32>;
+#[doc = "Field `CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1` writer - non busy cycle,for example: when cycle=100 and cycle=10,it means that in 100 cycle, if busy access success time less than 10, it will trigger interrutpt"]
+pub type CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>;
+impl R {
+    #[doc = "Bits 0:19 - non busy cycle,for example: when cycle=100 and cycle=10,it means that in 100 cycle, if busy access success time less than 10, it will trigger interrutpt"]
+    #[inline(always)]
+    pub fn core_x_iram0_dram0_limit_cycle_1(&self) -> CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_R {
+        CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_R::new(self.bits & 0x000f_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1")
+            .field(
+                "core_x_iram0_dram0_limit_cycle_1",
+                &self.core_x_iram0_dram0_limit_cycle_1(),
+            )
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:19 - non busy cycle,for example: when cycle=100 and cycle=10,it means that in 100 cycle, if busy access success time less than 10, it will trigger interrutpt"]
+    #[inline(always)]
+    pub fn core_x_iram0_dram0_limit_cycle_1(
+        &mut self,
+    ) -> CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_W<CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_SPEC> {
+        CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_W::new(self, 0)
+    }
+}
+#[doc = "bus busy configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_x_iram0_dram0_exception_monitor_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_x_iram0_dram0_exception_monitor_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_SPEC;
+impl crate::RegisterSpec for CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`core_x_iram0_dram0_exception_monitor_1::R`](R) reader structure"]
+impl crate::Readable for CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`core_x_iram0_dram0_exception_monitor_1::W`](W) writer structure"]
+impl crate::Writable for CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1 to value 0x000f_ffff"]
+impl crate::Resettable for CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_SPEC {
+    const RESET_VALUE: u32 = 0x000f_ffff;
+}

vendor/esp32s3/src/assist_debug/date.rs

@@ -0,0 +1,45 @@
+#[doc = "Register `DATE` reader"]
+pub type R = crate::R<DATE_SPEC>;
+#[doc = "Register `DATE` writer"]
+pub type W = crate::W<DATE_SPEC>;
+#[doc = "Field `DATE` reader - version register"]
+pub type DATE_R = crate::FieldReader<u32>;
+#[doc = "Field `DATE` writer - version register"]
+pub type DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>;
+impl R {
+    #[doc = "Bits 0:27 - version register"]
+    #[inline(always)]
+    pub fn date(&self) -> DATE_R {
+        DATE_R::new(self.bits & 0x0fff_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DATE").field("date", &self.date()).finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:27 - version register"]
+    #[inline(always)]
+    pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
+        DATE_W::new(self, 0)
+    }
+}
+#[doc = "version register\n\nYou can [`read`](crate::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DATE_SPEC;
+impl crate::RegisterSpec for DATE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`date::R`](R) reader structure"]
+impl crate::Readable for DATE_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"]
+impl crate::Writable for DATE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DATE to value 0x0200_3040"]
+impl crate::Resettable for DATE_SPEC {
+    const RESET_VALUE: u32 = 0x0200_3040;
+}

vendor/esp32s3/src/assist_debug/log_data_0.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `LOG_DATA_0` reader"]
+pub type R = crate::R<LOG_DATA_0_SPEC>;
+#[doc = "Register `LOG_DATA_0` writer"]
+pub type W = crate::W<LOG_DATA_0_SPEC>;
+#[doc = "Field `LOG_DATA_0` reader - check data0"]
+pub type LOG_DATA_0_R = crate::FieldReader<u32>;
+#[doc = "Field `LOG_DATA_0` writer - check data0"]
+pub type LOG_DATA_0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - check data0"]
+    #[inline(always)]
+    pub fn log_data_0(&self) -> LOG_DATA_0_R {
+        LOG_DATA_0_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("LOG_DATA_0")
+            .field("log_data_0", &self.log_data_0())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - check data0"]
+    #[inline(always)]
+    pub fn log_data_0(&mut self) -> LOG_DATA_0_W<LOG_DATA_0_SPEC> {
+        LOG_DATA_0_W::new(self, 0)
+    }
+}
+#[doc = "log check data register\n\nYou can [`read`](crate::Reg::read) this register and get [`log_data_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`log_data_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct LOG_DATA_0_SPEC;
+impl crate::RegisterSpec for LOG_DATA_0_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`log_data_0::R`](R) reader structure"]
+impl crate::Readable for LOG_DATA_0_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`log_data_0::W`](W) writer structure"]
+impl crate::Writable for LOG_DATA_0_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets LOG_DATA_0 to value 0"]
+impl crate::Resettable for LOG_DATA_0_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/log_data_1.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `LOG_DATA_1` reader"]
+pub type R = crate::R<LOG_DATA_1_SPEC>;
+#[doc = "Register `LOG_DATA_1` writer"]
+pub type W = crate::W<LOG_DATA_1_SPEC>;
+#[doc = "Field `LOG_DATA_1` reader - check data1"]
+pub type LOG_DATA_1_R = crate::FieldReader<u32>;
+#[doc = "Field `LOG_DATA_1` writer - check data1"]
+pub type LOG_DATA_1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - check data1"]
+    #[inline(always)]
+    pub fn log_data_1(&self) -> LOG_DATA_1_R {
+        LOG_DATA_1_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("LOG_DATA_1")
+            .field("log_data_1", &self.log_data_1())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - check data1"]
+    #[inline(always)]
+    pub fn log_data_1(&mut self) -> LOG_DATA_1_W<LOG_DATA_1_SPEC> {
+        LOG_DATA_1_W::new(self, 0)
+    }
+}
+#[doc = "log check data register\n\nYou can [`read`](crate::Reg::read) this register and get [`log_data_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`log_data_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct LOG_DATA_1_SPEC;
+impl crate::RegisterSpec for LOG_DATA_1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`log_data_1::R`](R) reader structure"]
+impl crate::Readable for LOG_DATA_1_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`log_data_1::W`](W) writer structure"]
+impl crate::Writable for LOG_DATA_1_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets LOG_DATA_1 to value 0"]
+impl crate::Resettable for LOG_DATA_1_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/log_data_2.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `LOG_DATA_2` reader"]
+pub type R = crate::R<LOG_DATA_2_SPEC>;
+#[doc = "Register `LOG_DATA_2` writer"]
+pub type W = crate::W<LOG_DATA_2_SPEC>;
+#[doc = "Field `LOG_DATA_2` reader - check data2"]
+pub type LOG_DATA_2_R = crate::FieldReader<u32>;
+#[doc = "Field `LOG_DATA_2` writer - check data2"]
+pub type LOG_DATA_2_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - check data2"]
+    #[inline(always)]
+    pub fn log_data_2(&self) -> LOG_DATA_2_R {
+        LOG_DATA_2_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("LOG_DATA_2")
+            .field("log_data_2", &self.log_data_2())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - check data2"]
+    #[inline(always)]
+    pub fn log_data_2(&mut self) -> LOG_DATA_2_W<LOG_DATA_2_SPEC> {
+        LOG_DATA_2_W::new(self, 0)
+    }
+}
+#[doc = "log check data register\n\nYou can [`read`](crate::Reg::read) this register and get [`log_data_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`log_data_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct LOG_DATA_2_SPEC;
+impl crate::RegisterSpec for LOG_DATA_2_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`log_data_2::R`](R) reader structure"]
+impl crate::Readable for LOG_DATA_2_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`log_data_2::W`](W) writer structure"]
+impl crate::Writable for LOG_DATA_2_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets LOG_DATA_2 to value 0"]
+impl crate::Resettable for LOG_DATA_2_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/log_data_3.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `LOG_DATA_3` reader"]
+pub type R = crate::R<LOG_DATA_3_SPEC>;
+#[doc = "Register `LOG_DATA_3` writer"]
+pub type W = crate::W<LOG_DATA_3_SPEC>;
+#[doc = "Field `LOG_DATA_3` reader - check data3"]
+pub type LOG_DATA_3_R = crate::FieldReader<u32>;
+#[doc = "Field `LOG_DATA_3` writer - check data3"]
+pub type LOG_DATA_3_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - check data3"]
+    #[inline(always)]
+    pub fn log_data_3(&self) -> LOG_DATA_3_R {
+        LOG_DATA_3_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("LOG_DATA_3")
+            .field("log_data_3", &self.log_data_3())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - check data3"]
+    #[inline(always)]
+    pub fn log_data_3(&mut self) -> LOG_DATA_3_W<LOG_DATA_3_SPEC> {
+        LOG_DATA_3_W::new(self, 0)
+    }
+}
+#[doc = "log check data register\n\nYou can [`read`](crate::Reg::read) this register and get [`log_data_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`log_data_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct LOG_DATA_3_SPEC;
+impl crate::RegisterSpec for LOG_DATA_3_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`log_data_3::R`](R) reader structure"]
+impl crate::Readable for LOG_DATA_3_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`log_data_3::W`](W) writer structure"]
+impl crate::Writable for LOG_DATA_3_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets LOG_DATA_3 to value 0"]
+impl crate::Resettable for LOG_DATA_3_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/log_data_mask.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `LOG_DATA_MASK` reader"]
+pub type R = crate::R<LOG_DATA_MASK_SPEC>;
+#[doc = "Register `LOG_DATA_MASK` writer"]
+pub type W = crate::W<LOG_DATA_MASK_SPEC>;
+#[doc = "Field `LOG_DATA_SIZE` reader - data mask"]
+pub type LOG_DATA_SIZE_R = crate::FieldReader<u16>;
+#[doc = "Field `LOG_DATA_SIZE` writer - data mask"]
+pub type LOG_DATA_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
+impl R {
+    #[doc = "Bits 0:15 - data mask"]
+    #[inline(always)]
+    pub fn log_data_size(&self) -> LOG_DATA_SIZE_R {
+        LOG_DATA_SIZE_R::new((self.bits & 0xffff) as u16)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("LOG_DATA_MASK")
+            .field("log_data_size", &self.log_data_size())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:15 - data mask"]
+    #[inline(always)]
+    pub fn log_data_size(&mut self) -> LOG_DATA_SIZE_W<LOG_DATA_MASK_SPEC> {
+        LOG_DATA_SIZE_W::new(self, 0)
+    }
+}
+#[doc = "log check data mask register\n\nYou can [`read`](crate::Reg::read) this register and get [`log_data_mask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`log_data_mask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct LOG_DATA_MASK_SPEC;
+impl crate::RegisterSpec for LOG_DATA_MASK_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`log_data_mask::R`](R) reader structure"]
+impl crate::Readable for LOG_DATA_MASK_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`log_data_mask::W`](W) writer structure"]
+impl crate::Writable for LOG_DATA_MASK_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets LOG_DATA_MASK to value 0"]
+impl crate::Resettable for LOG_DATA_MASK_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/log_max.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `LOG_MAX` reader"]
+pub type R = crate::R<LOG_MAX_SPEC>;
+#[doc = "Register `LOG_MAX` writer"]
+pub type W = crate::W<LOG_MAX_SPEC>;
+#[doc = "Field `LOG_MAX` reader - check region max addr"]
+pub type LOG_MAX_R = crate::FieldReader<u32>;
+#[doc = "Field `LOG_MAX` writer - check region max addr"]
+pub type LOG_MAX_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - check region max addr"]
+    #[inline(always)]
+    pub fn log_max(&self) -> LOG_MAX_R {
+        LOG_MAX_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("LOG_MAX")
+            .field("log_max", &self.log_max())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - check region max addr"]
+    #[inline(always)]
+    pub fn log_max(&mut self) -> LOG_MAX_W<LOG_MAX_SPEC> {
+        LOG_MAX_W::new(self, 0)
+    }
+}
+#[doc = "log check region configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`log_max::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`log_max::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct LOG_MAX_SPEC;
+impl crate::RegisterSpec for LOG_MAX_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`log_max::R`](R) reader structure"]
+impl crate::Readable for LOG_MAX_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`log_max::W`](W) writer structure"]
+impl crate::Writable for LOG_MAX_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets LOG_MAX to value 0"]
+impl crate::Resettable for LOG_MAX_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/log_mem_end.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `LOG_MEM_END` reader"]
+pub type R = crate::R<LOG_MEM_END_SPEC>;
+#[doc = "Register `LOG_MEM_END` writer"]
+pub type W = crate::W<LOG_MEM_END_SPEC>;
+#[doc = "Field `LOG_MEM_END` reader - mem end addr"]
+pub type LOG_MEM_END_R = crate::FieldReader<u32>;
+#[doc = "Field `LOG_MEM_END` writer - mem end addr"]
+pub type LOG_MEM_END_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - mem end addr"]
+    #[inline(always)]
+    pub fn log_mem_end(&self) -> LOG_MEM_END_R {
+        LOG_MEM_END_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("LOG_MEM_END")
+            .field("log_mem_end", &self.log_mem_end())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - mem end addr"]
+    #[inline(always)]
+    pub fn log_mem_end(&mut self) -> LOG_MEM_END_W<LOG_MEM_END_SPEC> {
+        LOG_MEM_END_W::new(self, 0)
+    }
+}
+#[doc = "log mem region configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`log_mem_end::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`log_mem_end::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct LOG_MEM_END_SPEC;
+impl crate::RegisterSpec for LOG_MEM_END_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`log_mem_end::R`](R) reader structure"]
+impl crate::Readable for LOG_MEM_END_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`log_mem_end::W`](W) writer structure"]
+impl crate::Writable for LOG_MEM_END_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets LOG_MEM_END to value 0"]
+impl crate::Resettable for LOG_MEM_END_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/log_mem_full_flag.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `LOG_MEM_FULL_FLAG` reader"]
+pub type R = crate::R<LOG_MEM_FULL_FLAG_SPEC>;
+#[doc = "Register `LOG_MEM_FULL_FLAG` writer"]
+pub type W = crate::W<LOG_MEM_FULL_FLAG_SPEC>;
+#[doc = "Field `LOG_MEM_FULL_FLAG` reader - when it's 1,show that mem write loop morte than one time."]
+pub type LOG_MEM_FULL_FLAG_R = crate::BitReader;
+#[doc = "Field `LOG_MEM_FULL_FLAG` writer - when it's 1,show that mem write loop morte than one time."]
+pub type LOG_MEM_FULL_FLAG_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - when it's 1,show that mem write loop morte than one time."]
+    #[inline(always)]
+    pub fn log_mem_full_flag(&self) -> LOG_MEM_FULL_FLAG_R {
+        LOG_MEM_FULL_FLAG_R::new((self.bits & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("LOG_MEM_FULL_FLAG")
+            .field("log_mem_full_flag", &self.log_mem_full_flag())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - when it's 1,show that mem write loop morte than one time."]
+    #[inline(always)]
+    pub fn log_mem_full_flag(&mut self) -> LOG_MEM_FULL_FLAG_W<LOG_MEM_FULL_FLAG_SPEC> {
+        LOG_MEM_FULL_FLAG_W::new(self, 0)
+    }
+}
+#[doc = "log mem status register\n\nYou can [`read`](crate::Reg::read) this register and get [`log_mem_full_flag::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`log_mem_full_flag::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct LOG_MEM_FULL_FLAG_SPEC;
+impl crate::RegisterSpec for LOG_MEM_FULL_FLAG_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`log_mem_full_flag::R`](R) reader structure"]
+impl crate::Readable for LOG_MEM_FULL_FLAG_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`log_mem_full_flag::W`](W) writer structure"]
+impl crate::Writable for LOG_MEM_FULL_FLAG_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets LOG_MEM_FULL_FLAG to value 0"]
+impl crate::Resettable for LOG_MEM_FULL_FLAG_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/log_mem_start.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `LOG_MEM_START` reader"]
+pub type R = crate::R<LOG_MEM_START_SPEC>;
+#[doc = "Register `LOG_MEM_START` writer"]
+pub type W = crate::W<LOG_MEM_START_SPEC>;
+#[doc = "Field `LOG_MEM_START` reader - mem start addr"]
+pub type LOG_MEM_START_R = crate::FieldReader<u32>;
+#[doc = "Field `LOG_MEM_START` writer - mem start addr"]
+pub type LOG_MEM_START_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - mem start addr"]
+    #[inline(always)]
+    pub fn log_mem_start(&self) -> LOG_MEM_START_R {
+        LOG_MEM_START_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("LOG_MEM_START")
+            .field("log_mem_start", &self.log_mem_start())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - mem start addr"]
+    #[inline(always)]
+    pub fn log_mem_start(&mut self) -> LOG_MEM_START_W<LOG_MEM_START_SPEC> {
+        LOG_MEM_START_W::new(self, 0)
+    }
+}
+#[doc = "log mem region configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`log_mem_start::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`log_mem_start::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct LOG_MEM_START_SPEC;
+impl crate::RegisterSpec for LOG_MEM_START_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`log_mem_start::R`](R) reader structure"]
+impl crate::Readable for LOG_MEM_START_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`log_mem_start::W`](W) writer structure"]
+impl crate::Writable for LOG_MEM_START_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets LOG_MEM_START to value 0"]
+impl crate::Resettable for LOG_MEM_START_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/log_mem_writing_addr.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `LOG_MEM_WRITING_ADDR` reader"]
+pub type R = crate::R<LOG_MEM_WRITING_ADDR_SPEC>;
+#[doc = "Field `LOG_MEM_WRITING_ADDR` reader - mem current addr, it means next writing addr"]
+pub type LOG_MEM_WRITING_ADDR_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - mem current addr, it means next writing addr"]
+    #[inline(always)]
+    pub fn log_mem_writing_addr(&self) -> LOG_MEM_WRITING_ADDR_R {
+        LOG_MEM_WRITING_ADDR_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("LOG_MEM_WRITING_ADDR")
+            .field("log_mem_writing_addr", &self.log_mem_writing_addr())
+            .finish()
+    }
+}
+#[doc = "log mem addr status register\n\nYou can [`read`](crate::Reg::read) this register and get [`log_mem_writing_addr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct LOG_MEM_WRITING_ADDR_SPEC;
+impl crate::RegisterSpec for LOG_MEM_WRITING_ADDR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`log_mem_writing_addr::R`](R) reader structure"]
+impl crate::Readable for LOG_MEM_WRITING_ADDR_SPEC {}
+#[doc = "`reset()` method sets LOG_MEM_WRITING_ADDR to value 0"]
+impl crate::Resettable for LOG_MEM_WRITING_ADDR_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/log_min.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `LOG_MIN` reader"]
+pub type R = crate::R<LOG_MIN_SPEC>;
+#[doc = "Register `LOG_MIN` writer"]
+pub type W = crate::W<LOG_MIN_SPEC>;
+#[doc = "Field `LOG_MIN` reader - check region min addr"]
+pub type LOG_MIN_R = crate::FieldReader<u32>;
+#[doc = "Field `LOG_MIN` writer - check region min addr"]
+pub type LOG_MIN_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - check region min addr"]
+    #[inline(always)]
+    pub fn log_min(&self) -> LOG_MIN_R {
+        LOG_MIN_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("LOG_MIN")
+            .field("log_min", &self.log_min())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - check region min addr"]
+    #[inline(always)]
+    pub fn log_min(&mut self) -> LOG_MIN_W<LOG_MIN_SPEC> {
+        LOG_MIN_W::new(self, 0)
+    }
+}
+#[doc = "log check region configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`log_min::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`log_min::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct LOG_MIN_SPEC;
+impl crate::RegisterSpec for LOG_MIN_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`log_min::R`](R) reader structure"]
+impl crate::Readable for LOG_MIN_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`log_min::W`](W) writer structure"]
+impl crate::Writable for LOG_MIN_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets LOG_MIN to value 0"]
+impl crate::Resettable for LOG_MIN_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/assist_debug/log_setting.rs

@@ -0,0 +1,77 @@
+#[doc = "Register `LOG_SETTING` reader"]
+pub type R = crate::R<LOG_SETTING_SPEC>;
+#[doc = "Register `LOG_SETTING` writer"]
+pub type W = crate::W<LOG_SETTING_SPEC>;
+#[doc = "Field `LOG_ENA` reader - bus moniter enable: \\[0\\]Core1,\\[1\\]core1,\\[2\\]dma"]
+pub type LOG_ENA_R = crate::FieldReader;
+#[doc = "Field `LOG_ENA` writer - bus moniter enable: \\[0\\]Core1,\\[1\\]core1,\\[2\\]dma"]
+pub type LOG_ENA_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `LOG_MODE` reader - check_mode:0:write,1:word,2:halword,3:byte,4:doubleword,5:4word"]
+pub type LOG_MODE_R = crate::FieldReader;
+#[doc = "Field `LOG_MODE` writer - check_mode:0:write,1:word,2:halword,3:byte,4:doubleword,5:4word"]
+pub type LOG_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `LOG_MEM_LOOP_ENABLE` reader - mem_loop enable,1 means that loop write"]
+pub type LOG_MEM_LOOP_ENABLE_R = crate::BitReader;
+#[doc = "Field `LOG_MEM_LOOP_ENABLE` writer - mem_loop enable,1 means that loop write"]
+pub type LOG_MEM_LOOP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 0:2 - bus moniter enable: \\[0\\]Core1,\\[1\\]core1,\\[2\\]dma"]
+    #[inline(always)]
+    pub fn log_ena(&self) -> LOG_ENA_R {
+        LOG_ENA_R::new((self.bits & 7) as u8)
+    }
+    #[doc = "Bits 3:5 - check_mode:0:write,1:word,2:halword,3:byte,4:doubleword,5:4word"]
+    #[inline(always)]
+    pub fn log_mode(&self) -> LOG_MODE_R {
+        LOG_MODE_R::new(((self.bits >> 3) & 7) as u8)
+    }
+    #[doc = "Bit 6 - mem_loop enable,1 means that loop write"]
+    #[inline(always)]
+    pub fn log_mem_loop_enable(&self) -> LOG_MEM_LOOP_ENABLE_R {
+        LOG_MEM_LOOP_ENABLE_R::new(((self.bits >> 6) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("LOG_SETTING")
+            .field("log_ena", &self.log_ena())
+            .field("log_mode", &self.log_mode())
+            .field("log_mem_loop_enable", &self.log_mem_loop_enable())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:2 - bus moniter enable: \\[0\\]Core1,\\[1\\]core1,\\[2\\]dma"]
+    #[inline(always)]
+    pub fn log_ena(&mut self) -> LOG_ENA_W<LOG_SETTING_SPEC> {
+        LOG_ENA_W::new(self, 0)
+    }
+    #[doc = "Bits 3:5 - check_mode:0:write,1:word,2:halword,3:byte,4:doubleword,5:4word"]
+    #[inline(always)]
+    pub fn log_mode(&mut self) -> LOG_MODE_W<LOG_SETTING_SPEC> {
+        LOG_MODE_W::new(self, 3)
+    }
+    #[doc = "Bit 6 - mem_loop enable,1 means that loop write"]
+    #[inline(always)]
+    pub fn log_mem_loop_enable(&mut self) -> LOG_MEM_LOOP_ENABLE_W<LOG_SETTING_SPEC> {
+        LOG_MEM_LOOP_ENABLE_W::new(self, 6)
+    }
+}
+#[doc = "log set register\n\nYou can [`read`](crate::Reg::read) this register and get [`log_setting::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`log_setting::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct LOG_SETTING_SPEC;
+impl crate::RegisterSpec for LOG_SETTING_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`log_setting::R`](R) reader structure"]
+impl crate::Readable for LOG_SETTING_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`log_setting::W`](W) writer structure"]
+impl crate::Writable for LOG_SETTING_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets LOG_SETTING to value 0x40"]
+impl crate::Resettable for LOG_SETTING_SPEC {
+    const RESET_VALUE: u32 = 0x40;
+}