feat: add display UI with splash screen, dashboard, and RSSI sparkline

Implement full SSD1306 OLED display support:
- Splash screen on boot (1.5s) with project name, version, board
- Dashboard showing radio state, config, counters, RSSI/SNR
- RSSI history sparkline (64-sample ring buffer, 2px-wide bars)
- DisplayOn/DisplayOff host commands routed via dedicated channel
- Pure render functions against generic DrawTarget (no hardware coupling)
- Display on/off control bypasses radio task entirely

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>

vendor/esp32s3/src/dma/ahb_test.rs

@@ -0,0 +1,62 @@
+#[doc = "Register `AHB_TEST` reader"]
+pub type R = crate::R<AHB_TEST_SPEC>;
+#[doc = "Register `AHB_TEST` writer"]
+pub type W = crate::W<AHB_TEST_SPEC>;
+#[doc = "Field `AHB_TESTMODE` reader - reserved"]
+pub type AHB_TESTMODE_R = crate::FieldReader;
+#[doc = "Field `AHB_TESTMODE` writer - reserved"]
+pub type AHB_TESTMODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `AHB_TESTADDR` reader - reserved"]
+pub type AHB_TESTADDR_R = crate::FieldReader;
+#[doc = "Field `AHB_TESTADDR` writer - reserved"]
+pub type AHB_TESTADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+impl R {
+    #[doc = "Bits 0:2 - reserved"]
+    #[inline(always)]
+    pub fn ahb_testmode(&self) -> AHB_TESTMODE_R {
+        AHB_TESTMODE_R::new((self.bits & 7) as u8)
+    }
+    #[doc = "Bits 4:5 - reserved"]
+    #[inline(always)]
+    pub fn ahb_testaddr(&self) -> AHB_TESTADDR_R {
+        AHB_TESTADDR_R::new(((self.bits >> 4) & 3) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("AHB_TEST")
+            .field("ahb_testmode", &self.ahb_testmode())
+            .field("ahb_testaddr", &self.ahb_testaddr())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:2 - reserved"]
+    #[inline(always)]
+    pub fn ahb_testmode(&mut self) -> AHB_TESTMODE_W<AHB_TEST_SPEC> {
+        AHB_TESTMODE_W::new(self, 0)
+    }
+    #[doc = "Bits 4:5 - reserved"]
+    #[inline(always)]
+    pub fn ahb_testaddr(&mut self) -> AHB_TESTADDR_W<AHB_TEST_SPEC> {
+        AHB_TESTADDR_W::new(self, 4)
+    }
+}
+#[doc = "reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`ahb_test::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ahb_test::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct AHB_TEST_SPEC;
+impl crate::RegisterSpec for AHB_TEST_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`ahb_test::R`](R) reader structure"]
+impl crate::Readable for AHB_TEST_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`ahb_test::W`](W) writer structure"]
+impl crate::Writable for AHB_TEST_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets AHB_TEST to value 0"]
+impl crate::Resettable for AHB_TEST_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/dma/ch.rs

@@ -0,0 +1,313 @@
+#[repr(C)]
+#[cfg_attr(feature = "impl-register-debug", derive(Debug))]
+#[doc = "Cluster CH%s, containing IN_CONF0_CH?, IN_CONF1_CH?, IN_INT_RAW_CH?, IN_INT_ST_CH?, IN_INT_ENA_CH?, IN_INT_CLR_CH?, INFIFO_STATUS_CH?, IN_POP_CH?, IN_LINK_CH?, IN_STATE_CH?, IN_SUC_EOF_DES_ADDR_CH?, IN_ERR_EOF_DES_ADDR_CH?, IN_DSCR_CH?, IN_DSCR_BF0_CH?, IN_DSCR_BF1_CH?, IN_WIGHT_CH?, IN_PRI_CH?, IN_PERI_SEL_CH?, OUT_CONF0_CH?, OUT_CONF1_CH?, OUT_INT_RAW_CH?, OUT_INT_ST_CH?, OUT_INT_ENA_CH?, OUT_INT_CLR_CH?, OUTFIFO_STATUS_CH?, OUT_PUSH_CH?, OUT_LINK_CH?, OUT_STATE_CH?, OUT_EOF_DES_ADDR_CH?, OUT_EOF_BFR_DES_ADDR_CH?, OUT_DSCR_CH?, OUT_DSCR_BF0_CH?, OUT_DSCR_BF1_CH?, OUT_WIGHT_CH?, OUT_PRI_CH?, OUT_PERI_SEL_CH?"]
+pub struct CH {
+    in_conf0: IN_CONF0,
+    in_conf1: IN_CONF1,
+    in_int: IN_INT,
+    infifo_status: INFIFO_STATUS,
+    in_pop: IN_POP,
+    in_link: IN_LINK,
+    in_state: IN_STATE,
+    in_suc_eof_des_addr: IN_SUC_EOF_DES_ADDR,
+    in_err_eof_des_addr: IN_ERR_EOF_DES_ADDR,
+    in_dscr: IN_DSCR,
+    in_dscr_bf0: IN_DSCR_BF0,
+    in_dscr_bf1: IN_DSCR_BF1,
+    in_wight: IN_WIGHT,
+    _reserved13: [u8; 0x04],
+    in_pri: IN_PRI,
+    in_peri_sel: IN_PERI_SEL,
+    _reserved15: [u8; 0x14],
+    out_conf0: OUT_CONF0,
+    out_conf1: OUT_CONF1,
+    out_int: OUT_INT,
+    outfifo_status: OUTFIFO_STATUS,
+    out_push: OUT_PUSH,
+    out_link: OUT_LINK,
+    out_state: OUT_STATE,
+    out_eof_des_addr: OUT_EOF_DES_ADDR,
+    out_eof_bfr_des_addr: OUT_EOF_BFR_DES_ADDR,
+    out_dscr: OUT_DSCR,
+    out_dscr_bf0: OUT_DSCR_BF0,
+    out_dscr_bf1: OUT_DSCR_BF1,
+    out_wight: OUT_WIGHT,
+    _reserved28: [u8; 0x04],
+    out_pri: OUT_PRI,
+    out_peri_sel: OUT_PERI_SEL,
+    _reserved_end: [u8; 0x14],
+}
+impl CH {
+    #[doc = "0x00 - Configure 0 register of Rx channel 0"]
+    #[inline(always)]
+    pub const fn in_conf0(&self) -> &IN_CONF0 {
+        &self.in_conf0
+    }
+    #[doc = "0x04 - Configure 1 register of Rx channel 0"]
+    #[inline(always)]
+    pub const fn in_conf1(&self) -> &IN_CONF1 {
+        &self.in_conf1
+    }
+    #[doc = "0x08..0x18 - Cluster IN_INT, containing IN_INT_RAW, IN_INT_ST, IN_INT_ENA, IN_INT_CLR"]
+    #[inline(always)]
+    pub const fn in_int(&self) -> &IN_INT {
+        &self.in_int
+    }
+    #[doc = "0x18 - Receive FIFO status of Rx channel 0"]
+    #[inline(always)]
+    pub const fn infifo_status(&self) -> &INFIFO_STATUS {
+        &self.infifo_status
+    }
+    #[doc = "0x1c - Pop control register of Rx channel 0"]
+    #[inline(always)]
+    pub const fn in_pop(&self) -> &IN_POP {
+        &self.in_pop
+    }
+    #[doc = "0x20 - Link descriptor configure and control register of Rx channel 0"]
+    #[inline(always)]
+    pub const fn in_link(&self) -> &IN_LINK {
+        &self.in_link
+    }
+    #[doc = "0x24 - Receive status of Rx channel 0"]
+    #[inline(always)]
+    pub const fn in_state(&self) -> &IN_STATE {
+        &self.in_state
+    }
+    #[doc = "0x28 - Inlink descriptor address when EOF occurs of Rx channel 0"]
+    #[inline(always)]
+    pub const fn in_suc_eof_des_addr(&self) -> &IN_SUC_EOF_DES_ADDR {
+        &self.in_suc_eof_des_addr
+    }
+    #[doc = "0x2c - Inlink descriptor address when errors occur of Rx channel 0"]
+    #[inline(always)]
+    pub const fn in_err_eof_des_addr(&self) -> &IN_ERR_EOF_DES_ADDR {
+        &self.in_err_eof_des_addr
+    }
+    #[doc = "0x30 - Current inlink descriptor address of Rx channel 0"]
+    #[inline(always)]
+    pub const fn in_dscr(&self) -> &IN_DSCR {
+        &self.in_dscr
+    }
+    #[doc = "0x34 - The last inlink descriptor address of Rx channel 0"]
+    #[inline(always)]
+    pub const fn in_dscr_bf0(&self) -> &IN_DSCR_BF0 {
+        &self.in_dscr_bf0
+    }
+    #[doc = "0x38 - The second-to-last inlink descriptor address of Rx channel 0"]
+    #[inline(always)]
+    pub const fn in_dscr_bf1(&self) -> &IN_DSCR_BF1 {
+        &self.in_dscr_bf1
+    }
+    #[doc = "0x3c - Weight register of Rx channel 0"]
+    #[inline(always)]
+    pub const fn in_wight(&self) -> &IN_WIGHT {
+        &self.in_wight
+    }
+    #[doc = "0x44 - Priority register of Rx channel 0"]
+    #[inline(always)]
+    pub const fn in_pri(&self) -> &IN_PRI {
+        &self.in_pri
+    }
+    #[doc = "0x48 - Peripheral selection of Rx channel 0"]
+    #[inline(always)]
+    pub const fn in_peri_sel(&self) -> &IN_PERI_SEL {
+        &self.in_peri_sel
+    }
+    #[doc = "0x60 - Configure 0 register of Tx channel 0"]
+    #[inline(always)]
+    pub const fn out_conf0(&self) -> &OUT_CONF0 {
+        &self.out_conf0
+    }
+    #[doc = "0x64 - Configure 1 register of Tx channel 0"]
+    #[inline(always)]
+    pub const fn out_conf1(&self) -> &OUT_CONF1 {
+        &self.out_conf1
+    }
+    #[doc = "0x68..0x78 - Cluster OUT_INT, containing OUT_INT_RAW, OUT_INT_ST, OUT_INT_ENA, OUT_INT_CLR"]
+    #[inline(always)]
+    pub const fn out_int(&self) -> &OUT_INT {
+        &self.out_int
+    }
+    #[doc = "0x78 - Transmit FIFO status of Tx channel 0"]
+    #[inline(always)]
+    pub const fn outfifo_status(&self) -> &OUTFIFO_STATUS {
+        &self.outfifo_status
+    }
+    #[doc = "0x7c - Push control register of Rx channel 0"]
+    #[inline(always)]
+    pub const fn out_push(&self) -> &OUT_PUSH {
+        &self.out_push
+    }
+    #[doc = "0x80 - Link descriptor configure and control register of Tx channel 0"]
+    #[inline(always)]
+    pub const fn out_link(&self) -> &OUT_LINK {
+        &self.out_link
+    }
+    #[doc = "0x84 - Transmit status of Tx channel 0"]
+    #[inline(always)]
+    pub const fn out_state(&self) -> &OUT_STATE {
+        &self.out_state
+    }
+    #[doc = "0x88 - Outlink descriptor address when EOF occurs of Tx channel 0"]
+    #[inline(always)]
+    pub const fn out_eof_des_addr(&self) -> &OUT_EOF_DES_ADDR {
+        &self.out_eof_des_addr
+    }
+    #[doc = "0x8c - The last outlink descriptor address when EOF occurs of Tx channel 0"]
+    #[inline(always)]
+    pub const fn out_eof_bfr_des_addr(&self) -> &OUT_EOF_BFR_DES_ADDR {
+        &self.out_eof_bfr_des_addr
+    }
+    #[doc = "0x90 - Current inlink descriptor address of Tx channel 0"]
+    #[inline(always)]
+    pub const fn out_dscr(&self) -> &OUT_DSCR {
+        &self.out_dscr
+    }
+    #[doc = "0x94 - The last inlink descriptor address of Tx channel 0"]
+    #[inline(always)]
+    pub const fn out_dscr_bf0(&self) -> &OUT_DSCR_BF0 {
+        &self.out_dscr_bf0
+    }
+    #[doc = "0x98 - The second-to-last inlink descriptor address of Tx channel 0"]
+    #[inline(always)]
+    pub const fn out_dscr_bf1(&self) -> &OUT_DSCR_BF1 {
+        &self.out_dscr_bf1
+    }
+    #[doc = "0x9c - Weight register of Rx channel 0"]
+    #[inline(always)]
+    pub const fn out_wight(&self) -> &OUT_WIGHT {
+        &self.out_wight
+    }
+    #[doc = "0xa4 - Priority register of Tx channel 0."]
+    #[inline(always)]
+    pub const fn out_pri(&self) -> &OUT_PRI {
+        &self.out_pri
+    }
+    #[doc = "0xa8 - Peripheral selection of Tx channel 0"]
+    #[inline(always)]
+    pub const fn out_peri_sel(&self) -> &OUT_PERI_SEL {
+        &self.out_peri_sel
+    }
+}
+#[doc = "IN_CONF0 (rw) register accessor: Configure 0 register of Rx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`in_conf0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_conf0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_conf0`] module"]
+pub type IN_CONF0 = crate::Reg<in_conf0::IN_CONF0_SPEC>;
+#[doc = "Configure 0 register of Rx channel 0"]
+pub mod in_conf0;
+#[doc = "IN_CONF1 (rw) register accessor: Configure 1 register of Rx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`in_conf1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_conf1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_conf1`] module"]
+pub type IN_CONF1 = crate::Reg<in_conf1::IN_CONF1_SPEC>;
+#[doc = "Configure 1 register of Rx channel 0"]
+pub mod in_conf1;
+#[doc = "Cluster IN_INT, containing IN_INT_RAW, IN_INT_ST, IN_INT_ENA, IN_INT_CLR"]
+pub use self::in_int::IN_INT;
+#[doc = r"Cluster"]
+#[doc = "Cluster IN_INT, containing IN_INT_RAW, IN_INT_ST, IN_INT_ENA, IN_INT_CLR"]
+pub mod in_int;
+#[doc = "INFIFO_STATUS (r) register accessor: Receive FIFO status of Rx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`infifo_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@infifo_status`] module"]
+pub type INFIFO_STATUS = crate::Reg<infifo_status::INFIFO_STATUS_SPEC>;
+#[doc = "Receive FIFO status of Rx channel 0"]
+pub mod infifo_status;
+#[doc = "IN_POP (rw) register accessor: Pop control register of Rx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`in_pop::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_pop::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_pop`] module"]
+pub type IN_POP = crate::Reg<in_pop::IN_POP_SPEC>;
+#[doc = "Pop control register of Rx channel 0"]
+pub mod in_pop;
+#[doc = "IN_LINK (rw) register accessor: Link descriptor configure and control register of Rx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`in_link::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_link::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_link`] module"]
+pub type IN_LINK = crate::Reg<in_link::IN_LINK_SPEC>;
+#[doc = "Link descriptor configure and control register of Rx channel 0"]
+pub mod in_link;
+#[doc = "IN_STATE (r) register accessor: Receive status of Rx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`in_state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_state`] module"]
+pub type IN_STATE = crate::Reg<in_state::IN_STATE_SPEC>;
+#[doc = "Receive status of Rx channel 0"]
+pub mod in_state;
+#[doc = "IN_SUC_EOF_DES_ADDR (r) register accessor: Inlink descriptor address when EOF occurs of Rx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`in_suc_eof_des_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_suc_eof_des_addr`] module"]
+pub type IN_SUC_EOF_DES_ADDR = crate::Reg<in_suc_eof_des_addr::IN_SUC_EOF_DES_ADDR_SPEC>;
+#[doc = "Inlink descriptor address when EOF occurs of Rx channel 0"]
+pub mod in_suc_eof_des_addr;
+#[doc = "IN_ERR_EOF_DES_ADDR (r) register accessor: Inlink descriptor address when errors occur of Rx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`in_err_eof_des_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_err_eof_des_addr`] module"]
+pub type IN_ERR_EOF_DES_ADDR = crate::Reg<in_err_eof_des_addr::IN_ERR_EOF_DES_ADDR_SPEC>;
+#[doc = "Inlink descriptor address when errors occur of Rx channel 0"]
+pub mod in_err_eof_des_addr;
+#[doc = "IN_DSCR (r) register accessor: Current inlink descriptor address of Rx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`in_dscr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_dscr`] module"]
+pub type IN_DSCR = crate::Reg<in_dscr::IN_DSCR_SPEC>;
+#[doc = "Current inlink descriptor address of Rx channel 0"]
+pub mod in_dscr;
+#[doc = "IN_DSCR_BF0 (r) register accessor: The last inlink descriptor address of Rx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`in_dscr_bf0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_dscr_bf0`] module"]
+pub type IN_DSCR_BF0 = crate::Reg<in_dscr_bf0::IN_DSCR_BF0_SPEC>;
+#[doc = "The last inlink descriptor address of Rx channel 0"]
+pub mod in_dscr_bf0;
+#[doc = "IN_DSCR_BF1 (r) register accessor: The second-to-last inlink descriptor address of Rx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`in_dscr_bf1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_dscr_bf1`] module"]
+pub type IN_DSCR_BF1 = crate::Reg<in_dscr_bf1::IN_DSCR_BF1_SPEC>;
+#[doc = "The second-to-last inlink descriptor address of Rx channel 0"]
+pub mod in_dscr_bf1;
+#[doc = "IN_WIGHT (rw) register accessor: Weight register of Rx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`in_wight::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_wight::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_wight`] module"]
+pub type IN_WIGHT = crate::Reg<in_wight::IN_WIGHT_SPEC>;
+#[doc = "Weight register of Rx channel 0"]
+pub mod in_wight;
+#[doc = "IN_PRI (rw) register accessor: Priority register of Rx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`in_pri::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_pri::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_pri`] module"]
+pub type IN_PRI = crate::Reg<in_pri::IN_PRI_SPEC>;
+#[doc = "Priority register of Rx channel 0"]
+pub mod in_pri;
+#[doc = "IN_PERI_SEL (rw) register accessor: Peripheral selection of Rx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`in_peri_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_peri_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_peri_sel`] module"]
+pub type IN_PERI_SEL = crate::Reg<in_peri_sel::IN_PERI_SEL_SPEC>;
+#[doc = "Peripheral selection of Rx channel 0"]
+pub mod in_peri_sel;
+#[doc = "OUT_CONF0 (rw) register accessor: Configure 0 register of Tx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`out_conf0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`out_conf0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_conf0`] module"]
+pub type OUT_CONF0 = crate::Reg<out_conf0::OUT_CONF0_SPEC>;
+#[doc = "Configure 0 register of Tx channel 0"]
+pub mod out_conf0;
+#[doc = "OUT_CONF1 (rw) register accessor: Configure 1 register of Tx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`out_conf1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`out_conf1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_conf1`] module"]
+pub type OUT_CONF1 = crate::Reg<out_conf1::OUT_CONF1_SPEC>;
+#[doc = "Configure 1 register of Tx channel 0"]
+pub mod out_conf1;
+#[doc = "Cluster OUT_INT, containing OUT_INT_RAW, OUT_INT_ST, OUT_INT_ENA, OUT_INT_CLR"]
+pub use self::out_int::OUT_INT;
+#[doc = r"Cluster"]
+#[doc = "Cluster OUT_INT, containing OUT_INT_RAW, OUT_INT_ST, OUT_INT_ENA, OUT_INT_CLR"]
+pub mod out_int;
+#[doc = "OUTFIFO_STATUS (r) register accessor: Transmit FIFO status of Tx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`outfifo_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@outfifo_status`] module"]
+pub type OUTFIFO_STATUS = crate::Reg<outfifo_status::OUTFIFO_STATUS_SPEC>;
+#[doc = "Transmit FIFO status of Tx channel 0"]
+pub mod outfifo_status;
+#[doc = "OUT_PUSH (rw) register accessor: Push control register of Rx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`out_push::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`out_push::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_push`] module"]
+pub type OUT_PUSH = crate::Reg<out_push::OUT_PUSH_SPEC>;
+#[doc = "Push control register of Rx channel 0"]
+pub mod out_push;
+#[doc = "OUT_LINK (rw) register accessor: Link descriptor configure and control register of Tx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`out_link::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`out_link::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_link`] module"]
+pub type OUT_LINK = crate::Reg<out_link::OUT_LINK_SPEC>;
+#[doc = "Link descriptor configure and control register of Tx channel 0"]
+pub mod out_link;
+#[doc = "OUT_STATE (r) register accessor: Transmit status of Tx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`out_state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_state`] module"]
+pub type OUT_STATE = crate::Reg<out_state::OUT_STATE_SPEC>;
+#[doc = "Transmit status of Tx channel 0"]
+pub mod out_state;
+#[doc = "OUT_EOF_DES_ADDR (r) register accessor: Outlink descriptor address when EOF occurs of Tx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`out_eof_des_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_eof_des_addr`] module"]
+pub type OUT_EOF_DES_ADDR = crate::Reg<out_eof_des_addr::OUT_EOF_DES_ADDR_SPEC>;
+#[doc = "Outlink descriptor address when EOF occurs of Tx channel 0"]
+pub mod out_eof_des_addr;
+#[doc = "OUT_EOF_BFR_DES_ADDR (r) register accessor: The last outlink descriptor address when EOF occurs of Tx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`out_eof_bfr_des_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_eof_bfr_des_addr`] module"]
+pub type OUT_EOF_BFR_DES_ADDR = crate::Reg<out_eof_bfr_des_addr::OUT_EOF_BFR_DES_ADDR_SPEC>;
+#[doc = "The last outlink descriptor address when EOF occurs of Tx channel 0"]
+pub mod out_eof_bfr_des_addr;
+#[doc = "OUT_DSCR (r) register accessor: Current inlink descriptor address of Tx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`out_dscr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_dscr`] module"]
+pub type OUT_DSCR = crate::Reg<out_dscr::OUT_DSCR_SPEC>;
+#[doc = "Current inlink descriptor address of Tx channel 0"]
+pub mod out_dscr;
+#[doc = "OUT_DSCR_BF0 (r) register accessor: The last inlink descriptor address of Tx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`out_dscr_bf0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_dscr_bf0`] module"]
+pub type OUT_DSCR_BF0 = crate::Reg<out_dscr_bf0::OUT_DSCR_BF0_SPEC>;
+#[doc = "The last inlink descriptor address of Tx channel 0"]
+pub mod out_dscr_bf0;
+#[doc = "OUT_DSCR_BF1 (r) register accessor: The second-to-last inlink descriptor address of Tx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`out_dscr_bf1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_dscr_bf1`] module"]
+pub type OUT_DSCR_BF1 = crate::Reg<out_dscr_bf1::OUT_DSCR_BF1_SPEC>;
+#[doc = "The second-to-last inlink descriptor address of Tx channel 0"]
+pub mod out_dscr_bf1;
+#[doc = "OUT_WIGHT (rw) register accessor: Weight register of Rx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`out_wight::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`out_wight::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_wight`] module"]
+pub type OUT_WIGHT = crate::Reg<out_wight::OUT_WIGHT_SPEC>;
+#[doc = "Weight register of Rx channel 0"]
+pub mod out_wight;
+#[doc = "OUT_PRI (rw) register accessor: Priority register of Tx channel 0.\n\nYou can [`read`](crate::Reg::read) this register and get [`out_pri::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`out_pri::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_pri`] module"]
+pub type OUT_PRI = crate::Reg<out_pri::OUT_PRI_SPEC>;
+#[doc = "Priority register of Tx channel 0."]
+pub mod out_pri;
+#[doc = "OUT_PERI_SEL (rw) register accessor: Peripheral selection of Tx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`out_peri_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`out_peri_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_peri_sel`] module"]
+pub type OUT_PERI_SEL = crate::Reg<out_peri_sel::OUT_PERI_SEL_SPEC>;
+#[doc = "Peripheral selection of Tx channel 0"]
+pub mod out_peri_sel;

vendor/esp32s3/src/dma/ch/in_conf0.rs

@@ -0,0 +1,107 @@
+#[doc = "Register `IN_CONF0` reader"]
+pub type R = crate::R<IN_CONF0_SPEC>;
+#[doc = "Register `IN_CONF0` writer"]
+pub type W = crate::W<IN_CONF0_SPEC>;
+#[doc = "Field `IN_RST` reader - This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer."]
+pub type IN_RST_R = crate::BitReader;
+#[doc = "Field `IN_RST` writer - This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer."]
+pub type IN_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `IN_LOOP_TEST` reader - reserved"]
+pub type IN_LOOP_TEST_R = crate::BitReader;
+#[doc = "Field `IN_LOOP_TEST` writer - reserved"]
+pub type IN_LOOP_TEST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `INDSCR_BURST_EN` reader - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM."]
+pub type INDSCR_BURST_EN_R = crate::BitReader;
+#[doc = "Field `INDSCR_BURST_EN` writer - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM."]
+pub type INDSCR_BURST_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `IN_DATA_BURST_EN` reader - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM."]
+pub type IN_DATA_BURST_EN_R = crate::BitReader;
+#[doc = "Field `IN_DATA_BURST_EN` writer - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM."]
+pub type IN_DATA_BURST_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `MEM_TRANS_EN` reader - Set this bit 1 to enable automatic transmitting data from memory to memory via DMA."]
+pub type MEM_TRANS_EN_R = crate::BitReader;
+#[doc = "Field `MEM_TRANS_EN` writer - Set this bit 1 to enable automatic transmitting data from memory to memory via DMA."]
+pub type MEM_TRANS_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer."]
+    #[inline(always)]
+    pub fn in_rst(&self) -> IN_RST_R {
+        IN_RST_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - reserved"]
+    #[inline(always)]
+    pub fn in_loop_test(&self) -> IN_LOOP_TEST_R {
+        IN_LOOP_TEST_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM."]
+    #[inline(always)]
+    pub fn indscr_burst_en(&self) -> INDSCR_BURST_EN_R {
+        INDSCR_BURST_EN_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM."]
+    #[inline(always)]
+    pub fn in_data_burst_en(&self) -> IN_DATA_BURST_EN_R {
+        IN_DATA_BURST_EN_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Set this bit 1 to enable automatic transmitting data from memory to memory via DMA."]
+    #[inline(always)]
+    pub fn mem_trans_en(&self) -> MEM_TRANS_EN_R {
+        MEM_TRANS_EN_R::new(((self.bits >> 4) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("IN_CONF0")
+            .field("in_rst", &self.in_rst())
+            .field("in_loop_test", &self.in_loop_test())
+            .field("indscr_burst_en", &self.indscr_burst_en())
+            .field("in_data_burst_en", &self.in_data_burst_en())
+            .field("mem_trans_en", &self.mem_trans_en())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer."]
+    #[inline(always)]
+    pub fn in_rst(&mut self) -> IN_RST_W<IN_CONF0_SPEC> {
+        IN_RST_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - reserved"]
+    #[inline(always)]
+    pub fn in_loop_test(&mut self) -> IN_LOOP_TEST_W<IN_CONF0_SPEC> {
+        IN_LOOP_TEST_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM."]
+    #[inline(always)]
+    pub fn indscr_burst_en(&mut self) -> INDSCR_BURST_EN_W<IN_CONF0_SPEC> {
+        INDSCR_BURST_EN_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM."]
+    #[inline(always)]
+    pub fn in_data_burst_en(&mut self) -> IN_DATA_BURST_EN_W<IN_CONF0_SPEC> {
+        IN_DATA_BURST_EN_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - Set this bit 1 to enable automatic transmitting data from memory to memory via DMA."]
+    #[inline(always)]
+    pub fn mem_trans_en(&mut self) -> MEM_TRANS_EN_W<IN_CONF0_SPEC> {
+        MEM_TRANS_EN_W::new(self, 4)
+    }
+}
+#[doc = "Configure 0 register of Rx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`in_conf0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_conf0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct IN_CONF0_SPEC;
+impl crate::RegisterSpec for IN_CONF0_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`in_conf0::R`](R) reader structure"]
+impl crate::Readable for IN_CONF0_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`in_conf0::W`](W) writer structure"]
+impl crate::Writable for IN_CONF0_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets IN_CONF0 to value 0"]
+impl crate::Resettable for IN_CONF0_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/dma/ch/in_conf1.rs

@@ -0,0 +1,77 @@
+#[doc = "Register `IN_CONF1` reader"]
+pub type R = crate::R<IN_CONF1_SPEC>;
+#[doc = "Register `IN_CONF1` writer"]
+pub type W = crate::W<IN_CONF1_SPEC>;
+#[doc = "Field `DMA_INFIFO_FULL_THRS` reader - This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx channel 0 received byte number in Rx FIFO is up to the value of the register."]
+pub type DMA_INFIFO_FULL_THRS_R = crate::FieldReader<u16>;
+#[doc = "Field `DMA_INFIFO_FULL_THRS` writer - This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx channel 0 received byte number in Rx FIFO is up to the value of the register."]
+pub type DMA_INFIFO_FULL_THRS_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
+#[doc = "Field `IN_CHECK_OWNER` reader - Set this bit to enable checking the owner attribute of the link descriptor."]
+pub type IN_CHECK_OWNER_R = crate::BitReader;
+#[doc = "Field `IN_CHECK_OWNER` writer - Set this bit to enable checking the owner attribute of the link descriptor."]
+pub type IN_CHECK_OWNER_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `IN_EXT_MEM_BK_SIZE` reader - Block size of Rx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved"]
+pub type IN_EXT_MEM_BK_SIZE_R = crate::FieldReader;
+#[doc = "Field `IN_EXT_MEM_BK_SIZE` writer - Block size of Rx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved"]
+pub type IN_EXT_MEM_BK_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+impl R {
+    #[doc = "Bits 0:11 - This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx channel 0 received byte number in Rx FIFO is up to the value of the register."]
+    #[inline(always)]
+    pub fn dma_infifo_full_thrs(&self) -> DMA_INFIFO_FULL_THRS_R {
+        DMA_INFIFO_FULL_THRS_R::new((self.bits & 0x0fff) as u16)
+    }
+    #[doc = "Bit 12 - Set this bit to enable checking the owner attribute of the link descriptor."]
+    #[inline(always)]
+    pub fn in_check_owner(&self) -> IN_CHECK_OWNER_R {
+        IN_CHECK_OWNER_R::new(((self.bits >> 12) & 1) != 0)
+    }
+    #[doc = "Bits 13:14 - Block size of Rx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved"]
+    #[inline(always)]
+    pub fn in_ext_mem_bk_size(&self) -> IN_EXT_MEM_BK_SIZE_R {
+        IN_EXT_MEM_BK_SIZE_R::new(((self.bits >> 13) & 3) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("IN_CONF1")
+            .field("dma_infifo_full_thrs", &self.dma_infifo_full_thrs())
+            .field("in_check_owner", &self.in_check_owner())
+            .field("in_ext_mem_bk_size", &self.in_ext_mem_bk_size())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:11 - This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx channel 0 received byte number in Rx FIFO is up to the value of the register."]
+    #[inline(always)]
+    pub fn dma_infifo_full_thrs(&mut self) -> DMA_INFIFO_FULL_THRS_W<IN_CONF1_SPEC> {
+        DMA_INFIFO_FULL_THRS_W::new(self, 0)
+    }
+    #[doc = "Bit 12 - Set this bit to enable checking the owner attribute of the link descriptor."]
+    #[inline(always)]
+    pub fn in_check_owner(&mut self) -> IN_CHECK_OWNER_W<IN_CONF1_SPEC> {
+        IN_CHECK_OWNER_W::new(self, 12)
+    }
+    #[doc = "Bits 13:14 - Block size of Rx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved"]
+    #[inline(always)]
+    pub fn in_ext_mem_bk_size(&mut self) -> IN_EXT_MEM_BK_SIZE_W<IN_CONF1_SPEC> {
+        IN_EXT_MEM_BK_SIZE_W::new(self, 13)
+    }
+}
+#[doc = "Configure 1 register of Rx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`in_conf1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_conf1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct IN_CONF1_SPEC;
+impl crate::RegisterSpec for IN_CONF1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`in_conf1::R`](R) reader structure"]
+impl crate::Readable for IN_CONF1_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`in_conf1::W`](W) writer structure"]
+impl crate::Writable for IN_CONF1_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets IN_CONF1 to value 0x0c"]
+impl crate::Resettable for IN_CONF1_SPEC {
+    const RESET_VALUE: u32 = 0x0c;
+}

vendor/esp32s3/src/dma/ch/in_dscr.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `IN_DSCR` reader"]
+pub type R = crate::R<IN_DSCR_SPEC>;
+#[doc = "Field `INLINK_DSCR` reader - The address of the current inlink descriptor x."]
+pub type INLINK_DSCR_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - The address of the current inlink descriptor x."]
+    #[inline(always)]
+    pub fn inlink_dscr(&self) -> INLINK_DSCR_R {
+        INLINK_DSCR_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("IN_DSCR")
+            .field("inlink_dscr", &self.inlink_dscr())
+            .finish()
+    }
+}
+#[doc = "Current inlink descriptor address of Rx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`in_dscr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct IN_DSCR_SPEC;
+impl crate::RegisterSpec for IN_DSCR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`in_dscr::R`](R) reader structure"]
+impl crate::Readable for IN_DSCR_SPEC {}
+#[doc = "`reset()` method sets IN_DSCR to value 0"]
+impl crate::Resettable for IN_DSCR_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/dma/ch/in_dscr_bf0.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `IN_DSCR_BF0` reader"]
+pub type R = crate::R<IN_DSCR_BF0_SPEC>;
+#[doc = "Field `INLINK_DSCR_BF0` reader - The address of the last inlink descriptor x-1."]
+pub type INLINK_DSCR_BF0_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - The address of the last inlink descriptor x-1."]
+    #[inline(always)]
+    pub fn inlink_dscr_bf0(&self) -> INLINK_DSCR_BF0_R {
+        INLINK_DSCR_BF0_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("IN_DSCR_BF0")
+            .field("inlink_dscr_bf0", &self.inlink_dscr_bf0())
+            .finish()
+    }
+}
+#[doc = "The last inlink descriptor address of Rx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`in_dscr_bf0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct IN_DSCR_BF0_SPEC;
+impl crate::RegisterSpec for IN_DSCR_BF0_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`in_dscr_bf0::R`](R) reader structure"]
+impl crate::Readable for IN_DSCR_BF0_SPEC {}
+#[doc = "`reset()` method sets IN_DSCR_BF0 to value 0"]
+impl crate::Resettable for IN_DSCR_BF0_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/dma/ch/in_dscr_bf1.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `IN_DSCR_BF1` reader"]
+pub type R = crate::R<IN_DSCR_BF1_SPEC>;
+#[doc = "Field `INLINK_DSCR_BF1` reader - The address of the second-to-last inlink descriptor x-2."]
+pub type INLINK_DSCR_BF1_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - The address of the second-to-last inlink descriptor x-2."]
+    #[inline(always)]
+    pub fn inlink_dscr_bf1(&self) -> INLINK_DSCR_BF1_R {
+        INLINK_DSCR_BF1_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("IN_DSCR_BF1")
+            .field("inlink_dscr_bf1", &self.inlink_dscr_bf1())
+            .finish()
+    }
+}
+#[doc = "The second-to-last inlink descriptor address of Rx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`in_dscr_bf1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct IN_DSCR_BF1_SPEC;
+impl crate::RegisterSpec for IN_DSCR_BF1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`in_dscr_bf1::R`](R) reader structure"]
+impl crate::Readable for IN_DSCR_BF1_SPEC {}
+#[doc = "`reset()` method sets IN_DSCR_BF1 to value 0"]
+impl crate::Resettable for IN_DSCR_BF1_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/dma/ch/in_err_eof_des_addr.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `IN_ERR_EOF_DES_ADDR` reader"]
+pub type R = crate::R<IN_ERR_EOF_DES_ADDR_SPEC>;
+#[doc = "Field `IN_ERR_EOF_DES_ADDR` reader - This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0."]
+pub type IN_ERR_EOF_DES_ADDR_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0."]
+    #[inline(always)]
+    pub fn in_err_eof_des_addr(&self) -> IN_ERR_EOF_DES_ADDR_R {
+        IN_ERR_EOF_DES_ADDR_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("IN_ERR_EOF_DES_ADDR")
+            .field("in_err_eof_des_addr", &self.in_err_eof_des_addr())
+            .finish()
+    }
+}
+#[doc = "Inlink descriptor address when errors occur of Rx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`in_err_eof_des_addr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct IN_ERR_EOF_DES_ADDR_SPEC;
+impl crate::RegisterSpec for IN_ERR_EOF_DES_ADDR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`in_err_eof_des_addr::R`](R) reader structure"]
+impl crate::Readable for IN_ERR_EOF_DES_ADDR_SPEC {}
+#[doc = "`reset()` method sets IN_ERR_EOF_DES_ADDR to value 0"]
+impl crate::Resettable for IN_ERR_EOF_DES_ADDR_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/dma/ch/in_int.rs

@@ -0,0 +1,47 @@
+#[repr(C)]
+#[cfg_attr(feature = "impl-register-debug", derive(Debug))]
+#[doc = "Cluster IN_INT, containing IN_INT_RAW, IN_INT_ST, IN_INT_ENA, IN_INT_CLR"]
+pub struct IN_INT {
+    raw: RAW,
+    st: ST,
+    ena: ENA,
+    clr: CLR,
+}
+impl IN_INT {
+    #[doc = "0x00 - Raw status interrupt of Rx channel 0"]
+    #[inline(always)]
+    pub const fn raw(&self) -> &RAW {
+        &self.raw
+    }
+    #[doc = "0x04 - Masked interrupt of Rx channel 0"]
+    #[inline(always)]
+    pub const fn st(&self) -> &ST {
+        &self.st
+    }
+    #[doc = "0x08 - Interrupt enable bits of Rx channel 0"]
+    #[inline(always)]
+    pub const fn ena(&self) -> &ENA {
+        &self.ena
+    }
+    #[doc = "0x0c - Interrupt clear bits of Rx channel 0"]
+    #[inline(always)]
+    pub const fn clr(&self) -> &CLR {
+        &self.clr
+    }
+}
+#[doc = "RAW (rw) register accessor: Raw status interrupt of Rx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`raw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`raw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@raw`] module"]
+pub type RAW = crate::Reg<raw::RAW_SPEC>;
+#[doc = "Raw status interrupt of Rx channel 0"]
+pub mod raw;
+#[doc = "ST (r) register accessor: Masked interrupt of Rx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@st`] module"]
+pub type ST = crate::Reg<st::ST_SPEC>;
+#[doc = "Masked interrupt of Rx channel 0"]
+pub mod st;
+#[doc = "ENA (rw) register accessor: Interrupt enable bits of Rx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ena::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ena::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ena`] module"]
+pub type ENA = crate::Reg<ena::ENA_SPEC>;
+#[doc = "Interrupt enable bits of Rx channel 0"]
+pub mod ena;
+#[doc = "CLR (w) register accessor: Interrupt clear bits of Rx channel 0\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr`] module"]
+pub type CLR = crate::Reg<clr::CLR_SPEC>;
+#[doc = "Interrupt clear bits of Rx channel 0"]
+pub mod clr;

vendor/esp32s3/src/dma/ch/in_int/clr.rs

@@ -0,0 +1,95 @@
+#[doc = "Register `CLR` writer"]
+pub type W = crate::W<CLR_SPEC>;
+#[doc = "Field `IN_DONE` writer - Set this bit to clear the IN_DONE_CH_INT interrupt."]
+pub type IN_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `IN_SUC_EOF` writer - Set this bit to clear the IN_SUC_EOF_CH_INT interrupt."]
+pub type IN_SUC_EOF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `IN_ERR_EOF` writer - Set this bit to clear the IN_ERR_EOF_CH_INT interrupt."]
+pub type IN_ERR_EOF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `IN_DSCR_ERR` writer - Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt."]
+pub type IN_DSCR_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `IN_DSCR_EMPTY` writer - Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt."]
+pub type IN_DSCR_EMPTY_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `DMA_INFIFO_FULL_WM` writer - Set this bit to clear the INFIFO_FULL_WM_CH_INT interrupt."]
+pub type DMA_INFIFO_FULL_WM_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `INFIFO_OVF_L1` writer - Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt."]
+pub type INFIFO_OVF_L1_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `INFIFO_UDF_L1` writer - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt."]
+pub type INFIFO_UDF_L1_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `INFIFO_OVF_L3` writer - Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt."]
+pub type INFIFO_OVF_L3_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `INFIFO_UDF_L3` writer - Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt."]
+pub type INFIFO_UDF_L3_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for crate::generic::Reg<CLR_SPEC> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "(not readable)")
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Set this bit to clear the IN_DONE_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn in_done(&mut self) -> IN_DONE_W<CLR_SPEC> {
+        IN_DONE_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - Set this bit to clear the IN_SUC_EOF_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn in_suc_eof(&mut self) -> IN_SUC_EOF_W<CLR_SPEC> {
+        IN_SUC_EOF_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - Set this bit to clear the IN_ERR_EOF_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn in_err_eof(&mut self) -> IN_ERR_EOF_W<CLR_SPEC> {
+        IN_ERR_EOF_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn in_dscr_err(&mut self) -> IN_DSCR_ERR_W<CLR_SPEC> {
+        IN_DSCR_ERR_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn in_dscr_empty(&mut self) -> IN_DSCR_EMPTY_W<CLR_SPEC> {
+        IN_DSCR_EMPTY_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - Set this bit to clear the INFIFO_FULL_WM_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn dma_infifo_full_wm(&mut self) -> DMA_INFIFO_FULL_WM_W<CLR_SPEC> {
+        DMA_INFIFO_FULL_WM_W::new(self, 5)
+    }
+    #[doc = "Bit 6 - Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn infifo_ovf_l1(&mut self) -> INFIFO_OVF_L1_W<CLR_SPEC> {
+        INFIFO_OVF_L1_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn infifo_udf_l1(&mut self) -> INFIFO_UDF_L1_W<CLR_SPEC> {
+        INFIFO_UDF_L1_W::new(self, 7)
+    }
+    #[doc = "Bit 8 - Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn infifo_ovf_l3(&mut self) -> INFIFO_OVF_L3_W<CLR_SPEC> {
+        INFIFO_OVF_L3_W::new(self, 8)
+    }
+    #[doc = "Bit 9 - Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn infifo_udf_l3(&mut self) -> INFIFO_UDF_L3_W<CLR_SPEC> {
+        INFIFO_UDF_L3_W::new(self, 9)
+    }
+}
+#[doc = "Interrupt clear bits of Rx channel 0\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CLR_SPEC;
+impl crate::RegisterSpec for CLR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [`clr::W`](W) writer structure"]
+impl crate::Writable for CLR_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x03ff;
+}
+#[doc = "`reset()` method sets CLR to value 0"]
+impl crate::Resettable for CLR_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/dma/ch/in_int/ena.rs

@@ -0,0 +1,182 @@
+#[doc = "Register `ENA` reader"]
+pub type R = crate::R<ENA_SPEC>;
+#[doc = "Register `ENA` writer"]
+pub type W = crate::W<ENA_SPEC>;
+#[doc = "Field `IN_DONE` reader - The interrupt enable bit for the IN_DONE_CH_INT interrupt."]
+pub type IN_DONE_R = crate::BitReader;
+#[doc = "Field `IN_DONE` writer - The interrupt enable bit for the IN_DONE_CH_INT interrupt."]
+pub type IN_DONE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `IN_SUC_EOF` reader - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."]
+pub type IN_SUC_EOF_R = crate::BitReader;
+#[doc = "Field `IN_SUC_EOF` writer - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."]
+pub type IN_SUC_EOF_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `IN_ERR_EOF` reader - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."]
+pub type IN_ERR_EOF_R = crate::BitReader;
+#[doc = "Field `IN_ERR_EOF` writer - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."]
+pub type IN_ERR_EOF_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `IN_DSCR_ERR` reader - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."]
+pub type IN_DSCR_ERR_R = crate::BitReader;
+#[doc = "Field `IN_DSCR_ERR` writer - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."]
+pub type IN_DSCR_ERR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `IN_DSCR_EMPTY` reader - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."]
+pub type IN_DSCR_EMPTY_R = crate::BitReader;
+#[doc = "Field `IN_DSCR_EMPTY` writer - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."]
+pub type IN_DSCR_EMPTY_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `INFIFO_FULL_WM` reader - The interrupt enable bit for the INFIFO_FULL_WM_CH_INT interrupt."]
+pub type INFIFO_FULL_WM_R = crate::BitReader;
+#[doc = "Field `INFIFO_FULL_WM` writer - The interrupt enable bit for the INFIFO_FULL_WM_CH_INT interrupt."]
+pub type INFIFO_FULL_WM_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `INFIFO_OVF_L1` reader - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."]
+pub type INFIFO_OVF_L1_R = crate::BitReader;
+#[doc = "Field `INFIFO_OVF_L1` writer - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."]
+pub type INFIFO_OVF_L1_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `INFIFO_UDF_L1` reader - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."]
+pub type INFIFO_UDF_L1_R = crate::BitReader;
+#[doc = "Field `INFIFO_UDF_L1` writer - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."]
+pub type INFIFO_UDF_L1_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `INFIFO_OVF_L3` reader - The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt."]
+pub type INFIFO_OVF_L3_R = crate::BitReader;
+#[doc = "Field `INFIFO_OVF_L3` writer - The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt."]
+pub type INFIFO_OVF_L3_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `INFIFO_UDF_L3` reader - The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt."]
+pub type INFIFO_UDF_L3_R = crate::BitReader;
+#[doc = "Field `INFIFO_UDF_L3` writer - The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt."]
+pub type INFIFO_UDF_L3_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - The interrupt enable bit for the IN_DONE_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn in_done(&self) -> IN_DONE_R {
+        IN_DONE_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn in_suc_eof(&self) -> IN_SUC_EOF_R {
+        IN_SUC_EOF_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn in_err_eof(&self) -> IN_ERR_EOF_R {
+        IN_ERR_EOF_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn in_dscr_err(&self) -> IN_DSCR_ERR_R {
+        IN_DSCR_ERR_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn in_dscr_empty(&self) -> IN_DSCR_EMPTY_R {
+        IN_DSCR_EMPTY_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - The interrupt enable bit for the INFIFO_FULL_WM_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn infifo_full_wm(&self) -> INFIFO_FULL_WM_R {
+        INFIFO_FULL_WM_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn infifo_ovf_l1(&self) -> INFIFO_OVF_L1_R {
+        INFIFO_OVF_L1_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn infifo_udf_l1(&self) -> INFIFO_UDF_L1_R {
+        INFIFO_UDF_L1_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn infifo_ovf_l3(&self) -> INFIFO_OVF_L3_R {
+        INFIFO_OVF_L3_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn infifo_udf_l3(&self) -> INFIFO_UDF_L3_R {
+        INFIFO_UDF_L3_R::new(((self.bits >> 9) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("ENA")
+            .field("in_done", &self.in_done())
+            .field("in_suc_eof", &self.in_suc_eof())
+            .field("in_err_eof", &self.in_err_eof())
+            .field("in_dscr_err", &self.in_dscr_err())
+            .field("in_dscr_empty", &self.in_dscr_empty())
+            .field("infifo_full_wm", &self.infifo_full_wm())
+            .field("infifo_ovf_l1", &self.infifo_ovf_l1())
+            .field("infifo_udf_l1", &self.infifo_udf_l1())
+            .field("infifo_ovf_l3", &self.infifo_ovf_l3())
+            .field("infifo_udf_l3", &self.infifo_udf_l3())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - The interrupt enable bit for the IN_DONE_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn in_done(&mut self) -> IN_DONE_W<ENA_SPEC> {
+        IN_DONE_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn in_suc_eof(&mut self) -> IN_SUC_EOF_W<ENA_SPEC> {
+        IN_SUC_EOF_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn in_err_eof(&mut self) -> IN_ERR_EOF_W<ENA_SPEC> {
+        IN_ERR_EOF_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn in_dscr_err(&mut self) -> IN_DSCR_ERR_W<ENA_SPEC> {
+        IN_DSCR_ERR_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn in_dscr_empty(&mut self) -> IN_DSCR_EMPTY_W<ENA_SPEC> {
+        IN_DSCR_EMPTY_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - The interrupt enable bit for the INFIFO_FULL_WM_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn infifo_full_wm(&mut self) -> INFIFO_FULL_WM_W<ENA_SPEC> {
+        INFIFO_FULL_WM_W::new(self, 5)
+    }
+    #[doc = "Bit 6 - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn infifo_ovf_l1(&mut self) -> INFIFO_OVF_L1_W<ENA_SPEC> {
+        INFIFO_OVF_L1_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn infifo_udf_l1(&mut self) -> INFIFO_UDF_L1_W<ENA_SPEC> {
+        INFIFO_UDF_L1_W::new(self, 7)
+    }
+    #[doc = "Bit 8 - The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn infifo_ovf_l3(&mut self) -> INFIFO_OVF_L3_W<ENA_SPEC> {
+        INFIFO_OVF_L3_W::new(self, 8)
+    }
+    #[doc = "Bit 9 - The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn infifo_udf_l3(&mut self) -> INFIFO_UDF_L3_W<ENA_SPEC> {
+        INFIFO_UDF_L3_W::new(self, 9)
+    }
+}
+#[doc = "Interrupt enable bits of Rx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ENA_SPEC;
+impl crate::RegisterSpec for ENA_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`ena::R`](R) reader structure"]
+impl crate::Readable for ENA_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`ena::W`](W) writer structure"]
+impl crate::Writable for ENA_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets ENA to value 0"]
+impl crate::Resettable for ENA_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/dma/ch/in_int/raw.rs

@@ -0,0 +1,182 @@
+#[doc = "Register `RAW` reader"]
+pub type R = crate::R<RAW_SPEC>;
+#[doc = "Register `RAW` writer"]
+pub type W = crate::W<RAW_SPEC>;
+#[doc = "Field `IN_DONE` reader - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0."]
+pub type IN_DONE_R = crate::BitReader;
+#[doc = "Field `IN_DONE` writer - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0."]
+pub type IN_DONE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `IN_SUC_EOF` reader - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0."]
+pub type IN_SUC_EOF_R = crate::BitReader;
+#[doc = "Field `IN_SUC_EOF` writer - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0."]
+pub type IN_SUC_EOF_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `IN_ERR_EOF` reader - The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved."]
+pub type IN_ERR_EOF_R = crate::BitReader;
+#[doc = "Field `IN_ERR_EOF` writer - The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved."]
+pub type IN_ERR_EOF_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `IN_DSCR_ERR` reader - The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0."]
+pub type IN_DSCR_ERR_R = crate::BitReader;
+#[doc = "Field `IN_DSCR_ERR` writer - The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0."]
+pub type IN_DSCR_ERR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `IN_DSCR_EMPTY` reader - The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0."]
+pub type IN_DSCR_EMPTY_R = crate::BitReader;
+#[doc = "Field `IN_DSCR_EMPTY` writer - The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0."]
+pub type IN_DSCR_EMPTY_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `INFIFO_FULL_WM` reader - The raw interrupt bit turns to high level when received data byte number is up to threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 0."]
+pub type INFIFO_FULL_WM_R = crate::BitReader;
+#[doc = "Field `INFIFO_FULL_WM` writer - The raw interrupt bit turns to high level when received data byte number is up to threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 0."]
+pub type INFIFO_FULL_WM_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `INFIFO_OVF_L1` reader - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow."]
+pub type INFIFO_OVF_L1_R = crate::BitReader;
+#[doc = "Field `INFIFO_OVF_L1` writer - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow."]
+pub type INFIFO_OVF_L1_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `INFIFO_UDF_L1` reader - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow."]
+pub type INFIFO_UDF_L1_R = crate::BitReader;
+#[doc = "Field `INFIFO_UDF_L1` writer - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow."]
+pub type INFIFO_UDF_L1_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `INFIFO_OVF_L3` reader - This raw interrupt bit turns to high level when level 3 fifo of Rx channel 0 is overflow."]
+pub type INFIFO_OVF_L3_R = crate::BitReader;
+#[doc = "Field `INFIFO_OVF_L3` writer - This raw interrupt bit turns to high level when level 3 fifo of Rx channel 0 is overflow."]
+pub type INFIFO_OVF_L3_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `INFIFO_UDF_L3` reader - This raw interrupt bit turns to high level when level 3 fifo of Rx channel 0 is underflow."]
+pub type INFIFO_UDF_L3_R = crate::BitReader;
+#[doc = "Field `INFIFO_UDF_L3` writer - This raw interrupt bit turns to high level when level 3 fifo of Rx channel 0 is underflow."]
+pub type INFIFO_UDF_L3_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0."]
+    #[inline(always)]
+    pub fn in_done(&self) -> IN_DONE_R {
+        IN_DONE_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0."]
+    #[inline(always)]
+    pub fn in_suc_eof(&self) -> IN_SUC_EOF_R {
+        IN_SUC_EOF_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved."]
+    #[inline(always)]
+    pub fn in_err_eof(&self) -> IN_ERR_EOF_R {
+        IN_ERR_EOF_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0."]
+    #[inline(always)]
+    pub fn in_dscr_err(&self) -> IN_DSCR_ERR_R {
+        IN_DSCR_ERR_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0."]
+    #[inline(always)]
+    pub fn in_dscr_empty(&self) -> IN_DSCR_EMPTY_R {
+        IN_DSCR_EMPTY_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - The raw interrupt bit turns to high level when received data byte number is up to threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 0."]
+    #[inline(always)]
+    pub fn infifo_full_wm(&self) -> INFIFO_FULL_WM_R {
+        INFIFO_FULL_WM_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow."]
+    #[inline(always)]
+    pub fn infifo_ovf_l1(&self) -> INFIFO_OVF_L1_R {
+        INFIFO_OVF_L1_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow."]
+    #[inline(always)]
+    pub fn infifo_udf_l1(&self) -> INFIFO_UDF_L1_R {
+        INFIFO_UDF_L1_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - This raw interrupt bit turns to high level when level 3 fifo of Rx channel 0 is overflow."]
+    #[inline(always)]
+    pub fn infifo_ovf_l3(&self) -> INFIFO_OVF_L3_R {
+        INFIFO_OVF_L3_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - This raw interrupt bit turns to high level when level 3 fifo of Rx channel 0 is underflow."]
+    #[inline(always)]
+    pub fn infifo_udf_l3(&self) -> INFIFO_UDF_L3_R {
+        INFIFO_UDF_L3_R::new(((self.bits >> 9) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("RAW")
+            .field("in_done", &self.in_done())
+            .field("in_suc_eof", &self.in_suc_eof())
+            .field("in_err_eof", &self.in_err_eof())
+            .field("in_dscr_err", &self.in_dscr_err())
+            .field("in_dscr_empty", &self.in_dscr_empty())
+            .field("infifo_full_wm", &self.infifo_full_wm())
+            .field("infifo_ovf_l1", &self.infifo_ovf_l1())
+            .field("infifo_udf_l1", &self.infifo_udf_l1())
+            .field("infifo_ovf_l3", &self.infifo_ovf_l3())
+            .field("infifo_udf_l3", &self.infifo_udf_l3())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0."]
+    #[inline(always)]
+    pub fn in_done(&mut self) -> IN_DONE_W<RAW_SPEC> {
+        IN_DONE_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0."]
+    #[inline(always)]
+    pub fn in_suc_eof(&mut self) -> IN_SUC_EOF_W<RAW_SPEC> {
+        IN_SUC_EOF_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved."]
+    #[inline(always)]
+    pub fn in_err_eof(&mut self) -> IN_ERR_EOF_W<RAW_SPEC> {
+        IN_ERR_EOF_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0."]
+    #[inline(always)]
+    pub fn in_dscr_err(&mut self) -> IN_DSCR_ERR_W<RAW_SPEC> {
+        IN_DSCR_ERR_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0."]
+    #[inline(always)]
+    pub fn in_dscr_empty(&mut self) -> IN_DSCR_EMPTY_W<RAW_SPEC> {
+        IN_DSCR_EMPTY_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - The raw interrupt bit turns to high level when received data byte number is up to threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 0."]
+    #[inline(always)]
+    pub fn infifo_full_wm(&mut self) -> INFIFO_FULL_WM_W<RAW_SPEC> {
+        INFIFO_FULL_WM_W::new(self, 5)
+    }
+    #[doc = "Bit 6 - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow."]
+    #[inline(always)]
+    pub fn infifo_ovf_l1(&mut self) -> INFIFO_OVF_L1_W<RAW_SPEC> {
+        INFIFO_OVF_L1_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow."]
+    #[inline(always)]
+    pub fn infifo_udf_l1(&mut self) -> INFIFO_UDF_L1_W<RAW_SPEC> {
+        INFIFO_UDF_L1_W::new(self, 7)
+    }
+    #[doc = "Bit 8 - This raw interrupt bit turns to high level when level 3 fifo of Rx channel 0 is overflow."]
+    #[inline(always)]
+    pub fn infifo_ovf_l3(&mut self) -> INFIFO_OVF_L3_W<RAW_SPEC> {
+        INFIFO_OVF_L3_W::new(self, 8)
+    }
+    #[doc = "Bit 9 - This raw interrupt bit turns to high level when level 3 fifo of Rx channel 0 is underflow."]
+    #[inline(always)]
+    pub fn infifo_udf_l3(&mut self) -> INFIFO_UDF_L3_W<RAW_SPEC> {
+        INFIFO_UDF_L3_W::new(self, 9)
+    }
+}
+#[doc = "Raw status interrupt of Rx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`raw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`raw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct RAW_SPEC;
+impl crate::RegisterSpec for RAW_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`raw::R`](R) reader structure"]
+impl crate::Readable for RAW_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`raw::W`](W) writer structure"]
+impl crate::Writable for RAW_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets RAW to value 0"]
+impl crate::Resettable for RAW_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/dma/ch/in_int/st.rs

@@ -0,0 +1,102 @@
+#[doc = "Register `ST` reader"]
+pub type R = crate::R<ST_SPEC>;
+#[doc = "Field `IN_DONE` reader - The raw interrupt status bit for the IN_DONE_CH_INT interrupt."]
+pub type IN_DONE_R = crate::BitReader;
+#[doc = "Field `IN_SUC_EOF` reader - The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt."]
+pub type IN_SUC_EOF_R = crate::BitReader;
+#[doc = "Field `IN_ERR_EOF` reader - The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt."]
+pub type IN_ERR_EOF_R = crate::BitReader;
+#[doc = "Field `IN_DSCR_ERR` reader - The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt."]
+pub type IN_DSCR_ERR_R = crate::BitReader;
+#[doc = "Field `IN_DSCR_EMPTY` reader - The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt."]
+pub type IN_DSCR_EMPTY_R = crate::BitReader;
+#[doc = "Field `INFIFO_FULL_WM` reader - The raw interrupt status bit for the INFIFO_FULL_WM_CH_INT interrupt."]
+pub type INFIFO_FULL_WM_R = crate::BitReader;
+#[doc = "Field `INFIFO_OVF_L1` reader - The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt."]
+pub type INFIFO_OVF_L1_R = crate::BitReader;
+#[doc = "Field `INFIFO_UDF_L1` reader - The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt."]
+pub type INFIFO_UDF_L1_R = crate::BitReader;
+#[doc = "Field `INFIFO_OVF_L3` reader - The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt."]
+pub type INFIFO_OVF_L3_R = crate::BitReader;
+#[doc = "Field `INFIFO_UDF_L3` reader - The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt."]
+pub type INFIFO_UDF_L3_R = crate::BitReader;
+impl R {
+    #[doc = "Bit 0 - The raw interrupt status bit for the IN_DONE_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn in_done(&self) -> IN_DONE_R {
+        IN_DONE_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn in_suc_eof(&self) -> IN_SUC_EOF_R {
+        IN_SUC_EOF_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn in_err_eof(&self) -> IN_ERR_EOF_R {
+        IN_ERR_EOF_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn in_dscr_err(&self) -> IN_DSCR_ERR_R {
+        IN_DSCR_ERR_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn in_dscr_empty(&self) -> IN_DSCR_EMPTY_R {
+        IN_DSCR_EMPTY_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - The raw interrupt status bit for the INFIFO_FULL_WM_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn infifo_full_wm(&self) -> INFIFO_FULL_WM_R {
+        INFIFO_FULL_WM_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn infifo_ovf_l1(&self) -> INFIFO_OVF_L1_R {
+        INFIFO_OVF_L1_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn infifo_udf_l1(&self) -> INFIFO_UDF_L1_R {
+        INFIFO_UDF_L1_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn infifo_ovf_l3(&self) -> INFIFO_OVF_L3_R {
+        INFIFO_OVF_L3_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn infifo_udf_l3(&self) -> INFIFO_UDF_L3_R {
+        INFIFO_UDF_L3_R::new(((self.bits >> 9) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("ST")
+            .field("in_done", &self.in_done())
+            .field("in_suc_eof", &self.in_suc_eof())
+            .field("in_err_eof", &self.in_err_eof())
+            .field("in_dscr_err", &self.in_dscr_err())
+            .field("in_dscr_empty", &self.in_dscr_empty())
+            .field("infifo_full_wm", &self.infifo_full_wm())
+            .field("infifo_ovf_l1", &self.infifo_ovf_l1())
+            .field("infifo_udf_l1", &self.infifo_udf_l1())
+            .field("infifo_ovf_l3", &self.infifo_ovf_l3())
+            .field("infifo_udf_l3", &self.infifo_udf_l3())
+            .finish()
+    }
+}
+#[doc = "Masked interrupt of Rx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ST_SPEC;
+impl crate::RegisterSpec for ST_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`st::R`](R) reader structure"]
+impl crate::Readable for ST_SPEC {}
+#[doc = "`reset()` method sets ST to value 0"]
+impl crate::Resettable for ST_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/dma/ch/in_link.rs

@@ -0,0 +1,115 @@
+#[doc = "Register `IN_LINK` reader"]
+pub type R = crate::R<IN_LINK_SPEC>;
+#[doc = "Register `IN_LINK` writer"]
+pub type W = crate::W<IN_LINK_SPEC>;
+#[doc = "Field `INLINK_ADDR` reader - This register stores the 20 least significant bits of the first inlink descriptor's address."]
+pub type INLINK_ADDR_R = crate::FieldReader<u32>;
+#[doc = "Field `INLINK_ADDR` writer - This register stores the 20 least significant bits of the first inlink descriptor's address."]
+pub type INLINK_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>;
+#[doc = "Field `INLINK_AUTO_RET` reader - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data."]
+pub type INLINK_AUTO_RET_R = crate::BitReader;
+#[doc = "Field `INLINK_AUTO_RET` writer - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data."]
+pub type INLINK_AUTO_RET_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `INLINK_STOP` reader - Set this bit to stop dealing with the inlink descriptors."]
+pub type INLINK_STOP_R = crate::BitReader;
+#[doc = "Field `INLINK_STOP` writer - Set this bit to stop dealing with the inlink descriptors."]
+pub type INLINK_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `INLINK_START` reader - Set this bit to start dealing with the inlink descriptors."]
+pub type INLINK_START_R = crate::BitReader;
+#[doc = "Field `INLINK_START` writer - Set this bit to start dealing with the inlink descriptors."]
+pub type INLINK_START_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `INLINK_RESTART` reader - Set this bit to mount a new inlink descriptor."]
+pub type INLINK_RESTART_R = crate::BitReader;
+#[doc = "Field `INLINK_RESTART` writer - Set this bit to mount a new inlink descriptor."]
+pub type INLINK_RESTART_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `INLINK_PARK` reader - 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working."]
+pub type INLINK_PARK_R = crate::BitReader;
+impl R {
+    #[doc = "Bits 0:19 - This register stores the 20 least significant bits of the first inlink descriptor's address."]
+    #[inline(always)]
+    pub fn inlink_addr(&self) -> INLINK_ADDR_R {
+        INLINK_ADDR_R::new(self.bits & 0x000f_ffff)
+    }
+    #[doc = "Bit 20 - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data."]
+    #[inline(always)]
+    pub fn inlink_auto_ret(&self) -> INLINK_AUTO_RET_R {
+        INLINK_AUTO_RET_R::new(((self.bits >> 20) & 1) != 0)
+    }
+    #[doc = "Bit 21 - Set this bit to stop dealing with the inlink descriptors."]
+    #[inline(always)]
+    pub fn inlink_stop(&self) -> INLINK_STOP_R {
+        INLINK_STOP_R::new(((self.bits >> 21) & 1) != 0)
+    }
+    #[doc = "Bit 22 - Set this bit to start dealing with the inlink descriptors."]
+    #[inline(always)]
+    pub fn inlink_start(&self) -> INLINK_START_R {
+        INLINK_START_R::new(((self.bits >> 22) & 1) != 0)
+    }
+    #[doc = "Bit 23 - Set this bit to mount a new inlink descriptor."]
+    #[inline(always)]
+    pub fn inlink_restart(&self) -> INLINK_RESTART_R {
+        INLINK_RESTART_R::new(((self.bits >> 23) & 1) != 0)
+    }
+    #[doc = "Bit 24 - 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working."]
+    #[inline(always)]
+    pub fn inlink_park(&self) -> INLINK_PARK_R {
+        INLINK_PARK_R::new(((self.bits >> 24) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("IN_LINK")
+            .field("inlink_addr", &self.inlink_addr())
+            .field("inlink_auto_ret", &self.inlink_auto_ret())
+            .field("inlink_stop", &self.inlink_stop())
+            .field("inlink_start", &self.inlink_start())
+            .field("inlink_restart", &self.inlink_restart())
+            .field("inlink_park", &self.inlink_park())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:19 - This register stores the 20 least significant bits of the first inlink descriptor's address."]
+    #[inline(always)]
+    pub fn inlink_addr(&mut self) -> INLINK_ADDR_W<IN_LINK_SPEC> {
+        INLINK_ADDR_W::new(self, 0)
+    }
+    #[doc = "Bit 20 - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data."]
+    #[inline(always)]
+    pub fn inlink_auto_ret(&mut self) -> INLINK_AUTO_RET_W<IN_LINK_SPEC> {
+        INLINK_AUTO_RET_W::new(self, 20)
+    }
+    #[doc = "Bit 21 - Set this bit to stop dealing with the inlink descriptors."]
+    #[inline(always)]
+    pub fn inlink_stop(&mut self) -> INLINK_STOP_W<IN_LINK_SPEC> {
+        INLINK_STOP_W::new(self, 21)
+    }
+    #[doc = "Bit 22 - Set this bit to start dealing with the inlink descriptors."]
+    #[inline(always)]
+    pub fn inlink_start(&mut self) -> INLINK_START_W<IN_LINK_SPEC> {
+        INLINK_START_W::new(self, 22)
+    }
+    #[doc = "Bit 23 - Set this bit to mount a new inlink descriptor."]
+    #[inline(always)]
+    pub fn inlink_restart(&mut self) -> INLINK_RESTART_W<IN_LINK_SPEC> {
+        INLINK_RESTART_W::new(self, 23)
+    }
+}
+#[doc = "Link descriptor configure and control register of Rx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`in_link::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_link::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct IN_LINK_SPEC;
+impl crate::RegisterSpec for IN_LINK_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`in_link::R`](R) reader structure"]
+impl crate::Readable for IN_LINK_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`in_link::W`](W) writer structure"]
+impl crate::Writable for IN_LINK_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets IN_LINK to value 0x0110_0000"]
+impl crate::Resettable for IN_LINK_SPEC {
+    const RESET_VALUE: u32 = 0x0110_0000;
+}

vendor/esp32s3/src/dma/ch/in_peri_sel.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `IN_PERI_SEL` reader"]
+pub type R = crate::R<IN_PERI_SEL_SPEC>;
+#[doc = "Register `IN_PERI_SEL` writer"]
+pub type W = crate::W<IN_PERI_SEL_SPEC>;
+#[doc = "Field `PERI_IN_SEL` reader - This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: SPI3. 2: UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT."]
+pub type PERI_IN_SEL_R = crate::FieldReader;
+#[doc = "Field `PERI_IN_SEL` writer - This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: SPI3. 2: UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT."]
+pub type PERI_IN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
+impl R {
+    #[doc = "Bits 0:5 - This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: SPI3. 2: UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT."]
+    #[inline(always)]
+    pub fn peri_in_sel(&self) -> PERI_IN_SEL_R {
+        PERI_IN_SEL_R::new((self.bits & 0x3f) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("IN_PERI_SEL")
+            .field("peri_in_sel", &self.peri_in_sel())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:5 - This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: SPI3. 2: UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT."]
+    #[inline(always)]
+    pub fn peri_in_sel(&mut self) -> PERI_IN_SEL_W<IN_PERI_SEL_SPEC> {
+        PERI_IN_SEL_W::new(self, 0)
+    }
+}
+#[doc = "Peripheral selection of Rx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`in_peri_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_peri_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct IN_PERI_SEL_SPEC;
+impl crate::RegisterSpec for IN_PERI_SEL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`in_peri_sel::R`](R) reader structure"]
+impl crate::Readable for IN_PERI_SEL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`in_peri_sel::W`](W) writer structure"]
+impl crate::Writable for IN_PERI_SEL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets IN_PERI_SEL to value 0x3f"]
+impl crate::Resettable for IN_PERI_SEL_SPEC {
+    const RESET_VALUE: u32 = 0x3f;
+}

vendor/esp32s3/src/dma/ch/in_pop.rs

@@ -0,0 +1,55 @@
+#[doc = "Register `IN_POP` reader"]
+pub type R = crate::R<IN_POP_SPEC>;
+#[doc = "Register `IN_POP` writer"]
+pub type W = crate::W<IN_POP_SPEC>;
+#[doc = "Field `INFIFO_RDATA` reader - This register stores the data popping from DMA FIFO."]
+pub type INFIFO_RDATA_R = crate::FieldReader<u16>;
+#[doc = "Field `INFIFO_POP` reader - Set this bit to pop data from DMA FIFO."]
+pub type INFIFO_POP_R = crate::BitReader;
+#[doc = "Field `INFIFO_POP` writer - Set this bit to pop data from DMA FIFO."]
+pub type INFIFO_POP_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 0:11 - This register stores the data popping from DMA FIFO."]
+    #[inline(always)]
+    pub fn infifo_rdata(&self) -> INFIFO_RDATA_R {
+        INFIFO_RDATA_R::new((self.bits & 0x0fff) as u16)
+    }
+    #[doc = "Bit 12 - Set this bit to pop data from DMA FIFO."]
+    #[inline(always)]
+    pub fn infifo_pop(&self) -> INFIFO_POP_R {
+        INFIFO_POP_R::new(((self.bits >> 12) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("IN_POP")
+            .field("infifo_rdata", &self.infifo_rdata())
+            .field("infifo_pop", &self.infifo_pop())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 12 - Set this bit to pop data from DMA FIFO."]
+    #[inline(always)]
+    pub fn infifo_pop(&mut self) -> INFIFO_POP_W<IN_POP_SPEC> {
+        INFIFO_POP_W::new(self, 12)
+    }
+}
+#[doc = "Pop control register of Rx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`in_pop::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_pop::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct IN_POP_SPEC;
+impl crate::RegisterSpec for IN_POP_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`in_pop::R`](R) reader structure"]
+impl crate::Readable for IN_POP_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`in_pop::W`](W) writer structure"]
+impl crate::Writable for IN_POP_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets IN_POP to value 0x0800"]
+impl crate::Resettable for IN_POP_SPEC {
+    const RESET_VALUE: u32 = 0x0800;
+}

vendor/esp32s3/src/dma/ch/in_pri.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `IN_PRI` reader"]
+pub type R = crate::R<IN_PRI_SPEC>;
+#[doc = "Register `IN_PRI` writer"]
+pub type W = crate::W<IN_PRI_SPEC>;
+#[doc = "Field `RX_PRI` reader - The priority of Rx channel 0. The larger of the value, the higher of the priority."]
+pub type RX_PRI_R = crate::FieldReader;
+#[doc = "Field `RX_PRI` writer - The priority of Rx channel 0. The larger of the value, the higher of the priority."]
+pub type RX_PRI_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+impl R {
+    #[doc = "Bits 0:3 - The priority of Rx channel 0. The larger of the value, the higher of the priority."]
+    #[inline(always)]
+    pub fn rx_pri(&self) -> RX_PRI_R {
+        RX_PRI_R::new((self.bits & 0x0f) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("IN_PRI")
+            .field("rx_pri", &self.rx_pri())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:3 - The priority of Rx channel 0. The larger of the value, the higher of the priority."]
+    #[inline(always)]
+    pub fn rx_pri(&mut self) -> RX_PRI_W<IN_PRI_SPEC> {
+        RX_PRI_W::new(self, 0)
+    }
+}
+#[doc = "Priority register of Rx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`in_pri::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_pri::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct IN_PRI_SPEC;
+impl crate::RegisterSpec for IN_PRI_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`in_pri::R`](R) reader structure"]
+impl crate::Readable for IN_PRI_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`in_pri::W`](W) writer structure"]
+impl crate::Writable for IN_PRI_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets IN_PRI to value 0"]
+impl crate::Resettable for IN_PRI_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/dma/ch/in_state.rs

@@ -0,0 +1,46 @@
+#[doc = "Register `IN_STATE` reader"]
+pub type R = crate::R<IN_STATE_SPEC>;
+#[doc = "Field `INLINK_DSCR_ADDR` reader - This register stores the current inlink descriptor's address."]
+pub type INLINK_DSCR_ADDR_R = crate::FieldReader<u32>;
+#[doc = "Field `IN_DSCR_STATE` reader - reserved"]
+pub type IN_DSCR_STATE_R = crate::FieldReader;
+#[doc = "Field `IN_STATE` reader - reserved"]
+pub type IN_STATE_R = crate::FieldReader;
+impl R {
+    #[doc = "Bits 0:17 - This register stores the current inlink descriptor's address."]
+    #[inline(always)]
+    pub fn inlink_dscr_addr(&self) -> INLINK_DSCR_ADDR_R {
+        INLINK_DSCR_ADDR_R::new(self.bits & 0x0003_ffff)
+    }
+    #[doc = "Bits 18:19 - reserved"]
+    #[inline(always)]
+    pub fn in_dscr_state(&self) -> IN_DSCR_STATE_R {
+        IN_DSCR_STATE_R::new(((self.bits >> 18) & 3) as u8)
+    }
+    #[doc = "Bits 20:22 - reserved"]
+    #[inline(always)]
+    pub fn in_state(&self) -> IN_STATE_R {
+        IN_STATE_R::new(((self.bits >> 20) & 7) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("IN_STATE")
+            .field("inlink_dscr_addr", &self.inlink_dscr_addr())
+            .field("in_dscr_state", &self.in_dscr_state())
+            .field("in_state", &self.in_state())
+            .finish()
+    }
+}
+#[doc = "Receive status of Rx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`in_state::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct IN_STATE_SPEC;
+impl crate::RegisterSpec for IN_STATE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`in_state::R`](R) reader structure"]
+impl crate::Readable for IN_STATE_SPEC {}
+#[doc = "`reset()` method sets IN_STATE to value 0"]
+impl crate::Resettable for IN_STATE_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/dma/ch/in_suc_eof_des_addr.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `IN_SUC_EOF_DES_ADDR` reader"]
+pub type R = crate::R<IN_SUC_EOF_DES_ADDR_SPEC>;
+#[doc = "Field `IN_SUC_EOF_DES_ADDR` reader - This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1."]
+pub type IN_SUC_EOF_DES_ADDR_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1."]
+    #[inline(always)]
+    pub fn in_suc_eof_des_addr(&self) -> IN_SUC_EOF_DES_ADDR_R {
+        IN_SUC_EOF_DES_ADDR_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("IN_SUC_EOF_DES_ADDR")
+            .field("in_suc_eof_des_addr", &self.in_suc_eof_des_addr())
+            .finish()
+    }
+}
+#[doc = "Inlink descriptor address when EOF occurs of Rx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`in_suc_eof_des_addr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct IN_SUC_EOF_DES_ADDR_SPEC;
+impl crate::RegisterSpec for IN_SUC_EOF_DES_ADDR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`in_suc_eof_des_addr::R`](R) reader structure"]
+impl crate::Readable for IN_SUC_EOF_DES_ADDR_SPEC {}
+#[doc = "`reset()` method sets IN_SUC_EOF_DES_ADDR to value 0"]
+impl crate::Resettable for IN_SUC_EOF_DES_ADDR_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/dma/ch/in_wight.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `IN_WIGHT` reader"]
+pub type R = crate::R<IN_WIGHT_SPEC>;
+#[doc = "Register `IN_WIGHT` writer"]
+pub type W = crate::W<IN_WIGHT_SPEC>;
+#[doc = "Field `RX_WEIGHT` reader - The weight of Rx channel 0."]
+pub type RX_WEIGHT_R = crate::FieldReader;
+#[doc = "Field `RX_WEIGHT` writer - The weight of Rx channel 0."]
+pub type RX_WEIGHT_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+impl R {
+    #[doc = "Bits 8:11 - The weight of Rx channel 0."]
+    #[inline(always)]
+    pub fn rx_weight(&self) -> RX_WEIGHT_R {
+        RX_WEIGHT_R::new(((self.bits >> 8) & 0x0f) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("IN_WIGHT")
+            .field("rx_weight", &self.rx_weight())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 8:11 - The weight of Rx channel 0."]
+    #[inline(always)]
+    pub fn rx_weight(&mut self) -> RX_WEIGHT_W<IN_WIGHT_SPEC> {
+        RX_WEIGHT_W::new(self, 8)
+    }
+}
+#[doc = "Weight register of Rx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`in_wight::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_wight::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct IN_WIGHT_SPEC;
+impl crate::RegisterSpec for IN_WIGHT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`in_wight::R`](R) reader structure"]
+impl crate::Readable for IN_WIGHT_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`in_wight::W`](W) writer structure"]
+impl crate::Writable for IN_WIGHT_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets IN_WIGHT to value 0x0f00"]
+impl crate::Resettable for IN_WIGHT_SPEC {
+    const RESET_VALUE: u32 = 0x0f00;
+}

vendor/esp32s3/src/dma/ch/infifo_status.rs

@@ -0,0 +1,134 @@
+#[doc = "Register `INFIFO_STATUS` reader"]
+pub type R = crate::R<INFIFO_STATUS_SPEC>;
+#[doc = "Field `INFIFO_FULL_L1` reader - L1 Rx FIFO full signal for Rx channel 0."]
+pub type INFIFO_FULL_L1_R = crate::BitReader;
+#[doc = "Field `INFIFO_EMPTY_L1` reader - L1 Rx FIFO empty signal for Rx channel 0."]
+pub type INFIFO_EMPTY_L1_R = crate::BitReader;
+#[doc = "Field `INFIFO_FULL_L2` reader - L2 Rx FIFO full signal for Rx channel 0."]
+pub type INFIFO_FULL_L2_R = crate::BitReader;
+#[doc = "Field `INFIFO_EMPTY_L2` reader - L2 Rx FIFO empty signal for Rx channel 0."]
+pub type INFIFO_EMPTY_L2_R = crate::BitReader;
+#[doc = "Field `INFIFO_FULL_L3` reader - L3 Rx FIFO full signal for Rx channel 0."]
+pub type INFIFO_FULL_L3_R = crate::BitReader;
+#[doc = "Field `INFIFO_EMPTY_L3` reader - L3 Rx FIFO empty signal for Rx channel 0."]
+pub type INFIFO_EMPTY_L3_R = crate::BitReader;
+#[doc = "Field `INFIFO_CNT_L1` reader - The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0."]
+pub type INFIFO_CNT_L1_R = crate::FieldReader;
+#[doc = "Field `INFIFO_CNT_L2` reader - The register stores the byte number of the data in L2 Rx FIFO for Rx channel 0."]
+pub type INFIFO_CNT_L2_R = crate::FieldReader;
+#[doc = "Field `INFIFO_CNT_L3` reader - The register stores the byte number of the data in L3 Rx FIFO for Rx channel 0."]
+pub type INFIFO_CNT_L3_R = crate::FieldReader;
+#[doc = "Field `IN_REMAIN_UNDER_1B_L3` reader - reserved"]
+pub type IN_REMAIN_UNDER_1B_L3_R = crate::BitReader;
+#[doc = "Field `IN_REMAIN_UNDER_2B_L3` reader - reserved"]
+pub type IN_REMAIN_UNDER_2B_L3_R = crate::BitReader;
+#[doc = "Field `IN_REMAIN_UNDER_3B_L3` reader - reserved"]
+pub type IN_REMAIN_UNDER_3B_L3_R = crate::BitReader;
+#[doc = "Field `IN_REMAIN_UNDER_4B_L3` reader - reserved"]
+pub type IN_REMAIN_UNDER_4B_L3_R = crate::BitReader;
+#[doc = "Field `IN_BUF_HUNGRY` reader - reserved"]
+pub type IN_BUF_HUNGRY_R = crate::BitReader;
+impl R {
+    #[doc = "Bit 0 - L1 Rx FIFO full signal for Rx channel 0."]
+    #[inline(always)]
+    pub fn infifo_full_l1(&self) -> INFIFO_FULL_L1_R {
+        INFIFO_FULL_L1_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - L1 Rx FIFO empty signal for Rx channel 0."]
+    #[inline(always)]
+    pub fn infifo_empty_l1(&self) -> INFIFO_EMPTY_L1_R {
+        INFIFO_EMPTY_L1_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - L2 Rx FIFO full signal for Rx channel 0."]
+    #[inline(always)]
+    pub fn infifo_full_l2(&self) -> INFIFO_FULL_L2_R {
+        INFIFO_FULL_L2_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - L2 Rx FIFO empty signal for Rx channel 0."]
+    #[inline(always)]
+    pub fn infifo_empty_l2(&self) -> INFIFO_EMPTY_L2_R {
+        INFIFO_EMPTY_L2_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - L3 Rx FIFO full signal for Rx channel 0."]
+    #[inline(always)]
+    pub fn infifo_full_l3(&self) -> INFIFO_FULL_L3_R {
+        INFIFO_FULL_L3_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - L3 Rx FIFO empty signal for Rx channel 0."]
+    #[inline(always)]
+    pub fn infifo_empty_l3(&self) -> INFIFO_EMPTY_L3_R {
+        INFIFO_EMPTY_L3_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bits 6:11 - The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0."]
+    #[inline(always)]
+    pub fn infifo_cnt_l1(&self) -> INFIFO_CNT_L1_R {
+        INFIFO_CNT_L1_R::new(((self.bits >> 6) & 0x3f) as u8)
+    }
+    #[doc = "Bits 12:18 - The register stores the byte number of the data in L2 Rx FIFO for Rx channel 0."]
+    #[inline(always)]
+    pub fn infifo_cnt_l2(&self) -> INFIFO_CNT_L2_R {
+        INFIFO_CNT_L2_R::new(((self.bits >> 12) & 0x7f) as u8)
+    }
+    #[doc = "Bits 19:23 - The register stores the byte number of the data in L3 Rx FIFO for Rx channel 0."]
+    #[inline(always)]
+    pub fn infifo_cnt_l3(&self) -> INFIFO_CNT_L3_R {
+        INFIFO_CNT_L3_R::new(((self.bits >> 19) & 0x1f) as u8)
+    }
+    #[doc = "Bit 24 - reserved"]
+    #[inline(always)]
+    pub fn in_remain_under_1b_l3(&self) -> IN_REMAIN_UNDER_1B_L3_R {
+        IN_REMAIN_UNDER_1B_L3_R::new(((self.bits >> 24) & 1) != 0)
+    }
+    #[doc = "Bit 25 - reserved"]
+    #[inline(always)]
+    pub fn in_remain_under_2b_l3(&self) -> IN_REMAIN_UNDER_2B_L3_R {
+        IN_REMAIN_UNDER_2B_L3_R::new(((self.bits >> 25) & 1) != 0)
+    }
+    #[doc = "Bit 26 - reserved"]
+    #[inline(always)]
+    pub fn in_remain_under_3b_l3(&self) -> IN_REMAIN_UNDER_3B_L3_R {
+        IN_REMAIN_UNDER_3B_L3_R::new(((self.bits >> 26) & 1) != 0)
+    }
+    #[doc = "Bit 27 - reserved"]
+    #[inline(always)]
+    pub fn in_remain_under_4b_l3(&self) -> IN_REMAIN_UNDER_4B_L3_R {
+        IN_REMAIN_UNDER_4B_L3_R::new(((self.bits >> 27) & 1) != 0)
+    }
+    #[doc = "Bit 28 - reserved"]
+    #[inline(always)]
+    pub fn in_buf_hungry(&self) -> IN_BUF_HUNGRY_R {
+        IN_BUF_HUNGRY_R::new(((self.bits >> 28) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("INFIFO_STATUS")
+            .field("infifo_full_l1", &self.infifo_full_l1())
+            .field("infifo_empty_l1", &self.infifo_empty_l1())
+            .field("infifo_full_l2", &self.infifo_full_l2())
+            .field("infifo_empty_l2", &self.infifo_empty_l2())
+            .field("infifo_full_l3", &self.infifo_full_l3())
+            .field("infifo_empty_l3", &self.infifo_empty_l3())
+            .field("infifo_cnt_l1", &self.infifo_cnt_l1())
+            .field("infifo_cnt_l2", &self.infifo_cnt_l2())
+            .field("infifo_cnt_l3", &self.infifo_cnt_l3())
+            .field("in_remain_under_1b_l3", &self.in_remain_under_1b_l3())
+            .field("in_remain_under_2b_l3", &self.in_remain_under_2b_l3())
+            .field("in_remain_under_3b_l3", &self.in_remain_under_3b_l3())
+            .field("in_remain_under_4b_l3", &self.in_remain_under_4b_l3())
+            .field("in_buf_hungry", &self.in_buf_hungry())
+            .finish()
+    }
+}
+#[doc = "Receive FIFO status of Rx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`infifo_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct INFIFO_STATUS_SPEC;
+impl crate::RegisterSpec for INFIFO_STATUS_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`infifo_status::R`](R) reader structure"]
+impl crate::Readable for INFIFO_STATUS_SPEC {}
+#[doc = "`reset()` method sets INFIFO_STATUS to value 0x0f00_003a"]
+impl crate::Resettable for INFIFO_STATUS_SPEC {
+    const RESET_VALUE: u32 = 0x0f00_003a;
+}

vendor/esp32s3/src/dma/ch/out_conf0.rs

@@ -0,0 +1,122 @@
+#[doc = "Register `OUT_CONF0` reader"]
+pub type R = crate::R<OUT_CONF0_SPEC>;
+#[doc = "Register `OUT_CONF0` writer"]
+pub type W = crate::W<OUT_CONF0_SPEC>;
+#[doc = "Field `OUT_RST` reader - This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer."]
+pub type OUT_RST_R = crate::BitReader;
+#[doc = "Field `OUT_RST` writer - This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer."]
+pub type OUT_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `OUT_LOOP_TEST` reader - reserved"]
+pub type OUT_LOOP_TEST_R = crate::BitReader;
+#[doc = "Field `OUT_LOOP_TEST` writer - reserved"]
+pub type OUT_LOOP_TEST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `OUT_AUTO_WRBACK` reader - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."]
+pub type OUT_AUTO_WRBACK_R = crate::BitReader;
+#[doc = "Field `OUT_AUTO_WRBACK` writer - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."]
+pub type OUT_AUTO_WRBACK_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `OUT_EOF_MODE` reader - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA"]
+pub type OUT_EOF_MODE_R = crate::BitReader;
+#[doc = "Field `OUT_EOF_MODE` writer - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA"]
+pub type OUT_EOF_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `OUTDSCR_BURST_EN` reader - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM."]
+pub type OUTDSCR_BURST_EN_R = crate::BitReader;
+#[doc = "Field `OUTDSCR_BURST_EN` writer - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM."]
+pub type OUTDSCR_BURST_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `OUT_DATA_BURST_EN` reader - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM."]
+pub type OUT_DATA_BURST_EN_R = crate::BitReader;
+#[doc = "Field `OUT_DATA_BURST_EN` writer - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM."]
+pub type OUT_DATA_BURST_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer."]
+    #[inline(always)]
+    pub fn out_rst(&self) -> OUT_RST_R {
+        OUT_RST_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - reserved"]
+    #[inline(always)]
+    pub fn out_loop_test(&self) -> OUT_LOOP_TEST_R {
+        OUT_LOOP_TEST_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."]
+    #[inline(always)]
+    pub fn out_auto_wrback(&self) -> OUT_AUTO_WRBACK_R {
+        OUT_AUTO_WRBACK_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA"]
+    #[inline(always)]
+    pub fn out_eof_mode(&self) -> OUT_EOF_MODE_R {
+        OUT_EOF_MODE_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM."]
+    #[inline(always)]
+    pub fn outdscr_burst_en(&self) -> OUTDSCR_BURST_EN_R {
+        OUTDSCR_BURST_EN_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM."]
+    #[inline(always)]
+    pub fn out_data_burst_en(&self) -> OUT_DATA_BURST_EN_R {
+        OUT_DATA_BURST_EN_R::new(((self.bits >> 5) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("OUT_CONF0")
+            .field("out_rst", &self.out_rst())
+            .field("out_loop_test", &self.out_loop_test())
+            .field("out_auto_wrback", &self.out_auto_wrback())
+            .field("out_eof_mode", &self.out_eof_mode())
+            .field("outdscr_burst_en", &self.outdscr_burst_en())
+            .field("out_data_burst_en", &self.out_data_burst_en())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer."]
+    #[inline(always)]
+    pub fn out_rst(&mut self) -> OUT_RST_W<OUT_CONF0_SPEC> {
+        OUT_RST_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - reserved"]
+    #[inline(always)]
+    pub fn out_loop_test(&mut self) -> OUT_LOOP_TEST_W<OUT_CONF0_SPEC> {
+        OUT_LOOP_TEST_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted."]
+    #[inline(always)]
+    pub fn out_auto_wrback(&mut self) -> OUT_AUTO_WRBACK_W<OUT_CONF0_SPEC> {
+        OUT_AUTO_WRBACK_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA"]
+    #[inline(always)]
+    pub fn out_eof_mode(&mut self) -> OUT_EOF_MODE_W<OUT_CONF0_SPEC> {
+        OUT_EOF_MODE_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM."]
+    #[inline(always)]
+    pub fn outdscr_burst_en(&mut self) -> OUTDSCR_BURST_EN_W<OUT_CONF0_SPEC> {
+        OUTDSCR_BURST_EN_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM."]
+    #[inline(always)]
+    pub fn out_data_burst_en(&mut self) -> OUT_DATA_BURST_EN_W<OUT_CONF0_SPEC> {
+        OUT_DATA_BURST_EN_W::new(self, 5)
+    }
+}
+#[doc = "Configure 0 register of Tx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`out_conf0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`out_conf0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct OUT_CONF0_SPEC;
+impl crate::RegisterSpec for OUT_CONF0_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`out_conf0::R`](R) reader structure"]
+impl crate::Readable for OUT_CONF0_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`out_conf0::W`](W) writer structure"]
+impl crate::Writable for OUT_CONF0_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets OUT_CONF0 to value 0x08"]
+impl crate::Resettable for OUT_CONF0_SPEC {
+    const RESET_VALUE: u32 = 0x08;
+}

vendor/esp32s3/src/dma/ch/out_conf1.rs

@@ -0,0 +1,62 @@
+#[doc = "Register `OUT_CONF1` reader"]
+pub type R = crate::R<OUT_CONF1_SPEC>;
+#[doc = "Register `OUT_CONF1` writer"]
+pub type W = crate::W<OUT_CONF1_SPEC>;
+#[doc = "Field `OUT_CHECK_OWNER` reader - Set this bit to enable checking the owner attribute of the link descriptor."]
+pub type OUT_CHECK_OWNER_R = crate::BitReader;
+#[doc = "Field `OUT_CHECK_OWNER` writer - Set this bit to enable checking the owner attribute of the link descriptor."]
+pub type OUT_CHECK_OWNER_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `OUT_EXT_MEM_BK_SIZE` reader - Block size of Tx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved"]
+pub type OUT_EXT_MEM_BK_SIZE_R = crate::FieldReader;
+#[doc = "Field `OUT_EXT_MEM_BK_SIZE` writer - Block size of Tx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved"]
+pub type OUT_EXT_MEM_BK_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+impl R {
+    #[doc = "Bit 12 - Set this bit to enable checking the owner attribute of the link descriptor."]
+    #[inline(always)]
+    pub fn out_check_owner(&self) -> OUT_CHECK_OWNER_R {
+        OUT_CHECK_OWNER_R::new(((self.bits >> 12) & 1) != 0)
+    }
+    #[doc = "Bits 13:14 - Block size of Tx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved"]
+    #[inline(always)]
+    pub fn out_ext_mem_bk_size(&self) -> OUT_EXT_MEM_BK_SIZE_R {
+        OUT_EXT_MEM_BK_SIZE_R::new(((self.bits >> 13) & 3) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("OUT_CONF1")
+            .field("out_check_owner", &self.out_check_owner())
+            .field("out_ext_mem_bk_size", &self.out_ext_mem_bk_size())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 12 - Set this bit to enable checking the owner attribute of the link descriptor."]
+    #[inline(always)]
+    pub fn out_check_owner(&mut self) -> OUT_CHECK_OWNER_W<OUT_CONF1_SPEC> {
+        OUT_CHECK_OWNER_W::new(self, 12)
+    }
+    #[doc = "Bits 13:14 - Block size of Tx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved"]
+    #[inline(always)]
+    pub fn out_ext_mem_bk_size(&mut self) -> OUT_EXT_MEM_BK_SIZE_W<OUT_CONF1_SPEC> {
+        OUT_EXT_MEM_BK_SIZE_W::new(self, 13)
+    }
+}
+#[doc = "Configure 1 register of Tx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`out_conf1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`out_conf1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct OUT_CONF1_SPEC;
+impl crate::RegisterSpec for OUT_CONF1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`out_conf1::R`](R) reader structure"]
+impl crate::Readable for OUT_CONF1_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`out_conf1::W`](W) writer structure"]
+impl crate::Writable for OUT_CONF1_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets OUT_CONF1 to value 0"]
+impl crate::Resettable for OUT_CONF1_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/dma/ch/out_dscr.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `OUT_DSCR` reader"]
+pub type R = crate::R<OUT_DSCR_SPEC>;
+#[doc = "Field `OUTLINK_DSCR` reader - The address of the current outlink descriptor y."]
+pub type OUTLINK_DSCR_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - The address of the current outlink descriptor y."]
+    #[inline(always)]
+    pub fn outlink_dscr(&self) -> OUTLINK_DSCR_R {
+        OUTLINK_DSCR_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("OUT_DSCR")
+            .field("outlink_dscr", &self.outlink_dscr())
+            .finish()
+    }
+}
+#[doc = "Current inlink descriptor address of Tx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`out_dscr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct OUT_DSCR_SPEC;
+impl crate::RegisterSpec for OUT_DSCR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`out_dscr::R`](R) reader structure"]
+impl crate::Readable for OUT_DSCR_SPEC {}
+#[doc = "`reset()` method sets OUT_DSCR to value 0"]
+impl crate::Resettable for OUT_DSCR_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/dma/ch/out_dscr_bf0.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `OUT_DSCR_BF0` reader"]
+pub type R = crate::R<OUT_DSCR_BF0_SPEC>;
+#[doc = "Field `OUTLINK_DSCR_BF0` reader - The address of the last outlink descriptor y-1."]
+pub type OUTLINK_DSCR_BF0_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - The address of the last outlink descriptor y-1."]
+    #[inline(always)]
+    pub fn outlink_dscr_bf0(&self) -> OUTLINK_DSCR_BF0_R {
+        OUTLINK_DSCR_BF0_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("OUT_DSCR_BF0")
+            .field("outlink_dscr_bf0", &self.outlink_dscr_bf0())
+            .finish()
+    }
+}
+#[doc = "The last inlink descriptor address of Tx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`out_dscr_bf0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct OUT_DSCR_BF0_SPEC;
+impl crate::RegisterSpec for OUT_DSCR_BF0_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`out_dscr_bf0::R`](R) reader structure"]
+impl crate::Readable for OUT_DSCR_BF0_SPEC {}
+#[doc = "`reset()` method sets OUT_DSCR_BF0 to value 0"]
+impl crate::Resettable for OUT_DSCR_BF0_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/dma/ch/out_dscr_bf1.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `OUT_DSCR_BF1` reader"]
+pub type R = crate::R<OUT_DSCR_BF1_SPEC>;
+#[doc = "Field `OUTLINK_DSCR_BF1` reader - The address of the second-to-last inlink descriptor x-2."]
+pub type OUTLINK_DSCR_BF1_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - The address of the second-to-last inlink descriptor x-2."]
+    #[inline(always)]
+    pub fn outlink_dscr_bf1(&self) -> OUTLINK_DSCR_BF1_R {
+        OUTLINK_DSCR_BF1_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("OUT_DSCR_BF1")
+            .field("outlink_dscr_bf1", &self.outlink_dscr_bf1())
+            .finish()
+    }
+}
+#[doc = "The second-to-last inlink descriptor address of Tx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`out_dscr_bf1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct OUT_DSCR_BF1_SPEC;
+impl crate::RegisterSpec for OUT_DSCR_BF1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`out_dscr_bf1::R`](R) reader structure"]
+impl crate::Readable for OUT_DSCR_BF1_SPEC {}
+#[doc = "`reset()` method sets OUT_DSCR_BF1 to value 0"]
+impl crate::Resettable for OUT_DSCR_BF1_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/dma/ch/out_eof_bfr_des_addr.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `OUT_EOF_BFR_DES_ADDR` reader"]
+pub type R = crate::R<OUT_EOF_BFR_DES_ADDR_SPEC>;
+#[doc = "Field `OUT_EOF_BFR_DES_ADDR` reader - This register stores the address of the outlink descriptor before the last outlink descriptor."]
+pub type OUT_EOF_BFR_DES_ADDR_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - This register stores the address of the outlink descriptor before the last outlink descriptor."]
+    #[inline(always)]
+    pub fn out_eof_bfr_des_addr(&self) -> OUT_EOF_BFR_DES_ADDR_R {
+        OUT_EOF_BFR_DES_ADDR_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("OUT_EOF_BFR_DES_ADDR")
+            .field("out_eof_bfr_des_addr", &self.out_eof_bfr_des_addr())
+            .finish()
+    }
+}
+#[doc = "The last outlink descriptor address when EOF occurs of Tx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`out_eof_bfr_des_addr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct OUT_EOF_BFR_DES_ADDR_SPEC;
+impl crate::RegisterSpec for OUT_EOF_BFR_DES_ADDR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`out_eof_bfr_des_addr::R`](R) reader structure"]
+impl crate::Readable for OUT_EOF_BFR_DES_ADDR_SPEC {}
+#[doc = "`reset()` method sets OUT_EOF_BFR_DES_ADDR to value 0"]
+impl crate::Resettable for OUT_EOF_BFR_DES_ADDR_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/dma/ch/out_eof_des_addr.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `OUT_EOF_DES_ADDR` reader"]
+pub type R = crate::R<OUT_EOF_DES_ADDR_SPEC>;
+#[doc = "Field `OUT_EOF_DES_ADDR` reader - This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1."]
+pub type OUT_EOF_DES_ADDR_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1."]
+    #[inline(always)]
+    pub fn out_eof_des_addr(&self) -> OUT_EOF_DES_ADDR_R {
+        OUT_EOF_DES_ADDR_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("OUT_EOF_DES_ADDR")
+            .field("out_eof_des_addr", &self.out_eof_des_addr())
+            .finish()
+    }
+}
+#[doc = "Outlink descriptor address when EOF occurs of Tx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`out_eof_des_addr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct OUT_EOF_DES_ADDR_SPEC;
+impl crate::RegisterSpec for OUT_EOF_DES_ADDR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`out_eof_des_addr::R`](R) reader structure"]
+impl crate::Readable for OUT_EOF_DES_ADDR_SPEC {}
+#[doc = "`reset()` method sets OUT_EOF_DES_ADDR to value 0"]
+impl crate::Resettable for OUT_EOF_DES_ADDR_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/dma/ch/out_int.rs

@@ -0,0 +1,47 @@
+#[repr(C)]
+#[cfg_attr(feature = "impl-register-debug", derive(Debug))]
+#[doc = "Cluster OUT_INT, containing OUT_INT_RAW, OUT_INT_ST, OUT_INT_ENA, OUT_INT_CLR"]
+pub struct OUT_INT {
+    raw: RAW,
+    st: ST,
+    ena: ENA,
+    clr: CLR,
+}
+impl OUT_INT {
+    #[doc = "0x00 - Raw status interrupt of Tx channel 0"]
+    #[inline(always)]
+    pub const fn raw(&self) -> &RAW {
+        &self.raw
+    }
+    #[doc = "0x04 - Masked interrupt of Tx channel 0"]
+    #[inline(always)]
+    pub const fn st(&self) -> &ST {
+        &self.st
+    }
+    #[doc = "0x08 - Interrupt enable bits of Tx channel 0"]
+    #[inline(always)]
+    pub const fn ena(&self) -> &ENA {
+        &self.ena
+    }
+    #[doc = "0x0c - Interrupt clear bits of Tx channel 0"]
+    #[inline(always)]
+    pub const fn clr(&self) -> &CLR {
+        &self.clr
+    }
+}
+#[doc = "RAW (rw) register accessor: Raw status interrupt of Tx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`raw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`raw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@raw`] module"]
+pub type RAW = crate::Reg<raw::RAW_SPEC>;
+#[doc = "Raw status interrupt of Tx channel 0"]
+pub mod raw;
+#[doc = "ST (r) register accessor: Masked interrupt of Tx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@st`] module"]
+pub type ST = crate::Reg<st::ST_SPEC>;
+#[doc = "Masked interrupt of Tx channel 0"]
+pub mod st;
+#[doc = "ENA (rw) register accessor: Interrupt enable bits of Tx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ena::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ena::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ena`] module"]
+pub type ENA = crate::Reg<ena::ENA_SPEC>;
+#[doc = "Interrupt enable bits of Tx channel 0"]
+pub mod ena;
+#[doc = "CLR (w) register accessor: Interrupt clear bits of Tx channel 0\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr`] module"]
+pub type CLR = crate::Reg<clr::CLR_SPEC>;
+#[doc = "Interrupt clear bits of Tx channel 0"]
+pub mod clr;

vendor/esp32s3/src/dma/ch/out_int/clr.rs

@@ -0,0 +1,81 @@
+#[doc = "Register `CLR` writer"]
+pub type W = crate::W<CLR_SPEC>;
+#[doc = "Field `OUT_DONE` writer - Set this bit to clear the OUT_DONE_CH_INT interrupt."]
+pub type OUT_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `OUT_EOF` writer - Set this bit to clear the OUT_EOF_CH_INT interrupt."]
+pub type OUT_EOF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `OUT_DSCR_ERR` writer - Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt."]
+pub type OUT_DSCR_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `OUT_TOTAL_EOF` writer - Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt."]
+pub type OUT_TOTAL_EOF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `OUTFIFO_OVF_L1` writer - Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt."]
+pub type OUTFIFO_OVF_L1_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `OUTFIFO_UDF_L1` writer - Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt."]
+pub type OUTFIFO_UDF_L1_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `OUTFIFO_OVF_L3` writer - Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt."]
+pub type OUTFIFO_OVF_L3_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `OUTFIFO_UDF_L3` writer - Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt."]
+pub type OUTFIFO_UDF_L3_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for crate::generic::Reg<CLR_SPEC> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "(not readable)")
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Set this bit to clear the OUT_DONE_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn out_done(&mut self) -> OUT_DONE_W<CLR_SPEC> {
+        OUT_DONE_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - Set this bit to clear the OUT_EOF_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn out_eof(&mut self) -> OUT_EOF_W<CLR_SPEC> {
+        OUT_EOF_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn out_dscr_err(&mut self) -> OUT_DSCR_ERR_W<CLR_SPEC> {
+        OUT_DSCR_ERR_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn out_total_eof(&mut self) -> OUT_TOTAL_EOF_W<CLR_SPEC> {
+        OUT_TOTAL_EOF_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn outfifo_ovf_l1(&mut self) -> OUTFIFO_OVF_L1_W<CLR_SPEC> {
+        OUTFIFO_OVF_L1_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn outfifo_udf_l1(&mut self) -> OUTFIFO_UDF_L1_W<CLR_SPEC> {
+        OUTFIFO_UDF_L1_W::new(self, 5)
+    }
+    #[doc = "Bit 6 - Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn outfifo_ovf_l3(&mut self) -> OUTFIFO_OVF_L3_W<CLR_SPEC> {
+        OUTFIFO_OVF_L3_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn outfifo_udf_l3(&mut self) -> OUTFIFO_UDF_L3_W<CLR_SPEC> {
+        OUTFIFO_UDF_L3_W::new(self, 7)
+    }
+}
+#[doc = "Interrupt clear bits of Tx channel 0\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CLR_SPEC;
+impl crate::RegisterSpec for CLR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [`clr::W`](W) writer structure"]
+impl crate::Writable for CLR_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xff;
+}
+#[doc = "`reset()` method sets CLR to value 0"]
+impl crate::Resettable for CLR_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/dma/ch/out_int/ena.rs

@@ -0,0 +1,152 @@
+#[doc = "Register `ENA` reader"]
+pub type R = crate::R<ENA_SPEC>;
+#[doc = "Register `ENA` writer"]
+pub type W = crate::W<ENA_SPEC>;
+#[doc = "Field `OUT_DONE` reader - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."]
+pub type OUT_DONE_R = crate::BitReader;
+#[doc = "Field `OUT_DONE` writer - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."]
+pub type OUT_DONE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `OUT_EOF` reader - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."]
+pub type OUT_EOF_R = crate::BitReader;
+#[doc = "Field `OUT_EOF` writer - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."]
+pub type OUT_EOF_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `OUT_DSCR_ERR` reader - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."]
+pub type OUT_DSCR_ERR_R = crate::BitReader;
+#[doc = "Field `OUT_DSCR_ERR` writer - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."]
+pub type OUT_DSCR_ERR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `OUT_TOTAL_EOF` reader - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."]
+pub type OUT_TOTAL_EOF_R = crate::BitReader;
+#[doc = "Field `OUT_TOTAL_EOF` writer - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."]
+pub type OUT_TOTAL_EOF_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `OUTFIFO_OVF_L1` reader - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."]
+pub type OUTFIFO_OVF_L1_R = crate::BitReader;
+#[doc = "Field `OUTFIFO_OVF_L1` writer - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."]
+pub type OUTFIFO_OVF_L1_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `OUTFIFO_UDF_L1` reader - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."]
+pub type OUTFIFO_UDF_L1_R = crate::BitReader;
+#[doc = "Field `OUTFIFO_UDF_L1` writer - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."]
+pub type OUTFIFO_UDF_L1_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `OUTFIFO_OVF_L3` reader - The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt."]
+pub type OUTFIFO_OVF_L3_R = crate::BitReader;
+#[doc = "Field `OUTFIFO_OVF_L3` writer - The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt."]
+pub type OUTFIFO_OVF_L3_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `OUTFIFO_UDF_L3` reader - The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt."]
+pub type OUTFIFO_UDF_L3_R = crate::BitReader;
+#[doc = "Field `OUTFIFO_UDF_L3` writer - The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt."]
+pub type OUTFIFO_UDF_L3_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn out_done(&self) -> OUT_DONE_R {
+        OUT_DONE_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn out_eof(&self) -> OUT_EOF_R {
+        OUT_EOF_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn out_dscr_err(&self) -> OUT_DSCR_ERR_R {
+        OUT_DSCR_ERR_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn out_total_eof(&self) -> OUT_TOTAL_EOF_R {
+        OUT_TOTAL_EOF_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn outfifo_ovf_l1(&self) -> OUTFIFO_OVF_L1_R {
+        OUTFIFO_OVF_L1_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn outfifo_udf_l1(&self) -> OUTFIFO_UDF_L1_R {
+        OUTFIFO_UDF_L1_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn outfifo_ovf_l3(&self) -> OUTFIFO_OVF_L3_R {
+        OUTFIFO_OVF_L3_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn outfifo_udf_l3(&self) -> OUTFIFO_UDF_L3_R {
+        OUTFIFO_UDF_L3_R::new(((self.bits >> 7) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("ENA")
+            .field("out_done", &self.out_done())
+            .field("out_eof", &self.out_eof())
+            .field("out_dscr_err", &self.out_dscr_err())
+            .field("out_total_eof", &self.out_total_eof())
+            .field("outfifo_ovf_l1", &self.outfifo_ovf_l1())
+            .field("outfifo_udf_l1", &self.outfifo_udf_l1())
+            .field("outfifo_ovf_l3", &self.outfifo_ovf_l3())
+            .field("outfifo_udf_l3", &self.outfifo_udf_l3())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn out_done(&mut self) -> OUT_DONE_W<ENA_SPEC> {
+        OUT_DONE_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - The interrupt enable bit for the OUT_EOF_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn out_eof(&mut self) -> OUT_EOF_W<ENA_SPEC> {
+        OUT_EOF_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn out_dscr_err(&mut self) -> OUT_DSCR_ERR_W<ENA_SPEC> {
+        OUT_DSCR_ERR_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn out_total_eof(&mut self) -> OUT_TOTAL_EOF_W<ENA_SPEC> {
+        OUT_TOTAL_EOF_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn outfifo_ovf_l1(&mut self) -> OUTFIFO_OVF_L1_W<ENA_SPEC> {
+        OUTFIFO_OVF_L1_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn outfifo_udf_l1(&mut self) -> OUTFIFO_UDF_L1_W<ENA_SPEC> {
+        OUTFIFO_UDF_L1_W::new(self, 5)
+    }
+    #[doc = "Bit 6 - The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn outfifo_ovf_l3(&mut self) -> OUTFIFO_OVF_L3_W<ENA_SPEC> {
+        OUTFIFO_OVF_L3_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn outfifo_udf_l3(&mut self) -> OUTFIFO_UDF_L3_W<ENA_SPEC> {
+        OUTFIFO_UDF_L3_W::new(self, 7)
+    }
+}
+#[doc = "Interrupt enable bits of Tx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ENA_SPEC;
+impl crate::RegisterSpec for ENA_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`ena::R`](R) reader structure"]
+impl crate::Readable for ENA_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`ena::W`](W) writer structure"]
+impl crate::Writable for ENA_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets ENA to value 0"]
+impl crate::Resettable for ENA_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/dma/ch/out_int/raw.rs

@@ -0,0 +1,152 @@
+#[doc = "Register `RAW` reader"]
+pub type R = crate::R<RAW_SPEC>;
+#[doc = "Register `RAW` writer"]
+pub type W = crate::W<RAW_SPEC>;
+#[doc = "Field `OUT_DONE` reader - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0."]
+pub type OUT_DONE_R = crate::BitReader;
+#[doc = "Field `OUT_DONE` writer - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0."]
+pub type OUT_DONE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `OUT_EOF` reader - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0."]
+pub type OUT_EOF_R = crate::BitReader;
+#[doc = "Field `OUT_EOF` writer - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0."]
+pub type OUT_EOF_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `OUT_DSCR_ERR` reader - The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0."]
+pub type OUT_DSCR_ERR_R = crate::BitReader;
+#[doc = "Field `OUT_DSCR_ERR` writer - The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0."]
+pub type OUT_DSCR_ERR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `OUT_TOTAL_EOF` reader - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0."]
+pub type OUT_TOTAL_EOF_R = crate::BitReader;
+#[doc = "Field `OUT_TOTAL_EOF` writer - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0."]
+pub type OUT_TOTAL_EOF_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `OUTFIFO_OVF_L1` reader - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow."]
+pub type OUTFIFO_OVF_L1_R = crate::BitReader;
+#[doc = "Field `OUTFIFO_OVF_L1` writer - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow."]
+pub type OUTFIFO_OVF_L1_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `OUTFIFO_UDF_L1` reader - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow."]
+pub type OUTFIFO_UDF_L1_R = crate::BitReader;
+#[doc = "Field `OUTFIFO_UDF_L1` writer - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow."]
+pub type OUTFIFO_UDF_L1_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `OUTFIFO_OVF_L3` reader - This raw interrupt bit turns to high level when level 3 fifo of Tx channel 0 is overflow."]
+pub type OUTFIFO_OVF_L3_R = crate::BitReader;
+#[doc = "Field `OUTFIFO_OVF_L3` writer - This raw interrupt bit turns to high level when level 3 fifo of Tx channel 0 is overflow."]
+pub type OUTFIFO_OVF_L3_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `OUTFIFO_UDF_L3` reader - This raw interrupt bit turns to high level when level 3 fifo of Tx channel 0 is underflow."]
+pub type OUTFIFO_UDF_L3_R = crate::BitReader;
+#[doc = "Field `OUTFIFO_UDF_L3` writer - This raw interrupt bit turns to high level when level 3 fifo of Tx channel 0 is underflow."]
+pub type OUTFIFO_UDF_L3_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0."]
+    #[inline(always)]
+    pub fn out_done(&self) -> OUT_DONE_R {
+        OUT_DONE_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0."]
+    #[inline(always)]
+    pub fn out_eof(&self) -> OUT_EOF_R {
+        OUT_EOF_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0."]
+    #[inline(always)]
+    pub fn out_dscr_err(&self) -> OUT_DSCR_ERR_R {
+        OUT_DSCR_ERR_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0."]
+    #[inline(always)]
+    pub fn out_total_eof(&self) -> OUT_TOTAL_EOF_R {
+        OUT_TOTAL_EOF_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow."]
+    #[inline(always)]
+    pub fn outfifo_ovf_l1(&self) -> OUTFIFO_OVF_L1_R {
+        OUTFIFO_OVF_L1_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow."]
+    #[inline(always)]
+    pub fn outfifo_udf_l1(&self) -> OUTFIFO_UDF_L1_R {
+        OUTFIFO_UDF_L1_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - This raw interrupt bit turns to high level when level 3 fifo of Tx channel 0 is overflow."]
+    #[inline(always)]
+    pub fn outfifo_ovf_l3(&self) -> OUTFIFO_OVF_L3_R {
+        OUTFIFO_OVF_L3_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - This raw interrupt bit turns to high level when level 3 fifo of Tx channel 0 is underflow."]
+    #[inline(always)]
+    pub fn outfifo_udf_l3(&self) -> OUTFIFO_UDF_L3_R {
+        OUTFIFO_UDF_L3_R::new(((self.bits >> 7) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("RAW")
+            .field("out_done", &self.out_done())
+            .field("out_eof", &self.out_eof())
+            .field("out_dscr_err", &self.out_dscr_err())
+            .field("out_total_eof", &self.out_total_eof())
+            .field("outfifo_ovf_l1", &self.outfifo_ovf_l1())
+            .field("outfifo_udf_l1", &self.outfifo_udf_l1())
+            .field("outfifo_ovf_l3", &self.outfifo_ovf_l3())
+            .field("outfifo_udf_l3", &self.outfifo_udf_l3())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0."]
+    #[inline(always)]
+    pub fn out_done(&mut self) -> OUT_DONE_W<RAW_SPEC> {
+        OUT_DONE_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0."]
+    #[inline(always)]
+    pub fn out_eof(&mut self) -> OUT_EOF_W<RAW_SPEC> {
+        OUT_EOF_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0."]
+    #[inline(always)]
+    pub fn out_dscr_err(&mut self) -> OUT_DSCR_ERR_W<RAW_SPEC> {
+        OUT_DSCR_ERR_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0."]
+    #[inline(always)]
+    pub fn out_total_eof(&mut self) -> OUT_TOTAL_EOF_W<RAW_SPEC> {
+        OUT_TOTAL_EOF_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow."]
+    #[inline(always)]
+    pub fn outfifo_ovf_l1(&mut self) -> OUTFIFO_OVF_L1_W<RAW_SPEC> {
+        OUTFIFO_OVF_L1_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow."]
+    #[inline(always)]
+    pub fn outfifo_udf_l1(&mut self) -> OUTFIFO_UDF_L1_W<RAW_SPEC> {
+        OUTFIFO_UDF_L1_W::new(self, 5)
+    }
+    #[doc = "Bit 6 - This raw interrupt bit turns to high level when level 3 fifo of Tx channel 0 is overflow."]
+    #[inline(always)]
+    pub fn outfifo_ovf_l3(&mut self) -> OUTFIFO_OVF_L3_W<RAW_SPEC> {
+        OUTFIFO_OVF_L3_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - This raw interrupt bit turns to high level when level 3 fifo of Tx channel 0 is underflow."]
+    #[inline(always)]
+    pub fn outfifo_udf_l3(&mut self) -> OUTFIFO_UDF_L3_W<RAW_SPEC> {
+        OUTFIFO_UDF_L3_W::new(self, 7)
+    }
+}
+#[doc = "Raw status interrupt of Tx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`raw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`raw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct RAW_SPEC;
+impl crate::RegisterSpec for RAW_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`raw::R`](R) reader structure"]
+impl crate::Readable for RAW_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`raw::W`](W) writer structure"]
+impl crate::Writable for RAW_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets RAW to value 0"]
+impl crate::Resettable for RAW_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/dma/ch/out_int/st.rs

@@ -0,0 +1,86 @@
+#[doc = "Register `ST` reader"]
+pub type R = crate::R<ST_SPEC>;
+#[doc = "Field `OUT_DONE` reader - The raw interrupt status bit for the OUT_DONE_CH_INT interrupt."]
+pub type OUT_DONE_R = crate::BitReader;
+#[doc = "Field `OUT_EOF` reader - The raw interrupt status bit for the OUT_EOF_CH_INT interrupt."]
+pub type OUT_EOF_R = crate::BitReader;
+#[doc = "Field `OUT_DSCR_ERR` reader - The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt."]
+pub type OUT_DSCR_ERR_R = crate::BitReader;
+#[doc = "Field `OUT_TOTAL_EOF` reader - The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt."]
+pub type OUT_TOTAL_EOF_R = crate::BitReader;
+#[doc = "Field `OUTFIFO_OVF_L1` reader - The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt."]
+pub type OUTFIFO_OVF_L1_R = crate::BitReader;
+#[doc = "Field `OUTFIFO_UDF_L1` reader - The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt."]
+pub type OUTFIFO_UDF_L1_R = crate::BitReader;
+#[doc = "Field `OUTFIFO_OVF_L3` reader - The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt."]
+pub type OUTFIFO_OVF_L3_R = crate::BitReader;
+#[doc = "Field `OUTFIFO_UDF_L3` reader - The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt."]
+pub type OUTFIFO_UDF_L3_R = crate::BitReader;
+impl R {
+    #[doc = "Bit 0 - The raw interrupt status bit for the OUT_DONE_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn out_done(&self) -> OUT_DONE_R {
+        OUT_DONE_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - The raw interrupt status bit for the OUT_EOF_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn out_eof(&self) -> OUT_EOF_R {
+        OUT_EOF_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn out_dscr_err(&self) -> OUT_DSCR_ERR_R {
+        OUT_DSCR_ERR_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn out_total_eof(&self) -> OUT_TOTAL_EOF_R {
+        OUT_TOTAL_EOF_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn outfifo_ovf_l1(&self) -> OUTFIFO_OVF_L1_R {
+        OUTFIFO_OVF_L1_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn outfifo_udf_l1(&self) -> OUTFIFO_UDF_L1_R {
+        OUTFIFO_UDF_L1_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn outfifo_ovf_l3(&self) -> OUTFIFO_OVF_L3_R {
+        OUTFIFO_OVF_L3_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt."]
+    #[inline(always)]
+    pub fn outfifo_udf_l3(&self) -> OUTFIFO_UDF_L3_R {
+        OUTFIFO_UDF_L3_R::new(((self.bits >> 7) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("ST")
+            .field("out_done", &self.out_done())
+            .field("out_eof", &self.out_eof())
+            .field("out_dscr_err", &self.out_dscr_err())
+            .field("out_total_eof", &self.out_total_eof())
+            .field("outfifo_ovf_l1", &self.outfifo_ovf_l1())
+            .field("outfifo_udf_l1", &self.outfifo_udf_l1())
+            .field("outfifo_ovf_l3", &self.outfifo_ovf_l3())
+            .field("outfifo_udf_l3", &self.outfifo_udf_l3())
+            .finish()
+    }
+}
+#[doc = "Masked interrupt of Tx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ST_SPEC;
+impl crate::RegisterSpec for ST_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`st::R`](R) reader structure"]
+impl crate::Readable for ST_SPEC {}
+#[doc = "`reset()` method sets ST to value 0"]
+impl crate::Resettable for ST_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/dma/ch/out_link.rs

@@ -0,0 +1,100 @@
+#[doc = "Register `OUT_LINK` reader"]
+pub type R = crate::R<OUT_LINK_SPEC>;
+#[doc = "Register `OUT_LINK` writer"]
+pub type W = crate::W<OUT_LINK_SPEC>;
+#[doc = "Field `OUTLINK_ADDR` reader - This register stores the 20 least significant bits of the first outlink descriptor's address."]
+pub type OUTLINK_ADDR_R = crate::FieldReader<u32>;
+#[doc = "Field `OUTLINK_ADDR` writer - This register stores the 20 least significant bits of the first outlink descriptor's address."]
+pub type OUTLINK_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>;
+#[doc = "Field `OUTLINK_STOP` reader - Set this bit to stop dealing with the outlink descriptors."]
+pub type OUTLINK_STOP_R = crate::BitReader;
+#[doc = "Field `OUTLINK_STOP` writer - Set this bit to stop dealing with the outlink descriptors."]
+pub type OUTLINK_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `OUTLINK_START` reader - Set this bit to start dealing with the outlink descriptors."]
+pub type OUTLINK_START_R = crate::BitReader;
+#[doc = "Field `OUTLINK_START` writer - Set this bit to start dealing with the outlink descriptors."]
+pub type OUTLINK_START_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `OUTLINK_RESTART` reader - Set this bit to restart a new outlink from the last address."]
+pub type OUTLINK_RESTART_R = crate::BitReader;
+#[doc = "Field `OUTLINK_RESTART` writer - Set this bit to restart a new outlink from the last address."]
+pub type OUTLINK_RESTART_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `OUTLINK_PARK` reader - 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working."]
+pub type OUTLINK_PARK_R = crate::BitReader;
+impl R {
+    #[doc = "Bits 0:19 - This register stores the 20 least significant bits of the first outlink descriptor's address."]
+    #[inline(always)]
+    pub fn outlink_addr(&self) -> OUTLINK_ADDR_R {
+        OUTLINK_ADDR_R::new(self.bits & 0x000f_ffff)
+    }
+    #[doc = "Bit 20 - Set this bit to stop dealing with the outlink descriptors."]
+    #[inline(always)]
+    pub fn outlink_stop(&self) -> OUTLINK_STOP_R {
+        OUTLINK_STOP_R::new(((self.bits >> 20) & 1) != 0)
+    }
+    #[doc = "Bit 21 - Set this bit to start dealing with the outlink descriptors."]
+    #[inline(always)]
+    pub fn outlink_start(&self) -> OUTLINK_START_R {
+        OUTLINK_START_R::new(((self.bits >> 21) & 1) != 0)
+    }
+    #[doc = "Bit 22 - Set this bit to restart a new outlink from the last address."]
+    #[inline(always)]
+    pub fn outlink_restart(&self) -> OUTLINK_RESTART_R {
+        OUTLINK_RESTART_R::new(((self.bits >> 22) & 1) != 0)
+    }
+    #[doc = "Bit 23 - 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working."]
+    #[inline(always)]
+    pub fn outlink_park(&self) -> OUTLINK_PARK_R {
+        OUTLINK_PARK_R::new(((self.bits >> 23) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("OUT_LINK")
+            .field("outlink_addr", &self.outlink_addr())
+            .field("outlink_stop", &self.outlink_stop())
+            .field("outlink_start", &self.outlink_start())
+            .field("outlink_restart", &self.outlink_restart())
+            .field("outlink_park", &self.outlink_park())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:19 - This register stores the 20 least significant bits of the first outlink descriptor's address."]
+    #[inline(always)]
+    pub fn outlink_addr(&mut self) -> OUTLINK_ADDR_W<OUT_LINK_SPEC> {
+        OUTLINK_ADDR_W::new(self, 0)
+    }
+    #[doc = "Bit 20 - Set this bit to stop dealing with the outlink descriptors."]
+    #[inline(always)]
+    pub fn outlink_stop(&mut self) -> OUTLINK_STOP_W<OUT_LINK_SPEC> {
+        OUTLINK_STOP_W::new(self, 20)
+    }
+    #[doc = "Bit 21 - Set this bit to start dealing with the outlink descriptors."]
+    #[inline(always)]
+    pub fn outlink_start(&mut self) -> OUTLINK_START_W<OUT_LINK_SPEC> {
+        OUTLINK_START_W::new(self, 21)
+    }
+    #[doc = "Bit 22 - Set this bit to restart a new outlink from the last address."]
+    #[inline(always)]
+    pub fn outlink_restart(&mut self) -> OUTLINK_RESTART_W<OUT_LINK_SPEC> {
+        OUTLINK_RESTART_W::new(self, 22)
+    }
+}
+#[doc = "Link descriptor configure and control register of Tx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`out_link::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`out_link::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct OUT_LINK_SPEC;
+impl crate::RegisterSpec for OUT_LINK_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`out_link::R`](R) reader structure"]
+impl crate::Readable for OUT_LINK_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`out_link::W`](W) writer structure"]
+impl crate::Writable for OUT_LINK_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets OUT_LINK to value 0x0080_0000"]
+impl crate::Resettable for OUT_LINK_SPEC {
+    const RESET_VALUE: u32 = 0x0080_0000;
+}

vendor/esp32s3/src/dma/ch/out_peri_sel.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `OUT_PERI_SEL` reader"]
+pub type R = crate::R<OUT_PERI_SEL_SPEC>;
+#[doc = "Register `OUT_PERI_SEL` writer"]
+pub type W = crate::W<OUT_PERI_SEL_SPEC>;
+#[doc = "Field `PERI_OUT_SEL` reader - This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: SPI3. 2: UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT."]
+pub type PERI_OUT_SEL_R = crate::FieldReader;
+#[doc = "Field `PERI_OUT_SEL` writer - This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: SPI3. 2: UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT."]
+pub type PERI_OUT_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
+impl R {
+    #[doc = "Bits 0:5 - This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: SPI3. 2: UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT."]
+    #[inline(always)]
+    pub fn peri_out_sel(&self) -> PERI_OUT_SEL_R {
+        PERI_OUT_SEL_R::new((self.bits & 0x3f) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("OUT_PERI_SEL")
+            .field("peri_out_sel", &self.peri_out_sel())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:5 - This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: SPI3. 2: UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT."]
+    #[inline(always)]
+    pub fn peri_out_sel(&mut self) -> PERI_OUT_SEL_W<OUT_PERI_SEL_SPEC> {
+        PERI_OUT_SEL_W::new(self, 0)
+    }
+}
+#[doc = "Peripheral selection of Tx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`out_peri_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`out_peri_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct OUT_PERI_SEL_SPEC;
+impl crate::RegisterSpec for OUT_PERI_SEL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`out_peri_sel::R`](R) reader structure"]
+impl crate::Readable for OUT_PERI_SEL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`out_peri_sel::W`](W) writer structure"]
+impl crate::Writable for OUT_PERI_SEL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets OUT_PERI_SEL to value 0x3f"]
+impl crate::Resettable for OUT_PERI_SEL_SPEC {
+    const RESET_VALUE: u32 = 0x3f;
+}

vendor/esp32s3/src/dma/ch/out_pri.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `OUT_PRI` reader"]
+pub type R = crate::R<OUT_PRI_SPEC>;
+#[doc = "Register `OUT_PRI` writer"]
+pub type W = crate::W<OUT_PRI_SPEC>;
+#[doc = "Field `TX_PRI` reader - The priority of Tx channel 0. The larger of the value, the higher of the priority."]
+pub type TX_PRI_R = crate::FieldReader;
+#[doc = "Field `TX_PRI` writer - The priority of Tx channel 0. The larger of the value, the higher of the priority."]
+pub type TX_PRI_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+impl R {
+    #[doc = "Bits 0:3 - The priority of Tx channel 0. The larger of the value, the higher of the priority."]
+    #[inline(always)]
+    pub fn tx_pri(&self) -> TX_PRI_R {
+        TX_PRI_R::new((self.bits & 0x0f) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("OUT_PRI")
+            .field("tx_pri", &self.tx_pri())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:3 - The priority of Tx channel 0. The larger of the value, the higher of the priority."]
+    #[inline(always)]
+    pub fn tx_pri(&mut self) -> TX_PRI_W<OUT_PRI_SPEC> {
+        TX_PRI_W::new(self, 0)
+    }
+}
+#[doc = "Priority register of Tx channel 0.\n\nYou can [`read`](crate::Reg::read) this register and get [`out_pri::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`out_pri::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct OUT_PRI_SPEC;
+impl crate::RegisterSpec for OUT_PRI_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`out_pri::R`](R) reader structure"]
+impl crate::Readable for OUT_PRI_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`out_pri::W`](W) writer structure"]
+impl crate::Writable for OUT_PRI_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets OUT_PRI to value 0"]
+impl crate::Resettable for OUT_PRI_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/dma/ch/out_push.rs

@@ -0,0 +1,62 @@
+#[doc = "Register `OUT_PUSH` reader"]
+pub type R = crate::R<OUT_PUSH_SPEC>;
+#[doc = "Register `OUT_PUSH` writer"]
+pub type W = crate::W<OUT_PUSH_SPEC>;
+#[doc = "Field `OUTFIFO_WDATA` reader - This register stores the data that need to be pushed into DMA FIFO."]
+pub type OUTFIFO_WDATA_R = crate::FieldReader<u16>;
+#[doc = "Field `OUTFIFO_WDATA` writer - This register stores the data that need to be pushed into DMA FIFO."]
+pub type OUTFIFO_WDATA_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
+#[doc = "Field `OUTFIFO_PUSH` reader - Set this bit to push data into DMA FIFO."]
+pub type OUTFIFO_PUSH_R = crate::BitReader;
+#[doc = "Field `OUTFIFO_PUSH` writer - Set this bit to push data into DMA FIFO."]
+pub type OUTFIFO_PUSH_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 0:8 - This register stores the data that need to be pushed into DMA FIFO."]
+    #[inline(always)]
+    pub fn outfifo_wdata(&self) -> OUTFIFO_WDATA_R {
+        OUTFIFO_WDATA_R::new((self.bits & 0x01ff) as u16)
+    }
+    #[doc = "Bit 9 - Set this bit to push data into DMA FIFO."]
+    #[inline(always)]
+    pub fn outfifo_push(&self) -> OUTFIFO_PUSH_R {
+        OUTFIFO_PUSH_R::new(((self.bits >> 9) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("OUT_PUSH")
+            .field("outfifo_wdata", &self.outfifo_wdata())
+            .field("outfifo_push", &self.outfifo_push())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:8 - This register stores the data that need to be pushed into DMA FIFO."]
+    #[inline(always)]
+    pub fn outfifo_wdata(&mut self) -> OUTFIFO_WDATA_W<OUT_PUSH_SPEC> {
+        OUTFIFO_WDATA_W::new(self, 0)
+    }
+    #[doc = "Bit 9 - Set this bit to push data into DMA FIFO."]
+    #[inline(always)]
+    pub fn outfifo_push(&mut self) -> OUTFIFO_PUSH_W<OUT_PUSH_SPEC> {
+        OUTFIFO_PUSH_W::new(self, 9)
+    }
+}
+#[doc = "Push control register of Rx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`out_push::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`out_push::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct OUT_PUSH_SPEC;
+impl crate::RegisterSpec for OUT_PUSH_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`out_push::R`](R) reader structure"]
+impl crate::Readable for OUT_PUSH_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`out_push::W`](W) writer structure"]
+impl crate::Writable for OUT_PUSH_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets OUT_PUSH to value 0"]
+impl crate::Resettable for OUT_PUSH_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/dma/ch/out_state.rs

@@ -0,0 +1,46 @@
+#[doc = "Register `OUT_STATE` reader"]
+pub type R = crate::R<OUT_STATE_SPEC>;
+#[doc = "Field `OUTLINK_DSCR_ADDR` reader - This register stores the current outlink descriptor's address."]
+pub type OUTLINK_DSCR_ADDR_R = crate::FieldReader<u32>;
+#[doc = "Field `OUT_DSCR_STATE` reader - reserved"]
+pub type OUT_DSCR_STATE_R = crate::FieldReader;
+#[doc = "Field `OUT_STATE` reader - reserved"]
+pub type OUT_STATE_R = crate::FieldReader;
+impl R {
+    #[doc = "Bits 0:17 - This register stores the current outlink descriptor's address."]
+    #[inline(always)]
+    pub fn outlink_dscr_addr(&self) -> OUTLINK_DSCR_ADDR_R {
+        OUTLINK_DSCR_ADDR_R::new(self.bits & 0x0003_ffff)
+    }
+    #[doc = "Bits 18:19 - reserved"]
+    #[inline(always)]
+    pub fn out_dscr_state(&self) -> OUT_DSCR_STATE_R {
+        OUT_DSCR_STATE_R::new(((self.bits >> 18) & 3) as u8)
+    }
+    #[doc = "Bits 20:22 - reserved"]
+    #[inline(always)]
+    pub fn out_state(&self) -> OUT_STATE_R {
+        OUT_STATE_R::new(((self.bits >> 20) & 7) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("OUT_STATE")
+            .field("outlink_dscr_addr", &self.outlink_dscr_addr())
+            .field("out_dscr_state", &self.out_dscr_state())
+            .field("out_state", &self.out_state())
+            .finish()
+    }
+}
+#[doc = "Transmit status of Tx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`out_state::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct OUT_STATE_SPEC;
+impl crate::RegisterSpec for OUT_STATE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`out_state::R`](R) reader structure"]
+impl crate::Readable for OUT_STATE_SPEC {}
+#[doc = "`reset()` method sets OUT_STATE to value 0"]
+impl crate::Resettable for OUT_STATE_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/dma/ch/out_wight.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `OUT_WIGHT` reader"]
+pub type R = crate::R<OUT_WIGHT_SPEC>;
+#[doc = "Register `OUT_WIGHT` writer"]
+pub type W = crate::W<OUT_WIGHT_SPEC>;
+#[doc = "Field `TX_WEIGHT` reader - The weight of Tx channel 0."]
+pub type TX_WEIGHT_R = crate::FieldReader;
+#[doc = "Field `TX_WEIGHT` writer - The weight of Tx channel 0."]
+pub type TX_WEIGHT_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+impl R {
+    #[doc = "Bits 8:11 - The weight of Tx channel 0."]
+    #[inline(always)]
+    pub fn tx_weight(&self) -> TX_WEIGHT_R {
+        TX_WEIGHT_R::new(((self.bits >> 8) & 0x0f) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("OUT_WIGHT")
+            .field("tx_weight", &self.tx_weight())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 8:11 - The weight of Tx channel 0."]
+    #[inline(always)]
+    pub fn tx_weight(&mut self) -> TX_WEIGHT_W<OUT_WIGHT_SPEC> {
+        TX_WEIGHT_W::new(self, 8)
+    }
+}
+#[doc = "Weight register of Rx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`out_wight::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`out_wight::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct OUT_WIGHT_SPEC;
+impl crate::RegisterSpec for OUT_WIGHT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`out_wight::R`](R) reader structure"]
+impl crate::Readable for OUT_WIGHT_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`out_wight::W`](W) writer structure"]
+impl crate::Writable for OUT_WIGHT_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets OUT_WIGHT to value 0x0f00"]
+impl crate::Resettable for OUT_WIGHT_SPEC {
+    const RESET_VALUE: u32 = 0x0f00;
+}

vendor/esp32s3/src/dma/ch/outfifo_status.rs

@@ -0,0 +1,126 @@
+#[doc = "Register `OUTFIFO_STATUS` reader"]
+pub type R = crate::R<OUTFIFO_STATUS_SPEC>;
+#[doc = "Field `OUTFIFO_FULL_L1` reader - L1 Tx FIFO full signal for Tx channel 0."]
+pub type OUTFIFO_FULL_L1_R = crate::BitReader;
+#[doc = "Field `OUTFIFO_EMPTY_L1` reader - L1 Tx FIFO empty signal for Tx channel 0."]
+pub type OUTFIFO_EMPTY_L1_R = crate::BitReader;
+#[doc = "Field `OUTFIFO_FULL_L2` reader - L2 Tx FIFO full signal for Tx channel 0."]
+pub type OUTFIFO_FULL_L2_R = crate::BitReader;
+#[doc = "Field `OUTFIFO_EMPTY_L2` reader - L2 Tx FIFO empty signal for Tx channel 0."]
+pub type OUTFIFO_EMPTY_L2_R = crate::BitReader;
+#[doc = "Field `OUTFIFO_FULL_L3` reader - L3 Tx FIFO full signal for Tx channel 0."]
+pub type OUTFIFO_FULL_L3_R = crate::BitReader;
+#[doc = "Field `OUTFIFO_EMPTY_L3` reader - L3 Tx FIFO empty signal for Tx channel 0."]
+pub type OUTFIFO_EMPTY_L3_R = crate::BitReader;
+#[doc = "Field `OUTFIFO_CNT_L1` reader - The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0."]
+pub type OUTFIFO_CNT_L1_R = crate::FieldReader;
+#[doc = "Field `OUTFIFO_CNT_L2` reader - The register stores the byte number of the data in L2 Tx FIFO for Tx channel 0."]
+pub type OUTFIFO_CNT_L2_R = crate::FieldReader;
+#[doc = "Field `OUTFIFO_CNT_L3` reader - The register stores the byte number of the data in L3 Tx FIFO for Tx channel 0."]
+pub type OUTFIFO_CNT_L3_R = crate::FieldReader;
+#[doc = "Field `OUT_REMAIN_UNDER_1B_L3` reader - reserved"]
+pub type OUT_REMAIN_UNDER_1B_L3_R = crate::BitReader;
+#[doc = "Field `OUT_REMAIN_UNDER_2B_L3` reader - reserved"]
+pub type OUT_REMAIN_UNDER_2B_L3_R = crate::BitReader;
+#[doc = "Field `OUT_REMAIN_UNDER_3B_L3` reader - reserved"]
+pub type OUT_REMAIN_UNDER_3B_L3_R = crate::BitReader;
+#[doc = "Field `OUT_REMAIN_UNDER_4B_L3` reader - reserved"]
+pub type OUT_REMAIN_UNDER_4B_L3_R = crate::BitReader;
+impl R {
+    #[doc = "Bit 0 - L1 Tx FIFO full signal for Tx channel 0."]
+    #[inline(always)]
+    pub fn outfifo_full_l1(&self) -> OUTFIFO_FULL_L1_R {
+        OUTFIFO_FULL_L1_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - L1 Tx FIFO empty signal for Tx channel 0."]
+    #[inline(always)]
+    pub fn outfifo_empty_l1(&self) -> OUTFIFO_EMPTY_L1_R {
+        OUTFIFO_EMPTY_L1_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - L2 Tx FIFO full signal for Tx channel 0."]
+    #[inline(always)]
+    pub fn outfifo_full_l2(&self) -> OUTFIFO_FULL_L2_R {
+        OUTFIFO_FULL_L2_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - L2 Tx FIFO empty signal for Tx channel 0."]
+    #[inline(always)]
+    pub fn outfifo_empty_l2(&self) -> OUTFIFO_EMPTY_L2_R {
+        OUTFIFO_EMPTY_L2_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - L3 Tx FIFO full signal for Tx channel 0."]
+    #[inline(always)]
+    pub fn outfifo_full_l3(&self) -> OUTFIFO_FULL_L3_R {
+        OUTFIFO_FULL_L3_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - L3 Tx FIFO empty signal for Tx channel 0."]
+    #[inline(always)]
+    pub fn outfifo_empty_l3(&self) -> OUTFIFO_EMPTY_L3_R {
+        OUTFIFO_EMPTY_L3_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bits 6:10 - The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0."]
+    #[inline(always)]
+    pub fn outfifo_cnt_l1(&self) -> OUTFIFO_CNT_L1_R {
+        OUTFIFO_CNT_L1_R::new(((self.bits >> 6) & 0x1f) as u8)
+    }
+    #[doc = "Bits 11:17 - The register stores the byte number of the data in L2 Tx FIFO for Tx channel 0."]
+    #[inline(always)]
+    pub fn outfifo_cnt_l2(&self) -> OUTFIFO_CNT_L2_R {
+        OUTFIFO_CNT_L2_R::new(((self.bits >> 11) & 0x7f) as u8)
+    }
+    #[doc = "Bits 18:22 - The register stores the byte number of the data in L3 Tx FIFO for Tx channel 0."]
+    #[inline(always)]
+    pub fn outfifo_cnt_l3(&self) -> OUTFIFO_CNT_L3_R {
+        OUTFIFO_CNT_L3_R::new(((self.bits >> 18) & 0x1f) as u8)
+    }
+    #[doc = "Bit 23 - reserved"]
+    #[inline(always)]
+    pub fn out_remain_under_1b_l3(&self) -> OUT_REMAIN_UNDER_1B_L3_R {
+        OUT_REMAIN_UNDER_1B_L3_R::new(((self.bits >> 23) & 1) != 0)
+    }
+    #[doc = "Bit 24 - reserved"]
+    #[inline(always)]
+    pub fn out_remain_under_2b_l3(&self) -> OUT_REMAIN_UNDER_2B_L3_R {
+        OUT_REMAIN_UNDER_2B_L3_R::new(((self.bits >> 24) & 1) != 0)
+    }
+    #[doc = "Bit 25 - reserved"]
+    #[inline(always)]
+    pub fn out_remain_under_3b_l3(&self) -> OUT_REMAIN_UNDER_3B_L3_R {
+        OUT_REMAIN_UNDER_3B_L3_R::new(((self.bits >> 25) & 1) != 0)
+    }
+    #[doc = "Bit 26 - reserved"]
+    #[inline(always)]
+    pub fn out_remain_under_4b_l3(&self) -> OUT_REMAIN_UNDER_4B_L3_R {
+        OUT_REMAIN_UNDER_4B_L3_R::new(((self.bits >> 26) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("OUTFIFO_STATUS")
+            .field("outfifo_full_l1", &self.outfifo_full_l1())
+            .field("outfifo_empty_l1", &self.outfifo_empty_l1())
+            .field("outfifo_full_l2", &self.outfifo_full_l2())
+            .field("outfifo_empty_l2", &self.outfifo_empty_l2())
+            .field("outfifo_full_l3", &self.outfifo_full_l3())
+            .field("outfifo_empty_l3", &self.outfifo_empty_l3())
+            .field("outfifo_cnt_l1", &self.outfifo_cnt_l1())
+            .field("outfifo_cnt_l2", &self.outfifo_cnt_l2())
+            .field("outfifo_cnt_l3", &self.outfifo_cnt_l3())
+            .field("out_remain_under_1b_l3", &self.out_remain_under_1b_l3())
+            .field("out_remain_under_2b_l3", &self.out_remain_under_2b_l3())
+            .field("out_remain_under_3b_l3", &self.out_remain_under_3b_l3())
+            .field("out_remain_under_4b_l3", &self.out_remain_under_4b_l3())
+            .finish()
+    }
+}
+#[doc = "Transmit FIFO status of Tx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`outfifo_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct OUTFIFO_STATUS_SPEC;
+impl crate::RegisterSpec for OUTFIFO_STATUS_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`outfifo_status::R`](R) reader structure"]
+impl crate::Readable for OUTFIFO_STATUS_SPEC {}
+#[doc = "`reset()` method sets OUTFIFO_STATUS to value 0x0780_002a"]
+impl crate::Resettable for OUTFIFO_STATUS_SPEC {
+    const RESET_VALUE: u32 = 0x0780_002a;
+}

vendor/esp32s3/src/dma/date.rs

@@ -0,0 +1,45 @@
+#[doc = "Register `DATE` reader"]
+pub type R = crate::R<DATE_SPEC>;
+#[doc = "Register `DATE` writer"]
+pub type W = crate::W<DATE_SPEC>;
+#[doc = "Field `DATE` reader - register version."]
+pub type DATE_R = crate::FieldReader<u32>;
+#[doc = "Field `DATE` writer - register version."]
+pub type DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - register version."]
+    #[inline(always)]
+    pub fn date(&self) -> DATE_R {
+        DATE_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DATE").field("date", &self.date()).finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - register version."]
+    #[inline(always)]
+    pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
+        DATE_W::new(self, 0)
+    }
+}
+#[doc = "Version control register\n\nYou can [`read`](crate::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DATE_SPEC;
+impl crate::RegisterSpec for DATE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`date::R`](R) reader structure"]
+impl crate::Readable for DATE_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"]
+impl crate::Writable for DATE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DATE to value 0x0210_1180"]
+impl crate::Resettable for DATE_SPEC {
+    const RESET_VALUE: u32 = 0x0210_1180;
+}

vendor/esp32s3/src/dma/extmem_reject_addr.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `EXTMEM_REJECT_ADDR` reader"]
+pub type R = crate::R<EXTMEM_REJECT_ADDR_SPEC>;
+#[doc = "Field `EXTMEM_REJECT_ADDR` reader - This register store the first address rejected by permission control when accessing external RAM."]
+pub type EXTMEM_REJECT_ADDR_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - This register store the first address rejected by permission control when accessing external RAM."]
+    #[inline(always)]
+    pub fn extmem_reject_addr(&self) -> EXTMEM_REJECT_ADDR_R {
+        EXTMEM_REJECT_ADDR_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("EXTMEM_REJECT_ADDR")
+            .field("extmem_reject_addr", &self.extmem_reject_addr())
+            .finish()
+    }
+}
+#[doc = "Reject address accessing external RAM\n\nYou can [`read`](crate::Reg::read) this register and get [`extmem_reject_addr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct EXTMEM_REJECT_ADDR_SPEC;
+impl crate::RegisterSpec for EXTMEM_REJECT_ADDR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`extmem_reject_addr::R`](R) reader structure"]
+impl crate::Readable for EXTMEM_REJECT_ADDR_SPEC {}
+#[doc = "`reset()` method sets EXTMEM_REJECT_ADDR to value 0"]
+impl crate::Resettable for EXTMEM_REJECT_ADDR_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/dma/extmem_reject_int_clr.rs

@@ -0,0 +1,32 @@
+#[doc = "Register `EXTMEM_REJECT_INT_CLR` writer"]
+pub type W = crate::W<EXTMEM_REJECT_INT_CLR_SPEC>;
+#[doc = "Field `EXTMEM_REJECT_INT_CLR` writer - Set this bit to clear the EXTMEM_REJECT_INT interrupt."]
+pub type EXTMEM_REJECT_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for crate::generic::Reg<EXTMEM_REJECT_INT_CLR_SPEC> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "(not readable)")
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Set this bit to clear the EXTMEM_REJECT_INT interrupt."]
+    #[inline(always)]
+    pub fn extmem_reject_int_clr(&mut self) -> EXTMEM_REJECT_INT_CLR_W<EXTMEM_REJECT_INT_CLR_SPEC> {
+        EXTMEM_REJECT_INT_CLR_W::new(self, 0)
+    }
+}
+#[doc = "Interrupt clear bits of external RAM permission\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`extmem_reject_int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct EXTMEM_REJECT_INT_CLR_SPEC;
+impl crate::RegisterSpec for EXTMEM_REJECT_INT_CLR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [`extmem_reject_int_clr::W`](W) writer structure"]
+impl crate::Writable for EXTMEM_REJECT_INT_CLR_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets EXTMEM_REJECT_INT_CLR to value 0"]
+impl crate::Resettable for EXTMEM_REJECT_INT_CLR_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/dma/extmem_reject_int_ena.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `EXTMEM_REJECT_INT_ENA` reader"]
+pub type R = crate::R<EXTMEM_REJECT_INT_ENA_SPEC>;
+#[doc = "Register `EXTMEM_REJECT_INT_ENA` writer"]
+pub type W = crate::W<EXTMEM_REJECT_INT_ENA_SPEC>;
+#[doc = "Field `EXTMEM_REJECT_INT_ENA` reader - The interrupt enable bit for the EXTMEM_REJECT_INT interrupt."]
+pub type EXTMEM_REJECT_INT_ENA_R = crate::BitReader;
+#[doc = "Field `EXTMEM_REJECT_INT_ENA` writer - The interrupt enable bit for the EXTMEM_REJECT_INT interrupt."]
+pub type EXTMEM_REJECT_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - The interrupt enable bit for the EXTMEM_REJECT_INT interrupt."]
+    #[inline(always)]
+    pub fn extmem_reject_int_ena(&self) -> EXTMEM_REJECT_INT_ENA_R {
+        EXTMEM_REJECT_INT_ENA_R::new((self.bits & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("EXTMEM_REJECT_INT_ENA")
+            .field("extmem_reject_int_ena", &self.extmem_reject_int_ena())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - The interrupt enable bit for the EXTMEM_REJECT_INT interrupt."]
+    #[inline(always)]
+    pub fn extmem_reject_int_ena(&mut self) -> EXTMEM_REJECT_INT_ENA_W<EXTMEM_REJECT_INT_ENA_SPEC> {
+        EXTMEM_REJECT_INT_ENA_W::new(self, 0)
+    }
+}
+#[doc = "Interrupt enable bits of external RAM permission\n\nYou can [`read`](crate::Reg::read) this register and get [`extmem_reject_int_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`extmem_reject_int_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct EXTMEM_REJECT_INT_ENA_SPEC;
+impl crate::RegisterSpec for EXTMEM_REJECT_INT_ENA_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`extmem_reject_int_ena::R`](R) reader structure"]
+impl crate::Readable for EXTMEM_REJECT_INT_ENA_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`extmem_reject_int_ena::W`](W) writer structure"]
+impl crate::Writable for EXTMEM_REJECT_INT_ENA_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets EXTMEM_REJECT_INT_ENA to value 0"]
+impl crate::Resettable for EXTMEM_REJECT_INT_ENA_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/dma/extmem_reject_int_raw.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `EXTMEM_REJECT_INT_RAW` reader"]
+pub type R = crate::R<EXTMEM_REJECT_INT_RAW_SPEC>;
+#[doc = "Register `EXTMEM_REJECT_INT_RAW` writer"]
+pub type W = crate::W<EXTMEM_REJECT_INT_RAW_SPEC>;
+#[doc = "Field `EXTMEM_REJECT_INT_RAW` reader - The raw interrupt bit turns to high level when accessing external RAM is rejected by permission control."]
+pub type EXTMEM_REJECT_INT_RAW_R = crate::BitReader;
+#[doc = "Field `EXTMEM_REJECT_INT_RAW` writer - The raw interrupt bit turns to high level when accessing external RAM is rejected by permission control."]
+pub type EXTMEM_REJECT_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - The raw interrupt bit turns to high level when accessing external RAM is rejected by permission control."]
+    #[inline(always)]
+    pub fn extmem_reject_int_raw(&self) -> EXTMEM_REJECT_INT_RAW_R {
+        EXTMEM_REJECT_INT_RAW_R::new((self.bits & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("EXTMEM_REJECT_INT_RAW")
+            .field("extmem_reject_int_raw", &self.extmem_reject_int_raw())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - The raw interrupt bit turns to high level when accessing external RAM is rejected by permission control."]
+    #[inline(always)]
+    pub fn extmem_reject_int_raw(&mut self) -> EXTMEM_REJECT_INT_RAW_W<EXTMEM_REJECT_INT_RAW_SPEC> {
+        EXTMEM_REJECT_INT_RAW_W::new(self, 0)
+    }
+}
+#[doc = "Raw interrupt status of external RAM permission\n\nYou can [`read`](crate::Reg::read) this register and get [`extmem_reject_int_raw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`extmem_reject_int_raw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct EXTMEM_REJECT_INT_RAW_SPEC;
+impl crate::RegisterSpec for EXTMEM_REJECT_INT_RAW_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`extmem_reject_int_raw::R`](R) reader structure"]
+impl crate::Readable for EXTMEM_REJECT_INT_RAW_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`extmem_reject_int_raw::W`](W) writer structure"]
+impl crate::Writable for EXTMEM_REJECT_INT_RAW_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets EXTMEM_REJECT_INT_RAW to value 0"]
+impl crate::Resettable for EXTMEM_REJECT_INT_RAW_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/dma/extmem_reject_int_st.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `EXTMEM_REJECT_INT_ST` reader"]
+pub type R = crate::R<EXTMEM_REJECT_INT_ST_SPEC>;
+#[doc = "Field `EXTMEM_REJECT_INT_ST` reader - The raw interrupt status bit for the EXTMEM_REJECT_INT interrupt."]
+pub type EXTMEM_REJECT_INT_ST_R = crate::BitReader;
+impl R {
+    #[doc = "Bit 0 - The raw interrupt status bit for the EXTMEM_REJECT_INT interrupt."]
+    #[inline(always)]
+    pub fn extmem_reject_int_st(&self) -> EXTMEM_REJECT_INT_ST_R {
+        EXTMEM_REJECT_INT_ST_R::new((self.bits & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("EXTMEM_REJECT_INT_ST")
+            .field("extmem_reject_int_st", &self.extmem_reject_int_st())
+            .finish()
+    }
+}
+#[doc = "Masked interrupt status of external RAM permission\n\nYou can [`read`](crate::Reg::read) this register and get [`extmem_reject_int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct EXTMEM_REJECT_INT_ST_SPEC;
+impl crate::RegisterSpec for EXTMEM_REJECT_INT_ST_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`extmem_reject_int_st::R`](R) reader structure"]
+impl crate::Readable for EXTMEM_REJECT_INT_ST_SPEC {}
+#[doc = "`reset()` method sets EXTMEM_REJECT_INT_ST to value 0"]
+impl crate::Resettable for EXTMEM_REJECT_INT_ST_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/dma/extmem_reject_st.rs

@@ -0,0 +1,49 @@
+#[doc = "Register `EXTMEM_REJECT_ST` reader"]
+pub type R = crate::R<EXTMEM_REJECT_ST_SPEC>;
+#[doc = "Field `EXTMEM_REJECT_ATRR` reader - The reject accessing. Bit 0: if this bit is 1, the rejected accessing is READ. Bit 1: if this bit is 1, the rejected accessing is WRITE."]
+pub type EXTMEM_REJECT_ATRR_R = crate::FieldReader;
+#[doc = "Field `EXTMEM_REJECT_CHANNEL_NUM` reader - The register indicate the reject accessing from which channel."]
+pub type EXTMEM_REJECT_CHANNEL_NUM_R = crate::FieldReader;
+#[doc = "Field `EXTMEM_REJECT_PERI_NUM` reader - This register indicate reject accessing from which peripheral."]
+pub type EXTMEM_REJECT_PERI_NUM_R = crate::FieldReader;
+impl R {
+    #[doc = "Bits 0:1 - The reject accessing. Bit 0: if this bit is 1, the rejected accessing is READ. Bit 1: if this bit is 1, the rejected accessing is WRITE."]
+    #[inline(always)]
+    pub fn extmem_reject_atrr(&self) -> EXTMEM_REJECT_ATRR_R {
+        EXTMEM_REJECT_ATRR_R::new((self.bits & 3) as u8)
+    }
+    #[doc = "Bits 2:5 - The register indicate the reject accessing from which channel."]
+    #[inline(always)]
+    pub fn extmem_reject_channel_num(&self) -> EXTMEM_REJECT_CHANNEL_NUM_R {
+        EXTMEM_REJECT_CHANNEL_NUM_R::new(((self.bits >> 2) & 0x0f) as u8)
+    }
+    #[doc = "Bits 6:11 - This register indicate reject accessing from which peripheral."]
+    #[inline(always)]
+    pub fn extmem_reject_peri_num(&self) -> EXTMEM_REJECT_PERI_NUM_R {
+        EXTMEM_REJECT_PERI_NUM_R::new(((self.bits >> 6) & 0x3f) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("EXTMEM_REJECT_ST")
+            .field("extmem_reject_atrr", &self.extmem_reject_atrr())
+            .field(
+                "extmem_reject_channel_num",
+                &self.extmem_reject_channel_num(),
+            )
+            .field("extmem_reject_peri_num", &self.extmem_reject_peri_num())
+            .finish()
+    }
+}
+#[doc = "Reject status accessing external RAM\n\nYou can [`read`](crate::Reg::read) this register and get [`extmem_reject_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct EXTMEM_REJECT_ST_SPEC;
+impl crate::RegisterSpec for EXTMEM_REJECT_ST_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`extmem_reject_st::R`](R) reader structure"]
+impl crate::Readable for EXTMEM_REJECT_ST_SPEC {}
+#[doc = "`reset()` method sets EXTMEM_REJECT_ST to value 0"]
+impl crate::Resettable for EXTMEM_REJECT_ST_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/dma/in_sram_size_ch.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `IN_SRAM_SIZE_CH%s` reader"]
+pub type R = crate::R<IN_SRAM_SIZE_CH_SPEC>;
+#[doc = "Register `IN_SRAM_SIZE_CH%s` writer"]
+pub type W = crate::W<IN_SRAM_SIZE_CH_SPEC>;
+#[doc = "Field `IN_SIZE` reader - This register is used to configure the size of L2 Tx FIFO for Rx channel 0. 0:16 bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 bytes. 7: 72 bytes. 8: 80 bytes."]
+pub type IN_SIZE_R = crate::FieldReader;
+#[doc = "Field `IN_SIZE` writer - This register is used to configure the size of L2 Tx FIFO for Rx channel 0. 0:16 bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 bytes. 7: 72 bytes. 8: 80 bytes."]
+pub type IN_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
+impl R {
+    #[doc = "Bits 0:6 - This register is used to configure the size of L2 Tx FIFO for Rx channel 0. 0:16 bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 bytes. 7: 72 bytes. 8: 80 bytes."]
+    #[inline(always)]
+    pub fn in_size(&self) -> IN_SIZE_R {
+        IN_SIZE_R::new((self.bits & 0x7f) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("IN_SRAM_SIZE_CH")
+            .field("in_size", &self.in_size())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:6 - This register is used to configure the size of L2 Tx FIFO for Rx channel 0. 0:16 bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 bytes. 7: 72 bytes. 8: 80 bytes."]
+    #[inline(always)]
+    pub fn in_size(&mut self) -> IN_SIZE_W<IN_SRAM_SIZE_CH_SPEC> {
+        IN_SIZE_W::new(self, 0)
+    }
+}
+#[doc = "Receive L2 FIFO depth of Rx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`in_sram_size_ch::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`in_sram_size_ch::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct IN_SRAM_SIZE_CH_SPEC;
+impl crate::RegisterSpec for IN_SRAM_SIZE_CH_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`in_sram_size_ch::R`](R) reader structure"]
+impl crate::Readable for IN_SRAM_SIZE_CH_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`in_sram_size_ch::W`](W) writer structure"]
+impl crate::Writable for IN_SRAM_SIZE_CH_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets IN_SRAM_SIZE_CH%s to value 0x0e"]
+impl crate::Resettable for IN_SRAM_SIZE_CH_SPEC {
+    const RESET_VALUE: u32 = 0x0e;
+}

vendor/esp32s3/src/dma/misc_conf.rs

@@ -0,0 +1,92 @@
+#[doc = "Register `MISC_CONF` reader"]
+pub type R = crate::R<MISC_CONF_SPEC>;
+#[doc = "Register `MISC_CONF` writer"]
+pub type W = crate::W<MISC_CONF_SPEC>;
+#[doc = "Field `AHBM_RST_INTER` reader - Set this bit, then clear this bit to reset the internal ahb FSM."]
+pub type AHBM_RST_INTER_R = crate::BitReader;
+#[doc = "Field `AHBM_RST_INTER` writer - Set this bit, then clear this bit to reset the internal ahb FSM."]
+pub type AHBM_RST_INTER_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `AHBM_RST_EXTER` reader - Set this bit, then clear this bit to reset the external ahb FSM."]
+pub type AHBM_RST_EXTER_R = crate::BitReader;
+#[doc = "Field `AHBM_RST_EXTER` writer - Set this bit, then clear this bit to reset the external ahb FSM."]
+pub type AHBM_RST_EXTER_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ARB_PRI_DIS` reader - Set this bit to disable priority arbitration function."]
+pub type ARB_PRI_DIS_R = crate::BitReader;
+#[doc = "Field `ARB_PRI_DIS` writer - Set this bit to disable priority arbitration function."]
+pub type ARB_PRI_DIS_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CLK_EN` reader - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers."]
+pub type CLK_EN_R = crate::BitReader;
+#[doc = "Field `CLK_EN` writer - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers."]
+pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Set this bit, then clear this bit to reset the internal ahb FSM."]
+    #[inline(always)]
+    pub fn ahbm_rst_inter(&self) -> AHBM_RST_INTER_R {
+        AHBM_RST_INTER_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Set this bit, then clear this bit to reset the external ahb FSM."]
+    #[inline(always)]
+    pub fn ahbm_rst_exter(&self) -> AHBM_RST_EXTER_R {
+        AHBM_RST_EXTER_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Set this bit to disable priority arbitration function."]
+    #[inline(always)]
+    pub fn arb_pri_dis(&self) -> ARB_PRI_DIS_R {
+        ARB_PRI_DIS_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 4 - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers."]
+    #[inline(always)]
+    pub fn clk_en(&self) -> CLK_EN_R {
+        CLK_EN_R::new(((self.bits >> 4) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("MISC_CONF")
+            .field("ahbm_rst_inter", &self.ahbm_rst_inter())
+            .field("ahbm_rst_exter", &self.ahbm_rst_exter())
+            .field("arb_pri_dis", &self.arb_pri_dis())
+            .field("clk_en", &self.clk_en())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Set this bit, then clear this bit to reset the internal ahb FSM."]
+    #[inline(always)]
+    pub fn ahbm_rst_inter(&mut self) -> AHBM_RST_INTER_W<MISC_CONF_SPEC> {
+        AHBM_RST_INTER_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - Set this bit, then clear this bit to reset the external ahb FSM."]
+    #[inline(always)]
+    pub fn ahbm_rst_exter(&mut self) -> AHBM_RST_EXTER_W<MISC_CONF_SPEC> {
+        AHBM_RST_EXTER_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - Set this bit to disable priority arbitration function."]
+    #[inline(always)]
+    pub fn arb_pri_dis(&mut self) -> ARB_PRI_DIS_W<MISC_CONF_SPEC> {
+        ARB_PRI_DIS_W::new(self, 2)
+    }
+    #[doc = "Bit 4 - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers."]
+    #[inline(always)]
+    pub fn clk_en(&mut self) -> CLK_EN_W<MISC_CONF_SPEC> {
+        CLK_EN_W::new(self, 4)
+    }
+}
+#[doc = "MISC register\n\nYou can [`read`](crate::Reg::read) this register and get [`misc_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`misc_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct MISC_CONF_SPEC;
+impl crate::RegisterSpec for MISC_CONF_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`misc_conf::R`](R) reader structure"]
+impl crate::Readable for MISC_CONF_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`misc_conf::W`](W) writer structure"]
+impl crate::Writable for MISC_CONF_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets MISC_CONF to value 0"]
+impl crate::Resettable for MISC_CONF_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/dma/out_sram_size_ch.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `OUT_SRAM_SIZE_CH%s` reader"]
+pub type R = crate::R<OUT_SRAM_SIZE_CH_SPEC>;
+#[doc = "Register `OUT_SRAM_SIZE_CH%s` writer"]
+pub type W = crate::W<OUT_SRAM_SIZE_CH_SPEC>;
+#[doc = "Field `OUT_SIZE` reader - This register is used to configure the size of L2 Tx FIFO for Tx channel 0. 0:16 bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 bytes. 7: 72 bytes. 8: 80 bytes."]
+pub type OUT_SIZE_R = crate::FieldReader;
+#[doc = "Field `OUT_SIZE` writer - This register is used to configure the size of L2 Tx FIFO for Tx channel 0. 0:16 bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 bytes. 7: 72 bytes. 8: 80 bytes."]
+pub type OUT_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
+impl R {
+    #[doc = "Bits 0:6 - This register is used to configure the size of L2 Tx FIFO for Tx channel 0. 0:16 bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 bytes. 7: 72 bytes. 8: 80 bytes."]
+    #[inline(always)]
+    pub fn out_size(&self) -> OUT_SIZE_R {
+        OUT_SIZE_R::new((self.bits & 0x7f) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("OUT_SRAM_SIZE_CH")
+            .field("out_size", &self.out_size())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:6 - This register is used to configure the size of L2 Tx FIFO for Tx channel 0. 0:16 bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 bytes. 7: 72 bytes. 8: 80 bytes."]
+    #[inline(always)]
+    pub fn out_size(&mut self) -> OUT_SIZE_W<OUT_SRAM_SIZE_CH_SPEC> {
+        OUT_SIZE_W::new(self, 0)
+    }
+}
+#[doc = "Transmit L2 FIFO depth of Tx channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`out_sram_size_ch::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`out_sram_size_ch::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct OUT_SRAM_SIZE_CH_SPEC;
+impl crate::RegisterSpec for OUT_SRAM_SIZE_CH_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`out_sram_size_ch::R`](R) reader structure"]
+impl crate::Readable for OUT_SRAM_SIZE_CH_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`out_sram_size_ch::W`](W) writer structure"]
+impl crate::Writable for OUT_SRAM_SIZE_CH_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets OUT_SRAM_SIZE_CH%s to value 0x0e"]
+impl crate::Resettable for OUT_SRAM_SIZE_CH_SPEC {
+    const RESET_VALUE: u32 = 0x0e;
+}

vendor/esp32s3/src/dma/pd_conf.rs

@@ -0,0 +1,77 @@
+#[doc = "Register `PD_CONF` reader"]
+pub type R = crate::R<PD_CONF_SPEC>;
+#[doc = "Register `PD_CONF` writer"]
+pub type W = crate::W<PD_CONF_SPEC>;
+#[doc = "Field `DMA_RAM_FORCE_PD` reader - Set this bit to force power down DMA internal memory."]
+pub type DMA_RAM_FORCE_PD_R = crate::BitReader;
+#[doc = "Field `DMA_RAM_FORCE_PD` writer - Set this bit to force power down DMA internal memory."]
+pub type DMA_RAM_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DMA_RAM_FORCE_PU` reader - Set this bit to force power up DMA internal memory"]
+pub type DMA_RAM_FORCE_PU_R = crate::BitReader;
+#[doc = "Field `DMA_RAM_FORCE_PU` writer - Set this bit to force power up DMA internal memory"]
+pub type DMA_RAM_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DMA_RAM_CLK_FO` reader - 1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. 0: A gate-clock will be used when accessing the RAM in DMA."]
+pub type DMA_RAM_CLK_FO_R = crate::BitReader;
+#[doc = "Field `DMA_RAM_CLK_FO` writer - 1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. 0: A gate-clock will be used when accessing the RAM in DMA."]
+pub type DMA_RAM_CLK_FO_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 4 - Set this bit to force power down DMA internal memory."]
+    #[inline(always)]
+    pub fn dma_ram_force_pd(&self) -> DMA_RAM_FORCE_PD_R {
+        DMA_RAM_FORCE_PD_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - Set this bit to force power up DMA internal memory"]
+    #[inline(always)]
+    pub fn dma_ram_force_pu(&self) -> DMA_RAM_FORCE_PU_R {
+        DMA_RAM_FORCE_PU_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - 1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. 0: A gate-clock will be used when accessing the RAM in DMA."]
+    #[inline(always)]
+    pub fn dma_ram_clk_fo(&self) -> DMA_RAM_CLK_FO_R {
+        DMA_RAM_CLK_FO_R::new(((self.bits >> 6) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("PD_CONF")
+            .field("dma_ram_force_pd", &self.dma_ram_force_pd())
+            .field("dma_ram_force_pu", &self.dma_ram_force_pu())
+            .field("dma_ram_clk_fo", &self.dma_ram_clk_fo())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 4 - Set this bit to force power down DMA internal memory."]
+    #[inline(always)]
+    pub fn dma_ram_force_pd(&mut self) -> DMA_RAM_FORCE_PD_W<PD_CONF_SPEC> {
+        DMA_RAM_FORCE_PD_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - Set this bit to force power up DMA internal memory"]
+    #[inline(always)]
+    pub fn dma_ram_force_pu(&mut self) -> DMA_RAM_FORCE_PU_W<PD_CONF_SPEC> {
+        DMA_RAM_FORCE_PU_W::new(self, 5)
+    }
+    #[doc = "Bit 6 - 1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. 0: A gate-clock will be used when accessing the RAM in DMA."]
+    #[inline(always)]
+    pub fn dma_ram_clk_fo(&mut self) -> DMA_RAM_CLK_FO_W<PD_CONF_SPEC> {
+        DMA_RAM_CLK_FO_W::new(self, 6)
+    }
+}
+#[doc = "reserved\n\nYou can [`read`](crate::Reg::read) this register and get [`pd_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pd_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct PD_CONF_SPEC;
+impl crate::RegisterSpec for PD_CONF_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`pd_conf::R`](R) reader structure"]
+impl crate::Readable for PD_CONF_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`pd_conf::W`](W) writer structure"]
+impl crate::Writable for PD_CONF_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets PD_CONF to value 0x20"]
+impl crate::Resettable for PD_CONF_SPEC {
+    const RESET_VALUE: u32 = 0x20;
+}