feat: add display UI with splash screen, dashboard, and RSSI sparkline

Implement full SSD1306 OLED display support:
- Splash screen on boot (1.5s) with project name, version, board
- Dashboard showing radio state, config, counters, RSSI/SNR
- RSSI history sparkline (64-sample ring buffer, 2px-wide bars)
- DisplayOn/DisplayOff host commands routed via dedicated channel
- Pure render functions against generic DrawTarget (no hardware coupling)
- Display on/off control bypasses radio task entirely

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>

vendor/esp32s3/src/gpio_sd/clock_gate.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `CLOCK_GATE` reader"]
+pub type R = crate::R<CLOCK_GATE_SPEC>;
+#[doc = "Register `CLOCK_GATE` writer"]
+pub type W = crate::W<CLOCK_GATE_SPEC>;
+#[doc = "Field `CLK_EN` reader - Clock enable bit of configuration registers for sigma delta modulation."]
+pub type CLK_EN_R = crate::BitReader;
+#[doc = "Field `CLK_EN` writer - Clock enable bit of configuration registers for sigma delta modulation."]
+pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 31 - Clock enable bit of configuration registers for sigma delta modulation."]
+    #[inline(always)]
+    pub fn clk_en(&self) -> CLK_EN_R {
+        CLK_EN_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CLOCK_GATE")
+            .field("clk_en", &self.clk_en())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 31 - Clock enable bit of configuration registers for sigma delta modulation."]
+    #[inline(always)]
+    pub fn clk_en(&mut self) -> CLK_EN_W<CLOCK_GATE_SPEC> {
+        CLK_EN_W::new(self, 31)
+    }
+}
+#[doc = "Clock Gating Configure Register\n\nYou can [`read`](crate::Reg::read) this register and get [`clock_gate::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clock_gate::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CLOCK_GATE_SPEC;
+impl crate::RegisterSpec for CLOCK_GATE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`clock_gate::R`](R) reader structure"]
+impl crate::Readable for CLOCK_GATE_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`clock_gate::W`](W) writer structure"]
+impl crate::Writable for CLOCK_GATE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CLOCK_GATE to value 0"]
+impl crate::Resettable for CLOCK_GATE_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/gpio_sd/sigmadelta.rs

@@ -0,0 +1,62 @@
+#[doc = "Register `SIGMADELTA%s` reader"]
+pub type R = crate::R<SIGMADELTA_SPEC>;
+#[doc = "Register `SIGMADELTA%s` writer"]
+pub type W = crate::W<SIGMADELTA_SPEC>;
+#[doc = "Field `IN` reader - This field is used to configure the duty cycle of sigma delta modulation output."]
+pub type IN_R = crate::FieldReader;
+#[doc = "Field `IN` writer - This field is used to configure the duty cycle of sigma delta modulation output."]
+pub type IN_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+#[doc = "Field `PRESCALE` reader - This field is used to set a divider value to divide APB clock."]
+pub type PRESCALE_R = crate::FieldReader;
+#[doc = "Field `PRESCALE` writer - This field is used to set a divider value to divide APB clock."]
+pub type PRESCALE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+impl R {
+    #[doc = "Bits 0:7 - This field is used to configure the duty cycle of sigma delta modulation output."]
+    #[inline(always)]
+    pub fn in_(&self) -> IN_R {
+        IN_R::new((self.bits & 0xff) as u8)
+    }
+    #[doc = "Bits 8:15 - This field is used to set a divider value to divide APB clock."]
+    #[inline(always)]
+    pub fn prescale(&self) -> PRESCALE_R {
+        PRESCALE_R::new(((self.bits >> 8) & 0xff) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SIGMADELTA")
+            .field("in_", &self.in_())
+            .field("prescale", &self.prescale())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - This field is used to configure the duty cycle of sigma delta modulation output."]
+    #[inline(always)]
+    pub fn in_(&mut self) -> IN_W<SIGMADELTA_SPEC> {
+        IN_W::new(self, 0)
+    }
+    #[doc = "Bits 8:15 - This field is used to set a divider value to divide APB clock."]
+    #[inline(always)]
+    pub fn prescale(&mut self) -> PRESCALE_W<SIGMADELTA_SPEC> {
+        PRESCALE_W::new(self, 8)
+    }
+}
+#[doc = "Duty Cycle Configure Register of SDM%s\n\nYou can [`read`](crate::Reg::read) this register and get [`sigmadelta::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sigmadelta::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SIGMADELTA_SPEC;
+impl crate::RegisterSpec for SIGMADELTA_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sigmadelta::R`](R) reader structure"]
+impl crate::Readable for SIGMADELTA_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sigmadelta::W`](W) writer structure"]
+impl crate::Writable for SIGMADELTA_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SIGMADELTA%s to value 0xff00"]
+impl crate::Resettable for SIGMADELTA_SPEC {
+    const RESET_VALUE: u32 = 0xff00;
+}

vendor/esp32s3/src/gpio_sd/sigmadelta_misc.rs

@@ -0,0 +1,62 @@
+#[doc = "Register `SIGMADELTA_MISC` reader"]
+pub type R = crate::R<SIGMADELTA_MISC_SPEC>;
+#[doc = "Register `SIGMADELTA_MISC` writer"]
+pub type W = crate::W<SIGMADELTA_MISC_SPEC>;
+#[doc = "Field `FUNCTION_CLK_EN` reader - Clock enable bit of sigma delta modulation."]
+pub type FUNCTION_CLK_EN_R = crate::BitReader;
+#[doc = "Field `FUNCTION_CLK_EN` writer - Clock enable bit of sigma delta modulation."]
+pub type FUNCTION_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SPI_SWAP` reader - Reserved."]
+pub type SPI_SWAP_R = crate::BitReader;
+#[doc = "Field `SPI_SWAP` writer - Reserved."]
+pub type SPI_SWAP_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 30 - Clock enable bit of sigma delta modulation."]
+    #[inline(always)]
+    pub fn function_clk_en(&self) -> FUNCTION_CLK_EN_R {
+        FUNCTION_CLK_EN_R::new(((self.bits >> 30) & 1) != 0)
+    }
+    #[doc = "Bit 31 - Reserved."]
+    #[inline(always)]
+    pub fn spi_swap(&self) -> SPI_SWAP_R {
+        SPI_SWAP_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SIGMADELTA_MISC")
+            .field("function_clk_en", &self.function_clk_en())
+            .field("spi_swap", &self.spi_swap())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 30 - Clock enable bit of sigma delta modulation."]
+    #[inline(always)]
+    pub fn function_clk_en(&mut self) -> FUNCTION_CLK_EN_W<SIGMADELTA_MISC_SPEC> {
+        FUNCTION_CLK_EN_W::new(self, 30)
+    }
+    #[doc = "Bit 31 - Reserved."]
+    #[inline(always)]
+    pub fn spi_swap(&mut self) -> SPI_SWAP_W<SIGMADELTA_MISC_SPEC> {
+        SPI_SWAP_W::new(self, 31)
+    }
+}
+#[doc = "MISC Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sigmadelta_misc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sigmadelta_misc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SIGMADELTA_MISC_SPEC;
+impl crate::RegisterSpec for SIGMADELTA_MISC_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sigmadelta_misc::R`](R) reader structure"]
+impl crate::Readable for SIGMADELTA_MISC_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sigmadelta_misc::W`](W) writer structure"]
+impl crate::Writable for SIGMADELTA_MISC_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SIGMADELTA_MISC to value 0"]
+impl crate::Resettable for SIGMADELTA_MISC_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/gpio_sd/version.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `VERSION` reader"]
+pub type R = crate::R<VERSION_SPEC>;
+#[doc = "Register `VERSION` writer"]
+pub type W = crate::W<VERSION_SPEC>;
+#[doc = "Field `GPIO_SD_DATE` reader - Version control register."]
+pub type GPIO_SD_DATE_R = crate::FieldReader<u32>;
+#[doc = "Field `GPIO_SD_DATE` writer - Version control register."]
+pub type GPIO_SD_DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>;
+impl R {
+    #[doc = "Bits 0:27 - Version control register."]
+    #[inline(always)]
+    pub fn gpio_sd_date(&self) -> GPIO_SD_DATE_R {
+        GPIO_SD_DATE_R::new(self.bits & 0x0fff_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("VERSION")
+            .field("gpio_sd_date", &self.gpio_sd_date())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:27 - Version control register."]
+    #[inline(always)]
+    pub fn gpio_sd_date(&mut self) -> GPIO_SD_DATE_W<VERSION_SPEC> {
+        GPIO_SD_DATE_W::new(self, 0)
+    }
+}
+#[doc = "Version Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`version::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`version::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct VERSION_SPEC;
+impl crate::RegisterSpec for VERSION_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`version::R`](R) reader structure"]
+impl crate::Readable for VERSION_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`version::W`](W) writer structure"]
+impl crate::Writable for VERSION_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets VERSION to value 0x0180_2260"]
+impl crate::Resettable for VERSION_SPEC {
+    const RESET_VALUE: u32 = 0x0180_2260;
+}