feat: add display UI with splash screen, dashboard, and RSSI sparkline

Implement full SSD1306 OLED display support:
- Splash screen on boot (1.5s) with project name, version, board
- Dashboard showing radio state, config, counters, RSSI/SNR
- RSSI history sparkline (64-sample ring buffer, 2px-wide bars)
- DisplayOn/DisplayOff host commands routed via dedicated channel
- Pure render functions against generic DrawTarget (no hardware coupling)
- Display on/off control bypasses radio task entirely

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>

vendor/esp32s3/src/i2s0/conf_sigle_data.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `CONF_SIGLE_DATA` reader"]
+pub type R = crate::R<CONF_SIGLE_DATA_SPEC>;
+#[doc = "Register `CONF_SIGLE_DATA` writer"]
+pub type W = crate::W<CONF_SIGLE_DATA_SPEC>;
+#[doc = "Field `SINGLE_DATA` reader - The configured constant channel data to be sent out."]
+pub type SINGLE_DATA_R = crate::FieldReader<u32>;
+#[doc = "Field `SINGLE_DATA` writer - The configured constant channel data to be sent out."]
+pub type SINGLE_DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - The configured constant channel data to be sent out."]
+    #[inline(always)]
+    pub fn single_data(&self) -> SINGLE_DATA_R {
+        SINGLE_DATA_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CONF_SIGLE_DATA")
+            .field("single_data", &self.single_data())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - The configured constant channel data to be sent out."]
+    #[inline(always)]
+    pub fn single_data(&mut self) -> SINGLE_DATA_W<CONF_SIGLE_DATA_SPEC> {
+        SINGLE_DATA_W::new(self, 0)
+    }
+}
+#[doc = "I2S signal data register\n\nYou can [`read`](crate::Reg::read) this register and get [`conf_sigle_data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`conf_sigle_data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CONF_SIGLE_DATA_SPEC;
+impl crate::RegisterSpec for CONF_SIGLE_DATA_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`conf_sigle_data::R`](R) reader structure"]
+impl crate::Readable for CONF_SIGLE_DATA_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`conf_sigle_data::W`](W) writer structure"]
+impl crate::Writable for CONF_SIGLE_DATA_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CONF_SIGLE_DATA to value 0"]
+impl crate::Resettable for CONF_SIGLE_DATA_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/i2s0/date.rs

@@ -0,0 +1,45 @@
+#[doc = "Register `DATE` reader"]
+pub type R = crate::R<DATE_SPEC>;
+#[doc = "Register `DATE` writer"]
+pub type W = crate::W<DATE_SPEC>;
+#[doc = "Field `DATE` reader - I2S version control register"]
+pub type DATE_R = crate::FieldReader<u32>;
+#[doc = "Field `DATE` writer - I2S version control register"]
+pub type DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>;
+impl R {
+    #[doc = "Bits 0:27 - I2S version control register"]
+    #[inline(always)]
+    pub fn date(&self) -> DATE_R {
+        DATE_R::new(self.bits & 0x0fff_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DATE").field("date", &self.date()).finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:27 - I2S version control register"]
+    #[inline(always)]
+    pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
+        DATE_W::new(self, 0)
+    }
+}
+#[doc = "Version control register\n\nYou can [`read`](crate::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DATE_SPEC;
+impl crate::RegisterSpec for DATE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`date::R`](R) reader structure"]
+impl crate::Readable for DATE_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"]
+impl crate::Writable for DATE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DATE to value 0x0200_9070"]
+impl crate::Resettable for DATE_SPEC {
+    const RESET_VALUE: u32 = 0x0200_9070;
+}

vendor/esp32s3/src/i2s0/int_clr.rs

@@ -0,0 +1,53 @@
+#[doc = "Register `INT_CLR` writer"]
+pub type W = crate::W<INT_CLR_SPEC>;
+#[doc = "Field `RX_DONE` writer - Set this bit to clear the i2s_rx_done_int interrupt"]
+pub type RX_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TX_DONE` writer - Set this bit to clear the i2s_tx_done_int interrupt"]
+pub type TX_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `RX_HUNG` writer - Set this bit to clear the i2s_rx_hung_int interrupt"]
+pub type RX_HUNG_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TX_HUNG` writer - Set this bit to clear the i2s_tx_hung_int interrupt"]
+pub type TX_HUNG_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "(not readable)")
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Set this bit to clear the i2s_rx_done_int interrupt"]
+    #[inline(always)]
+    pub fn rx_done(&mut self) -> RX_DONE_W<INT_CLR_SPEC> {
+        RX_DONE_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - Set this bit to clear the i2s_tx_done_int interrupt"]
+    #[inline(always)]
+    pub fn tx_done(&mut self) -> TX_DONE_W<INT_CLR_SPEC> {
+        TX_DONE_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - Set this bit to clear the i2s_rx_hung_int interrupt"]
+    #[inline(always)]
+    pub fn rx_hung(&mut self) -> RX_HUNG_W<INT_CLR_SPEC> {
+        RX_HUNG_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - Set this bit to clear the i2s_tx_hung_int interrupt"]
+    #[inline(always)]
+    pub fn tx_hung(&mut self) -> TX_HUNG_W<INT_CLR_SPEC> {
+        TX_HUNG_W::new(self, 3)
+    }
+}
+#[doc = "I2S interrupt clear register.\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct INT_CLR_SPEC;
+impl crate::RegisterSpec for INT_CLR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
+impl crate::Writable for INT_CLR_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0f;
+}
+#[doc = "`reset()` method sets INT_CLR to value 0"]
+impl crate::Resettable for INT_CLR_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/i2s0/int_ena.rs

@@ -0,0 +1,92 @@
+#[doc = "Register `INT_ENA` reader"]
+pub type R = crate::R<INT_ENA_SPEC>;
+#[doc = "Register `INT_ENA` writer"]
+pub type W = crate::W<INT_ENA_SPEC>;
+#[doc = "Field `RX_DONE` reader - The interrupt enable bit for the i2s_rx_done_int interrupt"]
+pub type RX_DONE_R = crate::BitReader;
+#[doc = "Field `RX_DONE` writer - The interrupt enable bit for the i2s_rx_done_int interrupt"]
+pub type RX_DONE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TX_DONE` reader - The interrupt enable bit for the i2s_tx_done_int interrupt"]
+pub type TX_DONE_R = crate::BitReader;
+#[doc = "Field `TX_DONE` writer - The interrupt enable bit for the i2s_tx_done_int interrupt"]
+pub type TX_DONE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RX_HUNG` reader - The interrupt enable bit for the i2s_rx_hung_int interrupt"]
+pub type RX_HUNG_R = crate::BitReader;
+#[doc = "Field `RX_HUNG` writer - The interrupt enable bit for the i2s_rx_hung_int interrupt"]
+pub type RX_HUNG_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TX_HUNG` reader - The interrupt enable bit for the i2s_tx_hung_int interrupt"]
+pub type TX_HUNG_R = crate::BitReader;
+#[doc = "Field `TX_HUNG` writer - The interrupt enable bit for the i2s_tx_hung_int interrupt"]
+pub type TX_HUNG_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - The interrupt enable bit for the i2s_rx_done_int interrupt"]
+    #[inline(always)]
+    pub fn rx_done(&self) -> RX_DONE_R {
+        RX_DONE_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - The interrupt enable bit for the i2s_tx_done_int interrupt"]
+    #[inline(always)]
+    pub fn tx_done(&self) -> TX_DONE_R {
+        TX_DONE_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - The interrupt enable bit for the i2s_rx_hung_int interrupt"]
+    #[inline(always)]
+    pub fn rx_hung(&self) -> RX_HUNG_R {
+        RX_HUNG_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - The interrupt enable bit for the i2s_tx_hung_int interrupt"]
+    #[inline(always)]
+    pub fn tx_hung(&self) -> TX_HUNG_R {
+        TX_HUNG_R::new(((self.bits >> 3) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("INT_ENA")
+            .field("rx_done", &self.rx_done())
+            .field("tx_done", &self.tx_done())
+            .field("rx_hung", &self.rx_hung())
+            .field("tx_hung", &self.tx_hung())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - The interrupt enable bit for the i2s_rx_done_int interrupt"]
+    #[inline(always)]
+    pub fn rx_done(&mut self) -> RX_DONE_W<INT_ENA_SPEC> {
+        RX_DONE_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - The interrupt enable bit for the i2s_tx_done_int interrupt"]
+    #[inline(always)]
+    pub fn tx_done(&mut self) -> TX_DONE_W<INT_ENA_SPEC> {
+        TX_DONE_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - The interrupt enable bit for the i2s_rx_hung_int interrupt"]
+    #[inline(always)]
+    pub fn rx_hung(&mut self) -> RX_HUNG_W<INT_ENA_SPEC> {
+        RX_HUNG_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - The interrupt enable bit for the i2s_tx_hung_int interrupt"]
+    #[inline(always)]
+    pub fn tx_hung(&mut self) -> TX_HUNG_W<INT_ENA_SPEC> {
+        TX_HUNG_W::new(self, 3)
+    }
+}
+#[doc = "I2S interrupt enable register.\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct INT_ENA_SPEC;
+impl crate::RegisterSpec for INT_ENA_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"]
+impl crate::Readable for INT_ENA_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"]
+impl crate::Writable for INT_ENA_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets INT_ENA to value 0"]
+impl crate::Resettable for INT_ENA_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/i2s0/int_raw.rs

@@ -0,0 +1,54 @@
+#[doc = "Register `INT_RAW` reader"]
+pub type R = crate::R<INT_RAW_SPEC>;
+#[doc = "Field `RX_DONE` reader - The raw interrupt status bit for the i2s_rx_done_int interrupt"]
+pub type RX_DONE_R = crate::BitReader;
+#[doc = "Field `TX_DONE` reader - The raw interrupt status bit for the i2s_tx_done_int interrupt"]
+pub type TX_DONE_R = crate::BitReader;
+#[doc = "Field `RX_HUNG` reader - The raw interrupt status bit for the i2s_rx_hung_int interrupt"]
+pub type RX_HUNG_R = crate::BitReader;
+#[doc = "Field `TX_HUNG` reader - The raw interrupt status bit for the i2s_tx_hung_int interrupt"]
+pub type TX_HUNG_R = crate::BitReader;
+impl R {
+    #[doc = "Bit 0 - The raw interrupt status bit for the i2s_rx_done_int interrupt"]
+    #[inline(always)]
+    pub fn rx_done(&self) -> RX_DONE_R {
+        RX_DONE_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - The raw interrupt status bit for the i2s_tx_done_int interrupt"]
+    #[inline(always)]
+    pub fn tx_done(&self) -> TX_DONE_R {
+        TX_DONE_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - The raw interrupt status bit for the i2s_rx_hung_int interrupt"]
+    #[inline(always)]
+    pub fn rx_hung(&self) -> RX_HUNG_R {
+        RX_HUNG_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - The raw interrupt status bit for the i2s_tx_hung_int interrupt"]
+    #[inline(always)]
+    pub fn tx_hung(&self) -> TX_HUNG_R {
+        TX_HUNG_R::new(((self.bits >> 3) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("INT_RAW")
+            .field("rx_done", &self.rx_done())
+            .field("tx_done", &self.tx_done())
+            .field("rx_hung", &self.rx_hung())
+            .field("tx_hung", &self.tx_hung())
+            .finish()
+    }
+}
+#[doc = "I2S interrupt raw register, valid in level.\n\nYou can [`read`](crate::Reg::read) this register and get [`int_raw::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct INT_RAW_SPEC;
+impl crate::RegisterSpec for INT_RAW_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"]
+impl crate::Readable for INT_RAW_SPEC {}
+#[doc = "`reset()` method sets INT_RAW to value 0"]
+impl crate::Resettable for INT_RAW_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/i2s0/int_st.rs

@@ -0,0 +1,54 @@
+#[doc = "Register `INT_ST` reader"]
+pub type R = crate::R<INT_ST_SPEC>;
+#[doc = "Field `RX_DONE` reader - The masked interrupt status bit for the i2s_rx_done_int interrupt"]
+pub type RX_DONE_R = crate::BitReader;
+#[doc = "Field `TX_DONE` reader - The masked interrupt status bit for the i2s_tx_done_int interrupt"]
+pub type TX_DONE_R = crate::BitReader;
+#[doc = "Field `RX_HUNG` reader - The masked interrupt status bit for the i2s_rx_hung_int interrupt"]
+pub type RX_HUNG_R = crate::BitReader;
+#[doc = "Field `TX_HUNG` reader - The masked interrupt status bit for the i2s_tx_hung_int interrupt"]
+pub type TX_HUNG_R = crate::BitReader;
+impl R {
+    #[doc = "Bit 0 - The masked interrupt status bit for the i2s_rx_done_int interrupt"]
+    #[inline(always)]
+    pub fn rx_done(&self) -> RX_DONE_R {
+        RX_DONE_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - The masked interrupt status bit for the i2s_tx_done_int interrupt"]
+    #[inline(always)]
+    pub fn tx_done(&self) -> TX_DONE_R {
+        TX_DONE_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - The masked interrupt status bit for the i2s_rx_hung_int interrupt"]
+    #[inline(always)]
+    pub fn rx_hung(&self) -> RX_HUNG_R {
+        RX_HUNG_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - The masked interrupt status bit for the i2s_tx_hung_int interrupt"]
+    #[inline(always)]
+    pub fn tx_hung(&self) -> TX_HUNG_R {
+        TX_HUNG_R::new(((self.bits >> 3) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("INT_ST")
+            .field("rx_done", &self.rx_done())
+            .field("tx_done", &self.tx_done())
+            .field("rx_hung", &self.rx_hung())
+            .field("tx_hung", &self.tx_hung())
+            .finish()
+    }
+}
+#[doc = "I2S interrupt status register.\n\nYou can [`read`](crate::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct INT_ST_SPEC;
+impl crate::RegisterSpec for INT_ST_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`int_st::R`](R) reader structure"]
+impl crate::Readable for INT_ST_SPEC {}
+#[doc = "`reset()` method sets INT_ST to value 0"]
+impl crate::Resettable for INT_ST_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/i2s0/lc_hung_conf.rs

@@ -0,0 +1,77 @@
+#[doc = "Register `LC_HUNG_CONF` reader"]
+pub type R = crate::R<LC_HUNG_CONF_SPEC>;
+#[doc = "Register `LC_HUNG_CONF` writer"]
+pub type W = crate::W<LC_HUNG_CONF_SPEC>;
+#[doc = "Field `LC_FIFO_TIMEOUT` reader - the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value"]
+pub type LC_FIFO_TIMEOUT_R = crate::FieldReader;
+#[doc = "Field `LC_FIFO_TIMEOUT` writer - the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value"]
+pub type LC_FIFO_TIMEOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+#[doc = "Field `LC_FIFO_TIMEOUT_SHIFT` reader - The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift"]
+pub type LC_FIFO_TIMEOUT_SHIFT_R = crate::FieldReader;
+#[doc = "Field `LC_FIFO_TIMEOUT_SHIFT` writer - The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift"]
+pub type LC_FIFO_TIMEOUT_SHIFT_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `LC_FIFO_TIMEOUT_ENA` reader - The enable bit for FIFO timeout"]
+pub type LC_FIFO_TIMEOUT_ENA_R = crate::BitReader;
+#[doc = "Field `LC_FIFO_TIMEOUT_ENA` writer - The enable bit for FIFO timeout"]
+pub type LC_FIFO_TIMEOUT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 0:7 - the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value"]
+    #[inline(always)]
+    pub fn lc_fifo_timeout(&self) -> LC_FIFO_TIMEOUT_R {
+        LC_FIFO_TIMEOUT_R::new((self.bits & 0xff) as u8)
+    }
+    #[doc = "Bits 8:10 - The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift"]
+    #[inline(always)]
+    pub fn lc_fifo_timeout_shift(&self) -> LC_FIFO_TIMEOUT_SHIFT_R {
+        LC_FIFO_TIMEOUT_SHIFT_R::new(((self.bits >> 8) & 7) as u8)
+    }
+    #[doc = "Bit 11 - The enable bit for FIFO timeout"]
+    #[inline(always)]
+    pub fn lc_fifo_timeout_ena(&self) -> LC_FIFO_TIMEOUT_ENA_R {
+        LC_FIFO_TIMEOUT_ENA_R::new(((self.bits >> 11) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("LC_HUNG_CONF")
+            .field("lc_fifo_timeout", &self.lc_fifo_timeout())
+            .field("lc_fifo_timeout_shift", &self.lc_fifo_timeout_shift())
+            .field("lc_fifo_timeout_ena", &self.lc_fifo_timeout_ena())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value"]
+    #[inline(always)]
+    pub fn lc_fifo_timeout(&mut self) -> LC_FIFO_TIMEOUT_W<LC_HUNG_CONF_SPEC> {
+        LC_FIFO_TIMEOUT_W::new(self, 0)
+    }
+    #[doc = "Bits 8:10 - The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift"]
+    #[inline(always)]
+    pub fn lc_fifo_timeout_shift(&mut self) -> LC_FIFO_TIMEOUT_SHIFT_W<LC_HUNG_CONF_SPEC> {
+        LC_FIFO_TIMEOUT_SHIFT_W::new(self, 8)
+    }
+    #[doc = "Bit 11 - The enable bit for FIFO timeout"]
+    #[inline(always)]
+    pub fn lc_fifo_timeout_ena(&mut self) -> LC_FIFO_TIMEOUT_ENA_W<LC_HUNG_CONF_SPEC> {
+        LC_FIFO_TIMEOUT_ENA_W::new(self, 11)
+    }
+}
+#[doc = "I2S HUNG configure register.\n\nYou can [`read`](crate::Reg::read) this register and get [`lc_hung_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lc_hung_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct LC_HUNG_CONF_SPEC;
+impl crate::RegisterSpec for LC_HUNG_CONF_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`lc_hung_conf::R`](R) reader structure"]
+impl crate::Readable for LC_HUNG_CONF_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`lc_hung_conf::W`](W) writer structure"]
+impl crate::Writable for LC_HUNG_CONF_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets LC_HUNG_CONF to value 0x0810"]
+impl crate::Resettable for LC_HUNG_CONF_SPEC {
+    const RESET_VALUE: u32 = 0x0810;
+}

vendor/esp32s3/src/i2s0/rx_clkm_conf.rs

@@ -0,0 +1,92 @@
+#[doc = "Register `RX_CLKM_CONF` reader"]
+pub type R = crate::R<RX_CLKM_CONF_SPEC>;
+#[doc = "Register `RX_CLKM_CONF` writer"]
+pub type W = crate::W<RX_CLKM_CONF_SPEC>;
+#[doc = "Field `RX_CLKM_DIV_NUM` reader - Integral I2S clock divider value"]
+pub type RX_CLKM_DIV_NUM_R = crate::FieldReader;
+#[doc = "Field `RX_CLKM_DIV_NUM` writer - Integral I2S clock divider value"]
+pub type RX_CLKM_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+#[doc = "Field `RX_CLK_ACTIVE` reader - I2S Rx module clock enable signal."]
+pub type RX_CLK_ACTIVE_R = crate::BitReader;
+#[doc = "Field `RX_CLK_ACTIVE` writer - I2S Rx module clock enable signal."]
+pub type RX_CLK_ACTIVE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RX_CLK_SEL` reader - Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in."]
+pub type RX_CLK_SEL_R = crate::FieldReader;
+#[doc = "Field `RX_CLK_SEL` writer - Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in."]
+pub type RX_CLK_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `MCLK_SEL` reader - 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MCLK_OUT."]
+pub type MCLK_SEL_R = crate::BitReader;
+#[doc = "Field `MCLK_SEL` writer - 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MCLK_OUT."]
+pub type MCLK_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 0:7 - Integral I2S clock divider value"]
+    #[inline(always)]
+    pub fn rx_clkm_div_num(&self) -> RX_CLKM_DIV_NUM_R {
+        RX_CLKM_DIV_NUM_R::new((self.bits & 0xff) as u8)
+    }
+    #[doc = "Bit 26 - I2S Rx module clock enable signal."]
+    #[inline(always)]
+    pub fn rx_clk_active(&self) -> RX_CLK_ACTIVE_R {
+        RX_CLK_ACTIVE_R::new(((self.bits >> 26) & 1) != 0)
+    }
+    #[doc = "Bits 27:28 - Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in."]
+    #[inline(always)]
+    pub fn rx_clk_sel(&self) -> RX_CLK_SEL_R {
+        RX_CLK_SEL_R::new(((self.bits >> 27) & 3) as u8)
+    }
+    #[doc = "Bit 29 - 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MCLK_OUT."]
+    #[inline(always)]
+    pub fn mclk_sel(&self) -> MCLK_SEL_R {
+        MCLK_SEL_R::new(((self.bits >> 29) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("RX_CLKM_CONF")
+            .field("rx_clkm_div_num", &self.rx_clkm_div_num())
+            .field("rx_clk_active", &self.rx_clk_active())
+            .field("rx_clk_sel", &self.rx_clk_sel())
+            .field("mclk_sel", &self.mclk_sel())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - Integral I2S clock divider value"]
+    #[inline(always)]
+    pub fn rx_clkm_div_num(&mut self) -> RX_CLKM_DIV_NUM_W<RX_CLKM_CONF_SPEC> {
+        RX_CLKM_DIV_NUM_W::new(self, 0)
+    }
+    #[doc = "Bit 26 - I2S Rx module clock enable signal."]
+    #[inline(always)]
+    pub fn rx_clk_active(&mut self) -> RX_CLK_ACTIVE_W<RX_CLKM_CONF_SPEC> {
+        RX_CLK_ACTIVE_W::new(self, 26)
+    }
+    #[doc = "Bits 27:28 - Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in."]
+    #[inline(always)]
+    pub fn rx_clk_sel(&mut self) -> RX_CLK_SEL_W<RX_CLKM_CONF_SPEC> {
+        RX_CLK_SEL_W::new(self, 27)
+    }
+    #[doc = "Bit 29 - 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MCLK_OUT."]
+    #[inline(always)]
+    pub fn mclk_sel(&mut self) -> MCLK_SEL_W<RX_CLKM_CONF_SPEC> {
+        MCLK_SEL_W::new(self, 29)
+    }
+}
+#[doc = "I2S RX clock configure register\n\nYou can [`read`](crate::Reg::read) this register and get [`rx_clkm_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx_clkm_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct RX_CLKM_CONF_SPEC;
+impl crate::RegisterSpec for RX_CLKM_CONF_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`rx_clkm_conf::R`](R) reader structure"]
+impl crate::Readable for RX_CLKM_CONF_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`rx_clkm_conf::W`](W) writer structure"]
+impl crate::Writable for RX_CLKM_CONF_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets RX_CLKM_CONF to value 0x02"]
+impl crate::Resettable for RX_CLKM_CONF_SPEC {
+    const RESET_VALUE: u32 = 0x02;
+}

vendor/esp32s3/src/i2s0/rx_clkm_div_conf.rs

@@ -0,0 +1,92 @@
+#[doc = "Register `RX_CLKM_DIV_CONF` reader"]
+pub type R = crate::R<RX_CLKM_DIV_CONF_SPEC>;
+#[doc = "Register `RX_CLKM_DIV_CONF` writer"]
+pub type W = crate::W<RX_CLKM_DIV_CONF_SPEC>;
+#[doc = "Field `RX_CLKM_DIV_Z` reader - For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b)."]
+pub type RX_CLKM_DIV_Z_R = crate::FieldReader<u16>;
+#[doc = "Field `RX_CLKM_DIV_Z` writer - For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b)."]
+pub type RX_CLKM_DIV_Z_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
+#[doc = "Field `RX_CLKM_DIV_Y` reader - For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b))."]
+pub type RX_CLKM_DIV_Y_R = crate::FieldReader<u16>;
+#[doc = "Field `RX_CLKM_DIV_Y` writer - For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b))."]
+pub type RX_CLKM_DIV_Y_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
+#[doc = "Field `RX_CLKM_DIV_X` reader - For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1."]
+pub type RX_CLKM_DIV_X_R = crate::FieldReader<u16>;
+#[doc = "Field `RX_CLKM_DIV_X` writer - For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1."]
+pub type RX_CLKM_DIV_X_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
+#[doc = "Field `RX_CLKM_DIV_YN1` reader - For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1."]
+pub type RX_CLKM_DIV_YN1_R = crate::BitReader;
+#[doc = "Field `RX_CLKM_DIV_YN1` writer - For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1."]
+pub type RX_CLKM_DIV_YN1_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 0:8 - For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b)."]
+    #[inline(always)]
+    pub fn rx_clkm_div_z(&self) -> RX_CLKM_DIV_Z_R {
+        RX_CLKM_DIV_Z_R::new((self.bits & 0x01ff) as u16)
+    }
+    #[doc = "Bits 9:17 - For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b))."]
+    #[inline(always)]
+    pub fn rx_clkm_div_y(&self) -> RX_CLKM_DIV_Y_R {
+        RX_CLKM_DIV_Y_R::new(((self.bits >> 9) & 0x01ff) as u16)
+    }
+    #[doc = "Bits 18:26 - For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1."]
+    #[inline(always)]
+    pub fn rx_clkm_div_x(&self) -> RX_CLKM_DIV_X_R {
+        RX_CLKM_DIV_X_R::new(((self.bits >> 18) & 0x01ff) as u16)
+    }
+    #[doc = "Bit 27 - For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1."]
+    #[inline(always)]
+    pub fn rx_clkm_div_yn1(&self) -> RX_CLKM_DIV_YN1_R {
+        RX_CLKM_DIV_YN1_R::new(((self.bits >> 27) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("RX_CLKM_DIV_CONF")
+            .field("rx_clkm_div_z", &self.rx_clkm_div_z())
+            .field("rx_clkm_div_y", &self.rx_clkm_div_y())
+            .field("rx_clkm_div_x", &self.rx_clkm_div_x())
+            .field("rx_clkm_div_yn1", &self.rx_clkm_div_yn1())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:8 - For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b)."]
+    #[inline(always)]
+    pub fn rx_clkm_div_z(&mut self) -> RX_CLKM_DIV_Z_W<RX_CLKM_DIV_CONF_SPEC> {
+        RX_CLKM_DIV_Z_W::new(self, 0)
+    }
+    #[doc = "Bits 9:17 - For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b))."]
+    #[inline(always)]
+    pub fn rx_clkm_div_y(&mut self) -> RX_CLKM_DIV_Y_W<RX_CLKM_DIV_CONF_SPEC> {
+        RX_CLKM_DIV_Y_W::new(self, 9)
+    }
+    #[doc = "Bits 18:26 - For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1."]
+    #[inline(always)]
+    pub fn rx_clkm_div_x(&mut self) -> RX_CLKM_DIV_X_W<RX_CLKM_DIV_CONF_SPEC> {
+        RX_CLKM_DIV_X_W::new(self, 18)
+    }
+    #[doc = "Bit 27 - For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1."]
+    #[inline(always)]
+    pub fn rx_clkm_div_yn1(&mut self) -> RX_CLKM_DIV_YN1_W<RX_CLKM_DIV_CONF_SPEC> {
+        RX_CLKM_DIV_YN1_W::new(self, 27)
+    }
+}
+#[doc = "I2S RX module clock divider configure register\n\nYou can [`read`](crate::Reg::read) this register and get [`rx_clkm_div_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx_clkm_div_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct RX_CLKM_DIV_CONF_SPEC;
+impl crate::RegisterSpec for RX_CLKM_DIV_CONF_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`rx_clkm_div_conf::R`](R) reader structure"]
+impl crate::Readable for RX_CLKM_DIV_CONF_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`rx_clkm_div_conf::W`](W) writer structure"]
+impl crate::Writable for RX_CLKM_DIV_CONF_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets RX_CLKM_DIV_CONF to value 0x0200"]
+impl crate::Resettable for RX_CLKM_DIV_CONF_SPEC {
+    const RESET_VALUE: u32 = 0x0200;
+}

vendor/esp32s3/src/i2s0/rx_conf.rs

@@ -0,0 +1,301 @@
+#[doc = "Register `RX_CONF` reader"]
+pub type R = crate::R<RX_CONF_SPEC>;
+#[doc = "Register `RX_CONF` writer"]
+pub type W = crate::W<RX_CONF_SPEC>;
+#[doc = "Field `RX_RESET` writer - Set this bit to reset receiver"]
+pub type RX_RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RX_FIFO_RESET` writer - Set this bit to reset Rx AFIFO"]
+pub type RX_FIFO_RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RX_START` reader - Set this bit to start receiving data"]
+pub type RX_START_R = crate::BitReader;
+#[doc = "Field `RX_START` writer - Set this bit to start receiving data"]
+pub type RX_START_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RX_SLAVE_MOD` reader - Set this bit to enable slave receiver mode"]
+pub type RX_SLAVE_MOD_R = crate::BitReader;
+#[doc = "Field `RX_SLAVE_MOD` writer - Set this bit to enable slave receiver mode"]
+pub type RX_SLAVE_MOD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RX_MONO` reader - Set this bit to enable receiver in mono mode"]
+pub type RX_MONO_R = crate::BitReader;
+#[doc = "Field `RX_MONO` writer - Set this bit to enable receiver in mono mode"]
+pub type RX_MONO_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RX_BIG_ENDIAN` reader - I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value."]
+pub type RX_BIG_ENDIAN_R = crate::BitReader;
+#[doc = "Field `RX_BIG_ENDIAN` writer - I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value."]
+pub type RX_BIG_ENDIAN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RX_UPDATE` reader - Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done."]
+pub type RX_UPDATE_R = crate::BitReader;
+#[doc = "Field `RX_UPDATE` writer - Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done."]
+pub type RX_UPDATE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RX_MONO_FST_VLD` reader - 1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode."]
+pub type RX_MONO_FST_VLD_R = crate::BitReader;
+#[doc = "Field `RX_MONO_FST_VLD` writer - 1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode."]
+pub type RX_MONO_FST_VLD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RX_PCM_CONF` reader - I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &"]
+pub type RX_PCM_CONF_R = crate::FieldReader;
+#[doc = "Field `RX_PCM_CONF` writer - I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &"]
+pub type RX_PCM_CONF_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `RX_PCM_BYPASS` reader - Set this bit to bypass Compress/Decompress module for received data."]
+pub type RX_PCM_BYPASS_R = crate::BitReader;
+#[doc = "Field `RX_PCM_BYPASS` writer - Set this bit to bypass Compress/Decompress module for received data."]
+pub type RX_PCM_BYPASS_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RX_STOP_MODE` reader - 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full."]
+pub type RX_STOP_MODE_R = crate::FieldReader;
+#[doc = "Field `RX_STOP_MODE` writer - 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full."]
+pub type RX_STOP_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `RX_LEFT_ALIGN` reader - 1: I2S RX left alignment mode. 0: I2S RX right alignment mode."]
+pub type RX_LEFT_ALIGN_R = crate::BitReader;
+#[doc = "Field `RX_LEFT_ALIGN` writer - 1: I2S RX left alignment mode. 0: I2S RX right alignment mode."]
+pub type RX_LEFT_ALIGN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RX_24_FILL_EN` reader - 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits."]
+pub type RX_24_FILL_EN_R = crate::BitReader;
+#[doc = "Field `RX_24_FILL_EN` writer - 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits."]
+pub type RX_24_FILL_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RX_WS_IDLE_POL` reader - 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel."]
+pub type RX_WS_IDLE_POL_R = crate::BitReader;
+#[doc = "Field `RX_WS_IDLE_POL` writer - 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel."]
+pub type RX_WS_IDLE_POL_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RX_BIT_ORDER` reader - I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first."]
+pub type RX_BIT_ORDER_R = crate::BitReader;
+#[doc = "Field `RX_BIT_ORDER` writer - I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first."]
+pub type RX_BIT_ORDER_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RX_TDM_EN` reader - 1: Enable I2S TDM Rx mode . 0: Disable."]
+pub type RX_TDM_EN_R = crate::BitReader;
+#[doc = "Field `RX_TDM_EN` writer - 1: Enable I2S TDM Rx mode . 0: Disable."]
+pub type RX_TDM_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RX_PDM_EN` reader - 1: Enable I2S PDM Rx mode . 0: Disable."]
+pub type RX_PDM_EN_R = crate::BitReader;
+#[doc = "Field `RX_PDM_EN` writer - 1: Enable I2S PDM Rx mode . 0: Disable."]
+pub type RX_PDM_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RX_PDM2PCM_EN` reader - 1: Enable PDM2PCM RX mode. 0: DIsable."]
+pub type RX_PDM2PCM_EN_R = crate::BitReader;
+#[doc = "Field `RX_PDM2PCM_EN` writer - 1: Enable PDM2PCM RX mode. 0: DIsable."]
+pub type RX_PDM2PCM_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RX_PDM_SINC_DSR_16_EN` reader - Configure the down sampling rate of PDM RX filter group1 module. 1: The down sampling rate is 128. 0: down sampling rate is 64."]
+pub type RX_PDM_SINC_DSR_16_EN_R = crate::BitReader;
+#[doc = "Field `RX_PDM_SINC_DSR_16_EN` writer - Configure the down sampling rate of PDM RX filter group1 module. 1: The down sampling rate is 128. 0: down sampling rate is 64."]
+pub type RX_PDM_SINC_DSR_16_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 2 - Set this bit to start receiving data"]
+    #[inline(always)]
+    pub fn rx_start(&self) -> RX_START_R {
+        RX_START_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Set this bit to enable slave receiver mode"]
+    #[inline(always)]
+    pub fn rx_slave_mod(&self) -> RX_SLAVE_MOD_R {
+        RX_SLAVE_MOD_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 5 - Set this bit to enable receiver in mono mode"]
+    #[inline(always)]
+    pub fn rx_mono(&self) -> RX_MONO_R {
+        RX_MONO_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 7 - I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value."]
+    #[inline(always)]
+    pub fn rx_big_endian(&self) -> RX_BIG_ENDIAN_R {
+        RX_BIG_ENDIAN_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done."]
+    #[inline(always)]
+    pub fn rx_update(&self) -> RX_UPDATE_R {
+        RX_UPDATE_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - 1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode."]
+    #[inline(always)]
+    pub fn rx_mono_fst_vld(&self) -> RX_MONO_FST_VLD_R {
+        RX_MONO_FST_VLD_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bits 10:11 - I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &"]
+    #[inline(always)]
+    pub fn rx_pcm_conf(&self) -> RX_PCM_CONF_R {
+        RX_PCM_CONF_R::new(((self.bits >> 10) & 3) as u8)
+    }
+    #[doc = "Bit 12 - Set this bit to bypass Compress/Decompress module for received data."]
+    #[inline(always)]
+    pub fn rx_pcm_bypass(&self) -> RX_PCM_BYPASS_R {
+        RX_PCM_BYPASS_R::new(((self.bits >> 12) & 1) != 0)
+    }
+    #[doc = "Bits 13:14 - 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full."]
+    #[inline(always)]
+    pub fn rx_stop_mode(&self) -> RX_STOP_MODE_R {
+        RX_STOP_MODE_R::new(((self.bits >> 13) & 3) as u8)
+    }
+    #[doc = "Bit 15 - 1: I2S RX left alignment mode. 0: I2S RX right alignment mode."]
+    #[inline(always)]
+    pub fn rx_left_align(&self) -> RX_LEFT_ALIGN_R {
+        RX_LEFT_ALIGN_R::new(((self.bits >> 15) & 1) != 0)
+    }
+    #[doc = "Bit 16 - 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits."]
+    #[inline(always)]
+    pub fn rx_24_fill_en(&self) -> RX_24_FILL_EN_R {
+        RX_24_FILL_EN_R::new(((self.bits >> 16) & 1) != 0)
+    }
+    #[doc = "Bit 17 - 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel."]
+    #[inline(always)]
+    pub fn rx_ws_idle_pol(&self) -> RX_WS_IDLE_POL_R {
+        RX_WS_IDLE_POL_R::new(((self.bits >> 17) & 1) != 0)
+    }
+    #[doc = "Bit 18 - I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first."]
+    #[inline(always)]
+    pub fn rx_bit_order(&self) -> RX_BIT_ORDER_R {
+        RX_BIT_ORDER_R::new(((self.bits >> 18) & 1) != 0)
+    }
+    #[doc = "Bit 19 - 1: Enable I2S TDM Rx mode . 0: Disable."]
+    #[inline(always)]
+    pub fn rx_tdm_en(&self) -> RX_TDM_EN_R {
+        RX_TDM_EN_R::new(((self.bits >> 19) & 1) != 0)
+    }
+    #[doc = "Bit 20 - 1: Enable I2S PDM Rx mode . 0: Disable."]
+    #[inline(always)]
+    pub fn rx_pdm_en(&self) -> RX_PDM_EN_R {
+        RX_PDM_EN_R::new(((self.bits >> 20) & 1) != 0)
+    }
+    #[doc = "Bit 21 - 1: Enable PDM2PCM RX mode. 0: DIsable."]
+    #[inline(always)]
+    pub fn rx_pdm2pcm_en(&self) -> RX_PDM2PCM_EN_R {
+        RX_PDM2PCM_EN_R::new(((self.bits >> 21) & 1) != 0)
+    }
+    #[doc = "Bit 22 - Configure the down sampling rate of PDM RX filter group1 module. 1: The down sampling rate is 128. 0: down sampling rate is 64."]
+    #[inline(always)]
+    pub fn rx_pdm_sinc_dsr_16_en(&self) -> RX_PDM_SINC_DSR_16_EN_R {
+        RX_PDM_SINC_DSR_16_EN_R::new(((self.bits >> 22) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("RX_CONF")
+            .field("rx_start", &self.rx_start())
+            .field("rx_slave_mod", &self.rx_slave_mod())
+            .field("rx_mono", &self.rx_mono())
+            .field("rx_big_endian", &self.rx_big_endian())
+            .field("rx_update", &self.rx_update())
+            .field("rx_mono_fst_vld", &self.rx_mono_fst_vld())
+            .field("rx_pcm_conf", &self.rx_pcm_conf())
+            .field("rx_pcm_bypass", &self.rx_pcm_bypass())
+            .field("rx_stop_mode", &self.rx_stop_mode())
+            .field("rx_left_align", &self.rx_left_align())
+            .field("rx_24_fill_en", &self.rx_24_fill_en())
+            .field("rx_ws_idle_pol", &self.rx_ws_idle_pol())
+            .field("rx_bit_order", &self.rx_bit_order())
+            .field("rx_tdm_en", &self.rx_tdm_en())
+            .field("rx_pdm_en", &self.rx_pdm_en())
+            .field("rx_pdm2pcm_en", &self.rx_pdm2pcm_en())
+            .field("rx_pdm_sinc_dsr_16_en", &self.rx_pdm_sinc_dsr_16_en())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Set this bit to reset receiver"]
+    #[inline(always)]
+    pub fn rx_reset(&mut self) -> RX_RESET_W<RX_CONF_SPEC> {
+        RX_RESET_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - Set this bit to reset Rx AFIFO"]
+    #[inline(always)]
+    pub fn rx_fifo_reset(&mut self) -> RX_FIFO_RESET_W<RX_CONF_SPEC> {
+        RX_FIFO_RESET_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - Set this bit to start receiving data"]
+    #[inline(always)]
+    pub fn rx_start(&mut self) -> RX_START_W<RX_CONF_SPEC> {
+        RX_START_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - Set this bit to enable slave receiver mode"]
+    #[inline(always)]
+    pub fn rx_slave_mod(&mut self) -> RX_SLAVE_MOD_W<RX_CONF_SPEC> {
+        RX_SLAVE_MOD_W::new(self, 3)
+    }
+    #[doc = "Bit 5 - Set this bit to enable receiver in mono mode"]
+    #[inline(always)]
+    pub fn rx_mono(&mut self) -> RX_MONO_W<RX_CONF_SPEC> {
+        RX_MONO_W::new(self, 5)
+    }
+    #[doc = "Bit 7 - I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value."]
+    #[inline(always)]
+    pub fn rx_big_endian(&mut self) -> RX_BIG_ENDIAN_W<RX_CONF_SPEC> {
+        RX_BIG_ENDIAN_W::new(self, 7)
+    }
+    #[doc = "Bit 8 - Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done."]
+    #[inline(always)]
+    pub fn rx_update(&mut self) -> RX_UPDATE_W<RX_CONF_SPEC> {
+        RX_UPDATE_W::new(self, 8)
+    }
+    #[doc = "Bit 9 - 1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode."]
+    #[inline(always)]
+    pub fn rx_mono_fst_vld(&mut self) -> RX_MONO_FST_VLD_W<RX_CONF_SPEC> {
+        RX_MONO_FST_VLD_W::new(self, 9)
+    }
+    #[doc = "Bits 10:11 - I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &"]
+    #[inline(always)]
+    pub fn rx_pcm_conf(&mut self) -> RX_PCM_CONF_W<RX_CONF_SPEC> {
+        RX_PCM_CONF_W::new(self, 10)
+    }
+    #[doc = "Bit 12 - Set this bit to bypass Compress/Decompress module for received data."]
+    #[inline(always)]
+    pub fn rx_pcm_bypass(&mut self) -> RX_PCM_BYPASS_W<RX_CONF_SPEC> {
+        RX_PCM_BYPASS_W::new(self, 12)
+    }
+    #[doc = "Bits 13:14 - 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full."]
+    #[inline(always)]
+    pub fn rx_stop_mode(&mut self) -> RX_STOP_MODE_W<RX_CONF_SPEC> {
+        RX_STOP_MODE_W::new(self, 13)
+    }
+    #[doc = "Bit 15 - 1: I2S RX left alignment mode. 0: I2S RX right alignment mode."]
+    #[inline(always)]
+    pub fn rx_left_align(&mut self) -> RX_LEFT_ALIGN_W<RX_CONF_SPEC> {
+        RX_LEFT_ALIGN_W::new(self, 15)
+    }
+    #[doc = "Bit 16 - 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits."]
+    #[inline(always)]
+    pub fn rx_24_fill_en(&mut self) -> RX_24_FILL_EN_W<RX_CONF_SPEC> {
+        RX_24_FILL_EN_W::new(self, 16)
+    }
+    #[doc = "Bit 17 - 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel."]
+    #[inline(always)]
+    pub fn rx_ws_idle_pol(&mut self) -> RX_WS_IDLE_POL_W<RX_CONF_SPEC> {
+        RX_WS_IDLE_POL_W::new(self, 17)
+    }
+    #[doc = "Bit 18 - I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first."]
+    #[inline(always)]
+    pub fn rx_bit_order(&mut self) -> RX_BIT_ORDER_W<RX_CONF_SPEC> {
+        RX_BIT_ORDER_W::new(self, 18)
+    }
+    #[doc = "Bit 19 - 1: Enable I2S TDM Rx mode . 0: Disable."]
+    #[inline(always)]
+    pub fn rx_tdm_en(&mut self) -> RX_TDM_EN_W<RX_CONF_SPEC> {
+        RX_TDM_EN_W::new(self, 19)
+    }
+    #[doc = "Bit 20 - 1: Enable I2S PDM Rx mode . 0: Disable."]
+    #[inline(always)]
+    pub fn rx_pdm_en(&mut self) -> RX_PDM_EN_W<RX_CONF_SPEC> {
+        RX_PDM_EN_W::new(self, 20)
+    }
+    #[doc = "Bit 21 - 1: Enable PDM2PCM RX mode. 0: DIsable."]
+    #[inline(always)]
+    pub fn rx_pdm2pcm_en(&mut self) -> RX_PDM2PCM_EN_W<RX_CONF_SPEC> {
+        RX_PDM2PCM_EN_W::new(self, 21)
+    }
+    #[doc = "Bit 22 - Configure the down sampling rate of PDM RX filter group1 module. 1: The down sampling rate is 128. 0: down sampling rate is 64."]
+    #[inline(always)]
+    pub fn rx_pdm_sinc_dsr_16_en(&mut self) -> RX_PDM_SINC_DSR_16_EN_W<RX_CONF_SPEC> {
+        RX_PDM_SINC_DSR_16_EN_W::new(self, 22)
+    }
+}
+#[doc = "I2S RX configure register\n\nYou can [`read`](crate::Reg::read) this register and get [`rx_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct RX_CONF_SPEC;
+impl crate::RegisterSpec for RX_CONF_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`rx_conf::R`](R) reader structure"]
+impl crate::Readable for RX_CONF_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`rx_conf::W`](W) writer structure"]
+impl crate::Writable for RX_CONF_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets RX_CONF to value 0x9600"]
+impl crate::Resettable for RX_CONF_SPEC {
+    const RESET_VALUE: u32 = 0x9600;
+}

vendor/esp32s3/src/i2s0/rx_conf1.rs

@@ -0,0 +1,122 @@
+#[doc = "Register `RX_CONF1` reader"]
+pub type R = crate::R<RX_CONF1_SPEC>;
+#[doc = "Register `RX_CONF1` writer"]
+pub type W = crate::W<RX_CONF1_SPEC>;
+#[doc = "Field `RX_TDM_WS_WIDTH` reader - The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH\\[6:0\\] +1) * T_bck"]
+pub type RX_TDM_WS_WIDTH_R = crate::FieldReader;
+#[doc = "Field `RX_TDM_WS_WIDTH` writer - The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH\\[6:0\\] +1) * T_bck"]
+pub type RX_TDM_WS_WIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
+#[doc = "Field `RX_BCK_DIV_NUM` reader - Bit clock configuration bits in receiver mode."]
+pub type RX_BCK_DIV_NUM_R = crate::FieldReader;
+#[doc = "Field `RX_BCK_DIV_NUM` writer - Bit clock configuration bits in receiver mode."]
+pub type RX_BCK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
+#[doc = "Field `RX_BITS_MOD` reader - Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode."]
+pub type RX_BITS_MOD_R = crate::FieldReader;
+#[doc = "Field `RX_BITS_MOD` writer - Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode."]
+pub type RX_BITS_MOD_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
+#[doc = "Field `RX_HALF_SAMPLE_BITS` reader - I2S Rx half sample bits -1."]
+pub type RX_HALF_SAMPLE_BITS_R = crate::FieldReader;
+#[doc = "Field `RX_HALF_SAMPLE_BITS` writer - I2S Rx half sample bits -1."]
+pub type RX_HALF_SAMPLE_BITS_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
+#[doc = "Field `RX_TDM_CHAN_BITS` reader - The Rx bit number for each channel minus 1in TDM mode."]
+pub type RX_TDM_CHAN_BITS_R = crate::FieldReader;
+#[doc = "Field `RX_TDM_CHAN_BITS` writer - The Rx bit number for each channel minus 1in TDM mode."]
+pub type RX_TDM_CHAN_BITS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
+#[doc = "Field `RX_MSB_SHIFT` reader - Set this bit to enable receiver in Phillips standard mode"]
+pub type RX_MSB_SHIFT_R = crate::BitReader;
+#[doc = "Field `RX_MSB_SHIFT` writer - Set this bit to enable receiver in Phillips standard mode"]
+pub type RX_MSB_SHIFT_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 0:6 - The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH\\[6:0\\] +1) * T_bck"]
+    #[inline(always)]
+    pub fn rx_tdm_ws_width(&self) -> RX_TDM_WS_WIDTH_R {
+        RX_TDM_WS_WIDTH_R::new((self.bits & 0x7f) as u8)
+    }
+    #[doc = "Bits 7:12 - Bit clock configuration bits in receiver mode."]
+    #[inline(always)]
+    pub fn rx_bck_div_num(&self) -> RX_BCK_DIV_NUM_R {
+        RX_BCK_DIV_NUM_R::new(((self.bits >> 7) & 0x3f) as u8)
+    }
+    #[doc = "Bits 13:17 - Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode."]
+    #[inline(always)]
+    pub fn rx_bits_mod(&self) -> RX_BITS_MOD_R {
+        RX_BITS_MOD_R::new(((self.bits >> 13) & 0x1f) as u8)
+    }
+    #[doc = "Bits 18:23 - I2S Rx half sample bits -1."]
+    #[inline(always)]
+    pub fn rx_half_sample_bits(&self) -> RX_HALF_SAMPLE_BITS_R {
+        RX_HALF_SAMPLE_BITS_R::new(((self.bits >> 18) & 0x3f) as u8)
+    }
+    #[doc = "Bits 24:28 - The Rx bit number for each channel minus 1in TDM mode."]
+    #[inline(always)]
+    pub fn rx_tdm_chan_bits(&self) -> RX_TDM_CHAN_BITS_R {
+        RX_TDM_CHAN_BITS_R::new(((self.bits >> 24) & 0x1f) as u8)
+    }
+    #[doc = "Bit 29 - Set this bit to enable receiver in Phillips standard mode"]
+    #[inline(always)]
+    pub fn rx_msb_shift(&self) -> RX_MSB_SHIFT_R {
+        RX_MSB_SHIFT_R::new(((self.bits >> 29) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("RX_CONF1")
+            .field("rx_tdm_ws_width", &self.rx_tdm_ws_width())
+            .field("rx_bck_div_num", &self.rx_bck_div_num())
+            .field("rx_bits_mod", &self.rx_bits_mod())
+            .field("rx_half_sample_bits", &self.rx_half_sample_bits())
+            .field("rx_tdm_chan_bits", &self.rx_tdm_chan_bits())
+            .field("rx_msb_shift", &self.rx_msb_shift())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:6 - The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH\\[6:0\\] +1) * T_bck"]
+    #[inline(always)]
+    pub fn rx_tdm_ws_width(&mut self) -> RX_TDM_WS_WIDTH_W<RX_CONF1_SPEC> {
+        RX_TDM_WS_WIDTH_W::new(self, 0)
+    }
+    #[doc = "Bits 7:12 - Bit clock configuration bits in receiver mode."]
+    #[inline(always)]
+    pub fn rx_bck_div_num(&mut self) -> RX_BCK_DIV_NUM_W<RX_CONF1_SPEC> {
+        RX_BCK_DIV_NUM_W::new(self, 7)
+    }
+    #[doc = "Bits 13:17 - Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode."]
+    #[inline(always)]
+    pub fn rx_bits_mod(&mut self) -> RX_BITS_MOD_W<RX_CONF1_SPEC> {
+        RX_BITS_MOD_W::new(self, 13)
+    }
+    #[doc = "Bits 18:23 - I2S Rx half sample bits -1."]
+    #[inline(always)]
+    pub fn rx_half_sample_bits(&mut self) -> RX_HALF_SAMPLE_BITS_W<RX_CONF1_SPEC> {
+        RX_HALF_SAMPLE_BITS_W::new(self, 18)
+    }
+    #[doc = "Bits 24:28 - The Rx bit number for each channel minus 1in TDM mode."]
+    #[inline(always)]
+    pub fn rx_tdm_chan_bits(&mut self) -> RX_TDM_CHAN_BITS_W<RX_CONF1_SPEC> {
+        RX_TDM_CHAN_BITS_W::new(self, 24)
+    }
+    #[doc = "Bit 29 - Set this bit to enable receiver in Phillips standard mode"]
+    #[inline(always)]
+    pub fn rx_msb_shift(&mut self) -> RX_MSB_SHIFT_W<RX_CONF1_SPEC> {
+        RX_MSB_SHIFT_W::new(self, 29)
+    }
+}
+#[doc = "I2S RX configure register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`rx_conf1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx_conf1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct RX_CONF1_SPEC;
+impl crate::RegisterSpec for RX_CONF1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`rx_conf1::R`](R) reader structure"]
+impl crate::Readable for RX_CONF1_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`rx_conf1::W`](W) writer structure"]
+impl crate::Writable for RX_CONF1_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets RX_CONF1 to value 0x2f3d_e300"]
+impl crate::Resettable for RX_CONF1_SPEC {
+    const RESET_VALUE: u32 = 0x2f3d_e300;
+}

vendor/esp32s3/src/i2s0/rx_tdm_ctrl.rs

@@ -0,0 +1,287 @@
+#[doc = "Register `RX_TDM_CTRL` reader"]
+pub type R = crate::R<RX_TDM_CTRL_SPEC>;
+#[doc = "Register `RX_TDM_CTRL` writer"]
+pub type W = crate::W<RX_TDM_CTRL_SPEC>;
+#[doc = "Field `RX_TDM_PDM_CHAN0_EN` reader - 1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just input 0 in this channel."]
+pub type RX_TDM_PDM_CHAN0_EN_R = crate::BitReader;
+#[doc = "Field `RX_TDM_PDM_CHAN0_EN` writer - 1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just input 0 in this channel."]
+pub type RX_TDM_PDM_CHAN0_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RX_TDM_PDM_CHAN1_EN` reader - 1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0: Disable, just input 0 in this channel."]
+pub type RX_TDM_PDM_CHAN1_EN_R = crate::BitReader;
+#[doc = "Field `RX_TDM_PDM_CHAN1_EN` writer - 1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0: Disable, just input 0 in this channel."]
+pub type RX_TDM_PDM_CHAN1_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RX_TDM_PDM_CHAN2_EN` reader - 1: Enable the valid data input of I2S RX TDM or PDM channel 2. 0: Disable, just input 0 in this channel."]
+pub type RX_TDM_PDM_CHAN2_EN_R = crate::BitReader;
+#[doc = "Field `RX_TDM_PDM_CHAN2_EN` writer - 1: Enable the valid data input of I2S RX TDM or PDM channel 2. 0: Disable, just input 0 in this channel."]
+pub type RX_TDM_PDM_CHAN2_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RX_TDM_PDM_CHAN3_EN` reader - 1: Enable the valid data input of I2S RX TDM or PDM channel 3. 0: Disable, just input 0 in this channel."]
+pub type RX_TDM_PDM_CHAN3_EN_R = crate::BitReader;
+#[doc = "Field `RX_TDM_PDM_CHAN3_EN` writer - 1: Enable the valid data input of I2S RX TDM or PDM channel 3. 0: Disable, just input 0 in this channel."]
+pub type RX_TDM_PDM_CHAN3_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RX_TDM_PDM_CHAN4_EN` reader - 1: Enable the valid data input of I2S RX TDM or PDM channel 4. 0: Disable, just input 0 in this channel."]
+pub type RX_TDM_PDM_CHAN4_EN_R = crate::BitReader;
+#[doc = "Field `RX_TDM_PDM_CHAN4_EN` writer - 1: Enable the valid data input of I2S RX TDM or PDM channel 4. 0: Disable, just input 0 in this channel."]
+pub type RX_TDM_PDM_CHAN4_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RX_TDM_PDM_CHAN5_EN` reader - 1: Enable the valid data input of I2S RX TDM or PDM channel 5. 0: Disable, just input 0 in this channel."]
+pub type RX_TDM_PDM_CHAN5_EN_R = crate::BitReader;
+#[doc = "Field `RX_TDM_PDM_CHAN5_EN` writer - 1: Enable the valid data input of I2S RX TDM or PDM channel 5. 0: Disable, just input 0 in this channel."]
+pub type RX_TDM_PDM_CHAN5_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RX_TDM_PDM_CHAN6_EN` reader - 1: Enable the valid data input of I2S RX TDM or PDM channel 6. 0: Disable, just input 0 in this channel."]
+pub type RX_TDM_PDM_CHAN6_EN_R = crate::BitReader;
+#[doc = "Field `RX_TDM_PDM_CHAN6_EN` writer - 1: Enable the valid data input of I2S RX TDM or PDM channel 6. 0: Disable, just input 0 in this channel."]
+pub type RX_TDM_PDM_CHAN6_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RX_TDM_PDM_CHAN7_EN` reader - 1: Enable the valid data input of I2S RX TDM or PDM channel 7. 0: Disable, just input 0 in this channel."]
+pub type RX_TDM_PDM_CHAN7_EN_R = crate::BitReader;
+#[doc = "Field `RX_TDM_PDM_CHAN7_EN` writer - 1: Enable the valid data input of I2S RX TDM or PDM channel 7. 0: Disable, just input 0 in this channel."]
+pub type RX_TDM_PDM_CHAN7_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RX_TDM_CHAN8_EN` reader - 1: Enable the valid data input of I2S RX TDM channel 8. 0: Disable, just input 0 in this channel."]
+pub type RX_TDM_CHAN8_EN_R = crate::BitReader;
+#[doc = "Field `RX_TDM_CHAN8_EN` writer - 1: Enable the valid data input of I2S RX TDM channel 8. 0: Disable, just input 0 in this channel."]
+pub type RX_TDM_CHAN8_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RX_TDM_CHAN9_EN` reader - 1: Enable the valid data input of I2S RX TDM channel 9. 0: Disable, just input 0 in this channel."]
+pub type RX_TDM_CHAN9_EN_R = crate::BitReader;
+#[doc = "Field `RX_TDM_CHAN9_EN` writer - 1: Enable the valid data input of I2S RX TDM channel 9. 0: Disable, just input 0 in this channel."]
+pub type RX_TDM_CHAN9_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RX_TDM_CHAN10_EN` reader - 1: Enable the valid data input of I2S RX TDM channel 10. 0: Disable, just input 0 in this channel."]
+pub type RX_TDM_CHAN10_EN_R = crate::BitReader;
+#[doc = "Field `RX_TDM_CHAN10_EN` writer - 1: Enable the valid data input of I2S RX TDM channel 10. 0: Disable, just input 0 in this channel."]
+pub type RX_TDM_CHAN10_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RX_TDM_CHAN11_EN` reader - 1: Enable the valid data input of I2S RX TDM channel 11. 0: Disable, just input 0 in this channel."]
+pub type RX_TDM_CHAN11_EN_R = crate::BitReader;
+#[doc = "Field `RX_TDM_CHAN11_EN` writer - 1: Enable the valid data input of I2S RX TDM channel 11. 0: Disable, just input 0 in this channel."]
+pub type RX_TDM_CHAN11_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RX_TDM_CHAN12_EN` reader - 1: Enable the valid data input of I2S RX TDM channel 12. 0: Disable, just input 0 in this channel."]
+pub type RX_TDM_CHAN12_EN_R = crate::BitReader;
+#[doc = "Field `RX_TDM_CHAN12_EN` writer - 1: Enable the valid data input of I2S RX TDM channel 12. 0: Disable, just input 0 in this channel."]
+pub type RX_TDM_CHAN12_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RX_TDM_CHAN13_EN` reader - 1: Enable the valid data input of I2S RX TDM channel 13. 0: Disable, just input 0 in this channel."]
+pub type RX_TDM_CHAN13_EN_R = crate::BitReader;
+#[doc = "Field `RX_TDM_CHAN13_EN` writer - 1: Enable the valid data input of I2S RX TDM channel 13. 0: Disable, just input 0 in this channel."]
+pub type RX_TDM_CHAN13_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RX_TDM_CHAN14_EN` reader - 1: Enable the valid data input of I2S RX TDM channel 14. 0: Disable, just input 0 in this channel."]
+pub type RX_TDM_CHAN14_EN_R = crate::BitReader;
+#[doc = "Field `RX_TDM_CHAN14_EN` writer - 1: Enable the valid data input of I2S RX TDM channel 14. 0: Disable, just input 0 in this channel."]
+pub type RX_TDM_CHAN14_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RX_TDM_CHAN15_EN` reader - 1: Enable the valid data input of I2S RX TDM channel 15. 0: Disable, just input 0 in this channel."]
+pub type RX_TDM_CHAN15_EN_R = crate::BitReader;
+#[doc = "Field `RX_TDM_CHAN15_EN` writer - 1: Enable the valid data input of I2S RX TDM channel 15. 0: Disable, just input 0 in this channel."]
+pub type RX_TDM_CHAN15_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RX_TDM_TOT_CHAN_NUM` reader - The total channel number of I2S TX TDM mode."]
+pub type RX_TDM_TOT_CHAN_NUM_R = crate::FieldReader;
+#[doc = "Field `RX_TDM_TOT_CHAN_NUM` writer - The total channel number of I2S TX TDM mode."]
+pub type RX_TDM_TOT_CHAN_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+impl R {
+    #[doc = "Bit 0 - 1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just input 0 in this channel."]
+    #[inline(always)]
+    pub fn rx_tdm_pdm_chan0_en(&self) -> RX_TDM_PDM_CHAN0_EN_R {
+        RX_TDM_PDM_CHAN0_EN_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - 1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0: Disable, just input 0 in this channel."]
+    #[inline(always)]
+    pub fn rx_tdm_pdm_chan1_en(&self) -> RX_TDM_PDM_CHAN1_EN_R {
+        RX_TDM_PDM_CHAN1_EN_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - 1: Enable the valid data input of I2S RX TDM or PDM channel 2. 0: Disable, just input 0 in this channel."]
+    #[inline(always)]
+    pub fn rx_tdm_pdm_chan2_en(&self) -> RX_TDM_PDM_CHAN2_EN_R {
+        RX_TDM_PDM_CHAN2_EN_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - 1: Enable the valid data input of I2S RX TDM or PDM channel 3. 0: Disable, just input 0 in this channel."]
+    #[inline(always)]
+    pub fn rx_tdm_pdm_chan3_en(&self) -> RX_TDM_PDM_CHAN3_EN_R {
+        RX_TDM_PDM_CHAN3_EN_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - 1: Enable the valid data input of I2S RX TDM or PDM channel 4. 0: Disable, just input 0 in this channel."]
+    #[inline(always)]
+    pub fn rx_tdm_pdm_chan4_en(&self) -> RX_TDM_PDM_CHAN4_EN_R {
+        RX_TDM_PDM_CHAN4_EN_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - 1: Enable the valid data input of I2S RX TDM or PDM channel 5. 0: Disable, just input 0 in this channel."]
+    #[inline(always)]
+    pub fn rx_tdm_pdm_chan5_en(&self) -> RX_TDM_PDM_CHAN5_EN_R {
+        RX_TDM_PDM_CHAN5_EN_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - 1: Enable the valid data input of I2S RX TDM or PDM channel 6. 0: Disable, just input 0 in this channel."]
+    #[inline(always)]
+    pub fn rx_tdm_pdm_chan6_en(&self) -> RX_TDM_PDM_CHAN6_EN_R {
+        RX_TDM_PDM_CHAN6_EN_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - 1: Enable the valid data input of I2S RX TDM or PDM channel 7. 0: Disable, just input 0 in this channel."]
+    #[inline(always)]
+    pub fn rx_tdm_pdm_chan7_en(&self) -> RX_TDM_PDM_CHAN7_EN_R {
+        RX_TDM_PDM_CHAN7_EN_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - 1: Enable the valid data input of I2S RX TDM channel 8. 0: Disable, just input 0 in this channel."]
+    #[inline(always)]
+    pub fn rx_tdm_chan8_en(&self) -> RX_TDM_CHAN8_EN_R {
+        RX_TDM_CHAN8_EN_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - 1: Enable the valid data input of I2S RX TDM channel 9. 0: Disable, just input 0 in this channel."]
+    #[inline(always)]
+    pub fn rx_tdm_chan9_en(&self) -> RX_TDM_CHAN9_EN_R {
+        RX_TDM_CHAN9_EN_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 10 - 1: Enable the valid data input of I2S RX TDM channel 10. 0: Disable, just input 0 in this channel."]
+    #[inline(always)]
+    pub fn rx_tdm_chan10_en(&self) -> RX_TDM_CHAN10_EN_R {
+        RX_TDM_CHAN10_EN_R::new(((self.bits >> 10) & 1) != 0)
+    }
+    #[doc = "Bit 11 - 1: Enable the valid data input of I2S RX TDM channel 11. 0: Disable, just input 0 in this channel."]
+    #[inline(always)]
+    pub fn rx_tdm_chan11_en(&self) -> RX_TDM_CHAN11_EN_R {
+        RX_TDM_CHAN11_EN_R::new(((self.bits >> 11) & 1) != 0)
+    }
+    #[doc = "Bit 12 - 1: Enable the valid data input of I2S RX TDM channel 12. 0: Disable, just input 0 in this channel."]
+    #[inline(always)]
+    pub fn rx_tdm_chan12_en(&self) -> RX_TDM_CHAN12_EN_R {
+        RX_TDM_CHAN12_EN_R::new(((self.bits >> 12) & 1) != 0)
+    }
+    #[doc = "Bit 13 - 1: Enable the valid data input of I2S RX TDM channel 13. 0: Disable, just input 0 in this channel."]
+    #[inline(always)]
+    pub fn rx_tdm_chan13_en(&self) -> RX_TDM_CHAN13_EN_R {
+        RX_TDM_CHAN13_EN_R::new(((self.bits >> 13) & 1) != 0)
+    }
+    #[doc = "Bit 14 - 1: Enable the valid data input of I2S RX TDM channel 14. 0: Disable, just input 0 in this channel."]
+    #[inline(always)]
+    pub fn rx_tdm_chan14_en(&self) -> RX_TDM_CHAN14_EN_R {
+        RX_TDM_CHAN14_EN_R::new(((self.bits >> 14) & 1) != 0)
+    }
+    #[doc = "Bit 15 - 1: Enable the valid data input of I2S RX TDM channel 15. 0: Disable, just input 0 in this channel."]
+    #[inline(always)]
+    pub fn rx_tdm_chan15_en(&self) -> RX_TDM_CHAN15_EN_R {
+        RX_TDM_CHAN15_EN_R::new(((self.bits >> 15) & 1) != 0)
+    }
+    #[doc = "Bits 16:19 - The total channel number of I2S TX TDM mode."]
+    #[inline(always)]
+    pub fn rx_tdm_tot_chan_num(&self) -> RX_TDM_TOT_CHAN_NUM_R {
+        RX_TDM_TOT_CHAN_NUM_R::new(((self.bits >> 16) & 0x0f) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("RX_TDM_CTRL")
+            .field("rx_tdm_pdm_chan0_en", &self.rx_tdm_pdm_chan0_en())
+            .field("rx_tdm_pdm_chan1_en", &self.rx_tdm_pdm_chan1_en())
+            .field("rx_tdm_pdm_chan2_en", &self.rx_tdm_pdm_chan2_en())
+            .field("rx_tdm_pdm_chan3_en", &self.rx_tdm_pdm_chan3_en())
+            .field("rx_tdm_pdm_chan4_en", &self.rx_tdm_pdm_chan4_en())
+            .field("rx_tdm_pdm_chan5_en", &self.rx_tdm_pdm_chan5_en())
+            .field("rx_tdm_pdm_chan6_en", &self.rx_tdm_pdm_chan6_en())
+            .field("rx_tdm_pdm_chan7_en", &self.rx_tdm_pdm_chan7_en())
+            .field("rx_tdm_chan8_en", &self.rx_tdm_chan8_en())
+            .field("rx_tdm_chan9_en", &self.rx_tdm_chan9_en())
+            .field("rx_tdm_chan10_en", &self.rx_tdm_chan10_en())
+            .field("rx_tdm_chan11_en", &self.rx_tdm_chan11_en())
+            .field("rx_tdm_chan12_en", &self.rx_tdm_chan12_en())
+            .field("rx_tdm_chan13_en", &self.rx_tdm_chan13_en())
+            .field("rx_tdm_chan14_en", &self.rx_tdm_chan14_en())
+            .field("rx_tdm_chan15_en", &self.rx_tdm_chan15_en())
+            .field("rx_tdm_tot_chan_num", &self.rx_tdm_tot_chan_num())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - 1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just input 0 in this channel."]
+    #[inline(always)]
+    pub fn rx_tdm_pdm_chan0_en(&mut self) -> RX_TDM_PDM_CHAN0_EN_W<RX_TDM_CTRL_SPEC> {
+        RX_TDM_PDM_CHAN0_EN_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - 1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0: Disable, just input 0 in this channel."]
+    #[inline(always)]
+    pub fn rx_tdm_pdm_chan1_en(&mut self) -> RX_TDM_PDM_CHAN1_EN_W<RX_TDM_CTRL_SPEC> {
+        RX_TDM_PDM_CHAN1_EN_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - 1: Enable the valid data input of I2S RX TDM or PDM channel 2. 0: Disable, just input 0 in this channel."]
+    #[inline(always)]
+    pub fn rx_tdm_pdm_chan2_en(&mut self) -> RX_TDM_PDM_CHAN2_EN_W<RX_TDM_CTRL_SPEC> {
+        RX_TDM_PDM_CHAN2_EN_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - 1: Enable the valid data input of I2S RX TDM or PDM channel 3. 0: Disable, just input 0 in this channel."]
+    #[inline(always)]
+    pub fn rx_tdm_pdm_chan3_en(&mut self) -> RX_TDM_PDM_CHAN3_EN_W<RX_TDM_CTRL_SPEC> {
+        RX_TDM_PDM_CHAN3_EN_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - 1: Enable the valid data input of I2S RX TDM or PDM channel 4. 0: Disable, just input 0 in this channel."]
+    #[inline(always)]
+    pub fn rx_tdm_pdm_chan4_en(&mut self) -> RX_TDM_PDM_CHAN4_EN_W<RX_TDM_CTRL_SPEC> {
+        RX_TDM_PDM_CHAN4_EN_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - 1: Enable the valid data input of I2S RX TDM or PDM channel 5. 0: Disable, just input 0 in this channel."]
+    #[inline(always)]
+    pub fn rx_tdm_pdm_chan5_en(&mut self) -> RX_TDM_PDM_CHAN5_EN_W<RX_TDM_CTRL_SPEC> {
+        RX_TDM_PDM_CHAN5_EN_W::new(self, 5)
+    }
+    #[doc = "Bit 6 - 1: Enable the valid data input of I2S RX TDM or PDM channel 6. 0: Disable, just input 0 in this channel."]
+    #[inline(always)]
+    pub fn rx_tdm_pdm_chan6_en(&mut self) -> RX_TDM_PDM_CHAN6_EN_W<RX_TDM_CTRL_SPEC> {
+        RX_TDM_PDM_CHAN6_EN_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - 1: Enable the valid data input of I2S RX TDM or PDM channel 7. 0: Disable, just input 0 in this channel."]
+    #[inline(always)]
+    pub fn rx_tdm_pdm_chan7_en(&mut self) -> RX_TDM_PDM_CHAN7_EN_W<RX_TDM_CTRL_SPEC> {
+        RX_TDM_PDM_CHAN7_EN_W::new(self, 7)
+    }
+    #[doc = "Bit 8 - 1: Enable the valid data input of I2S RX TDM channel 8. 0: Disable, just input 0 in this channel."]
+    #[inline(always)]
+    pub fn rx_tdm_chan8_en(&mut self) -> RX_TDM_CHAN8_EN_W<RX_TDM_CTRL_SPEC> {
+        RX_TDM_CHAN8_EN_W::new(self, 8)
+    }
+    #[doc = "Bit 9 - 1: Enable the valid data input of I2S RX TDM channel 9. 0: Disable, just input 0 in this channel."]
+    #[inline(always)]
+    pub fn rx_tdm_chan9_en(&mut self) -> RX_TDM_CHAN9_EN_W<RX_TDM_CTRL_SPEC> {
+        RX_TDM_CHAN9_EN_W::new(self, 9)
+    }
+    #[doc = "Bit 10 - 1: Enable the valid data input of I2S RX TDM channel 10. 0: Disable, just input 0 in this channel."]
+    #[inline(always)]
+    pub fn rx_tdm_chan10_en(&mut self) -> RX_TDM_CHAN10_EN_W<RX_TDM_CTRL_SPEC> {
+        RX_TDM_CHAN10_EN_W::new(self, 10)
+    }
+    #[doc = "Bit 11 - 1: Enable the valid data input of I2S RX TDM channel 11. 0: Disable, just input 0 in this channel."]
+    #[inline(always)]
+    pub fn rx_tdm_chan11_en(&mut self) -> RX_TDM_CHAN11_EN_W<RX_TDM_CTRL_SPEC> {
+        RX_TDM_CHAN11_EN_W::new(self, 11)
+    }
+    #[doc = "Bit 12 - 1: Enable the valid data input of I2S RX TDM channel 12. 0: Disable, just input 0 in this channel."]
+    #[inline(always)]
+    pub fn rx_tdm_chan12_en(&mut self) -> RX_TDM_CHAN12_EN_W<RX_TDM_CTRL_SPEC> {
+        RX_TDM_CHAN12_EN_W::new(self, 12)
+    }
+    #[doc = "Bit 13 - 1: Enable the valid data input of I2S RX TDM channel 13. 0: Disable, just input 0 in this channel."]
+    #[inline(always)]
+    pub fn rx_tdm_chan13_en(&mut self) -> RX_TDM_CHAN13_EN_W<RX_TDM_CTRL_SPEC> {
+        RX_TDM_CHAN13_EN_W::new(self, 13)
+    }
+    #[doc = "Bit 14 - 1: Enable the valid data input of I2S RX TDM channel 14. 0: Disable, just input 0 in this channel."]
+    #[inline(always)]
+    pub fn rx_tdm_chan14_en(&mut self) -> RX_TDM_CHAN14_EN_W<RX_TDM_CTRL_SPEC> {
+        RX_TDM_CHAN14_EN_W::new(self, 14)
+    }
+    #[doc = "Bit 15 - 1: Enable the valid data input of I2S RX TDM channel 15. 0: Disable, just input 0 in this channel."]
+    #[inline(always)]
+    pub fn rx_tdm_chan15_en(&mut self) -> RX_TDM_CHAN15_EN_W<RX_TDM_CTRL_SPEC> {
+        RX_TDM_CHAN15_EN_W::new(self, 15)
+    }
+    #[doc = "Bits 16:19 - The total channel number of I2S TX TDM mode."]
+    #[inline(always)]
+    pub fn rx_tdm_tot_chan_num(&mut self) -> RX_TDM_TOT_CHAN_NUM_W<RX_TDM_CTRL_SPEC> {
+        RX_TDM_TOT_CHAN_NUM_W::new(self, 16)
+    }
+}
+#[doc = "I2S TX TDM mode control register\n\nYou can [`read`](crate::Reg::read) this register and get [`rx_tdm_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx_tdm_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct RX_TDM_CTRL_SPEC;
+impl crate::RegisterSpec for RX_TDM_CTRL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`rx_tdm_ctrl::R`](R) reader structure"]
+impl crate::Readable for RX_TDM_CTRL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`rx_tdm_ctrl::W`](W) writer structure"]
+impl crate::Writable for RX_TDM_CTRL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets RX_TDM_CTRL to value 0xffff"]
+impl crate::Resettable for RX_TDM_CTRL_SPEC {
+    const RESET_VALUE: u32 = 0xffff;
+}

vendor/esp32s3/src/i2s0/rx_timing.rs

@@ -0,0 +1,152 @@
+#[doc = "Register `RX_TIMING` reader"]
+pub type R = crate::R<RX_TIMING_SPEC>;
+#[doc = "Register `RX_TIMING` writer"]
+pub type W = crate::W<RX_TIMING_SPEC>;
+#[doc = "Field `RX_SD_IN_DM` reader - The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
+pub type RX_SD_IN_DM_R = crate::FieldReader;
+#[doc = "Field `RX_SD_IN_DM` writer - The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
+pub type RX_SD_IN_DM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `RX_SD1_IN_DM` reader - The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
+pub type RX_SD1_IN_DM_R = crate::FieldReader;
+#[doc = "Field `RX_SD1_IN_DM` writer - The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
+pub type RX_SD1_IN_DM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `RX_SD2_IN_DM` reader - The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
+pub type RX_SD2_IN_DM_R = crate::FieldReader;
+#[doc = "Field `RX_SD2_IN_DM` writer - The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
+pub type RX_SD2_IN_DM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `RX_SD3_IN_DM` reader - The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
+pub type RX_SD3_IN_DM_R = crate::FieldReader;
+#[doc = "Field `RX_SD3_IN_DM` writer - The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
+pub type RX_SD3_IN_DM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `RX_WS_OUT_DM` reader - The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
+pub type RX_WS_OUT_DM_R = crate::FieldReader;
+#[doc = "Field `RX_WS_OUT_DM` writer - The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
+pub type RX_WS_OUT_DM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `RX_BCK_OUT_DM` reader - The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
+pub type RX_BCK_OUT_DM_R = crate::FieldReader;
+#[doc = "Field `RX_BCK_OUT_DM` writer - The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
+pub type RX_BCK_OUT_DM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `RX_WS_IN_DM` reader - The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
+pub type RX_WS_IN_DM_R = crate::FieldReader;
+#[doc = "Field `RX_WS_IN_DM` writer - The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
+pub type RX_WS_IN_DM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `RX_BCK_IN_DM` reader - The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
+pub type RX_BCK_IN_DM_R = crate::FieldReader;
+#[doc = "Field `RX_BCK_IN_DM` writer - The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
+pub type RX_BCK_IN_DM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+impl R {
+    #[doc = "Bits 0:1 - The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
+    #[inline(always)]
+    pub fn rx_sd_in_dm(&self) -> RX_SD_IN_DM_R {
+        RX_SD_IN_DM_R::new((self.bits & 3) as u8)
+    }
+    #[doc = "Bits 4:5 - The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
+    #[inline(always)]
+    pub fn rx_sd1_in_dm(&self) -> RX_SD1_IN_DM_R {
+        RX_SD1_IN_DM_R::new(((self.bits >> 4) & 3) as u8)
+    }
+    #[doc = "Bits 8:9 - The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
+    #[inline(always)]
+    pub fn rx_sd2_in_dm(&self) -> RX_SD2_IN_DM_R {
+        RX_SD2_IN_DM_R::new(((self.bits >> 8) & 3) as u8)
+    }
+    #[doc = "Bits 12:13 - The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
+    #[inline(always)]
+    pub fn rx_sd3_in_dm(&self) -> RX_SD3_IN_DM_R {
+        RX_SD3_IN_DM_R::new(((self.bits >> 12) & 3) as u8)
+    }
+    #[doc = "Bits 16:17 - The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
+    #[inline(always)]
+    pub fn rx_ws_out_dm(&self) -> RX_WS_OUT_DM_R {
+        RX_WS_OUT_DM_R::new(((self.bits >> 16) & 3) as u8)
+    }
+    #[doc = "Bits 20:21 - The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
+    #[inline(always)]
+    pub fn rx_bck_out_dm(&self) -> RX_BCK_OUT_DM_R {
+        RX_BCK_OUT_DM_R::new(((self.bits >> 20) & 3) as u8)
+    }
+    #[doc = "Bits 24:25 - The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
+    #[inline(always)]
+    pub fn rx_ws_in_dm(&self) -> RX_WS_IN_DM_R {
+        RX_WS_IN_DM_R::new(((self.bits >> 24) & 3) as u8)
+    }
+    #[doc = "Bits 28:29 - The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
+    #[inline(always)]
+    pub fn rx_bck_in_dm(&self) -> RX_BCK_IN_DM_R {
+        RX_BCK_IN_DM_R::new(((self.bits >> 28) & 3) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("RX_TIMING")
+            .field("rx_sd_in_dm", &self.rx_sd_in_dm())
+            .field("rx_sd1_in_dm", &self.rx_sd1_in_dm())
+            .field("rx_sd2_in_dm", &self.rx_sd2_in_dm())
+            .field("rx_sd3_in_dm", &self.rx_sd3_in_dm())
+            .field("rx_ws_out_dm", &self.rx_ws_out_dm())
+            .field("rx_bck_out_dm", &self.rx_bck_out_dm())
+            .field("rx_ws_in_dm", &self.rx_ws_in_dm())
+            .field("rx_bck_in_dm", &self.rx_bck_in_dm())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:1 - The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
+    #[inline(always)]
+    pub fn rx_sd_in_dm(&mut self) -> RX_SD_IN_DM_W<RX_TIMING_SPEC> {
+        RX_SD_IN_DM_W::new(self, 0)
+    }
+    #[doc = "Bits 4:5 - The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
+    #[inline(always)]
+    pub fn rx_sd1_in_dm(&mut self) -> RX_SD1_IN_DM_W<RX_TIMING_SPEC> {
+        RX_SD1_IN_DM_W::new(self, 4)
+    }
+    #[doc = "Bits 8:9 - The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
+    #[inline(always)]
+    pub fn rx_sd2_in_dm(&mut self) -> RX_SD2_IN_DM_W<RX_TIMING_SPEC> {
+        RX_SD2_IN_DM_W::new(self, 8)
+    }
+    #[doc = "Bits 12:13 - The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
+    #[inline(always)]
+    pub fn rx_sd3_in_dm(&mut self) -> RX_SD3_IN_DM_W<RX_TIMING_SPEC> {
+        RX_SD3_IN_DM_W::new(self, 12)
+    }
+    #[doc = "Bits 16:17 - The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
+    #[inline(always)]
+    pub fn rx_ws_out_dm(&mut self) -> RX_WS_OUT_DM_W<RX_TIMING_SPEC> {
+        RX_WS_OUT_DM_W::new(self, 16)
+    }
+    #[doc = "Bits 20:21 - The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
+    #[inline(always)]
+    pub fn rx_bck_out_dm(&mut self) -> RX_BCK_OUT_DM_W<RX_TIMING_SPEC> {
+        RX_BCK_OUT_DM_W::new(self, 20)
+    }
+    #[doc = "Bits 24:25 - The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
+    #[inline(always)]
+    pub fn rx_ws_in_dm(&mut self) -> RX_WS_IN_DM_W<RX_TIMING_SPEC> {
+        RX_WS_IN_DM_W::new(self, 24)
+    }
+    #[doc = "Bits 28:29 - The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
+    #[inline(always)]
+    pub fn rx_bck_in_dm(&mut self) -> RX_BCK_IN_DM_W<RX_TIMING_SPEC> {
+        RX_BCK_IN_DM_W::new(self, 28)
+    }
+}
+#[doc = "I2S RX timing control register\n\nYou can [`read`](crate::Reg::read) this register and get [`rx_timing::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx_timing::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct RX_TIMING_SPEC;
+impl crate::RegisterSpec for RX_TIMING_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`rx_timing::R`](R) reader structure"]
+impl crate::Readable for RX_TIMING_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`rx_timing::W`](W) writer structure"]
+impl crate::Writable for RX_TIMING_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets RX_TIMING to value 0"]
+impl crate::Resettable for RX_TIMING_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/i2s0/rxeof_num.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `RXEOF_NUM` reader"]
+pub type R = crate::R<RXEOF_NUM_SPEC>;
+#[doc = "Register `RXEOF_NUM` writer"]
+pub type W = crate::W<RXEOF_NUM_SPEC>;
+#[doc = "Field `RX_EOF_NUM` reader - The receive data bit length is (I2S_RX_BITS_MOD\\[4:0\\] + 1) * (REG_RX_EOF_NUM\\[11:0\\] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel."]
+pub type RX_EOF_NUM_R = crate::FieldReader<u16>;
+#[doc = "Field `RX_EOF_NUM` writer - The receive data bit length is (I2S_RX_BITS_MOD\\[4:0\\] + 1) * (REG_RX_EOF_NUM\\[11:0\\] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel."]
+pub type RX_EOF_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
+impl R {
+    #[doc = "Bits 0:11 - The receive data bit length is (I2S_RX_BITS_MOD\\[4:0\\] + 1) * (REG_RX_EOF_NUM\\[11:0\\] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel."]
+    #[inline(always)]
+    pub fn rx_eof_num(&self) -> RX_EOF_NUM_R {
+        RX_EOF_NUM_R::new((self.bits & 0x0fff) as u16)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("RXEOF_NUM")
+            .field("rx_eof_num", &self.rx_eof_num())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:11 - The receive data bit length is (I2S_RX_BITS_MOD\\[4:0\\] + 1) * (REG_RX_EOF_NUM\\[11:0\\] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel."]
+    #[inline(always)]
+    pub fn rx_eof_num(&mut self) -> RX_EOF_NUM_W<RXEOF_NUM_SPEC> {
+        RX_EOF_NUM_W::new(self, 0)
+    }
+}
+#[doc = "I2S RX data number control register.\n\nYou can [`read`](crate::Reg::read) this register and get [`rxeof_num::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxeof_num::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct RXEOF_NUM_SPEC;
+impl crate::RegisterSpec for RXEOF_NUM_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`rxeof_num::R`](R) reader structure"]
+impl crate::Readable for RXEOF_NUM_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`rxeof_num::W`](W) writer structure"]
+impl crate::Writable for RXEOF_NUM_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets RXEOF_NUM to value 0x40"]
+impl crate::Resettable for RXEOF_NUM_SPEC {
+    const RESET_VALUE: u32 = 0x40;
+}

vendor/esp32s3/src/i2s0/state.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `STATE` reader"]
+pub type R = crate::R<STATE_SPEC>;
+#[doc = "Field `TX_IDLE` reader - 1: i2s_tx is idle state. 0: i2s_tx is working."]
+pub type TX_IDLE_R = crate::BitReader;
+impl R {
+    #[doc = "Bit 0 - 1: i2s_tx is idle state. 0: i2s_tx is working."]
+    #[inline(always)]
+    pub fn tx_idle(&self) -> TX_IDLE_R {
+        TX_IDLE_R::new((self.bits & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("STATE")
+            .field("tx_idle", &self.tx_idle())
+            .finish()
+    }
+}
+#[doc = "I2S TX status register\n\nYou can [`read`](crate::Reg::read) this register and get [`state::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct STATE_SPEC;
+impl crate::RegisterSpec for STATE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`state::R`](R) reader structure"]
+impl crate::Readable for STATE_SPEC {}
+#[doc = "`reset()` method sets STATE to value 0x01"]
+impl crate::Resettable for STATE_SPEC {
+    const RESET_VALUE: u32 = 0x01;
+}

vendor/esp32s3/src/i2s0/tx_clkm_conf.rs

@@ -0,0 +1,92 @@
+#[doc = "Register `TX_CLKM_CONF` reader"]
+pub type R = crate::R<TX_CLKM_CONF_SPEC>;
+#[doc = "Register `TX_CLKM_CONF` writer"]
+pub type W = crate::W<TX_CLKM_CONF_SPEC>;
+#[doc = "Field `TX_CLKM_DIV_NUM` reader - Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2, z * \\[x * n-div + (n+1)-div\\] + y * n-div. For b > a/2, z * \\[n-div + x * (n+1)-div\\] + y * (n+1)-div."]
+pub type TX_CLKM_DIV_NUM_R = crate::FieldReader;
+#[doc = "Field `TX_CLKM_DIV_NUM` writer - Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2, z * \\[x * n-div + (n+1)-div\\] + y * n-div. For b > a/2, z * \\[n-div + x * (n+1)-div\\] + y * (n+1)-div."]
+pub type TX_CLKM_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+#[doc = "Field `TX_CLK_ACTIVE` reader - I2S Tx module clock enable signal."]
+pub type TX_CLK_ACTIVE_R = crate::BitReader;
+#[doc = "Field `TX_CLK_ACTIVE` writer - I2S Tx module clock enable signal."]
+pub type TX_CLK_ACTIVE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TX_CLK_SEL` reader - Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in."]
+pub type TX_CLK_SEL_R = crate::FieldReader;
+#[doc = "Field `TX_CLK_SEL` writer - Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in."]
+pub type TX_CLK_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `CLK_EN` reader - Set this bit to enable clk gate"]
+pub type CLK_EN_R = crate::BitReader;
+#[doc = "Field `CLK_EN` writer - Set this bit to enable clk gate"]
+pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 0:7 - Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2, z * \\[x * n-div + (n+1)-div\\] + y * n-div. For b > a/2, z * \\[n-div + x * (n+1)-div\\] + y * (n+1)-div."]
+    #[inline(always)]
+    pub fn tx_clkm_div_num(&self) -> TX_CLKM_DIV_NUM_R {
+        TX_CLKM_DIV_NUM_R::new((self.bits & 0xff) as u8)
+    }
+    #[doc = "Bit 26 - I2S Tx module clock enable signal."]
+    #[inline(always)]
+    pub fn tx_clk_active(&self) -> TX_CLK_ACTIVE_R {
+        TX_CLK_ACTIVE_R::new(((self.bits >> 26) & 1) != 0)
+    }
+    #[doc = "Bits 27:28 - Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in."]
+    #[inline(always)]
+    pub fn tx_clk_sel(&self) -> TX_CLK_SEL_R {
+        TX_CLK_SEL_R::new(((self.bits >> 27) & 3) as u8)
+    }
+    #[doc = "Bit 29 - Set this bit to enable clk gate"]
+    #[inline(always)]
+    pub fn clk_en(&self) -> CLK_EN_R {
+        CLK_EN_R::new(((self.bits >> 29) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("TX_CLKM_CONF")
+            .field("tx_clkm_div_num", &self.tx_clkm_div_num())
+            .field("tx_clk_active", &self.tx_clk_active())
+            .field("tx_clk_sel", &self.tx_clk_sel())
+            .field("clk_en", &self.clk_en())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2, z * \\[x * n-div + (n+1)-div\\] + y * n-div. For b > a/2, z * \\[n-div + x * (n+1)-div\\] + y * (n+1)-div."]
+    #[inline(always)]
+    pub fn tx_clkm_div_num(&mut self) -> TX_CLKM_DIV_NUM_W<TX_CLKM_CONF_SPEC> {
+        TX_CLKM_DIV_NUM_W::new(self, 0)
+    }
+    #[doc = "Bit 26 - I2S Tx module clock enable signal."]
+    #[inline(always)]
+    pub fn tx_clk_active(&mut self) -> TX_CLK_ACTIVE_W<TX_CLKM_CONF_SPEC> {
+        TX_CLK_ACTIVE_W::new(self, 26)
+    }
+    #[doc = "Bits 27:28 - Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in."]
+    #[inline(always)]
+    pub fn tx_clk_sel(&mut self) -> TX_CLK_SEL_W<TX_CLKM_CONF_SPEC> {
+        TX_CLK_SEL_W::new(self, 27)
+    }
+    #[doc = "Bit 29 - Set this bit to enable clk gate"]
+    #[inline(always)]
+    pub fn clk_en(&mut self) -> CLK_EN_W<TX_CLKM_CONF_SPEC> {
+        CLK_EN_W::new(self, 29)
+    }
+}
+#[doc = "I2S TX clock configure register\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_clkm_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_clkm_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct TX_CLKM_CONF_SPEC;
+impl crate::RegisterSpec for TX_CLKM_CONF_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`tx_clkm_conf::R`](R) reader structure"]
+impl crate::Readable for TX_CLKM_CONF_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`tx_clkm_conf::W`](W) writer structure"]
+impl crate::Writable for TX_CLKM_CONF_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets TX_CLKM_CONF to value 0x02"]
+impl crate::Resettable for TX_CLKM_CONF_SPEC {
+    const RESET_VALUE: u32 = 0x02;
+}

vendor/esp32s3/src/i2s0/tx_clkm_div_conf.rs

@@ -0,0 +1,92 @@
+#[doc = "Register `TX_CLKM_DIV_CONF` reader"]
+pub type R = crate::R<TX_CLKM_DIV_CONF_SPEC>;
+#[doc = "Register `TX_CLKM_DIV_CONF` writer"]
+pub type W = crate::W<TX_CLKM_DIV_CONF_SPEC>;
+#[doc = "Field `TX_CLKM_DIV_Z` reader - For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b)."]
+pub type TX_CLKM_DIV_Z_R = crate::FieldReader<u16>;
+#[doc = "Field `TX_CLKM_DIV_Z` writer - For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b)."]
+pub type TX_CLKM_DIV_Z_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
+#[doc = "Field `TX_CLKM_DIV_Y` reader - For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b))."]
+pub type TX_CLKM_DIV_Y_R = crate::FieldReader<u16>;
+#[doc = "Field `TX_CLKM_DIV_Y` writer - For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b))."]
+pub type TX_CLKM_DIV_Y_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
+#[doc = "Field `TX_CLKM_DIV_X` reader - For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1."]
+pub type TX_CLKM_DIV_X_R = crate::FieldReader<u16>;
+#[doc = "Field `TX_CLKM_DIV_X` writer - For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1."]
+pub type TX_CLKM_DIV_X_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
+#[doc = "Field `TX_CLKM_DIV_YN1` reader - For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1."]
+pub type TX_CLKM_DIV_YN1_R = crate::BitReader;
+#[doc = "Field `TX_CLKM_DIV_YN1` writer - For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1."]
+pub type TX_CLKM_DIV_YN1_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 0:8 - For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b)."]
+    #[inline(always)]
+    pub fn tx_clkm_div_z(&self) -> TX_CLKM_DIV_Z_R {
+        TX_CLKM_DIV_Z_R::new((self.bits & 0x01ff) as u16)
+    }
+    #[doc = "Bits 9:17 - For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b))."]
+    #[inline(always)]
+    pub fn tx_clkm_div_y(&self) -> TX_CLKM_DIV_Y_R {
+        TX_CLKM_DIV_Y_R::new(((self.bits >> 9) & 0x01ff) as u16)
+    }
+    #[doc = "Bits 18:26 - For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1."]
+    #[inline(always)]
+    pub fn tx_clkm_div_x(&self) -> TX_CLKM_DIV_X_R {
+        TX_CLKM_DIV_X_R::new(((self.bits >> 18) & 0x01ff) as u16)
+    }
+    #[doc = "Bit 27 - For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1."]
+    #[inline(always)]
+    pub fn tx_clkm_div_yn1(&self) -> TX_CLKM_DIV_YN1_R {
+        TX_CLKM_DIV_YN1_R::new(((self.bits >> 27) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("TX_CLKM_DIV_CONF")
+            .field("tx_clkm_div_z", &self.tx_clkm_div_z())
+            .field("tx_clkm_div_y", &self.tx_clkm_div_y())
+            .field("tx_clkm_div_x", &self.tx_clkm_div_x())
+            .field("tx_clkm_div_yn1", &self.tx_clkm_div_yn1())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:8 - For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b)."]
+    #[inline(always)]
+    pub fn tx_clkm_div_z(&mut self) -> TX_CLKM_DIV_Z_W<TX_CLKM_DIV_CONF_SPEC> {
+        TX_CLKM_DIV_Z_W::new(self, 0)
+    }
+    #[doc = "Bits 9:17 - For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b))."]
+    #[inline(always)]
+    pub fn tx_clkm_div_y(&mut self) -> TX_CLKM_DIV_Y_W<TX_CLKM_DIV_CONF_SPEC> {
+        TX_CLKM_DIV_Y_W::new(self, 9)
+    }
+    #[doc = "Bits 18:26 - For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1."]
+    #[inline(always)]
+    pub fn tx_clkm_div_x(&mut self) -> TX_CLKM_DIV_X_W<TX_CLKM_DIV_CONF_SPEC> {
+        TX_CLKM_DIV_X_W::new(self, 18)
+    }
+    #[doc = "Bit 27 - For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1."]
+    #[inline(always)]
+    pub fn tx_clkm_div_yn1(&mut self) -> TX_CLKM_DIV_YN1_W<TX_CLKM_DIV_CONF_SPEC> {
+        TX_CLKM_DIV_YN1_W::new(self, 27)
+    }
+}
+#[doc = "I2S TX module clock divider configure register\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_clkm_div_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_clkm_div_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct TX_CLKM_DIV_CONF_SPEC;
+impl crate::RegisterSpec for TX_CLKM_DIV_CONF_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`tx_clkm_div_conf::R`](R) reader structure"]
+impl crate::Readable for TX_CLKM_DIV_CONF_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`tx_clkm_div_conf::W`](W) writer structure"]
+impl crate::Writable for TX_CLKM_DIV_CONF_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets TX_CLKM_DIV_CONF to value 0x0200"]
+impl crate::Resettable for TX_CLKM_DIV_CONF_SPEC {
+    const RESET_VALUE: u32 = 0x0200;
+}

vendor/esp32s3/src/i2s0/tx_conf.rs

@@ -0,0 +1,316 @@
+#[doc = "Register `TX_CONF` reader"]
+pub type R = crate::R<TX_CONF_SPEC>;
+#[doc = "Register `TX_CONF` writer"]
+pub type W = crate::W<TX_CONF_SPEC>;
+#[doc = "Field `TX_RESET` writer - Set this bit to reset transmitter"]
+pub type TX_RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TX_FIFO_RESET` writer - Set this bit to reset Tx AFIFO"]
+pub type TX_FIFO_RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TX_START` reader - Set this bit to start transmitting data"]
+pub type TX_START_R = crate::BitReader;
+#[doc = "Field `TX_START` writer - Set this bit to start transmitting data"]
+pub type TX_START_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TX_SLAVE_MOD` reader - Set this bit to enable slave transmitter mode"]
+pub type TX_SLAVE_MOD_R = crate::BitReader;
+#[doc = "Field `TX_SLAVE_MOD` writer - Set this bit to enable slave transmitter mode"]
+pub type TX_SLAVE_MOD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TX_MONO` reader - Set this bit to enable transmitter in mono mode"]
+pub type TX_MONO_R = crate::BitReader;
+#[doc = "Field `TX_MONO` writer - Set this bit to enable transmitter in mono mode"]
+pub type TX_MONO_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TX_CHAN_EQUAL` reader - 1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode."]
+pub type TX_CHAN_EQUAL_R = crate::BitReader;
+#[doc = "Field `TX_CHAN_EQUAL` writer - 1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode."]
+pub type TX_CHAN_EQUAL_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TX_BIG_ENDIAN` reader - I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr value."]
+pub type TX_BIG_ENDIAN_R = crate::BitReader;
+#[doc = "Field `TX_BIG_ENDIAN` writer - I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr value."]
+pub type TX_BIG_ENDIAN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TX_UPDATE` reader - Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done."]
+pub type TX_UPDATE_R = crate::BitReader;
+#[doc = "Field `TX_UPDATE` writer - Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done."]
+pub type TX_UPDATE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TX_MONO_FST_VLD` reader - 1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode."]
+pub type TX_MONO_FST_VLD_R = crate::BitReader;
+#[doc = "Field `TX_MONO_FST_VLD` writer - 1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode."]
+pub type TX_MONO_FST_VLD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TX_PCM_CONF` reader - I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &"]
+pub type TX_PCM_CONF_R = crate::FieldReader;
+#[doc = "Field `TX_PCM_CONF` writer - I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &"]
+pub type TX_PCM_CONF_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `TX_PCM_BYPASS` reader - Set this bit to bypass Compress/Decompress module for transmitted data."]
+pub type TX_PCM_BYPASS_R = crate::BitReader;
+#[doc = "Field `TX_PCM_BYPASS` writer - Set this bit to bypass Compress/Decompress module for transmitted data."]
+pub type TX_PCM_BYPASS_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TX_STOP_EN` reader - Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy"]
+pub type TX_STOP_EN_R = crate::BitReader;
+#[doc = "Field `TX_STOP_EN` writer - Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy"]
+pub type TX_STOP_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TX_LEFT_ALIGN` reader - 1: I2S TX left alignment mode. 0: I2S TX right alignment mode."]
+pub type TX_LEFT_ALIGN_R = crate::BitReader;
+#[doc = "Field `TX_LEFT_ALIGN` writer - 1: I2S TX left alignment mode. 0: I2S TX right alignment mode."]
+pub type TX_LEFT_ALIGN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TX_24_FILL_EN` reader - 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode"]
+pub type TX_24_FILL_EN_R = crate::BitReader;
+#[doc = "Field `TX_24_FILL_EN` writer - 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode"]
+pub type TX_24_FILL_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TX_WS_IDLE_POL` reader - 0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: WS should be 1 when sending left channel data, and WS is 0in right channel."]
+pub type TX_WS_IDLE_POL_R = crate::BitReader;
+#[doc = "Field `TX_WS_IDLE_POL` writer - 0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: WS should be 1 when sending left channel data, and WS is 0in right channel."]
+pub type TX_WS_IDLE_POL_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TX_BIT_ORDER` reader - I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first."]
+pub type TX_BIT_ORDER_R = crate::BitReader;
+#[doc = "Field `TX_BIT_ORDER` writer - I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first."]
+pub type TX_BIT_ORDER_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TX_TDM_EN` reader - 1: Enable I2S TDM Tx mode . 0: Disable."]
+pub type TX_TDM_EN_R = crate::BitReader;
+#[doc = "Field `TX_TDM_EN` writer - 1: Enable I2S TDM Tx mode . 0: Disable."]
+pub type TX_TDM_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TX_PDM_EN` reader - 1: Enable I2S PDM Tx mode . 0: Disable."]
+pub type TX_PDM_EN_R = crate::BitReader;
+#[doc = "Field `TX_PDM_EN` writer - 1: Enable I2S PDM Tx mode . 0: Disable."]
+pub type TX_PDM_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TX_CHAN_MOD` reader - I2S transmitter channel mode configuration bits."]
+pub type TX_CHAN_MOD_R = crate::FieldReader;
+#[doc = "Field `TX_CHAN_MOD` writer - I2S transmitter channel mode configuration bits."]
+pub type TX_CHAN_MOD_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `SIG_LOOPBACK` reader - Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals."]
+pub type SIG_LOOPBACK_R = crate::BitReader;
+#[doc = "Field `SIG_LOOPBACK` writer - Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals."]
+pub type SIG_LOOPBACK_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 2 - Set this bit to start transmitting data"]
+    #[inline(always)]
+    pub fn tx_start(&self) -> TX_START_R {
+        TX_START_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Set this bit to enable slave transmitter mode"]
+    #[inline(always)]
+    pub fn tx_slave_mod(&self) -> TX_SLAVE_MOD_R {
+        TX_SLAVE_MOD_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 5 - Set this bit to enable transmitter in mono mode"]
+    #[inline(always)]
+    pub fn tx_mono(&self) -> TX_MONO_R {
+        TX_MONO_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - 1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode."]
+    #[inline(always)]
+    pub fn tx_chan_equal(&self) -> TX_CHAN_EQUAL_R {
+        TX_CHAN_EQUAL_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr value."]
+    #[inline(always)]
+    pub fn tx_big_endian(&self) -> TX_BIG_ENDIAN_R {
+        TX_BIG_ENDIAN_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done."]
+    #[inline(always)]
+    pub fn tx_update(&self) -> TX_UPDATE_R {
+        TX_UPDATE_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - 1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode."]
+    #[inline(always)]
+    pub fn tx_mono_fst_vld(&self) -> TX_MONO_FST_VLD_R {
+        TX_MONO_FST_VLD_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bits 10:11 - I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &"]
+    #[inline(always)]
+    pub fn tx_pcm_conf(&self) -> TX_PCM_CONF_R {
+        TX_PCM_CONF_R::new(((self.bits >> 10) & 3) as u8)
+    }
+    #[doc = "Bit 12 - Set this bit to bypass Compress/Decompress module for transmitted data."]
+    #[inline(always)]
+    pub fn tx_pcm_bypass(&self) -> TX_PCM_BYPASS_R {
+        TX_PCM_BYPASS_R::new(((self.bits >> 12) & 1) != 0)
+    }
+    #[doc = "Bit 13 - Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy"]
+    #[inline(always)]
+    pub fn tx_stop_en(&self) -> TX_STOP_EN_R {
+        TX_STOP_EN_R::new(((self.bits >> 13) & 1) != 0)
+    }
+    #[doc = "Bit 15 - 1: I2S TX left alignment mode. 0: I2S TX right alignment mode."]
+    #[inline(always)]
+    pub fn tx_left_align(&self) -> TX_LEFT_ALIGN_R {
+        TX_LEFT_ALIGN_R::new(((self.bits >> 15) & 1) != 0)
+    }
+    #[doc = "Bit 16 - 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode"]
+    #[inline(always)]
+    pub fn tx_24_fill_en(&self) -> TX_24_FILL_EN_R {
+        TX_24_FILL_EN_R::new(((self.bits >> 16) & 1) != 0)
+    }
+    #[doc = "Bit 17 - 0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: WS should be 1 when sending left channel data, and WS is 0in right channel."]
+    #[inline(always)]
+    pub fn tx_ws_idle_pol(&self) -> TX_WS_IDLE_POL_R {
+        TX_WS_IDLE_POL_R::new(((self.bits >> 17) & 1) != 0)
+    }
+    #[doc = "Bit 18 - I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first."]
+    #[inline(always)]
+    pub fn tx_bit_order(&self) -> TX_BIT_ORDER_R {
+        TX_BIT_ORDER_R::new(((self.bits >> 18) & 1) != 0)
+    }
+    #[doc = "Bit 19 - 1: Enable I2S TDM Tx mode . 0: Disable."]
+    #[inline(always)]
+    pub fn tx_tdm_en(&self) -> TX_TDM_EN_R {
+        TX_TDM_EN_R::new(((self.bits >> 19) & 1) != 0)
+    }
+    #[doc = "Bit 20 - 1: Enable I2S PDM Tx mode . 0: Disable."]
+    #[inline(always)]
+    pub fn tx_pdm_en(&self) -> TX_PDM_EN_R {
+        TX_PDM_EN_R::new(((self.bits >> 20) & 1) != 0)
+    }
+    #[doc = "Bits 24:26 - I2S transmitter channel mode configuration bits."]
+    #[inline(always)]
+    pub fn tx_chan_mod(&self) -> TX_CHAN_MOD_R {
+        TX_CHAN_MOD_R::new(((self.bits >> 24) & 7) as u8)
+    }
+    #[doc = "Bit 27 - Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals."]
+    #[inline(always)]
+    pub fn sig_loopback(&self) -> SIG_LOOPBACK_R {
+        SIG_LOOPBACK_R::new(((self.bits >> 27) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("TX_CONF")
+            .field("tx_start", &self.tx_start())
+            .field("tx_slave_mod", &self.tx_slave_mod())
+            .field("tx_mono", &self.tx_mono())
+            .field("tx_chan_equal", &self.tx_chan_equal())
+            .field("tx_big_endian", &self.tx_big_endian())
+            .field("tx_update", &self.tx_update())
+            .field("tx_mono_fst_vld", &self.tx_mono_fst_vld())
+            .field("tx_pcm_conf", &self.tx_pcm_conf())
+            .field("tx_pcm_bypass", &self.tx_pcm_bypass())
+            .field("tx_stop_en", &self.tx_stop_en())
+            .field("tx_left_align", &self.tx_left_align())
+            .field("tx_24_fill_en", &self.tx_24_fill_en())
+            .field("tx_ws_idle_pol", &self.tx_ws_idle_pol())
+            .field("tx_bit_order", &self.tx_bit_order())
+            .field("tx_tdm_en", &self.tx_tdm_en())
+            .field("tx_pdm_en", &self.tx_pdm_en())
+            .field("tx_chan_mod", &self.tx_chan_mod())
+            .field("sig_loopback", &self.sig_loopback())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Set this bit to reset transmitter"]
+    #[inline(always)]
+    pub fn tx_reset(&mut self) -> TX_RESET_W<TX_CONF_SPEC> {
+        TX_RESET_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - Set this bit to reset Tx AFIFO"]
+    #[inline(always)]
+    pub fn tx_fifo_reset(&mut self) -> TX_FIFO_RESET_W<TX_CONF_SPEC> {
+        TX_FIFO_RESET_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - Set this bit to start transmitting data"]
+    #[inline(always)]
+    pub fn tx_start(&mut self) -> TX_START_W<TX_CONF_SPEC> {
+        TX_START_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - Set this bit to enable slave transmitter mode"]
+    #[inline(always)]
+    pub fn tx_slave_mod(&mut self) -> TX_SLAVE_MOD_W<TX_CONF_SPEC> {
+        TX_SLAVE_MOD_W::new(self, 3)
+    }
+    #[doc = "Bit 5 - Set this bit to enable transmitter in mono mode"]
+    #[inline(always)]
+    pub fn tx_mono(&mut self) -> TX_MONO_W<TX_CONF_SPEC> {
+        TX_MONO_W::new(self, 5)
+    }
+    #[doc = "Bit 6 - 1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode."]
+    #[inline(always)]
+    pub fn tx_chan_equal(&mut self) -> TX_CHAN_EQUAL_W<TX_CONF_SPEC> {
+        TX_CHAN_EQUAL_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr value."]
+    #[inline(always)]
+    pub fn tx_big_endian(&mut self) -> TX_BIG_ENDIAN_W<TX_CONF_SPEC> {
+        TX_BIG_ENDIAN_W::new(self, 7)
+    }
+    #[doc = "Bit 8 - Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done."]
+    #[inline(always)]
+    pub fn tx_update(&mut self) -> TX_UPDATE_W<TX_CONF_SPEC> {
+        TX_UPDATE_W::new(self, 8)
+    }
+    #[doc = "Bit 9 - 1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode."]
+    #[inline(always)]
+    pub fn tx_mono_fst_vld(&mut self) -> TX_MONO_FST_VLD_W<TX_CONF_SPEC> {
+        TX_MONO_FST_VLD_W::new(self, 9)
+    }
+    #[doc = "Bits 10:11 - I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &"]
+    #[inline(always)]
+    pub fn tx_pcm_conf(&mut self) -> TX_PCM_CONF_W<TX_CONF_SPEC> {
+        TX_PCM_CONF_W::new(self, 10)
+    }
+    #[doc = "Bit 12 - Set this bit to bypass Compress/Decompress module for transmitted data."]
+    #[inline(always)]
+    pub fn tx_pcm_bypass(&mut self) -> TX_PCM_BYPASS_W<TX_CONF_SPEC> {
+        TX_PCM_BYPASS_W::new(self, 12)
+    }
+    #[doc = "Bit 13 - Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy"]
+    #[inline(always)]
+    pub fn tx_stop_en(&mut self) -> TX_STOP_EN_W<TX_CONF_SPEC> {
+        TX_STOP_EN_W::new(self, 13)
+    }
+    #[doc = "Bit 15 - 1: I2S TX left alignment mode. 0: I2S TX right alignment mode."]
+    #[inline(always)]
+    pub fn tx_left_align(&mut self) -> TX_LEFT_ALIGN_W<TX_CONF_SPEC> {
+        TX_LEFT_ALIGN_W::new(self, 15)
+    }
+    #[doc = "Bit 16 - 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode"]
+    #[inline(always)]
+    pub fn tx_24_fill_en(&mut self) -> TX_24_FILL_EN_W<TX_CONF_SPEC> {
+        TX_24_FILL_EN_W::new(self, 16)
+    }
+    #[doc = "Bit 17 - 0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: WS should be 1 when sending left channel data, and WS is 0in right channel."]
+    #[inline(always)]
+    pub fn tx_ws_idle_pol(&mut self) -> TX_WS_IDLE_POL_W<TX_CONF_SPEC> {
+        TX_WS_IDLE_POL_W::new(self, 17)
+    }
+    #[doc = "Bit 18 - I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first."]
+    #[inline(always)]
+    pub fn tx_bit_order(&mut self) -> TX_BIT_ORDER_W<TX_CONF_SPEC> {
+        TX_BIT_ORDER_W::new(self, 18)
+    }
+    #[doc = "Bit 19 - 1: Enable I2S TDM Tx mode . 0: Disable."]
+    #[inline(always)]
+    pub fn tx_tdm_en(&mut self) -> TX_TDM_EN_W<TX_CONF_SPEC> {
+        TX_TDM_EN_W::new(self, 19)
+    }
+    #[doc = "Bit 20 - 1: Enable I2S PDM Tx mode . 0: Disable."]
+    #[inline(always)]
+    pub fn tx_pdm_en(&mut self) -> TX_PDM_EN_W<TX_CONF_SPEC> {
+        TX_PDM_EN_W::new(self, 20)
+    }
+    #[doc = "Bits 24:26 - I2S transmitter channel mode configuration bits."]
+    #[inline(always)]
+    pub fn tx_chan_mod(&mut self) -> TX_CHAN_MOD_W<TX_CONF_SPEC> {
+        TX_CHAN_MOD_W::new(self, 24)
+    }
+    #[doc = "Bit 27 - Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals."]
+    #[inline(always)]
+    pub fn sig_loopback(&mut self) -> SIG_LOOPBACK_W<TX_CONF_SPEC> {
+        SIG_LOOPBACK_W::new(self, 27)
+    }
+}
+#[doc = "I2S TX configure register\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct TX_CONF_SPEC;
+impl crate::RegisterSpec for TX_CONF_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`tx_conf::R`](R) reader structure"]
+impl crate::Readable for TX_CONF_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`tx_conf::W`](W) writer structure"]
+impl crate::Writable for TX_CONF_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets TX_CONF to value 0xb200"]
+impl crate::Resettable for TX_CONF_SPEC {
+    const RESET_VALUE: u32 = 0xb200;
+}

vendor/esp32s3/src/i2s0/tx_conf1.rs

@@ -0,0 +1,137 @@
+#[doc = "Register `TX_CONF1` reader"]
+pub type R = crate::R<TX_CONF1_SPEC>;
+#[doc = "Register `TX_CONF1` writer"]
+pub type W = crate::W<TX_CONF1_SPEC>;
+#[doc = "Field `TX_TDM_WS_WIDTH` reader - The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH\\[6:0\\] +1) * T_bck"]
+pub type TX_TDM_WS_WIDTH_R = crate::FieldReader;
+#[doc = "Field `TX_TDM_WS_WIDTH` writer - The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH\\[6:0\\] +1) * T_bck"]
+pub type TX_TDM_WS_WIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
+#[doc = "Field `TX_BCK_DIV_NUM` reader - Bit clock configuration bits in transmitter mode."]
+pub type TX_BCK_DIV_NUM_R = crate::FieldReader;
+#[doc = "Field `TX_BCK_DIV_NUM` writer - Bit clock configuration bits in transmitter mode."]
+pub type TX_BCK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
+#[doc = "Field `TX_BITS_MOD` reader - Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode."]
+pub type TX_BITS_MOD_R = crate::FieldReader;
+#[doc = "Field `TX_BITS_MOD` writer - Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode."]
+pub type TX_BITS_MOD_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
+#[doc = "Field `TX_HALF_SAMPLE_BITS` reader - I2S Tx half sample bits -1."]
+pub type TX_HALF_SAMPLE_BITS_R = crate::FieldReader;
+#[doc = "Field `TX_HALF_SAMPLE_BITS` writer - I2S Tx half sample bits -1."]
+pub type TX_HALF_SAMPLE_BITS_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
+#[doc = "Field `TX_TDM_CHAN_BITS` reader - The Tx bit number for each channel minus 1in TDM mode."]
+pub type TX_TDM_CHAN_BITS_R = crate::FieldReader;
+#[doc = "Field `TX_TDM_CHAN_BITS` writer - The Tx bit number for each channel minus 1in TDM mode."]
+pub type TX_TDM_CHAN_BITS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
+#[doc = "Field `TX_MSB_SHIFT` reader - Set this bit to enable transmitter in Phillips standard mode"]
+pub type TX_MSB_SHIFT_R = crate::BitReader;
+#[doc = "Field `TX_MSB_SHIFT` writer - Set this bit to enable transmitter in Phillips standard mode"]
+pub type TX_MSB_SHIFT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TX_BCK_NO_DLY` reader - 1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode."]
+pub type TX_BCK_NO_DLY_R = crate::BitReader;
+#[doc = "Field `TX_BCK_NO_DLY` writer - 1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode."]
+pub type TX_BCK_NO_DLY_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 0:6 - The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH\\[6:0\\] +1) * T_bck"]
+    #[inline(always)]
+    pub fn tx_tdm_ws_width(&self) -> TX_TDM_WS_WIDTH_R {
+        TX_TDM_WS_WIDTH_R::new((self.bits & 0x7f) as u8)
+    }
+    #[doc = "Bits 7:12 - Bit clock configuration bits in transmitter mode."]
+    #[inline(always)]
+    pub fn tx_bck_div_num(&self) -> TX_BCK_DIV_NUM_R {
+        TX_BCK_DIV_NUM_R::new(((self.bits >> 7) & 0x3f) as u8)
+    }
+    #[doc = "Bits 13:17 - Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode."]
+    #[inline(always)]
+    pub fn tx_bits_mod(&self) -> TX_BITS_MOD_R {
+        TX_BITS_MOD_R::new(((self.bits >> 13) & 0x1f) as u8)
+    }
+    #[doc = "Bits 18:23 - I2S Tx half sample bits -1."]
+    #[inline(always)]
+    pub fn tx_half_sample_bits(&self) -> TX_HALF_SAMPLE_BITS_R {
+        TX_HALF_SAMPLE_BITS_R::new(((self.bits >> 18) & 0x3f) as u8)
+    }
+    #[doc = "Bits 24:28 - The Tx bit number for each channel minus 1in TDM mode."]
+    #[inline(always)]
+    pub fn tx_tdm_chan_bits(&self) -> TX_TDM_CHAN_BITS_R {
+        TX_TDM_CHAN_BITS_R::new(((self.bits >> 24) & 0x1f) as u8)
+    }
+    #[doc = "Bit 29 - Set this bit to enable transmitter in Phillips standard mode"]
+    #[inline(always)]
+    pub fn tx_msb_shift(&self) -> TX_MSB_SHIFT_R {
+        TX_MSB_SHIFT_R::new(((self.bits >> 29) & 1) != 0)
+    }
+    #[doc = "Bit 30 - 1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode."]
+    #[inline(always)]
+    pub fn tx_bck_no_dly(&self) -> TX_BCK_NO_DLY_R {
+        TX_BCK_NO_DLY_R::new(((self.bits >> 30) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("TX_CONF1")
+            .field("tx_tdm_ws_width", &self.tx_tdm_ws_width())
+            .field("tx_bck_div_num", &self.tx_bck_div_num())
+            .field("tx_bits_mod", &self.tx_bits_mod())
+            .field("tx_half_sample_bits", &self.tx_half_sample_bits())
+            .field("tx_tdm_chan_bits", &self.tx_tdm_chan_bits())
+            .field("tx_msb_shift", &self.tx_msb_shift())
+            .field("tx_bck_no_dly", &self.tx_bck_no_dly())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:6 - The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH\\[6:0\\] +1) * T_bck"]
+    #[inline(always)]
+    pub fn tx_tdm_ws_width(&mut self) -> TX_TDM_WS_WIDTH_W<TX_CONF1_SPEC> {
+        TX_TDM_WS_WIDTH_W::new(self, 0)
+    }
+    #[doc = "Bits 7:12 - Bit clock configuration bits in transmitter mode."]
+    #[inline(always)]
+    pub fn tx_bck_div_num(&mut self) -> TX_BCK_DIV_NUM_W<TX_CONF1_SPEC> {
+        TX_BCK_DIV_NUM_W::new(self, 7)
+    }
+    #[doc = "Bits 13:17 - Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode."]
+    #[inline(always)]
+    pub fn tx_bits_mod(&mut self) -> TX_BITS_MOD_W<TX_CONF1_SPEC> {
+        TX_BITS_MOD_W::new(self, 13)
+    }
+    #[doc = "Bits 18:23 - I2S Tx half sample bits -1."]
+    #[inline(always)]
+    pub fn tx_half_sample_bits(&mut self) -> TX_HALF_SAMPLE_BITS_W<TX_CONF1_SPEC> {
+        TX_HALF_SAMPLE_BITS_W::new(self, 18)
+    }
+    #[doc = "Bits 24:28 - The Tx bit number for each channel minus 1in TDM mode."]
+    #[inline(always)]
+    pub fn tx_tdm_chan_bits(&mut self) -> TX_TDM_CHAN_BITS_W<TX_CONF1_SPEC> {
+        TX_TDM_CHAN_BITS_W::new(self, 24)
+    }
+    #[doc = "Bit 29 - Set this bit to enable transmitter in Phillips standard mode"]
+    #[inline(always)]
+    pub fn tx_msb_shift(&mut self) -> TX_MSB_SHIFT_W<TX_CONF1_SPEC> {
+        TX_MSB_SHIFT_W::new(self, 29)
+    }
+    #[doc = "Bit 30 - 1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode."]
+    #[inline(always)]
+    pub fn tx_bck_no_dly(&mut self) -> TX_BCK_NO_DLY_W<TX_CONF1_SPEC> {
+        TX_BCK_NO_DLY_W::new(self, 30)
+    }
+}
+#[doc = "I2S TX configure register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_conf1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_conf1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct TX_CONF1_SPEC;
+impl crate::RegisterSpec for TX_CONF1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`tx_conf1::R`](R) reader structure"]
+impl crate::Readable for TX_CONF1_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`tx_conf1::W`](W) writer structure"]
+impl crate::Writable for TX_CONF1_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets TX_CONF1 to value 0x6f3d_e300"]
+impl crate::Resettable for TX_CONF1_SPEC {
+    const RESET_VALUE: u32 = 0x6f3d_e300;
+}

vendor/esp32s3/src/i2s0/tx_pcm2pdm_conf.rs

@@ -0,0 +1,222 @@
+#[doc = "Register `TX_PCM2PDM_CONF` reader"]
+pub type R = crate::R<TX_PCM2PDM_CONF_SPEC>;
+#[doc = "Register `TX_PCM2PDM_CONF` writer"]
+pub type W = crate::W<TX_PCM2PDM_CONF_SPEC>;
+#[doc = "Field `TX_PDM_HP_BYPASS` reader - I2S TX PDM bypass hp filter or not. The option has been removed."]
+pub type TX_PDM_HP_BYPASS_R = crate::BitReader;
+#[doc = "Field `TX_PDM_HP_BYPASS` writer - I2S TX PDM bypass hp filter or not. The option has been removed."]
+pub type TX_PDM_HP_BYPASS_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TX_PDM_SINC_OSR2` reader - I2S TX PDM OSR2 value"]
+pub type TX_PDM_SINC_OSR2_R = crate::FieldReader;
+#[doc = "Field `TX_PDM_SINC_OSR2` writer - I2S TX PDM OSR2 value"]
+pub type TX_PDM_SINC_OSR2_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `TX_PDM_PRESCALE` reader - I2S TX PDM prescale for sigmadelta"]
+pub type TX_PDM_PRESCALE_R = crate::FieldReader;
+#[doc = "Field `TX_PDM_PRESCALE` writer - I2S TX PDM prescale for sigmadelta"]
+pub type TX_PDM_PRESCALE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+#[doc = "Field `TX_PDM_HP_IN_SHIFT` reader - I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4"]
+pub type TX_PDM_HP_IN_SHIFT_R = crate::FieldReader;
+#[doc = "Field `TX_PDM_HP_IN_SHIFT` writer - I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4"]
+pub type TX_PDM_HP_IN_SHIFT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `TX_PDM_LP_IN_SHIFT` reader - I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4"]
+pub type TX_PDM_LP_IN_SHIFT_R = crate::FieldReader;
+#[doc = "Field `TX_PDM_LP_IN_SHIFT` writer - I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4"]
+pub type TX_PDM_LP_IN_SHIFT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `TX_PDM_SINC_IN_SHIFT` reader - I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4"]
+pub type TX_PDM_SINC_IN_SHIFT_R = crate::FieldReader;
+#[doc = "Field `TX_PDM_SINC_IN_SHIFT` writer - I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4"]
+pub type TX_PDM_SINC_IN_SHIFT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `TX_PDM_SIGMADELTA_IN_SHIFT` reader - I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4"]
+pub type TX_PDM_SIGMADELTA_IN_SHIFT_R = crate::FieldReader;
+#[doc = "Field `TX_PDM_SIGMADELTA_IN_SHIFT` writer - I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4"]
+pub type TX_PDM_SIGMADELTA_IN_SHIFT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `TX_PDM_SIGMADELTA_DITHER2` reader - I2S TX PDM sigmadelta dither2 value"]
+pub type TX_PDM_SIGMADELTA_DITHER2_R = crate::BitReader;
+#[doc = "Field `TX_PDM_SIGMADELTA_DITHER2` writer - I2S TX PDM sigmadelta dither2 value"]
+pub type TX_PDM_SIGMADELTA_DITHER2_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TX_PDM_SIGMADELTA_DITHER` reader - I2S TX PDM sigmadelta dither value"]
+pub type TX_PDM_SIGMADELTA_DITHER_R = crate::BitReader;
+#[doc = "Field `TX_PDM_SIGMADELTA_DITHER` writer - I2S TX PDM sigmadelta dither value"]
+pub type TX_PDM_SIGMADELTA_DITHER_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TX_PDM_DAC_2OUT_EN` reader - I2S TX PDM dac mode enable"]
+pub type TX_PDM_DAC_2OUT_EN_R = crate::BitReader;
+#[doc = "Field `TX_PDM_DAC_2OUT_EN` writer - I2S TX PDM dac mode enable"]
+pub type TX_PDM_DAC_2OUT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TX_PDM_DAC_MODE_EN` reader - I2S TX PDM dac 2channel enable"]
+pub type TX_PDM_DAC_MODE_EN_R = crate::BitReader;
+#[doc = "Field `TX_PDM_DAC_MODE_EN` writer - I2S TX PDM dac 2channel enable"]
+pub type TX_PDM_DAC_MODE_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PCM2PDM_CONV_EN` reader - I2S TX PDM Converter enable"]
+pub type PCM2PDM_CONV_EN_R = crate::BitReader;
+#[doc = "Field `PCM2PDM_CONV_EN` writer - I2S TX PDM Converter enable"]
+pub type PCM2PDM_CONV_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - I2S TX PDM bypass hp filter or not. The option has been removed."]
+    #[inline(always)]
+    pub fn tx_pdm_hp_bypass(&self) -> TX_PDM_HP_BYPASS_R {
+        TX_PDM_HP_BYPASS_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bits 1:4 - I2S TX PDM OSR2 value"]
+    #[inline(always)]
+    pub fn tx_pdm_sinc_osr2(&self) -> TX_PDM_SINC_OSR2_R {
+        TX_PDM_SINC_OSR2_R::new(((self.bits >> 1) & 0x0f) as u8)
+    }
+    #[doc = "Bits 5:12 - I2S TX PDM prescale for sigmadelta"]
+    #[inline(always)]
+    pub fn tx_pdm_prescale(&self) -> TX_PDM_PRESCALE_R {
+        TX_PDM_PRESCALE_R::new(((self.bits >> 5) & 0xff) as u8)
+    }
+    #[doc = "Bits 13:14 - I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4"]
+    #[inline(always)]
+    pub fn tx_pdm_hp_in_shift(&self) -> TX_PDM_HP_IN_SHIFT_R {
+        TX_PDM_HP_IN_SHIFT_R::new(((self.bits >> 13) & 3) as u8)
+    }
+    #[doc = "Bits 15:16 - I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4"]
+    #[inline(always)]
+    pub fn tx_pdm_lp_in_shift(&self) -> TX_PDM_LP_IN_SHIFT_R {
+        TX_PDM_LP_IN_SHIFT_R::new(((self.bits >> 15) & 3) as u8)
+    }
+    #[doc = "Bits 17:18 - I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4"]
+    #[inline(always)]
+    pub fn tx_pdm_sinc_in_shift(&self) -> TX_PDM_SINC_IN_SHIFT_R {
+        TX_PDM_SINC_IN_SHIFT_R::new(((self.bits >> 17) & 3) as u8)
+    }
+    #[doc = "Bits 19:20 - I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4"]
+    #[inline(always)]
+    pub fn tx_pdm_sigmadelta_in_shift(&self) -> TX_PDM_SIGMADELTA_IN_SHIFT_R {
+        TX_PDM_SIGMADELTA_IN_SHIFT_R::new(((self.bits >> 19) & 3) as u8)
+    }
+    #[doc = "Bit 21 - I2S TX PDM sigmadelta dither2 value"]
+    #[inline(always)]
+    pub fn tx_pdm_sigmadelta_dither2(&self) -> TX_PDM_SIGMADELTA_DITHER2_R {
+        TX_PDM_SIGMADELTA_DITHER2_R::new(((self.bits >> 21) & 1) != 0)
+    }
+    #[doc = "Bit 22 - I2S TX PDM sigmadelta dither value"]
+    #[inline(always)]
+    pub fn tx_pdm_sigmadelta_dither(&self) -> TX_PDM_SIGMADELTA_DITHER_R {
+        TX_PDM_SIGMADELTA_DITHER_R::new(((self.bits >> 22) & 1) != 0)
+    }
+    #[doc = "Bit 23 - I2S TX PDM dac mode enable"]
+    #[inline(always)]
+    pub fn tx_pdm_dac_2out_en(&self) -> TX_PDM_DAC_2OUT_EN_R {
+        TX_PDM_DAC_2OUT_EN_R::new(((self.bits >> 23) & 1) != 0)
+    }
+    #[doc = "Bit 24 - I2S TX PDM dac 2channel enable"]
+    #[inline(always)]
+    pub fn tx_pdm_dac_mode_en(&self) -> TX_PDM_DAC_MODE_EN_R {
+        TX_PDM_DAC_MODE_EN_R::new(((self.bits >> 24) & 1) != 0)
+    }
+    #[doc = "Bit 25 - I2S TX PDM Converter enable"]
+    #[inline(always)]
+    pub fn pcm2pdm_conv_en(&self) -> PCM2PDM_CONV_EN_R {
+        PCM2PDM_CONV_EN_R::new(((self.bits >> 25) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("TX_PCM2PDM_CONF")
+            .field("tx_pdm_hp_bypass", &self.tx_pdm_hp_bypass())
+            .field("tx_pdm_sinc_osr2", &self.tx_pdm_sinc_osr2())
+            .field("tx_pdm_prescale", &self.tx_pdm_prescale())
+            .field("tx_pdm_hp_in_shift", &self.tx_pdm_hp_in_shift())
+            .field("tx_pdm_lp_in_shift", &self.tx_pdm_lp_in_shift())
+            .field("tx_pdm_sinc_in_shift", &self.tx_pdm_sinc_in_shift())
+            .field(
+                "tx_pdm_sigmadelta_in_shift",
+                &self.tx_pdm_sigmadelta_in_shift(),
+            )
+            .field(
+                "tx_pdm_sigmadelta_dither2",
+                &self.tx_pdm_sigmadelta_dither2(),
+            )
+            .field("tx_pdm_sigmadelta_dither", &self.tx_pdm_sigmadelta_dither())
+            .field("tx_pdm_dac_2out_en", &self.tx_pdm_dac_2out_en())
+            .field("tx_pdm_dac_mode_en", &self.tx_pdm_dac_mode_en())
+            .field("pcm2pdm_conv_en", &self.pcm2pdm_conv_en())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - I2S TX PDM bypass hp filter or not. The option has been removed."]
+    #[inline(always)]
+    pub fn tx_pdm_hp_bypass(&mut self) -> TX_PDM_HP_BYPASS_W<TX_PCM2PDM_CONF_SPEC> {
+        TX_PDM_HP_BYPASS_W::new(self, 0)
+    }
+    #[doc = "Bits 1:4 - I2S TX PDM OSR2 value"]
+    #[inline(always)]
+    pub fn tx_pdm_sinc_osr2(&mut self) -> TX_PDM_SINC_OSR2_W<TX_PCM2PDM_CONF_SPEC> {
+        TX_PDM_SINC_OSR2_W::new(self, 1)
+    }
+    #[doc = "Bits 5:12 - I2S TX PDM prescale for sigmadelta"]
+    #[inline(always)]
+    pub fn tx_pdm_prescale(&mut self) -> TX_PDM_PRESCALE_W<TX_PCM2PDM_CONF_SPEC> {
+        TX_PDM_PRESCALE_W::new(self, 5)
+    }
+    #[doc = "Bits 13:14 - I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4"]
+    #[inline(always)]
+    pub fn tx_pdm_hp_in_shift(&mut self) -> TX_PDM_HP_IN_SHIFT_W<TX_PCM2PDM_CONF_SPEC> {
+        TX_PDM_HP_IN_SHIFT_W::new(self, 13)
+    }
+    #[doc = "Bits 15:16 - I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4"]
+    #[inline(always)]
+    pub fn tx_pdm_lp_in_shift(&mut self) -> TX_PDM_LP_IN_SHIFT_W<TX_PCM2PDM_CONF_SPEC> {
+        TX_PDM_LP_IN_SHIFT_W::new(self, 15)
+    }
+    #[doc = "Bits 17:18 - I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4"]
+    #[inline(always)]
+    pub fn tx_pdm_sinc_in_shift(&mut self) -> TX_PDM_SINC_IN_SHIFT_W<TX_PCM2PDM_CONF_SPEC> {
+        TX_PDM_SINC_IN_SHIFT_W::new(self, 17)
+    }
+    #[doc = "Bits 19:20 - I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4"]
+    #[inline(always)]
+    pub fn tx_pdm_sigmadelta_in_shift(
+        &mut self,
+    ) -> TX_PDM_SIGMADELTA_IN_SHIFT_W<TX_PCM2PDM_CONF_SPEC> {
+        TX_PDM_SIGMADELTA_IN_SHIFT_W::new(self, 19)
+    }
+    #[doc = "Bit 21 - I2S TX PDM sigmadelta dither2 value"]
+    #[inline(always)]
+    pub fn tx_pdm_sigmadelta_dither2(
+        &mut self,
+    ) -> TX_PDM_SIGMADELTA_DITHER2_W<TX_PCM2PDM_CONF_SPEC> {
+        TX_PDM_SIGMADELTA_DITHER2_W::new(self, 21)
+    }
+    #[doc = "Bit 22 - I2S TX PDM sigmadelta dither value"]
+    #[inline(always)]
+    pub fn tx_pdm_sigmadelta_dither(&mut self) -> TX_PDM_SIGMADELTA_DITHER_W<TX_PCM2PDM_CONF_SPEC> {
+        TX_PDM_SIGMADELTA_DITHER_W::new(self, 22)
+    }
+    #[doc = "Bit 23 - I2S TX PDM dac mode enable"]
+    #[inline(always)]
+    pub fn tx_pdm_dac_2out_en(&mut self) -> TX_PDM_DAC_2OUT_EN_W<TX_PCM2PDM_CONF_SPEC> {
+        TX_PDM_DAC_2OUT_EN_W::new(self, 23)
+    }
+    #[doc = "Bit 24 - I2S TX PDM dac 2channel enable"]
+    #[inline(always)]
+    pub fn tx_pdm_dac_mode_en(&mut self) -> TX_PDM_DAC_MODE_EN_W<TX_PCM2PDM_CONF_SPEC> {
+        TX_PDM_DAC_MODE_EN_W::new(self, 24)
+    }
+    #[doc = "Bit 25 - I2S TX PDM Converter enable"]
+    #[inline(always)]
+    pub fn pcm2pdm_conv_en(&mut self) -> PCM2PDM_CONV_EN_W<TX_PCM2PDM_CONF_SPEC> {
+        PCM2PDM_CONV_EN_W::new(self, 25)
+    }
+}
+#[doc = "I2S TX PCM2PDM configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_pcm2pdm_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_pcm2pdm_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct TX_PCM2PDM_CONF_SPEC;
+impl crate::RegisterSpec for TX_PCM2PDM_CONF_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`tx_pcm2pdm_conf::R`](R) reader structure"]
+impl crate::Readable for TX_PCM2PDM_CONF_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`tx_pcm2pdm_conf::W`](W) writer structure"]
+impl crate::Writable for TX_PCM2PDM_CONF_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets TX_PCM2PDM_CONF to value 0x004a_a004"]
+impl crate::Resettable for TX_PCM2PDM_CONF_SPEC {
+    const RESET_VALUE: u32 = 0x004a_a004;
+}

vendor/esp32s3/src/i2s0/tx_pcm2pdm_conf1.rs

@@ -0,0 +1,92 @@
+#[doc = "Register `TX_PCM2PDM_CONF1` reader"]
+pub type R = crate::R<TX_PCM2PDM_CONF1_SPEC>;
+#[doc = "Register `TX_PCM2PDM_CONF1` writer"]
+pub type W = crate::W<TX_PCM2PDM_CONF1_SPEC>;
+#[doc = "Field `TX_PDM_FP` reader - I2S TX PDM Fp"]
+pub type TX_PDM_FP_R = crate::FieldReader<u16>;
+#[doc = "Field `TX_PDM_FP` writer - I2S TX PDM Fp"]
+pub type TX_PDM_FP_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
+#[doc = "Field `TX_PDM_FS` reader - I2S TX PDM Fs"]
+pub type TX_PDM_FS_R = crate::FieldReader<u16>;
+#[doc = "Field `TX_PDM_FS` writer - I2S TX PDM Fs"]
+pub type TX_PDM_FS_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
+#[doc = "Field `TX_IIR_HP_MULT12_5` reader - The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5\\[2:0\\])"]
+pub type TX_IIR_HP_MULT12_5_R = crate::FieldReader;
+#[doc = "Field `TX_IIR_HP_MULT12_5` writer - The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5\\[2:0\\])"]
+pub type TX_IIR_HP_MULT12_5_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `TX_IIR_HP_MULT12_0` reader - The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0\\[2:0\\])"]
+pub type TX_IIR_HP_MULT12_0_R = crate::FieldReader;
+#[doc = "Field `TX_IIR_HP_MULT12_0` writer - The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0\\[2:0\\])"]
+pub type TX_IIR_HP_MULT12_0_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+impl R {
+    #[doc = "Bits 0:9 - I2S TX PDM Fp"]
+    #[inline(always)]
+    pub fn tx_pdm_fp(&self) -> TX_PDM_FP_R {
+        TX_PDM_FP_R::new((self.bits & 0x03ff) as u16)
+    }
+    #[doc = "Bits 10:19 - I2S TX PDM Fs"]
+    #[inline(always)]
+    pub fn tx_pdm_fs(&self) -> TX_PDM_FS_R {
+        TX_PDM_FS_R::new(((self.bits >> 10) & 0x03ff) as u16)
+    }
+    #[doc = "Bits 20:22 - The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5\\[2:0\\])"]
+    #[inline(always)]
+    pub fn tx_iir_hp_mult12_5(&self) -> TX_IIR_HP_MULT12_5_R {
+        TX_IIR_HP_MULT12_5_R::new(((self.bits >> 20) & 7) as u8)
+    }
+    #[doc = "Bits 23:25 - The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0\\[2:0\\])"]
+    #[inline(always)]
+    pub fn tx_iir_hp_mult12_0(&self) -> TX_IIR_HP_MULT12_0_R {
+        TX_IIR_HP_MULT12_0_R::new(((self.bits >> 23) & 7) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("TX_PCM2PDM_CONF1")
+            .field("tx_pdm_fp", &self.tx_pdm_fp())
+            .field("tx_pdm_fs", &self.tx_pdm_fs())
+            .field("tx_iir_hp_mult12_5", &self.tx_iir_hp_mult12_5())
+            .field("tx_iir_hp_mult12_0", &self.tx_iir_hp_mult12_0())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:9 - I2S TX PDM Fp"]
+    #[inline(always)]
+    pub fn tx_pdm_fp(&mut self) -> TX_PDM_FP_W<TX_PCM2PDM_CONF1_SPEC> {
+        TX_PDM_FP_W::new(self, 0)
+    }
+    #[doc = "Bits 10:19 - I2S TX PDM Fs"]
+    #[inline(always)]
+    pub fn tx_pdm_fs(&mut self) -> TX_PDM_FS_W<TX_PCM2PDM_CONF1_SPEC> {
+        TX_PDM_FS_W::new(self, 10)
+    }
+    #[doc = "Bits 20:22 - The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5\\[2:0\\])"]
+    #[inline(always)]
+    pub fn tx_iir_hp_mult12_5(&mut self) -> TX_IIR_HP_MULT12_5_W<TX_PCM2PDM_CONF1_SPEC> {
+        TX_IIR_HP_MULT12_5_W::new(self, 20)
+    }
+    #[doc = "Bits 23:25 - The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0\\[2:0\\])"]
+    #[inline(always)]
+    pub fn tx_iir_hp_mult12_0(&mut self) -> TX_IIR_HP_MULT12_0_W<TX_PCM2PDM_CONF1_SPEC> {
+        TX_IIR_HP_MULT12_0_W::new(self, 23)
+    }
+}
+#[doc = "I2S TX PCM2PDM configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_pcm2pdm_conf1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_pcm2pdm_conf1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct TX_PCM2PDM_CONF1_SPEC;
+impl crate::RegisterSpec for TX_PCM2PDM_CONF1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`tx_pcm2pdm_conf1::R`](R) reader structure"]
+impl crate::Readable for TX_PCM2PDM_CONF1_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`tx_pcm2pdm_conf1::W`](W) writer structure"]
+impl crate::Writable for TX_PCM2PDM_CONF1_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets TX_PCM2PDM_CONF1 to value 0x03f7_83c0"]
+impl crate::Resettable for TX_PCM2PDM_CONF1_SPEC {
+    const RESET_VALUE: u32 = 0x03f7_83c0;
+}

vendor/esp32s3/src/i2s0/tx_tdm_ctrl.rs

@@ -0,0 +1,302 @@
+#[doc = "Register `TX_TDM_CTRL` reader"]
+pub type R = crate::R<TX_TDM_CTRL_SPEC>;
+#[doc = "Register `TX_TDM_CTRL` writer"]
+pub type W = crate::W<TX_TDM_CTRL_SPEC>;
+#[doc = "Field `TX_TDM_CHAN0_EN` reader - 1: Enable the valid data output of I2S TX TDM channel 0. 0: Disable, just output 0 in this channel."]
+pub type TX_TDM_CHAN0_EN_R = crate::BitReader;
+#[doc = "Field `TX_TDM_CHAN0_EN` writer - 1: Enable the valid data output of I2S TX TDM channel 0. 0: Disable, just output 0 in this channel."]
+pub type TX_TDM_CHAN0_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TX_TDM_CHAN1_EN` reader - 1: Enable the valid data output of I2S TX TDM channel 1. 0: Disable, just output 0 in this channel."]
+pub type TX_TDM_CHAN1_EN_R = crate::BitReader;
+#[doc = "Field `TX_TDM_CHAN1_EN` writer - 1: Enable the valid data output of I2S TX TDM channel 1. 0: Disable, just output 0 in this channel."]
+pub type TX_TDM_CHAN1_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TX_TDM_CHAN2_EN` reader - 1: Enable the valid data output of I2S TX TDM channel 2. 0: Disable, just output 0 in this channel."]
+pub type TX_TDM_CHAN2_EN_R = crate::BitReader;
+#[doc = "Field `TX_TDM_CHAN2_EN` writer - 1: Enable the valid data output of I2S TX TDM channel 2. 0: Disable, just output 0 in this channel."]
+pub type TX_TDM_CHAN2_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TX_TDM_CHAN3_EN` reader - 1: Enable the valid data output of I2S TX TDM channel 3. 0: Disable, just output 0 in this channel."]
+pub type TX_TDM_CHAN3_EN_R = crate::BitReader;
+#[doc = "Field `TX_TDM_CHAN3_EN` writer - 1: Enable the valid data output of I2S TX TDM channel 3. 0: Disable, just output 0 in this channel."]
+pub type TX_TDM_CHAN3_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TX_TDM_CHAN4_EN` reader - 1: Enable the valid data output of I2S TX TDM channel 4. 0: Disable, just output 0 in this channel."]
+pub type TX_TDM_CHAN4_EN_R = crate::BitReader;
+#[doc = "Field `TX_TDM_CHAN4_EN` writer - 1: Enable the valid data output of I2S TX TDM channel 4. 0: Disable, just output 0 in this channel."]
+pub type TX_TDM_CHAN4_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TX_TDM_CHAN5_EN` reader - 1: Enable the valid data output of I2S TX TDM channel 5. 0: Disable, just output 0 in this channel."]
+pub type TX_TDM_CHAN5_EN_R = crate::BitReader;
+#[doc = "Field `TX_TDM_CHAN5_EN` writer - 1: Enable the valid data output of I2S TX TDM channel 5. 0: Disable, just output 0 in this channel."]
+pub type TX_TDM_CHAN5_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TX_TDM_CHAN6_EN` reader - 1: Enable the valid data output of I2S TX TDM channel 6. 0: Disable, just output 0 in this channel."]
+pub type TX_TDM_CHAN6_EN_R = crate::BitReader;
+#[doc = "Field `TX_TDM_CHAN6_EN` writer - 1: Enable the valid data output of I2S TX TDM channel 6. 0: Disable, just output 0 in this channel."]
+pub type TX_TDM_CHAN6_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TX_TDM_CHAN7_EN` reader - 1: Enable the valid data output of I2S TX TDM channel 7. 0: Disable, just output 0 in this channel."]
+pub type TX_TDM_CHAN7_EN_R = crate::BitReader;
+#[doc = "Field `TX_TDM_CHAN7_EN` writer - 1: Enable the valid data output of I2S TX TDM channel 7. 0: Disable, just output 0 in this channel."]
+pub type TX_TDM_CHAN7_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TX_TDM_CHAN8_EN` reader - 1: Enable the valid data output of I2S TX TDM channel 8. 0: Disable, just output 0 in this channel."]
+pub type TX_TDM_CHAN8_EN_R = crate::BitReader;
+#[doc = "Field `TX_TDM_CHAN8_EN` writer - 1: Enable the valid data output of I2S TX TDM channel 8. 0: Disable, just output 0 in this channel."]
+pub type TX_TDM_CHAN8_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TX_TDM_CHAN9_EN` reader - 1: Enable the valid data output of I2S TX TDM channel 9. 0: Disable, just output 0 in this channel."]
+pub type TX_TDM_CHAN9_EN_R = crate::BitReader;
+#[doc = "Field `TX_TDM_CHAN9_EN` writer - 1: Enable the valid data output of I2S TX TDM channel 9. 0: Disable, just output 0 in this channel."]
+pub type TX_TDM_CHAN9_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TX_TDM_CHAN10_EN` reader - 1: Enable the valid data output of I2S TX TDM channel 10. 0: Disable, just output 0 in this channel."]
+pub type TX_TDM_CHAN10_EN_R = crate::BitReader;
+#[doc = "Field `TX_TDM_CHAN10_EN` writer - 1: Enable the valid data output of I2S TX TDM channel 10. 0: Disable, just output 0 in this channel."]
+pub type TX_TDM_CHAN10_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TX_TDM_CHAN11_EN` reader - 1: Enable the valid data output of I2S TX TDM channel 11. 0: Disable, just output 0 in this channel."]
+pub type TX_TDM_CHAN11_EN_R = crate::BitReader;
+#[doc = "Field `TX_TDM_CHAN11_EN` writer - 1: Enable the valid data output of I2S TX TDM channel 11. 0: Disable, just output 0 in this channel."]
+pub type TX_TDM_CHAN11_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TX_TDM_CHAN12_EN` reader - 1: Enable the valid data output of I2S TX TDM channel 12. 0: Disable, just output 0 in this channel."]
+pub type TX_TDM_CHAN12_EN_R = crate::BitReader;
+#[doc = "Field `TX_TDM_CHAN12_EN` writer - 1: Enable the valid data output of I2S TX TDM channel 12. 0: Disable, just output 0 in this channel."]
+pub type TX_TDM_CHAN12_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TX_TDM_CHAN13_EN` reader - 1: Enable the valid data output of I2S TX TDM channel 13. 0: Disable, just output 0 in this channel."]
+pub type TX_TDM_CHAN13_EN_R = crate::BitReader;
+#[doc = "Field `TX_TDM_CHAN13_EN` writer - 1: Enable the valid data output of I2S TX TDM channel 13. 0: Disable, just output 0 in this channel."]
+pub type TX_TDM_CHAN13_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TX_TDM_CHAN14_EN` reader - 1: Enable the valid data output of I2S TX TDM channel 14. 0: Disable, just output 0 in this channel."]
+pub type TX_TDM_CHAN14_EN_R = crate::BitReader;
+#[doc = "Field `TX_TDM_CHAN14_EN` writer - 1: Enable the valid data output of I2S TX TDM channel 14. 0: Disable, just output 0 in this channel."]
+pub type TX_TDM_CHAN14_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TX_TDM_CHAN15_EN` reader - 1: Enable the valid data output of I2S TX TDM channel 15. 0: Disable, just output 0 in this channel."]
+pub type TX_TDM_CHAN15_EN_R = crate::BitReader;
+#[doc = "Field `TX_TDM_CHAN15_EN` writer - 1: Enable the valid data output of I2S TX TDM channel 15. 0: Disable, just output 0 in this channel."]
+pub type TX_TDM_CHAN15_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TX_TDM_TOT_CHAN_NUM` reader - The total channel number of I2S TX TDM mode."]
+pub type TX_TDM_TOT_CHAN_NUM_R = crate::FieldReader;
+#[doc = "Field `TX_TDM_TOT_CHAN_NUM` writer - The total channel number of I2S TX TDM mode."]
+pub type TX_TDM_TOT_CHAN_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `TX_TDM_SKIP_MSK_EN` reader - When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, and only the data of the enabled channels is sent, then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels."]
+pub type TX_TDM_SKIP_MSK_EN_R = crate::BitReader;
+#[doc = "Field `TX_TDM_SKIP_MSK_EN` writer - When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, and only the data of the enabled channels is sent, then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels."]
+pub type TX_TDM_SKIP_MSK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - 1: Enable the valid data output of I2S TX TDM channel 0. 0: Disable, just output 0 in this channel."]
+    #[inline(always)]
+    pub fn tx_tdm_chan0_en(&self) -> TX_TDM_CHAN0_EN_R {
+        TX_TDM_CHAN0_EN_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - 1: Enable the valid data output of I2S TX TDM channel 1. 0: Disable, just output 0 in this channel."]
+    #[inline(always)]
+    pub fn tx_tdm_chan1_en(&self) -> TX_TDM_CHAN1_EN_R {
+        TX_TDM_CHAN1_EN_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - 1: Enable the valid data output of I2S TX TDM channel 2. 0: Disable, just output 0 in this channel."]
+    #[inline(always)]
+    pub fn tx_tdm_chan2_en(&self) -> TX_TDM_CHAN2_EN_R {
+        TX_TDM_CHAN2_EN_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - 1: Enable the valid data output of I2S TX TDM channel 3. 0: Disable, just output 0 in this channel."]
+    #[inline(always)]
+    pub fn tx_tdm_chan3_en(&self) -> TX_TDM_CHAN3_EN_R {
+        TX_TDM_CHAN3_EN_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - 1: Enable the valid data output of I2S TX TDM channel 4. 0: Disable, just output 0 in this channel."]
+    #[inline(always)]
+    pub fn tx_tdm_chan4_en(&self) -> TX_TDM_CHAN4_EN_R {
+        TX_TDM_CHAN4_EN_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - 1: Enable the valid data output of I2S TX TDM channel 5. 0: Disable, just output 0 in this channel."]
+    #[inline(always)]
+    pub fn tx_tdm_chan5_en(&self) -> TX_TDM_CHAN5_EN_R {
+        TX_TDM_CHAN5_EN_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - 1: Enable the valid data output of I2S TX TDM channel 6. 0: Disable, just output 0 in this channel."]
+    #[inline(always)]
+    pub fn tx_tdm_chan6_en(&self) -> TX_TDM_CHAN6_EN_R {
+        TX_TDM_CHAN6_EN_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - 1: Enable the valid data output of I2S TX TDM channel 7. 0: Disable, just output 0 in this channel."]
+    #[inline(always)]
+    pub fn tx_tdm_chan7_en(&self) -> TX_TDM_CHAN7_EN_R {
+        TX_TDM_CHAN7_EN_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - 1: Enable the valid data output of I2S TX TDM channel 8. 0: Disable, just output 0 in this channel."]
+    #[inline(always)]
+    pub fn tx_tdm_chan8_en(&self) -> TX_TDM_CHAN8_EN_R {
+        TX_TDM_CHAN8_EN_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - 1: Enable the valid data output of I2S TX TDM channel 9. 0: Disable, just output 0 in this channel."]
+    #[inline(always)]
+    pub fn tx_tdm_chan9_en(&self) -> TX_TDM_CHAN9_EN_R {
+        TX_TDM_CHAN9_EN_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 10 - 1: Enable the valid data output of I2S TX TDM channel 10. 0: Disable, just output 0 in this channel."]
+    #[inline(always)]
+    pub fn tx_tdm_chan10_en(&self) -> TX_TDM_CHAN10_EN_R {
+        TX_TDM_CHAN10_EN_R::new(((self.bits >> 10) & 1) != 0)
+    }
+    #[doc = "Bit 11 - 1: Enable the valid data output of I2S TX TDM channel 11. 0: Disable, just output 0 in this channel."]
+    #[inline(always)]
+    pub fn tx_tdm_chan11_en(&self) -> TX_TDM_CHAN11_EN_R {
+        TX_TDM_CHAN11_EN_R::new(((self.bits >> 11) & 1) != 0)
+    }
+    #[doc = "Bit 12 - 1: Enable the valid data output of I2S TX TDM channel 12. 0: Disable, just output 0 in this channel."]
+    #[inline(always)]
+    pub fn tx_tdm_chan12_en(&self) -> TX_TDM_CHAN12_EN_R {
+        TX_TDM_CHAN12_EN_R::new(((self.bits >> 12) & 1) != 0)
+    }
+    #[doc = "Bit 13 - 1: Enable the valid data output of I2S TX TDM channel 13. 0: Disable, just output 0 in this channel."]
+    #[inline(always)]
+    pub fn tx_tdm_chan13_en(&self) -> TX_TDM_CHAN13_EN_R {
+        TX_TDM_CHAN13_EN_R::new(((self.bits >> 13) & 1) != 0)
+    }
+    #[doc = "Bit 14 - 1: Enable the valid data output of I2S TX TDM channel 14. 0: Disable, just output 0 in this channel."]
+    #[inline(always)]
+    pub fn tx_tdm_chan14_en(&self) -> TX_TDM_CHAN14_EN_R {
+        TX_TDM_CHAN14_EN_R::new(((self.bits >> 14) & 1) != 0)
+    }
+    #[doc = "Bit 15 - 1: Enable the valid data output of I2S TX TDM channel 15. 0: Disable, just output 0 in this channel."]
+    #[inline(always)]
+    pub fn tx_tdm_chan15_en(&self) -> TX_TDM_CHAN15_EN_R {
+        TX_TDM_CHAN15_EN_R::new(((self.bits >> 15) & 1) != 0)
+    }
+    #[doc = "Bits 16:19 - The total channel number of I2S TX TDM mode."]
+    #[inline(always)]
+    pub fn tx_tdm_tot_chan_num(&self) -> TX_TDM_TOT_CHAN_NUM_R {
+        TX_TDM_TOT_CHAN_NUM_R::new(((self.bits >> 16) & 0x0f) as u8)
+    }
+    #[doc = "Bit 20 - When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, and only the data of the enabled channels is sent, then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels."]
+    #[inline(always)]
+    pub fn tx_tdm_skip_msk_en(&self) -> TX_TDM_SKIP_MSK_EN_R {
+        TX_TDM_SKIP_MSK_EN_R::new(((self.bits >> 20) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("TX_TDM_CTRL")
+            .field("tx_tdm_chan0_en", &self.tx_tdm_chan0_en())
+            .field("tx_tdm_chan1_en", &self.tx_tdm_chan1_en())
+            .field("tx_tdm_chan2_en", &self.tx_tdm_chan2_en())
+            .field("tx_tdm_chan3_en", &self.tx_tdm_chan3_en())
+            .field("tx_tdm_chan4_en", &self.tx_tdm_chan4_en())
+            .field("tx_tdm_chan5_en", &self.tx_tdm_chan5_en())
+            .field("tx_tdm_chan6_en", &self.tx_tdm_chan6_en())
+            .field("tx_tdm_chan7_en", &self.tx_tdm_chan7_en())
+            .field("tx_tdm_chan8_en", &self.tx_tdm_chan8_en())
+            .field("tx_tdm_chan9_en", &self.tx_tdm_chan9_en())
+            .field("tx_tdm_chan10_en", &self.tx_tdm_chan10_en())
+            .field("tx_tdm_chan11_en", &self.tx_tdm_chan11_en())
+            .field("tx_tdm_chan12_en", &self.tx_tdm_chan12_en())
+            .field("tx_tdm_chan13_en", &self.tx_tdm_chan13_en())
+            .field("tx_tdm_chan14_en", &self.tx_tdm_chan14_en())
+            .field("tx_tdm_chan15_en", &self.tx_tdm_chan15_en())
+            .field("tx_tdm_tot_chan_num", &self.tx_tdm_tot_chan_num())
+            .field("tx_tdm_skip_msk_en", &self.tx_tdm_skip_msk_en())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - 1: Enable the valid data output of I2S TX TDM channel 0. 0: Disable, just output 0 in this channel."]
+    #[inline(always)]
+    pub fn tx_tdm_chan0_en(&mut self) -> TX_TDM_CHAN0_EN_W<TX_TDM_CTRL_SPEC> {
+        TX_TDM_CHAN0_EN_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - 1: Enable the valid data output of I2S TX TDM channel 1. 0: Disable, just output 0 in this channel."]
+    #[inline(always)]
+    pub fn tx_tdm_chan1_en(&mut self) -> TX_TDM_CHAN1_EN_W<TX_TDM_CTRL_SPEC> {
+        TX_TDM_CHAN1_EN_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - 1: Enable the valid data output of I2S TX TDM channel 2. 0: Disable, just output 0 in this channel."]
+    #[inline(always)]
+    pub fn tx_tdm_chan2_en(&mut self) -> TX_TDM_CHAN2_EN_W<TX_TDM_CTRL_SPEC> {
+        TX_TDM_CHAN2_EN_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - 1: Enable the valid data output of I2S TX TDM channel 3. 0: Disable, just output 0 in this channel."]
+    #[inline(always)]
+    pub fn tx_tdm_chan3_en(&mut self) -> TX_TDM_CHAN3_EN_W<TX_TDM_CTRL_SPEC> {
+        TX_TDM_CHAN3_EN_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - 1: Enable the valid data output of I2S TX TDM channel 4. 0: Disable, just output 0 in this channel."]
+    #[inline(always)]
+    pub fn tx_tdm_chan4_en(&mut self) -> TX_TDM_CHAN4_EN_W<TX_TDM_CTRL_SPEC> {
+        TX_TDM_CHAN4_EN_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - 1: Enable the valid data output of I2S TX TDM channel 5. 0: Disable, just output 0 in this channel."]
+    #[inline(always)]
+    pub fn tx_tdm_chan5_en(&mut self) -> TX_TDM_CHAN5_EN_W<TX_TDM_CTRL_SPEC> {
+        TX_TDM_CHAN5_EN_W::new(self, 5)
+    }
+    #[doc = "Bit 6 - 1: Enable the valid data output of I2S TX TDM channel 6. 0: Disable, just output 0 in this channel."]
+    #[inline(always)]
+    pub fn tx_tdm_chan6_en(&mut self) -> TX_TDM_CHAN6_EN_W<TX_TDM_CTRL_SPEC> {
+        TX_TDM_CHAN6_EN_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - 1: Enable the valid data output of I2S TX TDM channel 7. 0: Disable, just output 0 in this channel."]
+    #[inline(always)]
+    pub fn tx_tdm_chan7_en(&mut self) -> TX_TDM_CHAN7_EN_W<TX_TDM_CTRL_SPEC> {
+        TX_TDM_CHAN7_EN_W::new(self, 7)
+    }
+    #[doc = "Bit 8 - 1: Enable the valid data output of I2S TX TDM channel 8. 0: Disable, just output 0 in this channel."]
+    #[inline(always)]
+    pub fn tx_tdm_chan8_en(&mut self) -> TX_TDM_CHAN8_EN_W<TX_TDM_CTRL_SPEC> {
+        TX_TDM_CHAN8_EN_W::new(self, 8)
+    }
+    #[doc = "Bit 9 - 1: Enable the valid data output of I2S TX TDM channel 9. 0: Disable, just output 0 in this channel."]
+    #[inline(always)]
+    pub fn tx_tdm_chan9_en(&mut self) -> TX_TDM_CHAN9_EN_W<TX_TDM_CTRL_SPEC> {
+        TX_TDM_CHAN9_EN_W::new(self, 9)
+    }
+    #[doc = "Bit 10 - 1: Enable the valid data output of I2S TX TDM channel 10. 0: Disable, just output 0 in this channel."]
+    #[inline(always)]
+    pub fn tx_tdm_chan10_en(&mut self) -> TX_TDM_CHAN10_EN_W<TX_TDM_CTRL_SPEC> {
+        TX_TDM_CHAN10_EN_W::new(self, 10)
+    }
+    #[doc = "Bit 11 - 1: Enable the valid data output of I2S TX TDM channel 11. 0: Disable, just output 0 in this channel."]
+    #[inline(always)]
+    pub fn tx_tdm_chan11_en(&mut self) -> TX_TDM_CHAN11_EN_W<TX_TDM_CTRL_SPEC> {
+        TX_TDM_CHAN11_EN_W::new(self, 11)
+    }
+    #[doc = "Bit 12 - 1: Enable the valid data output of I2S TX TDM channel 12. 0: Disable, just output 0 in this channel."]
+    #[inline(always)]
+    pub fn tx_tdm_chan12_en(&mut self) -> TX_TDM_CHAN12_EN_W<TX_TDM_CTRL_SPEC> {
+        TX_TDM_CHAN12_EN_W::new(self, 12)
+    }
+    #[doc = "Bit 13 - 1: Enable the valid data output of I2S TX TDM channel 13. 0: Disable, just output 0 in this channel."]
+    #[inline(always)]
+    pub fn tx_tdm_chan13_en(&mut self) -> TX_TDM_CHAN13_EN_W<TX_TDM_CTRL_SPEC> {
+        TX_TDM_CHAN13_EN_W::new(self, 13)
+    }
+    #[doc = "Bit 14 - 1: Enable the valid data output of I2S TX TDM channel 14. 0: Disable, just output 0 in this channel."]
+    #[inline(always)]
+    pub fn tx_tdm_chan14_en(&mut self) -> TX_TDM_CHAN14_EN_W<TX_TDM_CTRL_SPEC> {
+        TX_TDM_CHAN14_EN_W::new(self, 14)
+    }
+    #[doc = "Bit 15 - 1: Enable the valid data output of I2S TX TDM channel 15. 0: Disable, just output 0 in this channel."]
+    #[inline(always)]
+    pub fn tx_tdm_chan15_en(&mut self) -> TX_TDM_CHAN15_EN_W<TX_TDM_CTRL_SPEC> {
+        TX_TDM_CHAN15_EN_W::new(self, 15)
+    }
+    #[doc = "Bits 16:19 - The total channel number of I2S TX TDM mode."]
+    #[inline(always)]
+    pub fn tx_tdm_tot_chan_num(&mut self) -> TX_TDM_TOT_CHAN_NUM_W<TX_TDM_CTRL_SPEC> {
+        TX_TDM_TOT_CHAN_NUM_W::new(self, 16)
+    }
+    #[doc = "Bit 20 - When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, and only the data of the enabled channels is sent, then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels."]
+    #[inline(always)]
+    pub fn tx_tdm_skip_msk_en(&mut self) -> TX_TDM_SKIP_MSK_EN_W<TX_TDM_CTRL_SPEC> {
+        TX_TDM_SKIP_MSK_EN_W::new(self, 20)
+    }
+}
+#[doc = "I2S TX TDM mode control register\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_tdm_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_tdm_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct TX_TDM_CTRL_SPEC;
+impl crate::RegisterSpec for TX_TDM_CTRL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`tx_tdm_ctrl::R`](R) reader structure"]
+impl crate::Readable for TX_TDM_CTRL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`tx_tdm_ctrl::W`](W) writer structure"]
+impl crate::Writable for TX_TDM_CTRL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets TX_TDM_CTRL to value 0xffff"]
+impl crate::Resettable for TX_TDM_CTRL_SPEC {
+    const RESET_VALUE: u32 = 0xffff;
+}

vendor/esp32s3/src/i2s0/tx_timing.rs

@@ -0,0 +1,122 @@
+#[doc = "Register `TX_TIMING` reader"]
+pub type R = crate::R<TX_TIMING_SPEC>;
+#[doc = "Register `TX_TIMING` writer"]
+pub type W = crate::W<TX_TIMING_SPEC>;
+#[doc = "Field `TX_SD_OUT_DM` reader - The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
+pub type TX_SD_OUT_DM_R = crate::FieldReader;
+#[doc = "Field `TX_SD_OUT_DM` writer - The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
+pub type TX_SD_OUT_DM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `TX_SD1_OUT_DM` reader - The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
+pub type TX_SD1_OUT_DM_R = crate::FieldReader;
+#[doc = "Field `TX_SD1_OUT_DM` writer - The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
+pub type TX_SD1_OUT_DM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `TX_WS_OUT_DM` reader - The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
+pub type TX_WS_OUT_DM_R = crate::FieldReader;
+#[doc = "Field `TX_WS_OUT_DM` writer - The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
+pub type TX_WS_OUT_DM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `TX_BCK_OUT_DM` reader - The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
+pub type TX_BCK_OUT_DM_R = crate::FieldReader;
+#[doc = "Field `TX_BCK_OUT_DM` writer - The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
+pub type TX_BCK_OUT_DM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `TX_WS_IN_DM` reader - The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
+pub type TX_WS_IN_DM_R = crate::FieldReader;
+#[doc = "Field `TX_WS_IN_DM` writer - The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
+pub type TX_WS_IN_DM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `TX_BCK_IN_DM` reader - The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
+pub type TX_BCK_IN_DM_R = crate::FieldReader;
+#[doc = "Field `TX_BCK_IN_DM` writer - The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
+pub type TX_BCK_IN_DM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+impl R {
+    #[doc = "Bits 0:1 - The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
+    #[inline(always)]
+    pub fn tx_sd_out_dm(&self) -> TX_SD_OUT_DM_R {
+        TX_SD_OUT_DM_R::new((self.bits & 3) as u8)
+    }
+    #[doc = "Bits 4:5 - The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
+    #[inline(always)]
+    pub fn tx_sd1_out_dm(&self) -> TX_SD1_OUT_DM_R {
+        TX_SD1_OUT_DM_R::new(((self.bits >> 4) & 3) as u8)
+    }
+    #[doc = "Bits 16:17 - The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
+    #[inline(always)]
+    pub fn tx_ws_out_dm(&self) -> TX_WS_OUT_DM_R {
+        TX_WS_OUT_DM_R::new(((self.bits >> 16) & 3) as u8)
+    }
+    #[doc = "Bits 20:21 - The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
+    #[inline(always)]
+    pub fn tx_bck_out_dm(&self) -> TX_BCK_OUT_DM_R {
+        TX_BCK_OUT_DM_R::new(((self.bits >> 20) & 3) as u8)
+    }
+    #[doc = "Bits 24:25 - The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
+    #[inline(always)]
+    pub fn tx_ws_in_dm(&self) -> TX_WS_IN_DM_R {
+        TX_WS_IN_DM_R::new(((self.bits >> 24) & 3) as u8)
+    }
+    #[doc = "Bits 28:29 - The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
+    #[inline(always)]
+    pub fn tx_bck_in_dm(&self) -> TX_BCK_IN_DM_R {
+        TX_BCK_IN_DM_R::new(((self.bits >> 28) & 3) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("TX_TIMING")
+            .field("tx_sd_out_dm", &self.tx_sd_out_dm())
+            .field("tx_sd1_out_dm", &self.tx_sd1_out_dm())
+            .field("tx_ws_out_dm", &self.tx_ws_out_dm())
+            .field("tx_bck_out_dm", &self.tx_bck_out_dm())
+            .field("tx_ws_in_dm", &self.tx_ws_in_dm())
+            .field("tx_bck_in_dm", &self.tx_bck_in_dm())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:1 - The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
+    #[inline(always)]
+    pub fn tx_sd_out_dm(&mut self) -> TX_SD_OUT_DM_W<TX_TIMING_SPEC> {
+        TX_SD_OUT_DM_W::new(self, 0)
+    }
+    #[doc = "Bits 4:5 - The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
+    #[inline(always)]
+    pub fn tx_sd1_out_dm(&mut self) -> TX_SD1_OUT_DM_W<TX_TIMING_SPEC> {
+        TX_SD1_OUT_DM_W::new(self, 4)
+    }
+    #[doc = "Bits 16:17 - The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
+    #[inline(always)]
+    pub fn tx_ws_out_dm(&mut self) -> TX_WS_OUT_DM_W<TX_TIMING_SPEC> {
+        TX_WS_OUT_DM_W::new(self, 16)
+    }
+    #[doc = "Bits 20:21 - The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
+    #[inline(always)]
+    pub fn tx_bck_out_dm(&mut self) -> TX_BCK_OUT_DM_W<TX_TIMING_SPEC> {
+        TX_BCK_OUT_DM_W::new(self, 20)
+    }
+    #[doc = "Bits 24:25 - The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
+    #[inline(always)]
+    pub fn tx_ws_in_dm(&mut self) -> TX_WS_IN_DM_W<TX_TIMING_SPEC> {
+        TX_WS_IN_DM_W::new(self, 24)
+    }
+    #[doc = "Bits 28:29 - The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
+    #[inline(always)]
+    pub fn tx_bck_in_dm(&mut self) -> TX_BCK_IN_DM_W<TX_TIMING_SPEC> {
+        TX_BCK_IN_DM_W::new(self, 28)
+    }
+}
+#[doc = "I2S TX timing control register\n\nYou can [`read`](crate::Reg::read) this register and get [`tx_timing::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tx_timing::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct TX_TIMING_SPEC;
+impl crate::RegisterSpec for TX_TIMING_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`tx_timing::R`](R) reader structure"]
+impl crate::Readable for TX_TIMING_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`tx_timing::W`](W) writer structure"]
+impl crate::Writable for TX_TIMING_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets TX_TIMING to value 0"]
+impl crate::Resettable for TX_TIMING_SPEC {
+    const RESET_VALUE: u32 = 0;
+}