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feat: add display UI with splash screen, dashboard, and RSSI sparkline

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Implement full SSD1306 OLED display support:
- Splash screen on boot (1.5s) with project name, version, board
- Dashboard showing radio state, config, counters, RSSI/SNR
- RSSI history sparkline (64-sample ring buffer, 2px-wide bars)
- DisplayOn/DisplayOff host commands routed via dedicated channel
- Pure render functions against generic DrawTarget (no hardware coupling)
- Display on/off control bypasses radio task entirely

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
This commit is contained in:
swaitsandClaude Opus 4.6 committed 2026-03-29 20:42:54 -06:00
1 parent 7064110293
commit 3102fc747a
17624 files changed
+4564928 -38
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vendor/esp32s3/src/ledc/ch.rs
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#[repr(C)]
#[cfg_attr(feature = "impl-register-debug", derive(Debug))]
#[doc = "Cluster CH%s, containing CH?_CONF0, CH?_HPOINT, CH?_DUTY, CH?_CONF1, CH?_DUTY_R"]
pub struct CH {
conf0: CONF0,
hpoint: HPOINT,
duty: DUTY,
conf1: CONF1,
duty_r: DUTY_R,
}
impl CH {
#[doc = "0x00 - Configuration register 0 for channel 0"]
#[inline(always)]
pub const fn conf0(&self) -> &CONF0 {
&self.conf0
}
#[doc = "0x04 - High point register for channel 0"]
#[inline(always)]
pub const fn hpoint(&self) -> &HPOINT {
&self.hpoint
}
#[doc = "0x08 - Initial duty cycle for channel 0"]
#[inline(always)]
pub const fn duty(&self) -> &DUTY {
&self.duty
}
#[doc = "0x0c - Configuration register 1 for channel 0"]
#[inline(always)]
pub const fn conf1(&self) -> &CONF1 {
&self.conf1
}
#[doc = "0x10 - Current duty cycle for channel 0"]
#[inline(always)]
pub const fn duty_r(&self) -> &DUTY_R {
&self.duty_r
}
}
#[doc = "CONF0 (rw) register accessor: Configuration register 0 for channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`conf0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`conf0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@conf0`] module"]
pub type CONF0 = crate::Reg<conf0::CONF0_SPEC>;
#[doc = "Configuration register 0 for channel 0"]
pub mod conf0;
#[doc = "HPOINT (rw) register accessor: High point register for channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`hpoint::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hpoint::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hpoint`] module"]
pub type HPOINT = crate::Reg<hpoint::HPOINT_SPEC>;
#[doc = "High point register for channel 0"]
pub mod hpoint;
#[doc = "DUTY (rw) register accessor: Initial duty cycle for channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`duty::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`duty::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@duty`] module"]
pub type DUTY = crate::Reg<duty::DUTY_SPEC>;
#[doc = "Initial duty cycle for channel 0"]
pub mod duty;
#[doc = "CONF1 (rw) register accessor: Configuration register 1 for channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`conf1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`conf1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@conf1`] module"]
pub type CONF1 = crate::Reg<conf1::CONF1_SPEC>;
#[doc = "Configuration register 1 for channel 0"]
pub mod conf1;
#[doc = "DUTY_R (r) register accessor: Current duty cycle for channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`duty_r::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@duty_r`] module"]
pub type DUTY_R = crate::Reg<duty_r::DUTY_R_SPEC>;
#[doc = "Current duty cycle for channel 0"]
pub mod duty_r;
vendor/esp32s3/src/ledc/ch/conf0.rs
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#[doc = "Register `CONF0` reader"]
pub type R = crate::R<CONF0_SPEC>;
#[doc = "Register `CONF0` writer"]
pub type W = crate::W<CONF0_SPEC>;
#[doc = "Field `TIMER_SEL` reader - This field is used to select one of timers for channel %s. 0: select timer0 1: select timer1 2: select timer2 3: select timer3"]
pub type TIMER_SEL_R = crate::FieldReader;
#[doc = "Field `TIMER_SEL` writer - This field is used to select one of timers for channel %s. 0: select timer0 1: select timer1 2: select timer2 3: select timer3"]
pub type TIMER_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `SIG_OUT_EN` reader - Set this bit to enable signal output on channel %s."]
pub type SIG_OUT_EN_R = crate::BitReader;
#[doc = "Field `SIG_OUT_EN` writer - Set this bit to enable signal output on channel %s."]
pub type SIG_OUT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IDLE_LV` reader - This bit is used to control the output value when channel %s is inactive (when LEDC_SIG_OUT_EN_CH%s is 0)."]
pub type IDLE_LV_R = crate::BitReader;
#[doc = "Field `IDLE_LV` writer - This bit is used to control the output value when channel %s is inactive (when LEDC_SIG_OUT_EN_CH%s is 0)."]
pub type IDLE_LV_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PARA_UP` writer - This bit is used to update LEDC_HPOINT_CH%s, LEDC_DUTY_START_CH%s, LEDC_SIG_OUT_EN_CH%s, LEDC_TIMER_SEL_CH%s, LEDC_DUTY_NUM_CH%s, LEDC_DUTY_CYCLE_CH%s, LEDC_DUTY_SCALE_CH%s, LEDC_DUTY_INC_CH%s, and LEDC_OVF_CNT_EN_CH%s fields for channel %s, and will be automatically cleared by hardware."]
pub type PARA_UP_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OVF_NUM` reader - This register is used to configure the maximum times of overflow minus 1. The LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows for (LEDC_OVF_NUM_CH%s + 1) times."]
pub type OVF_NUM_R = crate::FieldReader<u16>;
#[doc = "Field `OVF_NUM` writer - This register is used to configure the maximum times of overflow minus 1. The LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows for (LEDC_OVF_NUM_CH%s + 1) times."]
pub type OVF_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
#[doc = "Field `OVF_CNT_EN` reader - This bit is used to enable the ovf_cnt of channel %s."]
pub type OVF_CNT_EN_R = crate::BitReader;
#[doc = "Field `OVF_CNT_EN` writer - This bit is used to enable the ovf_cnt of channel %s."]
pub type OVF_CNT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OVF_CNT_RESET` writer - Set this bit to reset the ovf_cnt of channel %s."]
pub type OVF_CNT_RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OVF_CNT_RESET_ST` reader - This is the status bit of LEDC_OVF_CNT_RESET_CH%s."]
pub type OVF_CNT_RESET_ST_R = crate::BitReader;
#[doc = "Field `OVF_CNT_RESET_ST` writer - This is the status bit of LEDC_OVF_CNT_RESET_CH%s."]
pub type OVF_CNT_RESET_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:1 - This field is used to select one of timers for channel %s. 0: select timer0 1: select timer1 2: select timer2 3: select timer3"]
#[inline(always)]
pub fn timer_sel(&self) -> TIMER_SEL_R {
TIMER_SEL_R::new((self.bits & 3) as u8)
}
#[doc = "Bit 2 - Set this bit to enable signal output on channel %s."]
#[inline(always)]
pub fn sig_out_en(&self) -> SIG_OUT_EN_R {
SIG_OUT_EN_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - This bit is used to control the output value when channel %s is inactive (when LEDC_SIG_OUT_EN_CH%s is 0)."]
#[inline(always)]
pub fn idle_lv(&self) -> IDLE_LV_R {
IDLE_LV_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 5:14 - This register is used to configure the maximum times of overflow minus 1. The LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows for (LEDC_OVF_NUM_CH%s + 1) times."]
#[inline(always)]
pub fn ovf_num(&self) -> OVF_NUM_R {
OVF_NUM_R::new(((self.bits >> 5) & 0x03ff) as u16)
}
#[doc = "Bit 15 - This bit is used to enable the ovf_cnt of channel %s."]
#[inline(always)]
pub fn ovf_cnt_en(&self) -> OVF_CNT_EN_R {
OVF_CNT_EN_R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 17 - This is the status bit of LEDC_OVF_CNT_RESET_CH%s."]
#[inline(always)]
pub fn ovf_cnt_reset_st(&self) -> OVF_CNT_RESET_ST_R {
OVF_CNT_RESET_ST_R::new(((self.bits >> 17) & 1) != 0)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CONF0")
.field("timer_sel", &self.timer_sel())
.field("sig_out_en", &self.sig_out_en())
.field("idle_lv", &self.idle_lv())
.field("ovf_num", &self.ovf_num())
.field("ovf_cnt_en", &self.ovf_cnt_en())
.field("ovf_cnt_reset_st", &self.ovf_cnt_reset_st())
.finish()
}
}
impl W {
#[doc = "Bits 0:1 - This field is used to select one of timers for channel %s. 0: select timer0 1: select timer1 2: select timer2 3: select timer3"]
#[inline(always)]
pub fn timer_sel(&mut self) -> TIMER_SEL_W<CONF0_SPEC> {
TIMER_SEL_W::new(self, 0)
}
#[doc = "Bit 2 - Set this bit to enable signal output on channel %s."]
#[inline(always)]
pub fn sig_out_en(&mut self) -> SIG_OUT_EN_W<CONF0_SPEC> {
SIG_OUT_EN_W::new(self, 2)
}
#[doc = "Bit 3 - This bit is used to control the output value when channel %s is inactive (when LEDC_SIG_OUT_EN_CH%s is 0)."]
#[inline(always)]
pub fn idle_lv(&mut self) -> IDLE_LV_W<CONF0_SPEC> {
IDLE_LV_W::new(self, 3)
}
#[doc = "Bit 4 - This bit is used to update LEDC_HPOINT_CH%s, LEDC_DUTY_START_CH%s, LEDC_SIG_OUT_EN_CH%s, LEDC_TIMER_SEL_CH%s, LEDC_DUTY_NUM_CH%s, LEDC_DUTY_CYCLE_CH%s, LEDC_DUTY_SCALE_CH%s, LEDC_DUTY_INC_CH%s, and LEDC_OVF_CNT_EN_CH%s fields for channel %s, and will be automatically cleared by hardware."]
#[inline(always)]
pub fn para_up(&mut self) -> PARA_UP_W<CONF0_SPEC> {
PARA_UP_W::new(self, 4)
}
#[doc = "Bits 5:14 - This register is used to configure the maximum times of overflow minus 1. The LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows for (LEDC_OVF_NUM_CH%s + 1) times."]
#[inline(always)]
pub fn ovf_num(&mut self) -> OVF_NUM_W<CONF0_SPEC> {
OVF_NUM_W::new(self, 5)
}
#[doc = "Bit 15 - This bit is used to enable the ovf_cnt of channel %s."]
#[inline(always)]
pub fn ovf_cnt_en(&mut self) -> OVF_CNT_EN_W<CONF0_SPEC> {
OVF_CNT_EN_W::new(self, 15)
}
#[doc = "Bit 16 - Set this bit to reset the ovf_cnt of channel %s."]
#[inline(always)]
pub fn ovf_cnt_reset(&mut self) -> OVF_CNT_RESET_W<CONF0_SPEC> {
OVF_CNT_RESET_W::new(self, 16)
}
#[doc = "Bit 17 - This is the status bit of LEDC_OVF_CNT_RESET_CH%s."]
#[inline(always)]
pub fn ovf_cnt_reset_st(&mut self) -> OVF_CNT_RESET_ST_W<CONF0_SPEC> {
OVF_CNT_RESET_ST_W::new(self, 17)
}
}
#[doc = "Configuration register 0 for channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`conf0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`conf0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CONF0_SPEC;
impl crate::RegisterSpec for CONF0_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`conf0::R`](R) reader structure"]
impl crate::Readable for CONF0_SPEC {}
#[doc = "`write(|w| ..)` method takes [`conf0::W`](W) writer structure"]
impl crate::Writable for CONF0_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CONF0 to value 0"]
impl crate::Resettable for CONF0_SPEC {
const RESET_VALUE: u32 = 0;
}
vendor/esp32s3/src/ledc/ch/conf1.rs
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#[doc = "Register `CONF1` reader"]
pub type R = crate::R<CONF1_SPEC>;
#[doc = "Register `CONF1` writer"]
pub type W = crate::W<CONF1_SPEC>;
#[doc = "Field `DUTY_SCALE` reader - This register is used to configure the changing step scale of duty on channel %s."]
pub type DUTY_SCALE_R = crate::FieldReader<u16>;
#[doc = "Field `DUTY_SCALE` writer - This register is used to configure the changing step scale of duty on channel %s."]
pub type DUTY_SCALE_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
#[doc = "Field `DUTY_CYCLE` reader - The duty will change every LEDC_DUTY_CYCLE_CH%s on channel %s."]
pub type DUTY_CYCLE_R = crate::FieldReader<u16>;
#[doc = "Field `DUTY_CYCLE` writer - The duty will change every LEDC_DUTY_CYCLE_CH%s on channel %s."]
pub type DUTY_CYCLE_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
#[doc = "Field `DUTY_NUM` reader - This register is used to control the number of times the duty cycle will be changed."]
pub type DUTY_NUM_R = crate::FieldReader<u16>;
#[doc = "Field `DUTY_NUM` writer - This register is used to control the number of times the duty cycle will be changed."]
pub type DUTY_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
#[doc = "Field `DUTY_INC` reader - This register is used to increase or decrease the duty of output signal on channel %s. 1: Increase; 0: Decrease."]
pub type DUTY_INC_R = crate::BitReader;
#[doc = "Field `DUTY_INC` writer - This register is used to increase or decrease the duty of output signal on channel %s. 1: Increase; 0: Decrease."]
pub type DUTY_INC_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DUTY_START` reader - Other configured fields in LEDC_CH%s_CONF1_REG will start to take effect when this bit is set to 1."]
pub type DUTY_START_R = crate::BitReader;
#[doc = "Field `DUTY_START` writer - Other configured fields in LEDC_CH%s_CONF1_REG will start to take effect when this bit is set to 1."]
pub type DUTY_START_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:9 - This register is used to configure the changing step scale of duty on channel %s."]
#[inline(always)]
pub fn duty_scale(&self) -> DUTY_SCALE_R {
DUTY_SCALE_R::new((self.bits & 0x03ff) as u16)
}
#[doc = "Bits 10:19 - The duty will change every LEDC_DUTY_CYCLE_CH%s on channel %s."]
#[inline(always)]
pub fn duty_cycle(&self) -> DUTY_CYCLE_R {
DUTY_CYCLE_R::new(((self.bits >> 10) & 0x03ff) as u16)
}
#[doc = "Bits 20:29 - This register is used to control the number of times the duty cycle will be changed."]
#[inline(always)]
pub fn duty_num(&self) -> DUTY_NUM_R {
DUTY_NUM_R::new(((self.bits >> 20) & 0x03ff) as u16)
}
#[doc = "Bit 30 - This register is used to increase or decrease the duty of output signal on channel %s. 1: Increase; 0: Decrease."]
#[inline(always)]
pub fn duty_inc(&self) -> DUTY_INC_R {
DUTY_INC_R::new(((self.bits >> 30) & 1) != 0)
}
#[doc = "Bit 31 - Other configured fields in LEDC_CH%s_CONF1_REG will start to take effect when this bit is set to 1."]
#[inline(always)]
pub fn duty_start(&self) -> DUTY_START_R {
DUTY_START_R::new(((self.bits >> 31) & 1) != 0)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CONF1")
.field("duty_scale", &self.duty_scale())
.field("duty_cycle", &self.duty_cycle())
.field("duty_num", &self.duty_num())
.field("duty_inc", &self.duty_inc())
.field("duty_start", &self.duty_start())
.finish()
}
}
impl W {
#[doc = "Bits 0:9 - This register is used to configure the changing step scale of duty on channel %s."]
#[inline(always)]
pub fn duty_scale(&mut self) -> DUTY_SCALE_W<CONF1_SPEC> {
DUTY_SCALE_W::new(self, 0)
}
#[doc = "Bits 10:19 - The duty will change every LEDC_DUTY_CYCLE_CH%s on channel %s."]
#[inline(always)]
pub fn duty_cycle(&mut self) -> DUTY_CYCLE_W<CONF1_SPEC> {
DUTY_CYCLE_W::new(self, 10)
}
#[doc = "Bits 20:29 - This register is used to control the number of times the duty cycle will be changed."]
#[inline(always)]
pub fn duty_num(&mut self) -> DUTY_NUM_W<CONF1_SPEC> {
DUTY_NUM_W::new(self, 20)
}
#[doc = "Bit 30 - This register is used to increase or decrease the duty of output signal on channel %s. 1: Increase; 0: Decrease."]
#[inline(always)]
pub fn duty_inc(&mut self) -> DUTY_INC_W<CONF1_SPEC> {
DUTY_INC_W::new(self, 30)
}
#[doc = "Bit 31 - Other configured fields in LEDC_CH%s_CONF1_REG will start to take effect when this bit is set to 1."]
#[inline(always)]
pub fn duty_start(&mut self) -> DUTY_START_W<CONF1_SPEC> {
DUTY_START_W::new(self, 31)
}
}
#[doc = "Configuration register 1 for channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`conf1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`conf1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CONF1_SPEC;
impl crate::RegisterSpec for CONF1_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`conf1::R`](R) reader structure"]
impl crate::Readable for CONF1_SPEC {}
#[doc = "`write(|w| ..)` method takes [`conf1::W`](W) writer structure"]
impl crate::Writable for CONF1_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CONF1 to value 0x4000_0000"]
impl crate::Resettable for CONF1_SPEC {
const RESET_VALUE: u32 = 0x4000_0000;
}
vendor/esp32s3/src/ledc/ch/duty.rs
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#[doc = "Register `DUTY` reader"]
pub type R = crate::R<DUTY_SPEC>;
#[doc = "Register `DUTY` writer"]
pub type W = crate::W<DUTY_SPEC>;
#[doc = "Field `DUTY` reader - This register is used to change the output duty by controlling the Lpoint. The output value turns to low when the selected timers has reached the Lpoint."]
pub type DUTY_R = crate::FieldReader<u32>;
#[doc = "Field `DUTY` writer - This register is used to change the output duty by controlling the Lpoint. The output value turns to low when the selected timers has reached the Lpoint."]
pub type DUTY_W<'a, REG> = crate::FieldWriter<'a, REG, 19, u32>;
impl R {
#[doc = "Bits 0:18 - This register is used to change the output duty by controlling the Lpoint. The output value turns to low when the selected timers has reached the Lpoint."]
#[inline(always)]
pub fn duty(&self) -> DUTY_R {
DUTY_R::new(self.bits & 0x0007_ffff)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DUTY").field("duty", &self.duty()).finish()
}
}
impl W {
#[doc = "Bits 0:18 - This register is used to change the output duty by controlling the Lpoint. The output value turns to low when the selected timers has reached the Lpoint."]
#[inline(always)]
pub fn duty(&mut self) -> DUTY_W<DUTY_SPEC> {
DUTY_W::new(self, 0)
}
}
#[doc = "Initial duty cycle for channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`duty::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`duty::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DUTY_SPEC;
impl crate::RegisterSpec for DUTY_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`duty::R`](R) reader structure"]
impl crate::Readable for DUTY_SPEC {}
#[doc = "`write(|w| ..)` method takes [`duty::W`](W) writer structure"]
impl crate::Writable for DUTY_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DUTY to value 0"]
impl crate::Resettable for DUTY_SPEC {
const RESET_VALUE: u32 = 0;
}
vendor/esp32s3/src/ledc/ch/duty_r.rs
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#[doc = "Register `DUTY_R` reader"]
pub type R = crate::R<DUTY_R_SPEC>;
#[doc = "Field `DUTY_R` reader - This register stores the current duty of output signal on channel %s."]
pub type DUTY_R_R = crate::FieldReader<u32>;
impl R {
#[doc = "Bits 0:18 - This register stores the current duty of output signal on channel %s."]
#[inline(always)]
pub fn duty_r(&self) -> DUTY_R_R {
DUTY_R_R::new(self.bits & 0x0007_ffff)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DUTY_R")
.field("duty_r", &self.duty_r())
.finish()
}
}
#[doc = "Current duty cycle for channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`duty_r::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DUTY_R_SPEC;
impl crate::RegisterSpec for DUTY_R_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`duty_r::R`](R) reader structure"]
impl crate::Readable for DUTY_R_SPEC {}
#[doc = "`reset()` method sets DUTY_R to value 0"]
impl crate::Resettable for DUTY_R_SPEC {
const RESET_VALUE: u32 = 0;
}
vendor/esp32s3/src/ledc/ch/hpoint.rs
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#[doc = "Register `HPOINT` reader"]
pub type R = crate::R<HPOINT_SPEC>;
#[doc = "Register `HPOINT` writer"]
pub type W = crate::W<HPOINT_SPEC>;
#[doc = "Field `HPOINT` reader - The output value changes to high when the selected timers has reached the value specified by this register."]
pub type HPOINT_R = crate::FieldReader<u16>;
#[doc = "Field `HPOINT` writer - The output value changes to high when the selected timers has reached the value specified by this register."]
pub type HPOINT_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>;
impl R {
#[doc = "Bits 0:13 - The output value changes to high when the selected timers has reached the value specified by this register."]
#[inline(always)]
pub fn hpoint(&self) -> HPOINT_R {
HPOINT_R::new((self.bits & 0x3fff) as u16)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("HPOINT")
.field("hpoint", &self.hpoint())
.finish()
}
}
impl W {
#[doc = "Bits 0:13 - The output value changes to high when the selected timers has reached the value specified by this register."]
#[inline(always)]
pub fn hpoint(&mut self) -> HPOINT_W<HPOINT_SPEC> {
HPOINT_W::new(self, 0)
}
}
#[doc = "High point register for channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`hpoint::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hpoint::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HPOINT_SPEC;
impl crate::RegisterSpec for HPOINT_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`hpoint::R`](R) reader structure"]
impl crate::Readable for HPOINT_SPEC {}
#[doc = "`write(|w| ..)` method takes [`hpoint::W`](W) writer structure"]
impl crate::Writable for HPOINT_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets HPOINT to value 0"]
impl crate::Resettable for HPOINT_SPEC {
const RESET_VALUE: u32 = 0;
}
vendor/esp32s3/src/ledc/conf.rs
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#[doc = "Register `CONF` reader"]
pub type R = crate::R<CONF_SPEC>;
#[doc = "Register `CONF` writer"]
pub type W = crate::W<CONF_SPEC>;
#[doc = "Field `APB_CLK_SEL` reader - This bit is used to select clock source for the 4 timers . 2'd1: APB_CLK 2'd2: RTC8M_CLK 2'd3: XTAL_CLK"]
pub type APB_CLK_SEL_R = crate::FieldReader;
#[doc = "Field `APB_CLK_SEL` writer - This bit is used to select clock source for the 4 timers . 2'd1: APB_CLK 2'd2: RTC8M_CLK 2'd3: XTAL_CLK"]
pub type APB_CLK_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `CLK_EN` reader - This bit is used to control clock. 1'b1: Force clock on for register. 1'h0: Support clock only when application writes registers."]
pub type CLK_EN_R = crate::BitReader;
#[doc = "Field `CLK_EN` writer - This bit is used to control clock. 1'b1: Force clock on for register. 1'h0: Support clock only when application writes registers."]
pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:1 - This bit is used to select clock source for the 4 timers . 2'd1: APB_CLK 2'd2: RTC8M_CLK 2'd3: XTAL_CLK"]
#[inline(always)]
pub fn apb_clk_sel(&self) -> APB_CLK_SEL_R {
APB_CLK_SEL_R::new((self.bits & 3) as u8)
}
#[doc = "Bit 31 - This bit is used to control clock. 1'b1: Force clock on for register. 1'h0: Support clock only when application writes registers."]
#[inline(always)]
pub fn clk_en(&self) -> CLK_EN_R {
CLK_EN_R::new(((self.bits >> 31) & 1) != 0)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CONF")
.field("apb_clk_sel", &self.apb_clk_sel())
.field("clk_en", &self.clk_en())
.finish()
}
}
impl W {
#[doc = "Bits 0:1 - This bit is used to select clock source for the 4 timers . 2'd1: APB_CLK 2'd2: RTC8M_CLK 2'd3: XTAL_CLK"]
#[inline(always)]
pub fn apb_clk_sel(&mut self) -> APB_CLK_SEL_W<CONF_SPEC> {
APB_CLK_SEL_W::new(self, 0)
}
#[doc = "Bit 31 - This bit is used to control clock. 1'b1: Force clock on for register. 1'h0: Support clock only when application writes registers."]
#[inline(always)]
pub fn clk_en(&mut self) -> CLK_EN_W<CONF_SPEC> {
CLK_EN_W::new(self, 31)
}
}
#[doc = "Global ledc configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CONF_SPEC;
impl crate::RegisterSpec for CONF_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`conf::R`](R) reader structure"]
impl crate::Readable for CONF_SPEC {}
#[doc = "`write(|w| ..)` method takes [`conf::W`](W) writer structure"]
impl crate::Writable for CONF_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CONF to value 0"]
impl crate::Resettable for CONF_SPEC {
const RESET_VALUE: u32 = 0;
}
vendor/esp32s3/src/ledc/date.rs
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#[doc = "Register `DATE` reader"]
pub type R = crate::R<DATE_SPEC>;
#[doc = "Register `DATE` writer"]
pub type W = crate::W<DATE_SPEC>;
#[doc = "Field `DATE` reader - This is the version control register."]
pub type DATE_R = crate::FieldReader<u32>;
#[doc = "Field `DATE` writer - This is the version control register."]
pub type DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - This is the version control register."]
#[inline(always)]
pub fn date(&self) -> DATE_R {
DATE_R::new(self.bits)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("DATE").field("date", &self.date()).finish()
}
}
impl W {
#[doc = "Bits 0:31 - This is the version control register."]
#[inline(always)]
pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
DATE_W::new(self, 0)
}
}
#[doc = "Version control register\n\nYou can [`read`](crate::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DATE_SPEC;
impl crate::RegisterSpec for DATE_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`date::R`](R) reader structure"]
impl crate::Readable for DATE_SPEC {}
#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"]
impl crate::Writable for DATE_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DATE to value 0x1904_0200"]
impl crate::Resettable for DATE_SPEC {
const RESET_VALUE: u32 = 0x1904_0200;
}
vendor/esp32s3/src/ledc/int_clr.rs
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#[doc = "Register `INT_CLR` writer"]
pub type W = crate::W<INT_CLR_SPEC>;
#[doc = "Field `TIMER_OVF(0-3)` writer - Set this bit to clear the TIMER%s_OVF interrupt."]
pub type TIMER_OVF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
#[doc = "Field `DUTY_CHNG_END_CH(0-7)` writer - Set this bit to clear the DUTY_CHNG_END_CH%s interrupt."]
pub type DUTY_CHNG_END_CH_W<'a, REG> = crate::BitWriter1C<'a, REG>;
#[doc = "Field `OVF_CNT_CH(0-7)` writer - Set this bit to clear the OVF_CNT_CH%s interrupt."]
pub type OVF_CNT_CH_W<'a, REG> = crate::BitWriter1C<'a, REG>;
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
write!(f, "(not readable)")
}
}
impl W {
#[doc = "Set this bit to clear the TIMER(0-3)_OVF interrupt."]
#[doc = ""]
#[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_OVF` field.</div>"]
#[inline(always)]
pub fn timer_ovf(&mut self, n: u8) -> TIMER_OVF_W<INT_CLR_SPEC> {
#[allow(clippy::no_effect)]
[(); 4][n as usize];
TIMER_OVF_W::new(self, n)
}
#[doc = "Bit 0 - Set this bit to clear the TIMER0_OVF interrupt."]
#[inline(always)]
pub fn timer0_ovf(&mut self) -> TIMER_OVF_W<INT_CLR_SPEC> {
TIMER_OVF_W::new(self, 0)
}
#[doc = "Bit 1 - Set this bit to clear the TIMER1_OVF interrupt."]
#[inline(always)]
pub fn timer1_ovf(&mut self) -> TIMER_OVF_W<INT_CLR_SPEC> {
TIMER_OVF_W::new(self, 1)
}
#[doc = "Bit 2 - Set this bit to clear the TIMER2_OVF interrupt."]
#[inline(always)]
pub fn timer2_ovf(&mut self) -> TIMER_OVF_W<INT_CLR_SPEC> {
TIMER_OVF_W::new(self, 2)
}
#[doc = "Bit 3 - Set this bit to clear the TIMER3_OVF interrupt."]
#[inline(always)]
pub fn timer3_ovf(&mut self) -> TIMER_OVF_W<INT_CLR_SPEC> {
TIMER_OVF_W::new(self, 3)
}
#[doc = "Set this bit to clear the DUTY_CHNG_END_CH(0-7) interrupt."]
#[doc = ""]
#[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `DUTY_CHNG_END_CH0` field.</div>"]
#[inline(always)]
pub fn duty_chng_end_ch(&mut self, n: u8) -> DUTY_CHNG_END_CH_W<INT_CLR_SPEC> {
#[allow(clippy::no_effect)]
[(); 8][n as usize];
DUTY_CHNG_END_CH_W::new(self, n + 4)
}
#[doc = "Bit 4 - Set this bit to clear the DUTY_CHNG_END_CH0 interrupt."]
#[inline(always)]
pub fn duty_chng_end_ch0(&mut self) -> DUTY_CHNG_END_CH_W<INT_CLR_SPEC> {
DUTY_CHNG_END_CH_W::new(self, 4)
}
#[doc = "Bit 5 - Set this bit to clear the DUTY_CHNG_END_CH1 interrupt."]
#[inline(always)]
pub fn duty_chng_end_ch1(&mut self) -> DUTY_CHNG_END_CH_W<INT_CLR_SPEC> {
DUTY_CHNG_END_CH_W::new(self, 5)
}
#[doc = "Bit 6 - Set this bit to clear the DUTY_CHNG_END_CH2 interrupt."]
#[inline(always)]
pub fn duty_chng_end_ch2(&mut self) -> DUTY_CHNG_END_CH_W<INT_CLR_SPEC> {
DUTY_CHNG_END_CH_W::new(self, 6)
}
#[doc = "Bit 7 - Set this bit to clear the DUTY_CHNG_END_CH3 interrupt."]
#[inline(always)]
pub fn duty_chng_end_ch3(&mut self) -> DUTY_CHNG_END_CH_W<INT_CLR_SPEC> {
DUTY_CHNG_END_CH_W::new(self, 7)
}
#[doc = "Bit 8 - Set this bit to clear the DUTY_CHNG_END_CH4 interrupt."]
#[inline(always)]
pub fn duty_chng_end_ch4(&mut self) -> DUTY_CHNG_END_CH_W<INT_CLR_SPEC> {
DUTY_CHNG_END_CH_W::new(self, 8)
}
#[doc = "Bit 9 - Set this bit to clear the DUTY_CHNG_END_CH5 interrupt."]
#[inline(always)]
pub fn duty_chng_end_ch5(&mut self) -> DUTY_CHNG_END_CH_W<INT_CLR_SPEC> {
DUTY_CHNG_END_CH_W::new(self, 9)
}
#[doc = "Bit 10 - Set this bit to clear the DUTY_CHNG_END_CH6 interrupt."]
#[inline(always)]
pub fn duty_chng_end_ch6(&mut self) -> DUTY_CHNG_END_CH_W<INT_CLR_SPEC> {
DUTY_CHNG_END_CH_W::new(self, 10)
}
#[doc = "Bit 11 - Set this bit to clear the DUTY_CHNG_END_CH7 interrupt."]
#[inline(always)]
pub fn duty_chng_end_ch7(&mut self) -> DUTY_CHNG_END_CH_W<INT_CLR_SPEC> {
DUTY_CHNG_END_CH_W::new(self, 11)
}
#[doc = "Set this bit to clear the OVF_CNT_CH(0-7) interrupt."]
#[doc = ""]
#[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `OVF_CNT_CH0` field.</div>"]
#[inline(always)]
pub fn ovf_cnt_ch(&mut self, n: u8) -> OVF_CNT_CH_W<INT_CLR_SPEC> {
#[allow(clippy::no_effect)]
[(); 8][n as usize];
OVF_CNT_CH_W::new(self, n + 12)
}
#[doc = "Bit 12 - Set this bit to clear the OVF_CNT_CH0 interrupt."]
#[inline(always)]
pub fn ovf_cnt_ch0(&mut self) -> OVF_CNT_CH_W<INT_CLR_SPEC> {
OVF_CNT_CH_W::new(self, 12)
}
#[doc = "Bit 13 - Set this bit to clear the OVF_CNT_CH1 interrupt."]
#[inline(always)]
pub fn ovf_cnt_ch1(&mut self) -> OVF_CNT_CH_W<INT_CLR_SPEC> {
OVF_CNT_CH_W::new(self, 13)
}
#[doc = "Bit 14 - Set this bit to clear the OVF_CNT_CH2 interrupt."]
#[inline(always)]
pub fn ovf_cnt_ch2(&mut self) -> OVF_CNT_CH_W<INT_CLR_SPEC> {
OVF_CNT_CH_W::new(self, 14)
}
#[doc = "Bit 15 - Set this bit to clear the OVF_CNT_CH3 interrupt."]
#[inline(always)]
pub fn ovf_cnt_ch3(&mut self) -> OVF_CNT_CH_W<INT_CLR_SPEC> {
OVF_CNT_CH_W::new(self, 15)
}
#[doc = "Bit 16 - Set this bit to clear the OVF_CNT_CH4 interrupt."]
#[inline(always)]
pub fn ovf_cnt_ch4(&mut self) -> OVF_CNT_CH_W<INT_CLR_SPEC> {
OVF_CNT_CH_W::new(self, 16)
}
#[doc = "Bit 17 - Set this bit to clear the OVF_CNT_CH5 interrupt."]
#[inline(always)]
pub fn ovf_cnt_ch5(&mut self) -> OVF_CNT_CH_W<INT_CLR_SPEC> {
OVF_CNT_CH_W::new(self, 17)
}
#[doc = "Bit 18 - Set this bit to clear the OVF_CNT_CH6 interrupt."]
#[inline(always)]
pub fn ovf_cnt_ch6(&mut self) -> OVF_CNT_CH_W<INT_CLR_SPEC> {
OVF_CNT_CH_W::new(self, 18)
}
#[doc = "Bit 19 - Set this bit to clear the OVF_CNT_CH7 interrupt."]
#[inline(always)]
pub fn ovf_cnt_ch7(&mut self) -> OVF_CNT_CH_W<INT_CLR_SPEC> {
OVF_CNT_CH_W::new(self, 19)
}
}
#[doc = "Interrupt clear bits\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_CLR_SPEC;
impl crate::RegisterSpec for INT_CLR_SPEC {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
impl crate::Writable for INT_CLR_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x000f_ffff;
}
#[doc = "`reset()` method sets INT_CLR to value 0"]
impl crate::Resettable for INT_CLR_SPEC {
const RESET_VALUE: u32 = 0;
}
vendor/esp32s3/src/ledc/int_ena.rs
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#[doc = "Register `INT_ENA` reader"]
pub type R = crate::R<INT_ENA_SPEC>;
#[doc = "Register `INT_ENA` writer"]
pub type W = crate::W<INT_ENA_SPEC>;
#[doc = "Field `TIMER_OVF(0-3)` reader - The interrupt enable bit for the TIMER%s_OVF interrupt."]
pub type TIMER_OVF_R = crate::BitReader;
#[doc = "Field `TIMER_OVF(0-3)` writer - The interrupt enable bit for the TIMER%s_OVF interrupt."]
pub type TIMER_OVF_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DUTY_CHNG_END_CH(0-7)` reader - The interrupt enable bit for the DUTY_CHNG_END_CH%s interrupt."]
pub type DUTY_CHNG_END_CH_R = crate::BitReader;
#[doc = "Field `DUTY_CHNG_END_CH(0-7)` writer - The interrupt enable bit for the DUTY_CHNG_END_CH%s interrupt."]
pub type DUTY_CHNG_END_CH_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OVF_CNT_CH(0-7)` reader - The interrupt enable bit for the OVF_CNT_CH%s interrupt."]
pub type OVF_CNT_CH_R = crate::BitReader;
#[doc = "Field `OVF_CNT_CH(0-7)` writer - The interrupt enable bit for the OVF_CNT_CH%s interrupt."]
pub type OVF_CNT_CH_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "The interrupt enable bit for the TIMER(0-3)_OVF interrupt."]
#[doc = ""]
#[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_OVF` field.</div>"]
#[inline(always)]
pub fn timer_ovf(&self, n: u8) -> TIMER_OVF_R {
#[allow(clippy::no_effect)]
[(); 4][n as usize];
TIMER_OVF_R::new(((self.bits >> n) & 1) != 0)
}
#[doc = "Iterator for array of:"]
#[doc = "The interrupt enable bit for the TIMER(0-3)_OVF interrupt."]
#[inline(always)]
pub fn timer_ovf_iter(&self) -> impl Iterator<Item = TIMER_OVF_R> + '_ {
(0..4).map(move |n| TIMER_OVF_R::new(((self.bits >> n) & 1) != 0))
}
#[doc = "Bit 0 - The interrupt enable bit for the TIMER0_OVF interrupt."]
#[inline(always)]
pub fn timer0_ovf(&self) -> TIMER_OVF_R {
TIMER_OVF_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - The interrupt enable bit for the TIMER1_OVF interrupt."]
#[inline(always)]
pub fn timer1_ovf(&self) -> TIMER_OVF_R {
TIMER_OVF_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - The interrupt enable bit for the TIMER2_OVF interrupt."]
#[inline(always)]
pub fn timer2_ovf(&self) -> TIMER_OVF_R {
TIMER_OVF_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - The interrupt enable bit for the TIMER3_OVF interrupt."]
#[inline(always)]
pub fn timer3_ovf(&self) -> TIMER_OVF_R {
TIMER_OVF_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "The interrupt enable bit for the DUTY_CHNG_END_CH(0-7) interrupt."]
#[doc = ""]
#[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `DUTY_CHNG_END_CH0` field.</div>"]
#[inline(always)]
pub fn duty_chng_end_ch(&self, n: u8) -> DUTY_CHNG_END_CH_R {
#[allow(clippy::no_effect)]
[(); 8][n as usize];
DUTY_CHNG_END_CH_R::new(((self.bits >> (n + 4)) & 1) != 0)
}
#[doc = "Iterator for array of:"]
#[doc = "The interrupt enable bit for the DUTY_CHNG_END_CH(0-7) interrupt."]
#[inline(always)]
pub fn duty_chng_end_ch_iter(&self) -> impl Iterator<Item = DUTY_CHNG_END_CH_R> + '_ {
(0..8).map(move |n| DUTY_CHNG_END_CH_R::new(((self.bits >> (n + 4)) & 1) != 0))
}
#[doc = "Bit 4 - The interrupt enable bit for the DUTY_CHNG_END_CH0 interrupt."]
#[inline(always)]
pub fn duty_chng_end_ch0(&self) -> DUTY_CHNG_END_CH_R {
DUTY_CHNG_END_CH_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - The interrupt enable bit for the DUTY_CHNG_END_CH1 interrupt."]
#[inline(always)]
pub fn duty_chng_end_ch1(&self) -> DUTY_CHNG_END_CH_R {
DUTY_CHNG_END_CH_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - The interrupt enable bit for the DUTY_CHNG_END_CH2 interrupt."]
#[inline(always)]
pub fn duty_chng_end_ch2(&self) -> DUTY_CHNG_END_CH_R {
DUTY_CHNG_END_CH_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - The interrupt enable bit for the DUTY_CHNG_END_CH3 interrupt."]
#[inline(always)]
pub fn duty_chng_end_ch3(&self) -> DUTY_CHNG_END_CH_R {
DUTY_CHNG_END_CH_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - The interrupt enable bit for the DUTY_CHNG_END_CH4 interrupt."]
#[inline(always)]
pub fn duty_chng_end_ch4(&self) -> DUTY_CHNG_END_CH_R {
DUTY_CHNG_END_CH_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - The interrupt enable bit for the DUTY_CHNG_END_CH5 interrupt."]
#[inline(always)]
pub fn duty_chng_end_ch5(&self) -> DUTY_CHNG_END_CH_R {
DUTY_CHNG_END_CH_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - The interrupt enable bit for the DUTY_CHNG_END_CH6 interrupt."]
#[inline(always)]
pub fn duty_chng_end_ch6(&self) -> DUTY_CHNG_END_CH_R {
DUTY_CHNG_END_CH_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - The interrupt enable bit for the DUTY_CHNG_END_CH7 interrupt."]
#[inline(always)]
pub fn duty_chng_end_ch7(&self) -> DUTY_CHNG_END_CH_R {
DUTY_CHNG_END_CH_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "The interrupt enable bit for the OVF_CNT_CH(0-7) interrupt."]
#[doc = ""]
#[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `OVF_CNT_CH0` field.</div>"]
#[inline(always)]
pub fn ovf_cnt_ch(&self, n: u8) -> OVF_CNT_CH_R {
#[allow(clippy::no_effect)]
[(); 8][n as usize];
OVF_CNT_CH_R::new(((self.bits >> (n + 12)) & 1) != 0)
}
#[doc = "Iterator for array of:"]
#[doc = "The interrupt enable bit for the OVF_CNT_CH(0-7) interrupt."]
#[inline(always)]
pub fn ovf_cnt_ch_iter(&self) -> impl Iterator<Item = OVF_CNT_CH_R> + '_ {
(0..8).map(move |n| OVF_CNT_CH_R::new(((self.bits >> (n + 12)) & 1) != 0))
}
#[doc = "Bit 12 - The interrupt enable bit for the OVF_CNT_CH0 interrupt."]
#[inline(always)]
pub fn ovf_cnt_ch0(&self) -> OVF_CNT_CH_R {
OVF_CNT_CH_R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - The interrupt enable bit for the OVF_CNT_CH1 interrupt."]
#[inline(always)]
pub fn ovf_cnt_ch1(&self) -> OVF_CNT_CH_R {
OVF_CNT_CH_R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - The interrupt enable bit for the OVF_CNT_CH2 interrupt."]
#[inline(always)]
pub fn ovf_cnt_ch2(&self) -> OVF_CNT_CH_R {
OVF_CNT_CH_R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - The interrupt enable bit for the OVF_CNT_CH3 interrupt."]
#[inline(always)]
pub fn ovf_cnt_ch3(&self) -> OVF_CNT_CH_R {
OVF_CNT_CH_R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 16 - The interrupt enable bit for the OVF_CNT_CH4 interrupt."]
#[inline(always)]
pub fn ovf_cnt_ch4(&self) -> OVF_CNT_CH_R {
OVF_CNT_CH_R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17 - The interrupt enable bit for the OVF_CNT_CH5 interrupt."]
#[inline(always)]
pub fn ovf_cnt_ch5(&self) -> OVF_CNT_CH_R {
OVF_CNT_CH_R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18 - The interrupt enable bit for the OVF_CNT_CH6 interrupt."]
#[inline(always)]
pub fn ovf_cnt_ch6(&self) -> OVF_CNT_CH_R {
OVF_CNT_CH_R::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19 - The interrupt enable bit for the OVF_CNT_CH7 interrupt."]
#[inline(always)]
pub fn ovf_cnt_ch7(&self) -> OVF_CNT_CH_R {
OVF_CNT_CH_R::new(((self.bits >> 19) & 1) != 0)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("INT_ENA")
.field("timer0_ovf", &self.timer0_ovf())
.field("timer1_ovf", &self.timer1_ovf())
.field("timer2_ovf", &self.timer2_ovf())
.field("timer3_ovf", &self.timer3_ovf())
.field("duty_chng_end_ch0", &self.duty_chng_end_ch0())
.field("duty_chng_end_ch1", &self.duty_chng_end_ch1())
.field("duty_chng_end_ch2", &self.duty_chng_end_ch2())
.field("duty_chng_end_ch3", &self.duty_chng_end_ch3())
.field("duty_chng_end_ch4", &self.duty_chng_end_ch4())
.field("duty_chng_end_ch5", &self.duty_chng_end_ch5())
.field("duty_chng_end_ch6", &self.duty_chng_end_ch6())
.field("duty_chng_end_ch7", &self.duty_chng_end_ch7())
.field("ovf_cnt_ch0", &self.ovf_cnt_ch0())
.field("ovf_cnt_ch1", &self.ovf_cnt_ch1())
.field("ovf_cnt_ch2", &self.ovf_cnt_ch2())
.field("ovf_cnt_ch3", &self.ovf_cnt_ch3())
.field("ovf_cnt_ch4", &self.ovf_cnt_ch4())
.field("ovf_cnt_ch5", &self.ovf_cnt_ch5())
.field("ovf_cnt_ch6", &self.ovf_cnt_ch6())
.field("ovf_cnt_ch7", &self.ovf_cnt_ch7())
.finish()
}
}
impl W {
#[doc = "The interrupt enable bit for the TIMER(0-3)_OVF interrupt."]
#[doc = ""]
#[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_OVF` field.</div>"]
#[inline(always)]
pub fn timer_ovf(&mut self, n: u8) -> TIMER_OVF_W<INT_ENA_SPEC> {
#[allow(clippy::no_effect)]
[(); 4][n as usize];
TIMER_OVF_W::new(self, n)
}
#[doc = "Bit 0 - The interrupt enable bit for the TIMER0_OVF interrupt."]
#[inline(always)]
pub fn timer0_ovf(&mut self) -> TIMER_OVF_W<INT_ENA_SPEC> {
TIMER_OVF_W::new(self, 0)
}
#[doc = "Bit 1 - The interrupt enable bit for the TIMER1_OVF interrupt."]
#[inline(always)]
pub fn timer1_ovf(&mut self) -> TIMER_OVF_W<INT_ENA_SPEC> {
TIMER_OVF_W::new(self, 1)
}
#[doc = "Bit 2 - The interrupt enable bit for the TIMER2_OVF interrupt."]
#[inline(always)]
pub fn timer2_ovf(&mut self) -> TIMER_OVF_W<INT_ENA_SPEC> {
TIMER_OVF_W::new(self, 2)
}
#[doc = "Bit 3 - The interrupt enable bit for the TIMER3_OVF interrupt."]
#[inline(always)]
pub fn timer3_ovf(&mut self) -> TIMER_OVF_W<INT_ENA_SPEC> {
TIMER_OVF_W::new(self, 3)
}
#[doc = "The interrupt enable bit for the DUTY_CHNG_END_CH(0-7) interrupt."]
#[doc = ""]
#[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `DUTY_CHNG_END_CH0` field.</div>"]
#[inline(always)]
pub fn duty_chng_end_ch(&mut self, n: u8) -> DUTY_CHNG_END_CH_W<INT_ENA_SPEC> {
#[allow(clippy::no_effect)]
[(); 8][n as usize];
DUTY_CHNG_END_CH_W::new(self, n + 4)
}
#[doc = "Bit 4 - The interrupt enable bit for the DUTY_CHNG_END_CH0 interrupt."]
#[inline(always)]
pub fn duty_chng_end_ch0(&mut self) -> DUTY_CHNG_END_CH_W<INT_ENA_SPEC> {
DUTY_CHNG_END_CH_W::new(self, 4)
}
#[doc = "Bit 5 - The interrupt enable bit for the DUTY_CHNG_END_CH1 interrupt."]
#[inline(always)]
pub fn duty_chng_end_ch1(&mut self) -> DUTY_CHNG_END_CH_W<INT_ENA_SPEC> {
DUTY_CHNG_END_CH_W::new(self, 5)
}
#[doc = "Bit 6 - The interrupt enable bit for the DUTY_CHNG_END_CH2 interrupt."]
#[inline(always)]
pub fn duty_chng_end_ch2(&mut self) -> DUTY_CHNG_END_CH_W<INT_ENA_SPEC> {
DUTY_CHNG_END_CH_W::new(self, 6)
}
#[doc = "Bit 7 - The interrupt enable bit for the DUTY_CHNG_END_CH3 interrupt."]
#[inline(always)]
pub fn duty_chng_end_ch3(&mut self) -> DUTY_CHNG_END_CH_W<INT_ENA_SPEC> {
DUTY_CHNG_END_CH_W::new(self, 7)
}
#[doc = "Bit 8 - The interrupt enable bit for the DUTY_CHNG_END_CH4 interrupt."]
#[inline(always)]
pub fn duty_chng_end_ch4(&mut self) -> DUTY_CHNG_END_CH_W<INT_ENA_SPEC> {
DUTY_CHNG_END_CH_W::new(self, 8)
}
#[doc = "Bit 9 - The interrupt enable bit for the DUTY_CHNG_END_CH5 interrupt."]
#[inline(always)]
pub fn duty_chng_end_ch5(&mut self) -> DUTY_CHNG_END_CH_W<INT_ENA_SPEC> {
DUTY_CHNG_END_CH_W::new(self, 9)
}
#[doc = "Bit 10 - The interrupt enable bit for the DUTY_CHNG_END_CH6 interrupt."]
#[inline(always)]
pub fn duty_chng_end_ch6(&mut self) -> DUTY_CHNG_END_CH_W<INT_ENA_SPEC> {
DUTY_CHNG_END_CH_W::new(self, 10)
}
#[doc = "Bit 11 - The interrupt enable bit for the DUTY_CHNG_END_CH7 interrupt."]
#[inline(always)]
pub fn duty_chng_end_ch7(&mut self) -> DUTY_CHNG_END_CH_W<INT_ENA_SPEC> {
DUTY_CHNG_END_CH_W::new(self, 11)
}
#[doc = "The interrupt enable bit for the OVF_CNT_CH(0-7) interrupt."]
#[doc = ""]
#[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `OVF_CNT_CH0` field.</div>"]
#[inline(always)]
pub fn ovf_cnt_ch(&mut self, n: u8) -> OVF_CNT_CH_W<INT_ENA_SPEC> {
#[allow(clippy::no_effect)]
[(); 8][n as usize];
OVF_CNT_CH_W::new(self, n + 12)
}
#[doc = "Bit 12 - The interrupt enable bit for the OVF_CNT_CH0 interrupt."]
#[inline(always)]
pub fn ovf_cnt_ch0(&mut self) -> OVF_CNT_CH_W<INT_ENA_SPEC> {
OVF_CNT_CH_W::new(self, 12)
}
#[doc = "Bit 13 - The interrupt enable bit for the OVF_CNT_CH1 interrupt."]
#[inline(always)]
pub fn ovf_cnt_ch1(&mut self) -> OVF_CNT_CH_W<INT_ENA_SPEC> {
OVF_CNT_CH_W::new(self, 13)
}
#[doc = "Bit 14 - The interrupt enable bit for the OVF_CNT_CH2 interrupt."]
#[inline(always)]
pub fn ovf_cnt_ch2(&mut self) -> OVF_CNT_CH_W<INT_ENA_SPEC> {
OVF_CNT_CH_W::new(self, 14)
}
#[doc = "Bit 15 - The interrupt enable bit for the OVF_CNT_CH3 interrupt."]
#[inline(always)]
pub fn ovf_cnt_ch3(&mut self) -> OVF_CNT_CH_W<INT_ENA_SPEC> {
OVF_CNT_CH_W::new(self, 15)
}
#[doc = "Bit 16 - The interrupt enable bit for the OVF_CNT_CH4 interrupt."]
#[inline(always)]
pub fn ovf_cnt_ch4(&mut self) -> OVF_CNT_CH_W<INT_ENA_SPEC> {
OVF_CNT_CH_W::new(self, 16)
}
#[doc = "Bit 17 - The interrupt enable bit for the OVF_CNT_CH5 interrupt."]
#[inline(always)]
pub fn ovf_cnt_ch5(&mut self) -> OVF_CNT_CH_W<INT_ENA_SPEC> {
OVF_CNT_CH_W::new(self, 17)
}
#[doc = "Bit 18 - The interrupt enable bit for the OVF_CNT_CH6 interrupt."]
#[inline(always)]
pub fn ovf_cnt_ch6(&mut self) -> OVF_CNT_CH_W<INT_ENA_SPEC> {
OVF_CNT_CH_W::new(self, 18)
}
#[doc = "Bit 19 - The interrupt enable bit for the OVF_CNT_CH7 interrupt."]
#[inline(always)]
pub fn ovf_cnt_ch7(&mut self) -> OVF_CNT_CH_W<INT_ENA_SPEC> {
OVF_CNT_CH_W::new(self, 19)
}
}
#[doc = "Interrupt enable bits\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_ENA_SPEC;
impl crate::RegisterSpec for INT_ENA_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"]
impl crate::Readable for INT_ENA_SPEC {}
#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"]
impl crate::Writable for INT_ENA_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets INT_ENA to value 0"]
impl crate::Resettable for INT_ENA_SPEC {
const RESET_VALUE: u32 = 0;
}
vendor/esp32s3/src/ledc/int_raw.rs
Vendored
+336
View File
@@ -0,0 +1,336 @@
#[doc = "Register `INT_RAW` reader"]
pub type R = crate::R<INT_RAW_SPEC>;
#[doc = "Register `INT_RAW` writer"]
pub type W = crate::W<INT_RAW_SPEC>;
#[doc = "Field `TIMER_OVF(0-3)` reader - Triggered when the timer%s has reached its maximum counter value."]
pub type TIMER_OVF_R = crate::BitReader;
#[doc = "Field `TIMER_OVF(0-3)` writer - Triggered when the timer%s has reached its maximum counter value."]
pub type TIMER_OVF_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DUTY_CHNG_END_CH(0-7)` reader - Interrupt raw bit for channel %s. Triggered when the gradual change of duty has finished."]
pub type DUTY_CHNG_END_CH_R = crate::BitReader;
#[doc = "Field `DUTY_CHNG_END_CH(0-7)` writer - Interrupt raw bit for channel %s. Triggered when the gradual change of duty has finished."]
pub type DUTY_CHNG_END_CH_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `OVF_CNT_CH(0-7)` reader - Interrupt raw bit for channel %s. Triggered when the OVF_CNT has reached the value specified by LEDC.CHx.CONF0.OVF_NUM."]
pub type OVF_CNT_CH_R = crate::BitReader;
#[doc = "Field `OVF_CNT_CH(0-7)` writer - Interrupt raw bit for channel %s. Triggered when the OVF_CNT has reached the value specified by LEDC.CHx.CONF0.OVF_NUM."]
pub type OVF_CNT_CH_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Triggered when the timer(0-3) has reached its maximum counter value."]
#[doc = ""]
#[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_OVF` field.</div>"]
#[inline(always)]
pub fn timer_ovf(&self, n: u8) -> TIMER_OVF_R {
#[allow(clippy::no_effect)]
[(); 4][n as usize];
TIMER_OVF_R::new(((self.bits >> n) & 1) != 0)
}
#[doc = "Iterator for array of:"]
#[doc = "Triggered when the timer(0-3) has reached its maximum counter value."]
#[inline(always)]
pub fn timer_ovf_iter(&self) -> impl Iterator<Item = TIMER_OVF_R> + '_ {
(0..4).map(move |n| TIMER_OVF_R::new(((self.bits >> n) & 1) != 0))
}
#[doc = "Bit 0 - Triggered when the timer0 has reached its maximum counter value."]
#[inline(always)]
pub fn timer0_ovf(&self) -> TIMER_OVF_R {
TIMER_OVF_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Triggered when the timer1 has reached its maximum counter value."]
#[inline(always)]
pub fn timer1_ovf(&self) -> TIMER_OVF_R {
TIMER_OVF_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Triggered when the timer2 has reached its maximum counter value."]
#[inline(always)]
pub fn timer2_ovf(&self) -> TIMER_OVF_R {
TIMER_OVF_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Triggered when the timer3 has reached its maximum counter value."]
#[inline(always)]
pub fn timer3_ovf(&self) -> TIMER_OVF_R {
TIMER_OVF_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Interrupt raw bit for channel (0-7). Triggered when the gradual change of duty has finished."]
#[doc = ""]
#[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `DUTY_CHNG_END_CH0` field.</div>"]
#[inline(always)]
pub fn duty_chng_end_ch(&self, n: u8) -> DUTY_CHNG_END_CH_R {
#[allow(clippy::no_effect)]
[(); 8][n as usize];
DUTY_CHNG_END_CH_R::new(((self.bits >> (n + 4)) & 1) != 0)
}
#[doc = "Iterator for array of:"]
#[doc = "Interrupt raw bit for channel (0-7). Triggered when the gradual change of duty has finished."]
#[inline(always)]
pub fn duty_chng_end_ch_iter(&self) -> impl Iterator<Item = DUTY_CHNG_END_CH_R> + '_ {
(0..8).map(move |n| DUTY_CHNG_END_CH_R::new(((self.bits >> (n + 4)) & 1) != 0))
}
#[doc = "Bit 4 - Interrupt raw bit for channel 0. Triggered when the gradual change of duty has finished."]
#[inline(always)]
pub fn duty_chng_end_ch0(&self) -> DUTY_CHNG_END_CH_R {
DUTY_CHNG_END_CH_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Interrupt raw bit for channel 1. Triggered when the gradual change of duty has finished."]
#[inline(always)]
pub fn duty_chng_end_ch1(&self) -> DUTY_CHNG_END_CH_R {
DUTY_CHNG_END_CH_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Interrupt raw bit for channel 2. Triggered when the gradual change of duty has finished."]
#[inline(always)]
pub fn duty_chng_end_ch2(&self) -> DUTY_CHNG_END_CH_R {
DUTY_CHNG_END_CH_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Interrupt raw bit for channel 3. Triggered when the gradual change of duty has finished."]
#[inline(always)]
pub fn duty_chng_end_ch3(&self) -> DUTY_CHNG_END_CH_R {
DUTY_CHNG_END_CH_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Interrupt raw bit for channel 4. Triggered when the gradual change of duty has finished."]
#[inline(always)]
pub fn duty_chng_end_ch4(&self) -> DUTY_CHNG_END_CH_R {
DUTY_CHNG_END_CH_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Interrupt raw bit for channel 5. Triggered when the gradual change of duty has finished."]
#[inline(always)]
pub fn duty_chng_end_ch5(&self) -> DUTY_CHNG_END_CH_R {
DUTY_CHNG_END_CH_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Interrupt raw bit for channel 6. Triggered when the gradual change of duty has finished."]
#[inline(always)]
pub fn duty_chng_end_ch6(&self) -> DUTY_CHNG_END_CH_R {
DUTY_CHNG_END_CH_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Interrupt raw bit for channel 7. Triggered when the gradual change of duty has finished."]
#[inline(always)]
pub fn duty_chng_end_ch7(&self) -> DUTY_CHNG_END_CH_R {
DUTY_CHNG_END_CH_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "Interrupt raw bit for channel (0-7). Triggered when the OVF_CNT has reached the value specified by LEDC.CHx.CONF0.OVF_NUM."]
#[doc = ""]
#[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `OVF_CNT_CH0` field.</div>"]
#[inline(always)]
pub fn ovf_cnt_ch(&self, n: u8) -> OVF_CNT_CH_R {
#[allow(clippy::no_effect)]
[(); 8][n as usize];
OVF_CNT_CH_R::new(((self.bits >> (n + 12)) & 1) != 0)
}
#[doc = "Iterator for array of:"]
#[doc = "Interrupt raw bit for channel (0-7). Triggered when the OVF_CNT has reached the value specified by LEDC.CHx.CONF0.OVF_NUM."]
#[inline(always)]
pub fn ovf_cnt_ch_iter(&self) -> impl Iterator<Item = OVF_CNT_CH_R> + '_ {
(0..8).map(move |n| OVF_CNT_CH_R::new(((self.bits >> (n + 12)) & 1) != 0))
}
#[doc = "Bit 12 - Interrupt raw bit for channel 0. Triggered when the OVF_CNT has reached the value specified by LEDC.CHx.CONF0.OVF_NUM."]
#[inline(always)]
pub fn ovf_cnt_ch0(&self) -> OVF_CNT_CH_R {
OVF_CNT_CH_R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - Interrupt raw bit for channel 1. Triggered when the OVF_CNT has reached the value specified by LEDC.CHx.CONF0.OVF_NUM."]
#[inline(always)]
pub fn ovf_cnt_ch1(&self) -> OVF_CNT_CH_R {
OVF_CNT_CH_R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - Interrupt raw bit for channel 2. Triggered when the OVF_CNT has reached the value specified by LEDC.CHx.CONF0.OVF_NUM."]
#[inline(always)]
pub fn ovf_cnt_ch2(&self) -> OVF_CNT_CH_R {
OVF_CNT_CH_R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - Interrupt raw bit for channel 3. Triggered when the OVF_CNT has reached the value specified by LEDC.CHx.CONF0.OVF_NUM."]
#[inline(always)]
pub fn ovf_cnt_ch3(&self) -> OVF_CNT_CH_R {
OVF_CNT_CH_R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 16 - Interrupt raw bit for channel 4. Triggered when the OVF_CNT has reached the value specified by LEDC.CHx.CONF0.OVF_NUM."]
#[inline(always)]
pub fn ovf_cnt_ch4(&self) -> OVF_CNT_CH_R {
OVF_CNT_CH_R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17 - Interrupt raw bit for channel 5. Triggered when the OVF_CNT has reached the value specified by LEDC.CHx.CONF0.OVF_NUM."]
#[inline(always)]
pub fn ovf_cnt_ch5(&self) -> OVF_CNT_CH_R {
OVF_CNT_CH_R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18 - Interrupt raw bit for channel 6. Triggered when the OVF_CNT has reached the value specified by LEDC.CHx.CONF0.OVF_NUM."]
#[inline(always)]
pub fn ovf_cnt_ch6(&self) -> OVF_CNT_CH_R {
OVF_CNT_CH_R::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19 - Interrupt raw bit for channel 7. Triggered when the OVF_CNT has reached the value specified by LEDC.CHx.CONF0.OVF_NUM."]
#[inline(always)]
pub fn ovf_cnt_ch7(&self) -> OVF_CNT_CH_R {
OVF_CNT_CH_R::new(((self.bits >> 19) & 1) != 0)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("INT_RAW")
.field("timer0_ovf", &self.timer0_ovf())
.field("timer1_ovf", &self.timer1_ovf())
.field("timer2_ovf", &self.timer2_ovf())
.field("timer3_ovf", &self.timer3_ovf())
.field("duty_chng_end_ch0", &self.duty_chng_end_ch0())
.field("duty_chng_end_ch1", &self.duty_chng_end_ch1())
.field("duty_chng_end_ch2", &self.duty_chng_end_ch2())
.field("duty_chng_end_ch3", &self.duty_chng_end_ch3())
.field("duty_chng_end_ch4", &self.duty_chng_end_ch4())
.field("duty_chng_end_ch5", &self.duty_chng_end_ch5())
.field("duty_chng_end_ch6", &self.duty_chng_end_ch6())
.field("duty_chng_end_ch7", &self.duty_chng_end_ch7())
.field("ovf_cnt_ch0", &self.ovf_cnt_ch0())
.field("ovf_cnt_ch1", &self.ovf_cnt_ch1())
.field("ovf_cnt_ch2", &self.ovf_cnt_ch2())
.field("ovf_cnt_ch3", &self.ovf_cnt_ch3())
.field("ovf_cnt_ch4", &self.ovf_cnt_ch4())
.field("ovf_cnt_ch5", &self.ovf_cnt_ch5())
.field("ovf_cnt_ch6", &self.ovf_cnt_ch6())
.field("ovf_cnt_ch7", &self.ovf_cnt_ch7())
.finish()
}
}
impl W {
#[doc = "Triggered when the timer(0-3) has reached its maximum counter value."]
#[doc = ""]
#[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_OVF` field.</div>"]
#[inline(always)]
pub fn timer_ovf(&mut self, n: u8) -> TIMER_OVF_W<INT_RAW_SPEC> {
#[allow(clippy::no_effect)]
[(); 4][n as usize];
TIMER_OVF_W::new(self, n)
}
#[doc = "Bit 0 - Triggered when the timer0 has reached its maximum counter value."]
#[inline(always)]
pub fn timer0_ovf(&mut self) -> TIMER_OVF_W<INT_RAW_SPEC> {
TIMER_OVF_W::new(self, 0)
}
#[doc = "Bit 1 - Triggered when the timer1 has reached its maximum counter value."]
#[inline(always)]
pub fn timer1_ovf(&mut self) -> TIMER_OVF_W<INT_RAW_SPEC> {
TIMER_OVF_W::new(self, 1)
}
#[doc = "Bit 2 - Triggered when the timer2 has reached its maximum counter value."]
#[inline(always)]
pub fn timer2_ovf(&mut self) -> TIMER_OVF_W<INT_RAW_SPEC> {
TIMER_OVF_W::new(self, 2)
}
#[doc = "Bit 3 - Triggered when the timer3 has reached its maximum counter value."]
#[inline(always)]
pub fn timer3_ovf(&mut self) -> TIMER_OVF_W<INT_RAW_SPEC> {
TIMER_OVF_W::new(self, 3)
}
#[doc = "Interrupt raw bit for channel (0-7). Triggered when the gradual change of duty has finished."]
#[doc = ""]
#[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `DUTY_CHNG_END_CH0` field.</div>"]
#[inline(always)]
pub fn duty_chng_end_ch(&mut self, n: u8) -> DUTY_CHNG_END_CH_W<INT_RAW_SPEC> {
#[allow(clippy::no_effect)]
[(); 8][n as usize];
DUTY_CHNG_END_CH_W::new(self, n + 4)
}
#[doc = "Bit 4 - Interrupt raw bit for channel 0. Triggered when the gradual change of duty has finished."]
#[inline(always)]
pub fn duty_chng_end_ch0(&mut self) -> DUTY_CHNG_END_CH_W<INT_RAW_SPEC> {
DUTY_CHNG_END_CH_W::new(self, 4)
}
#[doc = "Bit 5 - Interrupt raw bit for channel 1. Triggered when the gradual change of duty has finished."]
#[inline(always)]
pub fn duty_chng_end_ch1(&mut self) -> DUTY_CHNG_END_CH_W<INT_RAW_SPEC> {
DUTY_CHNG_END_CH_W::new(self, 5)
}
#[doc = "Bit 6 - Interrupt raw bit for channel 2. Triggered when the gradual change of duty has finished."]
#[inline(always)]
pub fn duty_chng_end_ch2(&mut self) -> DUTY_CHNG_END_CH_W<INT_RAW_SPEC> {
DUTY_CHNG_END_CH_W::new(self, 6)
}
#[doc = "Bit 7 - Interrupt raw bit for channel 3. Triggered when the gradual change of duty has finished."]
#[inline(always)]
pub fn duty_chng_end_ch3(&mut self) -> DUTY_CHNG_END_CH_W<INT_RAW_SPEC> {
DUTY_CHNG_END_CH_W::new(self, 7)
}
#[doc = "Bit 8 - Interrupt raw bit for channel 4. Triggered when the gradual change of duty has finished."]
#[inline(always)]
pub fn duty_chng_end_ch4(&mut self) -> DUTY_CHNG_END_CH_W<INT_RAW_SPEC> {
DUTY_CHNG_END_CH_W::new(self, 8)
}
#[doc = "Bit 9 - Interrupt raw bit for channel 5. Triggered when the gradual change of duty has finished."]
#[inline(always)]
pub fn duty_chng_end_ch5(&mut self) -> DUTY_CHNG_END_CH_W<INT_RAW_SPEC> {
DUTY_CHNG_END_CH_W::new(self, 9)
}
#[doc = "Bit 10 - Interrupt raw bit for channel 6. Triggered when the gradual change of duty has finished."]
#[inline(always)]
pub fn duty_chng_end_ch6(&mut self) -> DUTY_CHNG_END_CH_W<INT_RAW_SPEC> {
DUTY_CHNG_END_CH_W::new(self, 10)
}
#[doc = "Bit 11 - Interrupt raw bit for channel 7. Triggered when the gradual change of duty has finished."]
#[inline(always)]
pub fn duty_chng_end_ch7(&mut self) -> DUTY_CHNG_END_CH_W<INT_RAW_SPEC> {
DUTY_CHNG_END_CH_W::new(self, 11)
}
#[doc = "Interrupt raw bit for channel (0-7). Triggered when the OVF_CNT has reached the value specified by LEDC.CHx.CONF0.OVF_NUM."]
#[doc = ""]
#[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `OVF_CNT_CH0` field.</div>"]
#[inline(always)]
pub fn ovf_cnt_ch(&mut self, n: u8) -> OVF_CNT_CH_W<INT_RAW_SPEC> {
#[allow(clippy::no_effect)]
[(); 8][n as usize];
OVF_CNT_CH_W::new(self, n + 12)
}
#[doc = "Bit 12 - Interrupt raw bit for channel 0. Triggered when the OVF_CNT has reached the value specified by LEDC.CHx.CONF0.OVF_NUM."]
#[inline(always)]
pub fn ovf_cnt_ch0(&mut self) -> OVF_CNT_CH_W<INT_RAW_SPEC> {
OVF_CNT_CH_W::new(self, 12)
}
#[doc = "Bit 13 - Interrupt raw bit for channel 1. Triggered when the OVF_CNT has reached the value specified by LEDC.CHx.CONF0.OVF_NUM."]
#[inline(always)]
pub fn ovf_cnt_ch1(&mut self) -> OVF_CNT_CH_W<INT_RAW_SPEC> {
OVF_CNT_CH_W::new(self, 13)
}
#[doc = "Bit 14 - Interrupt raw bit for channel 2. Triggered when the OVF_CNT has reached the value specified by LEDC.CHx.CONF0.OVF_NUM."]
#[inline(always)]
pub fn ovf_cnt_ch2(&mut self) -> OVF_CNT_CH_W<INT_RAW_SPEC> {
OVF_CNT_CH_W::new(self, 14)
}
#[doc = "Bit 15 - Interrupt raw bit for channel 3. Triggered when the OVF_CNT has reached the value specified by LEDC.CHx.CONF0.OVF_NUM."]
#[inline(always)]
pub fn ovf_cnt_ch3(&mut self) -> OVF_CNT_CH_W<INT_RAW_SPEC> {
OVF_CNT_CH_W::new(self, 15)
}
#[doc = "Bit 16 - Interrupt raw bit for channel 4. Triggered when the OVF_CNT has reached the value specified by LEDC.CHx.CONF0.OVF_NUM."]
#[inline(always)]
pub fn ovf_cnt_ch4(&mut self) -> OVF_CNT_CH_W<INT_RAW_SPEC> {
OVF_CNT_CH_W::new(self, 16)
}
#[doc = "Bit 17 - Interrupt raw bit for channel 5. Triggered when the OVF_CNT has reached the value specified by LEDC.CHx.CONF0.OVF_NUM."]
#[inline(always)]
pub fn ovf_cnt_ch5(&mut self) -> OVF_CNT_CH_W<INT_RAW_SPEC> {
OVF_CNT_CH_W::new(self, 17)
}
#[doc = "Bit 18 - Interrupt raw bit for channel 6. Triggered when the OVF_CNT has reached the value specified by LEDC.CHx.CONF0.OVF_NUM."]
#[inline(always)]
pub fn ovf_cnt_ch6(&mut self) -> OVF_CNT_CH_W<INT_RAW_SPEC> {
OVF_CNT_CH_W::new(self, 18)
}
#[doc = "Bit 19 - Interrupt raw bit for channel 7. Triggered when the OVF_CNT has reached the value specified by LEDC.CHx.CONF0.OVF_NUM."]
#[inline(always)]
pub fn ovf_cnt_ch7(&mut self) -> OVF_CNT_CH_W<INT_RAW_SPEC> {
OVF_CNT_CH_W::new(self, 19)
}
}
#[doc = "Raw interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`int_raw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_raw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_RAW_SPEC;
impl crate::RegisterSpec for INT_RAW_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"]
impl crate::Readable for INT_RAW_SPEC {}
#[doc = "`write(|w| ..)` method takes [`int_raw::W`](W) writer structure"]
impl crate::Writable for INT_RAW_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets INT_RAW to value 0"]
impl crate::Resettable for INT_RAW_SPEC {
const RESET_VALUE: u32 = 0;
}
vendor/esp32s3/src/ledc/int_st.rs
Vendored
+193
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#[doc = "Register `INT_ST` reader"]
pub type R = crate::R<INT_ST_SPEC>;
#[doc = "Field `TIMER_OVF(0-3)` reader - This is the masked interrupt status bit for the TIMER%s_OVF interrupt when LEDC.INT_ENA.TIMERx_OVF is set to 1."]
pub type TIMER_OVF_R = crate::BitReader;
#[doc = "Field `DUTY_CHNG_END_CH(0-7)` reader - This is the masked interrupt status bit for the DUTY_CHNG_END_CH%s interrupt when LEDC.INT_ENA.DUTY_CHNG_END_CHx is set to 1."]
pub type DUTY_CHNG_END_CH_R = crate::BitReader;
#[doc = "Field `OVF_CNT_CH(0-7)` reader - This is the masked interrupt status bit for the LEDC.INT_RAW.OVF_CNT_CH%s interrupt when LEDC.INT_ENA.OVF_CNT_CHx is set to 1."]
pub type OVF_CNT_CH_R = crate::BitReader;
impl R {
#[doc = "This is the masked interrupt status bit for the TIMER(0-3)_OVF interrupt when LEDC.INT_ENA.TIMERx_OVF is set to 1."]
#[doc = ""]
#[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TIMER0_OVF` field.</div>"]
#[inline(always)]
pub fn timer_ovf(&self, n: u8) -> TIMER_OVF_R {
#[allow(clippy::no_effect)]
[(); 4][n as usize];
TIMER_OVF_R::new(((self.bits >> n) & 1) != 0)
}
#[doc = "Iterator for array of:"]
#[doc = "This is the masked interrupt status bit for the TIMER(0-3)_OVF interrupt when LEDC.INT_ENA.TIMERx_OVF is set to 1."]
#[inline(always)]
pub fn timer_ovf_iter(&self) -> impl Iterator<Item = TIMER_OVF_R> + '_ {
(0..4).map(move |n| TIMER_OVF_R::new(((self.bits >> n) & 1) != 0))
}
#[doc = "Bit 0 - This is the masked interrupt status bit for the TIMER0_OVF interrupt when LEDC.INT_ENA.TIMERx_OVF is set to 1."]
#[inline(always)]
pub fn timer0_ovf(&self) -> TIMER_OVF_R {
TIMER_OVF_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - This is the masked interrupt status bit for the TIMER1_OVF interrupt when LEDC.INT_ENA.TIMERx_OVF is set to 1."]
#[inline(always)]
pub fn timer1_ovf(&self) -> TIMER_OVF_R {
TIMER_OVF_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - This is the masked interrupt status bit for the TIMER2_OVF interrupt when LEDC.INT_ENA.TIMERx_OVF is set to 1."]
#[inline(always)]
pub fn timer2_ovf(&self) -> TIMER_OVF_R {
TIMER_OVF_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - This is the masked interrupt status bit for the TIMER3_OVF interrupt when LEDC.INT_ENA.TIMERx_OVF is set to 1."]
#[inline(always)]
pub fn timer3_ovf(&self) -> TIMER_OVF_R {
TIMER_OVF_R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "This is the masked interrupt status bit for the DUTY_CHNG_END_CH(0-7) interrupt when LEDC.INT_ENA.DUTY_CHNG_END_CHx is set to 1."]
#[doc = ""]
#[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `DUTY_CHNG_END_CH0` field.</div>"]
#[inline(always)]
pub fn duty_chng_end_ch(&self, n: u8) -> DUTY_CHNG_END_CH_R {
#[allow(clippy::no_effect)]
[(); 8][n as usize];
DUTY_CHNG_END_CH_R::new(((self.bits >> (n + 4)) & 1) != 0)
}
#[doc = "Iterator for array of:"]
#[doc = "This is the masked interrupt status bit for the DUTY_CHNG_END_CH(0-7) interrupt when LEDC.INT_ENA.DUTY_CHNG_END_CHx is set to 1."]
#[inline(always)]
pub fn duty_chng_end_ch_iter(&self) -> impl Iterator<Item = DUTY_CHNG_END_CH_R> + '_ {
(0..8).map(move |n| DUTY_CHNG_END_CH_R::new(((self.bits >> (n + 4)) & 1) != 0))
}
#[doc = "Bit 4 - This is the masked interrupt status bit for the DUTY_CHNG_END_CH0 interrupt when LEDC.INT_ENA.DUTY_CHNG_END_CHx is set to 1."]
#[inline(always)]
pub fn duty_chng_end_ch0(&self) -> DUTY_CHNG_END_CH_R {
DUTY_CHNG_END_CH_R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - This is the masked interrupt status bit for the DUTY_CHNG_END_CH1 interrupt when LEDC.INT_ENA.DUTY_CHNG_END_CHx is set to 1."]
#[inline(always)]
pub fn duty_chng_end_ch1(&self) -> DUTY_CHNG_END_CH_R {
DUTY_CHNG_END_CH_R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - This is the masked interrupt status bit for the DUTY_CHNG_END_CH2 interrupt when LEDC.INT_ENA.DUTY_CHNG_END_CHx is set to 1."]
#[inline(always)]
pub fn duty_chng_end_ch2(&self) -> DUTY_CHNG_END_CH_R {
DUTY_CHNG_END_CH_R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - This is the masked interrupt status bit for the DUTY_CHNG_END_CH3 interrupt when LEDC.INT_ENA.DUTY_CHNG_END_CHx is set to 1."]
#[inline(always)]
pub fn duty_chng_end_ch3(&self) -> DUTY_CHNG_END_CH_R {
DUTY_CHNG_END_CH_R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - This is the masked interrupt status bit for the DUTY_CHNG_END_CH4 interrupt when LEDC.INT_ENA.DUTY_CHNG_END_CHx is set to 1."]
#[inline(always)]
pub fn duty_chng_end_ch4(&self) -> DUTY_CHNG_END_CH_R {
DUTY_CHNG_END_CH_R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - This is the masked interrupt status bit for the DUTY_CHNG_END_CH5 interrupt when LEDC.INT_ENA.DUTY_CHNG_END_CHx is set to 1."]
#[inline(always)]
pub fn duty_chng_end_ch5(&self) -> DUTY_CHNG_END_CH_R {
DUTY_CHNG_END_CH_R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - This is the masked interrupt status bit for the DUTY_CHNG_END_CH6 interrupt when LEDC.INT_ENA.DUTY_CHNG_END_CHx is set to 1."]
#[inline(always)]
pub fn duty_chng_end_ch6(&self) -> DUTY_CHNG_END_CH_R {
DUTY_CHNG_END_CH_R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - This is the masked interrupt status bit for the DUTY_CHNG_END_CH7 interrupt when LEDC.INT_ENA.DUTY_CHNG_END_CHx is set to 1."]
#[inline(always)]
pub fn duty_chng_end_ch7(&self) -> DUTY_CHNG_END_CH_R {
DUTY_CHNG_END_CH_R::new(((self.bits >> 11) & 1) != 0)
}
#[doc = "This is the masked interrupt status bit for the LEDC.INT_RAW.OVF_CNT_CH(0-7) interrupt when LEDC.INT_ENA.OVF_CNT_CHx is set to 1."]
#[doc = ""]
#[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `OVF_CNT_CH0` field.</div>"]
#[inline(always)]
pub fn ovf_cnt_ch(&self, n: u8) -> OVF_CNT_CH_R {
#[allow(clippy::no_effect)]
[(); 8][n as usize];
OVF_CNT_CH_R::new(((self.bits >> (n + 12)) & 1) != 0)
}
#[doc = "Iterator for array of:"]
#[doc = "This is the masked interrupt status bit for the LEDC.INT_RAW.OVF_CNT_CH(0-7) interrupt when LEDC.INT_ENA.OVF_CNT_CHx is set to 1."]
#[inline(always)]
pub fn ovf_cnt_ch_iter(&self) -> impl Iterator<Item = OVF_CNT_CH_R> + '_ {
(0..8).map(move |n| OVF_CNT_CH_R::new(((self.bits >> (n + 12)) & 1) != 0))
}
#[doc = "Bit 12 - This is the masked interrupt status bit for the LEDC.INT_RAW.OVF_CNT_CH0 interrupt when LEDC.INT_ENA.OVF_CNT_CHx is set to 1."]
#[inline(always)]
pub fn ovf_cnt_ch0(&self) -> OVF_CNT_CH_R {
OVF_CNT_CH_R::new(((self.bits >> 12) & 1) != 0)
}
#[doc = "Bit 13 - This is the masked interrupt status bit for the LEDC.INT_RAW.OVF_CNT_CH1 interrupt when LEDC.INT_ENA.OVF_CNT_CHx is set to 1."]
#[inline(always)]
pub fn ovf_cnt_ch1(&self) -> OVF_CNT_CH_R {
OVF_CNT_CH_R::new(((self.bits >> 13) & 1) != 0)
}
#[doc = "Bit 14 - This is the masked interrupt status bit for the LEDC.INT_RAW.OVF_CNT_CH2 interrupt when LEDC.INT_ENA.OVF_CNT_CHx is set to 1."]
#[inline(always)]
pub fn ovf_cnt_ch2(&self) -> OVF_CNT_CH_R {
OVF_CNT_CH_R::new(((self.bits >> 14) & 1) != 0)
}
#[doc = "Bit 15 - This is the masked interrupt status bit for the LEDC.INT_RAW.OVF_CNT_CH3 interrupt when LEDC.INT_ENA.OVF_CNT_CHx is set to 1."]
#[inline(always)]
pub fn ovf_cnt_ch3(&self) -> OVF_CNT_CH_R {
OVF_CNT_CH_R::new(((self.bits >> 15) & 1) != 0)
}
#[doc = "Bit 16 - This is the masked interrupt status bit for the LEDC.INT_RAW.OVF_CNT_CH4 interrupt when LEDC.INT_ENA.OVF_CNT_CHx is set to 1."]
#[inline(always)]
pub fn ovf_cnt_ch4(&self) -> OVF_CNT_CH_R {
OVF_CNT_CH_R::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bit 17 - This is the masked interrupt status bit for the LEDC.INT_RAW.OVF_CNT_CH5 interrupt when LEDC.INT_ENA.OVF_CNT_CHx is set to 1."]
#[inline(always)]
pub fn ovf_cnt_ch5(&self) -> OVF_CNT_CH_R {
OVF_CNT_CH_R::new(((self.bits >> 17) & 1) != 0)
}
#[doc = "Bit 18 - This is the masked interrupt status bit for the LEDC.INT_RAW.OVF_CNT_CH6 interrupt when LEDC.INT_ENA.OVF_CNT_CHx is set to 1."]
#[inline(always)]
pub fn ovf_cnt_ch6(&self) -> OVF_CNT_CH_R {
OVF_CNT_CH_R::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19 - This is the masked interrupt status bit for the LEDC.INT_RAW.OVF_CNT_CH7 interrupt when LEDC.INT_ENA.OVF_CNT_CHx is set to 1."]
#[inline(always)]
pub fn ovf_cnt_ch7(&self) -> OVF_CNT_CH_R {
OVF_CNT_CH_R::new(((self.bits >> 19) & 1) != 0)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("INT_ST")
.field("timer0_ovf", &self.timer0_ovf())
.field("timer1_ovf", &self.timer1_ovf())
.field("timer2_ovf", &self.timer2_ovf())
.field("timer3_ovf", &self.timer3_ovf())
.field("duty_chng_end_ch0", &self.duty_chng_end_ch0())
.field("duty_chng_end_ch1", &self.duty_chng_end_ch1())
.field("duty_chng_end_ch2", &self.duty_chng_end_ch2())
.field("duty_chng_end_ch3", &self.duty_chng_end_ch3())
.field("duty_chng_end_ch4", &self.duty_chng_end_ch4())
.field("duty_chng_end_ch5", &self.duty_chng_end_ch5())
.field("duty_chng_end_ch6", &self.duty_chng_end_ch6())
.field("duty_chng_end_ch7", &self.duty_chng_end_ch7())
.field("ovf_cnt_ch0", &self.ovf_cnt_ch0())
.field("ovf_cnt_ch1", &self.ovf_cnt_ch1())
.field("ovf_cnt_ch2", &self.ovf_cnt_ch2())
.field("ovf_cnt_ch3", &self.ovf_cnt_ch3())
.field("ovf_cnt_ch4", &self.ovf_cnt_ch4())
.field("ovf_cnt_ch5", &self.ovf_cnt_ch5())
.field("ovf_cnt_ch6", &self.ovf_cnt_ch6())
.field("ovf_cnt_ch7", &self.ovf_cnt_ch7())
.finish()
}
}
#[doc = "Masked interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_ST_SPEC;
impl crate::RegisterSpec for INT_ST_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`int_st::R`](R) reader structure"]
impl crate::Readable for INT_ST_SPEC {}
#[doc = "`reset()` method sets INT_ST to value 0"]
impl crate::Resettable for INT_ST_SPEC {
const RESET_VALUE: u32 = 0;
}
vendor/esp32s3/src/ledc/timer.rs
Vendored
+27
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@@ -0,0 +1,27 @@
#[repr(C)]
#[cfg_attr(feature = "impl-register-debug", derive(Debug))]
#[doc = "Cluster TIMER%s, containing TIMER?_CONF, TIMER?_VALUE"]
pub struct TIMER {
conf: CONF,
value: VALUE,
}
impl TIMER {
#[doc = "0x00 - Timer 0 configuration"]
#[inline(always)]
pub const fn conf(&self) -> &CONF {
&self.conf
}
#[doc = "0x04 - Timer 0 current counter value"]
#[inline(always)]
pub const fn value(&self) -> &VALUE {
&self.value
}
}
#[doc = "CONF (rw) register accessor: Timer 0 configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@conf`] module"]
pub type CONF = crate::Reg<conf::CONF_SPEC>;
#[doc = "Timer 0 configuration"]
pub mod conf;
#[doc = "VALUE (r) register accessor: Timer 0 current counter value\n\nYou can [`read`](crate::Reg::read) this register and get [`value::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@value`] module"]
pub type VALUE = crate::Reg<value::VALUE_SPEC>;
#[doc = "Timer 0 current counter value"]
pub mod value;
vendor/esp32s3/src/ledc/timer/conf.rs
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#[doc = "Register `CONF` reader"]
pub type R = crate::R<CONF_SPEC>;
#[doc = "Register `CONF` writer"]
pub type W = crate::W<CONF_SPEC>;
#[doc = "Field `DUTY_RES` reader - This register is used to control the range of the counter in timer %s."]
pub type DUTY_RES_R = crate::FieldReader;
#[doc = "Field `DUTY_RES` writer - This register is used to control the range of the counter in timer %s."]
pub type DUTY_RES_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `CLK_DIV` reader - This register is used to configure the divisor for the divider in timer %s. The least significant eight bits represent the fractional part."]
pub type CLK_DIV_R = crate::FieldReader<u32>;
#[doc = "Field `CLK_DIV` writer - This register is used to configure the divisor for the divider in timer %s. The least significant eight bits represent the fractional part."]
pub type CLK_DIV_W<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>;
#[doc = "Field `PAUSE` reader - This bit is used to suspend the counter in timer %s."]
pub type PAUSE_R = crate::BitReader;
#[doc = "Field `PAUSE` writer - This bit is used to suspend the counter in timer %s."]
pub type PAUSE_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `RST` reader - This bit is used to reset timer %s. The counter will show 0 after reset."]
pub type RST_R = crate::BitReader;
#[doc = "Field `RST` writer - This bit is used to reset timer %s. The counter will show 0 after reset."]
pub type RST_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TICK_SEL` reader - This bit is used to select clock for timer %s. When this bit is set to 1 LEDC_APB_CLK_SEL\\[1:0\\] should be 1, otherwise the timer clock may be not accurate. 1'h0: SLOW_CLK 1'h1: REF_TICK"]
pub type TICK_SEL_R = crate::BitReader;
#[doc = "Field `TICK_SEL` writer - This bit is used to select clock for timer %s. When this bit is set to 1 LEDC_APB_CLK_SEL\\[1:0\\] should be 1, otherwise the timer clock may be not accurate. 1'h0: SLOW_CLK 1'h1: REF_TICK"]
pub type TICK_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `PARA_UP` writer - Set this bit to update LEDC_CLK_DIV_TIMER%s and LEDC_TIMER%s_DUTY_RES."]
pub type PARA_UP_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:3 - This register is used to control the range of the counter in timer %s."]
#[inline(always)]
pub fn duty_res(&self) -> DUTY_RES_R {
DUTY_RES_R::new((self.bits & 0x0f) as u8)
}
#[doc = "Bits 4:21 - This register is used to configure the divisor for the divider in timer %s. The least significant eight bits represent the fractional part."]
#[inline(always)]
pub fn clk_div(&self) -> CLK_DIV_R {
CLK_DIV_R::new((self.bits >> 4) & 0x0003_ffff)
}
#[doc = "Bit 22 - This bit is used to suspend the counter in timer %s."]
#[inline(always)]
pub fn pause(&self) -> PAUSE_R {
PAUSE_R::new(((self.bits >> 22) & 1) != 0)
}
#[doc = "Bit 23 - This bit is used to reset timer %s. The counter will show 0 after reset."]
#[inline(always)]
pub fn rst(&self) -> RST_R {
RST_R::new(((self.bits >> 23) & 1) != 0)
}
#[doc = "Bit 24 - This bit is used to select clock for timer %s. When this bit is set to 1 LEDC_APB_CLK_SEL\\[1:0\\] should be 1, otherwise the timer clock may be not accurate. 1'h0: SLOW_CLK 1'h1: REF_TICK"]
#[inline(always)]
pub fn tick_sel(&self) -> TICK_SEL_R {
TICK_SEL_R::new(((self.bits >> 24) & 1) != 0)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CONF")
.field("duty_res", &self.duty_res())
.field("clk_div", &self.clk_div())
.field("pause", &self.pause())
.field("rst", &self.rst())
.field("tick_sel", &self.tick_sel())
.finish()
}
}
impl W {
#[doc = "Bits 0:3 - This register is used to control the range of the counter in timer %s."]
#[inline(always)]
pub fn duty_res(&mut self) -> DUTY_RES_W<CONF_SPEC> {
DUTY_RES_W::new(self, 0)
}
#[doc = "Bits 4:21 - This register is used to configure the divisor for the divider in timer %s. The least significant eight bits represent the fractional part."]
#[inline(always)]
pub fn clk_div(&mut self) -> CLK_DIV_W<CONF_SPEC> {
CLK_DIV_W::new(self, 4)
}
#[doc = "Bit 22 - This bit is used to suspend the counter in timer %s."]
#[inline(always)]
pub fn pause(&mut self) -> PAUSE_W<CONF_SPEC> {
PAUSE_W::new(self, 22)
}
#[doc = "Bit 23 - This bit is used to reset timer %s. The counter will show 0 after reset."]
#[inline(always)]
pub fn rst(&mut self) -> RST_W<CONF_SPEC> {
RST_W::new(self, 23)
}
#[doc = "Bit 24 - This bit is used to select clock for timer %s. When this bit is set to 1 LEDC_APB_CLK_SEL\\[1:0\\] should be 1, otherwise the timer clock may be not accurate. 1'h0: SLOW_CLK 1'h1: REF_TICK"]
#[inline(always)]
pub fn tick_sel(&mut self) -> TICK_SEL_W<CONF_SPEC> {
TICK_SEL_W::new(self, 24)
}
#[doc = "Bit 25 - Set this bit to update LEDC_CLK_DIV_TIMER%s and LEDC_TIMER%s_DUTY_RES."]
#[inline(always)]
pub fn para_up(&mut self) -> PARA_UP_W<CONF_SPEC> {
PARA_UP_W::new(self, 25)
}
}
#[doc = "Timer 0 configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CONF_SPEC;
impl crate::RegisterSpec for CONF_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`conf::R`](R) reader structure"]
impl crate::Readable for CONF_SPEC {}
#[doc = "`write(|w| ..)` method takes [`conf::W`](W) writer structure"]
impl crate::Writable for CONF_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CONF to value 0x0080_0000"]
impl crate::Resettable for CONF_SPEC {
const RESET_VALUE: u32 = 0x0080_0000;
}
vendor/esp32s3/src/ledc/timer/value.rs
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#[doc = "Register `VALUE` reader"]
pub type R = crate::R<VALUE_SPEC>;
#[doc = "Field `CNT` reader - This register stores the current counter value of timer %s."]
pub type CNT_R = crate::FieldReader<u16>;
impl R {
#[doc = "Bits 0:13 - This register stores the current counter value of timer %s."]
#[inline(always)]
pub fn cnt(&self) -> CNT_R {
CNT_R::new((self.bits & 0x3fff) as u16)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("VALUE").field("cnt", &self.cnt()).finish()
}
}
#[doc = "Timer 0 current counter value\n\nYou can [`read`](crate::Reg::read) this register and get [`value::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct VALUE_SPEC;
impl crate::RegisterSpec for VALUE_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`value::R`](R) reader structure"]
impl crate::Readable for VALUE_SPEC {}
#[doc = "`reset()` method sets VALUE to value 0"]
impl crate::Resettable for VALUE_SPEC {
const RESET_VALUE: u32 = 0;
}