feat: add display UI with splash screen, dashboard, and RSSI sparkline

Implement full SSD1306 OLED display support:
- Splash screen on boot (1.5s) with project name, version, board
- Dashboard showing radio state, config, counters, RSSI/SNR
- RSSI history sparkline (64-sample ring buffer, 2px-wide bars)
- DisplayOn/DisplayOff host commands routed via dedicated channel
- Pure render functions against generic DrawTarget (no hardware coupling)
- Display on/off control bypasses radio task entirely

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>

vendor/esp32s3/src/mcpwm0/cap_ch.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `CAP_CH%s` reader"]
+pub type R = crate::R<CAP_CH_SPEC>;
+#[doc = "Field `VALUE` reader - Value of last capture on channel 0"]
+pub type VALUE_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - Value of last capture on channel 0"]
+    #[inline(always)]
+    pub fn value(&self) -> VALUE_R {
+        VALUE_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CAP_CH")
+            .field("value", &self.value())
+            .finish()
+    }
+}
+#[doc = "Value of last capture on channel %s\n\nYou can [`read`](crate::Reg::read) this register and get [`cap_ch::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CAP_CH_SPEC;
+impl crate::RegisterSpec for CAP_CH_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cap_ch::R`](R) reader structure"]
+impl crate::Readable for CAP_CH_SPEC {}
+#[doc = "`reset()` method sets CAP_CH%s to value 0"]
+impl crate::Resettable for CAP_CH_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/mcpwm0/cap_ch_cfg.rs

@@ -0,0 +1,99 @@
+#[doc = "Register `CAP_CH%s_CFG` reader"]
+pub type R = crate::R<CAP_CH_CFG_SPEC>;
+#[doc = "Register `CAP_CH%s_CFG` writer"]
+pub type W = crate::W<CAP_CH_CFG_SPEC>;
+#[doc = "Field `EN` reader - When set, capture on channel 0 is enabled"]
+pub type EN_R = crate::BitReader;
+#[doc = "Field `EN` writer - When set, capture on channel 0 is enabled"]
+pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `MODE` reader - Edge of capture on channel 0 after prescaling. When bit0 is set to 1: enable capture on the negative edge, When bit1 is set to 1: enable capture on the positive edge."]
+pub type MODE_R = crate::FieldReader;
+#[doc = "Field `MODE` writer - Edge of capture on channel 0 after prescaling. When bit0 is set to 1: enable capture on the negative edge, When bit1 is set to 1: enable capture on the positive edge."]
+pub type MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `PRESCALE` reader - Value of prescaling on possitive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE + 1"]
+pub type PRESCALE_R = crate::FieldReader;
+#[doc = "Field `PRESCALE` writer - Value of prescaling on possitive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE + 1"]
+pub type PRESCALE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+#[doc = "Field `IN_INVERT` reader - when set, CAP0 form GPIO matrix is inverted before prescale"]
+pub type IN_INVERT_R = crate::BitReader;
+#[doc = "Field `IN_INVERT` writer - when set, CAP0 form GPIO matrix is inverted before prescale"]
+pub type IN_INVERT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SW` writer - Write 1 will trigger a software forced capture on channel 0"]
+pub type SW_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - When set, capture on channel 0 is enabled"]
+    #[inline(always)]
+    pub fn en(&self) -> EN_R {
+        EN_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bits 1:2 - Edge of capture on channel 0 after prescaling. When bit0 is set to 1: enable capture on the negative edge, When bit1 is set to 1: enable capture on the positive edge."]
+    #[inline(always)]
+    pub fn mode(&self) -> MODE_R {
+        MODE_R::new(((self.bits >> 1) & 3) as u8)
+    }
+    #[doc = "Bits 3:10 - Value of prescaling on possitive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE + 1"]
+    #[inline(always)]
+    pub fn prescale(&self) -> PRESCALE_R {
+        PRESCALE_R::new(((self.bits >> 3) & 0xff) as u8)
+    }
+    #[doc = "Bit 11 - when set, CAP0 form GPIO matrix is inverted before prescale"]
+    #[inline(always)]
+    pub fn in_invert(&self) -> IN_INVERT_R {
+        IN_INVERT_R::new(((self.bits >> 11) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CAP_CH_CFG")
+            .field("en", &self.en())
+            .field("mode", &self.mode())
+            .field("prescale", &self.prescale())
+            .field("in_invert", &self.in_invert())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - When set, capture on channel 0 is enabled"]
+    #[inline(always)]
+    pub fn en(&mut self) -> EN_W<CAP_CH_CFG_SPEC> {
+        EN_W::new(self, 0)
+    }
+    #[doc = "Bits 1:2 - Edge of capture on channel 0 after prescaling. When bit0 is set to 1: enable capture on the negative edge, When bit1 is set to 1: enable capture on the positive edge."]
+    #[inline(always)]
+    pub fn mode(&mut self) -> MODE_W<CAP_CH_CFG_SPEC> {
+        MODE_W::new(self, 1)
+    }
+    #[doc = "Bits 3:10 - Value of prescaling on possitive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE + 1"]
+    #[inline(always)]
+    pub fn prescale(&mut self) -> PRESCALE_W<CAP_CH_CFG_SPEC> {
+        PRESCALE_W::new(self, 3)
+    }
+    #[doc = "Bit 11 - when set, CAP0 form GPIO matrix is inverted before prescale"]
+    #[inline(always)]
+    pub fn in_invert(&mut self) -> IN_INVERT_W<CAP_CH_CFG_SPEC> {
+        IN_INVERT_W::new(self, 11)
+    }
+    #[doc = "Bit 12 - Write 1 will trigger a software forced capture on channel 0"]
+    #[inline(always)]
+    pub fn sw(&mut self) -> SW_W<CAP_CH_CFG_SPEC> {
+        SW_W::new(self, 12)
+    }
+}
+#[doc = "Capture channel %s configuration and enable\n\nYou can [`read`](crate::Reg::read) this register and get [`cap_ch_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cap_ch_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CAP_CH_CFG_SPEC;
+impl crate::RegisterSpec for CAP_CH_CFG_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cap_ch_cfg::R`](R) reader structure"]
+impl crate::Readable for CAP_CH_CFG_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`cap_ch_cfg::W`](W) writer structure"]
+impl crate::Writable for CAP_CH_CFG_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CAP_CH%s_CFG to value 0"]
+impl crate::Resettable for CAP_CH_CFG_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/mcpwm0/cap_status.rs

@@ -0,0 +1,46 @@
+#[doc = "Register `CAP_STATUS` reader"]
+pub type R = crate::R<CAP_STATUS_SPEC>;
+#[doc = "Field `CAP0_EDGE` reader - Edge of last capture trigger on channel 0, 0: posedge, 1: negedge"]
+pub type CAP0_EDGE_R = crate::BitReader;
+#[doc = "Field `CAP1_EDGE` reader - Edge of last capture trigger on channel 1, 0: posedge, 1: negedge"]
+pub type CAP1_EDGE_R = crate::BitReader;
+#[doc = "Field `CAP2_EDGE` reader - Edge of last capture trigger on channel 2, 0: posedge, 1: negedge"]
+pub type CAP2_EDGE_R = crate::BitReader;
+impl R {
+    #[doc = "Bit 0 - Edge of last capture trigger on channel 0, 0: posedge, 1: negedge"]
+    #[inline(always)]
+    pub fn cap0_edge(&self) -> CAP0_EDGE_R {
+        CAP0_EDGE_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Edge of last capture trigger on channel 1, 0: posedge, 1: negedge"]
+    #[inline(always)]
+    pub fn cap1_edge(&self) -> CAP1_EDGE_R {
+        CAP1_EDGE_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Edge of last capture trigger on channel 2, 0: posedge, 1: negedge"]
+    #[inline(always)]
+    pub fn cap2_edge(&self) -> CAP2_EDGE_R {
+        CAP2_EDGE_R::new(((self.bits >> 2) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CAP_STATUS")
+            .field("cap0_edge", &self.cap0_edge())
+            .field("cap1_edge", &self.cap1_edge())
+            .field("cap2_edge", &self.cap2_edge())
+            .finish()
+    }
+}
+#[doc = "Edge of last capture trigger\n\nYou can [`read`](crate::Reg::read) this register and get [`cap_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CAP_STATUS_SPEC;
+impl crate::RegisterSpec for CAP_STATUS_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cap_status::R`](R) reader structure"]
+impl crate::Readable for CAP_STATUS_SPEC {}
+#[doc = "`reset()` method sets CAP_STATUS to value 0"]
+impl crate::Resettable for CAP_STATUS_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/mcpwm0/cap_timer_cfg.rs

@@ -0,0 +1,84 @@
+#[doc = "Register `CAP_TIMER_CFG` reader"]
+pub type R = crate::R<CAP_TIMER_CFG_SPEC>;
+#[doc = "Register `CAP_TIMER_CFG` writer"]
+pub type W = crate::W<CAP_TIMER_CFG_SPEC>;
+#[doc = "Field `CAP_TIMER_EN` reader - When set, capture timer incrementing under APB_clk is enabled."]
+pub type CAP_TIMER_EN_R = crate::BitReader;
+#[doc = "Field `CAP_TIMER_EN` writer - When set, capture timer incrementing under APB_clk is enabled."]
+pub type CAP_TIMER_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CAP_SYNCI_EN` reader - When set, capture timer sync is enabled."]
+pub type CAP_SYNCI_EN_R = crate::BitReader;
+#[doc = "Field `CAP_SYNCI_EN` writer - When set, capture timer sync is enabled."]
+pub type CAP_SYNCI_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CAP_SYNCI_SEL` reader - capture module sync input selection. 0: none, 1: timer0 sync_out, 2: timer1 sync_out, 3: timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix"]
+pub type CAP_SYNCI_SEL_R = crate::FieldReader;
+#[doc = "Field `CAP_SYNCI_SEL` writer - capture module sync input selection. 0: none, 1: timer0 sync_out, 2: timer1 sync_out, 3: timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix"]
+pub type CAP_SYNCI_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `CAP_SYNC_SW` writer - Write 1 will force a capture timer sync, capture timer is loaded with value in phase register."]
+pub type CAP_SYNC_SW_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - When set, capture timer incrementing under APB_clk is enabled."]
+    #[inline(always)]
+    pub fn cap_timer_en(&self) -> CAP_TIMER_EN_R {
+        CAP_TIMER_EN_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - When set, capture timer sync is enabled."]
+    #[inline(always)]
+    pub fn cap_synci_en(&self) -> CAP_SYNCI_EN_R {
+        CAP_SYNCI_EN_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bits 2:4 - capture module sync input selection. 0: none, 1: timer0 sync_out, 2: timer1 sync_out, 3: timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix"]
+    #[inline(always)]
+    pub fn cap_synci_sel(&self) -> CAP_SYNCI_SEL_R {
+        CAP_SYNCI_SEL_R::new(((self.bits >> 2) & 7) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CAP_TIMER_CFG")
+            .field("cap_timer_en", &self.cap_timer_en())
+            .field("cap_synci_en", &self.cap_synci_en())
+            .field("cap_synci_sel", &self.cap_synci_sel())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - When set, capture timer incrementing under APB_clk is enabled."]
+    #[inline(always)]
+    pub fn cap_timer_en(&mut self) -> CAP_TIMER_EN_W<CAP_TIMER_CFG_SPEC> {
+        CAP_TIMER_EN_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - When set, capture timer sync is enabled."]
+    #[inline(always)]
+    pub fn cap_synci_en(&mut self) -> CAP_SYNCI_EN_W<CAP_TIMER_CFG_SPEC> {
+        CAP_SYNCI_EN_W::new(self, 1)
+    }
+    #[doc = "Bits 2:4 - capture module sync input selection. 0: none, 1: timer0 sync_out, 2: timer1 sync_out, 3: timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix"]
+    #[inline(always)]
+    pub fn cap_synci_sel(&mut self) -> CAP_SYNCI_SEL_W<CAP_TIMER_CFG_SPEC> {
+        CAP_SYNCI_SEL_W::new(self, 2)
+    }
+    #[doc = "Bit 5 - Write 1 will force a capture timer sync, capture timer is loaded with value in phase register."]
+    #[inline(always)]
+    pub fn cap_sync_sw(&mut self) -> CAP_SYNC_SW_W<CAP_TIMER_CFG_SPEC> {
+        CAP_SYNC_SW_W::new(self, 5)
+    }
+}
+#[doc = "Configure capture timer\n\nYou can [`read`](crate::Reg::read) this register and get [`cap_timer_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cap_timer_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CAP_TIMER_CFG_SPEC;
+impl crate::RegisterSpec for CAP_TIMER_CFG_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cap_timer_cfg::R`](R) reader structure"]
+impl crate::Readable for CAP_TIMER_CFG_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`cap_timer_cfg::W`](W) writer structure"]
+impl crate::Writable for CAP_TIMER_CFG_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CAP_TIMER_CFG to value 0"]
+impl crate::Resettable for CAP_TIMER_CFG_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/mcpwm0/cap_timer_phase.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `CAP_TIMER_PHASE` reader"]
+pub type R = crate::R<CAP_TIMER_PHASE_SPEC>;
+#[doc = "Register `CAP_TIMER_PHASE` writer"]
+pub type W = crate::W<CAP_TIMER_PHASE_SPEC>;
+#[doc = "Field `CAP_PHASE` reader - Phase value for capture timer sync operation."]
+pub type CAP_PHASE_R = crate::FieldReader<u32>;
+#[doc = "Field `CAP_PHASE` writer - Phase value for capture timer sync operation."]
+pub type CAP_PHASE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - Phase value for capture timer sync operation."]
+    #[inline(always)]
+    pub fn cap_phase(&self) -> CAP_PHASE_R {
+        CAP_PHASE_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CAP_TIMER_PHASE")
+            .field("cap_phase", &self.cap_phase())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Phase value for capture timer sync operation."]
+    #[inline(always)]
+    pub fn cap_phase(&mut self) -> CAP_PHASE_W<CAP_TIMER_PHASE_SPEC> {
+        CAP_PHASE_W::new(self, 0)
+    }
+}
+#[doc = "Phase for capture timer sync\n\nYou can [`read`](crate::Reg::read) this register and get [`cap_timer_phase::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cap_timer_phase::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CAP_TIMER_PHASE_SPEC;
+impl crate::RegisterSpec for CAP_TIMER_PHASE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cap_timer_phase::R`](R) reader structure"]
+impl crate::Readable for CAP_TIMER_PHASE_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`cap_timer_phase::W`](W) writer structure"]
+impl crate::Writable for CAP_TIMER_PHASE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CAP_TIMER_PHASE to value 0"]
+impl crate::Resettable for CAP_TIMER_PHASE_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/mcpwm0/ch.rs

@@ -0,0 +1,155 @@
+#[repr(C)]
+#[cfg_attr(feature = "impl-register-debug", derive(Debug))]
+#[doc = "Cluster CH%s, containing CMPR?_CFG, CMPR?_VALUE0, CMPR?_VALUE1, GEN?_CFG0, GEN?_FORCE, GEN?_A, GEN?_B, DB?_CFG, DB?_FED_CFG, DB?_RED_CFG, CHOPPER?_CFG, TZ?_CFG0, TZ?_CFG1, TZ?_STATUS"]
+pub struct CH {
+    cmpr_cfg: CMPR_CFG,
+    cmpr_value0: CMPR_VALUE0,
+    cmpr_value1: CMPR_VALUE1,
+    gen_cfg0: GEN_CFG0,
+    gen_force: GEN_FORCE,
+    gen: [GEN; 2],
+    db_cfg: DB_CFG,
+    db_fed_cfg: DB_FED_CFG,
+    db_red_cfg: DB_RED_CFG,
+    chopper_cfg: CHOPPER_CFG,
+    tz_cfg0: TZ_CFG0,
+    tz_cfg1: TZ_CFG1,
+    tz_status: TZ_STATUS,
+}
+impl CH {
+    #[doc = "0x00 - Transfer status and update method for time stamp registers A and B"]
+    #[inline(always)]
+    pub const fn cmpr_cfg(&self) -> &CMPR_CFG {
+        &self.cmpr_cfg
+    }
+    #[doc = "0x04 - Shadow register for register A."]
+    #[inline(always)]
+    pub const fn cmpr_value0(&self) -> &CMPR_VALUE0 {
+        &self.cmpr_value0
+    }
+    #[doc = "0x08 - Shadow register for register B."]
+    #[inline(always)]
+    pub const fn cmpr_value1(&self) -> &CMPR_VALUE1 {
+        &self.cmpr_value1
+    }
+    #[doc = "0x0c - Fault event T0 and T1 handling"]
+    #[inline(always)]
+    pub const fn gen_cfg0(&self) -> &GEN_CFG0 {
+        &self.gen_cfg0
+    }
+    #[doc = "0x10 - Permissives to force PWMxA and PWMxB outputs by software"]
+    #[inline(always)]
+    pub const fn gen_force(&self) -> &GEN_FORCE {
+        &self.gen_force
+    }
+    #[doc = "0x14..0x1c - Actions triggered by events on PWMx%s"]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is the index of register in the array. `n == 0` corresponds to `GENA` register.</div>"]
+    #[inline(always)]
+    pub const fn gen(&self, n: usize) -> &GEN {
+        &self.gen[n]
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "0x14..0x1c - Actions triggered by events on PWMx%s"]
+    #[inline(always)]
+    pub fn gen_iter(&self) -> impl Iterator<Item = &GEN> {
+        self.gen.iter()
+    }
+    #[doc = "0x14 - Actions triggered by events on PWMxA"]
+    #[inline(always)]
+    pub const fn gena(&self) -> &GEN {
+        self.gen(0)
+    }
+    #[doc = "0x18 - Actions triggered by events on PWMxB"]
+    #[inline(always)]
+    pub const fn genb(&self) -> &GEN {
+        self.gen(1)
+    }
+    #[doc = "0x1c - dead time type selection and configuration"]
+    #[inline(always)]
+    pub const fn db_cfg(&self) -> &DB_CFG {
+        &self.db_cfg
+    }
+    #[doc = "0x20 - Shadow register for falling edge delay (FED)."]
+    #[inline(always)]
+    pub const fn db_fed_cfg(&self) -> &DB_FED_CFG {
+        &self.db_fed_cfg
+    }
+    #[doc = "0x24 - Shadow register for rising edge delay (RED)."]
+    #[inline(always)]
+    pub const fn db_red_cfg(&self) -> &DB_RED_CFG {
+        &self.db_red_cfg
+    }
+    #[doc = "0x28 - Carrier enable and configuratoin"]
+    #[inline(always)]
+    pub const fn chopper_cfg(&self) -> &CHOPPER_CFG {
+        &self.chopper_cfg
+    }
+    #[doc = "0x2c - Actions on PWMxA and PWMxB trip events"]
+    #[inline(always)]
+    pub const fn tz_cfg0(&self) -> &TZ_CFG0 {
+        &self.tz_cfg0
+    }
+    #[doc = "0x30 - Software triggers for fault handler actions"]
+    #[inline(always)]
+    pub const fn tz_cfg1(&self) -> &TZ_CFG1 {
+        &self.tz_cfg1
+    }
+    #[doc = "0x34 - Status of fault events."]
+    #[inline(always)]
+    pub const fn tz_status(&self) -> &TZ_STATUS {
+        &self.tz_status
+    }
+}
+#[doc = "CMPR_CFG (rw) register accessor: Transfer status and update method for time stamp registers A and B\n\nYou can [`read`](crate::Reg::read) this register and get [`cmpr_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmpr_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmpr_cfg`] module"]
+pub type CMPR_CFG = crate::Reg<cmpr_cfg::CMPR_CFG_SPEC>;
+#[doc = "Transfer status and update method for time stamp registers A and B"]
+pub mod cmpr_cfg;
+#[doc = "CMPR_VALUE0 (rw) register accessor: Shadow register for register A.\n\nYou can [`read`](crate::Reg::read) this register and get [`cmpr_value0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmpr_value0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmpr_value0`] module"]
+pub type CMPR_VALUE0 = crate::Reg<cmpr_value0::CMPR_VALUE0_SPEC>;
+#[doc = "Shadow register for register A."]
+pub mod cmpr_value0;
+#[doc = "CMPR_VALUE1 (rw) register accessor: Shadow register for register B.\n\nYou can [`read`](crate::Reg::read) this register and get [`cmpr_value1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmpr_value1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmpr_value1`] module"]
+pub type CMPR_VALUE1 = crate::Reg<cmpr_value1::CMPR_VALUE1_SPEC>;
+#[doc = "Shadow register for register B."]
+pub mod cmpr_value1;
+#[doc = "GEN_CFG0 (rw) register accessor: Fault event T0 and T1 handling\n\nYou can [`read`](crate::Reg::read) this register and get [`gen_cfg0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gen_cfg0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gen_cfg0`] module"]
+pub type GEN_CFG0 = crate::Reg<gen_cfg0::GEN_CFG0_SPEC>;
+#[doc = "Fault event T0 and T1 handling"]
+pub mod gen_cfg0;
+#[doc = "GEN_FORCE (rw) register accessor: Permissives to force PWMxA and PWMxB outputs by software\n\nYou can [`read`](crate::Reg::read) this register and get [`gen_force::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gen_force::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gen_force`] module"]
+pub type GEN_FORCE = crate::Reg<gen_force::GEN_FORCE_SPEC>;
+#[doc = "Permissives to force PWMxA and PWMxB outputs by software"]
+pub mod gen_force;
+#[doc = "GEN (rw) register accessor: Actions triggered by events on PWMx%s\n\nYou can [`read`](crate::Reg::read) this register and get [`gen::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gen::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gen`] module"]
+pub type GEN = crate::Reg<gen::GEN_SPEC>;
+#[doc = "Actions triggered by events on PWMx%s"]
+pub mod gen;
+#[doc = "DB_CFG (rw) register accessor: dead time type selection and configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`db_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`db_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@db_cfg`] module"]
+pub type DB_CFG = crate::Reg<db_cfg::DB_CFG_SPEC>;
+#[doc = "dead time type selection and configuration"]
+pub mod db_cfg;
+#[doc = "DB_FED_CFG (rw) register accessor: Shadow register for falling edge delay (FED).\n\nYou can [`read`](crate::Reg::read) this register and get [`db_fed_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`db_fed_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@db_fed_cfg`] module"]
+pub type DB_FED_CFG = crate::Reg<db_fed_cfg::DB_FED_CFG_SPEC>;
+#[doc = "Shadow register for falling edge delay (FED)."]
+pub mod db_fed_cfg;
+#[doc = "DB_RED_CFG (rw) register accessor: Shadow register for rising edge delay (RED).\n\nYou can [`read`](crate::Reg::read) this register and get [`db_red_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`db_red_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@db_red_cfg`] module"]
+pub type DB_RED_CFG = crate::Reg<db_red_cfg::DB_RED_CFG_SPEC>;
+#[doc = "Shadow register for rising edge delay (RED)."]
+pub mod db_red_cfg;
+#[doc = "CHOPPER_CFG (rw) register accessor: Carrier enable and configuratoin\n\nYou can [`read`](crate::Reg::read) this register and get [`chopper_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chopper_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@chopper_cfg`] module"]
+pub type CHOPPER_CFG = crate::Reg<chopper_cfg::CHOPPER_CFG_SPEC>;
+#[doc = "Carrier enable and configuratoin"]
+pub mod chopper_cfg;
+#[doc = "TZ_CFG0 (rw) register accessor: Actions on PWMxA and PWMxB trip events\n\nYou can [`read`](crate::Reg::read) this register and get [`tz_cfg0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tz_cfg0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tz_cfg0`] module"]
+pub type TZ_CFG0 = crate::Reg<tz_cfg0::TZ_CFG0_SPEC>;
+#[doc = "Actions on PWMxA and PWMxB trip events"]
+pub mod tz_cfg0;
+#[doc = "TZ_CFG1 (rw) register accessor: Software triggers for fault handler actions\n\nYou can [`read`](crate::Reg::read) this register and get [`tz_cfg1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tz_cfg1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tz_cfg1`] module"]
+pub type TZ_CFG1 = crate::Reg<tz_cfg1::TZ_CFG1_SPEC>;
+#[doc = "Software triggers for fault handler actions"]
+pub mod tz_cfg1;
+#[doc = "TZ_STATUS (r) register accessor: Status of fault events.\n\nYou can [`read`](crate::Reg::read) this register and get [`tz_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tz_status`] module"]
+pub type TZ_STATUS = crate::Reg<tz_status::TZ_STATUS_SPEC>;
+#[doc = "Status of fault events."]
+pub mod tz_status;

vendor/esp32s3/src/mcpwm0/ch/chopper_cfg.rs

@@ -0,0 +1,122 @@
+#[doc = "Register `CHOPPER_CFG` reader"]
+pub type R = crate::R<CHOPPER_CFG_SPEC>;
+#[doc = "Register `CHOPPER_CFG` writer"]
+pub type W = crate::W<CHOPPER_CFG_SPEC>;
+#[doc = "Field `EN` reader - When set, carrier0 function is enabled. When cleared, carrier0 is bypassed"]
+pub type EN_R = crate::BitReader;
+#[doc = "Field `EN` writer - When set, carrier0 function is enabled. When cleared, carrier0 is bypassed"]
+pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PRESCALE` reader - PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1)"]
+pub type PRESCALE_R = crate::FieldReader;
+#[doc = "Field `PRESCALE` writer - PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1)"]
+pub type PRESCALE_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `DUTY` reader - carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8"]
+pub type DUTY_R = crate::FieldReader;
+#[doc = "Field `DUTY` writer - carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8"]
+pub type DUTY_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `OSHTWTH` reader - width of the fist pulse in number of periods of the carrier"]
+pub type OSHTWTH_R = crate::FieldReader;
+#[doc = "Field `OSHTWTH` writer - width of the fist pulse in number of periods of the carrier"]
+pub type OSHTWTH_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `OUT_INVERT` reader - when set, invert the output of PWM0A and PWM0B for this submodule"]
+pub type OUT_INVERT_R = crate::BitReader;
+#[doc = "Field `OUT_INVERT` writer - when set, invert the output of PWM0A and PWM0B for this submodule"]
+pub type OUT_INVERT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `IN_INVERT` reader - when set, invert the input of PWM0A and PWM0B for this submodule"]
+pub type IN_INVERT_R = crate::BitReader;
+#[doc = "Field `IN_INVERT` writer - when set, invert the input of PWM0A and PWM0B for this submodule"]
+pub type IN_INVERT_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - When set, carrier0 function is enabled. When cleared, carrier0 is bypassed"]
+    #[inline(always)]
+    pub fn en(&self) -> EN_R {
+        EN_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bits 1:4 - PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1)"]
+    #[inline(always)]
+    pub fn prescale(&self) -> PRESCALE_R {
+        PRESCALE_R::new(((self.bits >> 1) & 0x0f) as u8)
+    }
+    #[doc = "Bits 5:7 - carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8"]
+    #[inline(always)]
+    pub fn duty(&self) -> DUTY_R {
+        DUTY_R::new(((self.bits >> 5) & 7) as u8)
+    }
+    #[doc = "Bits 8:11 - width of the fist pulse in number of periods of the carrier"]
+    #[inline(always)]
+    pub fn oshtwth(&self) -> OSHTWTH_R {
+        OSHTWTH_R::new(((self.bits >> 8) & 0x0f) as u8)
+    }
+    #[doc = "Bit 12 - when set, invert the output of PWM0A and PWM0B for this submodule"]
+    #[inline(always)]
+    pub fn out_invert(&self) -> OUT_INVERT_R {
+        OUT_INVERT_R::new(((self.bits >> 12) & 1) != 0)
+    }
+    #[doc = "Bit 13 - when set, invert the input of PWM0A and PWM0B for this submodule"]
+    #[inline(always)]
+    pub fn in_invert(&self) -> IN_INVERT_R {
+        IN_INVERT_R::new(((self.bits >> 13) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CHOPPER_CFG")
+            .field("en", &self.en())
+            .field("prescale", &self.prescale())
+            .field("duty", &self.duty())
+            .field("oshtwth", &self.oshtwth())
+            .field("out_invert", &self.out_invert())
+            .field("in_invert", &self.in_invert())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - When set, carrier0 function is enabled. When cleared, carrier0 is bypassed"]
+    #[inline(always)]
+    pub fn en(&mut self) -> EN_W<CHOPPER_CFG_SPEC> {
+        EN_W::new(self, 0)
+    }
+    #[doc = "Bits 1:4 - PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1)"]
+    #[inline(always)]
+    pub fn prescale(&mut self) -> PRESCALE_W<CHOPPER_CFG_SPEC> {
+        PRESCALE_W::new(self, 1)
+    }
+    #[doc = "Bits 5:7 - carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8"]
+    #[inline(always)]
+    pub fn duty(&mut self) -> DUTY_W<CHOPPER_CFG_SPEC> {
+        DUTY_W::new(self, 5)
+    }
+    #[doc = "Bits 8:11 - width of the fist pulse in number of periods of the carrier"]
+    #[inline(always)]
+    pub fn oshtwth(&mut self) -> OSHTWTH_W<CHOPPER_CFG_SPEC> {
+        OSHTWTH_W::new(self, 8)
+    }
+    #[doc = "Bit 12 - when set, invert the output of PWM0A and PWM0B for this submodule"]
+    #[inline(always)]
+    pub fn out_invert(&mut self) -> OUT_INVERT_W<CHOPPER_CFG_SPEC> {
+        OUT_INVERT_W::new(self, 12)
+    }
+    #[doc = "Bit 13 - when set, invert the input of PWM0A and PWM0B for this submodule"]
+    #[inline(always)]
+    pub fn in_invert(&mut self) -> IN_INVERT_W<CHOPPER_CFG_SPEC> {
+        IN_INVERT_W::new(self, 13)
+    }
+}
+#[doc = "Carrier enable and configuratoin\n\nYou can [`read`](crate::Reg::read) this register and get [`chopper_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chopper_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CHOPPER_CFG_SPEC;
+impl crate::RegisterSpec for CHOPPER_CFG_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`chopper_cfg::R`](R) reader structure"]
+impl crate::Readable for CHOPPER_CFG_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`chopper_cfg::W`](W) writer structure"]
+impl crate::Writable for CHOPPER_CFG_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CHOPPER_CFG to value 0"]
+impl crate::Resettable for CHOPPER_CFG_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/mcpwm0/ch/cmpr_cfg.rs

@@ -0,0 +1,92 @@
+#[doc = "Register `CMPR_CFG` reader"]
+pub type R = crate::R<CMPR_CFG_SPEC>;
+#[doc = "Register `CMPR_CFG` writer"]
+pub type W = crate::W<CMPR_CFG_SPEC>;
+#[doc = "Field `A_UPMETHOD` reader - Update method for PWM generator 0 time stamp A's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update."]
+pub type A_UPMETHOD_R = crate::FieldReader;
+#[doc = "Field `A_UPMETHOD` writer - Update method for PWM generator 0 time stamp A's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update."]
+pub type A_UPMETHOD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `B_UPMETHOD` reader - Update method for PWM generator 0 time stamp B's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update."]
+pub type B_UPMETHOD_R = crate::FieldReader;
+#[doc = "Field `B_UPMETHOD` writer - Update method for PWM generator 0 time stamp B's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update."]
+pub type B_UPMETHOD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `A_SHDW_FULL` reader - Set and reset by hardware. If set, PWM generator 0 time stamp A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared, A's active reg has been updated with shadow register latest value"]
+pub type A_SHDW_FULL_R = crate::BitReader;
+#[doc = "Field `A_SHDW_FULL` writer - Set and reset by hardware. If set, PWM generator 0 time stamp A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared, A's active reg has been updated with shadow register latest value"]
+pub type A_SHDW_FULL_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `B_SHDW_FULL` reader - Set and reset by hardware. If set, PWM generator 0 time stamp B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared, B's active reg has been updated with shadow register latest value"]
+pub type B_SHDW_FULL_R = crate::BitReader;
+#[doc = "Field `B_SHDW_FULL` writer - Set and reset by hardware. If set, PWM generator 0 time stamp B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared, B's active reg has been updated with shadow register latest value"]
+pub type B_SHDW_FULL_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 0:3 - Update method for PWM generator 0 time stamp A's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update."]
+    #[inline(always)]
+    pub fn a_upmethod(&self) -> A_UPMETHOD_R {
+        A_UPMETHOD_R::new((self.bits & 0x0f) as u8)
+    }
+    #[doc = "Bits 4:7 - Update method for PWM generator 0 time stamp B's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update."]
+    #[inline(always)]
+    pub fn b_upmethod(&self) -> B_UPMETHOD_R {
+        B_UPMETHOD_R::new(((self.bits >> 4) & 0x0f) as u8)
+    }
+    #[doc = "Bit 8 - Set and reset by hardware. If set, PWM generator 0 time stamp A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared, A's active reg has been updated with shadow register latest value"]
+    #[inline(always)]
+    pub fn a_shdw_full(&self) -> A_SHDW_FULL_R {
+        A_SHDW_FULL_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - Set and reset by hardware. If set, PWM generator 0 time stamp B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared, B's active reg has been updated with shadow register latest value"]
+    #[inline(always)]
+    pub fn b_shdw_full(&self) -> B_SHDW_FULL_R {
+        B_SHDW_FULL_R::new(((self.bits >> 9) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CMPR_CFG")
+            .field("a_upmethod", &self.a_upmethod())
+            .field("b_upmethod", &self.b_upmethod())
+            .field("a_shdw_full", &self.a_shdw_full())
+            .field("b_shdw_full", &self.b_shdw_full())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:3 - Update method for PWM generator 0 time stamp A's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update."]
+    #[inline(always)]
+    pub fn a_upmethod(&mut self) -> A_UPMETHOD_W<CMPR_CFG_SPEC> {
+        A_UPMETHOD_W::new(self, 0)
+    }
+    #[doc = "Bits 4:7 - Update method for PWM generator 0 time stamp B's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update."]
+    #[inline(always)]
+    pub fn b_upmethod(&mut self) -> B_UPMETHOD_W<CMPR_CFG_SPEC> {
+        B_UPMETHOD_W::new(self, 4)
+    }
+    #[doc = "Bit 8 - Set and reset by hardware. If set, PWM generator 0 time stamp A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared, A's active reg has been updated with shadow register latest value"]
+    #[inline(always)]
+    pub fn a_shdw_full(&mut self) -> A_SHDW_FULL_W<CMPR_CFG_SPEC> {
+        A_SHDW_FULL_W::new(self, 8)
+    }
+    #[doc = "Bit 9 - Set and reset by hardware. If set, PWM generator 0 time stamp B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared, B's active reg has been updated with shadow register latest value"]
+    #[inline(always)]
+    pub fn b_shdw_full(&mut self) -> B_SHDW_FULL_W<CMPR_CFG_SPEC> {
+        B_SHDW_FULL_W::new(self, 9)
+    }
+}
+#[doc = "Transfer status and update method for time stamp registers A and B\n\nYou can [`read`](crate::Reg::read) this register and get [`cmpr_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmpr_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CMPR_CFG_SPEC;
+impl crate::RegisterSpec for CMPR_CFG_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cmpr_cfg::R`](R) reader structure"]
+impl crate::Readable for CMPR_CFG_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`cmpr_cfg::W`](W) writer structure"]
+impl crate::Writable for CMPR_CFG_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CMPR_CFG to value 0"]
+impl crate::Resettable for CMPR_CFG_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/mcpwm0/ch/cmpr_value0.rs

@@ -0,0 +1,45 @@
+#[doc = "Register `CMPR_VALUE0` reader"]
+pub type R = crate::R<CMPR_VALUE0_SPEC>;
+#[doc = "Register `CMPR_VALUE0` writer"]
+pub type W = crate::W<CMPR_VALUE0_SPEC>;
+#[doc = "Field `A` reader - PWM generator 0 time stamp A's shadow register"]
+pub type A_R = crate::FieldReader<u16>;
+#[doc = "Field `A` writer - PWM generator 0 time stamp A's shadow register"]
+pub type A_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
+impl R {
+    #[doc = "Bits 0:15 - PWM generator 0 time stamp A's shadow register"]
+    #[inline(always)]
+    pub fn a(&self) -> A_R {
+        A_R::new((self.bits & 0xffff) as u16)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CMPR_VALUE0").field("a", &self.a()).finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:15 - PWM generator 0 time stamp A's shadow register"]
+    #[inline(always)]
+    pub fn a(&mut self) -> A_W<CMPR_VALUE0_SPEC> {
+        A_W::new(self, 0)
+    }
+}
+#[doc = "Shadow register for register A.\n\nYou can [`read`](crate::Reg::read) this register and get [`cmpr_value0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmpr_value0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CMPR_VALUE0_SPEC;
+impl crate::RegisterSpec for CMPR_VALUE0_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cmpr_value0::R`](R) reader structure"]
+impl crate::Readable for CMPR_VALUE0_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`cmpr_value0::W`](W) writer structure"]
+impl crate::Writable for CMPR_VALUE0_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CMPR_VALUE0 to value 0"]
+impl crate::Resettable for CMPR_VALUE0_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/mcpwm0/ch/cmpr_value1.rs

@@ -0,0 +1,45 @@
+#[doc = "Register `CMPR_VALUE1` reader"]
+pub type R = crate::R<CMPR_VALUE1_SPEC>;
+#[doc = "Register `CMPR_VALUE1` writer"]
+pub type W = crate::W<CMPR_VALUE1_SPEC>;
+#[doc = "Field `B` reader - PWM generator 0 time stamp B's shadow register"]
+pub type B_R = crate::FieldReader<u16>;
+#[doc = "Field `B` writer - PWM generator 0 time stamp B's shadow register"]
+pub type B_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
+impl R {
+    #[doc = "Bits 0:15 - PWM generator 0 time stamp B's shadow register"]
+    #[inline(always)]
+    pub fn b(&self) -> B_R {
+        B_R::new((self.bits & 0xffff) as u16)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CMPR_VALUE1").field("b", &self.b()).finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:15 - PWM generator 0 time stamp B's shadow register"]
+    #[inline(always)]
+    pub fn b(&mut self) -> B_W<CMPR_VALUE1_SPEC> {
+        B_W::new(self, 0)
+    }
+}
+#[doc = "Shadow register for register B.\n\nYou can [`read`](crate::Reg::read) this register and get [`cmpr_value1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmpr_value1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CMPR_VALUE1_SPEC;
+impl crate::RegisterSpec for CMPR_VALUE1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cmpr_value1::R`](R) reader structure"]
+impl crate::Readable for CMPR_VALUE1_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`cmpr_value1::W`](W) writer structure"]
+impl crate::Writable for CMPR_VALUE1_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CMPR_VALUE1 to value 0"]
+impl crate::Resettable for CMPR_VALUE1_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/mcpwm0/ch/db_cfg.rs

@@ -0,0 +1,212 @@
+#[doc = "Register `DB_CFG` reader"]
+pub type R = crate::R<DB_CFG_SPEC>;
+#[doc = "Register `DB_CFG` writer"]
+pub type W = crate::W<DB_CFG_SPEC>;
+#[doc = "Field `FED_UPMETHOD` reader - Update method for FED (falling edge delay) active register. 0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze"]
+pub type FED_UPMETHOD_R = crate::FieldReader;
+#[doc = "Field `FED_UPMETHOD` writer - Update method for FED (falling edge delay) active register. 0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze"]
+pub type FED_UPMETHOD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `RED_UPMETHOD` reader - Update method for RED (rising edge delay) active register. 0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze"]
+pub type RED_UPMETHOD_R = crate::FieldReader;
+#[doc = "Field `RED_UPMETHOD` writer - Update method for RED (rising edge delay) active register. 0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze"]
+pub type RED_UPMETHOD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `DEB_MODE` reader - S8 in documentation, dual-edge B mode, 0: fed/red take effect on different path separately, 1: fed/red take effect on B path, A out is in bypass or dulpB mode"]
+pub type DEB_MODE_R = crate::BitReader;
+#[doc = "Field `DEB_MODE` writer - S8 in documentation, dual-edge B mode, 0: fed/red take effect on different path separately, 1: fed/red take effect on B path, A out is in bypass or dulpB mode"]
+pub type DEB_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `A_OUTSWAP` reader - S6 in documentation"]
+pub type A_OUTSWAP_R = crate::BitReader;
+#[doc = "Field `A_OUTSWAP` writer - S6 in documentation"]
+pub type A_OUTSWAP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `B_OUTSWAP` reader - S7 in documentation"]
+pub type B_OUTSWAP_R = crate::BitReader;
+#[doc = "Field `B_OUTSWAP` writer - S7 in documentation"]
+pub type B_OUTSWAP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RED_INSEL` reader - S4 in documentation"]
+pub type RED_INSEL_R = crate::BitReader;
+#[doc = "Field `RED_INSEL` writer - S4 in documentation"]
+pub type RED_INSEL_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FED_INSEL` reader - S5 in documentation"]
+pub type FED_INSEL_R = crate::BitReader;
+#[doc = "Field `FED_INSEL` writer - S5 in documentation"]
+pub type FED_INSEL_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RED_OUTINVERT` reader - S2 in documentation"]
+pub type RED_OUTINVERT_R = crate::BitReader;
+#[doc = "Field `RED_OUTINVERT` writer - S2 in documentation"]
+pub type RED_OUTINVERT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FED_OUTINVERT` reader - S3 in documentation"]
+pub type FED_OUTINVERT_R = crate::BitReader;
+#[doc = "Field `FED_OUTINVERT` writer - S3 in documentation"]
+pub type FED_OUTINVERT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `A_OUTBYPASS` reader - S1 in documentation"]
+pub type A_OUTBYPASS_R = crate::BitReader;
+#[doc = "Field `A_OUTBYPASS` writer - S1 in documentation"]
+pub type A_OUTBYPASS_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `B_OUTBYPASS` reader - S0 in documentation"]
+pub type B_OUTBYPASS_R = crate::BitReader;
+#[doc = "Field `B_OUTBYPASS` writer - S0 in documentation"]
+pub type B_OUTBYPASS_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CLK_SEL` reader - Dead time generator 0 clock selection. 0: PWM_clk, 1: PT_clk"]
+pub type CLK_SEL_R = crate::BitReader;
+#[doc = "Field `CLK_SEL` writer - Dead time generator 0 clock selection. 0: PWM_clk, 1: PT_clk"]
+pub type CLK_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 0:3 - Update method for FED (falling edge delay) active register. 0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze"]
+    #[inline(always)]
+    pub fn fed_upmethod(&self) -> FED_UPMETHOD_R {
+        FED_UPMETHOD_R::new((self.bits & 0x0f) as u8)
+    }
+    #[doc = "Bits 4:7 - Update method for RED (rising edge delay) active register. 0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze"]
+    #[inline(always)]
+    pub fn red_upmethod(&self) -> RED_UPMETHOD_R {
+        RED_UPMETHOD_R::new(((self.bits >> 4) & 0x0f) as u8)
+    }
+    #[doc = "Bit 8 - S8 in documentation, dual-edge B mode, 0: fed/red take effect on different path separately, 1: fed/red take effect on B path, A out is in bypass or dulpB mode"]
+    #[inline(always)]
+    pub fn deb_mode(&self) -> DEB_MODE_R {
+        DEB_MODE_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - S6 in documentation"]
+    #[inline(always)]
+    pub fn a_outswap(&self) -> A_OUTSWAP_R {
+        A_OUTSWAP_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 10 - S7 in documentation"]
+    #[inline(always)]
+    pub fn b_outswap(&self) -> B_OUTSWAP_R {
+        B_OUTSWAP_R::new(((self.bits >> 10) & 1) != 0)
+    }
+    #[doc = "Bit 11 - S4 in documentation"]
+    #[inline(always)]
+    pub fn red_insel(&self) -> RED_INSEL_R {
+        RED_INSEL_R::new(((self.bits >> 11) & 1) != 0)
+    }
+    #[doc = "Bit 12 - S5 in documentation"]
+    #[inline(always)]
+    pub fn fed_insel(&self) -> FED_INSEL_R {
+        FED_INSEL_R::new(((self.bits >> 12) & 1) != 0)
+    }
+    #[doc = "Bit 13 - S2 in documentation"]
+    #[inline(always)]
+    pub fn red_outinvert(&self) -> RED_OUTINVERT_R {
+        RED_OUTINVERT_R::new(((self.bits >> 13) & 1) != 0)
+    }
+    #[doc = "Bit 14 - S3 in documentation"]
+    #[inline(always)]
+    pub fn fed_outinvert(&self) -> FED_OUTINVERT_R {
+        FED_OUTINVERT_R::new(((self.bits >> 14) & 1) != 0)
+    }
+    #[doc = "Bit 15 - S1 in documentation"]
+    #[inline(always)]
+    pub fn a_outbypass(&self) -> A_OUTBYPASS_R {
+        A_OUTBYPASS_R::new(((self.bits >> 15) & 1) != 0)
+    }
+    #[doc = "Bit 16 - S0 in documentation"]
+    #[inline(always)]
+    pub fn b_outbypass(&self) -> B_OUTBYPASS_R {
+        B_OUTBYPASS_R::new(((self.bits >> 16) & 1) != 0)
+    }
+    #[doc = "Bit 17 - Dead time generator 0 clock selection. 0: PWM_clk, 1: PT_clk"]
+    #[inline(always)]
+    pub fn clk_sel(&self) -> CLK_SEL_R {
+        CLK_SEL_R::new(((self.bits >> 17) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DB_CFG")
+            .field("fed_upmethod", &self.fed_upmethod())
+            .field("red_upmethod", &self.red_upmethod())
+            .field("deb_mode", &self.deb_mode())
+            .field("a_outswap", &self.a_outswap())
+            .field("b_outswap", &self.b_outswap())
+            .field("red_insel", &self.red_insel())
+            .field("fed_insel", &self.fed_insel())
+            .field("red_outinvert", &self.red_outinvert())
+            .field("fed_outinvert", &self.fed_outinvert())
+            .field("a_outbypass", &self.a_outbypass())
+            .field("b_outbypass", &self.b_outbypass())
+            .field("clk_sel", &self.clk_sel())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:3 - Update method for FED (falling edge delay) active register. 0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze"]
+    #[inline(always)]
+    pub fn fed_upmethod(&mut self) -> FED_UPMETHOD_W<DB_CFG_SPEC> {
+        FED_UPMETHOD_W::new(self, 0)
+    }
+    #[doc = "Bits 4:7 - Update method for RED (rising edge delay) active register. 0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze"]
+    #[inline(always)]
+    pub fn red_upmethod(&mut self) -> RED_UPMETHOD_W<DB_CFG_SPEC> {
+        RED_UPMETHOD_W::new(self, 4)
+    }
+    #[doc = "Bit 8 - S8 in documentation, dual-edge B mode, 0: fed/red take effect on different path separately, 1: fed/red take effect on B path, A out is in bypass or dulpB mode"]
+    #[inline(always)]
+    pub fn deb_mode(&mut self) -> DEB_MODE_W<DB_CFG_SPEC> {
+        DEB_MODE_W::new(self, 8)
+    }
+    #[doc = "Bit 9 - S6 in documentation"]
+    #[inline(always)]
+    pub fn a_outswap(&mut self) -> A_OUTSWAP_W<DB_CFG_SPEC> {
+        A_OUTSWAP_W::new(self, 9)
+    }
+    #[doc = "Bit 10 - S7 in documentation"]
+    #[inline(always)]
+    pub fn b_outswap(&mut self) -> B_OUTSWAP_W<DB_CFG_SPEC> {
+        B_OUTSWAP_W::new(self, 10)
+    }
+    #[doc = "Bit 11 - S4 in documentation"]
+    #[inline(always)]
+    pub fn red_insel(&mut self) -> RED_INSEL_W<DB_CFG_SPEC> {
+        RED_INSEL_W::new(self, 11)
+    }
+    #[doc = "Bit 12 - S5 in documentation"]
+    #[inline(always)]
+    pub fn fed_insel(&mut self) -> FED_INSEL_W<DB_CFG_SPEC> {
+        FED_INSEL_W::new(self, 12)
+    }
+    #[doc = "Bit 13 - S2 in documentation"]
+    #[inline(always)]
+    pub fn red_outinvert(&mut self) -> RED_OUTINVERT_W<DB_CFG_SPEC> {
+        RED_OUTINVERT_W::new(self, 13)
+    }
+    #[doc = "Bit 14 - S3 in documentation"]
+    #[inline(always)]
+    pub fn fed_outinvert(&mut self) -> FED_OUTINVERT_W<DB_CFG_SPEC> {
+        FED_OUTINVERT_W::new(self, 14)
+    }
+    #[doc = "Bit 15 - S1 in documentation"]
+    #[inline(always)]
+    pub fn a_outbypass(&mut self) -> A_OUTBYPASS_W<DB_CFG_SPEC> {
+        A_OUTBYPASS_W::new(self, 15)
+    }
+    #[doc = "Bit 16 - S0 in documentation"]
+    #[inline(always)]
+    pub fn b_outbypass(&mut self) -> B_OUTBYPASS_W<DB_CFG_SPEC> {
+        B_OUTBYPASS_W::new(self, 16)
+    }
+    #[doc = "Bit 17 - Dead time generator 0 clock selection. 0: PWM_clk, 1: PT_clk"]
+    #[inline(always)]
+    pub fn clk_sel(&mut self) -> CLK_SEL_W<DB_CFG_SPEC> {
+        CLK_SEL_W::new(self, 17)
+    }
+}
+#[doc = "dead time type selection and configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`db_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`db_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DB_CFG_SPEC;
+impl crate::RegisterSpec for DB_CFG_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`db_cfg::R`](R) reader structure"]
+impl crate::Readable for DB_CFG_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`db_cfg::W`](W) writer structure"]
+impl crate::Writable for DB_CFG_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DB_CFG to value 0x0001_8000"]
+impl crate::Resettable for DB_CFG_SPEC {
+    const RESET_VALUE: u32 = 0x0001_8000;
+}

vendor/esp32s3/src/mcpwm0/ch/db_fed_cfg.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `DB_FED_CFG` reader"]
+pub type R = crate::R<DB_FED_CFG_SPEC>;
+#[doc = "Register `DB_FED_CFG` writer"]
+pub type W = crate::W<DB_FED_CFG_SPEC>;
+#[doc = "Field `FED` reader - Shadow register for FED"]
+pub type FED_R = crate::FieldReader<u16>;
+#[doc = "Field `FED` writer - Shadow register for FED"]
+pub type FED_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
+impl R {
+    #[doc = "Bits 0:15 - Shadow register for FED"]
+    #[inline(always)]
+    pub fn fed(&self) -> FED_R {
+        FED_R::new((self.bits & 0xffff) as u16)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DB_FED_CFG")
+            .field("fed", &self.fed())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:15 - Shadow register for FED"]
+    #[inline(always)]
+    pub fn fed(&mut self) -> FED_W<DB_FED_CFG_SPEC> {
+        FED_W::new(self, 0)
+    }
+}
+#[doc = "Shadow register for falling edge delay (FED).\n\nYou can [`read`](crate::Reg::read) this register and get [`db_fed_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`db_fed_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DB_FED_CFG_SPEC;
+impl crate::RegisterSpec for DB_FED_CFG_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`db_fed_cfg::R`](R) reader structure"]
+impl crate::Readable for DB_FED_CFG_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`db_fed_cfg::W`](W) writer structure"]
+impl crate::Writable for DB_FED_CFG_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DB_FED_CFG to value 0"]
+impl crate::Resettable for DB_FED_CFG_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/mcpwm0/ch/db_red_cfg.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `DB_RED_CFG` reader"]
+pub type R = crate::R<DB_RED_CFG_SPEC>;
+#[doc = "Register `DB_RED_CFG` writer"]
+pub type W = crate::W<DB_RED_CFG_SPEC>;
+#[doc = "Field `RED` reader - Shadow register for RED"]
+pub type RED_R = crate::FieldReader<u16>;
+#[doc = "Field `RED` writer - Shadow register for RED"]
+pub type RED_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
+impl R {
+    #[doc = "Bits 0:15 - Shadow register for RED"]
+    #[inline(always)]
+    pub fn red(&self) -> RED_R {
+        RED_R::new((self.bits & 0xffff) as u16)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DB_RED_CFG")
+            .field("red", &self.red())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:15 - Shadow register for RED"]
+    #[inline(always)]
+    pub fn red(&mut self) -> RED_W<DB_RED_CFG_SPEC> {
+        RED_W::new(self, 0)
+    }
+}
+#[doc = "Shadow register for rising edge delay (RED).\n\nYou can [`read`](crate::Reg::read) this register and get [`db_red_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`db_red_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DB_RED_CFG_SPEC;
+impl crate::RegisterSpec for DB_RED_CFG_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`db_red_cfg::R`](R) reader structure"]
+impl crate::Readable for DB_RED_CFG_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`db_red_cfg::W`](W) writer structure"]
+impl crate::Writable for DB_RED_CFG_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DB_RED_CFG to value 0"]
+impl crate::Resettable for DB_RED_CFG_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/mcpwm0/ch/gen.rs

@@ -0,0 +1,212 @@
+#[doc = "Register `GEN%s` reader"]
+pub type R = crate::R<GEN_SPEC>;
+#[doc = "Register `GEN%s` writer"]
+pub type W = crate::W<GEN_SPEC>;
+#[doc = "Field `UTEZ` reader - Action on PWM0A triggered by event TEZ when timer increasing"]
+pub type UTEZ_R = crate::FieldReader;
+#[doc = "Field `UTEZ` writer - Action on PWM0A triggered by event TEZ when timer increasing"]
+pub type UTEZ_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `UTEP` reader - Action on PWM0A triggered by event TEP when timer increasing"]
+pub type UTEP_R = crate::FieldReader;
+#[doc = "Field `UTEP` writer - Action on PWM0A triggered by event TEP when timer increasing"]
+pub type UTEP_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `UTEA` reader - Action on PWM0A triggered by event TEA when timer increasing"]
+pub type UTEA_R = crate::FieldReader;
+#[doc = "Field `UTEA` writer - Action on PWM0A triggered by event TEA when timer increasing"]
+pub type UTEA_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `UTEB` reader - Action on PWM0A triggered by event TEB when timer increasing"]
+pub type UTEB_R = crate::FieldReader;
+#[doc = "Field `UTEB` writer - Action on PWM0A triggered by event TEB when timer increasing"]
+pub type UTEB_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `UT0` reader - Action on PWM0A triggered by event_t0 when timer increasing"]
+pub type UT0_R = crate::FieldReader;
+#[doc = "Field `UT0` writer - Action on PWM0A triggered by event_t0 when timer increasing"]
+pub type UT0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `UT1` reader - Action on PWM0A triggered by event_t1 when timer increasing"]
+pub type UT1_R = crate::FieldReader;
+#[doc = "Field `UT1` writer - Action on PWM0A triggered by event_t1 when timer increasing"]
+pub type UT1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `DTEZ` reader - Action on PWM0A triggered by event TEZ when timer decreasing"]
+pub type DTEZ_R = crate::FieldReader;
+#[doc = "Field `DTEZ` writer - Action on PWM0A triggered by event TEZ when timer decreasing"]
+pub type DTEZ_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `DTEP` reader - Action on PWM0A triggered by event TEP when timer decreasing"]
+pub type DTEP_R = crate::FieldReader;
+#[doc = "Field `DTEP` writer - Action on PWM0A triggered by event TEP when timer decreasing"]
+pub type DTEP_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `DTEA` reader - Action on PWM0A triggered by event TEA when timer decreasing"]
+pub type DTEA_R = crate::FieldReader;
+#[doc = "Field `DTEA` writer - Action on PWM0A triggered by event TEA when timer decreasing"]
+pub type DTEA_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `DTEB` reader - Action on PWM0A triggered by event TEB when timer decreasing"]
+pub type DTEB_R = crate::FieldReader;
+#[doc = "Field `DTEB` writer - Action on PWM0A triggered by event TEB when timer decreasing"]
+pub type DTEB_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `DT0` reader - Action on PWM0A triggered by event_t0 when timer decreasing"]
+pub type DT0_R = crate::FieldReader;
+#[doc = "Field `DT0` writer - Action on PWM0A triggered by event_t0 when timer decreasing"]
+pub type DT0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `DT1` reader - Action on PWM0A triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle"]
+pub type DT1_R = crate::FieldReader;
+#[doc = "Field `DT1` writer - Action on PWM0A triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle"]
+pub type DT1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+impl R {
+    #[doc = "Bits 0:1 - Action on PWM0A triggered by event TEZ when timer increasing"]
+    #[inline(always)]
+    pub fn utez(&self) -> UTEZ_R {
+        UTEZ_R::new((self.bits & 3) as u8)
+    }
+    #[doc = "Bits 2:3 - Action on PWM0A triggered by event TEP when timer increasing"]
+    #[inline(always)]
+    pub fn utep(&self) -> UTEP_R {
+        UTEP_R::new(((self.bits >> 2) & 3) as u8)
+    }
+    #[doc = "Bits 4:5 - Action on PWM0A triggered by event TEA when timer increasing"]
+    #[inline(always)]
+    pub fn utea(&self) -> UTEA_R {
+        UTEA_R::new(((self.bits >> 4) & 3) as u8)
+    }
+    #[doc = "Bits 6:7 - Action on PWM0A triggered by event TEB when timer increasing"]
+    #[inline(always)]
+    pub fn uteb(&self) -> UTEB_R {
+        UTEB_R::new(((self.bits >> 6) & 3) as u8)
+    }
+    #[doc = "Bits 8:9 - Action on PWM0A triggered by event_t0 when timer increasing"]
+    #[inline(always)]
+    pub fn ut0(&self) -> UT0_R {
+        UT0_R::new(((self.bits >> 8) & 3) as u8)
+    }
+    #[doc = "Bits 10:11 - Action on PWM0A triggered by event_t1 when timer increasing"]
+    #[inline(always)]
+    pub fn ut1(&self) -> UT1_R {
+        UT1_R::new(((self.bits >> 10) & 3) as u8)
+    }
+    #[doc = "Bits 12:13 - Action on PWM0A triggered by event TEZ when timer decreasing"]
+    #[inline(always)]
+    pub fn dtez(&self) -> DTEZ_R {
+        DTEZ_R::new(((self.bits >> 12) & 3) as u8)
+    }
+    #[doc = "Bits 14:15 - Action on PWM0A triggered by event TEP when timer decreasing"]
+    #[inline(always)]
+    pub fn dtep(&self) -> DTEP_R {
+        DTEP_R::new(((self.bits >> 14) & 3) as u8)
+    }
+    #[doc = "Bits 16:17 - Action on PWM0A triggered by event TEA when timer decreasing"]
+    #[inline(always)]
+    pub fn dtea(&self) -> DTEA_R {
+        DTEA_R::new(((self.bits >> 16) & 3) as u8)
+    }
+    #[doc = "Bits 18:19 - Action on PWM0A triggered by event TEB when timer decreasing"]
+    #[inline(always)]
+    pub fn dteb(&self) -> DTEB_R {
+        DTEB_R::new(((self.bits >> 18) & 3) as u8)
+    }
+    #[doc = "Bits 20:21 - Action on PWM0A triggered by event_t0 when timer decreasing"]
+    #[inline(always)]
+    pub fn dt0(&self) -> DT0_R {
+        DT0_R::new(((self.bits >> 20) & 3) as u8)
+    }
+    #[doc = "Bits 22:23 - Action on PWM0A triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle"]
+    #[inline(always)]
+    pub fn dt1(&self) -> DT1_R {
+        DT1_R::new(((self.bits >> 22) & 3) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("GEN")
+            .field("utez", &self.utez())
+            .field("utep", &self.utep())
+            .field("utea", &self.utea())
+            .field("uteb", &self.uteb())
+            .field("ut0", &self.ut0())
+            .field("ut1", &self.ut1())
+            .field("dtez", &self.dtez())
+            .field("dtep", &self.dtep())
+            .field("dtea", &self.dtea())
+            .field("dteb", &self.dteb())
+            .field("dt0", &self.dt0())
+            .field("dt1", &self.dt1())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:1 - Action on PWM0A triggered by event TEZ when timer increasing"]
+    #[inline(always)]
+    pub fn utez(&mut self) -> UTEZ_W<GEN_SPEC> {
+        UTEZ_W::new(self, 0)
+    }
+    #[doc = "Bits 2:3 - Action on PWM0A triggered by event TEP when timer increasing"]
+    #[inline(always)]
+    pub fn utep(&mut self) -> UTEP_W<GEN_SPEC> {
+        UTEP_W::new(self, 2)
+    }
+    #[doc = "Bits 4:5 - Action on PWM0A triggered by event TEA when timer increasing"]
+    #[inline(always)]
+    pub fn utea(&mut self) -> UTEA_W<GEN_SPEC> {
+        UTEA_W::new(self, 4)
+    }
+    #[doc = "Bits 6:7 - Action on PWM0A triggered by event TEB when timer increasing"]
+    #[inline(always)]
+    pub fn uteb(&mut self) -> UTEB_W<GEN_SPEC> {
+        UTEB_W::new(self, 6)
+    }
+    #[doc = "Bits 8:9 - Action on PWM0A triggered by event_t0 when timer increasing"]
+    #[inline(always)]
+    pub fn ut0(&mut self) -> UT0_W<GEN_SPEC> {
+        UT0_W::new(self, 8)
+    }
+    #[doc = "Bits 10:11 - Action on PWM0A triggered by event_t1 when timer increasing"]
+    #[inline(always)]
+    pub fn ut1(&mut self) -> UT1_W<GEN_SPEC> {
+        UT1_W::new(self, 10)
+    }
+    #[doc = "Bits 12:13 - Action on PWM0A triggered by event TEZ when timer decreasing"]
+    #[inline(always)]
+    pub fn dtez(&mut self) -> DTEZ_W<GEN_SPEC> {
+        DTEZ_W::new(self, 12)
+    }
+    #[doc = "Bits 14:15 - Action on PWM0A triggered by event TEP when timer decreasing"]
+    #[inline(always)]
+    pub fn dtep(&mut self) -> DTEP_W<GEN_SPEC> {
+        DTEP_W::new(self, 14)
+    }
+    #[doc = "Bits 16:17 - Action on PWM0A triggered by event TEA when timer decreasing"]
+    #[inline(always)]
+    pub fn dtea(&mut self) -> DTEA_W<GEN_SPEC> {
+        DTEA_W::new(self, 16)
+    }
+    #[doc = "Bits 18:19 - Action on PWM0A triggered by event TEB when timer decreasing"]
+    #[inline(always)]
+    pub fn dteb(&mut self) -> DTEB_W<GEN_SPEC> {
+        DTEB_W::new(self, 18)
+    }
+    #[doc = "Bits 20:21 - Action on PWM0A triggered by event_t0 when timer decreasing"]
+    #[inline(always)]
+    pub fn dt0(&mut self) -> DT0_W<GEN_SPEC> {
+        DT0_W::new(self, 20)
+    }
+    #[doc = "Bits 22:23 - Action on PWM0A triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle"]
+    #[inline(always)]
+    pub fn dt1(&mut self) -> DT1_W<GEN_SPEC> {
+        DT1_W::new(self, 22)
+    }
+}
+#[doc = "Actions triggered by events on PWMx%s\n\nYou can [`read`](crate::Reg::read) this register and get [`gen::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gen::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct GEN_SPEC;
+impl crate::RegisterSpec for GEN_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`gen::R`](R) reader structure"]
+impl crate::Readable for GEN_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`gen::W`](W) writer structure"]
+impl crate::Writable for GEN_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets GEN%s to value 0"]
+impl crate::Resettable for GEN_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/mcpwm0/ch/gen_cfg0.rs

@@ -0,0 +1,77 @@
+#[doc = "Register `GEN_CFG0` reader"]
+pub type R = crate::R<GEN_CFG0_SPEC>;
+#[doc = "Register `GEN_CFG0` writer"]
+pub type W = crate::W<GEN_CFG0_SPEC>;
+#[doc = "Field `CFG_UPMETHOD` reader - Update method for PWM generator 0's active register of configuration. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1:"]
+pub type CFG_UPMETHOD_R = crate::FieldReader;
+#[doc = "Field `CFG_UPMETHOD` writer - Update method for PWM generator 0's active register of configuration. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1:"]
+pub type CFG_UPMETHOD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `T0_SEL` reader - Source selection for PWM generator 0 event_t0, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none"]
+pub type T0_SEL_R = crate::FieldReader;
+#[doc = "Field `T0_SEL` writer - Source selection for PWM generator 0 event_t0, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none"]
+pub type T0_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `T1_SEL` reader - Source selection for PWM generator 0 event_t1, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none"]
+pub type T1_SEL_R = crate::FieldReader;
+#[doc = "Field `T1_SEL` writer - Source selection for PWM generator 0 event_t1, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none"]
+pub type T1_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+impl R {
+    #[doc = "Bits 0:3 - Update method for PWM generator 0's active register of configuration. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1:"]
+    #[inline(always)]
+    pub fn cfg_upmethod(&self) -> CFG_UPMETHOD_R {
+        CFG_UPMETHOD_R::new((self.bits & 0x0f) as u8)
+    }
+    #[doc = "Bits 4:6 - Source selection for PWM generator 0 event_t0, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none"]
+    #[inline(always)]
+    pub fn t0_sel(&self) -> T0_SEL_R {
+        T0_SEL_R::new(((self.bits >> 4) & 7) as u8)
+    }
+    #[doc = "Bits 7:9 - Source selection for PWM generator 0 event_t1, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none"]
+    #[inline(always)]
+    pub fn t1_sel(&self) -> T1_SEL_R {
+        T1_SEL_R::new(((self.bits >> 7) & 7) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("GEN_CFG0")
+            .field("cfg_upmethod", &self.cfg_upmethod())
+            .field("t0_sel", &self.t0_sel())
+            .field("t1_sel", &self.t1_sel())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:3 - Update method for PWM generator 0's active register of configuration. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1:"]
+    #[inline(always)]
+    pub fn cfg_upmethod(&mut self) -> CFG_UPMETHOD_W<GEN_CFG0_SPEC> {
+        CFG_UPMETHOD_W::new(self, 0)
+    }
+    #[doc = "Bits 4:6 - Source selection for PWM generator 0 event_t0, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none"]
+    #[inline(always)]
+    pub fn t0_sel(&mut self) -> T0_SEL_W<GEN_CFG0_SPEC> {
+        T0_SEL_W::new(self, 4)
+    }
+    #[doc = "Bits 7:9 - Source selection for PWM generator 0 event_t1, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none"]
+    #[inline(always)]
+    pub fn t1_sel(&mut self) -> T1_SEL_W<GEN_CFG0_SPEC> {
+        T1_SEL_W::new(self, 7)
+    }
+}
+#[doc = "Fault event T0 and T1 handling\n\nYou can [`read`](crate::Reg::read) this register and get [`gen_cfg0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gen_cfg0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct GEN_CFG0_SPEC;
+impl crate::RegisterSpec for GEN_CFG0_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`gen_cfg0::R`](R) reader structure"]
+impl crate::Readable for GEN_CFG0_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`gen_cfg0::W`](W) writer structure"]
+impl crate::Writable for GEN_CFG0_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets GEN_CFG0 to value 0"]
+impl crate::Resettable for GEN_CFG0_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/mcpwm0/ch/gen_force.rs

@@ -0,0 +1,137 @@
+#[doc = "Register `GEN_FORCE` reader"]
+pub type R = crate::R<GEN_FORCE_SPEC>;
+#[doc = "Register `GEN_FORCE` writer"]
+pub type W = crate::W<GEN_FORCE_SPEC>;
+#[doc = "Field `CNTUFORCE_UPMETHOD` reader - Updating method for continuous software force of PWM generator0. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, when bit5 is set to 1: disable update. (TEA/B here and below means an event generated when the timer's value equals to that of register A/B.)"]
+pub type CNTUFORCE_UPMETHOD_R = crate::FieldReader;
+#[doc = "Field `CNTUFORCE_UPMETHOD` writer - Updating method for continuous software force of PWM generator0. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, when bit5 is set to 1: disable update. (TEA/B here and below means an event generated when the timer's value equals to that of register A/B.)"]
+pub type CNTUFORCE_UPMETHOD_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
+#[doc = "Field `A_CNTUFORCE_MODE` reader - Continuous software force mode for PWM0A. 0: disabled, 1: low, 2: high, 3: disabled"]
+pub type A_CNTUFORCE_MODE_R = crate::FieldReader;
+#[doc = "Field `A_CNTUFORCE_MODE` writer - Continuous software force mode for PWM0A. 0: disabled, 1: low, 2: high, 3: disabled"]
+pub type A_CNTUFORCE_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `B_CNTUFORCE_MODE` reader - Continuous software force mode for PWM0B. 0: disabled, 1: low, 2: high, 3: disabled"]
+pub type B_CNTUFORCE_MODE_R = crate::FieldReader;
+#[doc = "Field `B_CNTUFORCE_MODE` writer - Continuous software force mode for PWM0B. 0: disabled, 1: low, 2: high, 3: disabled"]
+pub type B_CNTUFORCE_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `A_NCIFORCE` reader - Trigger of non-continuous immediate software-force event for PWM0A, a toggle will trigger a force event."]
+pub type A_NCIFORCE_R = crate::BitReader;
+#[doc = "Field `A_NCIFORCE` writer - Trigger of non-continuous immediate software-force event for PWM0A, a toggle will trigger a force event."]
+pub type A_NCIFORCE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `A_NCIFORCE_MODE` reader - non-continuous immediate software force mode for PWM0A, 0: disabled, 1: low, 2: high, 3: disabled"]
+pub type A_NCIFORCE_MODE_R = crate::FieldReader;
+#[doc = "Field `A_NCIFORCE_MODE` writer - non-continuous immediate software force mode for PWM0A, 0: disabled, 1: low, 2: high, 3: disabled"]
+pub type A_NCIFORCE_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `B_NCIFORCE` reader - Trigger of non-continuous immediate software-force event for PWM0B, a toggle will trigger a force event."]
+pub type B_NCIFORCE_R = crate::BitReader;
+#[doc = "Field `B_NCIFORCE` writer - Trigger of non-continuous immediate software-force event for PWM0B, a toggle will trigger a force event."]
+pub type B_NCIFORCE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `B_NCIFORCE_MODE` reader - non-continuous immediate software force mode for PWM0B, 0: disabled, 1: low, 2: high, 3: disabled"]
+pub type B_NCIFORCE_MODE_R = crate::FieldReader;
+#[doc = "Field `B_NCIFORCE_MODE` writer - non-continuous immediate software force mode for PWM0B, 0: disabled, 1: low, 2: high, 3: disabled"]
+pub type B_NCIFORCE_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+impl R {
+    #[doc = "Bits 0:5 - Updating method for continuous software force of PWM generator0. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, when bit5 is set to 1: disable update. (TEA/B here and below means an event generated when the timer's value equals to that of register A/B.)"]
+    #[inline(always)]
+    pub fn cntuforce_upmethod(&self) -> CNTUFORCE_UPMETHOD_R {
+        CNTUFORCE_UPMETHOD_R::new((self.bits & 0x3f) as u8)
+    }
+    #[doc = "Bits 6:7 - Continuous software force mode for PWM0A. 0: disabled, 1: low, 2: high, 3: disabled"]
+    #[inline(always)]
+    pub fn a_cntuforce_mode(&self) -> A_CNTUFORCE_MODE_R {
+        A_CNTUFORCE_MODE_R::new(((self.bits >> 6) & 3) as u8)
+    }
+    #[doc = "Bits 8:9 - Continuous software force mode for PWM0B. 0: disabled, 1: low, 2: high, 3: disabled"]
+    #[inline(always)]
+    pub fn b_cntuforce_mode(&self) -> B_CNTUFORCE_MODE_R {
+        B_CNTUFORCE_MODE_R::new(((self.bits >> 8) & 3) as u8)
+    }
+    #[doc = "Bit 10 - Trigger of non-continuous immediate software-force event for PWM0A, a toggle will trigger a force event."]
+    #[inline(always)]
+    pub fn a_nciforce(&self) -> A_NCIFORCE_R {
+        A_NCIFORCE_R::new(((self.bits >> 10) & 1) != 0)
+    }
+    #[doc = "Bits 11:12 - non-continuous immediate software force mode for PWM0A, 0: disabled, 1: low, 2: high, 3: disabled"]
+    #[inline(always)]
+    pub fn a_nciforce_mode(&self) -> A_NCIFORCE_MODE_R {
+        A_NCIFORCE_MODE_R::new(((self.bits >> 11) & 3) as u8)
+    }
+    #[doc = "Bit 13 - Trigger of non-continuous immediate software-force event for PWM0B, a toggle will trigger a force event."]
+    #[inline(always)]
+    pub fn b_nciforce(&self) -> B_NCIFORCE_R {
+        B_NCIFORCE_R::new(((self.bits >> 13) & 1) != 0)
+    }
+    #[doc = "Bits 14:15 - non-continuous immediate software force mode for PWM0B, 0: disabled, 1: low, 2: high, 3: disabled"]
+    #[inline(always)]
+    pub fn b_nciforce_mode(&self) -> B_NCIFORCE_MODE_R {
+        B_NCIFORCE_MODE_R::new(((self.bits >> 14) & 3) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("GEN_FORCE")
+            .field("cntuforce_upmethod", &self.cntuforce_upmethod())
+            .field("a_cntuforce_mode", &self.a_cntuforce_mode())
+            .field("b_cntuforce_mode", &self.b_cntuforce_mode())
+            .field("a_nciforce", &self.a_nciforce())
+            .field("a_nciforce_mode", &self.a_nciforce_mode())
+            .field("b_nciforce", &self.b_nciforce())
+            .field("b_nciforce_mode", &self.b_nciforce_mode())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:5 - Updating method for continuous software force of PWM generator0. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, when bit5 is set to 1: disable update. (TEA/B here and below means an event generated when the timer's value equals to that of register A/B.)"]
+    #[inline(always)]
+    pub fn cntuforce_upmethod(&mut self) -> CNTUFORCE_UPMETHOD_W<GEN_FORCE_SPEC> {
+        CNTUFORCE_UPMETHOD_W::new(self, 0)
+    }
+    #[doc = "Bits 6:7 - Continuous software force mode for PWM0A. 0: disabled, 1: low, 2: high, 3: disabled"]
+    #[inline(always)]
+    pub fn a_cntuforce_mode(&mut self) -> A_CNTUFORCE_MODE_W<GEN_FORCE_SPEC> {
+        A_CNTUFORCE_MODE_W::new(self, 6)
+    }
+    #[doc = "Bits 8:9 - Continuous software force mode for PWM0B. 0: disabled, 1: low, 2: high, 3: disabled"]
+    #[inline(always)]
+    pub fn b_cntuforce_mode(&mut self) -> B_CNTUFORCE_MODE_W<GEN_FORCE_SPEC> {
+        B_CNTUFORCE_MODE_W::new(self, 8)
+    }
+    #[doc = "Bit 10 - Trigger of non-continuous immediate software-force event for PWM0A, a toggle will trigger a force event."]
+    #[inline(always)]
+    pub fn a_nciforce(&mut self) -> A_NCIFORCE_W<GEN_FORCE_SPEC> {
+        A_NCIFORCE_W::new(self, 10)
+    }
+    #[doc = "Bits 11:12 - non-continuous immediate software force mode for PWM0A, 0: disabled, 1: low, 2: high, 3: disabled"]
+    #[inline(always)]
+    pub fn a_nciforce_mode(&mut self) -> A_NCIFORCE_MODE_W<GEN_FORCE_SPEC> {
+        A_NCIFORCE_MODE_W::new(self, 11)
+    }
+    #[doc = "Bit 13 - Trigger of non-continuous immediate software-force event for PWM0B, a toggle will trigger a force event."]
+    #[inline(always)]
+    pub fn b_nciforce(&mut self) -> B_NCIFORCE_W<GEN_FORCE_SPEC> {
+        B_NCIFORCE_W::new(self, 13)
+    }
+    #[doc = "Bits 14:15 - non-continuous immediate software force mode for PWM0B, 0: disabled, 1: low, 2: high, 3: disabled"]
+    #[inline(always)]
+    pub fn b_nciforce_mode(&mut self) -> B_NCIFORCE_MODE_W<GEN_FORCE_SPEC> {
+        B_NCIFORCE_MODE_W::new(self, 14)
+    }
+}
+#[doc = "Permissives to force PWMxA and PWMxB outputs by software\n\nYou can [`read`](crate::Reg::read) this register and get [`gen_force::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gen_force::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct GEN_FORCE_SPEC;
+impl crate::RegisterSpec for GEN_FORCE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`gen_force::R`](R) reader structure"]
+impl crate::Readable for GEN_FORCE_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`gen_force::W`](W) writer structure"]
+impl crate::Writable for GEN_FORCE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets GEN_FORCE to value 0x20"]
+impl crate::Resettable for GEN_FORCE_SPEC {
+    const RESET_VALUE: u32 = 0x20;
+}

vendor/esp32s3/src/mcpwm0/ch/tz_cfg0.rs

@@ -0,0 +1,272 @@
+#[doc = "Register `TZ_CFG0` reader"]
+pub type R = crate::R<TZ_CFG0_SPEC>;
+#[doc = "Register `TZ_CFG0` writer"]
+pub type W = crate::W<TZ_CFG0_SPEC>;
+#[doc = "Field `SW_CBC` reader - Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable"]
+pub type SW_CBC_R = crate::BitReader;
+#[doc = "Field `SW_CBC` writer - Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable"]
+pub type SW_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `F2_CBC` reader - event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable"]
+pub type F2_CBC_R = crate::BitReader;
+#[doc = "Field `F2_CBC` writer - event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable"]
+pub type F2_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `F1_CBC` reader - event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable"]
+pub type F1_CBC_R = crate::BitReader;
+#[doc = "Field `F1_CBC` writer - event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable"]
+pub type F1_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `F0_CBC` reader - event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable"]
+pub type F0_CBC_R = crate::BitReader;
+#[doc = "Field `F0_CBC` writer - event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable"]
+pub type F0_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SW_OST` reader - Enable register for software force one-shot mode action. 0: disable, 1: enable"]
+pub type SW_OST_R = crate::BitReader;
+#[doc = "Field `SW_OST` writer - Enable register for software force one-shot mode action. 0: disable, 1: enable"]
+pub type SW_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `F2_OST` reader - event_f2 will trigger one-shot mode action. 0: disable, 1: enable"]
+pub type F2_OST_R = crate::BitReader;
+#[doc = "Field `F2_OST` writer - event_f2 will trigger one-shot mode action. 0: disable, 1: enable"]
+pub type F2_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `F1_OST` reader - event_f1 will trigger one-shot mode action. 0: disable, 1: enable"]
+pub type F1_OST_R = crate::BitReader;
+#[doc = "Field `F1_OST` writer - event_f1 will trigger one-shot mode action. 0: disable, 1: enable"]
+pub type F1_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `F0_OST` reader - event_f0 will trigger one-shot mode action. 0: disable, 1: enable"]
+pub type F0_OST_R = crate::BitReader;
+#[doc = "Field `F0_OST` writer - event_f0 will trigger one-shot mode action. 0: disable, 1: enable"]
+pub type F0_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `A_CBC_D` reader - Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle"]
+pub type A_CBC_D_R = crate::FieldReader;
+#[doc = "Field `A_CBC_D` writer - Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle"]
+pub type A_CBC_D_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `A_CBC_U` reader - Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle"]
+pub type A_CBC_U_R = crate::FieldReader;
+#[doc = "Field `A_CBC_U` writer - Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle"]
+pub type A_CBC_U_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `A_OST_D` reader - One-shot mode action on PWM0A when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle"]
+pub type A_OST_D_R = crate::FieldReader;
+#[doc = "Field `A_OST_D` writer - One-shot mode action on PWM0A when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle"]
+pub type A_OST_D_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `A_OST_U` reader - One-shot mode action on PWM0A when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle"]
+pub type A_OST_U_R = crate::FieldReader;
+#[doc = "Field `A_OST_U` writer - One-shot mode action on PWM0A when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle"]
+pub type A_OST_U_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `B_CBC_D` reader - Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle"]
+pub type B_CBC_D_R = crate::FieldReader;
+#[doc = "Field `B_CBC_D` writer - Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle"]
+pub type B_CBC_D_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `B_CBC_U` reader - Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle"]
+pub type B_CBC_U_R = crate::FieldReader;
+#[doc = "Field `B_CBC_U` writer - Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle"]
+pub type B_CBC_U_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `B_OST_D` reader - One-shot mode action on PWM0B when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle"]
+pub type B_OST_D_R = crate::FieldReader;
+#[doc = "Field `B_OST_D` writer - One-shot mode action on PWM0B when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle"]
+pub type B_OST_D_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `B_OST_U` reader - One-shot mode action on PWM0B when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle"]
+pub type B_OST_U_R = crate::FieldReader;
+#[doc = "Field `B_OST_U` writer - One-shot mode action on PWM0B when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle"]
+pub type B_OST_U_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+impl R {
+    #[doc = "Bit 0 - Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable"]
+    #[inline(always)]
+    pub fn sw_cbc(&self) -> SW_CBC_R {
+        SW_CBC_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable"]
+    #[inline(always)]
+    pub fn f2_cbc(&self) -> F2_CBC_R {
+        F2_CBC_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable"]
+    #[inline(always)]
+    pub fn f1_cbc(&self) -> F1_CBC_R {
+        F1_CBC_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable"]
+    #[inline(always)]
+    pub fn f0_cbc(&self) -> F0_CBC_R {
+        F0_CBC_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Enable register for software force one-shot mode action. 0: disable, 1: enable"]
+    #[inline(always)]
+    pub fn sw_ost(&self) -> SW_OST_R {
+        SW_OST_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - event_f2 will trigger one-shot mode action. 0: disable, 1: enable"]
+    #[inline(always)]
+    pub fn f2_ost(&self) -> F2_OST_R {
+        F2_OST_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - event_f1 will trigger one-shot mode action. 0: disable, 1: enable"]
+    #[inline(always)]
+    pub fn f1_ost(&self) -> F1_OST_R {
+        F1_OST_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - event_f0 will trigger one-shot mode action. 0: disable, 1: enable"]
+    #[inline(always)]
+    pub fn f0_ost(&self) -> F0_OST_R {
+        F0_OST_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bits 8:9 - Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle"]
+    #[inline(always)]
+    pub fn a_cbc_d(&self) -> A_CBC_D_R {
+        A_CBC_D_R::new(((self.bits >> 8) & 3) as u8)
+    }
+    #[doc = "Bits 10:11 - Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle"]
+    #[inline(always)]
+    pub fn a_cbc_u(&self) -> A_CBC_U_R {
+        A_CBC_U_R::new(((self.bits >> 10) & 3) as u8)
+    }
+    #[doc = "Bits 12:13 - One-shot mode action on PWM0A when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle"]
+    #[inline(always)]
+    pub fn a_ost_d(&self) -> A_OST_D_R {
+        A_OST_D_R::new(((self.bits >> 12) & 3) as u8)
+    }
+    #[doc = "Bits 14:15 - One-shot mode action on PWM0A when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle"]
+    #[inline(always)]
+    pub fn a_ost_u(&self) -> A_OST_U_R {
+        A_OST_U_R::new(((self.bits >> 14) & 3) as u8)
+    }
+    #[doc = "Bits 16:17 - Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle"]
+    #[inline(always)]
+    pub fn b_cbc_d(&self) -> B_CBC_D_R {
+        B_CBC_D_R::new(((self.bits >> 16) & 3) as u8)
+    }
+    #[doc = "Bits 18:19 - Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle"]
+    #[inline(always)]
+    pub fn b_cbc_u(&self) -> B_CBC_U_R {
+        B_CBC_U_R::new(((self.bits >> 18) & 3) as u8)
+    }
+    #[doc = "Bits 20:21 - One-shot mode action on PWM0B when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle"]
+    #[inline(always)]
+    pub fn b_ost_d(&self) -> B_OST_D_R {
+        B_OST_D_R::new(((self.bits >> 20) & 3) as u8)
+    }
+    #[doc = "Bits 22:23 - One-shot mode action on PWM0B when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle"]
+    #[inline(always)]
+    pub fn b_ost_u(&self) -> B_OST_U_R {
+        B_OST_U_R::new(((self.bits >> 22) & 3) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("TZ_CFG0")
+            .field("sw_cbc", &self.sw_cbc())
+            .field("f2_cbc", &self.f2_cbc())
+            .field("f1_cbc", &self.f1_cbc())
+            .field("f0_cbc", &self.f0_cbc())
+            .field("sw_ost", &self.sw_ost())
+            .field("f2_ost", &self.f2_ost())
+            .field("f1_ost", &self.f1_ost())
+            .field("f0_ost", &self.f0_ost())
+            .field("a_cbc_d", &self.a_cbc_d())
+            .field("a_cbc_u", &self.a_cbc_u())
+            .field("a_ost_d", &self.a_ost_d())
+            .field("a_ost_u", &self.a_ost_u())
+            .field("b_cbc_d", &self.b_cbc_d())
+            .field("b_cbc_u", &self.b_cbc_u())
+            .field("b_ost_d", &self.b_ost_d())
+            .field("b_ost_u", &self.b_ost_u())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable"]
+    #[inline(always)]
+    pub fn sw_cbc(&mut self) -> SW_CBC_W<TZ_CFG0_SPEC> {
+        SW_CBC_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable"]
+    #[inline(always)]
+    pub fn f2_cbc(&mut self) -> F2_CBC_W<TZ_CFG0_SPEC> {
+        F2_CBC_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable"]
+    #[inline(always)]
+    pub fn f1_cbc(&mut self) -> F1_CBC_W<TZ_CFG0_SPEC> {
+        F1_CBC_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable"]
+    #[inline(always)]
+    pub fn f0_cbc(&mut self) -> F0_CBC_W<TZ_CFG0_SPEC> {
+        F0_CBC_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - Enable register for software force one-shot mode action. 0: disable, 1: enable"]
+    #[inline(always)]
+    pub fn sw_ost(&mut self) -> SW_OST_W<TZ_CFG0_SPEC> {
+        SW_OST_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - event_f2 will trigger one-shot mode action. 0: disable, 1: enable"]
+    #[inline(always)]
+    pub fn f2_ost(&mut self) -> F2_OST_W<TZ_CFG0_SPEC> {
+        F2_OST_W::new(self, 5)
+    }
+    #[doc = "Bit 6 - event_f1 will trigger one-shot mode action. 0: disable, 1: enable"]
+    #[inline(always)]
+    pub fn f1_ost(&mut self) -> F1_OST_W<TZ_CFG0_SPEC> {
+        F1_OST_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - event_f0 will trigger one-shot mode action. 0: disable, 1: enable"]
+    #[inline(always)]
+    pub fn f0_ost(&mut self) -> F0_OST_W<TZ_CFG0_SPEC> {
+        F0_OST_W::new(self, 7)
+    }
+    #[doc = "Bits 8:9 - Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle"]
+    #[inline(always)]
+    pub fn a_cbc_d(&mut self) -> A_CBC_D_W<TZ_CFG0_SPEC> {
+        A_CBC_D_W::new(self, 8)
+    }
+    #[doc = "Bits 10:11 - Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle"]
+    #[inline(always)]
+    pub fn a_cbc_u(&mut self) -> A_CBC_U_W<TZ_CFG0_SPEC> {
+        A_CBC_U_W::new(self, 10)
+    }
+    #[doc = "Bits 12:13 - One-shot mode action on PWM0A when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle"]
+    #[inline(always)]
+    pub fn a_ost_d(&mut self) -> A_OST_D_W<TZ_CFG0_SPEC> {
+        A_OST_D_W::new(self, 12)
+    }
+    #[doc = "Bits 14:15 - One-shot mode action on PWM0A when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle"]
+    #[inline(always)]
+    pub fn a_ost_u(&mut self) -> A_OST_U_W<TZ_CFG0_SPEC> {
+        A_OST_U_W::new(self, 14)
+    }
+    #[doc = "Bits 16:17 - Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle"]
+    #[inline(always)]
+    pub fn b_cbc_d(&mut self) -> B_CBC_D_W<TZ_CFG0_SPEC> {
+        B_CBC_D_W::new(self, 16)
+    }
+    #[doc = "Bits 18:19 - Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle"]
+    #[inline(always)]
+    pub fn b_cbc_u(&mut self) -> B_CBC_U_W<TZ_CFG0_SPEC> {
+        B_CBC_U_W::new(self, 18)
+    }
+    #[doc = "Bits 20:21 - One-shot mode action on PWM0B when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle"]
+    #[inline(always)]
+    pub fn b_ost_d(&mut self) -> B_OST_D_W<TZ_CFG0_SPEC> {
+        B_OST_D_W::new(self, 20)
+    }
+    #[doc = "Bits 22:23 - One-shot mode action on PWM0B when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle"]
+    #[inline(always)]
+    pub fn b_ost_u(&mut self) -> B_OST_U_W<TZ_CFG0_SPEC> {
+        B_OST_U_W::new(self, 22)
+    }
+}
+#[doc = "Actions on PWMxA and PWMxB trip events\n\nYou can [`read`](crate::Reg::read) this register and get [`tz_cfg0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tz_cfg0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct TZ_CFG0_SPEC;
+impl crate::RegisterSpec for TZ_CFG0_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`tz_cfg0::R`](R) reader structure"]
+impl crate::Readable for TZ_CFG0_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`tz_cfg0::W`](W) writer structure"]
+impl crate::Writable for TZ_CFG0_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets TZ_CFG0 to value 0"]
+impl crate::Resettable for TZ_CFG0_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/mcpwm0/ch/tz_cfg1.rs

@@ -0,0 +1,92 @@
+#[doc = "Register `TZ_CFG1` reader"]
+pub type R = crate::R<TZ_CFG1_SPEC>;
+#[doc = "Register `TZ_CFG1` writer"]
+pub type W = crate::W<TZ_CFG1_SPEC>;
+#[doc = "Field `CLR_OST` reader - a rising edge will clear on going one-shot mode action"]
+pub type CLR_OST_R = crate::BitReader;
+#[doc = "Field `CLR_OST` writer - a rising edge will clear on going one-shot mode action"]
+pub type CLR_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CBCPULSE` reader - cycle-by-cycle mode action refresh moment selection. Bit0: TEZ, bit1:TEP"]
+pub type CBCPULSE_R = crate::FieldReader;
+#[doc = "Field `CBCPULSE` writer - cycle-by-cycle mode action refresh moment selection. Bit0: TEZ, bit1:TEP"]
+pub type CBCPULSE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `FORCE_CBC` reader - a toggle trigger a cycle-by-cycle mode action"]
+pub type FORCE_CBC_R = crate::BitReader;
+#[doc = "Field `FORCE_CBC` writer - a toggle trigger a cycle-by-cycle mode action"]
+pub type FORCE_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FORCE_OST` reader - a toggle (software negate its value) triggers a one-shot mode action"]
+pub type FORCE_OST_R = crate::BitReader;
+#[doc = "Field `FORCE_OST` writer - a toggle (software negate its value) triggers a one-shot mode action"]
+pub type FORCE_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - a rising edge will clear on going one-shot mode action"]
+    #[inline(always)]
+    pub fn clr_ost(&self) -> CLR_OST_R {
+        CLR_OST_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bits 1:2 - cycle-by-cycle mode action refresh moment selection. Bit0: TEZ, bit1:TEP"]
+    #[inline(always)]
+    pub fn cbcpulse(&self) -> CBCPULSE_R {
+        CBCPULSE_R::new(((self.bits >> 1) & 3) as u8)
+    }
+    #[doc = "Bit 3 - a toggle trigger a cycle-by-cycle mode action"]
+    #[inline(always)]
+    pub fn force_cbc(&self) -> FORCE_CBC_R {
+        FORCE_CBC_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - a toggle (software negate its value) triggers a one-shot mode action"]
+    #[inline(always)]
+    pub fn force_ost(&self) -> FORCE_OST_R {
+        FORCE_OST_R::new(((self.bits >> 4) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("TZ_CFG1")
+            .field("clr_ost", &self.clr_ost())
+            .field("cbcpulse", &self.cbcpulse())
+            .field("force_cbc", &self.force_cbc())
+            .field("force_ost", &self.force_ost())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - a rising edge will clear on going one-shot mode action"]
+    #[inline(always)]
+    pub fn clr_ost(&mut self) -> CLR_OST_W<TZ_CFG1_SPEC> {
+        CLR_OST_W::new(self, 0)
+    }
+    #[doc = "Bits 1:2 - cycle-by-cycle mode action refresh moment selection. Bit0: TEZ, bit1:TEP"]
+    #[inline(always)]
+    pub fn cbcpulse(&mut self) -> CBCPULSE_W<TZ_CFG1_SPEC> {
+        CBCPULSE_W::new(self, 1)
+    }
+    #[doc = "Bit 3 - a toggle trigger a cycle-by-cycle mode action"]
+    #[inline(always)]
+    pub fn force_cbc(&mut self) -> FORCE_CBC_W<TZ_CFG1_SPEC> {
+        FORCE_CBC_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - a toggle (software negate its value) triggers a one-shot mode action"]
+    #[inline(always)]
+    pub fn force_ost(&mut self) -> FORCE_OST_W<TZ_CFG1_SPEC> {
+        FORCE_OST_W::new(self, 4)
+    }
+}
+#[doc = "Software triggers for fault handler actions\n\nYou can [`read`](crate::Reg::read) this register and get [`tz_cfg1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tz_cfg1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct TZ_CFG1_SPEC;
+impl crate::RegisterSpec for TZ_CFG1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`tz_cfg1::R`](R) reader structure"]
+impl crate::Readable for TZ_CFG1_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`tz_cfg1::W`](W) writer structure"]
+impl crate::Writable for TZ_CFG1_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets TZ_CFG1 to value 0"]
+impl crate::Resettable for TZ_CFG1_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/mcpwm0/ch/tz_status.rs

@@ -0,0 +1,38 @@
+#[doc = "Register `TZ_STATUS` reader"]
+pub type R = crate::R<TZ_STATUS_SPEC>;
+#[doc = "Field `CBC_ON` reader - Set and reset by hardware. If set, a cycle-by-cycle mode action is on going"]
+pub type CBC_ON_R = crate::BitReader;
+#[doc = "Field `OST_ON` reader - Set and reset by hardware. If set, an one-shot mode action is on going"]
+pub type OST_ON_R = crate::BitReader;
+impl R {
+    #[doc = "Bit 0 - Set and reset by hardware. If set, a cycle-by-cycle mode action is on going"]
+    #[inline(always)]
+    pub fn cbc_on(&self) -> CBC_ON_R {
+        CBC_ON_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Set and reset by hardware. If set, an one-shot mode action is on going"]
+    #[inline(always)]
+    pub fn ost_on(&self) -> OST_ON_R {
+        OST_ON_R::new(((self.bits >> 1) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("TZ_STATUS")
+            .field("cbc_on", &self.cbc_on())
+            .field("ost_on", &self.ost_on())
+            .finish()
+    }
+}
+#[doc = "Status of fault events.\n\nYou can [`read`](crate::Reg::read) this register and get [`tz_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct TZ_STATUS_SPEC;
+impl crate::RegisterSpec for TZ_STATUS_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`tz_status::R`](R) reader structure"]
+impl crate::Readable for TZ_STATUS_SPEC {}
+#[doc = "`reset()` method sets TZ_STATUS to value 0"]
+impl crate::Resettable for TZ_STATUS_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/mcpwm0/clk.rs

@@ -0,0 +1,45 @@
+#[doc = "Register `CLK` reader"]
+pub type R = crate::R<CLK_SPEC>;
+#[doc = "Register `CLK` writer"]
+pub type W = crate::W<CLK_SPEC>;
+#[doc = "Field `EN` reader - Force clock on for this register file"]
+pub type EN_R = crate::BitReader;
+#[doc = "Field `EN` writer - Force clock on for this register file"]
+pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Force clock on for this register file"]
+    #[inline(always)]
+    pub fn en(&self) -> EN_R {
+        EN_R::new((self.bits & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CLK").field("en", &self.en()).finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Force clock on for this register file"]
+    #[inline(always)]
+    pub fn en(&mut self) -> EN_W<CLK_SPEC> {
+        EN_W::new(self, 0)
+    }
+}
+#[doc = "MCPWM APB configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`clk::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CLK_SPEC;
+impl crate::RegisterSpec for CLK_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`clk::R`](R) reader structure"]
+impl crate::Readable for CLK_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`clk::W`](W) writer structure"]
+impl crate::Writable for CLK_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CLK to value 0"]
+impl crate::Resettable for CLK_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/mcpwm0/clk_cfg.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `CLK_CFG` reader"]
+pub type R = crate::R<CLK_CFG_SPEC>;
+#[doc = "Register `CLK_CFG` writer"]
+pub type W = crate::W<CLK_CFG_SPEC>;
+#[doc = "Field `CLK_PRESCALE` reader - Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)"]
+pub type CLK_PRESCALE_R = crate::FieldReader;
+#[doc = "Field `CLK_PRESCALE` writer - Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)"]
+pub type CLK_PRESCALE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+impl R {
+    #[doc = "Bits 0:7 - Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)"]
+    #[inline(always)]
+    pub fn clk_prescale(&self) -> CLK_PRESCALE_R {
+        CLK_PRESCALE_R::new((self.bits & 0xff) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CLK_CFG")
+            .field("clk_prescale", &self.clk_prescale())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)"]
+    #[inline(always)]
+    pub fn clk_prescale(&mut self) -> CLK_PRESCALE_W<CLK_CFG_SPEC> {
+        CLK_PRESCALE_W::new(self, 0)
+    }
+}
+#[doc = "PWM clock prescaler register.\n\nYou can [`read`](crate::Reg::read) this register and get [`clk_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CLK_CFG_SPEC;
+impl crate::RegisterSpec for CLK_CFG_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`clk_cfg::R`](R) reader structure"]
+impl crate::Readable for CLK_CFG_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`clk_cfg::W`](W) writer structure"]
+impl crate::Writable for CLK_CFG_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CLK_CFG to value 0"]
+impl crate::Resettable for CLK_CFG_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/mcpwm0/fault_detect.rs

@@ -0,0 +1,146 @@
+#[doc = "Register `FAULT_DETECT` reader"]
+pub type R = crate::R<FAULT_DETECT_SPEC>;
+#[doc = "Register `FAULT_DETECT` writer"]
+pub type W = crate::W<FAULT_DETECT_SPEC>;
+#[doc = "Field `F0_EN` reader - When set, event_f0 generation is enabled"]
+pub type F0_EN_R = crate::BitReader;
+#[doc = "Field `F0_EN` writer - When set, event_f0 generation is enabled"]
+pub type F0_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `F1_EN` reader - When set, event_f1 generation is enabled"]
+pub type F1_EN_R = crate::BitReader;
+#[doc = "Field `F1_EN` writer - When set, event_f1 generation is enabled"]
+pub type F1_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `F2_EN` reader - When set, event_f2 generation is enabled"]
+pub type F2_EN_R = crate::BitReader;
+#[doc = "Field `F2_EN` writer - When set, event_f2 generation is enabled"]
+pub type F2_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `F0_POLE` reader - Set event_f0 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high"]
+pub type F0_POLE_R = crate::BitReader;
+#[doc = "Field `F0_POLE` writer - Set event_f0 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high"]
+pub type F0_POLE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `F1_POLE` reader - Set event_f1 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high"]
+pub type F1_POLE_R = crate::BitReader;
+#[doc = "Field `F1_POLE` writer - Set event_f1 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high"]
+pub type F1_POLE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `F2_POLE` reader - Set event_f2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high"]
+pub type F2_POLE_R = crate::BitReader;
+#[doc = "Field `F2_POLE` writer - Set event_f2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high"]
+pub type F2_POLE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `EVENT_F0` reader - Set and reset by hardware. If set, event_f0 is on going"]
+pub type EVENT_F0_R = crate::BitReader;
+#[doc = "Field `EVENT_F1` reader - Set and reset by hardware. If set, event_f1 is on going"]
+pub type EVENT_F1_R = crate::BitReader;
+#[doc = "Field `EVENT_F2` reader - Set and reset by hardware. If set, event_f2 is on going"]
+pub type EVENT_F2_R = crate::BitReader;
+impl R {
+    #[doc = "Bit 0 - When set, event_f0 generation is enabled"]
+    #[inline(always)]
+    pub fn f0_en(&self) -> F0_EN_R {
+        F0_EN_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - When set, event_f1 generation is enabled"]
+    #[inline(always)]
+    pub fn f1_en(&self) -> F1_EN_R {
+        F1_EN_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - When set, event_f2 generation is enabled"]
+    #[inline(always)]
+    pub fn f2_en(&self) -> F2_EN_R {
+        F2_EN_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Set event_f0 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high"]
+    #[inline(always)]
+    pub fn f0_pole(&self) -> F0_POLE_R {
+        F0_POLE_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Set event_f1 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high"]
+    #[inline(always)]
+    pub fn f1_pole(&self) -> F1_POLE_R {
+        F1_POLE_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - Set event_f2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high"]
+    #[inline(always)]
+    pub fn f2_pole(&self) -> F2_POLE_R {
+        F2_POLE_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - Set and reset by hardware. If set, event_f0 is on going"]
+    #[inline(always)]
+    pub fn event_f0(&self) -> EVENT_F0_R {
+        EVENT_F0_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - Set and reset by hardware. If set, event_f1 is on going"]
+    #[inline(always)]
+    pub fn event_f1(&self) -> EVENT_F1_R {
+        EVENT_F1_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - Set and reset by hardware. If set, event_f2 is on going"]
+    #[inline(always)]
+    pub fn event_f2(&self) -> EVENT_F2_R {
+        EVENT_F2_R::new(((self.bits >> 8) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("FAULT_DETECT")
+            .field("f0_en", &self.f0_en())
+            .field("f1_en", &self.f1_en())
+            .field("f2_en", &self.f2_en())
+            .field("f0_pole", &self.f0_pole())
+            .field("f1_pole", &self.f1_pole())
+            .field("f2_pole", &self.f2_pole())
+            .field("event_f0", &self.event_f0())
+            .field("event_f1", &self.event_f1())
+            .field("event_f2", &self.event_f2())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - When set, event_f0 generation is enabled"]
+    #[inline(always)]
+    pub fn f0_en(&mut self) -> F0_EN_W<FAULT_DETECT_SPEC> {
+        F0_EN_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - When set, event_f1 generation is enabled"]
+    #[inline(always)]
+    pub fn f1_en(&mut self) -> F1_EN_W<FAULT_DETECT_SPEC> {
+        F1_EN_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - When set, event_f2 generation is enabled"]
+    #[inline(always)]
+    pub fn f2_en(&mut self) -> F2_EN_W<FAULT_DETECT_SPEC> {
+        F2_EN_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - Set event_f0 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high"]
+    #[inline(always)]
+    pub fn f0_pole(&mut self) -> F0_POLE_W<FAULT_DETECT_SPEC> {
+        F0_POLE_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - Set event_f1 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high"]
+    #[inline(always)]
+    pub fn f1_pole(&mut self) -> F1_POLE_W<FAULT_DETECT_SPEC> {
+        F1_POLE_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - Set event_f2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high"]
+    #[inline(always)]
+    pub fn f2_pole(&mut self) -> F2_POLE_W<FAULT_DETECT_SPEC> {
+        F2_POLE_W::new(self, 5)
+    }
+}
+#[doc = "Fault detection configuration and status\n\nYou can [`read`](crate::Reg::read) this register and get [`fault_detect::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fault_detect::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct FAULT_DETECT_SPEC;
+impl crate::RegisterSpec for FAULT_DETECT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`fault_detect::R`](R) reader structure"]
+impl crate::Readable for FAULT_DETECT_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`fault_detect::W`](W) writer structure"]
+impl crate::Writable for FAULT_DETECT_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets FAULT_DETECT to value 0"]
+impl crate::Resettable for FAULT_DETECT_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/mcpwm0/int_clr.rs

@@ -0,0 +1,235 @@
+#[doc = "Register `INT_CLR` writer"]
+pub type W = crate::W<INT_CLR_SPEC>;
+#[doc = "Field `TIMER0_STOP` writer - Set this bit to clear the interrupt triggered when the timer 0 stops."]
+pub type TIMER0_STOP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TIMER1_STOP` writer - Set this bit to clear the interrupt triggered when the timer 1 stops."]
+pub type TIMER1_STOP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TIMER2_STOP` writer - Set this bit to clear the interrupt triggered when the timer 2 stops."]
+pub type TIMER2_STOP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TIMER0_TEZ` writer - Set this bit to clear the interrupt triggered by a PWM timer 0 TEZ event."]
+pub type TIMER0_TEZ_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TIMER1_TEZ` writer - Set this bit to clear the interrupt triggered by a PWM timer 1 TEZ event."]
+pub type TIMER1_TEZ_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TIMER2_TEZ` writer - Set this bit to clear the interrupt triggered by a PWM timer 2 TEZ event."]
+pub type TIMER2_TEZ_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TIMER0_TEP` writer - Set this bit to clear the interrupt triggered by a PWM timer 0 TEP event."]
+pub type TIMER0_TEP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TIMER1_TEP` writer - Set this bit to clear the interrupt triggered by a PWM timer 1 TEP event."]
+pub type TIMER1_TEP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TIMER2_TEP` writer - Set this bit to clear the interrupt triggered by a PWM timer 2 TEP event."]
+pub type TIMER2_TEP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `FAULT0` writer - Set this bit to clear the interrupt triggered when event_f0 starts."]
+pub type FAULT0_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `FAULT1` writer - Set this bit to clear the interrupt triggered when event_f1 starts."]
+pub type FAULT1_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `FAULT2` writer - Set this bit to clear the interrupt triggered when event_f2 starts."]
+pub type FAULT2_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `FAULT0_CLR` writer - Set this bit to clear the interrupt triggered when event_f0 ends."]
+pub type FAULT0_CLR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `FAULT1_CLR` writer - Set this bit to clear the interrupt triggered when event_f1 ends."]
+pub type FAULT1_CLR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `FAULT2_CLR` writer - Set this bit to clear the interrupt triggered when event_f2 ends."]
+pub type FAULT2_CLR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `CMPR0_TEA` writer - Set this bit to clear the interrupt triggered by a PWM operator 0 TEA event"]
+pub type CMPR0_TEA_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `CMPR1_TEA` writer - Set this bit to clear the interrupt triggered by a PWM operator 1 TEA event"]
+pub type CMPR1_TEA_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `CMPR2_TEA` writer - Set this bit to clear the interrupt triggered by a PWM operator 2 TEA event"]
+pub type CMPR2_TEA_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `CMPR0_TEB` writer - Set this bit to clear the interrupt triggered by a PWM operator 0 TEB event"]
+pub type CMPR0_TEB_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `CMPR1_TEB` writer - Set this bit to clear the interrupt triggered by a PWM operator 1 TEB event"]
+pub type CMPR1_TEB_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `CMPR2_TEB` writer - Set this bit to clear the interrupt triggered by a PWM operator 2 TEB event"]
+pub type CMPR2_TEB_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TZ0_CBC` writer - Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
+pub type TZ0_CBC_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TZ1_CBC` writer - Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
+pub type TZ1_CBC_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TZ2_CBC` writer - Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
+pub type TZ2_CBC_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TZ0_OST` writer - Set this bit to clear the interrupt triggered by a one-shot mode action on PWM0."]
+pub type TZ0_OST_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TZ1_OST` writer - Set this bit to clear the interrupt triggered by a one-shot mode action on PWM1."]
+pub type TZ1_OST_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TZ2_OST` writer - Set this bit to clear the interrupt triggered by a one-shot mode action on PWM2."]
+pub type TZ2_OST_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `CAP0` writer - Set this bit to clear the interrupt triggered by capture on channel 0."]
+pub type CAP0_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `CAP1` writer - Set this bit to clear the interrupt triggered by capture on channel 1."]
+pub type CAP1_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `CAP2` writer - Set this bit to clear the interrupt triggered by capture on channel 2."]
+pub type CAP2_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "(not readable)")
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Set this bit to clear the interrupt triggered when the timer 0 stops."]
+    #[inline(always)]
+    pub fn timer0_stop(&mut self) -> TIMER0_STOP_W<INT_CLR_SPEC> {
+        TIMER0_STOP_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - Set this bit to clear the interrupt triggered when the timer 1 stops."]
+    #[inline(always)]
+    pub fn timer1_stop(&mut self) -> TIMER1_STOP_W<INT_CLR_SPEC> {
+        TIMER1_STOP_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - Set this bit to clear the interrupt triggered when the timer 2 stops."]
+    #[inline(always)]
+    pub fn timer2_stop(&mut self) -> TIMER2_STOP_W<INT_CLR_SPEC> {
+        TIMER2_STOP_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - Set this bit to clear the interrupt triggered by a PWM timer 0 TEZ event."]
+    #[inline(always)]
+    pub fn timer0_tez(&mut self) -> TIMER0_TEZ_W<INT_CLR_SPEC> {
+        TIMER0_TEZ_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - Set this bit to clear the interrupt triggered by a PWM timer 1 TEZ event."]
+    #[inline(always)]
+    pub fn timer1_tez(&mut self) -> TIMER1_TEZ_W<INT_CLR_SPEC> {
+        TIMER1_TEZ_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - Set this bit to clear the interrupt triggered by a PWM timer 2 TEZ event."]
+    #[inline(always)]
+    pub fn timer2_tez(&mut self) -> TIMER2_TEZ_W<INT_CLR_SPEC> {
+        TIMER2_TEZ_W::new(self, 5)
+    }
+    #[doc = "Bit 6 - Set this bit to clear the interrupt triggered by a PWM timer 0 TEP event."]
+    #[inline(always)]
+    pub fn timer0_tep(&mut self) -> TIMER0_TEP_W<INT_CLR_SPEC> {
+        TIMER0_TEP_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - Set this bit to clear the interrupt triggered by a PWM timer 1 TEP event."]
+    #[inline(always)]
+    pub fn timer1_tep(&mut self) -> TIMER1_TEP_W<INT_CLR_SPEC> {
+        TIMER1_TEP_W::new(self, 7)
+    }
+    #[doc = "Bit 8 - Set this bit to clear the interrupt triggered by a PWM timer 2 TEP event."]
+    #[inline(always)]
+    pub fn timer2_tep(&mut self) -> TIMER2_TEP_W<INT_CLR_SPEC> {
+        TIMER2_TEP_W::new(self, 8)
+    }
+    #[doc = "Bit 9 - Set this bit to clear the interrupt triggered when event_f0 starts."]
+    #[inline(always)]
+    pub fn fault0(&mut self) -> FAULT0_W<INT_CLR_SPEC> {
+        FAULT0_W::new(self, 9)
+    }
+    #[doc = "Bit 10 - Set this bit to clear the interrupt triggered when event_f1 starts."]
+    #[inline(always)]
+    pub fn fault1(&mut self) -> FAULT1_W<INT_CLR_SPEC> {
+        FAULT1_W::new(self, 10)
+    }
+    #[doc = "Bit 11 - Set this bit to clear the interrupt triggered when event_f2 starts."]
+    #[inline(always)]
+    pub fn fault2(&mut self) -> FAULT2_W<INT_CLR_SPEC> {
+        FAULT2_W::new(self, 11)
+    }
+    #[doc = "Bit 12 - Set this bit to clear the interrupt triggered when event_f0 ends."]
+    #[inline(always)]
+    pub fn fault0_clr(&mut self) -> FAULT0_CLR_W<INT_CLR_SPEC> {
+        FAULT0_CLR_W::new(self, 12)
+    }
+    #[doc = "Bit 13 - Set this bit to clear the interrupt triggered when event_f1 ends."]
+    #[inline(always)]
+    pub fn fault1_clr(&mut self) -> FAULT1_CLR_W<INT_CLR_SPEC> {
+        FAULT1_CLR_W::new(self, 13)
+    }
+    #[doc = "Bit 14 - Set this bit to clear the interrupt triggered when event_f2 ends."]
+    #[inline(always)]
+    pub fn fault2_clr(&mut self) -> FAULT2_CLR_W<INT_CLR_SPEC> {
+        FAULT2_CLR_W::new(self, 14)
+    }
+    #[doc = "Bit 15 - Set this bit to clear the interrupt triggered by a PWM operator 0 TEA event"]
+    #[inline(always)]
+    pub fn cmpr0_tea(&mut self) -> CMPR0_TEA_W<INT_CLR_SPEC> {
+        CMPR0_TEA_W::new(self, 15)
+    }
+    #[doc = "Bit 16 - Set this bit to clear the interrupt triggered by a PWM operator 1 TEA event"]
+    #[inline(always)]
+    pub fn cmpr1_tea(&mut self) -> CMPR1_TEA_W<INT_CLR_SPEC> {
+        CMPR1_TEA_W::new(self, 16)
+    }
+    #[doc = "Bit 17 - Set this bit to clear the interrupt triggered by a PWM operator 2 TEA event"]
+    #[inline(always)]
+    pub fn cmpr2_tea(&mut self) -> CMPR2_TEA_W<INT_CLR_SPEC> {
+        CMPR2_TEA_W::new(self, 17)
+    }
+    #[doc = "Bit 18 - Set this bit to clear the interrupt triggered by a PWM operator 0 TEB event"]
+    #[inline(always)]
+    pub fn cmpr0_teb(&mut self) -> CMPR0_TEB_W<INT_CLR_SPEC> {
+        CMPR0_TEB_W::new(self, 18)
+    }
+    #[doc = "Bit 19 - Set this bit to clear the interrupt triggered by a PWM operator 1 TEB event"]
+    #[inline(always)]
+    pub fn cmpr1_teb(&mut self) -> CMPR1_TEB_W<INT_CLR_SPEC> {
+        CMPR1_TEB_W::new(self, 19)
+    }
+    #[doc = "Bit 20 - Set this bit to clear the interrupt triggered by a PWM operator 2 TEB event"]
+    #[inline(always)]
+    pub fn cmpr2_teb(&mut self) -> CMPR2_TEB_W<INT_CLR_SPEC> {
+        CMPR2_TEB_W::new(self, 20)
+    }
+    #[doc = "Bit 21 - Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
+    #[inline(always)]
+    pub fn tz0_cbc(&mut self) -> TZ0_CBC_W<INT_CLR_SPEC> {
+        TZ0_CBC_W::new(self, 21)
+    }
+    #[doc = "Bit 22 - Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
+    #[inline(always)]
+    pub fn tz1_cbc(&mut self) -> TZ1_CBC_W<INT_CLR_SPEC> {
+        TZ1_CBC_W::new(self, 22)
+    }
+    #[doc = "Bit 23 - Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
+    #[inline(always)]
+    pub fn tz2_cbc(&mut self) -> TZ2_CBC_W<INT_CLR_SPEC> {
+        TZ2_CBC_W::new(self, 23)
+    }
+    #[doc = "Bit 24 - Set this bit to clear the interrupt triggered by a one-shot mode action on PWM0."]
+    #[inline(always)]
+    pub fn tz0_ost(&mut self) -> TZ0_OST_W<INT_CLR_SPEC> {
+        TZ0_OST_W::new(self, 24)
+    }
+    #[doc = "Bit 25 - Set this bit to clear the interrupt triggered by a one-shot mode action on PWM1."]
+    #[inline(always)]
+    pub fn tz1_ost(&mut self) -> TZ1_OST_W<INT_CLR_SPEC> {
+        TZ1_OST_W::new(self, 25)
+    }
+    #[doc = "Bit 26 - Set this bit to clear the interrupt triggered by a one-shot mode action on PWM2."]
+    #[inline(always)]
+    pub fn tz2_ost(&mut self) -> TZ2_OST_W<INT_CLR_SPEC> {
+        TZ2_OST_W::new(self, 26)
+    }
+    #[doc = "Bit 27 - Set this bit to clear the interrupt triggered by capture on channel 0."]
+    #[inline(always)]
+    pub fn cap0(&mut self) -> CAP0_W<INT_CLR_SPEC> {
+        CAP0_W::new(self, 27)
+    }
+    #[doc = "Bit 28 - Set this bit to clear the interrupt triggered by capture on channel 1."]
+    #[inline(always)]
+    pub fn cap1(&mut self) -> CAP1_W<INT_CLR_SPEC> {
+        CAP1_W::new(self, 28)
+    }
+    #[doc = "Bit 29 - Set this bit to clear the interrupt triggered by capture on channel 2."]
+    #[inline(always)]
+    pub fn cap2(&mut self) -> CAP2_W<INT_CLR_SPEC> {
+        CAP2_W::new(self, 29)
+    }
+}
+#[doc = "Interrupt clear bits\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct INT_CLR_SPEC;
+impl crate::RegisterSpec for INT_CLR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
+impl crate::Writable for INT_CLR_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x3fff_ffff;
+}
+#[doc = "`reset()` method sets INT_CLR to value 0"]
+impl crate::Resettable for INT_CLR_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/mcpwm0/int_ena.rs

@@ -0,0 +1,482 @@
+#[doc = "Register `INT_ENA` reader"]
+pub type R = crate::R<INT_ENA_SPEC>;
+#[doc = "Register `INT_ENA` writer"]
+pub type W = crate::W<INT_ENA_SPEC>;
+#[doc = "Field `TIMER0_STOP` reader - The enable bit for the interrupt triggered when the timer 0 stops."]
+pub type TIMER0_STOP_R = crate::BitReader;
+#[doc = "Field `TIMER0_STOP` writer - The enable bit for the interrupt triggered when the timer 0 stops."]
+pub type TIMER0_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER1_STOP` reader - The enable bit for the interrupt triggered when the timer 1 stops."]
+pub type TIMER1_STOP_R = crate::BitReader;
+#[doc = "Field `TIMER1_STOP` writer - The enable bit for the interrupt triggered when the timer 1 stops."]
+pub type TIMER1_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER2_STOP` reader - The enable bit for the interrupt triggered when the timer 2 stops."]
+pub type TIMER2_STOP_R = crate::BitReader;
+#[doc = "Field `TIMER2_STOP` writer - The enable bit for the interrupt triggered when the timer 2 stops."]
+pub type TIMER2_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER0_TEZ` reader - The enable bit for the interrupt triggered by a PWM timer 0 TEZ event."]
+pub type TIMER0_TEZ_R = crate::BitReader;
+#[doc = "Field `TIMER0_TEZ` writer - The enable bit for the interrupt triggered by a PWM timer 0 TEZ event."]
+pub type TIMER0_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER1_TEZ` reader - The enable bit for the interrupt triggered by a PWM timer 1 TEZ event."]
+pub type TIMER1_TEZ_R = crate::BitReader;
+#[doc = "Field `TIMER1_TEZ` writer - The enable bit for the interrupt triggered by a PWM timer 1 TEZ event."]
+pub type TIMER1_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER2_TEZ` reader - The enable bit for the interrupt triggered by a PWM timer 2 TEZ event."]
+pub type TIMER2_TEZ_R = crate::BitReader;
+#[doc = "Field `TIMER2_TEZ` writer - The enable bit for the interrupt triggered by a PWM timer 2 TEZ event."]
+pub type TIMER2_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER0_TEP` reader - The enable bit for the interrupt triggered by a PWM timer 0 TEP event."]
+pub type TIMER0_TEP_R = crate::BitReader;
+#[doc = "Field `TIMER0_TEP` writer - The enable bit for the interrupt triggered by a PWM timer 0 TEP event."]
+pub type TIMER0_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER1_TEP` reader - The enable bit for the interrupt triggered by a PWM timer 1 TEP event."]
+pub type TIMER1_TEP_R = crate::BitReader;
+#[doc = "Field `TIMER1_TEP` writer - The enable bit for the interrupt triggered by a PWM timer 1 TEP event."]
+pub type TIMER1_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER2_TEP` reader - The enable bit for the interrupt triggered by a PWM timer 2 TEP event."]
+pub type TIMER2_TEP_R = crate::BitReader;
+#[doc = "Field `TIMER2_TEP` writer - The enable bit for the interrupt triggered by a PWM timer 2 TEP event."]
+pub type TIMER2_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FAULT0` reader - The enable bit for the interrupt triggered when event_f0 starts."]
+pub type FAULT0_R = crate::BitReader;
+#[doc = "Field `FAULT0` writer - The enable bit for the interrupt triggered when event_f0 starts."]
+pub type FAULT0_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FAULT1` reader - The enable bit for the interrupt triggered when event_f1 starts."]
+pub type FAULT1_R = crate::BitReader;
+#[doc = "Field `FAULT1` writer - The enable bit for the interrupt triggered when event_f1 starts."]
+pub type FAULT1_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FAULT2` reader - The enable bit for the interrupt triggered when event_f2 starts."]
+pub type FAULT2_R = crate::BitReader;
+#[doc = "Field `FAULT2` writer - The enable bit for the interrupt triggered when event_f2 starts."]
+pub type FAULT2_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FAULT0_CLR` reader - The enable bit for the interrupt triggered when event_f0 ends."]
+pub type FAULT0_CLR_R = crate::BitReader;
+#[doc = "Field `FAULT0_CLR` writer - The enable bit for the interrupt triggered when event_f0 ends."]
+pub type FAULT0_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FAULT1_CLR` reader - The enable bit for the interrupt triggered when event_f1 ends."]
+pub type FAULT1_CLR_R = crate::BitReader;
+#[doc = "Field `FAULT1_CLR` writer - The enable bit for the interrupt triggered when event_f1 ends."]
+pub type FAULT1_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FAULT2_CLR` reader - The enable bit for the interrupt triggered when event_f2 ends."]
+pub type FAULT2_CLR_R = crate::BitReader;
+#[doc = "Field `FAULT2_CLR` writer - The enable bit for the interrupt triggered when event_f2 ends."]
+pub type FAULT2_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CMPR0_TEA` reader - The enable bit for the interrupt triggered by a PWM operator 0 TEA event"]
+pub type CMPR0_TEA_R = crate::BitReader;
+#[doc = "Field `CMPR0_TEA` writer - The enable bit for the interrupt triggered by a PWM operator 0 TEA event"]
+pub type CMPR0_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CMPR1_TEA` reader - The enable bit for the interrupt triggered by a PWM operator 1 TEA event"]
+pub type CMPR1_TEA_R = crate::BitReader;
+#[doc = "Field `CMPR1_TEA` writer - The enable bit for the interrupt triggered by a PWM operator 1 TEA event"]
+pub type CMPR1_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CMPR2_TEA` reader - The enable bit for the interrupt triggered by a PWM operator 2 TEA event"]
+pub type CMPR2_TEA_R = crate::BitReader;
+#[doc = "Field `CMPR2_TEA` writer - The enable bit for the interrupt triggered by a PWM operator 2 TEA event"]
+pub type CMPR2_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CMPR0_TEB` reader - The enable bit for the interrupt triggered by a PWM operator 0 TEB event"]
+pub type CMPR0_TEB_R = crate::BitReader;
+#[doc = "Field `CMPR0_TEB` writer - The enable bit for the interrupt triggered by a PWM operator 0 TEB event"]
+pub type CMPR0_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CMPR1_TEB` reader - The enable bit for the interrupt triggered by a PWM operator 1 TEB event"]
+pub type CMPR1_TEB_R = crate::BitReader;
+#[doc = "Field `CMPR1_TEB` writer - The enable bit for the interrupt triggered by a PWM operator 1 TEB event"]
+pub type CMPR1_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CMPR2_TEB` reader - The enable bit for the interrupt triggered by a PWM operator 2 TEB event"]
+pub type CMPR2_TEB_R = crate::BitReader;
+#[doc = "Field `CMPR2_TEB` writer - The enable bit for the interrupt triggered by a PWM operator 2 TEB event"]
+pub type CMPR2_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TZ0_CBC` reader - The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
+pub type TZ0_CBC_R = crate::BitReader;
+#[doc = "Field `TZ0_CBC` writer - The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
+pub type TZ0_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TZ1_CBC` reader - The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
+pub type TZ1_CBC_R = crate::BitReader;
+#[doc = "Field `TZ1_CBC` writer - The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
+pub type TZ1_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TZ2_CBC` reader - The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
+pub type TZ2_CBC_R = crate::BitReader;
+#[doc = "Field `TZ2_CBC` writer - The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
+pub type TZ2_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TZ0_OST` reader - The enable bit for the interrupt triggered by a one-shot mode action on PWM0."]
+pub type TZ0_OST_R = crate::BitReader;
+#[doc = "Field `TZ0_OST` writer - The enable bit for the interrupt triggered by a one-shot mode action on PWM0."]
+pub type TZ0_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TZ1_OST` reader - The enable bit for the interrupt triggered by a one-shot mode action on PWM1."]
+pub type TZ1_OST_R = crate::BitReader;
+#[doc = "Field `TZ1_OST` writer - The enable bit for the interrupt triggered by a one-shot mode action on PWM1."]
+pub type TZ1_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TZ2_OST` reader - The enable bit for the interrupt triggered by a one-shot mode action on PWM2."]
+pub type TZ2_OST_R = crate::BitReader;
+#[doc = "Field `TZ2_OST` writer - The enable bit for the interrupt triggered by a one-shot mode action on PWM2."]
+pub type TZ2_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CAP0` reader - The enable bit for the interrupt triggered by capture on channel 0."]
+pub type CAP0_R = crate::BitReader;
+#[doc = "Field `CAP0` writer - The enable bit for the interrupt triggered by capture on channel 0."]
+pub type CAP0_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CAP1` reader - The enable bit for the interrupt triggered by capture on channel 1."]
+pub type CAP1_R = crate::BitReader;
+#[doc = "Field `CAP1` writer - The enable bit for the interrupt triggered by capture on channel 1."]
+pub type CAP1_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CAP2` reader - The enable bit for the interrupt triggered by capture on channel 2."]
+pub type CAP2_R = crate::BitReader;
+#[doc = "Field `CAP2` writer - The enable bit for the interrupt triggered by capture on channel 2."]
+pub type CAP2_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - The enable bit for the interrupt triggered when the timer 0 stops."]
+    #[inline(always)]
+    pub fn timer0_stop(&self) -> TIMER0_STOP_R {
+        TIMER0_STOP_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - The enable bit for the interrupt triggered when the timer 1 stops."]
+    #[inline(always)]
+    pub fn timer1_stop(&self) -> TIMER1_STOP_R {
+        TIMER1_STOP_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - The enable bit for the interrupt triggered when the timer 2 stops."]
+    #[inline(always)]
+    pub fn timer2_stop(&self) -> TIMER2_STOP_R {
+        TIMER2_STOP_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - The enable bit for the interrupt triggered by a PWM timer 0 TEZ event."]
+    #[inline(always)]
+    pub fn timer0_tez(&self) -> TIMER0_TEZ_R {
+        TIMER0_TEZ_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - The enable bit for the interrupt triggered by a PWM timer 1 TEZ event."]
+    #[inline(always)]
+    pub fn timer1_tez(&self) -> TIMER1_TEZ_R {
+        TIMER1_TEZ_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - The enable bit for the interrupt triggered by a PWM timer 2 TEZ event."]
+    #[inline(always)]
+    pub fn timer2_tez(&self) -> TIMER2_TEZ_R {
+        TIMER2_TEZ_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - The enable bit for the interrupt triggered by a PWM timer 0 TEP event."]
+    #[inline(always)]
+    pub fn timer0_tep(&self) -> TIMER0_TEP_R {
+        TIMER0_TEP_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - The enable bit for the interrupt triggered by a PWM timer 1 TEP event."]
+    #[inline(always)]
+    pub fn timer1_tep(&self) -> TIMER1_TEP_R {
+        TIMER1_TEP_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - The enable bit for the interrupt triggered by a PWM timer 2 TEP event."]
+    #[inline(always)]
+    pub fn timer2_tep(&self) -> TIMER2_TEP_R {
+        TIMER2_TEP_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - The enable bit for the interrupt triggered when event_f0 starts."]
+    #[inline(always)]
+    pub fn fault0(&self) -> FAULT0_R {
+        FAULT0_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 10 - The enable bit for the interrupt triggered when event_f1 starts."]
+    #[inline(always)]
+    pub fn fault1(&self) -> FAULT1_R {
+        FAULT1_R::new(((self.bits >> 10) & 1) != 0)
+    }
+    #[doc = "Bit 11 - The enable bit for the interrupt triggered when event_f2 starts."]
+    #[inline(always)]
+    pub fn fault2(&self) -> FAULT2_R {
+        FAULT2_R::new(((self.bits >> 11) & 1) != 0)
+    }
+    #[doc = "Bit 12 - The enable bit for the interrupt triggered when event_f0 ends."]
+    #[inline(always)]
+    pub fn fault0_clr(&self) -> FAULT0_CLR_R {
+        FAULT0_CLR_R::new(((self.bits >> 12) & 1) != 0)
+    }
+    #[doc = "Bit 13 - The enable bit for the interrupt triggered when event_f1 ends."]
+    #[inline(always)]
+    pub fn fault1_clr(&self) -> FAULT1_CLR_R {
+        FAULT1_CLR_R::new(((self.bits >> 13) & 1) != 0)
+    }
+    #[doc = "Bit 14 - The enable bit for the interrupt triggered when event_f2 ends."]
+    #[inline(always)]
+    pub fn fault2_clr(&self) -> FAULT2_CLR_R {
+        FAULT2_CLR_R::new(((self.bits >> 14) & 1) != 0)
+    }
+    #[doc = "Bit 15 - The enable bit for the interrupt triggered by a PWM operator 0 TEA event"]
+    #[inline(always)]
+    pub fn cmpr0_tea(&self) -> CMPR0_TEA_R {
+        CMPR0_TEA_R::new(((self.bits >> 15) & 1) != 0)
+    }
+    #[doc = "Bit 16 - The enable bit for the interrupt triggered by a PWM operator 1 TEA event"]
+    #[inline(always)]
+    pub fn cmpr1_tea(&self) -> CMPR1_TEA_R {
+        CMPR1_TEA_R::new(((self.bits >> 16) & 1) != 0)
+    }
+    #[doc = "Bit 17 - The enable bit for the interrupt triggered by a PWM operator 2 TEA event"]
+    #[inline(always)]
+    pub fn cmpr2_tea(&self) -> CMPR2_TEA_R {
+        CMPR2_TEA_R::new(((self.bits >> 17) & 1) != 0)
+    }
+    #[doc = "Bit 18 - The enable bit for the interrupt triggered by a PWM operator 0 TEB event"]
+    #[inline(always)]
+    pub fn cmpr0_teb(&self) -> CMPR0_TEB_R {
+        CMPR0_TEB_R::new(((self.bits >> 18) & 1) != 0)
+    }
+    #[doc = "Bit 19 - The enable bit for the interrupt triggered by a PWM operator 1 TEB event"]
+    #[inline(always)]
+    pub fn cmpr1_teb(&self) -> CMPR1_TEB_R {
+        CMPR1_TEB_R::new(((self.bits >> 19) & 1) != 0)
+    }
+    #[doc = "Bit 20 - The enable bit for the interrupt triggered by a PWM operator 2 TEB event"]
+    #[inline(always)]
+    pub fn cmpr2_teb(&self) -> CMPR2_TEB_R {
+        CMPR2_TEB_R::new(((self.bits >> 20) & 1) != 0)
+    }
+    #[doc = "Bit 21 - The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
+    #[inline(always)]
+    pub fn tz0_cbc(&self) -> TZ0_CBC_R {
+        TZ0_CBC_R::new(((self.bits >> 21) & 1) != 0)
+    }
+    #[doc = "Bit 22 - The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
+    #[inline(always)]
+    pub fn tz1_cbc(&self) -> TZ1_CBC_R {
+        TZ1_CBC_R::new(((self.bits >> 22) & 1) != 0)
+    }
+    #[doc = "Bit 23 - The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
+    #[inline(always)]
+    pub fn tz2_cbc(&self) -> TZ2_CBC_R {
+        TZ2_CBC_R::new(((self.bits >> 23) & 1) != 0)
+    }
+    #[doc = "Bit 24 - The enable bit for the interrupt triggered by a one-shot mode action on PWM0."]
+    #[inline(always)]
+    pub fn tz0_ost(&self) -> TZ0_OST_R {
+        TZ0_OST_R::new(((self.bits >> 24) & 1) != 0)
+    }
+    #[doc = "Bit 25 - The enable bit for the interrupt triggered by a one-shot mode action on PWM1."]
+    #[inline(always)]
+    pub fn tz1_ost(&self) -> TZ1_OST_R {
+        TZ1_OST_R::new(((self.bits >> 25) & 1) != 0)
+    }
+    #[doc = "Bit 26 - The enable bit for the interrupt triggered by a one-shot mode action on PWM2."]
+    #[inline(always)]
+    pub fn tz2_ost(&self) -> TZ2_OST_R {
+        TZ2_OST_R::new(((self.bits >> 26) & 1) != 0)
+    }
+    #[doc = "Bit 27 - The enable bit for the interrupt triggered by capture on channel 0."]
+    #[inline(always)]
+    pub fn cap0(&self) -> CAP0_R {
+        CAP0_R::new(((self.bits >> 27) & 1) != 0)
+    }
+    #[doc = "Bit 28 - The enable bit for the interrupt triggered by capture on channel 1."]
+    #[inline(always)]
+    pub fn cap1(&self) -> CAP1_R {
+        CAP1_R::new(((self.bits >> 28) & 1) != 0)
+    }
+    #[doc = "Bit 29 - The enable bit for the interrupt triggered by capture on channel 2."]
+    #[inline(always)]
+    pub fn cap2(&self) -> CAP2_R {
+        CAP2_R::new(((self.bits >> 29) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("INT_ENA")
+            .field("timer0_stop", &self.timer0_stop())
+            .field("timer1_stop", &self.timer1_stop())
+            .field("timer2_stop", &self.timer2_stop())
+            .field("timer0_tez", &self.timer0_tez())
+            .field("timer1_tez", &self.timer1_tez())
+            .field("timer2_tez", &self.timer2_tez())
+            .field("timer0_tep", &self.timer0_tep())
+            .field("timer1_tep", &self.timer1_tep())
+            .field("timer2_tep", &self.timer2_tep())
+            .field("fault0", &self.fault0())
+            .field("fault1", &self.fault1())
+            .field("fault2", &self.fault2())
+            .field("fault0_clr", &self.fault0_clr())
+            .field("fault1_clr", &self.fault1_clr())
+            .field("fault2_clr", &self.fault2_clr())
+            .field("cmpr0_tea", &self.cmpr0_tea())
+            .field("cmpr1_tea", &self.cmpr1_tea())
+            .field("cmpr2_tea", &self.cmpr2_tea())
+            .field("cmpr0_teb", &self.cmpr0_teb())
+            .field("cmpr1_teb", &self.cmpr1_teb())
+            .field("cmpr2_teb", &self.cmpr2_teb())
+            .field("tz0_cbc", &self.tz0_cbc())
+            .field("tz1_cbc", &self.tz1_cbc())
+            .field("tz2_cbc", &self.tz2_cbc())
+            .field("tz0_ost", &self.tz0_ost())
+            .field("tz1_ost", &self.tz1_ost())
+            .field("tz2_ost", &self.tz2_ost())
+            .field("cap0", &self.cap0())
+            .field("cap1", &self.cap1())
+            .field("cap2", &self.cap2())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - The enable bit for the interrupt triggered when the timer 0 stops."]
+    #[inline(always)]
+    pub fn timer0_stop(&mut self) -> TIMER0_STOP_W<INT_ENA_SPEC> {
+        TIMER0_STOP_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - The enable bit for the interrupt triggered when the timer 1 stops."]
+    #[inline(always)]
+    pub fn timer1_stop(&mut self) -> TIMER1_STOP_W<INT_ENA_SPEC> {
+        TIMER1_STOP_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - The enable bit for the interrupt triggered when the timer 2 stops."]
+    #[inline(always)]
+    pub fn timer2_stop(&mut self) -> TIMER2_STOP_W<INT_ENA_SPEC> {
+        TIMER2_STOP_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - The enable bit for the interrupt triggered by a PWM timer 0 TEZ event."]
+    #[inline(always)]
+    pub fn timer0_tez(&mut self) -> TIMER0_TEZ_W<INT_ENA_SPEC> {
+        TIMER0_TEZ_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - The enable bit for the interrupt triggered by a PWM timer 1 TEZ event."]
+    #[inline(always)]
+    pub fn timer1_tez(&mut self) -> TIMER1_TEZ_W<INT_ENA_SPEC> {
+        TIMER1_TEZ_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - The enable bit for the interrupt triggered by a PWM timer 2 TEZ event."]
+    #[inline(always)]
+    pub fn timer2_tez(&mut self) -> TIMER2_TEZ_W<INT_ENA_SPEC> {
+        TIMER2_TEZ_W::new(self, 5)
+    }
+    #[doc = "Bit 6 - The enable bit for the interrupt triggered by a PWM timer 0 TEP event."]
+    #[inline(always)]
+    pub fn timer0_tep(&mut self) -> TIMER0_TEP_W<INT_ENA_SPEC> {
+        TIMER0_TEP_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - The enable bit for the interrupt triggered by a PWM timer 1 TEP event."]
+    #[inline(always)]
+    pub fn timer1_tep(&mut self) -> TIMER1_TEP_W<INT_ENA_SPEC> {
+        TIMER1_TEP_W::new(self, 7)
+    }
+    #[doc = "Bit 8 - The enable bit for the interrupt triggered by a PWM timer 2 TEP event."]
+    #[inline(always)]
+    pub fn timer2_tep(&mut self) -> TIMER2_TEP_W<INT_ENA_SPEC> {
+        TIMER2_TEP_W::new(self, 8)
+    }
+    #[doc = "Bit 9 - The enable bit for the interrupt triggered when event_f0 starts."]
+    #[inline(always)]
+    pub fn fault0(&mut self) -> FAULT0_W<INT_ENA_SPEC> {
+        FAULT0_W::new(self, 9)
+    }
+    #[doc = "Bit 10 - The enable bit for the interrupt triggered when event_f1 starts."]
+    #[inline(always)]
+    pub fn fault1(&mut self) -> FAULT1_W<INT_ENA_SPEC> {
+        FAULT1_W::new(self, 10)
+    }
+    #[doc = "Bit 11 - The enable bit for the interrupt triggered when event_f2 starts."]
+    #[inline(always)]
+    pub fn fault2(&mut self) -> FAULT2_W<INT_ENA_SPEC> {
+        FAULT2_W::new(self, 11)
+    }
+    #[doc = "Bit 12 - The enable bit for the interrupt triggered when event_f0 ends."]
+    #[inline(always)]
+    pub fn fault0_clr(&mut self) -> FAULT0_CLR_W<INT_ENA_SPEC> {
+        FAULT0_CLR_W::new(self, 12)
+    }
+    #[doc = "Bit 13 - The enable bit for the interrupt triggered when event_f1 ends."]
+    #[inline(always)]
+    pub fn fault1_clr(&mut self) -> FAULT1_CLR_W<INT_ENA_SPEC> {
+        FAULT1_CLR_W::new(self, 13)
+    }
+    #[doc = "Bit 14 - The enable bit for the interrupt triggered when event_f2 ends."]
+    #[inline(always)]
+    pub fn fault2_clr(&mut self) -> FAULT2_CLR_W<INT_ENA_SPEC> {
+        FAULT2_CLR_W::new(self, 14)
+    }
+    #[doc = "Bit 15 - The enable bit for the interrupt triggered by a PWM operator 0 TEA event"]
+    #[inline(always)]
+    pub fn cmpr0_tea(&mut self) -> CMPR0_TEA_W<INT_ENA_SPEC> {
+        CMPR0_TEA_W::new(self, 15)
+    }
+    #[doc = "Bit 16 - The enable bit for the interrupt triggered by a PWM operator 1 TEA event"]
+    #[inline(always)]
+    pub fn cmpr1_tea(&mut self) -> CMPR1_TEA_W<INT_ENA_SPEC> {
+        CMPR1_TEA_W::new(self, 16)
+    }
+    #[doc = "Bit 17 - The enable bit for the interrupt triggered by a PWM operator 2 TEA event"]
+    #[inline(always)]
+    pub fn cmpr2_tea(&mut self) -> CMPR2_TEA_W<INT_ENA_SPEC> {
+        CMPR2_TEA_W::new(self, 17)
+    }
+    #[doc = "Bit 18 - The enable bit for the interrupt triggered by a PWM operator 0 TEB event"]
+    #[inline(always)]
+    pub fn cmpr0_teb(&mut self) -> CMPR0_TEB_W<INT_ENA_SPEC> {
+        CMPR0_TEB_W::new(self, 18)
+    }
+    #[doc = "Bit 19 - The enable bit for the interrupt triggered by a PWM operator 1 TEB event"]
+    #[inline(always)]
+    pub fn cmpr1_teb(&mut self) -> CMPR1_TEB_W<INT_ENA_SPEC> {
+        CMPR1_TEB_W::new(self, 19)
+    }
+    #[doc = "Bit 20 - The enable bit for the interrupt triggered by a PWM operator 2 TEB event"]
+    #[inline(always)]
+    pub fn cmpr2_teb(&mut self) -> CMPR2_TEB_W<INT_ENA_SPEC> {
+        CMPR2_TEB_W::new(self, 20)
+    }
+    #[doc = "Bit 21 - The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
+    #[inline(always)]
+    pub fn tz0_cbc(&mut self) -> TZ0_CBC_W<INT_ENA_SPEC> {
+        TZ0_CBC_W::new(self, 21)
+    }
+    #[doc = "Bit 22 - The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
+    #[inline(always)]
+    pub fn tz1_cbc(&mut self) -> TZ1_CBC_W<INT_ENA_SPEC> {
+        TZ1_CBC_W::new(self, 22)
+    }
+    #[doc = "Bit 23 - The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
+    #[inline(always)]
+    pub fn tz2_cbc(&mut self) -> TZ2_CBC_W<INT_ENA_SPEC> {
+        TZ2_CBC_W::new(self, 23)
+    }
+    #[doc = "Bit 24 - The enable bit for the interrupt triggered by a one-shot mode action on PWM0."]
+    #[inline(always)]
+    pub fn tz0_ost(&mut self) -> TZ0_OST_W<INT_ENA_SPEC> {
+        TZ0_OST_W::new(self, 24)
+    }
+    #[doc = "Bit 25 - The enable bit for the interrupt triggered by a one-shot mode action on PWM1."]
+    #[inline(always)]
+    pub fn tz1_ost(&mut self) -> TZ1_OST_W<INT_ENA_SPEC> {
+        TZ1_OST_W::new(self, 25)
+    }
+    #[doc = "Bit 26 - The enable bit for the interrupt triggered by a one-shot mode action on PWM2."]
+    #[inline(always)]
+    pub fn tz2_ost(&mut self) -> TZ2_OST_W<INT_ENA_SPEC> {
+        TZ2_OST_W::new(self, 26)
+    }
+    #[doc = "Bit 27 - The enable bit for the interrupt triggered by capture on channel 0."]
+    #[inline(always)]
+    pub fn cap0(&mut self) -> CAP0_W<INT_ENA_SPEC> {
+        CAP0_W::new(self, 27)
+    }
+    #[doc = "Bit 28 - The enable bit for the interrupt triggered by capture on channel 1."]
+    #[inline(always)]
+    pub fn cap1(&mut self) -> CAP1_W<INT_ENA_SPEC> {
+        CAP1_W::new(self, 28)
+    }
+    #[doc = "Bit 29 - The enable bit for the interrupt triggered by capture on channel 2."]
+    #[inline(always)]
+    pub fn cap2(&mut self) -> CAP2_W<INT_ENA_SPEC> {
+        CAP2_W::new(self, 29)
+    }
+}
+#[doc = "Interrupt enable bits\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct INT_ENA_SPEC;
+impl crate::RegisterSpec for INT_ENA_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"]
+impl crate::Readable for INT_ENA_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"]
+impl crate::Writable for INT_ENA_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets INT_ENA to value 0"]
+impl crate::Resettable for INT_ENA_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/mcpwm0/int_raw.rs

@@ -0,0 +1,482 @@
+#[doc = "Register `INT_RAW` reader"]
+pub type R = crate::R<INT_RAW_SPEC>;
+#[doc = "Register `INT_RAW` writer"]
+pub type W = crate::W<INT_RAW_SPEC>;
+#[doc = "Field `TIMER0_STOP` reader - The raw status bit for the interrupt triggered when the timer 0 stops."]
+pub type TIMER0_STOP_R = crate::BitReader;
+#[doc = "Field `TIMER0_STOP` writer - The raw status bit for the interrupt triggered when the timer 0 stops."]
+pub type TIMER0_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER1_STOP` reader - The raw status bit for the interrupt triggered when the timer 1 stops."]
+pub type TIMER1_STOP_R = crate::BitReader;
+#[doc = "Field `TIMER1_STOP` writer - The raw status bit for the interrupt triggered when the timer 1 stops."]
+pub type TIMER1_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER2_STOP` reader - The raw status bit for the interrupt triggered when the timer 2 stops."]
+pub type TIMER2_STOP_R = crate::BitReader;
+#[doc = "Field `TIMER2_STOP` writer - The raw status bit for the interrupt triggered when the timer 2 stops."]
+pub type TIMER2_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER0_TEZ` reader - The raw status bit for the interrupt triggered by a PWM timer 0 TEZ event."]
+pub type TIMER0_TEZ_R = crate::BitReader;
+#[doc = "Field `TIMER0_TEZ` writer - The raw status bit for the interrupt triggered by a PWM timer 0 TEZ event."]
+pub type TIMER0_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER1_TEZ` reader - The raw status bit for the interrupt triggered by a PWM timer 1 TEZ event."]
+pub type TIMER1_TEZ_R = crate::BitReader;
+#[doc = "Field `TIMER1_TEZ` writer - The raw status bit for the interrupt triggered by a PWM timer 1 TEZ event."]
+pub type TIMER1_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER2_TEZ` reader - The raw status bit for the interrupt triggered by a PWM timer 2 TEZ event."]
+pub type TIMER2_TEZ_R = crate::BitReader;
+#[doc = "Field `TIMER2_TEZ` writer - The raw status bit for the interrupt triggered by a PWM timer 2 TEZ event."]
+pub type TIMER2_TEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER0_TEP` reader - The raw status bit for the interrupt triggered by a PWM timer 0 TEP event."]
+pub type TIMER0_TEP_R = crate::BitReader;
+#[doc = "Field `TIMER0_TEP` writer - The raw status bit for the interrupt triggered by a PWM timer 0 TEP event."]
+pub type TIMER0_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER1_TEP` reader - The raw status bit for the interrupt triggered by a PWM timer 1 TEP event."]
+pub type TIMER1_TEP_R = crate::BitReader;
+#[doc = "Field `TIMER1_TEP` writer - The raw status bit for the interrupt triggered by a PWM timer 1 TEP event."]
+pub type TIMER1_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER2_TEP` reader - The raw status bit for the interrupt triggered by a PWM timer 2 TEP event."]
+pub type TIMER2_TEP_R = crate::BitReader;
+#[doc = "Field `TIMER2_TEP` writer - The raw status bit for the interrupt triggered by a PWM timer 2 TEP event."]
+pub type TIMER2_TEP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FAULT0` reader - The raw status bit for the interrupt triggered when event_f0 starts."]
+pub type FAULT0_R = crate::BitReader;
+#[doc = "Field `FAULT0` writer - The raw status bit for the interrupt triggered when event_f0 starts."]
+pub type FAULT0_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FAULT1` reader - The raw status bit for the interrupt triggered when event_f1 starts."]
+pub type FAULT1_R = crate::BitReader;
+#[doc = "Field `FAULT1` writer - The raw status bit for the interrupt triggered when event_f1 starts."]
+pub type FAULT1_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FAULT2` reader - The raw status bit for the interrupt triggered when event_f2 starts."]
+pub type FAULT2_R = crate::BitReader;
+#[doc = "Field `FAULT2` writer - The raw status bit for the interrupt triggered when event_f2 starts."]
+pub type FAULT2_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FAULT0_CLR` reader - The raw status bit for the interrupt triggered when event_f0 ends."]
+pub type FAULT0_CLR_R = crate::BitReader;
+#[doc = "Field `FAULT0_CLR` writer - The raw status bit for the interrupt triggered when event_f0 ends."]
+pub type FAULT0_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FAULT1_CLR` reader - The raw status bit for the interrupt triggered when event_f1 ends."]
+pub type FAULT1_CLR_R = crate::BitReader;
+#[doc = "Field `FAULT1_CLR` writer - The raw status bit for the interrupt triggered when event_f1 ends."]
+pub type FAULT1_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FAULT2_CLR` reader - The raw status bit for the interrupt triggered when event_f2 ends."]
+pub type FAULT2_CLR_R = crate::BitReader;
+#[doc = "Field `FAULT2_CLR` writer - The raw status bit for the interrupt triggered when event_f2 ends."]
+pub type FAULT2_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CMPR0_TEA` reader - The raw status bit for the interrupt triggered by a PWM operator 0 TEA event"]
+pub type CMPR0_TEA_R = crate::BitReader;
+#[doc = "Field `CMPR0_TEA` writer - The raw status bit for the interrupt triggered by a PWM operator 0 TEA event"]
+pub type CMPR0_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CMPR1_TEA` reader - The raw status bit for the interrupt triggered by a PWM operator 1 TEA event"]
+pub type CMPR1_TEA_R = crate::BitReader;
+#[doc = "Field `CMPR1_TEA` writer - The raw status bit for the interrupt triggered by a PWM operator 1 TEA event"]
+pub type CMPR1_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CMPR2_TEA` reader - The raw status bit for the interrupt triggered by a PWM operator 2 TEA event"]
+pub type CMPR2_TEA_R = crate::BitReader;
+#[doc = "Field `CMPR2_TEA` writer - The raw status bit for the interrupt triggered by a PWM operator 2 TEA event"]
+pub type CMPR2_TEA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CMPR0_TEB` reader - The raw status bit for the interrupt triggered by a PWM operator 0 TEB event"]
+pub type CMPR0_TEB_R = crate::BitReader;
+#[doc = "Field `CMPR0_TEB` writer - The raw status bit for the interrupt triggered by a PWM operator 0 TEB event"]
+pub type CMPR0_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CMPR1_TEB` reader - The raw status bit for the interrupt triggered by a PWM operator 1 TEB event"]
+pub type CMPR1_TEB_R = crate::BitReader;
+#[doc = "Field `CMPR1_TEB` writer - The raw status bit for the interrupt triggered by a PWM operator 1 TEB event"]
+pub type CMPR1_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CMPR2_TEB` reader - The raw status bit for the interrupt triggered by a PWM operator 2 TEB event"]
+pub type CMPR2_TEB_R = crate::BitReader;
+#[doc = "Field `CMPR2_TEB` writer - The raw status bit for the interrupt triggered by a PWM operator 2 TEB event"]
+pub type CMPR2_TEB_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TZ0_CBC` reader - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
+pub type TZ0_CBC_R = crate::BitReader;
+#[doc = "Field `TZ0_CBC` writer - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
+pub type TZ0_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TZ1_CBC` reader - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
+pub type TZ1_CBC_R = crate::BitReader;
+#[doc = "Field `TZ1_CBC` writer - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
+pub type TZ1_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TZ2_CBC` reader - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
+pub type TZ2_CBC_R = crate::BitReader;
+#[doc = "Field `TZ2_CBC` writer - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
+pub type TZ2_CBC_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TZ0_OST` reader - The raw status bit for the interrupt triggered by a one-shot mode action on PWM0."]
+pub type TZ0_OST_R = crate::BitReader;
+#[doc = "Field `TZ0_OST` writer - The raw status bit for the interrupt triggered by a one-shot mode action on PWM0."]
+pub type TZ0_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TZ1_OST` reader - The raw status bit for the interrupt triggered by a one-shot mode action on PWM1."]
+pub type TZ1_OST_R = crate::BitReader;
+#[doc = "Field `TZ1_OST` writer - The raw status bit for the interrupt triggered by a one-shot mode action on PWM1."]
+pub type TZ1_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TZ2_OST` reader - The raw status bit for the interrupt triggered by a one-shot mode action on PWM2."]
+pub type TZ2_OST_R = crate::BitReader;
+#[doc = "Field `TZ2_OST` writer - The raw status bit for the interrupt triggered by a one-shot mode action on PWM2."]
+pub type TZ2_OST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CAP0` reader - The raw status bit for the interrupt triggered by capture on channel 0."]
+pub type CAP0_R = crate::BitReader;
+#[doc = "Field `CAP0` writer - The raw status bit for the interrupt triggered by capture on channel 0."]
+pub type CAP0_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CAP1` reader - The raw status bit for the interrupt triggered by capture on channel 1."]
+pub type CAP1_R = crate::BitReader;
+#[doc = "Field `CAP1` writer - The raw status bit for the interrupt triggered by capture on channel 1."]
+pub type CAP1_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CAP2` reader - The raw status bit for the interrupt triggered by capture on channel 2."]
+pub type CAP2_R = crate::BitReader;
+#[doc = "Field `CAP2` writer - The raw status bit for the interrupt triggered by capture on channel 2."]
+pub type CAP2_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - The raw status bit for the interrupt triggered when the timer 0 stops."]
+    #[inline(always)]
+    pub fn timer0_stop(&self) -> TIMER0_STOP_R {
+        TIMER0_STOP_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - The raw status bit for the interrupt triggered when the timer 1 stops."]
+    #[inline(always)]
+    pub fn timer1_stop(&self) -> TIMER1_STOP_R {
+        TIMER1_STOP_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - The raw status bit for the interrupt triggered when the timer 2 stops."]
+    #[inline(always)]
+    pub fn timer2_stop(&self) -> TIMER2_STOP_R {
+        TIMER2_STOP_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - The raw status bit for the interrupt triggered by a PWM timer 0 TEZ event."]
+    #[inline(always)]
+    pub fn timer0_tez(&self) -> TIMER0_TEZ_R {
+        TIMER0_TEZ_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - The raw status bit for the interrupt triggered by a PWM timer 1 TEZ event."]
+    #[inline(always)]
+    pub fn timer1_tez(&self) -> TIMER1_TEZ_R {
+        TIMER1_TEZ_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - The raw status bit for the interrupt triggered by a PWM timer 2 TEZ event."]
+    #[inline(always)]
+    pub fn timer2_tez(&self) -> TIMER2_TEZ_R {
+        TIMER2_TEZ_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - The raw status bit for the interrupt triggered by a PWM timer 0 TEP event."]
+    #[inline(always)]
+    pub fn timer0_tep(&self) -> TIMER0_TEP_R {
+        TIMER0_TEP_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - The raw status bit for the interrupt triggered by a PWM timer 1 TEP event."]
+    #[inline(always)]
+    pub fn timer1_tep(&self) -> TIMER1_TEP_R {
+        TIMER1_TEP_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - The raw status bit for the interrupt triggered by a PWM timer 2 TEP event."]
+    #[inline(always)]
+    pub fn timer2_tep(&self) -> TIMER2_TEP_R {
+        TIMER2_TEP_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - The raw status bit for the interrupt triggered when event_f0 starts."]
+    #[inline(always)]
+    pub fn fault0(&self) -> FAULT0_R {
+        FAULT0_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 10 - The raw status bit for the interrupt triggered when event_f1 starts."]
+    #[inline(always)]
+    pub fn fault1(&self) -> FAULT1_R {
+        FAULT1_R::new(((self.bits >> 10) & 1) != 0)
+    }
+    #[doc = "Bit 11 - The raw status bit for the interrupt triggered when event_f2 starts."]
+    #[inline(always)]
+    pub fn fault2(&self) -> FAULT2_R {
+        FAULT2_R::new(((self.bits >> 11) & 1) != 0)
+    }
+    #[doc = "Bit 12 - The raw status bit for the interrupt triggered when event_f0 ends."]
+    #[inline(always)]
+    pub fn fault0_clr(&self) -> FAULT0_CLR_R {
+        FAULT0_CLR_R::new(((self.bits >> 12) & 1) != 0)
+    }
+    #[doc = "Bit 13 - The raw status bit for the interrupt triggered when event_f1 ends."]
+    #[inline(always)]
+    pub fn fault1_clr(&self) -> FAULT1_CLR_R {
+        FAULT1_CLR_R::new(((self.bits >> 13) & 1) != 0)
+    }
+    #[doc = "Bit 14 - The raw status bit for the interrupt triggered when event_f2 ends."]
+    #[inline(always)]
+    pub fn fault2_clr(&self) -> FAULT2_CLR_R {
+        FAULT2_CLR_R::new(((self.bits >> 14) & 1) != 0)
+    }
+    #[doc = "Bit 15 - The raw status bit for the interrupt triggered by a PWM operator 0 TEA event"]
+    #[inline(always)]
+    pub fn cmpr0_tea(&self) -> CMPR0_TEA_R {
+        CMPR0_TEA_R::new(((self.bits >> 15) & 1) != 0)
+    }
+    #[doc = "Bit 16 - The raw status bit for the interrupt triggered by a PWM operator 1 TEA event"]
+    #[inline(always)]
+    pub fn cmpr1_tea(&self) -> CMPR1_TEA_R {
+        CMPR1_TEA_R::new(((self.bits >> 16) & 1) != 0)
+    }
+    #[doc = "Bit 17 - The raw status bit for the interrupt triggered by a PWM operator 2 TEA event"]
+    #[inline(always)]
+    pub fn cmpr2_tea(&self) -> CMPR2_TEA_R {
+        CMPR2_TEA_R::new(((self.bits >> 17) & 1) != 0)
+    }
+    #[doc = "Bit 18 - The raw status bit for the interrupt triggered by a PWM operator 0 TEB event"]
+    #[inline(always)]
+    pub fn cmpr0_teb(&self) -> CMPR0_TEB_R {
+        CMPR0_TEB_R::new(((self.bits >> 18) & 1) != 0)
+    }
+    #[doc = "Bit 19 - The raw status bit for the interrupt triggered by a PWM operator 1 TEB event"]
+    #[inline(always)]
+    pub fn cmpr1_teb(&self) -> CMPR1_TEB_R {
+        CMPR1_TEB_R::new(((self.bits >> 19) & 1) != 0)
+    }
+    #[doc = "Bit 20 - The raw status bit for the interrupt triggered by a PWM operator 2 TEB event"]
+    #[inline(always)]
+    pub fn cmpr2_teb(&self) -> CMPR2_TEB_R {
+        CMPR2_TEB_R::new(((self.bits >> 20) & 1) != 0)
+    }
+    #[doc = "Bit 21 - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
+    #[inline(always)]
+    pub fn tz0_cbc(&self) -> TZ0_CBC_R {
+        TZ0_CBC_R::new(((self.bits >> 21) & 1) != 0)
+    }
+    #[doc = "Bit 22 - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
+    #[inline(always)]
+    pub fn tz1_cbc(&self) -> TZ1_CBC_R {
+        TZ1_CBC_R::new(((self.bits >> 22) & 1) != 0)
+    }
+    #[doc = "Bit 23 - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
+    #[inline(always)]
+    pub fn tz2_cbc(&self) -> TZ2_CBC_R {
+        TZ2_CBC_R::new(((self.bits >> 23) & 1) != 0)
+    }
+    #[doc = "Bit 24 - The raw status bit for the interrupt triggered by a one-shot mode action on PWM0."]
+    #[inline(always)]
+    pub fn tz0_ost(&self) -> TZ0_OST_R {
+        TZ0_OST_R::new(((self.bits >> 24) & 1) != 0)
+    }
+    #[doc = "Bit 25 - The raw status bit for the interrupt triggered by a one-shot mode action on PWM1."]
+    #[inline(always)]
+    pub fn tz1_ost(&self) -> TZ1_OST_R {
+        TZ1_OST_R::new(((self.bits >> 25) & 1) != 0)
+    }
+    #[doc = "Bit 26 - The raw status bit for the interrupt triggered by a one-shot mode action on PWM2."]
+    #[inline(always)]
+    pub fn tz2_ost(&self) -> TZ2_OST_R {
+        TZ2_OST_R::new(((self.bits >> 26) & 1) != 0)
+    }
+    #[doc = "Bit 27 - The raw status bit for the interrupt triggered by capture on channel 0."]
+    #[inline(always)]
+    pub fn cap0(&self) -> CAP0_R {
+        CAP0_R::new(((self.bits >> 27) & 1) != 0)
+    }
+    #[doc = "Bit 28 - The raw status bit for the interrupt triggered by capture on channel 1."]
+    #[inline(always)]
+    pub fn cap1(&self) -> CAP1_R {
+        CAP1_R::new(((self.bits >> 28) & 1) != 0)
+    }
+    #[doc = "Bit 29 - The raw status bit for the interrupt triggered by capture on channel 2."]
+    #[inline(always)]
+    pub fn cap2(&self) -> CAP2_R {
+        CAP2_R::new(((self.bits >> 29) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("INT_RAW")
+            .field("timer0_stop", &self.timer0_stop())
+            .field("timer1_stop", &self.timer1_stop())
+            .field("timer2_stop", &self.timer2_stop())
+            .field("timer0_tez", &self.timer0_tez())
+            .field("timer1_tez", &self.timer1_tez())
+            .field("timer2_tez", &self.timer2_tez())
+            .field("timer0_tep", &self.timer0_tep())
+            .field("timer1_tep", &self.timer1_tep())
+            .field("timer2_tep", &self.timer2_tep())
+            .field("fault0", &self.fault0())
+            .field("fault1", &self.fault1())
+            .field("fault2", &self.fault2())
+            .field("fault0_clr", &self.fault0_clr())
+            .field("fault1_clr", &self.fault1_clr())
+            .field("fault2_clr", &self.fault2_clr())
+            .field("cmpr0_tea", &self.cmpr0_tea())
+            .field("cmpr1_tea", &self.cmpr1_tea())
+            .field("cmpr2_tea", &self.cmpr2_tea())
+            .field("cmpr0_teb", &self.cmpr0_teb())
+            .field("cmpr1_teb", &self.cmpr1_teb())
+            .field("cmpr2_teb", &self.cmpr2_teb())
+            .field("tz0_cbc", &self.tz0_cbc())
+            .field("tz1_cbc", &self.tz1_cbc())
+            .field("tz2_cbc", &self.tz2_cbc())
+            .field("tz0_ost", &self.tz0_ost())
+            .field("tz1_ost", &self.tz1_ost())
+            .field("tz2_ost", &self.tz2_ost())
+            .field("cap0", &self.cap0())
+            .field("cap1", &self.cap1())
+            .field("cap2", &self.cap2())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - The raw status bit for the interrupt triggered when the timer 0 stops."]
+    #[inline(always)]
+    pub fn timer0_stop(&mut self) -> TIMER0_STOP_W<INT_RAW_SPEC> {
+        TIMER0_STOP_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - The raw status bit for the interrupt triggered when the timer 1 stops."]
+    #[inline(always)]
+    pub fn timer1_stop(&mut self) -> TIMER1_STOP_W<INT_RAW_SPEC> {
+        TIMER1_STOP_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - The raw status bit for the interrupt triggered when the timer 2 stops."]
+    #[inline(always)]
+    pub fn timer2_stop(&mut self) -> TIMER2_STOP_W<INT_RAW_SPEC> {
+        TIMER2_STOP_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - The raw status bit for the interrupt triggered by a PWM timer 0 TEZ event."]
+    #[inline(always)]
+    pub fn timer0_tez(&mut self) -> TIMER0_TEZ_W<INT_RAW_SPEC> {
+        TIMER0_TEZ_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - The raw status bit for the interrupt triggered by a PWM timer 1 TEZ event."]
+    #[inline(always)]
+    pub fn timer1_tez(&mut self) -> TIMER1_TEZ_W<INT_RAW_SPEC> {
+        TIMER1_TEZ_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - The raw status bit for the interrupt triggered by a PWM timer 2 TEZ event."]
+    #[inline(always)]
+    pub fn timer2_tez(&mut self) -> TIMER2_TEZ_W<INT_RAW_SPEC> {
+        TIMER2_TEZ_W::new(self, 5)
+    }
+    #[doc = "Bit 6 - The raw status bit for the interrupt triggered by a PWM timer 0 TEP event."]
+    #[inline(always)]
+    pub fn timer0_tep(&mut self) -> TIMER0_TEP_W<INT_RAW_SPEC> {
+        TIMER0_TEP_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - The raw status bit for the interrupt triggered by a PWM timer 1 TEP event."]
+    #[inline(always)]
+    pub fn timer1_tep(&mut self) -> TIMER1_TEP_W<INT_RAW_SPEC> {
+        TIMER1_TEP_W::new(self, 7)
+    }
+    #[doc = "Bit 8 - The raw status bit for the interrupt triggered by a PWM timer 2 TEP event."]
+    #[inline(always)]
+    pub fn timer2_tep(&mut self) -> TIMER2_TEP_W<INT_RAW_SPEC> {
+        TIMER2_TEP_W::new(self, 8)
+    }
+    #[doc = "Bit 9 - The raw status bit for the interrupt triggered when event_f0 starts."]
+    #[inline(always)]
+    pub fn fault0(&mut self) -> FAULT0_W<INT_RAW_SPEC> {
+        FAULT0_W::new(self, 9)
+    }
+    #[doc = "Bit 10 - The raw status bit for the interrupt triggered when event_f1 starts."]
+    #[inline(always)]
+    pub fn fault1(&mut self) -> FAULT1_W<INT_RAW_SPEC> {
+        FAULT1_W::new(self, 10)
+    }
+    #[doc = "Bit 11 - The raw status bit for the interrupt triggered when event_f2 starts."]
+    #[inline(always)]
+    pub fn fault2(&mut self) -> FAULT2_W<INT_RAW_SPEC> {
+        FAULT2_W::new(self, 11)
+    }
+    #[doc = "Bit 12 - The raw status bit for the interrupt triggered when event_f0 ends."]
+    #[inline(always)]
+    pub fn fault0_clr(&mut self) -> FAULT0_CLR_W<INT_RAW_SPEC> {
+        FAULT0_CLR_W::new(self, 12)
+    }
+    #[doc = "Bit 13 - The raw status bit for the interrupt triggered when event_f1 ends."]
+    #[inline(always)]
+    pub fn fault1_clr(&mut self) -> FAULT1_CLR_W<INT_RAW_SPEC> {
+        FAULT1_CLR_W::new(self, 13)
+    }
+    #[doc = "Bit 14 - The raw status bit for the interrupt triggered when event_f2 ends."]
+    #[inline(always)]
+    pub fn fault2_clr(&mut self) -> FAULT2_CLR_W<INT_RAW_SPEC> {
+        FAULT2_CLR_W::new(self, 14)
+    }
+    #[doc = "Bit 15 - The raw status bit for the interrupt triggered by a PWM operator 0 TEA event"]
+    #[inline(always)]
+    pub fn cmpr0_tea(&mut self) -> CMPR0_TEA_W<INT_RAW_SPEC> {
+        CMPR0_TEA_W::new(self, 15)
+    }
+    #[doc = "Bit 16 - The raw status bit for the interrupt triggered by a PWM operator 1 TEA event"]
+    #[inline(always)]
+    pub fn cmpr1_tea(&mut self) -> CMPR1_TEA_W<INT_RAW_SPEC> {
+        CMPR1_TEA_W::new(self, 16)
+    }
+    #[doc = "Bit 17 - The raw status bit for the interrupt triggered by a PWM operator 2 TEA event"]
+    #[inline(always)]
+    pub fn cmpr2_tea(&mut self) -> CMPR2_TEA_W<INT_RAW_SPEC> {
+        CMPR2_TEA_W::new(self, 17)
+    }
+    #[doc = "Bit 18 - The raw status bit for the interrupt triggered by a PWM operator 0 TEB event"]
+    #[inline(always)]
+    pub fn cmpr0_teb(&mut self) -> CMPR0_TEB_W<INT_RAW_SPEC> {
+        CMPR0_TEB_W::new(self, 18)
+    }
+    #[doc = "Bit 19 - The raw status bit for the interrupt triggered by a PWM operator 1 TEB event"]
+    #[inline(always)]
+    pub fn cmpr1_teb(&mut self) -> CMPR1_TEB_W<INT_RAW_SPEC> {
+        CMPR1_TEB_W::new(self, 19)
+    }
+    #[doc = "Bit 20 - The raw status bit for the interrupt triggered by a PWM operator 2 TEB event"]
+    #[inline(always)]
+    pub fn cmpr2_teb(&mut self) -> CMPR2_TEB_W<INT_RAW_SPEC> {
+        CMPR2_TEB_W::new(self, 20)
+    }
+    #[doc = "Bit 21 - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
+    #[inline(always)]
+    pub fn tz0_cbc(&mut self) -> TZ0_CBC_W<INT_RAW_SPEC> {
+        TZ0_CBC_W::new(self, 21)
+    }
+    #[doc = "Bit 22 - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
+    #[inline(always)]
+    pub fn tz1_cbc(&mut self) -> TZ1_CBC_W<INT_RAW_SPEC> {
+        TZ1_CBC_W::new(self, 22)
+    }
+    #[doc = "Bit 23 - The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
+    #[inline(always)]
+    pub fn tz2_cbc(&mut self) -> TZ2_CBC_W<INT_RAW_SPEC> {
+        TZ2_CBC_W::new(self, 23)
+    }
+    #[doc = "Bit 24 - The raw status bit for the interrupt triggered by a one-shot mode action on PWM0."]
+    #[inline(always)]
+    pub fn tz0_ost(&mut self) -> TZ0_OST_W<INT_RAW_SPEC> {
+        TZ0_OST_W::new(self, 24)
+    }
+    #[doc = "Bit 25 - The raw status bit for the interrupt triggered by a one-shot mode action on PWM1."]
+    #[inline(always)]
+    pub fn tz1_ost(&mut self) -> TZ1_OST_W<INT_RAW_SPEC> {
+        TZ1_OST_W::new(self, 25)
+    }
+    #[doc = "Bit 26 - The raw status bit for the interrupt triggered by a one-shot mode action on PWM2."]
+    #[inline(always)]
+    pub fn tz2_ost(&mut self) -> TZ2_OST_W<INT_RAW_SPEC> {
+        TZ2_OST_W::new(self, 26)
+    }
+    #[doc = "Bit 27 - The raw status bit for the interrupt triggered by capture on channel 0."]
+    #[inline(always)]
+    pub fn cap0(&mut self) -> CAP0_W<INT_RAW_SPEC> {
+        CAP0_W::new(self, 27)
+    }
+    #[doc = "Bit 28 - The raw status bit for the interrupt triggered by capture on channel 1."]
+    #[inline(always)]
+    pub fn cap1(&mut self) -> CAP1_W<INT_RAW_SPEC> {
+        CAP1_W::new(self, 28)
+    }
+    #[doc = "Bit 29 - The raw status bit for the interrupt triggered by capture on channel 2."]
+    #[inline(always)]
+    pub fn cap2(&mut self) -> CAP2_W<INT_RAW_SPEC> {
+        CAP2_W::new(self, 29)
+    }
+}
+#[doc = "Raw interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`int_raw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_raw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct INT_RAW_SPEC;
+impl crate::RegisterSpec for INT_RAW_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"]
+impl crate::Readable for INT_RAW_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`int_raw::W`](W) writer structure"]
+impl crate::Writable for INT_RAW_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets INT_RAW to value 0"]
+impl crate::Resettable for INT_RAW_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/mcpwm0/int_st.rs

@@ -0,0 +1,262 @@
+#[doc = "Register `INT_ST` reader"]
+pub type R = crate::R<INT_ST_SPEC>;
+#[doc = "Field `TIMER0_STOP` reader - The masked status bit for the interrupt triggered when the timer 0 stops."]
+pub type TIMER0_STOP_R = crate::BitReader;
+#[doc = "Field `TIMER1_STOP` reader - The masked status bit for the interrupt triggered when the timer 1 stops."]
+pub type TIMER1_STOP_R = crate::BitReader;
+#[doc = "Field `TIMER2_STOP` reader - The masked status bit for the interrupt triggered when the timer 2 stops."]
+pub type TIMER2_STOP_R = crate::BitReader;
+#[doc = "Field `TIMER0_TEZ` reader - The masked status bit for the interrupt triggered by a PWM timer 0 TEZ event."]
+pub type TIMER0_TEZ_R = crate::BitReader;
+#[doc = "Field `TIMER1_TEZ` reader - The masked status bit for the interrupt triggered by a PWM timer 1 TEZ event."]
+pub type TIMER1_TEZ_R = crate::BitReader;
+#[doc = "Field `TIMER2_TEZ` reader - The masked status bit for the interrupt triggered by a PWM timer 2 TEZ event."]
+pub type TIMER2_TEZ_R = crate::BitReader;
+#[doc = "Field `TIMER0_TEP` reader - The masked status bit for the interrupt triggered by a PWM timer 0 TEP event."]
+pub type TIMER0_TEP_R = crate::BitReader;
+#[doc = "Field `TIMER1_TEP` reader - The masked status bit for the interrupt triggered by a PWM timer 1 TEP event."]
+pub type TIMER1_TEP_R = crate::BitReader;
+#[doc = "Field `TIMER2_TEP` reader - The masked status bit for the interrupt triggered by a PWM timer 2 TEP event."]
+pub type TIMER2_TEP_R = crate::BitReader;
+#[doc = "Field `FAULT0` reader - The masked status bit for the interrupt triggered when event_f0 starts."]
+pub type FAULT0_R = crate::BitReader;
+#[doc = "Field `FAULT1` reader - The masked status bit for the interrupt triggered when event_f1 starts."]
+pub type FAULT1_R = crate::BitReader;
+#[doc = "Field `FAULT2` reader - The masked status bit for the interrupt triggered when event_f2 starts."]
+pub type FAULT2_R = crate::BitReader;
+#[doc = "Field `FAULT0_CLR` reader - The masked status bit for the interrupt triggered when event_f0 ends."]
+pub type FAULT0_CLR_R = crate::BitReader;
+#[doc = "Field `FAULT1_CLR` reader - The masked status bit for the interrupt triggered when event_f1 ends."]
+pub type FAULT1_CLR_R = crate::BitReader;
+#[doc = "Field `FAULT2_CLR` reader - The masked status bit for the interrupt triggered when event_f2 ends."]
+pub type FAULT2_CLR_R = crate::BitReader;
+#[doc = "Field `CMPR0_TEA` reader - The masked status bit for the interrupt triggered by a PWM operator 0 TEA event"]
+pub type CMPR0_TEA_R = crate::BitReader;
+#[doc = "Field `CMPR1_TEA` reader - The masked status bit for the interrupt triggered by a PWM operator 1 TEA event"]
+pub type CMPR1_TEA_R = crate::BitReader;
+#[doc = "Field `CMPR2_TEA` reader - The masked status bit for the interrupt triggered by a PWM operator 2 TEA event"]
+pub type CMPR2_TEA_R = crate::BitReader;
+#[doc = "Field `CMPR0_TEB` reader - The masked status bit for the interrupt triggered by a PWM operator 0 TEB event"]
+pub type CMPR0_TEB_R = crate::BitReader;
+#[doc = "Field `CMPR1_TEB` reader - The masked status bit for the interrupt triggered by a PWM operator 1 TEB event"]
+pub type CMPR1_TEB_R = crate::BitReader;
+#[doc = "Field `CMPR2_TEB` reader - The masked status bit for the interrupt triggered by a PWM operator 2 TEB event"]
+pub type CMPR2_TEB_R = crate::BitReader;
+#[doc = "Field `TZ0_CBC` reader - The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
+pub type TZ0_CBC_R = crate::BitReader;
+#[doc = "Field `TZ1_CBC` reader - The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
+pub type TZ1_CBC_R = crate::BitReader;
+#[doc = "Field `TZ2_CBC` reader - The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
+pub type TZ2_CBC_R = crate::BitReader;
+#[doc = "Field `TZ0_OST` reader - The masked status bit for the interrupt triggered by a one-shot mode action on PWM0."]
+pub type TZ0_OST_R = crate::BitReader;
+#[doc = "Field `TZ1_OST` reader - The masked status bit for the interrupt triggered by a one-shot mode action on PWM1."]
+pub type TZ1_OST_R = crate::BitReader;
+#[doc = "Field `TZ2_OST` reader - The masked status bit for the interrupt triggered by a one-shot mode action on PWM2."]
+pub type TZ2_OST_R = crate::BitReader;
+#[doc = "Field `CAP0` reader - The masked status bit for the interrupt triggered by capture on channel 0."]
+pub type CAP0_R = crate::BitReader;
+#[doc = "Field `CAP1` reader - The masked status bit for the interrupt triggered by capture on channel 1."]
+pub type CAP1_R = crate::BitReader;
+#[doc = "Field `CAP2` reader - The masked status bit for the interrupt triggered by capture on channel 2."]
+pub type CAP2_R = crate::BitReader;
+impl R {
+    #[doc = "Bit 0 - The masked status bit for the interrupt triggered when the timer 0 stops."]
+    #[inline(always)]
+    pub fn timer0_stop(&self) -> TIMER0_STOP_R {
+        TIMER0_STOP_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - The masked status bit for the interrupt triggered when the timer 1 stops."]
+    #[inline(always)]
+    pub fn timer1_stop(&self) -> TIMER1_STOP_R {
+        TIMER1_STOP_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - The masked status bit for the interrupt triggered when the timer 2 stops."]
+    #[inline(always)]
+    pub fn timer2_stop(&self) -> TIMER2_STOP_R {
+        TIMER2_STOP_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - The masked status bit for the interrupt triggered by a PWM timer 0 TEZ event."]
+    #[inline(always)]
+    pub fn timer0_tez(&self) -> TIMER0_TEZ_R {
+        TIMER0_TEZ_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - The masked status bit for the interrupt triggered by a PWM timer 1 TEZ event."]
+    #[inline(always)]
+    pub fn timer1_tez(&self) -> TIMER1_TEZ_R {
+        TIMER1_TEZ_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - The masked status bit for the interrupt triggered by a PWM timer 2 TEZ event."]
+    #[inline(always)]
+    pub fn timer2_tez(&self) -> TIMER2_TEZ_R {
+        TIMER2_TEZ_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - The masked status bit for the interrupt triggered by a PWM timer 0 TEP event."]
+    #[inline(always)]
+    pub fn timer0_tep(&self) -> TIMER0_TEP_R {
+        TIMER0_TEP_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - The masked status bit for the interrupt triggered by a PWM timer 1 TEP event."]
+    #[inline(always)]
+    pub fn timer1_tep(&self) -> TIMER1_TEP_R {
+        TIMER1_TEP_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - The masked status bit for the interrupt triggered by a PWM timer 2 TEP event."]
+    #[inline(always)]
+    pub fn timer2_tep(&self) -> TIMER2_TEP_R {
+        TIMER2_TEP_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - The masked status bit for the interrupt triggered when event_f0 starts."]
+    #[inline(always)]
+    pub fn fault0(&self) -> FAULT0_R {
+        FAULT0_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 10 - The masked status bit for the interrupt triggered when event_f1 starts."]
+    #[inline(always)]
+    pub fn fault1(&self) -> FAULT1_R {
+        FAULT1_R::new(((self.bits >> 10) & 1) != 0)
+    }
+    #[doc = "Bit 11 - The masked status bit for the interrupt triggered when event_f2 starts."]
+    #[inline(always)]
+    pub fn fault2(&self) -> FAULT2_R {
+        FAULT2_R::new(((self.bits >> 11) & 1) != 0)
+    }
+    #[doc = "Bit 12 - The masked status bit for the interrupt triggered when event_f0 ends."]
+    #[inline(always)]
+    pub fn fault0_clr(&self) -> FAULT0_CLR_R {
+        FAULT0_CLR_R::new(((self.bits >> 12) & 1) != 0)
+    }
+    #[doc = "Bit 13 - The masked status bit for the interrupt triggered when event_f1 ends."]
+    #[inline(always)]
+    pub fn fault1_clr(&self) -> FAULT1_CLR_R {
+        FAULT1_CLR_R::new(((self.bits >> 13) & 1) != 0)
+    }
+    #[doc = "Bit 14 - The masked status bit for the interrupt triggered when event_f2 ends."]
+    #[inline(always)]
+    pub fn fault2_clr(&self) -> FAULT2_CLR_R {
+        FAULT2_CLR_R::new(((self.bits >> 14) & 1) != 0)
+    }
+    #[doc = "Bit 15 - The masked status bit for the interrupt triggered by a PWM operator 0 TEA event"]
+    #[inline(always)]
+    pub fn cmpr0_tea(&self) -> CMPR0_TEA_R {
+        CMPR0_TEA_R::new(((self.bits >> 15) & 1) != 0)
+    }
+    #[doc = "Bit 16 - The masked status bit for the interrupt triggered by a PWM operator 1 TEA event"]
+    #[inline(always)]
+    pub fn cmpr1_tea(&self) -> CMPR1_TEA_R {
+        CMPR1_TEA_R::new(((self.bits >> 16) & 1) != 0)
+    }
+    #[doc = "Bit 17 - The masked status bit for the interrupt triggered by a PWM operator 2 TEA event"]
+    #[inline(always)]
+    pub fn cmpr2_tea(&self) -> CMPR2_TEA_R {
+        CMPR2_TEA_R::new(((self.bits >> 17) & 1) != 0)
+    }
+    #[doc = "Bit 18 - The masked status bit for the interrupt triggered by a PWM operator 0 TEB event"]
+    #[inline(always)]
+    pub fn cmpr0_teb(&self) -> CMPR0_TEB_R {
+        CMPR0_TEB_R::new(((self.bits >> 18) & 1) != 0)
+    }
+    #[doc = "Bit 19 - The masked status bit for the interrupt triggered by a PWM operator 1 TEB event"]
+    #[inline(always)]
+    pub fn cmpr1_teb(&self) -> CMPR1_TEB_R {
+        CMPR1_TEB_R::new(((self.bits >> 19) & 1) != 0)
+    }
+    #[doc = "Bit 20 - The masked status bit for the interrupt triggered by a PWM operator 2 TEB event"]
+    #[inline(always)]
+    pub fn cmpr2_teb(&self) -> CMPR2_TEB_R {
+        CMPR2_TEB_R::new(((self.bits >> 20) & 1) != 0)
+    }
+    #[doc = "Bit 21 - The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0."]
+    #[inline(always)]
+    pub fn tz0_cbc(&self) -> TZ0_CBC_R {
+        TZ0_CBC_R::new(((self.bits >> 21) & 1) != 0)
+    }
+    #[doc = "Bit 22 - The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1."]
+    #[inline(always)]
+    pub fn tz1_cbc(&self) -> TZ1_CBC_R {
+        TZ1_CBC_R::new(((self.bits >> 22) & 1) != 0)
+    }
+    #[doc = "Bit 23 - The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2."]
+    #[inline(always)]
+    pub fn tz2_cbc(&self) -> TZ2_CBC_R {
+        TZ2_CBC_R::new(((self.bits >> 23) & 1) != 0)
+    }
+    #[doc = "Bit 24 - The masked status bit for the interrupt triggered by a one-shot mode action on PWM0."]
+    #[inline(always)]
+    pub fn tz0_ost(&self) -> TZ0_OST_R {
+        TZ0_OST_R::new(((self.bits >> 24) & 1) != 0)
+    }
+    #[doc = "Bit 25 - The masked status bit for the interrupt triggered by a one-shot mode action on PWM1."]
+    #[inline(always)]
+    pub fn tz1_ost(&self) -> TZ1_OST_R {
+        TZ1_OST_R::new(((self.bits >> 25) & 1) != 0)
+    }
+    #[doc = "Bit 26 - The masked status bit for the interrupt triggered by a one-shot mode action on PWM2."]
+    #[inline(always)]
+    pub fn tz2_ost(&self) -> TZ2_OST_R {
+        TZ2_OST_R::new(((self.bits >> 26) & 1) != 0)
+    }
+    #[doc = "Bit 27 - The masked status bit for the interrupt triggered by capture on channel 0."]
+    #[inline(always)]
+    pub fn cap0(&self) -> CAP0_R {
+        CAP0_R::new(((self.bits >> 27) & 1) != 0)
+    }
+    #[doc = "Bit 28 - The masked status bit for the interrupt triggered by capture on channel 1."]
+    #[inline(always)]
+    pub fn cap1(&self) -> CAP1_R {
+        CAP1_R::new(((self.bits >> 28) & 1) != 0)
+    }
+    #[doc = "Bit 29 - The masked status bit for the interrupt triggered by capture on channel 2."]
+    #[inline(always)]
+    pub fn cap2(&self) -> CAP2_R {
+        CAP2_R::new(((self.bits >> 29) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("INT_ST")
+            .field("timer0_stop", &self.timer0_stop())
+            .field("timer1_stop", &self.timer1_stop())
+            .field("timer2_stop", &self.timer2_stop())
+            .field("timer0_tez", &self.timer0_tez())
+            .field("timer1_tez", &self.timer1_tez())
+            .field("timer2_tez", &self.timer2_tez())
+            .field("timer0_tep", &self.timer0_tep())
+            .field("timer1_tep", &self.timer1_tep())
+            .field("timer2_tep", &self.timer2_tep())
+            .field("fault0", &self.fault0())
+            .field("fault1", &self.fault1())
+            .field("fault2", &self.fault2())
+            .field("fault0_clr", &self.fault0_clr())
+            .field("fault1_clr", &self.fault1_clr())
+            .field("fault2_clr", &self.fault2_clr())
+            .field("cmpr0_tea", &self.cmpr0_tea())
+            .field("cmpr1_tea", &self.cmpr1_tea())
+            .field("cmpr2_tea", &self.cmpr2_tea())
+            .field("cmpr0_teb", &self.cmpr0_teb())
+            .field("cmpr1_teb", &self.cmpr1_teb())
+            .field("cmpr2_teb", &self.cmpr2_teb())
+            .field("tz0_cbc", &self.tz0_cbc())
+            .field("tz1_cbc", &self.tz1_cbc())
+            .field("tz2_cbc", &self.tz2_cbc())
+            .field("tz0_ost", &self.tz0_ost())
+            .field("tz1_ost", &self.tz1_ost())
+            .field("tz2_ost", &self.tz2_ost())
+            .field("cap0", &self.cap0())
+            .field("cap1", &self.cap1())
+            .field("cap2", &self.cap2())
+            .finish()
+    }
+}
+#[doc = "Masked interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct INT_ST_SPEC;
+impl crate::RegisterSpec for INT_ST_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`int_st::R`](R) reader structure"]
+impl crate::Readable for INT_ST_SPEC {}
+#[doc = "`reset()` method sets INT_ST to value 0"]
+impl crate::Resettable for INT_ST_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/mcpwm0/operator_timersel.rs

@@ -0,0 +1,77 @@
+#[doc = "Register `OPERATOR_TIMERSEL` reader"]
+pub type R = crate::R<OPERATOR_TIMERSEL_SPEC>;
+#[doc = "Register `OPERATOR_TIMERSEL` writer"]
+pub type W = crate::W<OPERATOR_TIMERSEL_SPEC>;
+#[doc = "Field `OPERATOR0_TIMERSEL` reader - Select which PWM timer's is the timing reference for PWM operator0, 0: timer0, 1: timer1, 2: timer2"]
+pub type OPERATOR0_TIMERSEL_R = crate::FieldReader;
+#[doc = "Field `OPERATOR0_TIMERSEL` writer - Select which PWM timer's is the timing reference for PWM operator0, 0: timer0, 1: timer1, 2: timer2"]
+pub type OPERATOR0_TIMERSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `OPERATOR1_TIMERSEL` reader - Select which PWM timer's is the timing reference for PWM operator1, 0: timer0, 1: timer1, 2: timer2"]
+pub type OPERATOR1_TIMERSEL_R = crate::FieldReader;
+#[doc = "Field `OPERATOR1_TIMERSEL` writer - Select which PWM timer's is the timing reference for PWM operator1, 0: timer0, 1: timer1, 2: timer2"]
+pub type OPERATOR1_TIMERSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `OPERATOR2_TIMERSEL` reader - Select which PWM timer's is the timing reference for PWM operator2, 0: timer0, 1: timer1, 2: timer2"]
+pub type OPERATOR2_TIMERSEL_R = crate::FieldReader;
+#[doc = "Field `OPERATOR2_TIMERSEL` writer - Select which PWM timer's is the timing reference for PWM operator2, 0: timer0, 1: timer1, 2: timer2"]
+pub type OPERATOR2_TIMERSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+impl R {
+    #[doc = "Bits 0:1 - Select which PWM timer's is the timing reference for PWM operator0, 0: timer0, 1: timer1, 2: timer2"]
+    #[inline(always)]
+    pub fn operator0_timersel(&self) -> OPERATOR0_TIMERSEL_R {
+        OPERATOR0_TIMERSEL_R::new((self.bits & 3) as u8)
+    }
+    #[doc = "Bits 2:3 - Select which PWM timer's is the timing reference for PWM operator1, 0: timer0, 1: timer1, 2: timer2"]
+    #[inline(always)]
+    pub fn operator1_timersel(&self) -> OPERATOR1_TIMERSEL_R {
+        OPERATOR1_TIMERSEL_R::new(((self.bits >> 2) & 3) as u8)
+    }
+    #[doc = "Bits 4:5 - Select which PWM timer's is the timing reference for PWM operator2, 0: timer0, 1: timer1, 2: timer2"]
+    #[inline(always)]
+    pub fn operator2_timersel(&self) -> OPERATOR2_TIMERSEL_R {
+        OPERATOR2_TIMERSEL_R::new(((self.bits >> 4) & 3) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("OPERATOR_TIMERSEL")
+            .field("operator0_timersel", &self.operator0_timersel())
+            .field("operator1_timersel", &self.operator1_timersel())
+            .field("operator2_timersel", &self.operator2_timersel())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:1 - Select which PWM timer's is the timing reference for PWM operator0, 0: timer0, 1: timer1, 2: timer2"]
+    #[inline(always)]
+    pub fn operator0_timersel(&mut self) -> OPERATOR0_TIMERSEL_W<OPERATOR_TIMERSEL_SPEC> {
+        OPERATOR0_TIMERSEL_W::new(self, 0)
+    }
+    #[doc = "Bits 2:3 - Select which PWM timer's is the timing reference for PWM operator1, 0: timer0, 1: timer1, 2: timer2"]
+    #[inline(always)]
+    pub fn operator1_timersel(&mut self) -> OPERATOR1_TIMERSEL_W<OPERATOR_TIMERSEL_SPEC> {
+        OPERATOR1_TIMERSEL_W::new(self, 2)
+    }
+    #[doc = "Bits 4:5 - Select which PWM timer's is the timing reference for PWM operator2, 0: timer0, 1: timer1, 2: timer2"]
+    #[inline(always)]
+    pub fn operator2_timersel(&mut self) -> OPERATOR2_TIMERSEL_W<OPERATOR_TIMERSEL_SPEC> {
+        OPERATOR2_TIMERSEL_W::new(self, 4)
+    }
+}
+#[doc = "Select specific timer for PWM operators.\n\nYou can [`read`](crate::Reg::read) this register and get [`operator_timersel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`operator_timersel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct OPERATOR_TIMERSEL_SPEC;
+impl crate::RegisterSpec for OPERATOR_TIMERSEL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`operator_timersel::R`](R) reader structure"]
+impl crate::Readable for OPERATOR_TIMERSEL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`operator_timersel::W`](W) writer structure"]
+impl crate::Writable for OPERATOR_TIMERSEL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets OPERATOR_TIMERSEL to value 0"]
+impl crate::Resettable for OPERATOR_TIMERSEL_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/mcpwm0/timer.rs

@@ -0,0 +1,47 @@
+#[repr(C)]
+#[cfg_attr(feature = "impl-register-debug", derive(Debug))]
+#[doc = "Cluster TIMER%s, containing TIMER?_CFG0, TIMER?_CFG1, TIMER?_SYNC, TIMER?_STATUS"]
+pub struct TIMER {
+    cfg0: CFG0,
+    cfg1: CFG1,
+    sync: SYNC,
+    status: STATUS,
+}
+impl TIMER {
+    #[doc = "0x00 - PWM TIMERx period and update method configuration register."]
+    #[inline(always)]
+    pub const fn cfg0(&self) -> &CFG0 {
+        &self.cfg0
+    }
+    #[doc = "0x04 - PWM TIMERx working mode and start/stop control configuration register."]
+    #[inline(always)]
+    pub const fn cfg1(&self) -> &CFG1 {
+        &self.cfg1
+    }
+    #[doc = "0x08 - PWM TIMERx sync function configuration register."]
+    #[inline(always)]
+    pub const fn sync(&self) -> &SYNC {
+        &self.sync
+    }
+    #[doc = "0x0c - PWM TIMERx status register."]
+    #[inline(always)]
+    pub const fn status(&self) -> &STATUS {
+        &self.status
+    }
+}
+#[doc = "CFG0 (rw) register accessor: PWM TIMERx period and update method configuration register.\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg0`] module"]
+pub type CFG0 = crate::Reg<cfg0::CFG0_SPEC>;
+#[doc = "PWM TIMERx period and update method configuration register."]
+pub mod cfg0;
+#[doc = "CFG1 (rw) register accessor: PWM TIMERx working mode and start/stop control configuration register.\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg1`] module"]
+pub type CFG1 = crate::Reg<cfg1::CFG1_SPEC>;
+#[doc = "PWM TIMERx working mode and start/stop control configuration register."]
+pub mod cfg1;
+#[doc = "SYNC (rw) register accessor: PWM TIMERx sync function configuration register.\n\nYou can [`read`](crate::Reg::read) this register and get [`sync::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sync::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sync`] module"]
+pub type SYNC = crate::Reg<sync::SYNC_SPEC>;
+#[doc = "PWM TIMERx sync function configuration register."]
+pub mod sync;
+#[doc = "STATUS (r) register accessor: PWM TIMERx status register.\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] module"]
+pub type STATUS = crate::Reg<status::STATUS_SPEC>;
+#[doc = "PWM TIMERx status register."]
+pub mod status;

vendor/esp32s3/src/mcpwm0/timer/cfg0.rs

@@ -0,0 +1,77 @@
+#[doc = "Register `CFG0` reader"]
+pub type R = crate::R<CFG0_SPEC>;
+#[doc = "Register `CFG0` writer"]
+pub type W = crate::W<CFG0_SPEC>;
+#[doc = "Field `PRESCALE` reader - period of PT0_clk = Period of PWM_clk * (PWM_TIMER0_PRESCALE + 1)"]
+pub type PRESCALE_R = crate::FieldReader;
+#[doc = "Field `PRESCALE` writer - period of PT0_clk = Period of PWM_clk * (PWM_TIMER0_PRESCALE + 1)"]
+pub type PRESCALE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+#[doc = "Field `PERIOD` reader - period shadow register of PWM timer0"]
+pub type PERIOD_R = crate::FieldReader<u16>;
+#[doc = "Field `PERIOD` writer - period shadow register of PWM timer0"]
+pub type PERIOD_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
+#[doc = "Field `PERIOD_UPMETHOD` reader - Update method for active register of PWM timer0 period, 0: immediate, 1: TEZ, 2: sync, 3: TEZ | sync. TEZ here and below means timer equal zero event"]
+pub type PERIOD_UPMETHOD_R = crate::FieldReader;
+#[doc = "Field `PERIOD_UPMETHOD` writer - Update method for active register of PWM timer0 period, 0: immediate, 1: TEZ, 2: sync, 3: TEZ | sync. TEZ here and below means timer equal zero event"]
+pub type PERIOD_UPMETHOD_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+impl R {
+    #[doc = "Bits 0:7 - period of PT0_clk = Period of PWM_clk * (PWM_TIMER0_PRESCALE + 1)"]
+    #[inline(always)]
+    pub fn prescale(&self) -> PRESCALE_R {
+        PRESCALE_R::new((self.bits & 0xff) as u8)
+    }
+    #[doc = "Bits 8:23 - period shadow register of PWM timer0"]
+    #[inline(always)]
+    pub fn period(&self) -> PERIOD_R {
+        PERIOD_R::new(((self.bits >> 8) & 0xffff) as u16)
+    }
+    #[doc = "Bits 24:25 - Update method for active register of PWM timer0 period, 0: immediate, 1: TEZ, 2: sync, 3: TEZ | sync. TEZ here and below means timer equal zero event"]
+    #[inline(always)]
+    pub fn period_upmethod(&self) -> PERIOD_UPMETHOD_R {
+        PERIOD_UPMETHOD_R::new(((self.bits >> 24) & 3) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CFG0")
+            .field("prescale", &self.prescale())
+            .field("period", &self.period())
+            .field("period_upmethod", &self.period_upmethod())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - period of PT0_clk = Period of PWM_clk * (PWM_TIMER0_PRESCALE + 1)"]
+    #[inline(always)]
+    pub fn prescale(&mut self) -> PRESCALE_W<CFG0_SPEC> {
+        PRESCALE_W::new(self, 0)
+    }
+    #[doc = "Bits 8:23 - period shadow register of PWM timer0"]
+    #[inline(always)]
+    pub fn period(&mut self) -> PERIOD_W<CFG0_SPEC> {
+        PERIOD_W::new(self, 8)
+    }
+    #[doc = "Bits 24:25 - Update method for active register of PWM timer0 period, 0: immediate, 1: TEZ, 2: sync, 3: TEZ | sync. TEZ here and below means timer equal zero event"]
+    #[inline(always)]
+    pub fn period_upmethod(&mut self) -> PERIOD_UPMETHOD_W<CFG0_SPEC> {
+        PERIOD_UPMETHOD_W::new(self, 24)
+    }
+}
+#[doc = "PWM TIMERx period and update method configuration register.\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CFG0_SPEC;
+impl crate::RegisterSpec for CFG0_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cfg0::R`](R) reader structure"]
+impl crate::Readable for CFG0_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`cfg0::W`](W) writer structure"]
+impl crate::Writable for CFG0_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CFG0 to value 0xff00"]
+impl crate::Resettable for CFG0_SPEC {
+    const RESET_VALUE: u32 = 0xff00;
+}

vendor/esp32s3/src/mcpwm0/timer/cfg1.rs

@@ -0,0 +1,62 @@
+#[doc = "Register `CFG1` reader"]
+pub type R = crate::R<CFG1_SPEC>;
+#[doc = "Register `CFG1` writer"]
+pub type W = crate::W<CFG1_SPEC>;
+#[doc = "Field `START` reader - PWM timer0 start and stop control. 0: if PWM timer0 starts, then stops at TEZ, 1: if timer0 starts, then stops at TEP, 2: PWM timer0 starts and runs on, 3: timer0 starts and stops at the next TEZ, 4: timer0 starts and stops at the next TEP. TEP here and below means the event that happens when the timer equals to period"]
+pub type START_R = crate::FieldReader;
+#[doc = "Field `START` writer - PWM timer0 start and stop control. 0: if PWM timer0 starts, then stops at TEZ, 1: if timer0 starts, then stops at TEP, 2: PWM timer0 starts and runs on, 3: timer0 starts and stops at the next TEZ, 4: timer0 starts and stops at the next TEP. TEP here and below means the event that happens when the timer equals to period"]
+pub type START_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `MOD` reader - PWM timer0 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down mode"]
+pub type MOD_R = crate::FieldReader;
+#[doc = "Field `MOD` writer - PWM timer0 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down mode"]
+pub type MOD_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+impl R {
+    #[doc = "Bits 0:2 - PWM timer0 start and stop control. 0: if PWM timer0 starts, then stops at TEZ, 1: if timer0 starts, then stops at TEP, 2: PWM timer0 starts and runs on, 3: timer0 starts and stops at the next TEZ, 4: timer0 starts and stops at the next TEP. TEP here and below means the event that happens when the timer equals to period"]
+    #[inline(always)]
+    pub fn start(&self) -> START_R {
+        START_R::new((self.bits & 7) as u8)
+    }
+    #[doc = "Bits 3:4 - PWM timer0 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down mode"]
+    #[inline(always)]
+    pub fn mod_(&self) -> MOD_R {
+        MOD_R::new(((self.bits >> 3) & 3) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CFG1")
+            .field("start", &self.start())
+            .field("mod_", &self.mod_())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:2 - PWM timer0 start and stop control. 0: if PWM timer0 starts, then stops at TEZ, 1: if timer0 starts, then stops at TEP, 2: PWM timer0 starts and runs on, 3: timer0 starts and stops at the next TEZ, 4: timer0 starts and stops at the next TEP. TEP here and below means the event that happens when the timer equals to period"]
+    #[inline(always)]
+    pub fn start(&mut self) -> START_W<CFG1_SPEC> {
+        START_W::new(self, 0)
+    }
+    #[doc = "Bits 3:4 - PWM timer0 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down mode"]
+    #[inline(always)]
+    pub fn mod_(&mut self) -> MOD_W<CFG1_SPEC> {
+        MOD_W::new(self, 3)
+    }
+}
+#[doc = "PWM TIMERx working mode and start/stop control configuration register.\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CFG1_SPEC;
+impl crate::RegisterSpec for CFG1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cfg1::R`](R) reader structure"]
+impl crate::Readable for CFG1_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`cfg1::W`](W) writer structure"]
+impl crate::Writable for CFG1_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CFG1 to value 0"]
+impl crate::Resettable for CFG1_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/mcpwm0/timer/status.rs

@@ -0,0 +1,38 @@
+#[doc = "Register `STATUS` reader"]
+pub type R = crate::R<STATUS_SPEC>;
+#[doc = "Field `VALUE` reader - current PWM timer0 counter value"]
+pub type VALUE_R = crate::FieldReader<u16>;
+#[doc = "Field `DIRECTION` reader - current PWM timer0 counter direction, 0: increment 1: decrement"]
+pub type DIRECTION_R = crate::BitReader;
+impl R {
+    #[doc = "Bits 0:15 - current PWM timer0 counter value"]
+    #[inline(always)]
+    pub fn value(&self) -> VALUE_R {
+        VALUE_R::new((self.bits & 0xffff) as u16)
+    }
+    #[doc = "Bit 16 - current PWM timer0 counter direction, 0: increment 1: decrement"]
+    #[inline(always)]
+    pub fn direction(&self) -> DIRECTION_R {
+        DIRECTION_R::new(((self.bits >> 16) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("STATUS")
+            .field("value", &self.value())
+            .field("direction", &self.direction())
+            .finish()
+    }
+}
+#[doc = "PWM TIMERx status register.\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct STATUS_SPEC;
+impl crate::RegisterSpec for STATUS_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`status::R`](R) reader structure"]
+impl crate::Readable for STATUS_SPEC {}
+#[doc = "`reset()` method sets STATUS to value 0"]
+impl crate::Resettable for STATUS_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/mcpwm0/timer/sync.rs

@@ -0,0 +1,107 @@
+#[doc = "Register `SYNC` reader"]
+pub type R = crate::R<SYNC_SPEC>;
+#[doc = "Register `SYNC` writer"]
+pub type W = crate::W<SYNC_SPEC>;
+#[doc = "Field `SYNCI_EN` reader - When set, timer reloading with phase on sync input event is enabled."]
+pub type SYNCI_EN_R = crate::BitReader;
+#[doc = "Field `SYNCI_EN` writer - When set, timer reloading with phase on sync input event is enabled."]
+pub type SYNCI_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SW` reader - Toggling this bit will trigger a software sync."]
+pub type SW_R = crate::BitReader;
+#[doc = "Field `SW` writer - Toggling this bit will trigger a software sync."]
+pub type SW_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SYNCO_SEL` reader - PWM timer0 sync_out selection, 0: synci, 1: TEZ, 2: TEP, otherwise:sync out is software sync"]
+pub type SYNCO_SEL_R = crate::FieldReader;
+#[doc = "Field `SYNCO_SEL` writer - PWM timer0 sync_out selection, 0: synci, 1: TEZ, 2: TEP, otherwise:sync out is software sync"]
+pub type SYNCO_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `PHASE` reader - phase for timer reload on sync event"]
+pub type PHASE_R = crate::FieldReader<u16>;
+#[doc = "Field `PHASE` writer - phase for timer reload on sync event"]
+pub type PHASE_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
+#[doc = "Field `PHASE_DIRECTION` reader - Configure the PWM timer0's direction when timer0 mode is up-down mode. 0: increase; 1: decrease."]
+pub type PHASE_DIRECTION_R = crate::BitReader;
+#[doc = "Field `PHASE_DIRECTION` writer - Configure the PWM timer0's direction when timer0 mode is up-down mode. 0: increase; 1: decrease."]
+pub type PHASE_DIRECTION_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - When set, timer reloading with phase on sync input event is enabled."]
+    #[inline(always)]
+    pub fn synci_en(&self) -> SYNCI_EN_R {
+        SYNCI_EN_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Toggling this bit will trigger a software sync."]
+    #[inline(always)]
+    pub fn sw(&self) -> SW_R {
+        SW_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bits 2:3 - PWM timer0 sync_out selection, 0: synci, 1: TEZ, 2: TEP, otherwise:sync out is software sync"]
+    #[inline(always)]
+    pub fn synco_sel(&self) -> SYNCO_SEL_R {
+        SYNCO_SEL_R::new(((self.bits >> 2) & 3) as u8)
+    }
+    #[doc = "Bits 4:19 - phase for timer reload on sync event"]
+    #[inline(always)]
+    pub fn phase(&self) -> PHASE_R {
+        PHASE_R::new(((self.bits >> 4) & 0xffff) as u16)
+    }
+    #[doc = "Bit 20 - Configure the PWM timer0's direction when timer0 mode is up-down mode. 0: increase; 1: decrease."]
+    #[inline(always)]
+    pub fn phase_direction(&self) -> PHASE_DIRECTION_R {
+        PHASE_DIRECTION_R::new(((self.bits >> 20) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SYNC")
+            .field("synci_en", &self.synci_en())
+            .field("sw", &self.sw())
+            .field("synco_sel", &self.synco_sel())
+            .field("phase", &self.phase())
+            .field("phase_direction", &self.phase_direction())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - When set, timer reloading with phase on sync input event is enabled."]
+    #[inline(always)]
+    pub fn synci_en(&mut self) -> SYNCI_EN_W<SYNC_SPEC> {
+        SYNCI_EN_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - Toggling this bit will trigger a software sync."]
+    #[inline(always)]
+    pub fn sw(&mut self) -> SW_W<SYNC_SPEC> {
+        SW_W::new(self, 1)
+    }
+    #[doc = "Bits 2:3 - PWM timer0 sync_out selection, 0: synci, 1: TEZ, 2: TEP, otherwise:sync out is software sync"]
+    #[inline(always)]
+    pub fn synco_sel(&mut self) -> SYNCO_SEL_W<SYNC_SPEC> {
+        SYNCO_SEL_W::new(self, 2)
+    }
+    #[doc = "Bits 4:19 - phase for timer reload on sync event"]
+    #[inline(always)]
+    pub fn phase(&mut self) -> PHASE_W<SYNC_SPEC> {
+        PHASE_W::new(self, 4)
+    }
+    #[doc = "Bit 20 - Configure the PWM timer0's direction when timer0 mode is up-down mode. 0: increase; 1: decrease."]
+    #[inline(always)]
+    pub fn phase_direction(&mut self) -> PHASE_DIRECTION_W<SYNC_SPEC> {
+        PHASE_DIRECTION_W::new(self, 20)
+    }
+}
+#[doc = "PWM TIMERx sync function configuration register.\n\nYou can [`read`](crate::Reg::read) this register and get [`sync::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sync::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SYNC_SPEC;
+impl crate::RegisterSpec for SYNC_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sync::R`](R) reader structure"]
+impl crate::Readable for SYNC_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sync::W`](W) writer structure"]
+impl crate::Writable for SYNC_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SYNC to value 0"]
+impl crate::Resettable for SYNC_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/mcpwm0/timer_synci_cfg.rs

@@ -0,0 +1,122 @@
+#[doc = "Register `TIMER_SYNCI_CFG` reader"]
+pub type R = crate::R<TIMER_SYNCI_CFG_SPEC>;
+#[doc = "Register `TIMER_SYNCI_CFG` writer"]
+pub type W = crate::W<TIMER_SYNCI_CFG_SPEC>;
+#[doc = "Field `TIMER0_SYNCISEL` reader - select sync input for PWM timer0, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
+pub type TIMER0_SYNCISEL_R = crate::FieldReader;
+#[doc = "Field `TIMER0_SYNCISEL` writer - select sync input for PWM timer0, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
+pub type TIMER0_SYNCISEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `TIMER1_SYNCISEL` reader - select sync input for PWM timer1, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
+pub type TIMER1_SYNCISEL_R = crate::FieldReader;
+#[doc = "Field `TIMER1_SYNCISEL` writer - select sync input for PWM timer1, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
+pub type TIMER1_SYNCISEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `TIMER2_SYNCISEL` reader - select sync input for PWM timer2, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
+pub type TIMER2_SYNCISEL_R = crate::FieldReader;
+#[doc = "Field `TIMER2_SYNCISEL` writer - select sync input for PWM timer2, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
+pub type TIMER2_SYNCISEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `EXTERNAL_SYNCI0_INVERT` reader - invert SYNC0 from GPIO matrix"]
+pub type EXTERNAL_SYNCI0_INVERT_R = crate::BitReader;
+#[doc = "Field `EXTERNAL_SYNCI0_INVERT` writer - invert SYNC0 from GPIO matrix"]
+pub type EXTERNAL_SYNCI0_INVERT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `EXTERNAL_SYNCI1_INVERT` reader - invert SYNC1 from GPIO matrix"]
+pub type EXTERNAL_SYNCI1_INVERT_R = crate::BitReader;
+#[doc = "Field `EXTERNAL_SYNCI1_INVERT` writer - invert SYNC1 from GPIO matrix"]
+pub type EXTERNAL_SYNCI1_INVERT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `EXTERNAL_SYNCI2_INVERT` reader - invert SYNC2 from GPIO matrix"]
+pub type EXTERNAL_SYNCI2_INVERT_R = crate::BitReader;
+#[doc = "Field `EXTERNAL_SYNCI2_INVERT` writer - invert SYNC2 from GPIO matrix"]
+pub type EXTERNAL_SYNCI2_INVERT_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 0:2 - select sync input for PWM timer0, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
+    #[inline(always)]
+    pub fn timer0_syncisel(&self) -> TIMER0_SYNCISEL_R {
+        TIMER0_SYNCISEL_R::new((self.bits & 7) as u8)
+    }
+    #[doc = "Bits 3:5 - select sync input for PWM timer1, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
+    #[inline(always)]
+    pub fn timer1_syncisel(&self) -> TIMER1_SYNCISEL_R {
+        TIMER1_SYNCISEL_R::new(((self.bits >> 3) & 7) as u8)
+    }
+    #[doc = "Bits 6:8 - select sync input for PWM timer2, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
+    #[inline(always)]
+    pub fn timer2_syncisel(&self) -> TIMER2_SYNCISEL_R {
+        TIMER2_SYNCISEL_R::new(((self.bits >> 6) & 7) as u8)
+    }
+    #[doc = "Bit 9 - invert SYNC0 from GPIO matrix"]
+    #[inline(always)]
+    pub fn external_synci0_invert(&self) -> EXTERNAL_SYNCI0_INVERT_R {
+        EXTERNAL_SYNCI0_INVERT_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 10 - invert SYNC1 from GPIO matrix"]
+    #[inline(always)]
+    pub fn external_synci1_invert(&self) -> EXTERNAL_SYNCI1_INVERT_R {
+        EXTERNAL_SYNCI1_INVERT_R::new(((self.bits >> 10) & 1) != 0)
+    }
+    #[doc = "Bit 11 - invert SYNC2 from GPIO matrix"]
+    #[inline(always)]
+    pub fn external_synci2_invert(&self) -> EXTERNAL_SYNCI2_INVERT_R {
+        EXTERNAL_SYNCI2_INVERT_R::new(((self.bits >> 11) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("TIMER_SYNCI_CFG")
+            .field("timer0_syncisel", &self.timer0_syncisel())
+            .field("timer1_syncisel", &self.timer1_syncisel())
+            .field("timer2_syncisel", &self.timer2_syncisel())
+            .field("external_synci0_invert", &self.external_synci0_invert())
+            .field("external_synci1_invert", &self.external_synci1_invert())
+            .field("external_synci2_invert", &self.external_synci2_invert())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:2 - select sync input for PWM timer0, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
+    #[inline(always)]
+    pub fn timer0_syncisel(&mut self) -> TIMER0_SYNCISEL_W<TIMER_SYNCI_CFG_SPEC> {
+        TIMER0_SYNCISEL_W::new(self, 0)
+    }
+    #[doc = "Bits 3:5 - select sync input for PWM timer1, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
+    #[inline(always)]
+    pub fn timer1_syncisel(&mut self) -> TIMER1_SYNCISEL_W<TIMER_SYNCI_CFG_SPEC> {
+        TIMER1_SYNCISEL_W::new(self, 3)
+    }
+    #[doc = "Bits 6:8 - select sync input for PWM timer2, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
+    #[inline(always)]
+    pub fn timer2_syncisel(&mut self) -> TIMER2_SYNCISEL_W<TIMER_SYNCI_CFG_SPEC> {
+        TIMER2_SYNCISEL_W::new(self, 6)
+    }
+    #[doc = "Bit 9 - invert SYNC0 from GPIO matrix"]
+    #[inline(always)]
+    pub fn external_synci0_invert(&mut self) -> EXTERNAL_SYNCI0_INVERT_W<TIMER_SYNCI_CFG_SPEC> {
+        EXTERNAL_SYNCI0_INVERT_W::new(self, 9)
+    }
+    #[doc = "Bit 10 - invert SYNC1 from GPIO matrix"]
+    #[inline(always)]
+    pub fn external_synci1_invert(&mut self) -> EXTERNAL_SYNCI1_INVERT_W<TIMER_SYNCI_CFG_SPEC> {
+        EXTERNAL_SYNCI1_INVERT_W::new(self, 10)
+    }
+    #[doc = "Bit 11 - invert SYNC2 from GPIO matrix"]
+    #[inline(always)]
+    pub fn external_synci2_invert(&mut self) -> EXTERNAL_SYNCI2_INVERT_W<TIMER_SYNCI_CFG_SPEC> {
+        EXTERNAL_SYNCI2_INVERT_W::new(self, 11)
+    }
+}
+#[doc = "Synchronization input selection for three PWM timers.\n\nYou can [`read`](crate::Reg::read) this register and get [`timer_synci_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer_synci_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct TIMER_SYNCI_CFG_SPEC;
+impl crate::RegisterSpec for TIMER_SYNCI_CFG_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`timer_synci_cfg::R`](R) reader structure"]
+impl crate::Readable for TIMER_SYNCI_CFG_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`timer_synci_cfg::W`](W) writer structure"]
+impl crate::Writable for TIMER_SYNCI_CFG_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets TIMER_SYNCI_CFG to value 0"]
+impl crate::Resettable for TIMER_SYNCI_CFG_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/mcpwm0/update_cfg.rs

@@ -0,0 +1,152 @@
+#[doc = "Register `UPDATE_CFG` reader"]
+pub type R = crate::R<UPDATE_CFG_SPEC>;
+#[doc = "Register `UPDATE_CFG` writer"]
+pub type W = crate::W<UPDATE_CFG_SPEC>;
+#[doc = "Field `GLOBAL_UP_EN` reader - The global enable of update of all active registers in MCPWM module"]
+pub type GLOBAL_UP_EN_R = crate::BitReader;
+#[doc = "Field `GLOBAL_UP_EN` writer - The global enable of update of all active registers in MCPWM module"]
+pub type GLOBAL_UP_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `GLOBAL_FORCE_UP` reader - a toggle (software invert its value) will trigger a forced update of all active registers in MCPWM module"]
+pub type GLOBAL_FORCE_UP_R = crate::BitReader;
+#[doc = "Field `GLOBAL_FORCE_UP` writer - a toggle (software invert its value) will trigger a forced update of all active registers in MCPWM module"]
+pub type GLOBAL_FORCE_UP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `OP0_UP_EN` reader - When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 0 are enabled"]
+pub type OP0_UP_EN_R = crate::BitReader;
+#[doc = "Field `OP0_UP_EN` writer - When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 0 are enabled"]
+pub type OP0_UP_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `OP0_FORCE_UP` reader - a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 0"]
+pub type OP0_FORCE_UP_R = crate::BitReader;
+#[doc = "Field `OP0_FORCE_UP` writer - a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 0"]
+pub type OP0_FORCE_UP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `OP1_UP_EN` reader - When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 1 are enabled"]
+pub type OP1_UP_EN_R = crate::BitReader;
+#[doc = "Field `OP1_UP_EN` writer - When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 1 are enabled"]
+pub type OP1_UP_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `OP1_FORCE_UP` reader - a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 1"]
+pub type OP1_FORCE_UP_R = crate::BitReader;
+#[doc = "Field `OP1_FORCE_UP` writer - a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 1"]
+pub type OP1_FORCE_UP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `OP2_UP_EN` reader - When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 2 are enabled"]
+pub type OP2_UP_EN_R = crate::BitReader;
+#[doc = "Field `OP2_UP_EN` writer - When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 2 are enabled"]
+pub type OP2_UP_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `OP2_FORCE_UP` reader - a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 2"]
+pub type OP2_FORCE_UP_R = crate::BitReader;
+#[doc = "Field `OP2_FORCE_UP` writer - a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 2"]
+pub type OP2_FORCE_UP_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - The global enable of update of all active registers in MCPWM module"]
+    #[inline(always)]
+    pub fn global_up_en(&self) -> GLOBAL_UP_EN_R {
+        GLOBAL_UP_EN_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - a toggle (software invert its value) will trigger a forced update of all active registers in MCPWM module"]
+    #[inline(always)]
+    pub fn global_force_up(&self) -> GLOBAL_FORCE_UP_R {
+        GLOBAL_FORCE_UP_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 0 are enabled"]
+    #[inline(always)]
+    pub fn op0_up_en(&self) -> OP0_UP_EN_R {
+        OP0_UP_EN_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 0"]
+    #[inline(always)]
+    pub fn op0_force_up(&self) -> OP0_FORCE_UP_R {
+        OP0_FORCE_UP_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 1 are enabled"]
+    #[inline(always)]
+    pub fn op1_up_en(&self) -> OP1_UP_EN_R {
+        OP1_UP_EN_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 1"]
+    #[inline(always)]
+    pub fn op1_force_up(&self) -> OP1_FORCE_UP_R {
+        OP1_FORCE_UP_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 2 are enabled"]
+    #[inline(always)]
+    pub fn op2_up_en(&self) -> OP2_UP_EN_R {
+        OP2_UP_EN_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 2"]
+    #[inline(always)]
+    pub fn op2_force_up(&self) -> OP2_FORCE_UP_R {
+        OP2_FORCE_UP_R::new(((self.bits >> 7) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("UPDATE_CFG")
+            .field("global_up_en", &self.global_up_en())
+            .field("global_force_up", &self.global_force_up())
+            .field("op0_up_en", &self.op0_up_en())
+            .field("op0_force_up", &self.op0_force_up())
+            .field("op1_up_en", &self.op1_up_en())
+            .field("op1_force_up", &self.op1_force_up())
+            .field("op2_up_en", &self.op2_up_en())
+            .field("op2_force_up", &self.op2_force_up())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - The global enable of update of all active registers in MCPWM module"]
+    #[inline(always)]
+    pub fn global_up_en(&mut self) -> GLOBAL_UP_EN_W<UPDATE_CFG_SPEC> {
+        GLOBAL_UP_EN_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - a toggle (software invert its value) will trigger a forced update of all active registers in MCPWM module"]
+    #[inline(always)]
+    pub fn global_force_up(&mut self) -> GLOBAL_FORCE_UP_W<UPDATE_CFG_SPEC> {
+        GLOBAL_FORCE_UP_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 0 are enabled"]
+    #[inline(always)]
+    pub fn op0_up_en(&mut self) -> OP0_UP_EN_W<UPDATE_CFG_SPEC> {
+        OP0_UP_EN_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 0"]
+    #[inline(always)]
+    pub fn op0_force_up(&mut self) -> OP0_FORCE_UP_W<UPDATE_CFG_SPEC> {
+        OP0_FORCE_UP_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 1 are enabled"]
+    #[inline(always)]
+    pub fn op1_up_en(&mut self) -> OP1_UP_EN_W<UPDATE_CFG_SPEC> {
+        OP1_UP_EN_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 1"]
+    #[inline(always)]
+    pub fn op1_force_up(&mut self) -> OP1_FORCE_UP_W<UPDATE_CFG_SPEC> {
+        OP1_FORCE_UP_W::new(self, 5)
+    }
+    #[doc = "Bit 6 - When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 2 are enabled"]
+    #[inline(always)]
+    pub fn op2_up_en(&mut self) -> OP2_UP_EN_W<UPDATE_CFG_SPEC> {
+        OP2_UP_EN_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 2"]
+    #[inline(always)]
+    pub fn op2_force_up(&mut self) -> OP2_FORCE_UP_W<UPDATE_CFG_SPEC> {
+        OP2_FORCE_UP_W::new(self, 7)
+    }
+}
+#[doc = "Enable update.\n\nYou can [`read`](crate::Reg::read) this register and get [`update_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`update_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct UPDATE_CFG_SPEC;
+impl crate::RegisterSpec for UPDATE_CFG_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`update_cfg::R`](R) reader structure"]
+impl crate::Readable for UPDATE_CFG_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`update_cfg::W`](W) writer structure"]
+impl crate::Writable for UPDATE_CFG_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets UPDATE_CFG to value 0x55"]
+impl crate::Resettable for UPDATE_CFG_SPEC {
+    const RESET_VALUE: u32 = 0x55;
+}

vendor/esp32s3/src/mcpwm0/version.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `VERSION` reader"]
+pub type R = crate::R<VERSION_SPEC>;
+#[doc = "Register `VERSION` writer"]
+pub type W = crate::W<VERSION_SPEC>;
+#[doc = "Field `DATE` reader - Version of this register file"]
+pub type DATE_R = crate::FieldReader<u32>;
+#[doc = "Field `DATE` writer - Version of this register file"]
+pub type DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>;
+impl R {
+    #[doc = "Bits 0:27 - Version of this register file"]
+    #[inline(always)]
+    pub fn date(&self) -> DATE_R {
+        DATE_R::new(self.bits & 0x0fff_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("VERSION")
+            .field("date", &self.date())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:27 - Version of this register file"]
+    #[inline(always)]
+    pub fn date(&mut self) -> DATE_W<VERSION_SPEC> {
+        DATE_W::new(self, 0)
+    }
+}
+#[doc = "Version register.\n\nYou can [`read`](crate::Reg::read) this register and get [`version::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`version::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct VERSION_SPEC;
+impl crate::RegisterSpec for VERSION_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`version::R`](R) reader structure"]
+impl crate::Readable for VERSION_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`version::W`](W) writer structure"]
+impl crate::Writable for VERSION_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets VERSION to value 0x0150_9110"]
+impl crate::Resettable for VERSION_SPEC {
+    const RESET_VALUE: u32 = 0x0150_9110;
+}