feat: add display UI with splash screen, dashboard, and RSSI sparkline

Implement full SSD1306 OLED display support:
- Splash screen on boot (1.5s) with project name, version, board
- Dashboard showing radio state, config, counters, RSSI/SNR
- RSSI history sparkline (64-sample ring buffer, 2px-wide bars)
- DisplayOn/DisplayOff host commands routed via dedicated channel
- Pure render functions against generic DrawTarget (no hardware coupling)
- Display on/off control bypasses radio task entirely

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>

vendor/esp32s3/src/pcnt/ctrl.rs

@@ -0,0 +1,191 @@
+#[doc = "Register `CTRL` reader"]
+pub type R = crate::R<CTRL_SPEC>;
+#[doc = "Register `CTRL` writer"]
+pub type W = crate::W<CTRL_SPEC>;
+#[doc = "Field `CNT_RST_U(0-3)` reader - Set this bit to clear unit%s's counter."]
+pub type CNT_RST_U_R = crate::BitReader;
+#[doc = "Field `CNT_RST_U(0-3)` writer - Set this bit to clear unit%s's counter."]
+pub type CNT_RST_U_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CNT_PAUSE_U(0-3)` reader - Set this bit to pause unit%s's counter."]
+pub type CNT_PAUSE_U_R = crate::BitReader;
+#[doc = "Field `CNT_PAUSE_U(0-3)` writer - Set this bit to pause unit%s's counter."]
+pub type CNT_PAUSE_U_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CLK_EN` reader - The registers clock gate enable signal of PCNT module. 1: the registers can be read and written by application. 0: the registers can not be read or written by application"]
+pub type CLK_EN_R = crate::BitReader;
+#[doc = "Field `CLK_EN` writer - The registers clock gate enable signal of PCNT module. 1: the registers can be read and written by application. 0: the registers can not be read or written by application"]
+pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Set this bit to clear unit(0-3)'s counter."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CNT_RST_U0` field.</div>"]
+    #[inline(always)]
+    pub fn cnt_rst_u(&self, n: u8) -> CNT_RST_U_R {
+        #[allow(clippy::no_effect)]
+        [(); 4][n as usize];
+        CNT_RST_U_R::new(((self.bits >> (n * 2)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "Set this bit to clear unit(0-3)'s counter."]
+    #[inline(always)]
+    pub fn cnt_rst_u_iter(&self) -> impl Iterator<Item = CNT_RST_U_R> + '_ {
+        (0..4).map(move |n| CNT_RST_U_R::new(((self.bits >> (n * 2)) & 1) != 0))
+    }
+    #[doc = "Bit 0 - Set this bit to clear unit0's counter."]
+    #[inline(always)]
+    pub fn cnt_rst_u0(&self) -> CNT_RST_U_R {
+        CNT_RST_U_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 2 - Set this bit to clear unit1's counter."]
+    #[inline(always)]
+    pub fn cnt_rst_u1(&self) -> CNT_RST_U_R {
+        CNT_RST_U_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Set this bit to clear unit2's counter."]
+    #[inline(always)]
+    pub fn cnt_rst_u2(&self) -> CNT_RST_U_R {
+        CNT_RST_U_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 6 - Set this bit to clear unit3's counter."]
+    #[inline(always)]
+    pub fn cnt_rst_u3(&self) -> CNT_RST_U_R {
+        CNT_RST_U_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Set this bit to pause unit(0-3)'s counter."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CNT_PAUSE_U0` field.</div>"]
+    #[inline(always)]
+    pub fn cnt_pause_u(&self, n: u8) -> CNT_PAUSE_U_R {
+        #[allow(clippy::no_effect)]
+        [(); 4][n as usize];
+        CNT_PAUSE_U_R::new(((self.bits >> (n * 2 + 1)) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "Set this bit to pause unit(0-3)'s counter."]
+    #[inline(always)]
+    pub fn cnt_pause_u_iter(&self) -> impl Iterator<Item = CNT_PAUSE_U_R> + '_ {
+        (0..4).map(move |n| CNT_PAUSE_U_R::new(((self.bits >> (n * 2 + 1)) & 1) != 0))
+    }
+    #[doc = "Bit 1 - Set this bit to pause unit0's counter."]
+    #[inline(always)]
+    pub fn cnt_pause_u0(&self) -> CNT_PAUSE_U_R {
+        CNT_PAUSE_U_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Set this bit to pause unit1's counter."]
+    #[inline(always)]
+    pub fn cnt_pause_u1(&self) -> CNT_PAUSE_U_R {
+        CNT_PAUSE_U_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 5 - Set this bit to pause unit2's counter."]
+    #[inline(always)]
+    pub fn cnt_pause_u2(&self) -> CNT_PAUSE_U_R {
+        CNT_PAUSE_U_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 7 - Set this bit to pause unit3's counter."]
+    #[inline(always)]
+    pub fn cnt_pause_u3(&self) -> CNT_PAUSE_U_R {
+        CNT_PAUSE_U_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 16 - The registers clock gate enable signal of PCNT module. 1: the registers can be read and written by application. 0: the registers can not be read or written by application"]
+    #[inline(always)]
+    pub fn clk_en(&self) -> CLK_EN_R {
+        CLK_EN_R::new(((self.bits >> 16) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CTRL")
+            .field("cnt_rst_u0", &self.cnt_rst_u0())
+            .field("cnt_rst_u1", &self.cnt_rst_u1())
+            .field("cnt_rst_u2", &self.cnt_rst_u2())
+            .field("cnt_rst_u3", &self.cnt_rst_u3())
+            .field("cnt_pause_u0", &self.cnt_pause_u0())
+            .field("cnt_pause_u1", &self.cnt_pause_u1())
+            .field("cnt_pause_u2", &self.cnt_pause_u2())
+            .field("cnt_pause_u3", &self.cnt_pause_u3())
+            .field("clk_en", &self.clk_en())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Set this bit to clear unit(0-3)'s counter."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CNT_RST_U0` field.</div>"]
+    #[inline(always)]
+    pub fn cnt_rst_u(&mut self, n: u8) -> CNT_RST_U_W<CTRL_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 4][n as usize];
+        CNT_RST_U_W::new(self, n * 2)
+    }
+    #[doc = "Bit 0 - Set this bit to clear unit0's counter."]
+    #[inline(always)]
+    pub fn cnt_rst_u0(&mut self) -> CNT_RST_U_W<CTRL_SPEC> {
+        CNT_RST_U_W::new(self, 0)
+    }
+    #[doc = "Bit 2 - Set this bit to clear unit1's counter."]
+    #[inline(always)]
+    pub fn cnt_rst_u1(&mut self) -> CNT_RST_U_W<CTRL_SPEC> {
+        CNT_RST_U_W::new(self, 2)
+    }
+    #[doc = "Bit 4 - Set this bit to clear unit2's counter."]
+    #[inline(always)]
+    pub fn cnt_rst_u2(&mut self) -> CNT_RST_U_W<CTRL_SPEC> {
+        CNT_RST_U_W::new(self, 4)
+    }
+    #[doc = "Bit 6 - Set this bit to clear unit3's counter."]
+    #[inline(always)]
+    pub fn cnt_rst_u3(&mut self) -> CNT_RST_U_W<CTRL_SPEC> {
+        CNT_RST_U_W::new(self, 6)
+    }
+    #[doc = "Set this bit to pause unit(0-3)'s counter."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CNT_PAUSE_U0` field.</div>"]
+    #[inline(always)]
+    pub fn cnt_pause_u(&mut self, n: u8) -> CNT_PAUSE_U_W<CTRL_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 4][n as usize];
+        CNT_PAUSE_U_W::new(self, n * 2 + 1)
+    }
+    #[doc = "Bit 1 - Set this bit to pause unit0's counter."]
+    #[inline(always)]
+    pub fn cnt_pause_u0(&mut self) -> CNT_PAUSE_U_W<CTRL_SPEC> {
+        CNT_PAUSE_U_W::new(self, 1)
+    }
+    #[doc = "Bit 3 - Set this bit to pause unit1's counter."]
+    #[inline(always)]
+    pub fn cnt_pause_u1(&mut self) -> CNT_PAUSE_U_W<CTRL_SPEC> {
+        CNT_PAUSE_U_W::new(self, 3)
+    }
+    #[doc = "Bit 5 - Set this bit to pause unit2's counter."]
+    #[inline(always)]
+    pub fn cnt_pause_u2(&mut self) -> CNT_PAUSE_U_W<CTRL_SPEC> {
+        CNT_PAUSE_U_W::new(self, 5)
+    }
+    #[doc = "Bit 7 - Set this bit to pause unit3's counter."]
+    #[inline(always)]
+    pub fn cnt_pause_u3(&mut self) -> CNT_PAUSE_U_W<CTRL_SPEC> {
+        CNT_PAUSE_U_W::new(self, 7)
+    }
+    #[doc = "Bit 16 - The registers clock gate enable signal of PCNT module. 1: the registers can be read and written by application. 0: the registers can not be read or written by application"]
+    #[inline(always)]
+    pub fn clk_en(&mut self) -> CLK_EN_W<CTRL_SPEC> {
+        CLK_EN_W::new(self, 16)
+    }
+}
+#[doc = "Control register for all counters\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CTRL_SPEC;
+impl crate::RegisterSpec for CTRL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"]
+impl crate::Readable for CTRL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
+impl crate::Writable for CTRL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CTRL to value 0x01"]
+impl crate::Resettable for CTRL_SPEC {
+    const RESET_VALUE: u32 = 0x01;
+}

vendor/esp32s3/src/pcnt/date.rs

@@ -0,0 +1,45 @@
+#[doc = "Register `DATE` reader"]
+pub type R = crate::R<DATE_SPEC>;
+#[doc = "Register `DATE` writer"]
+pub type W = crate::W<DATE_SPEC>;
+#[doc = "Field `DATE` reader - This is the PCNT version control register."]
+pub type DATE_R = crate::FieldReader<u32>;
+#[doc = "Field `DATE` writer - This is the PCNT version control register."]
+pub type DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - This is the PCNT version control register."]
+    #[inline(always)]
+    pub fn date(&self) -> DATE_R {
+        DATE_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DATE").field("date", &self.date()).finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - This is the PCNT version control register."]
+    #[inline(always)]
+    pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
+        DATE_W::new(self, 0)
+    }
+}
+#[doc = "PCNT version control register\n\nYou can [`read`](crate::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DATE_SPEC;
+impl crate::RegisterSpec for DATE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`date::R`](R) reader structure"]
+impl crate::Readable for DATE_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"]
+impl crate::Writable for DATE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DATE to value 0x1907_2601"]
+impl crate::Resettable for DATE_SPEC {
+    const RESET_VALUE: u32 = 0x1907_2601;
+}

vendor/esp32s3/src/pcnt/int_clr.rs

@@ -0,0 +1,56 @@
+#[doc = "Register `INT_CLR` writer"]
+pub type W = crate::W<INT_CLR_SPEC>;
+#[doc = "Field `CNT_THR_EVENT_U(0-3)` writer - Set this bit to clear the PCNT_CNT_THR_EVENT_U%s_INT interrupt."]
+pub type CNT_THR_EVENT_U_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "(not readable)")
+    }
+}
+impl W {
+    #[doc = "Set this bit to clear the PCNT_CNT_THR_EVENT_U(0-3)_INT interrupt."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CNT_THR_EVENT_U0` field.</div>"]
+    #[inline(always)]
+    pub fn cnt_thr_event_u(&mut self, n: u8) -> CNT_THR_EVENT_U_W<INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 4][n as usize];
+        CNT_THR_EVENT_U_W::new(self, n)
+    }
+    #[doc = "Bit 0 - Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt."]
+    #[inline(always)]
+    pub fn cnt_thr_event_u0(&mut self) -> CNT_THR_EVENT_U_W<INT_CLR_SPEC> {
+        CNT_THR_EVENT_U_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt."]
+    #[inline(always)]
+    pub fn cnt_thr_event_u1(&mut self) -> CNT_THR_EVENT_U_W<INT_CLR_SPEC> {
+        CNT_THR_EVENT_U_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt."]
+    #[inline(always)]
+    pub fn cnt_thr_event_u2(&mut self) -> CNT_THR_EVENT_U_W<INT_CLR_SPEC> {
+        CNT_THR_EVENT_U_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt."]
+    #[inline(always)]
+    pub fn cnt_thr_event_u3(&mut self) -> CNT_THR_EVENT_U_W<INT_CLR_SPEC> {
+        CNT_THR_EVENT_U_W::new(self, 3)
+    }
+}
+#[doc = "Interrupt clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct INT_CLR_SPEC;
+impl crate::RegisterSpec for INT_CLR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
+impl crate::Writable for INT_CLR_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets INT_CLR to value 0"]
+impl crate::Resettable for INT_CLR_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/pcnt/int_ena.rs

@@ -0,0 +1,104 @@
+#[doc = "Register `INT_ENA` reader"]
+pub type R = crate::R<INT_ENA_SPEC>;
+#[doc = "Register `INT_ENA` writer"]
+pub type W = crate::W<INT_ENA_SPEC>;
+#[doc = "Field `CNT_THR_EVENT_U(0-3)` reader - The interrupt enable bit for the PCNT_CNT_THR_EVENT_U%s_INT interrupt."]
+pub type CNT_THR_EVENT_U_R = crate::BitReader;
+#[doc = "Field `CNT_THR_EVENT_U(0-3)` writer - The interrupt enable bit for the PCNT_CNT_THR_EVENT_U%s_INT interrupt."]
+pub type CNT_THR_EVENT_U_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "The interrupt enable bit for the PCNT_CNT_THR_EVENT_U(0-3)_INT interrupt."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CNT_THR_EVENT_U0` field.</div>"]
+    #[inline(always)]
+    pub fn cnt_thr_event_u(&self, n: u8) -> CNT_THR_EVENT_U_R {
+        #[allow(clippy::no_effect)]
+        [(); 4][n as usize];
+        CNT_THR_EVENT_U_R::new(((self.bits >> n) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The interrupt enable bit for the PCNT_CNT_THR_EVENT_U(0-3)_INT interrupt."]
+    #[inline(always)]
+    pub fn cnt_thr_event_u_iter(&self) -> impl Iterator<Item = CNT_THR_EVENT_U_R> + '_ {
+        (0..4).map(move |n| CNT_THR_EVENT_U_R::new(((self.bits >> n) & 1) != 0))
+    }
+    #[doc = "Bit 0 - The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt."]
+    #[inline(always)]
+    pub fn cnt_thr_event_u0(&self) -> CNT_THR_EVENT_U_R {
+        CNT_THR_EVENT_U_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt."]
+    #[inline(always)]
+    pub fn cnt_thr_event_u1(&self) -> CNT_THR_EVENT_U_R {
+        CNT_THR_EVENT_U_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt."]
+    #[inline(always)]
+    pub fn cnt_thr_event_u2(&self) -> CNT_THR_EVENT_U_R {
+        CNT_THR_EVENT_U_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt."]
+    #[inline(always)]
+    pub fn cnt_thr_event_u3(&self) -> CNT_THR_EVENT_U_R {
+        CNT_THR_EVENT_U_R::new(((self.bits >> 3) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("INT_ENA")
+            .field("cnt_thr_event_u0", &self.cnt_thr_event_u0())
+            .field("cnt_thr_event_u1", &self.cnt_thr_event_u1())
+            .field("cnt_thr_event_u2", &self.cnt_thr_event_u2())
+            .field("cnt_thr_event_u3", &self.cnt_thr_event_u3())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "The interrupt enable bit for the PCNT_CNT_THR_EVENT_U(0-3)_INT interrupt."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CNT_THR_EVENT_U0` field.</div>"]
+    #[inline(always)]
+    pub fn cnt_thr_event_u(&mut self, n: u8) -> CNT_THR_EVENT_U_W<INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 4][n as usize];
+        CNT_THR_EVENT_U_W::new(self, n)
+    }
+    #[doc = "Bit 0 - The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt."]
+    #[inline(always)]
+    pub fn cnt_thr_event_u0(&mut self) -> CNT_THR_EVENT_U_W<INT_ENA_SPEC> {
+        CNT_THR_EVENT_U_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt."]
+    #[inline(always)]
+    pub fn cnt_thr_event_u1(&mut self) -> CNT_THR_EVENT_U_W<INT_ENA_SPEC> {
+        CNT_THR_EVENT_U_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt."]
+    #[inline(always)]
+    pub fn cnt_thr_event_u2(&mut self) -> CNT_THR_EVENT_U_W<INT_ENA_SPEC> {
+        CNT_THR_EVENT_U_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt."]
+    #[inline(always)]
+    pub fn cnt_thr_event_u3(&mut self) -> CNT_THR_EVENT_U_W<INT_ENA_SPEC> {
+        CNT_THR_EVENT_U_W::new(self, 3)
+    }
+}
+#[doc = "Interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct INT_ENA_SPEC;
+impl crate::RegisterSpec for INT_ENA_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"]
+impl crate::Readable for INT_ENA_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"]
+impl crate::Writable for INT_ENA_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets INT_ENA to value 0"]
+impl crate::Resettable for INT_ENA_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/pcnt/int_raw.rs

@@ -0,0 +1,63 @@
+#[doc = "Register `INT_RAW` reader"]
+pub type R = crate::R<INT_RAW_SPEC>;
+#[doc = "Field `CNT_THR_EVENT_U(0-3)` reader - The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U%s_INT interrupt."]
+pub type CNT_THR_EVENT_U_R = crate::BitReader;
+impl R {
+    #[doc = "The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U(0-3)_INT interrupt."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CNT_THR_EVENT_U0` field.</div>"]
+    #[inline(always)]
+    pub fn cnt_thr_event_u(&self, n: u8) -> CNT_THR_EVENT_U_R {
+        #[allow(clippy::no_effect)]
+        [(); 4][n as usize];
+        CNT_THR_EVENT_U_R::new(((self.bits >> n) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U(0-3)_INT interrupt."]
+    #[inline(always)]
+    pub fn cnt_thr_event_u_iter(&self) -> impl Iterator<Item = CNT_THR_EVENT_U_R> + '_ {
+        (0..4).map(move |n| CNT_THR_EVENT_U_R::new(((self.bits >> n) & 1) != 0))
+    }
+    #[doc = "Bit 0 - The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt."]
+    #[inline(always)]
+    pub fn cnt_thr_event_u0(&self) -> CNT_THR_EVENT_U_R {
+        CNT_THR_EVENT_U_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt."]
+    #[inline(always)]
+    pub fn cnt_thr_event_u1(&self) -> CNT_THR_EVENT_U_R {
+        CNT_THR_EVENT_U_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt."]
+    #[inline(always)]
+    pub fn cnt_thr_event_u2(&self) -> CNT_THR_EVENT_U_R {
+        CNT_THR_EVENT_U_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt."]
+    #[inline(always)]
+    pub fn cnt_thr_event_u3(&self) -> CNT_THR_EVENT_U_R {
+        CNT_THR_EVENT_U_R::new(((self.bits >> 3) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("INT_RAW")
+            .field("cnt_thr_event_u0", &self.cnt_thr_event_u0())
+            .field("cnt_thr_event_u1", &self.cnt_thr_event_u1())
+            .field("cnt_thr_event_u2", &self.cnt_thr_event_u2())
+            .field("cnt_thr_event_u3", &self.cnt_thr_event_u3())
+            .finish()
+    }
+}
+#[doc = "Interrupt raw status register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_raw::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct INT_RAW_SPEC;
+impl crate::RegisterSpec for INT_RAW_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"]
+impl crate::Readable for INT_RAW_SPEC {}
+#[doc = "`reset()` method sets INT_RAW to value 0"]
+impl crate::Resettable for INT_RAW_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/pcnt/int_st.rs

@@ -0,0 +1,63 @@
+#[doc = "Register `INT_ST` reader"]
+pub type R = crate::R<INT_ST_SPEC>;
+#[doc = "Field `CNT_THR_EVENT_U(0-3)` reader - The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U%s_INT interrupt."]
+pub type CNT_THR_EVENT_U_R = crate::BitReader;
+impl R {
+    #[doc = "The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U(0-3)_INT interrupt."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CNT_THR_EVENT_U0` field.</div>"]
+    #[inline(always)]
+    pub fn cnt_thr_event_u(&self, n: u8) -> CNT_THR_EVENT_U_R {
+        #[allow(clippy::no_effect)]
+        [(); 4][n as usize];
+        CNT_THR_EVENT_U_R::new(((self.bits >> n) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U(0-3)_INT interrupt."]
+    #[inline(always)]
+    pub fn cnt_thr_event_u_iter(&self) -> impl Iterator<Item = CNT_THR_EVENT_U_R> + '_ {
+        (0..4).map(move |n| CNT_THR_EVENT_U_R::new(((self.bits >> n) & 1) != 0))
+    }
+    #[doc = "Bit 0 - The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt."]
+    #[inline(always)]
+    pub fn cnt_thr_event_u0(&self) -> CNT_THR_EVENT_U_R {
+        CNT_THR_EVENT_U_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt."]
+    #[inline(always)]
+    pub fn cnt_thr_event_u1(&self) -> CNT_THR_EVENT_U_R {
+        CNT_THR_EVENT_U_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt."]
+    #[inline(always)]
+    pub fn cnt_thr_event_u2(&self) -> CNT_THR_EVENT_U_R {
+        CNT_THR_EVENT_U_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt."]
+    #[inline(always)]
+    pub fn cnt_thr_event_u3(&self) -> CNT_THR_EVENT_U_R {
+        CNT_THR_EVENT_U_R::new(((self.bits >> 3) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("INT_ST")
+            .field("cnt_thr_event_u0", &self.cnt_thr_event_u0())
+            .field("cnt_thr_event_u1", &self.cnt_thr_event_u1())
+            .field("cnt_thr_event_u2", &self.cnt_thr_event_u2())
+            .field("cnt_thr_event_u3", &self.cnt_thr_event_u3())
+            .finish()
+    }
+}
+#[doc = "Interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct INT_ST_SPEC;
+impl crate::RegisterSpec for INT_ST_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`int_st::R`](R) reader structure"]
+impl crate::Readable for INT_ST_SPEC {}
+#[doc = "`reset()` method sets INT_ST to value 0"]
+impl crate::Resettable for INT_ST_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/pcnt/u_cnt.rs

@@ -0,0 +1,28 @@
+#[doc = "Register `U%s_CNT` reader"]
+pub type R = crate::R<U_CNT_SPEC>;
+#[doc = "Field `CNT` reader - This register stores the current pulse count value for unit %s."]
+pub type CNT_R = crate::FieldReader<u16>;
+impl R {
+    #[doc = "Bits 0:15 - This register stores the current pulse count value for unit %s."]
+    #[inline(always)]
+    pub fn cnt(&self) -> CNT_R {
+        CNT_R::new((self.bits & 0xffff) as u16)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("U_CNT").field("cnt", &self.cnt()).finish()
+    }
+}
+#[doc = "Counter value for unit %s\n\nYou can [`read`](crate::Reg::read) this register and get [`u_cnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct U_CNT_SPEC;
+impl crate::RegisterSpec for U_CNT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`u_cnt::R`](R) reader structure"]
+impl crate::Readable for U_CNT_SPEC {}
+#[doc = "`reset()` method sets U%s_CNT to value 0"]
+impl crate::Resettable for U_CNT_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/pcnt/u_status.rs

@@ -0,0 +1,70 @@
+#[doc = "Register `U%s_STATUS` reader"]
+pub type R = crate::R<U_STATUS_SPEC>;
+#[doc = "Field `ZERO_MODE` reader - The pulse counter status of PCNT_U%s corresponding to 0. 0: pulse counter decreases from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter is negative. 3: pulse counter is positive."]
+pub type ZERO_MODE_R = crate::FieldReader;
+#[doc = "Field `THRES1` reader - The latched value of thres1 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: others"]
+pub type THRES1_R = crate::BitReader;
+#[doc = "Field `THRES0` reader - The latched value of thres0 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: others"]
+pub type THRES0_R = crate::BitReader;
+#[doc = "Field `L_LIM` reader - The latched value of low limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_l_lim and low limit event is valid. 0: others"]
+pub type L_LIM_R = crate::BitReader;
+#[doc = "Field `H_LIM` reader - The latched value of high limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_h_lim and high limit event is valid. 0: others"]
+pub type H_LIM_R = crate::BitReader;
+#[doc = "Field `ZERO` reader - The latched value of zero threshold event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to 0 and zero threshold event is valid. 0: others"]
+pub type ZERO_R = crate::BitReader;
+impl R {
+    #[doc = "Bits 0:1 - The pulse counter status of PCNT_U%s corresponding to 0. 0: pulse counter decreases from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter is negative. 3: pulse counter is positive."]
+    #[inline(always)]
+    pub fn zero_mode(&self) -> ZERO_MODE_R {
+        ZERO_MODE_R::new((self.bits & 3) as u8)
+    }
+    #[doc = "Bit 2 - The latched value of thres1 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: others"]
+    #[inline(always)]
+    pub fn thres1(&self) -> THRES1_R {
+        THRES1_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - The latched value of thres0 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: others"]
+    #[inline(always)]
+    pub fn thres0(&self) -> THRES0_R {
+        THRES0_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - The latched value of low limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_l_lim and low limit event is valid. 0: others"]
+    #[inline(always)]
+    pub fn l_lim(&self) -> L_LIM_R {
+        L_LIM_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - The latched value of high limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_h_lim and high limit event is valid. 0: others"]
+    #[inline(always)]
+    pub fn h_lim(&self) -> H_LIM_R {
+        H_LIM_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - The latched value of zero threshold event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to 0 and zero threshold event is valid. 0: others"]
+    #[inline(always)]
+    pub fn zero(&self) -> ZERO_R {
+        ZERO_R::new(((self.bits >> 6) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("U_STATUS")
+            .field("zero_mode", &self.zero_mode())
+            .field("thres1", &self.thres1())
+            .field("thres0", &self.thres0())
+            .field("l_lim", &self.l_lim())
+            .field("h_lim", &self.h_lim())
+            .field("zero", &self.zero())
+            .finish()
+    }
+}
+#[doc = "PNCT UNIT%s status register\n\nYou can [`read`](crate::Reg::read) this register and get [`u_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct U_STATUS_SPEC;
+impl crate::RegisterSpec for U_STATUS_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`u_status::R`](R) reader structure"]
+impl crate::Readable for U_STATUS_SPEC {}
+#[doc = "`reset()` method sets U%s_STATUS to value 0"]
+impl crate::Resettable for U_STATUS_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/pcnt/unit.rs

@@ -0,0 +1,37 @@
+#[repr(C)]
+#[cfg_attr(feature = "impl-register-debug", derive(Debug))]
+#[doc = "Cluster UNIT%s, containing U?_CONF0, U?_CONF1, U?_CONF2"]
+pub struct UNIT {
+    conf0: CONF0,
+    conf1: CONF1,
+    conf2: CONF2,
+}
+impl UNIT {
+    #[doc = "0x00 - Configuration register 0 for unit"]
+    #[inline(always)]
+    pub const fn conf0(&self) -> &CONF0 {
+        &self.conf0
+    }
+    #[doc = "0x04 - Configuration register 1 for unit 0"]
+    #[inline(always)]
+    pub const fn conf1(&self) -> &CONF1 {
+        &self.conf1
+    }
+    #[doc = "0x08 - Configuration register 2 for unit 0"]
+    #[inline(always)]
+    pub const fn conf2(&self) -> &CONF2 {
+        &self.conf2
+    }
+}
+#[doc = "CONF0 (rw) register accessor: Configuration register 0 for unit\n\nYou can [`read`](crate::Reg::read) this register and get [`conf0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`conf0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@conf0`] module"]
+pub type CONF0 = crate::Reg<conf0::CONF0_SPEC>;
+#[doc = "Configuration register 0 for unit"]
+pub mod conf0;
+#[doc = "CONF1 (rw) register accessor: Configuration register 1 for unit 0\n\nYou can [`read`](crate::Reg::read) this register and get [`conf1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`conf1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@conf1`] module"]
+pub type CONF1 = crate::Reg<conf1::CONF1_SPEC>;
+#[doc = "Configuration register 1 for unit 0"]
+pub mod conf1;
+#[doc = "CONF2 (rw) register accessor: Configuration register 2 for unit 0\n\nYou can [`read`](crate::Reg::read) this register and get [`conf2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`conf2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@conf2`] module"]
+pub type CONF2 = crate::Reg<conf2::CONF2_SPEC>;
+#[doc = "Configuration register 2 for unit 0"]
+pub mod conf2;

vendor/esp32s3/src/pcnt/unit/conf0.rs

@@ -0,0 +1,475 @@
+#[doc = "Register `CONF0` reader"]
+pub type R = crate::R<CONF0_SPEC>;
+#[doc = "Register `CONF0` writer"]
+pub type W = crate::W<CONF0_SPEC>;
+#[doc = "Field `FILTER_THRES` reader - This sets the maximum threshold, in APB_CLK cycles, for the filter. Any pulses with width less than this will be ignored when the filter is enabled."]
+pub type FILTER_THRES_R = crate::FieldReader<u16>;
+#[doc = "Field `FILTER_THRES` writer - This sets the maximum threshold, in APB_CLK cycles, for the filter. Any pulses with width less than this will be ignored when the filter is enabled."]
+pub type FILTER_THRES_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
+#[doc = "Field `FILTER_EN` reader - This is the enable bit for unit %s's input filter."]
+pub type FILTER_EN_R = crate::BitReader;
+#[doc = "Field `FILTER_EN` writer - This is the enable bit for unit %s's input filter."]
+pub type FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `THR_ZERO_EN` reader - This is the enable bit for unit %s's zero comparator."]
+pub type THR_ZERO_EN_R = crate::BitReader;
+#[doc = "Field `THR_ZERO_EN` writer - This is the enable bit for unit %s's zero comparator."]
+pub type THR_ZERO_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `THR_H_LIM_EN` reader - This is the enable bit for unit %s's thr_h_lim comparator."]
+pub type THR_H_LIM_EN_R = crate::BitReader;
+#[doc = "Field `THR_H_LIM_EN` writer - This is the enable bit for unit %s's thr_h_lim comparator."]
+pub type THR_H_LIM_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `THR_L_LIM_EN` reader - This is the enable bit for unit %s's thr_l_lim comparator."]
+pub type THR_L_LIM_EN_R = crate::BitReader;
+#[doc = "Field `THR_L_LIM_EN` writer - This is the enable bit for unit %s's thr_l_lim comparator."]
+pub type THR_L_LIM_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `THR_THRES0_EN` reader - This is the enable bit for unit %s's thres0 comparator."]
+pub type THR_THRES0_EN_R = crate::BitReader;
+#[doc = "Field `THR_THRES0_EN` writer - This is the enable bit for unit %s's thres0 comparator."]
+pub type THR_THRES0_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `THR_THRES1_EN` reader - This is the enable bit for unit %s's thres1 comparator."]
+pub type THR_THRES1_EN_R = crate::BitReader;
+#[doc = "Field `THR_THRES1_EN` writer - This is the enable bit for unit %s's thres1 comparator."]
+pub type THR_THRES1_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Configures the behavior when the signal input of channel %s detects a negative edge.\n\nValue on reset: 0"]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+#[repr(u8)]
+pub enum EDGE_MODE {
+    #[doc = "1: Increase the counter"]
+    Increment = 1,
+    #[doc = "2: Decrease the counter"]
+    Decrement = 2,
+    #[doc = "0: No effect on counter"]
+    Hold = 0,
+}
+impl From<EDGE_MODE> for u8 {
+    #[inline(always)]
+    fn from(variant: EDGE_MODE) -> Self {
+        variant as _
+    }
+}
+impl crate::FieldSpec for EDGE_MODE {
+    type Ux = u8;
+}
+impl crate::IsEnum for EDGE_MODE {}
+#[doc = "Field `CH_NEG_MODE(0-1)` reader - Configures the behavior when the signal input of channel %s detects a negative edge."]
+pub type CH_NEG_MODE_R = crate::FieldReader<EDGE_MODE>;
+impl CH_NEG_MODE_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub const fn variant(&self) -> EDGE_MODE {
+        match self.bits {
+            1 => EDGE_MODE::Increment,
+            2 => EDGE_MODE::Decrement,
+            _ => EDGE_MODE::Hold,
+        }
+    }
+    #[doc = "Increase the counter"]
+    #[inline(always)]
+    pub fn is_increment(&self) -> bool {
+        *self == EDGE_MODE::Increment
+    }
+    #[doc = "Decrease the counter"]
+    #[inline(always)]
+    pub fn is_decrement(&self) -> bool {
+        *self == EDGE_MODE::Decrement
+    }
+    #[doc = "No effect on counter"]
+    #[inline(always)]
+    pub fn is_hold(&self) -> bool {
+        matches!(self.variant(), EDGE_MODE::Hold)
+    }
+}
+#[doc = "Field `CH_NEG_MODE(0-1)` writer - Configures the behavior when the signal input of channel %s detects a negative edge."]
+pub type CH_NEG_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, EDGE_MODE, crate::Safe>;
+impl<'a, REG> CH_NEG_MODE_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+    REG::Ux: From<u8>,
+{
+    #[doc = "Increase the counter"]
+    #[inline(always)]
+    pub fn increment(self) -> &'a mut crate::W<REG> {
+        self.variant(EDGE_MODE::Increment)
+    }
+    #[doc = "Decrease the counter"]
+    #[inline(always)]
+    pub fn decrement(self) -> &'a mut crate::W<REG> {
+        self.variant(EDGE_MODE::Decrement)
+    }
+    #[doc = "No effect on counter"]
+    #[inline(always)]
+    pub fn hold(self) -> &'a mut crate::W<REG> {
+        self.variant(EDGE_MODE::Hold)
+    }
+}
+#[doc = "Field `CH_POS_MODE(0-1)` reader - Configures the behavior when the signal input of channel %s detects a positive edge."]
+pub use CH_NEG_MODE_R as CH_POS_MODE_R;
+#[doc = "Field `CH_POS_MODE(0-1)` writer - Configures the behavior when the signal input of channel %s detects a positive edge."]
+pub use CH_NEG_MODE_W as CH_POS_MODE_W;
+#[doc = "Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the control signal is high.\n\nValue on reset: 0"]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+#[repr(u8)]
+pub enum CTRL_MODE {
+    #[doc = "0: No modification"]
+    Keep = 0,
+    #[doc = "1: Invert behavior (increase -> decrease"]
+    Reverse = 1,
+    #[doc = "2: Inhibit counter modification"]
+    Disable = 2,
+}
+impl From<CTRL_MODE> for u8 {
+    #[inline(always)]
+    fn from(variant: CTRL_MODE) -> Self {
+        variant as _
+    }
+}
+impl crate::FieldSpec for CTRL_MODE {
+    type Ux = u8;
+}
+impl crate::IsEnum for CTRL_MODE {}
+#[doc = "Field `CH_HCTRL_MODE(0-1)` reader - Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the control signal is high."]
+pub type CH_HCTRL_MODE_R = crate::FieldReader<CTRL_MODE>;
+impl CH_HCTRL_MODE_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub const fn variant(&self) -> CTRL_MODE {
+        match self.bits {
+            0 => CTRL_MODE::Keep,
+            1 => CTRL_MODE::Reverse,
+            _ => CTRL_MODE::Disable,
+        }
+    }
+    #[doc = "No modification"]
+    #[inline(always)]
+    pub fn is_keep(&self) -> bool {
+        *self == CTRL_MODE::Keep
+    }
+    #[doc = "Invert behavior (increase -> decrease"]
+    #[inline(always)]
+    pub fn is_reverse(&self) -> bool {
+        *self == CTRL_MODE::Reverse
+    }
+    #[doc = "Inhibit counter modification"]
+    #[inline(always)]
+    pub fn is_disable(&self) -> bool {
+        matches!(self.variant(), CTRL_MODE::Disable)
+    }
+}
+#[doc = "Field `CH_HCTRL_MODE(0-1)` writer - Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the control signal is high."]
+pub type CH_HCTRL_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, CTRL_MODE, crate::Safe>;
+impl<'a, REG> CH_HCTRL_MODE_W<'a, REG>
+where
+    REG: crate::Writable + crate::RegisterSpec,
+    REG::Ux: From<u8>,
+{
+    #[doc = "No modification"]
+    #[inline(always)]
+    pub fn keep(self) -> &'a mut crate::W<REG> {
+        self.variant(CTRL_MODE::Keep)
+    }
+    #[doc = "Invert behavior (increase -> decrease"]
+    #[inline(always)]
+    pub fn reverse(self) -> &'a mut crate::W<REG> {
+        self.variant(CTRL_MODE::Reverse)
+    }
+    #[doc = "Inhibit counter modification"]
+    #[inline(always)]
+    pub fn disable(self) -> &'a mut crate::W<REG> {
+        self.variant(CTRL_MODE::Disable)
+    }
+}
+#[doc = "Field `CH_LCTRL_MODE(0-1)` reader - Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the control signal is low."]
+pub use CH_HCTRL_MODE_R as CH_LCTRL_MODE_R;
+#[doc = "Field `CH_LCTRL_MODE(0-1)` writer - Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the control signal is low."]
+pub use CH_HCTRL_MODE_W as CH_LCTRL_MODE_W;
+impl R {
+    #[doc = "Bits 0:9 - This sets the maximum threshold, in APB_CLK cycles, for the filter. Any pulses with width less than this will be ignored when the filter is enabled."]
+    #[inline(always)]
+    pub fn filter_thres(&self) -> FILTER_THRES_R {
+        FILTER_THRES_R::new((self.bits & 0x03ff) as u16)
+    }
+    #[doc = "Bit 10 - This is the enable bit for unit %s's input filter."]
+    #[inline(always)]
+    pub fn filter_en(&self) -> FILTER_EN_R {
+        FILTER_EN_R::new(((self.bits >> 10) & 1) != 0)
+    }
+    #[doc = "Bit 11 - This is the enable bit for unit %s's zero comparator."]
+    #[inline(always)]
+    pub fn thr_zero_en(&self) -> THR_ZERO_EN_R {
+        THR_ZERO_EN_R::new(((self.bits >> 11) & 1) != 0)
+    }
+    #[doc = "Bit 12 - This is the enable bit for unit %s's thr_h_lim comparator."]
+    #[inline(always)]
+    pub fn thr_h_lim_en(&self) -> THR_H_LIM_EN_R {
+        THR_H_LIM_EN_R::new(((self.bits >> 12) & 1) != 0)
+    }
+    #[doc = "Bit 13 - This is the enable bit for unit %s's thr_l_lim comparator."]
+    #[inline(always)]
+    pub fn thr_l_lim_en(&self) -> THR_L_LIM_EN_R {
+        THR_L_LIM_EN_R::new(((self.bits >> 13) & 1) != 0)
+    }
+    #[doc = "Bit 14 - This is the enable bit for unit %s's thres0 comparator."]
+    #[inline(always)]
+    pub fn thr_thres0_en(&self) -> THR_THRES0_EN_R {
+        THR_THRES0_EN_R::new(((self.bits >> 14) & 1) != 0)
+    }
+    #[doc = "Bit 15 - This is the enable bit for unit %s's thres1 comparator."]
+    #[inline(always)]
+    pub fn thr_thres1_en(&self) -> THR_THRES1_EN_R {
+        THR_THRES1_EN_R::new(((self.bits >> 15) & 1) != 0)
+    }
+    #[doc = "Configures the behavior when the signal input of channel (0-1) detects a negative edge."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_NEG_MODE` field.</div>"]
+    #[inline(always)]
+    pub fn ch_neg_mode(&self, n: u8) -> CH_NEG_MODE_R {
+        #[allow(clippy::no_effect)]
+        [(); 2][n as usize];
+        CH_NEG_MODE_R::new(((self.bits >> (n * 8 + 16)) & 3) as u8)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "Configures the behavior when the signal input of channel (0-1) detects a negative edge."]
+    #[inline(always)]
+    pub fn ch_neg_mode_iter(&self) -> impl Iterator<Item = CH_NEG_MODE_R> + '_ {
+        (0..2).map(move |n| CH_NEG_MODE_R::new(((self.bits >> (n * 8 + 16)) & 3) as u8))
+    }
+    #[doc = "Bits 16:17 - Configures the behavior when the signal input of channel 0 detects a negative edge."]
+    #[inline(always)]
+    pub fn ch0_neg_mode(&self) -> CH_NEG_MODE_R {
+        CH_NEG_MODE_R::new(((self.bits >> 16) & 3) as u8)
+    }
+    #[doc = "Bits 24:25 - Configures the behavior when the signal input of channel 1 detects a negative edge."]
+    #[inline(always)]
+    pub fn ch1_neg_mode(&self) -> CH_NEG_MODE_R {
+        CH_NEG_MODE_R::new(((self.bits >> 24) & 3) as u8)
+    }
+    #[doc = "Configures the behavior when the signal input of channel (0-1) detects a positive edge."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_POS_MODE` field.</div>"]
+    #[inline(always)]
+    pub fn ch_pos_mode(&self, n: u8) -> CH_POS_MODE_R {
+        #[allow(clippy::no_effect)]
+        [(); 2][n as usize];
+        CH_POS_MODE_R::new(((self.bits >> (n * 8 + 18)) & 3) as u8)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "Configures the behavior when the signal input of channel (0-1) detects a positive edge."]
+    #[inline(always)]
+    pub fn ch_pos_mode_iter(&self) -> impl Iterator<Item = CH_POS_MODE_R> + '_ {
+        (0..2).map(move |n| CH_POS_MODE_R::new(((self.bits >> (n * 8 + 18)) & 3) as u8))
+    }
+    #[doc = "Bits 18:19 - Configures the behavior when the signal input of channel 0 detects a positive edge."]
+    #[inline(always)]
+    pub fn ch0_pos_mode(&self) -> CH_POS_MODE_R {
+        CH_POS_MODE_R::new(((self.bits >> 18) & 3) as u8)
+    }
+    #[doc = "Bits 26:27 - Configures the behavior when the signal input of channel 1 detects a positive edge."]
+    #[inline(always)]
+    pub fn ch1_pos_mode(&self) -> CH_POS_MODE_R {
+        CH_POS_MODE_R::new(((self.bits >> 26) & 3) as u8)
+    }
+    #[doc = "Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the control signal is high."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_HCTRL_MODE` field.</div>"]
+    #[inline(always)]
+    pub fn ch_hctrl_mode(&self, n: u8) -> CH_HCTRL_MODE_R {
+        #[allow(clippy::no_effect)]
+        [(); 2][n as usize];
+        CH_HCTRL_MODE_R::new(((self.bits >> (n * 8 + 20)) & 3) as u8)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the control signal is high."]
+    #[inline(always)]
+    pub fn ch_hctrl_mode_iter(&self) -> impl Iterator<Item = CH_HCTRL_MODE_R> + '_ {
+        (0..2).map(move |n| CH_HCTRL_MODE_R::new(((self.bits >> (n * 8 + 20)) & 3) as u8))
+    }
+    #[doc = "Bits 20:21 - Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the control signal is high."]
+    #[inline(always)]
+    pub fn ch0_hctrl_mode(&self) -> CH_HCTRL_MODE_R {
+        CH_HCTRL_MODE_R::new(((self.bits >> 20) & 3) as u8)
+    }
+    #[doc = "Bits 28:29 - Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the control signal is high."]
+    #[inline(always)]
+    pub fn ch1_hctrl_mode(&self) -> CH_HCTRL_MODE_R {
+        CH_HCTRL_MODE_R::new(((self.bits >> 28) & 3) as u8)
+    }
+    #[doc = "Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the control signal is low."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_LCTRL_MODE` field.</div>"]
+    #[inline(always)]
+    pub fn ch_lctrl_mode(&self, n: u8) -> CH_LCTRL_MODE_R {
+        #[allow(clippy::no_effect)]
+        [(); 2][n as usize];
+        CH_LCTRL_MODE_R::new(((self.bits >> (n * 8 + 22)) & 3) as u8)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the control signal is low."]
+    #[inline(always)]
+    pub fn ch_lctrl_mode_iter(&self) -> impl Iterator<Item = CH_LCTRL_MODE_R> + '_ {
+        (0..2).map(move |n| CH_LCTRL_MODE_R::new(((self.bits >> (n * 8 + 22)) & 3) as u8))
+    }
+    #[doc = "Bits 22:23 - Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the control signal is low."]
+    #[inline(always)]
+    pub fn ch0_lctrl_mode(&self) -> CH_LCTRL_MODE_R {
+        CH_LCTRL_MODE_R::new(((self.bits >> 22) & 3) as u8)
+    }
+    #[doc = "Bits 30:31 - Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the control signal is low."]
+    #[inline(always)]
+    pub fn ch1_lctrl_mode(&self) -> CH_LCTRL_MODE_R {
+        CH_LCTRL_MODE_R::new(((self.bits >> 30) & 3) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CONF0")
+            .field("filter_thres", &self.filter_thres())
+            .field("filter_en", &self.filter_en())
+            .field("thr_zero_en", &self.thr_zero_en())
+            .field("thr_h_lim_en", &self.thr_h_lim_en())
+            .field("thr_l_lim_en", &self.thr_l_lim_en())
+            .field("thr_thres0_en", &self.thr_thres0_en())
+            .field("thr_thres1_en", &self.thr_thres1_en())
+            .field("ch0_neg_mode", &self.ch0_neg_mode())
+            .field("ch1_neg_mode", &self.ch1_neg_mode())
+            .field("ch0_pos_mode", &self.ch0_pos_mode())
+            .field("ch1_pos_mode", &self.ch1_pos_mode())
+            .field("ch0_hctrl_mode", &self.ch0_hctrl_mode())
+            .field("ch1_hctrl_mode", &self.ch1_hctrl_mode())
+            .field("ch0_lctrl_mode", &self.ch0_lctrl_mode())
+            .field("ch1_lctrl_mode", &self.ch1_lctrl_mode())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:9 - This sets the maximum threshold, in APB_CLK cycles, for the filter. Any pulses with width less than this will be ignored when the filter is enabled."]
+    #[inline(always)]
+    pub fn filter_thres(&mut self) -> FILTER_THRES_W<CONF0_SPEC> {
+        FILTER_THRES_W::new(self, 0)
+    }
+    #[doc = "Bit 10 - This is the enable bit for unit %s's input filter."]
+    #[inline(always)]
+    pub fn filter_en(&mut self) -> FILTER_EN_W<CONF0_SPEC> {
+        FILTER_EN_W::new(self, 10)
+    }
+    #[doc = "Bit 11 - This is the enable bit for unit %s's zero comparator."]
+    #[inline(always)]
+    pub fn thr_zero_en(&mut self) -> THR_ZERO_EN_W<CONF0_SPEC> {
+        THR_ZERO_EN_W::new(self, 11)
+    }
+    #[doc = "Bit 12 - This is the enable bit for unit %s's thr_h_lim comparator."]
+    #[inline(always)]
+    pub fn thr_h_lim_en(&mut self) -> THR_H_LIM_EN_W<CONF0_SPEC> {
+        THR_H_LIM_EN_W::new(self, 12)
+    }
+    #[doc = "Bit 13 - This is the enable bit for unit %s's thr_l_lim comparator."]
+    #[inline(always)]
+    pub fn thr_l_lim_en(&mut self) -> THR_L_LIM_EN_W<CONF0_SPEC> {
+        THR_L_LIM_EN_W::new(self, 13)
+    }
+    #[doc = "Bit 14 - This is the enable bit for unit %s's thres0 comparator."]
+    #[inline(always)]
+    pub fn thr_thres0_en(&mut self) -> THR_THRES0_EN_W<CONF0_SPEC> {
+        THR_THRES0_EN_W::new(self, 14)
+    }
+    #[doc = "Bit 15 - This is the enable bit for unit %s's thres1 comparator."]
+    #[inline(always)]
+    pub fn thr_thres1_en(&mut self) -> THR_THRES1_EN_W<CONF0_SPEC> {
+        THR_THRES1_EN_W::new(self, 15)
+    }
+    #[doc = "Configures the behavior when the signal input of channel (0-1) detects a negative edge."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_NEG_MODE` field.</div>"]
+    #[inline(always)]
+    pub fn ch_neg_mode(&mut self, n: u8) -> CH_NEG_MODE_W<CONF0_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 2][n as usize];
+        CH_NEG_MODE_W::new(self, n * 8 + 16)
+    }
+    #[doc = "Bits 16:17 - Configures the behavior when the signal input of channel 0 detects a negative edge."]
+    #[inline(always)]
+    pub fn ch0_neg_mode(&mut self) -> CH_NEG_MODE_W<CONF0_SPEC> {
+        CH_NEG_MODE_W::new(self, 16)
+    }
+    #[doc = "Bits 24:25 - Configures the behavior when the signal input of channel 1 detects a negative edge."]
+    #[inline(always)]
+    pub fn ch1_neg_mode(&mut self) -> CH_NEG_MODE_W<CONF0_SPEC> {
+        CH_NEG_MODE_W::new(self, 24)
+    }
+    #[doc = "Configures the behavior when the signal input of channel (0-1) detects a positive edge."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_POS_MODE` field.</div>"]
+    #[inline(always)]
+    pub fn ch_pos_mode(&mut self, n: u8) -> CH_POS_MODE_W<CONF0_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 2][n as usize];
+        CH_POS_MODE_W::new(self, n * 8 + 18)
+    }
+    #[doc = "Bits 18:19 - Configures the behavior when the signal input of channel 0 detects a positive edge."]
+    #[inline(always)]
+    pub fn ch0_pos_mode(&mut self) -> CH_POS_MODE_W<CONF0_SPEC> {
+        CH_POS_MODE_W::new(self, 18)
+    }
+    #[doc = "Bits 26:27 - Configures the behavior when the signal input of channel 1 detects a positive edge."]
+    #[inline(always)]
+    pub fn ch1_pos_mode(&mut self) -> CH_POS_MODE_W<CONF0_SPEC> {
+        CH_POS_MODE_W::new(self, 26)
+    }
+    #[doc = "Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the control signal is high."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_HCTRL_MODE` field.</div>"]
+    #[inline(always)]
+    pub fn ch_hctrl_mode(&mut self, n: u8) -> CH_HCTRL_MODE_W<CONF0_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 2][n as usize];
+        CH_HCTRL_MODE_W::new(self, n * 8 + 20)
+    }
+    #[doc = "Bits 20:21 - Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the control signal is high."]
+    #[inline(always)]
+    pub fn ch0_hctrl_mode(&mut self) -> CH_HCTRL_MODE_W<CONF0_SPEC> {
+        CH_HCTRL_MODE_W::new(self, 20)
+    }
+    #[doc = "Bits 28:29 - Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the control signal is high."]
+    #[inline(always)]
+    pub fn ch1_hctrl_mode(&mut self) -> CH_HCTRL_MODE_W<CONF0_SPEC> {
+        CH_HCTRL_MODE_W::new(self, 28)
+    }
+    #[doc = "Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the control signal is low."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_LCTRL_MODE` field.</div>"]
+    #[inline(always)]
+    pub fn ch_lctrl_mode(&mut self, n: u8) -> CH_LCTRL_MODE_W<CONF0_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 2][n as usize];
+        CH_LCTRL_MODE_W::new(self, n * 8 + 22)
+    }
+    #[doc = "Bits 22:23 - Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the control signal is low."]
+    #[inline(always)]
+    pub fn ch0_lctrl_mode(&mut self) -> CH_LCTRL_MODE_W<CONF0_SPEC> {
+        CH_LCTRL_MODE_W::new(self, 22)
+    }
+    #[doc = "Bits 30:31 - Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the control signal is low."]
+    #[inline(always)]
+    pub fn ch1_lctrl_mode(&mut self) -> CH_LCTRL_MODE_W<CONF0_SPEC> {
+        CH_LCTRL_MODE_W::new(self, 30)
+    }
+}
+#[doc = "Configuration register 0 for unit\n\nYou can [`read`](crate::Reg::read) this register and get [`conf0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`conf0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CONF0_SPEC;
+impl crate::RegisterSpec for CONF0_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`conf0::R`](R) reader structure"]
+impl crate::Readable for CONF0_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`conf0::W`](W) writer structure"]
+impl crate::Writable for CONF0_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CONF0 to value 0x3c10"]
+impl crate::Resettable for CONF0_SPEC {
+    const RESET_VALUE: u32 = 0x3c10;
+}

vendor/esp32s3/src/pcnt/unit/conf1.rs

@@ -0,0 +1,62 @@
+#[doc = "Register `CONF1` reader"]
+pub type R = crate::R<CONF1_SPEC>;
+#[doc = "Register `CONF1` writer"]
+pub type W = crate::W<CONF1_SPEC>;
+#[doc = "Field `CNT_THRES0` reader - This register is used to configure the thres0 value for unit %s."]
+pub type CNT_THRES0_R = crate::FieldReader<u16>;
+#[doc = "Field `CNT_THRES0` writer - This register is used to configure the thres0 value for unit %s."]
+pub type CNT_THRES0_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
+#[doc = "Field `CNT_THRES1` reader - This register is used to configure the thres1 value for unit %s."]
+pub type CNT_THRES1_R = crate::FieldReader<u16>;
+#[doc = "Field `CNT_THRES1` writer - This register is used to configure the thres1 value for unit %s."]
+pub type CNT_THRES1_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
+impl R {
+    #[doc = "Bits 0:15 - This register is used to configure the thres0 value for unit %s."]
+    #[inline(always)]
+    pub fn cnt_thres0(&self) -> CNT_THRES0_R {
+        CNT_THRES0_R::new((self.bits & 0xffff) as u16)
+    }
+    #[doc = "Bits 16:31 - This register is used to configure the thres1 value for unit %s."]
+    #[inline(always)]
+    pub fn cnt_thres1(&self) -> CNT_THRES1_R {
+        CNT_THRES1_R::new(((self.bits >> 16) & 0xffff) as u16)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CONF1")
+            .field("cnt_thres0", &self.cnt_thres0())
+            .field("cnt_thres1", &self.cnt_thres1())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:15 - This register is used to configure the thres0 value for unit %s."]
+    #[inline(always)]
+    pub fn cnt_thres0(&mut self) -> CNT_THRES0_W<CONF1_SPEC> {
+        CNT_THRES0_W::new(self, 0)
+    }
+    #[doc = "Bits 16:31 - This register is used to configure the thres1 value for unit %s."]
+    #[inline(always)]
+    pub fn cnt_thres1(&mut self) -> CNT_THRES1_W<CONF1_SPEC> {
+        CNT_THRES1_W::new(self, 16)
+    }
+}
+#[doc = "Configuration register 1 for unit 0\n\nYou can [`read`](crate::Reg::read) this register and get [`conf1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`conf1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CONF1_SPEC;
+impl crate::RegisterSpec for CONF1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`conf1::R`](R) reader structure"]
+impl crate::Readable for CONF1_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`conf1::W`](W) writer structure"]
+impl crate::Writable for CONF1_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CONF1 to value 0"]
+impl crate::Resettable for CONF1_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/pcnt/unit/conf2.rs

@@ -0,0 +1,62 @@
+#[doc = "Register `CONF2` reader"]
+pub type R = crate::R<CONF2_SPEC>;
+#[doc = "Register `CONF2` writer"]
+pub type W = crate::W<CONF2_SPEC>;
+#[doc = "Field `CNT_H_LIM` reader - This register is used to configure the thr_h_lim value for unit %s."]
+pub type CNT_H_LIM_R = crate::FieldReader<u16>;
+#[doc = "Field `CNT_H_LIM` writer - This register is used to configure the thr_h_lim value for unit %s."]
+pub type CNT_H_LIM_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
+#[doc = "Field `CNT_L_LIM` reader - This register is used to configure the thr_l_lim value for unit %s."]
+pub type CNT_L_LIM_R = crate::FieldReader<u16>;
+#[doc = "Field `CNT_L_LIM` writer - This register is used to configure the thr_l_lim value for unit %s."]
+pub type CNT_L_LIM_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
+impl R {
+    #[doc = "Bits 0:15 - This register is used to configure the thr_h_lim value for unit %s."]
+    #[inline(always)]
+    pub fn cnt_h_lim(&self) -> CNT_H_LIM_R {
+        CNT_H_LIM_R::new((self.bits & 0xffff) as u16)
+    }
+    #[doc = "Bits 16:31 - This register is used to configure the thr_l_lim value for unit %s."]
+    #[inline(always)]
+    pub fn cnt_l_lim(&self) -> CNT_L_LIM_R {
+        CNT_L_LIM_R::new(((self.bits >> 16) & 0xffff) as u16)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CONF2")
+            .field("cnt_h_lim", &self.cnt_h_lim())
+            .field("cnt_l_lim", &self.cnt_l_lim())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:15 - This register is used to configure the thr_h_lim value for unit %s."]
+    #[inline(always)]
+    pub fn cnt_h_lim(&mut self) -> CNT_H_LIM_W<CONF2_SPEC> {
+        CNT_H_LIM_W::new(self, 0)
+    }
+    #[doc = "Bits 16:31 - This register is used to configure the thr_l_lim value for unit %s."]
+    #[inline(always)]
+    pub fn cnt_l_lim(&mut self) -> CNT_L_LIM_W<CONF2_SPEC> {
+        CNT_L_LIM_W::new(self, 16)
+    }
+}
+#[doc = "Configuration register 2 for unit 0\n\nYou can [`read`](crate::Reg::read) this register and get [`conf2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`conf2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CONF2_SPEC;
+impl crate::RegisterSpec for CONF2_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`conf2::R`](R) reader structure"]
+impl crate::Readable for CONF2_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`conf2::W`](W) writer structure"]
+impl crate::Writable for CONF2_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CONF2 to value 0"]
+impl crate::Resettable for CONF2_SPEC {
+    const RESET_VALUE: u32 = 0;
+}