feat: add display UI with splash screen, dashboard, and RSSI sparkline

Implement full SSD1306 OLED display support:
- Splash screen on boot (1.5s) with project name, version, board
- Dashboard showing radio state, config, counters, RSSI/SNR
- RSSI history sparkline (64-sample ring buffer, 2px-wide bars)
- DisplayOn/DisplayOff host commands routed via dedicated channel
- Pure render functions against generic DrawTarget (no hardware coupling)
- Display on/off control bypasses radio task entirely

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>

vendor/esp32s3/src/rtc_cntl/ana_conf.rs

@@ -0,0 +1,212 @@
+#[doc = "Register `ANA_CONF` reader"]
+pub type R = crate::R<ANA_CONF_SPEC>;
+#[doc = "Register `ANA_CONF` writer"]
+pub type W = crate::W<ANA_CONF_SPEC>;
+#[doc = "Field `I2C_RESET_POR_FORCE_PD` reader - force down I2C_RESET_POR"]
+pub type I2C_RESET_POR_FORCE_PD_R = crate::BitReader;
+#[doc = "Field `I2C_RESET_POR_FORCE_PD` writer - force down I2C_RESET_POR"]
+pub type I2C_RESET_POR_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `I2C_RESET_POR_FORCE_PU` reader - force on I2C_RESET_POR"]
+pub type I2C_RESET_POR_FORCE_PU_R = crate::BitReader;
+#[doc = "Field `I2C_RESET_POR_FORCE_PU` writer - force on I2C_RESET_POR"]
+pub type I2C_RESET_POR_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `GLITCH_RST_EN` reader - enable clk glitch"]
+pub type GLITCH_RST_EN_R = crate::BitReader;
+#[doc = "Field `GLITCH_RST_EN` writer - enable clk glitch"]
+pub type GLITCH_RST_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_I2C_PU` reader - PLLA force power up"]
+pub type SAR_I2C_PU_R = crate::BitReader;
+#[doc = "Field `SAR_I2C_PU` writer - PLLA force power up"]
+pub type SAR_I2C_PU_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ANALOG_TOP_ISO_SLEEP` reader - PLLA force power down"]
+pub type ANALOG_TOP_ISO_SLEEP_R = crate::BitReader;
+#[doc = "Field `ANALOG_TOP_ISO_SLEEP` writer - PLLA force power down"]
+pub type ANALOG_TOP_ISO_SLEEP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ANALOG_TOP_ISO_MONITOR` reader - PLLA force power up"]
+pub type ANALOG_TOP_ISO_MONITOR_R = crate::BitReader;
+#[doc = "Field `ANALOG_TOP_ISO_MONITOR` writer - PLLA force power up"]
+pub type ANALOG_TOP_ISO_MONITOR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `BBPLL_CAL_SLP_START` reader - start BBPLL calibration during sleep"]
+pub type BBPLL_CAL_SLP_START_R = crate::BitReader;
+#[doc = "Field `BBPLL_CAL_SLP_START` writer - start BBPLL calibration during sleep"]
+pub type BBPLL_CAL_SLP_START_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PVTMON_PU` reader - 1: PVTMON power up, otherwise power down"]
+pub type PVTMON_PU_R = crate::BitReader;
+#[doc = "Field `PVTMON_PU` writer - 1: PVTMON power up, otherwise power down"]
+pub type PVTMON_PU_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TXRF_I2C_PU` reader - 1: TXRF_I2C power up, otherwise power down"]
+pub type TXRF_I2C_PU_R = crate::BitReader;
+#[doc = "Field `TXRF_I2C_PU` writer - 1: TXRF_I2C power up, otherwise power down"]
+pub type TXRF_I2C_PU_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RFRX_PBUS_PU` reader - 1: RFRX_PBUS power up, otherwise power down"]
+pub type RFRX_PBUS_PU_R = crate::BitReader;
+#[doc = "Field `RFRX_PBUS_PU` writer - 1: RFRX_PBUS power up, otherwise power down"]
+pub type RFRX_PBUS_PU_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CKGEN_I2C_PU` reader - 1: CKGEN_I2C power up, otherwise power down"]
+pub type CKGEN_I2C_PU_R = crate::BitReader;
+#[doc = "Field `CKGEN_I2C_PU` writer - 1: CKGEN_I2C power up, otherwise power down"]
+pub type CKGEN_I2C_PU_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PLL_I2C_PU` reader - power on pll i2c"]
+pub type PLL_I2C_PU_R = crate::BitReader;
+#[doc = "Field `PLL_I2C_PU` writer - power on pll i2c"]
+pub type PLL_I2C_PU_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 18 - force down I2C_RESET_POR"]
+    #[inline(always)]
+    pub fn i2c_reset_por_force_pd(&self) -> I2C_RESET_POR_FORCE_PD_R {
+        I2C_RESET_POR_FORCE_PD_R::new(((self.bits >> 18) & 1) != 0)
+    }
+    #[doc = "Bit 19 - force on I2C_RESET_POR"]
+    #[inline(always)]
+    pub fn i2c_reset_por_force_pu(&self) -> I2C_RESET_POR_FORCE_PU_R {
+        I2C_RESET_POR_FORCE_PU_R::new(((self.bits >> 19) & 1) != 0)
+    }
+    #[doc = "Bit 20 - enable clk glitch"]
+    #[inline(always)]
+    pub fn glitch_rst_en(&self) -> GLITCH_RST_EN_R {
+        GLITCH_RST_EN_R::new(((self.bits >> 20) & 1) != 0)
+    }
+    #[doc = "Bit 22 - PLLA force power up"]
+    #[inline(always)]
+    pub fn sar_i2c_pu(&self) -> SAR_I2C_PU_R {
+        SAR_I2C_PU_R::new(((self.bits >> 22) & 1) != 0)
+    }
+    #[doc = "Bit 23 - PLLA force power down"]
+    #[inline(always)]
+    pub fn analog_top_iso_sleep(&self) -> ANALOG_TOP_ISO_SLEEP_R {
+        ANALOG_TOP_ISO_SLEEP_R::new(((self.bits >> 23) & 1) != 0)
+    }
+    #[doc = "Bit 24 - PLLA force power up"]
+    #[inline(always)]
+    pub fn analog_top_iso_monitor(&self) -> ANALOG_TOP_ISO_MONITOR_R {
+        ANALOG_TOP_ISO_MONITOR_R::new(((self.bits >> 24) & 1) != 0)
+    }
+    #[doc = "Bit 25 - start BBPLL calibration during sleep"]
+    #[inline(always)]
+    pub fn bbpll_cal_slp_start(&self) -> BBPLL_CAL_SLP_START_R {
+        BBPLL_CAL_SLP_START_R::new(((self.bits >> 25) & 1) != 0)
+    }
+    #[doc = "Bit 26 - 1: PVTMON power up, otherwise power down"]
+    #[inline(always)]
+    pub fn pvtmon_pu(&self) -> PVTMON_PU_R {
+        PVTMON_PU_R::new(((self.bits >> 26) & 1) != 0)
+    }
+    #[doc = "Bit 27 - 1: TXRF_I2C power up, otherwise power down"]
+    #[inline(always)]
+    pub fn txrf_i2c_pu(&self) -> TXRF_I2C_PU_R {
+        TXRF_I2C_PU_R::new(((self.bits >> 27) & 1) != 0)
+    }
+    #[doc = "Bit 28 - 1: RFRX_PBUS power up, otherwise power down"]
+    #[inline(always)]
+    pub fn rfrx_pbus_pu(&self) -> RFRX_PBUS_PU_R {
+        RFRX_PBUS_PU_R::new(((self.bits >> 28) & 1) != 0)
+    }
+    #[doc = "Bit 30 - 1: CKGEN_I2C power up, otherwise power down"]
+    #[inline(always)]
+    pub fn ckgen_i2c_pu(&self) -> CKGEN_I2C_PU_R {
+        CKGEN_I2C_PU_R::new(((self.bits >> 30) & 1) != 0)
+    }
+    #[doc = "Bit 31 - power on pll i2c"]
+    #[inline(always)]
+    pub fn pll_i2c_pu(&self) -> PLL_I2C_PU_R {
+        PLL_I2C_PU_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("ANA_CONF")
+            .field("i2c_reset_por_force_pd", &self.i2c_reset_por_force_pd())
+            .field("i2c_reset_por_force_pu", &self.i2c_reset_por_force_pu())
+            .field("glitch_rst_en", &self.glitch_rst_en())
+            .field("sar_i2c_pu", &self.sar_i2c_pu())
+            .field("analog_top_iso_sleep", &self.analog_top_iso_sleep())
+            .field("analog_top_iso_monitor", &self.analog_top_iso_monitor())
+            .field("bbpll_cal_slp_start", &self.bbpll_cal_slp_start())
+            .field("pvtmon_pu", &self.pvtmon_pu())
+            .field("txrf_i2c_pu", &self.txrf_i2c_pu())
+            .field("rfrx_pbus_pu", &self.rfrx_pbus_pu())
+            .field("ckgen_i2c_pu", &self.ckgen_i2c_pu())
+            .field("pll_i2c_pu", &self.pll_i2c_pu())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 18 - force down I2C_RESET_POR"]
+    #[inline(always)]
+    pub fn i2c_reset_por_force_pd(&mut self) -> I2C_RESET_POR_FORCE_PD_W<ANA_CONF_SPEC> {
+        I2C_RESET_POR_FORCE_PD_W::new(self, 18)
+    }
+    #[doc = "Bit 19 - force on I2C_RESET_POR"]
+    #[inline(always)]
+    pub fn i2c_reset_por_force_pu(&mut self) -> I2C_RESET_POR_FORCE_PU_W<ANA_CONF_SPEC> {
+        I2C_RESET_POR_FORCE_PU_W::new(self, 19)
+    }
+    #[doc = "Bit 20 - enable clk glitch"]
+    #[inline(always)]
+    pub fn glitch_rst_en(&mut self) -> GLITCH_RST_EN_W<ANA_CONF_SPEC> {
+        GLITCH_RST_EN_W::new(self, 20)
+    }
+    #[doc = "Bit 22 - PLLA force power up"]
+    #[inline(always)]
+    pub fn sar_i2c_pu(&mut self) -> SAR_I2C_PU_W<ANA_CONF_SPEC> {
+        SAR_I2C_PU_W::new(self, 22)
+    }
+    #[doc = "Bit 23 - PLLA force power down"]
+    #[inline(always)]
+    pub fn analog_top_iso_sleep(&mut self) -> ANALOG_TOP_ISO_SLEEP_W<ANA_CONF_SPEC> {
+        ANALOG_TOP_ISO_SLEEP_W::new(self, 23)
+    }
+    #[doc = "Bit 24 - PLLA force power up"]
+    #[inline(always)]
+    pub fn analog_top_iso_monitor(&mut self) -> ANALOG_TOP_ISO_MONITOR_W<ANA_CONF_SPEC> {
+        ANALOG_TOP_ISO_MONITOR_W::new(self, 24)
+    }
+    #[doc = "Bit 25 - start BBPLL calibration during sleep"]
+    #[inline(always)]
+    pub fn bbpll_cal_slp_start(&mut self) -> BBPLL_CAL_SLP_START_W<ANA_CONF_SPEC> {
+        BBPLL_CAL_SLP_START_W::new(self, 25)
+    }
+    #[doc = "Bit 26 - 1: PVTMON power up, otherwise power down"]
+    #[inline(always)]
+    pub fn pvtmon_pu(&mut self) -> PVTMON_PU_W<ANA_CONF_SPEC> {
+        PVTMON_PU_W::new(self, 26)
+    }
+    #[doc = "Bit 27 - 1: TXRF_I2C power up, otherwise power down"]
+    #[inline(always)]
+    pub fn txrf_i2c_pu(&mut self) -> TXRF_I2C_PU_W<ANA_CONF_SPEC> {
+        TXRF_I2C_PU_W::new(self, 27)
+    }
+    #[doc = "Bit 28 - 1: RFRX_PBUS power up, otherwise power down"]
+    #[inline(always)]
+    pub fn rfrx_pbus_pu(&mut self) -> RFRX_PBUS_PU_W<ANA_CONF_SPEC> {
+        RFRX_PBUS_PU_W::new(self, 28)
+    }
+    #[doc = "Bit 30 - 1: CKGEN_I2C power up, otherwise power down"]
+    #[inline(always)]
+    pub fn ckgen_i2c_pu(&mut self) -> CKGEN_I2C_PU_W<ANA_CONF_SPEC> {
+        CKGEN_I2C_PU_W::new(self, 30)
+    }
+    #[doc = "Bit 31 - power on pll i2c"]
+    #[inline(always)]
+    pub fn pll_i2c_pu(&mut self) -> PLL_I2C_PU_W<ANA_CONF_SPEC> {
+        PLL_I2C_PU_W::new(self, 31)
+    }
+}
+#[doc = "analog configure register\n\nYou can [`read`](crate::Reg::read) this register and get [`ana_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ana_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ANA_CONF_SPEC;
+impl crate::RegisterSpec for ANA_CONF_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`ana_conf::R`](R) reader structure"]
+impl crate::Readable for ANA_CONF_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`ana_conf::W`](W) writer structure"]
+impl crate::Writable for ANA_CONF_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets ANA_CONF to value 0x0044_0000"]
+impl crate::Resettable for ANA_CONF_SPEC {
+    const RESET_VALUE: u32 = 0x0044_0000;
+}

vendor/esp32s3/src/rtc_cntl/bias_conf.rs

@@ -0,0 +1,197 @@
+#[doc = "Register `BIAS_CONF` reader"]
+pub type R = crate::R<BIAS_CONF_SPEC>;
+#[doc = "Register `BIAS_CONF` writer"]
+pub type W = crate::W<BIAS_CONF_SPEC>;
+#[doc = "Field `BIAS_BUF_IDLE` reader - No public"]
+pub type BIAS_BUF_IDLE_R = crate::BitReader;
+#[doc = "Field `BIAS_BUF_IDLE` writer - No public"]
+pub type BIAS_BUF_IDLE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `BIAS_BUF_WAKE` reader - No public"]
+pub type BIAS_BUF_WAKE_R = crate::BitReader;
+#[doc = "Field `BIAS_BUF_WAKE` writer - No public"]
+pub type BIAS_BUF_WAKE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `BIAS_BUF_DEEP_SLP` reader - No public"]
+pub type BIAS_BUF_DEEP_SLP_R = crate::BitReader;
+#[doc = "Field `BIAS_BUF_DEEP_SLP` writer - No public"]
+pub type BIAS_BUF_DEEP_SLP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `BIAS_BUF_MONITOR` reader - No public"]
+pub type BIAS_BUF_MONITOR_R = crate::BitReader;
+#[doc = "Field `BIAS_BUF_MONITOR` writer - No public"]
+pub type BIAS_BUF_MONITOR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PD_CUR_DEEP_SLP` reader - xpd cur when rtc in sleep_state"]
+pub type PD_CUR_DEEP_SLP_R = crate::BitReader;
+#[doc = "Field `PD_CUR_DEEP_SLP` writer - xpd cur when rtc in sleep_state"]
+pub type PD_CUR_DEEP_SLP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PD_CUR_MONITOR` reader - xpd cur when rtc in monitor state"]
+pub type PD_CUR_MONITOR_R = crate::BitReader;
+#[doc = "Field `PD_CUR_MONITOR` writer - xpd cur when rtc in monitor state"]
+pub type PD_CUR_MONITOR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `BIAS_SLEEP_DEEP_SLP` reader - bias_sleep when rtc in sleep_state"]
+pub type BIAS_SLEEP_DEEP_SLP_R = crate::BitReader;
+#[doc = "Field `BIAS_SLEEP_DEEP_SLP` writer - bias_sleep when rtc in sleep_state"]
+pub type BIAS_SLEEP_DEEP_SLP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `BIAS_SLEEP_MONITOR` reader - bias_sleep when rtc in monitor state"]
+pub type BIAS_SLEEP_MONITOR_R = crate::BitReader;
+#[doc = "Field `BIAS_SLEEP_MONITOR` writer - bias_sleep when rtc in monitor state"]
+pub type BIAS_SLEEP_MONITOR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DBG_ATTEN_DEEP_SLP` reader - DBG_ATTEN when rtc in sleep state"]
+pub type DBG_ATTEN_DEEP_SLP_R = crate::FieldReader;
+#[doc = "Field `DBG_ATTEN_DEEP_SLP` writer - DBG_ATTEN when rtc in sleep state"]
+pub type DBG_ATTEN_DEEP_SLP_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `DBG_ATTEN_MONITOR` reader - DBG_ATTEN when rtc in monitor state"]
+pub type DBG_ATTEN_MONITOR_R = crate::FieldReader;
+#[doc = "Field `DBG_ATTEN_MONITOR` writer - DBG_ATTEN when rtc in monitor state"]
+pub type DBG_ATTEN_MONITOR_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `DBG_ATTEN_WAKEUP` reader - No public"]
+pub type DBG_ATTEN_WAKEUP_R = crate::FieldReader;
+#[doc = "Field `DBG_ATTEN_WAKEUP` writer - No public"]
+pub type DBG_ATTEN_WAKEUP_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+impl R {
+    #[doc = "Bit 10 - No public"]
+    #[inline(always)]
+    pub fn bias_buf_idle(&self) -> BIAS_BUF_IDLE_R {
+        BIAS_BUF_IDLE_R::new(((self.bits >> 10) & 1) != 0)
+    }
+    #[doc = "Bit 11 - No public"]
+    #[inline(always)]
+    pub fn bias_buf_wake(&self) -> BIAS_BUF_WAKE_R {
+        BIAS_BUF_WAKE_R::new(((self.bits >> 11) & 1) != 0)
+    }
+    #[doc = "Bit 12 - No public"]
+    #[inline(always)]
+    pub fn bias_buf_deep_slp(&self) -> BIAS_BUF_DEEP_SLP_R {
+        BIAS_BUF_DEEP_SLP_R::new(((self.bits >> 12) & 1) != 0)
+    }
+    #[doc = "Bit 13 - No public"]
+    #[inline(always)]
+    pub fn bias_buf_monitor(&self) -> BIAS_BUF_MONITOR_R {
+        BIAS_BUF_MONITOR_R::new(((self.bits >> 13) & 1) != 0)
+    }
+    #[doc = "Bit 14 - xpd cur when rtc in sleep_state"]
+    #[inline(always)]
+    pub fn pd_cur_deep_slp(&self) -> PD_CUR_DEEP_SLP_R {
+        PD_CUR_DEEP_SLP_R::new(((self.bits >> 14) & 1) != 0)
+    }
+    #[doc = "Bit 15 - xpd cur when rtc in monitor state"]
+    #[inline(always)]
+    pub fn pd_cur_monitor(&self) -> PD_CUR_MONITOR_R {
+        PD_CUR_MONITOR_R::new(((self.bits >> 15) & 1) != 0)
+    }
+    #[doc = "Bit 16 - bias_sleep when rtc in sleep_state"]
+    #[inline(always)]
+    pub fn bias_sleep_deep_slp(&self) -> BIAS_SLEEP_DEEP_SLP_R {
+        BIAS_SLEEP_DEEP_SLP_R::new(((self.bits >> 16) & 1) != 0)
+    }
+    #[doc = "Bit 17 - bias_sleep when rtc in monitor state"]
+    #[inline(always)]
+    pub fn bias_sleep_monitor(&self) -> BIAS_SLEEP_MONITOR_R {
+        BIAS_SLEEP_MONITOR_R::new(((self.bits >> 17) & 1) != 0)
+    }
+    #[doc = "Bits 18:21 - DBG_ATTEN when rtc in sleep state"]
+    #[inline(always)]
+    pub fn dbg_atten_deep_slp(&self) -> DBG_ATTEN_DEEP_SLP_R {
+        DBG_ATTEN_DEEP_SLP_R::new(((self.bits >> 18) & 0x0f) as u8)
+    }
+    #[doc = "Bits 22:25 - DBG_ATTEN when rtc in monitor state"]
+    #[inline(always)]
+    pub fn dbg_atten_monitor(&self) -> DBG_ATTEN_MONITOR_R {
+        DBG_ATTEN_MONITOR_R::new(((self.bits >> 22) & 0x0f) as u8)
+    }
+    #[doc = "Bits 26:29 - No public"]
+    #[inline(always)]
+    pub fn dbg_atten_wakeup(&self) -> DBG_ATTEN_WAKEUP_R {
+        DBG_ATTEN_WAKEUP_R::new(((self.bits >> 26) & 0x0f) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("BIAS_CONF")
+            .field("bias_buf_idle", &self.bias_buf_idle())
+            .field("bias_buf_wake", &self.bias_buf_wake())
+            .field("bias_buf_deep_slp", &self.bias_buf_deep_slp())
+            .field("bias_buf_monitor", &self.bias_buf_monitor())
+            .field("pd_cur_deep_slp", &self.pd_cur_deep_slp())
+            .field("pd_cur_monitor", &self.pd_cur_monitor())
+            .field("bias_sleep_deep_slp", &self.bias_sleep_deep_slp())
+            .field("bias_sleep_monitor", &self.bias_sleep_monitor())
+            .field("dbg_atten_deep_slp", &self.dbg_atten_deep_slp())
+            .field("dbg_atten_monitor", &self.dbg_atten_monitor())
+            .field("dbg_atten_wakeup", &self.dbg_atten_wakeup())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 10 - No public"]
+    #[inline(always)]
+    pub fn bias_buf_idle(&mut self) -> BIAS_BUF_IDLE_W<BIAS_CONF_SPEC> {
+        BIAS_BUF_IDLE_W::new(self, 10)
+    }
+    #[doc = "Bit 11 - No public"]
+    #[inline(always)]
+    pub fn bias_buf_wake(&mut self) -> BIAS_BUF_WAKE_W<BIAS_CONF_SPEC> {
+        BIAS_BUF_WAKE_W::new(self, 11)
+    }
+    #[doc = "Bit 12 - No public"]
+    #[inline(always)]
+    pub fn bias_buf_deep_slp(&mut self) -> BIAS_BUF_DEEP_SLP_W<BIAS_CONF_SPEC> {
+        BIAS_BUF_DEEP_SLP_W::new(self, 12)
+    }
+    #[doc = "Bit 13 - No public"]
+    #[inline(always)]
+    pub fn bias_buf_monitor(&mut self) -> BIAS_BUF_MONITOR_W<BIAS_CONF_SPEC> {
+        BIAS_BUF_MONITOR_W::new(self, 13)
+    }
+    #[doc = "Bit 14 - xpd cur when rtc in sleep_state"]
+    #[inline(always)]
+    pub fn pd_cur_deep_slp(&mut self) -> PD_CUR_DEEP_SLP_W<BIAS_CONF_SPEC> {
+        PD_CUR_DEEP_SLP_W::new(self, 14)
+    }
+    #[doc = "Bit 15 - xpd cur when rtc in monitor state"]
+    #[inline(always)]
+    pub fn pd_cur_monitor(&mut self) -> PD_CUR_MONITOR_W<BIAS_CONF_SPEC> {
+        PD_CUR_MONITOR_W::new(self, 15)
+    }
+    #[doc = "Bit 16 - bias_sleep when rtc in sleep_state"]
+    #[inline(always)]
+    pub fn bias_sleep_deep_slp(&mut self) -> BIAS_SLEEP_DEEP_SLP_W<BIAS_CONF_SPEC> {
+        BIAS_SLEEP_DEEP_SLP_W::new(self, 16)
+    }
+    #[doc = "Bit 17 - bias_sleep when rtc in monitor state"]
+    #[inline(always)]
+    pub fn bias_sleep_monitor(&mut self) -> BIAS_SLEEP_MONITOR_W<BIAS_CONF_SPEC> {
+        BIAS_SLEEP_MONITOR_W::new(self, 17)
+    }
+    #[doc = "Bits 18:21 - DBG_ATTEN when rtc in sleep state"]
+    #[inline(always)]
+    pub fn dbg_atten_deep_slp(&mut self) -> DBG_ATTEN_DEEP_SLP_W<BIAS_CONF_SPEC> {
+        DBG_ATTEN_DEEP_SLP_W::new(self, 18)
+    }
+    #[doc = "Bits 22:25 - DBG_ATTEN when rtc in monitor state"]
+    #[inline(always)]
+    pub fn dbg_atten_monitor(&mut self) -> DBG_ATTEN_MONITOR_W<BIAS_CONF_SPEC> {
+        DBG_ATTEN_MONITOR_W::new(self, 22)
+    }
+    #[doc = "Bits 26:29 - No public"]
+    #[inline(always)]
+    pub fn dbg_atten_wakeup(&mut self) -> DBG_ATTEN_WAKEUP_W<BIAS_CONF_SPEC> {
+        DBG_ATTEN_WAKEUP_W::new(self, 26)
+    }
+}
+#[doc = "No public\n\nYou can [`read`](crate::Reg::read) this register and get [`bias_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bias_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct BIAS_CONF_SPEC;
+impl crate::RegisterSpec for BIAS_CONF_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`bias_conf::R`](R) reader structure"]
+impl crate::Readable for BIAS_CONF_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`bias_conf::W`](W) writer structure"]
+impl crate::Writable for BIAS_CONF_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets BIAS_CONF to value 0x0001_0800"]
+impl crate::Resettable for BIAS_CONF_SPEC {
+    const RESET_VALUE: u32 = 0x0001_0800;
+}

vendor/esp32s3/src/rtc_cntl/brown_out.rs

@@ -0,0 +1,170 @@
+#[doc = "Register `BROWN_OUT` reader"]
+pub type R = crate::R<BROWN_OUT_SPEC>;
+#[doc = "Register `BROWN_OUT` writer"]
+pub type W = crate::W<BROWN_OUT_SPEC>;
+#[doc = "Field `BROWN_OUT_INT_WAIT` reader - brown out interrupt wait cycles"]
+pub type BROWN_OUT_INT_WAIT_R = crate::FieldReader<u16>;
+#[doc = "Field `BROWN_OUT_INT_WAIT` writer - brown out interrupt wait cycles"]
+pub type BROWN_OUT_INT_WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
+#[doc = "Field `BROWN_OUT_CLOSE_FLASH_ENA` reader - enable close flash when brown out happens"]
+pub type BROWN_OUT_CLOSE_FLASH_ENA_R = crate::BitReader;
+#[doc = "Field `BROWN_OUT_CLOSE_FLASH_ENA` writer - enable close flash when brown out happens"]
+pub type BROWN_OUT_CLOSE_FLASH_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `BROWN_OUT_PD_RF_ENA` reader - enable power down RF when brown out happens"]
+pub type BROWN_OUT_PD_RF_ENA_R = crate::BitReader;
+#[doc = "Field `BROWN_OUT_PD_RF_ENA` writer - enable power down RF when brown out happens"]
+pub type BROWN_OUT_PD_RF_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `BROWN_OUT_RST_WAIT` reader - brown out reset wait cycles"]
+pub type BROWN_OUT_RST_WAIT_R = crate::FieldReader<u16>;
+#[doc = "Field `BROWN_OUT_RST_WAIT` writer - brown out reset wait cycles"]
+pub type BROWN_OUT_RST_WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
+#[doc = "Field `BROWN_OUT_RST_ENA` reader - enable brown out reset"]
+pub type BROWN_OUT_RST_ENA_R = crate::BitReader;
+#[doc = "Field `BROWN_OUT_RST_ENA` writer - enable brown out reset"]
+pub type BROWN_OUT_RST_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `BROWN_OUT_RST_SEL` reader - 1: 4-pos reset, 0: sys_reset"]
+pub type BROWN_OUT_RST_SEL_R = crate::BitReader;
+#[doc = "Field `BROWN_OUT_RST_SEL` writer - 1: 4-pos reset, 0: sys_reset"]
+pub type BROWN_OUT_RST_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `BROWN_OUT_ANA_RST_EN` reader - enable brown out reset en"]
+pub type BROWN_OUT_ANA_RST_EN_R = crate::BitReader;
+#[doc = "Field `BROWN_OUT_ANA_RST_EN` writer - enable brown out reset en"]
+pub type BROWN_OUT_ANA_RST_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `BROWN_OUT_CNT_CLR` writer - clear brown out counter"]
+pub type BROWN_OUT_CNT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `BROWN_OUT_ENA` reader - enable brown out"]
+pub type BROWN_OUT_ENA_R = crate::BitReader;
+#[doc = "Field `BROWN_OUT_ENA` writer - enable brown out"]
+pub type BROWN_OUT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DET` reader - get brown out detect"]
+pub type DET_R = crate::BitReader;
+impl R {
+    #[doc = "Bits 4:13 - brown out interrupt wait cycles"]
+    #[inline(always)]
+    pub fn brown_out_int_wait(&self) -> BROWN_OUT_INT_WAIT_R {
+        BROWN_OUT_INT_WAIT_R::new(((self.bits >> 4) & 0x03ff) as u16)
+    }
+    #[doc = "Bit 14 - enable close flash when brown out happens"]
+    #[inline(always)]
+    pub fn brown_out_close_flash_ena(&self) -> BROWN_OUT_CLOSE_FLASH_ENA_R {
+        BROWN_OUT_CLOSE_FLASH_ENA_R::new(((self.bits >> 14) & 1) != 0)
+    }
+    #[doc = "Bit 15 - enable power down RF when brown out happens"]
+    #[inline(always)]
+    pub fn brown_out_pd_rf_ena(&self) -> BROWN_OUT_PD_RF_ENA_R {
+        BROWN_OUT_PD_RF_ENA_R::new(((self.bits >> 15) & 1) != 0)
+    }
+    #[doc = "Bits 16:25 - brown out reset wait cycles"]
+    #[inline(always)]
+    pub fn brown_out_rst_wait(&self) -> BROWN_OUT_RST_WAIT_R {
+        BROWN_OUT_RST_WAIT_R::new(((self.bits >> 16) & 0x03ff) as u16)
+    }
+    #[doc = "Bit 26 - enable brown out reset"]
+    #[inline(always)]
+    pub fn brown_out_rst_ena(&self) -> BROWN_OUT_RST_ENA_R {
+        BROWN_OUT_RST_ENA_R::new(((self.bits >> 26) & 1) != 0)
+    }
+    #[doc = "Bit 27 - 1: 4-pos reset, 0: sys_reset"]
+    #[inline(always)]
+    pub fn brown_out_rst_sel(&self) -> BROWN_OUT_RST_SEL_R {
+        BROWN_OUT_RST_SEL_R::new(((self.bits >> 27) & 1) != 0)
+    }
+    #[doc = "Bit 28 - enable brown out reset en"]
+    #[inline(always)]
+    pub fn brown_out_ana_rst_en(&self) -> BROWN_OUT_ANA_RST_EN_R {
+        BROWN_OUT_ANA_RST_EN_R::new(((self.bits >> 28) & 1) != 0)
+    }
+    #[doc = "Bit 30 - enable brown out"]
+    #[inline(always)]
+    pub fn brown_out_ena(&self) -> BROWN_OUT_ENA_R {
+        BROWN_OUT_ENA_R::new(((self.bits >> 30) & 1) != 0)
+    }
+    #[doc = "Bit 31 - get brown out detect"]
+    #[inline(always)]
+    pub fn det(&self) -> DET_R {
+        DET_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("BROWN_OUT")
+            .field("brown_out_int_wait", &self.brown_out_int_wait())
+            .field(
+                "brown_out_close_flash_ena",
+                &self.brown_out_close_flash_ena(),
+            )
+            .field("brown_out_pd_rf_ena", &self.brown_out_pd_rf_ena())
+            .field("brown_out_rst_wait", &self.brown_out_rst_wait())
+            .field("brown_out_rst_ena", &self.brown_out_rst_ena())
+            .field("brown_out_rst_sel", &self.brown_out_rst_sel())
+            .field("brown_out_ana_rst_en", &self.brown_out_ana_rst_en())
+            .field("brown_out_ena", &self.brown_out_ena())
+            .field("det", &self.det())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 4:13 - brown out interrupt wait cycles"]
+    #[inline(always)]
+    pub fn brown_out_int_wait(&mut self) -> BROWN_OUT_INT_WAIT_W<BROWN_OUT_SPEC> {
+        BROWN_OUT_INT_WAIT_W::new(self, 4)
+    }
+    #[doc = "Bit 14 - enable close flash when brown out happens"]
+    #[inline(always)]
+    pub fn brown_out_close_flash_ena(&mut self) -> BROWN_OUT_CLOSE_FLASH_ENA_W<BROWN_OUT_SPEC> {
+        BROWN_OUT_CLOSE_FLASH_ENA_W::new(self, 14)
+    }
+    #[doc = "Bit 15 - enable power down RF when brown out happens"]
+    #[inline(always)]
+    pub fn brown_out_pd_rf_ena(&mut self) -> BROWN_OUT_PD_RF_ENA_W<BROWN_OUT_SPEC> {
+        BROWN_OUT_PD_RF_ENA_W::new(self, 15)
+    }
+    #[doc = "Bits 16:25 - brown out reset wait cycles"]
+    #[inline(always)]
+    pub fn brown_out_rst_wait(&mut self) -> BROWN_OUT_RST_WAIT_W<BROWN_OUT_SPEC> {
+        BROWN_OUT_RST_WAIT_W::new(self, 16)
+    }
+    #[doc = "Bit 26 - enable brown out reset"]
+    #[inline(always)]
+    pub fn brown_out_rst_ena(&mut self) -> BROWN_OUT_RST_ENA_W<BROWN_OUT_SPEC> {
+        BROWN_OUT_RST_ENA_W::new(self, 26)
+    }
+    #[doc = "Bit 27 - 1: 4-pos reset, 0: sys_reset"]
+    #[inline(always)]
+    pub fn brown_out_rst_sel(&mut self) -> BROWN_OUT_RST_SEL_W<BROWN_OUT_SPEC> {
+        BROWN_OUT_RST_SEL_W::new(self, 27)
+    }
+    #[doc = "Bit 28 - enable brown out reset en"]
+    #[inline(always)]
+    pub fn brown_out_ana_rst_en(&mut self) -> BROWN_OUT_ANA_RST_EN_W<BROWN_OUT_SPEC> {
+        BROWN_OUT_ANA_RST_EN_W::new(self, 28)
+    }
+    #[doc = "Bit 29 - clear brown out counter"]
+    #[inline(always)]
+    pub fn brown_out_cnt_clr(&mut self) -> BROWN_OUT_CNT_CLR_W<BROWN_OUT_SPEC> {
+        BROWN_OUT_CNT_CLR_W::new(self, 29)
+    }
+    #[doc = "Bit 30 - enable brown out"]
+    #[inline(always)]
+    pub fn brown_out_ena(&mut self) -> BROWN_OUT_ENA_W<BROWN_OUT_SPEC> {
+        BROWN_OUT_ENA_W::new(self, 30)
+    }
+}
+#[doc = "congfigure brownout\n\nYou can [`read`](crate::Reg::read) this register and get [`brown_out::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`brown_out::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct BROWN_OUT_SPEC;
+impl crate::RegisterSpec for BROWN_OUT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`brown_out::R`](R) reader structure"]
+impl crate::Readable for BROWN_OUT_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`brown_out::W`](W) writer structure"]
+impl crate::Writable for BROWN_OUT_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets BROWN_OUT to value 0x43ff_0010"]
+impl crate::Resettable for BROWN_OUT_SPEC {
+    const RESET_VALUE: u32 = 0x43ff_0010;
+}

vendor/esp32s3/src/rtc_cntl/clk_conf.rs

@@ -0,0 +1,320 @@
+#[doc = "Register `CLK_CONF` reader"]
+pub type R = crate::R<CLK_CONF_SPEC>;
+#[doc = "Register `CLK_CONF` writer"]
+pub type W = crate::W<CLK_CONF_SPEC>;
+#[doc = "Field `EFUSE_CLK_FORCE_GATING` reader - force efuse clk gating"]
+pub type EFUSE_CLK_FORCE_GATING_R = crate::BitReader;
+#[doc = "Field `EFUSE_CLK_FORCE_GATING` writer - force efuse clk gating"]
+pub type EFUSE_CLK_FORCE_GATING_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `EFUSE_CLK_FORCE_NOGATING` reader - force efuse clk nogating"]
+pub type EFUSE_CLK_FORCE_NOGATING_R = crate::BitReader;
+#[doc = "Field `EFUSE_CLK_FORCE_NOGATING` writer - force efuse clk nogating"]
+pub type EFUSE_CLK_FORCE_NOGATING_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CK8M_DIV_SEL_VLD` reader - used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel, then set vld to actually switch the clk"]
+pub type CK8M_DIV_SEL_VLD_R = crate::BitReader;
+#[doc = "Field `CK8M_DIV_SEL_VLD` writer - used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel, then set vld to actually switch the clk"]
+pub type CK8M_DIV_SEL_VLD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CK8M_DIV` reader - CK8M_D256_OUT divider. 00: div128, 01: div256, 10: div512, 11: div1024."]
+pub type CK8M_DIV_R = crate::FieldReader;
+#[doc = "Field `CK8M_DIV` writer - CK8M_D256_OUT divider. 00: div128, 01: div256, 10: div512, 11: div1024."]
+pub type CK8M_DIV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `ENB_CK8M` reader - disable CK8M and CK8M_D256_OUT"]
+pub type ENB_CK8M_R = crate::BitReader;
+#[doc = "Field `ENB_CK8M` writer - disable CK8M and CK8M_D256_OUT"]
+pub type ENB_CK8M_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ENB_CK8M_DIV` reader - 1: CK8M_D256_OUT is actually CK8M, 0: CK8M_D256_OUT is CK8M divided by 256"]
+pub type ENB_CK8M_DIV_R = crate::BitReader;
+#[doc = "Field `ENB_CK8M_DIV` writer - 1: CK8M_D256_OUT is actually CK8M, 0: CK8M_D256_OUT is CK8M divided by 256"]
+pub type ENB_CK8M_DIV_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DIG_XTAL32K_EN` reader - enable CK_XTAL_32K for digital core (no relationship with RTC core)"]
+pub type DIG_XTAL32K_EN_R = crate::BitReader;
+#[doc = "Field `DIG_XTAL32K_EN` writer - enable CK_XTAL_32K for digital core (no relationship with RTC core)"]
+pub type DIG_XTAL32K_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DIG_CLK8M_D256_EN` reader - enable CK8M_D256_OUT for digital core (no relationship with RTC core)"]
+pub type DIG_CLK8M_D256_EN_R = crate::BitReader;
+#[doc = "Field `DIG_CLK8M_D256_EN` writer - enable CK8M_D256_OUT for digital core (no relationship with RTC core)"]
+pub type DIG_CLK8M_D256_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DIG_CLK8M_EN` reader - enable CK8M for digital core (no relationship with RTC core)"]
+pub type DIG_CLK8M_EN_R = crate::BitReader;
+#[doc = "Field `DIG_CLK8M_EN` writer - enable CK8M for digital core (no relationship with RTC core)"]
+pub type DIG_CLK8M_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CK8M_DIV_SEL` reader - divider = reg_ck8m_div_sel + 1"]
+pub type CK8M_DIV_SEL_R = crate::FieldReader;
+#[doc = "Field `CK8M_DIV_SEL` writer - divider = reg_ck8m_div_sel + 1"]
+pub type CK8M_DIV_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `XTAL_FORCE_NOGATING` reader - XTAL force no gating during sleep"]
+pub type XTAL_FORCE_NOGATING_R = crate::BitReader;
+#[doc = "Field `XTAL_FORCE_NOGATING` writer - XTAL force no gating during sleep"]
+pub type XTAL_FORCE_NOGATING_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CK8M_FORCE_NOGATING` reader - CK8M force no gating during sleep"]
+pub type CK8M_FORCE_NOGATING_R = crate::BitReader;
+#[doc = "Field `CK8M_FORCE_NOGATING` writer - CK8M force no gating during sleep"]
+pub type CK8M_FORCE_NOGATING_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CK8M_DFREQ` reader - CK8M_DFREQ"]
+pub type CK8M_DFREQ_R = crate::FieldReader;
+#[doc = "Field `CK8M_DFREQ` writer - CK8M_DFREQ"]
+pub type CK8M_DFREQ_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+#[doc = "Field `CK8M_FORCE_PD` reader - CK8M force power down"]
+pub type CK8M_FORCE_PD_R = crate::BitReader;
+#[doc = "Field `CK8M_FORCE_PD` writer - CK8M force power down"]
+pub type CK8M_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CK8M_FORCE_PU` reader - CK8M force power up"]
+pub type CK8M_FORCE_PU_R = crate::BitReader;
+#[doc = "Field `CK8M_FORCE_PU` writer - CK8M force power up"]
+pub type CK8M_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `XTAL_GLOBAL_FORCE_GATING` reader - force global xtal gating"]
+pub type XTAL_GLOBAL_FORCE_GATING_R = crate::BitReader;
+#[doc = "Field `XTAL_GLOBAL_FORCE_GATING` writer - force global xtal gating"]
+pub type XTAL_GLOBAL_FORCE_GATING_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `XTAL_GLOBAL_FORCE_NOGATING` reader - force global xtal no gating"]
+pub type XTAL_GLOBAL_FORCE_NOGATING_R = crate::BitReader;
+#[doc = "Field `XTAL_GLOBAL_FORCE_NOGATING` writer - force global xtal no gating"]
+pub type XTAL_GLOBAL_FORCE_NOGATING_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FAST_CLK_RTC_SEL` reader - fast_clk_rtc sel. 0: XTAL div 4, 1: CK8M"]
+pub type FAST_CLK_RTC_SEL_R = crate::BitReader;
+#[doc = "Field `FAST_CLK_RTC_SEL` writer - fast_clk_rtc sel. 0: XTAL div 4, 1: CK8M"]
+pub type FAST_CLK_RTC_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ANA_CLK_RTC_SEL` reader - select slow clock"]
+pub type ANA_CLK_RTC_SEL_R = crate::FieldReader;
+#[doc = "Field `ANA_CLK_RTC_SEL` writer - select slow clock"]
+pub type ANA_CLK_RTC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+impl R {
+    #[doc = "Bit 1 - force efuse clk gating"]
+    #[inline(always)]
+    pub fn efuse_clk_force_gating(&self) -> EFUSE_CLK_FORCE_GATING_R {
+        EFUSE_CLK_FORCE_GATING_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - force efuse clk nogating"]
+    #[inline(always)]
+    pub fn efuse_clk_force_nogating(&self) -> EFUSE_CLK_FORCE_NOGATING_R {
+        EFUSE_CLK_FORCE_NOGATING_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel, then set vld to actually switch the clk"]
+    #[inline(always)]
+    pub fn ck8m_div_sel_vld(&self) -> CK8M_DIV_SEL_VLD_R {
+        CK8M_DIV_SEL_VLD_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bits 4:5 - CK8M_D256_OUT divider. 00: div128, 01: div256, 10: div512, 11: div1024."]
+    #[inline(always)]
+    pub fn ck8m_div(&self) -> CK8M_DIV_R {
+        CK8M_DIV_R::new(((self.bits >> 4) & 3) as u8)
+    }
+    #[doc = "Bit 6 - disable CK8M and CK8M_D256_OUT"]
+    #[inline(always)]
+    pub fn enb_ck8m(&self) -> ENB_CK8M_R {
+        ENB_CK8M_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - 1: CK8M_D256_OUT is actually CK8M, 0: CK8M_D256_OUT is CK8M divided by 256"]
+    #[inline(always)]
+    pub fn enb_ck8m_div(&self) -> ENB_CK8M_DIV_R {
+        ENB_CK8M_DIV_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - enable CK_XTAL_32K for digital core (no relationship with RTC core)"]
+    #[inline(always)]
+    pub fn dig_xtal32k_en(&self) -> DIG_XTAL32K_EN_R {
+        DIG_XTAL32K_EN_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - enable CK8M_D256_OUT for digital core (no relationship with RTC core)"]
+    #[inline(always)]
+    pub fn dig_clk8m_d256_en(&self) -> DIG_CLK8M_D256_EN_R {
+        DIG_CLK8M_D256_EN_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 10 - enable CK8M for digital core (no relationship with RTC core)"]
+    #[inline(always)]
+    pub fn dig_clk8m_en(&self) -> DIG_CLK8M_EN_R {
+        DIG_CLK8M_EN_R::new(((self.bits >> 10) & 1) != 0)
+    }
+    #[doc = "Bits 12:14 - divider = reg_ck8m_div_sel + 1"]
+    #[inline(always)]
+    pub fn ck8m_div_sel(&self) -> CK8M_DIV_SEL_R {
+        CK8M_DIV_SEL_R::new(((self.bits >> 12) & 7) as u8)
+    }
+    #[doc = "Bit 15 - XTAL force no gating during sleep"]
+    #[inline(always)]
+    pub fn xtal_force_nogating(&self) -> XTAL_FORCE_NOGATING_R {
+        XTAL_FORCE_NOGATING_R::new(((self.bits >> 15) & 1) != 0)
+    }
+    #[doc = "Bit 16 - CK8M force no gating during sleep"]
+    #[inline(always)]
+    pub fn ck8m_force_nogating(&self) -> CK8M_FORCE_NOGATING_R {
+        CK8M_FORCE_NOGATING_R::new(((self.bits >> 16) & 1) != 0)
+    }
+    #[doc = "Bits 17:24 - CK8M_DFREQ"]
+    #[inline(always)]
+    pub fn ck8m_dfreq(&self) -> CK8M_DFREQ_R {
+        CK8M_DFREQ_R::new(((self.bits >> 17) & 0xff) as u8)
+    }
+    #[doc = "Bit 25 - CK8M force power down"]
+    #[inline(always)]
+    pub fn ck8m_force_pd(&self) -> CK8M_FORCE_PD_R {
+        CK8M_FORCE_PD_R::new(((self.bits >> 25) & 1) != 0)
+    }
+    #[doc = "Bit 26 - CK8M force power up"]
+    #[inline(always)]
+    pub fn ck8m_force_pu(&self) -> CK8M_FORCE_PU_R {
+        CK8M_FORCE_PU_R::new(((self.bits >> 26) & 1) != 0)
+    }
+    #[doc = "Bit 27 - force global xtal gating"]
+    #[inline(always)]
+    pub fn xtal_global_force_gating(&self) -> XTAL_GLOBAL_FORCE_GATING_R {
+        XTAL_GLOBAL_FORCE_GATING_R::new(((self.bits >> 27) & 1) != 0)
+    }
+    #[doc = "Bit 28 - force global xtal no gating"]
+    #[inline(always)]
+    pub fn xtal_global_force_nogating(&self) -> XTAL_GLOBAL_FORCE_NOGATING_R {
+        XTAL_GLOBAL_FORCE_NOGATING_R::new(((self.bits >> 28) & 1) != 0)
+    }
+    #[doc = "Bit 29 - fast_clk_rtc sel. 0: XTAL div 4, 1: CK8M"]
+    #[inline(always)]
+    pub fn fast_clk_rtc_sel(&self) -> FAST_CLK_RTC_SEL_R {
+        FAST_CLK_RTC_SEL_R::new(((self.bits >> 29) & 1) != 0)
+    }
+    #[doc = "Bits 30:31 - select slow clock"]
+    #[inline(always)]
+    pub fn ana_clk_rtc_sel(&self) -> ANA_CLK_RTC_SEL_R {
+        ANA_CLK_RTC_SEL_R::new(((self.bits >> 30) & 3) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CLK_CONF")
+            .field("efuse_clk_force_gating", &self.efuse_clk_force_gating())
+            .field("efuse_clk_force_nogating", &self.efuse_clk_force_nogating())
+            .field("ck8m_div_sel_vld", &self.ck8m_div_sel_vld())
+            .field("ck8m_div", &self.ck8m_div())
+            .field("enb_ck8m", &self.enb_ck8m())
+            .field("enb_ck8m_div", &self.enb_ck8m_div())
+            .field("dig_xtal32k_en", &self.dig_xtal32k_en())
+            .field("dig_clk8m_d256_en", &self.dig_clk8m_d256_en())
+            .field("dig_clk8m_en", &self.dig_clk8m_en())
+            .field("ck8m_div_sel", &self.ck8m_div_sel())
+            .field("xtal_force_nogating", &self.xtal_force_nogating())
+            .field("ck8m_force_nogating", &self.ck8m_force_nogating())
+            .field("ck8m_dfreq", &self.ck8m_dfreq())
+            .field("ck8m_force_pd", &self.ck8m_force_pd())
+            .field("ck8m_force_pu", &self.ck8m_force_pu())
+            .field("xtal_global_force_gating", &self.xtal_global_force_gating())
+            .field(
+                "xtal_global_force_nogating",
+                &self.xtal_global_force_nogating(),
+            )
+            .field("fast_clk_rtc_sel", &self.fast_clk_rtc_sel())
+            .field("ana_clk_rtc_sel", &self.ana_clk_rtc_sel())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 1 - force efuse clk gating"]
+    #[inline(always)]
+    pub fn efuse_clk_force_gating(&mut self) -> EFUSE_CLK_FORCE_GATING_W<CLK_CONF_SPEC> {
+        EFUSE_CLK_FORCE_GATING_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - force efuse clk nogating"]
+    #[inline(always)]
+    pub fn efuse_clk_force_nogating(&mut self) -> EFUSE_CLK_FORCE_NOGATING_W<CLK_CONF_SPEC> {
+        EFUSE_CLK_FORCE_NOGATING_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel, then set vld to actually switch the clk"]
+    #[inline(always)]
+    pub fn ck8m_div_sel_vld(&mut self) -> CK8M_DIV_SEL_VLD_W<CLK_CONF_SPEC> {
+        CK8M_DIV_SEL_VLD_W::new(self, 3)
+    }
+    #[doc = "Bits 4:5 - CK8M_D256_OUT divider. 00: div128, 01: div256, 10: div512, 11: div1024."]
+    #[inline(always)]
+    pub fn ck8m_div(&mut self) -> CK8M_DIV_W<CLK_CONF_SPEC> {
+        CK8M_DIV_W::new(self, 4)
+    }
+    #[doc = "Bit 6 - disable CK8M and CK8M_D256_OUT"]
+    #[inline(always)]
+    pub fn enb_ck8m(&mut self) -> ENB_CK8M_W<CLK_CONF_SPEC> {
+        ENB_CK8M_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - 1: CK8M_D256_OUT is actually CK8M, 0: CK8M_D256_OUT is CK8M divided by 256"]
+    #[inline(always)]
+    pub fn enb_ck8m_div(&mut self) -> ENB_CK8M_DIV_W<CLK_CONF_SPEC> {
+        ENB_CK8M_DIV_W::new(self, 7)
+    }
+    #[doc = "Bit 8 - enable CK_XTAL_32K for digital core (no relationship with RTC core)"]
+    #[inline(always)]
+    pub fn dig_xtal32k_en(&mut self) -> DIG_XTAL32K_EN_W<CLK_CONF_SPEC> {
+        DIG_XTAL32K_EN_W::new(self, 8)
+    }
+    #[doc = "Bit 9 - enable CK8M_D256_OUT for digital core (no relationship with RTC core)"]
+    #[inline(always)]
+    pub fn dig_clk8m_d256_en(&mut self) -> DIG_CLK8M_D256_EN_W<CLK_CONF_SPEC> {
+        DIG_CLK8M_D256_EN_W::new(self, 9)
+    }
+    #[doc = "Bit 10 - enable CK8M for digital core (no relationship with RTC core)"]
+    #[inline(always)]
+    pub fn dig_clk8m_en(&mut self) -> DIG_CLK8M_EN_W<CLK_CONF_SPEC> {
+        DIG_CLK8M_EN_W::new(self, 10)
+    }
+    #[doc = "Bits 12:14 - divider = reg_ck8m_div_sel + 1"]
+    #[inline(always)]
+    pub fn ck8m_div_sel(&mut self) -> CK8M_DIV_SEL_W<CLK_CONF_SPEC> {
+        CK8M_DIV_SEL_W::new(self, 12)
+    }
+    #[doc = "Bit 15 - XTAL force no gating during sleep"]
+    #[inline(always)]
+    pub fn xtal_force_nogating(&mut self) -> XTAL_FORCE_NOGATING_W<CLK_CONF_SPEC> {
+        XTAL_FORCE_NOGATING_W::new(self, 15)
+    }
+    #[doc = "Bit 16 - CK8M force no gating during sleep"]
+    #[inline(always)]
+    pub fn ck8m_force_nogating(&mut self) -> CK8M_FORCE_NOGATING_W<CLK_CONF_SPEC> {
+        CK8M_FORCE_NOGATING_W::new(self, 16)
+    }
+    #[doc = "Bits 17:24 - CK8M_DFREQ"]
+    #[inline(always)]
+    pub fn ck8m_dfreq(&mut self) -> CK8M_DFREQ_W<CLK_CONF_SPEC> {
+        CK8M_DFREQ_W::new(self, 17)
+    }
+    #[doc = "Bit 25 - CK8M force power down"]
+    #[inline(always)]
+    pub fn ck8m_force_pd(&mut self) -> CK8M_FORCE_PD_W<CLK_CONF_SPEC> {
+        CK8M_FORCE_PD_W::new(self, 25)
+    }
+    #[doc = "Bit 26 - CK8M force power up"]
+    #[inline(always)]
+    pub fn ck8m_force_pu(&mut self) -> CK8M_FORCE_PU_W<CLK_CONF_SPEC> {
+        CK8M_FORCE_PU_W::new(self, 26)
+    }
+    #[doc = "Bit 27 - force global xtal gating"]
+    #[inline(always)]
+    pub fn xtal_global_force_gating(&mut self) -> XTAL_GLOBAL_FORCE_GATING_W<CLK_CONF_SPEC> {
+        XTAL_GLOBAL_FORCE_GATING_W::new(self, 27)
+    }
+    #[doc = "Bit 28 - force global xtal no gating"]
+    #[inline(always)]
+    pub fn xtal_global_force_nogating(&mut self) -> XTAL_GLOBAL_FORCE_NOGATING_W<CLK_CONF_SPEC> {
+        XTAL_GLOBAL_FORCE_NOGATING_W::new(self, 28)
+    }
+    #[doc = "Bit 29 - fast_clk_rtc sel. 0: XTAL div 4, 1: CK8M"]
+    #[inline(always)]
+    pub fn fast_clk_rtc_sel(&mut self) -> FAST_CLK_RTC_SEL_W<CLK_CONF_SPEC> {
+        FAST_CLK_RTC_SEL_W::new(self, 29)
+    }
+    #[doc = "Bits 30:31 - select slow clock"]
+    #[inline(always)]
+    pub fn ana_clk_rtc_sel(&mut self) -> ANA_CLK_RTC_SEL_W<CLK_CONF_SPEC> {
+        ANA_CLK_RTC_SEL_W::new(self, 30)
+    }
+}
+#[doc = "configure clock register\n\nYou can [`read`](crate::Reg::read) this register and get [`clk_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CLK_CONF_SPEC;
+impl crate::RegisterSpec for CLK_CONF_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`clk_conf::R`](R) reader structure"]
+impl crate::Readable for CLK_CONF_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`clk_conf::W`](W) writer structure"]
+impl crate::Writable for CLK_CONF_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CLK_CONF to value 0x1158_321c"]
+impl crate::Resettable for CLK_CONF_SPEC {
+    const RESET_VALUE: u32 = 0x1158_321c;
+}

vendor/esp32s3/src/rtc_cntl/cocpu_ctrl.rs

@@ -0,0 +1,189 @@
+#[doc = "Register `COCPU_CTRL` reader"]
+pub type R = crate::R<COCPU_CTRL_SPEC>;
+#[doc = "Register `COCPU_CTRL` writer"]
+pub type W = crate::W<COCPU_CTRL_SPEC>;
+#[doc = "Field `COCPU_CLK_FO` reader - cocpu clk force on"]
+pub type COCPU_CLK_FO_R = crate::BitReader;
+#[doc = "Field `COCPU_CLK_FO` writer - cocpu clk force on"]
+pub type COCPU_CLK_FO_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `COCPU_START_2_RESET_DIS` reader - time from start cocpu to pull down reset"]
+pub type COCPU_START_2_RESET_DIS_R = crate::FieldReader;
+#[doc = "Field `COCPU_START_2_RESET_DIS` writer - time from start cocpu to pull down reset"]
+pub type COCPU_START_2_RESET_DIS_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
+#[doc = "Field `COCPU_START_2_INTR_EN` reader - time from start cocpu to give start interrupt"]
+pub type COCPU_START_2_INTR_EN_R = crate::FieldReader;
+#[doc = "Field `COCPU_START_2_INTR_EN` writer - time from start cocpu to give start interrupt"]
+pub type COCPU_START_2_INTR_EN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
+#[doc = "Field `COCPU_SHUT` reader - to shut cocpu"]
+pub type COCPU_SHUT_R = crate::BitReader;
+#[doc = "Field `COCPU_SHUT` writer - to shut cocpu"]
+pub type COCPU_SHUT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `COCPU_SHUT_2_CLK_DIS` reader - time from shut cocpu to disable clk"]
+pub type COCPU_SHUT_2_CLK_DIS_R = crate::FieldReader;
+#[doc = "Field `COCPU_SHUT_2_CLK_DIS` writer - time from shut cocpu to disable clk"]
+pub type COCPU_SHUT_2_CLK_DIS_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+#[doc = "Field `COCPU_SHUT_RESET_EN` reader - to reset cocpu"]
+pub type COCPU_SHUT_RESET_EN_R = crate::BitReader;
+#[doc = "Field `COCPU_SHUT_RESET_EN` writer - to reset cocpu"]
+pub type COCPU_SHUT_RESET_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `COCPU_SEL` reader - 1: old ULP 0: new riscV"]
+pub type COCPU_SEL_R = crate::BitReader;
+#[doc = "Field `COCPU_SEL` writer - 1: old ULP 0: new riscV"]
+pub type COCPU_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `COCPU_DONE_FORCE` reader - 1: select riscv done 0: select ulp done"]
+pub type COCPU_DONE_FORCE_R = crate::BitReader;
+#[doc = "Field `COCPU_DONE_FORCE` writer - 1: select riscv done 0: select ulp done"]
+pub type COCPU_DONE_FORCE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `COCPU_DONE` reader - done signal used by riscv to control timer."]
+pub type COCPU_DONE_R = crate::BitReader;
+#[doc = "Field `COCPU_DONE` writer - done signal used by riscv to control timer."]
+pub type COCPU_DONE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `COCPU_SW_INT_TRIGGER` writer - trigger cocpu register interrupt"]
+pub type COCPU_SW_INT_TRIGGER_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `COCPU_CLKGATE_EN` reader - open ulp-riscv clk gate"]
+pub type COCPU_CLKGATE_EN_R = crate::BitReader;
+#[doc = "Field `COCPU_CLKGATE_EN` writer - open ulp-riscv clk gate"]
+pub type COCPU_CLKGATE_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - cocpu clk force on"]
+    #[inline(always)]
+    pub fn cocpu_clk_fo(&self) -> COCPU_CLK_FO_R {
+        COCPU_CLK_FO_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bits 1:6 - time from start cocpu to pull down reset"]
+    #[inline(always)]
+    pub fn cocpu_start_2_reset_dis(&self) -> COCPU_START_2_RESET_DIS_R {
+        COCPU_START_2_RESET_DIS_R::new(((self.bits >> 1) & 0x3f) as u8)
+    }
+    #[doc = "Bits 7:12 - time from start cocpu to give start interrupt"]
+    #[inline(always)]
+    pub fn cocpu_start_2_intr_en(&self) -> COCPU_START_2_INTR_EN_R {
+        COCPU_START_2_INTR_EN_R::new(((self.bits >> 7) & 0x3f) as u8)
+    }
+    #[doc = "Bit 13 - to shut cocpu"]
+    #[inline(always)]
+    pub fn cocpu_shut(&self) -> COCPU_SHUT_R {
+        COCPU_SHUT_R::new(((self.bits >> 13) & 1) != 0)
+    }
+    #[doc = "Bits 14:21 - time from shut cocpu to disable clk"]
+    #[inline(always)]
+    pub fn cocpu_shut_2_clk_dis(&self) -> COCPU_SHUT_2_CLK_DIS_R {
+        COCPU_SHUT_2_CLK_DIS_R::new(((self.bits >> 14) & 0xff) as u8)
+    }
+    #[doc = "Bit 22 - to reset cocpu"]
+    #[inline(always)]
+    pub fn cocpu_shut_reset_en(&self) -> COCPU_SHUT_RESET_EN_R {
+        COCPU_SHUT_RESET_EN_R::new(((self.bits >> 22) & 1) != 0)
+    }
+    #[doc = "Bit 23 - 1: old ULP 0: new riscV"]
+    #[inline(always)]
+    pub fn cocpu_sel(&self) -> COCPU_SEL_R {
+        COCPU_SEL_R::new(((self.bits >> 23) & 1) != 0)
+    }
+    #[doc = "Bit 24 - 1: select riscv done 0: select ulp done"]
+    #[inline(always)]
+    pub fn cocpu_done_force(&self) -> COCPU_DONE_FORCE_R {
+        COCPU_DONE_FORCE_R::new(((self.bits >> 24) & 1) != 0)
+    }
+    #[doc = "Bit 25 - done signal used by riscv to control timer."]
+    #[inline(always)]
+    pub fn cocpu_done(&self) -> COCPU_DONE_R {
+        COCPU_DONE_R::new(((self.bits >> 25) & 1) != 0)
+    }
+    #[doc = "Bit 27 - open ulp-riscv clk gate"]
+    #[inline(always)]
+    pub fn cocpu_clkgate_en(&self) -> COCPU_CLKGATE_EN_R {
+        COCPU_CLKGATE_EN_R::new(((self.bits >> 27) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("COCPU_CTRL")
+            .field("cocpu_clk_fo", &self.cocpu_clk_fo())
+            .field("cocpu_start_2_reset_dis", &self.cocpu_start_2_reset_dis())
+            .field("cocpu_start_2_intr_en", &self.cocpu_start_2_intr_en())
+            .field("cocpu_shut", &self.cocpu_shut())
+            .field("cocpu_shut_2_clk_dis", &self.cocpu_shut_2_clk_dis())
+            .field("cocpu_shut_reset_en", &self.cocpu_shut_reset_en())
+            .field("cocpu_sel", &self.cocpu_sel())
+            .field("cocpu_done_force", &self.cocpu_done_force())
+            .field("cocpu_done", &self.cocpu_done())
+            .field("cocpu_clkgate_en", &self.cocpu_clkgate_en())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - cocpu clk force on"]
+    #[inline(always)]
+    pub fn cocpu_clk_fo(&mut self) -> COCPU_CLK_FO_W<COCPU_CTRL_SPEC> {
+        COCPU_CLK_FO_W::new(self, 0)
+    }
+    #[doc = "Bits 1:6 - time from start cocpu to pull down reset"]
+    #[inline(always)]
+    pub fn cocpu_start_2_reset_dis(&mut self) -> COCPU_START_2_RESET_DIS_W<COCPU_CTRL_SPEC> {
+        COCPU_START_2_RESET_DIS_W::new(self, 1)
+    }
+    #[doc = "Bits 7:12 - time from start cocpu to give start interrupt"]
+    #[inline(always)]
+    pub fn cocpu_start_2_intr_en(&mut self) -> COCPU_START_2_INTR_EN_W<COCPU_CTRL_SPEC> {
+        COCPU_START_2_INTR_EN_W::new(self, 7)
+    }
+    #[doc = "Bit 13 - to shut cocpu"]
+    #[inline(always)]
+    pub fn cocpu_shut(&mut self) -> COCPU_SHUT_W<COCPU_CTRL_SPEC> {
+        COCPU_SHUT_W::new(self, 13)
+    }
+    #[doc = "Bits 14:21 - time from shut cocpu to disable clk"]
+    #[inline(always)]
+    pub fn cocpu_shut_2_clk_dis(&mut self) -> COCPU_SHUT_2_CLK_DIS_W<COCPU_CTRL_SPEC> {
+        COCPU_SHUT_2_CLK_DIS_W::new(self, 14)
+    }
+    #[doc = "Bit 22 - to reset cocpu"]
+    #[inline(always)]
+    pub fn cocpu_shut_reset_en(&mut self) -> COCPU_SHUT_RESET_EN_W<COCPU_CTRL_SPEC> {
+        COCPU_SHUT_RESET_EN_W::new(self, 22)
+    }
+    #[doc = "Bit 23 - 1: old ULP 0: new riscV"]
+    #[inline(always)]
+    pub fn cocpu_sel(&mut self) -> COCPU_SEL_W<COCPU_CTRL_SPEC> {
+        COCPU_SEL_W::new(self, 23)
+    }
+    #[doc = "Bit 24 - 1: select riscv done 0: select ulp done"]
+    #[inline(always)]
+    pub fn cocpu_done_force(&mut self) -> COCPU_DONE_FORCE_W<COCPU_CTRL_SPEC> {
+        COCPU_DONE_FORCE_W::new(self, 24)
+    }
+    #[doc = "Bit 25 - done signal used by riscv to control timer."]
+    #[inline(always)]
+    pub fn cocpu_done(&mut self) -> COCPU_DONE_W<COCPU_CTRL_SPEC> {
+        COCPU_DONE_W::new(self, 25)
+    }
+    #[doc = "Bit 26 - trigger cocpu register interrupt"]
+    #[inline(always)]
+    pub fn cocpu_sw_int_trigger(&mut self) -> COCPU_SW_INT_TRIGGER_W<COCPU_CTRL_SPEC> {
+        COCPU_SW_INT_TRIGGER_W::new(self, 26)
+    }
+    #[doc = "Bit 27 - open ulp-riscv clk gate"]
+    #[inline(always)]
+    pub fn cocpu_clkgate_en(&mut self) -> COCPU_CLKGATE_EN_W<COCPU_CTRL_SPEC> {
+        COCPU_CLKGATE_EN_W::new(self, 27)
+    }
+}
+#[doc = "configure ulp-riscv\n\nYou can [`read`](crate::Reg::read) this register and get [`cocpu_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cocpu_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct COCPU_CTRL_SPEC;
+impl crate::RegisterSpec for COCPU_CTRL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cocpu_ctrl::R`](R) reader structure"]
+impl crate::Readable for COCPU_CTRL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`cocpu_ctrl::W`](W) writer structure"]
+impl crate::Writable for COCPU_CTRL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets COCPU_CTRL to value 0x008a_0810"]
+impl crate::Resettable for COCPU_CTRL_SPEC {
+    const RESET_VALUE: u32 = 0x008a_0810;
+}

vendor/esp32s3/src/rtc_cntl/cocpu_disable.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `COCPU_DISABLE` reader"]
+pub type R = crate::R<COCPU_DISABLE_SPEC>;
+#[doc = "Register `COCPU_DISABLE` writer"]
+pub type W = crate::W<COCPU_DISABLE_SPEC>;
+#[doc = "Field `DISABLE_RTC_CPU` reader - configure ulp diable"]
+pub type DISABLE_RTC_CPU_R = crate::BitReader;
+#[doc = "Field `DISABLE_RTC_CPU` writer - configure ulp diable"]
+pub type DISABLE_RTC_CPU_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 31 - configure ulp diable"]
+    #[inline(always)]
+    pub fn disable_rtc_cpu(&self) -> DISABLE_RTC_CPU_R {
+        DISABLE_RTC_CPU_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("COCPU_DISABLE")
+            .field("disable_rtc_cpu", &self.disable_rtc_cpu())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 31 - configure ulp diable"]
+    #[inline(always)]
+    pub fn disable_rtc_cpu(&mut self) -> DISABLE_RTC_CPU_W<COCPU_DISABLE_SPEC> {
+        DISABLE_RTC_CPU_W::new(self, 31)
+    }
+}
+#[doc = "configure ulp diable\n\nYou can [`read`](crate::Reg::read) this register and get [`cocpu_disable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cocpu_disable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct COCPU_DISABLE_SPEC;
+impl crate::RegisterSpec for COCPU_DISABLE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cocpu_disable::R`](R) reader structure"]
+impl crate::Readable for COCPU_DISABLE_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`cocpu_disable::W`](W) writer structure"]
+impl crate::Writable for COCPU_DISABLE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets COCPU_DISABLE to value 0"]
+impl crate::Resettable for COCPU_DISABLE_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_cntl/cpu_period_conf.rs

@@ -0,0 +1,62 @@
+#[doc = "Register `CPU_PERIOD_CONF` reader"]
+pub type R = crate::R<CPU_PERIOD_CONF_SPEC>;
+#[doc = "Register `CPU_PERIOD_CONF` writer"]
+pub type W = crate::W<CPU_PERIOD_CONF_SPEC>;
+#[doc = "Field `CPUSEL_CONF` reader - CPU sel option"]
+pub type CPUSEL_CONF_R = crate::BitReader;
+#[doc = "Field `CPUSEL_CONF` writer - CPU sel option"]
+pub type CPUSEL_CONF_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CPUPERIOD_SEL` reader - conigure cpu freq"]
+pub type CPUPERIOD_SEL_R = crate::FieldReader;
+#[doc = "Field `CPUPERIOD_SEL` writer - conigure cpu freq"]
+pub type CPUPERIOD_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+impl R {
+    #[doc = "Bit 29 - CPU sel option"]
+    #[inline(always)]
+    pub fn cpusel_conf(&self) -> CPUSEL_CONF_R {
+        CPUSEL_CONF_R::new(((self.bits >> 29) & 1) != 0)
+    }
+    #[doc = "Bits 30:31 - conigure cpu freq"]
+    #[inline(always)]
+    pub fn cpuperiod_sel(&self) -> CPUPERIOD_SEL_R {
+        CPUPERIOD_SEL_R::new(((self.bits >> 30) & 3) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CPU_PERIOD_CONF")
+            .field("cpusel_conf", &self.cpusel_conf())
+            .field("cpuperiod_sel", &self.cpuperiod_sel())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 29 - CPU sel option"]
+    #[inline(always)]
+    pub fn cpusel_conf(&mut self) -> CPUSEL_CONF_W<CPU_PERIOD_CONF_SPEC> {
+        CPUSEL_CONF_W::new(self, 29)
+    }
+    #[doc = "Bits 30:31 - conigure cpu freq"]
+    #[inline(always)]
+    pub fn cpuperiod_sel(&mut self) -> CPUPERIOD_SEL_W<CPU_PERIOD_CONF_SPEC> {
+        CPUPERIOD_SEL_W::new(self, 30)
+    }
+}
+#[doc = "conigure cpu freq\n\nYou can [`read`](crate::Reg::read) this register and get [`cpu_period_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cpu_period_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CPU_PERIOD_CONF_SPEC;
+impl crate::RegisterSpec for CPU_PERIOD_CONF_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cpu_period_conf::R`](R) reader structure"]
+impl crate::Readable for CPU_PERIOD_CONF_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`cpu_period_conf::W`](W) writer structure"]
+impl crate::Writable for CPU_PERIOD_CONF_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CPU_PERIOD_CONF to value 0"]
+impl crate::Resettable for CPU_PERIOD_CONF_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_cntl/date.rs

@@ -0,0 +1,45 @@
+#[doc = "Register `DATE` reader"]
+pub type R = crate::R<DATE_SPEC>;
+#[doc = "Register `DATE` writer"]
+pub type W = crate::W<DATE_SPEC>;
+#[doc = "Field `DATE` reader - version register"]
+pub type DATE_R = crate::FieldReader<u32>;
+#[doc = "Field `DATE` writer - version register"]
+pub type DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>;
+impl R {
+    #[doc = "Bits 0:27 - version register"]
+    #[inline(always)]
+    pub fn date(&self) -> DATE_R {
+        DATE_R::new(self.bits & 0x0fff_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DATE").field("date", &self.date()).finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:27 - version register"]
+    #[inline(always)]
+    pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
+        DATE_W::new(self, 0)
+    }
+}
+#[doc = "version register\n\nYou can [`read`](crate::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DATE_SPEC;
+impl crate::RegisterSpec for DATE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`date::R`](R) reader structure"]
+impl crate::Readable for DATE_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"]
+impl crate::Writable for DATE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DATE to value 0x0210_1271"]
+impl crate::Resettable for DATE_SPEC {
+    const RESET_VALUE: u32 = 0x0210_1271;
+}

vendor/esp32s3/src/rtc_cntl/diag0.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `DIAG0` reader"]
+pub type R = crate::R<DIAG0_SPEC>;
+#[doc = "Field `LOW_POWER_DIAG1` reader - No public"]
+pub type LOW_POWER_DIAG1_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - No public"]
+    #[inline(always)]
+    pub fn low_power_diag1(&self) -> LOW_POWER_DIAG1_R {
+        LOW_POWER_DIAG1_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DIAG0")
+            .field("low_power_diag1", &self.low_power_diag1())
+            .finish()
+    }
+}
+#[doc = "No public\n\nYou can [`read`](crate::Reg::read) this register and get [`diag0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DIAG0_SPEC;
+impl crate::RegisterSpec for DIAG0_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`diag0::R`](R) reader structure"]
+impl crate::Readable for DIAG0_SPEC {}
+#[doc = "`reset()` method sets DIAG0 to value 0"]
+impl crate::Resettable for DIAG0_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_cntl/dig_iso.rs

@@ -0,0 +1,302 @@
+#[doc = "Register `DIG_ISO` reader"]
+pub type R = crate::R<DIG_ISO_SPEC>;
+#[doc = "Register `DIG_ISO` writer"]
+pub type W = crate::W<DIG_ISO_SPEC>;
+#[doc = "Field `FORCE_OFF` reader - No public"]
+pub type FORCE_OFF_R = crate::BitReader;
+#[doc = "Field `FORCE_OFF` writer - No public"]
+pub type FORCE_OFF_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FORCE_ON` reader - No public"]
+pub type FORCE_ON_R = crate::BitReader;
+#[doc = "Field `FORCE_ON` writer - No public"]
+pub type FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DG_PAD_AUTOHOLD` reader - read only register to indicate digital pad auto-hold status"]
+pub type DG_PAD_AUTOHOLD_R = crate::BitReader;
+#[doc = "Field `CLR_DG_PAD_AUTOHOLD` writer - wtite only register to clear digital pad auto-hold"]
+pub type CLR_DG_PAD_AUTOHOLD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DG_PAD_AUTOHOLD_EN` reader - digital pad enable auto-hold"]
+pub type DG_PAD_AUTOHOLD_EN_R = crate::BitReader;
+#[doc = "Field `DG_PAD_AUTOHOLD_EN` writer - digital pad enable auto-hold"]
+pub type DG_PAD_AUTOHOLD_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DG_PAD_FORCE_NOISO` reader - digital pad force no ISO"]
+pub type DG_PAD_FORCE_NOISO_R = crate::BitReader;
+#[doc = "Field `DG_PAD_FORCE_NOISO` writer - digital pad force no ISO"]
+pub type DG_PAD_FORCE_NOISO_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DG_PAD_FORCE_ISO` reader - digital pad force ISO"]
+pub type DG_PAD_FORCE_ISO_R = crate::BitReader;
+#[doc = "Field `DG_PAD_FORCE_ISO` writer - digital pad force ISO"]
+pub type DG_PAD_FORCE_ISO_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DG_PAD_FORCE_UNHOLD` reader - digital pad force un-hold"]
+pub type DG_PAD_FORCE_UNHOLD_R = crate::BitReader;
+#[doc = "Field `DG_PAD_FORCE_UNHOLD` writer - digital pad force un-hold"]
+pub type DG_PAD_FORCE_UNHOLD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DG_PAD_FORCE_HOLD` reader - digital pad force hold"]
+pub type DG_PAD_FORCE_HOLD_R = crate::BitReader;
+#[doc = "Field `DG_PAD_FORCE_HOLD` writer - digital pad force hold"]
+pub type DG_PAD_FORCE_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `BT_FORCE_ISO` reader - internal SRAM 2 force ISO"]
+pub type BT_FORCE_ISO_R = crate::BitReader;
+#[doc = "Field `BT_FORCE_ISO` writer - internal SRAM 2 force ISO"]
+pub type BT_FORCE_ISO_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `BT_FORCE_NOISO` reader - internal SRAM 2 force no ISO"]
+pub type BT_FORCE_NOISO_R = crate::BitReader;
+#[doc = "Field `BT_FORCE_NOISO` writer - internal SRAM 2 force no ISO"]
+pub type BT_FORCE_NOISO_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DG_PERI_FORCE_ISO` reader - internal SRAM 3 force ISO"]
+pub type DG_PERI_FORCE_ISO_R = crate::BitReader;
+#[doc = "Field `DG_PERI_FORCE_ISO` writer - internal SRAM 3 force ISO"]
+pub type DG_PERI_FORCE_ISO_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DG_PERI_FORCE_NOISO` reader - internal SRAM 3 force no ISO"]
+pub type DG_PERI_FORCE_NOISO_R = crate::BitReader;
+#[doc = "Field `DG_PERI_FORCE_NOISO` writer - internal SRAM 3 force no ISO"]
+pub type DG_PERI_FORCE_NOISO_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CPU_TOP_FORCE_ISO` reader - internal SRAM 4 force ISO"]
+pub type CPU_TOP_FORCE_ISO_R = crate::BitReader;
+#[doc = "Field `CPU_TOP_FORCE_ISO` writer - internal SRAM 4 force ISO"]
+pub type CPU_TOP_FORCE_ISO_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CPU_TOP_FORCE_NOISO` reader - internal SRAM 4 force no ISO"]
+pub type CPU_TOP_FORCE_NOISO_R = crate::BitReader;
+#[doc = "Field `CPU_TOP_FORCE_NOISO` writer - internal SRAM 4 force no ISO"]
+pub type CPU_TOP_FORCE_NOISO_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `WIFI_FORCE_ISO` reader - wifi force ISO"]
+pub type WIFI_FORCE_ISO_R = crate::BitReader;
+#[doc = "Field `WIFI_FORCE_ISO` writer - wifi force ISO"]
+pub type WIFI_FORCE_ISO_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `WIFI_FORCE_NOISO` reader - wifi force no ISO"]
+pub type WIFI_FORCE_NOISO_R = crate::BitReader;
+#[doc = "Field `WIFI_FORCE_NOISO` writer - wifi force no ISO"]
+pub type WIFI_FORCE_NOISO_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DG_WRAP_FORCE_ISO` reader - digital core force ISO"]
+pub type DG_WRAP_FORCE_ISO_R = crate::BitReader;
+#[doc = "Field `DG_WRAP_FORCE_ISO` writer - digital core force ISO"]
+pub type DG_WRAP_FORCE_ISO_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DG_WRAP_FORCE_NOISO` reader - digita core force no ISO"]
+pub type DG_WRAP_FORCE_NOISO_R = crate::BitReader;
+#[doc = "Field `DG_WRAP_FORCE_NOISO` writer - digita core force no ISO"]
+pub type DG_WRAP_FORCE_NOISO_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 7 - No public"]
+    #[inline(always)]
+    pub fn force_off(&self) -> FORCE_OFF_R {
+        FORCE_OFF_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - No public"]
+    #[inline(always)]
+    pub fn force_on(&self) -> FORCE_ON_R {
+        FORCE_ON_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - read only register to indicate digital pad auto-hold status"]
+    #[inline(always)]
+    pub fn dg_pad_autohold(&self) -> DG_PAD_AUTOHOLD_R {
+        DG_PAD_AUTOHOLD_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 11 - digital pad enable auto-hold"]
+    #[inline(always)]
+    pub fn dg_pad_autohold_en(&self) -> DG_PAD_AUTOHOLD_EN_R {
+        DG_PAD_AUTOHOLD_EN_R::new(((self.bits >> 11) & 1) != 0)
+    }
+    #[doc = "Bit 12 - digital pad force no ISO"]
+    #[inline(always)]
+    pub fn dg_pad_force_noiso(&self) -> DG_PAD_FORCE_NOISO_R {
+        DG_PAD_FORCE_NOISO_R::new(((self.bits >> 12) & 1) != 0)
+    }
+    #[doc = "Bit 13 - digital pad force ISO"]
+    #[inline(always)]
+    pub fn dg_pad_force_iso(&self) -> DG_PAD_FORCE_ISO_R {
+        DG_PAD_FORCE_ISO_R::new(((self.bits >> 13) & 1) != 0)
+    }
+    #[doc = "Bit 14 - digital pad force un-hold"]
+    #[inline(always)]
+    pub fn dg_pad_force_unhold(&self) -> DG_PAD_FORCE_UNHOLD_R {
+        DG_PAD_FORCE_UNHOLD_R::new(((self.bits >> 14) & 1) != 0)
+    }
+    #[doc = "Bit 15 - digital pad force hold"]
+    #[inline(always)]
+    pub fn dg_pad_force_hold(&self) -> DG_PAD_FORCE_HOLD_R {
+        DG_PAD_FORCE_HOLD_R::new(((self.bits >> 15) & 1) != 0)
+    }
+    #[doc = "Bit 22 - internal SRAM 2 force ISO"]
+    #[inline(always)]
+    pub fn bt_force_iso(&self) -> BT_FORCE_ISO_R {
+        BT_FORCE_ISO_R::new(((self.bits >> 22) & 1) != 0)
+    }
+    #[doc = "Bit 23 - internal SRAM 2 force no ISO"]
+    #[inline(always)]
+    pub fn bt_force_noiso(&self) -> BT_FORCE_NOISO_R {
+        BT_FORCE_NOISO_R::new(((self.bits >> 23) & 1) != 0)
+    }
+    #[doc = "Bit 24 - internal SRAM 3 force ISO"]
+    #[inline(always)]
+    pub fn dg_peri_force_iso(&self) -> DG_PERI_FORCE_ISO_R {
+        DG_PERI_FORCE_ISO_R::new(((self.bits >> 24) & 1) != 0)
+    }
+    #[doc = "Bit 25 - internal SRAM 3 force no ISO"]
+    #[inline(always)]
+    pub fn dg_peri_force_noiso(&self) -> DG_PERI_FORCE_NOISO_R {
+        DG_PERI_FORCE_NOISO_R::new(((self.bits >> 25) & 1) != 0)
+    }
+    #[doc = "Bit 26 - internal SRAM 4 force ISO"]
+    #[inline(always)]
+    pub fn cpu_top_force_iso(&self) -> CPU_TOP_FORCE_ISO_R {
+        CPU_TOP_FORCE_ISO_R::new(((self.bits >> 26) & 1) != 0)
+    }
+    #[doc = "Bit 27 - internal SRAM 4 force no ISO"]
+    #[inline(always)]
+    pub fn cpu_top_force_noiso(&self) -> CPU_TOP_FORCE_NOISO_R {
+        CPU_TOP_FORCE_NOISO_R::new(((self.bits >> 27) & 1) != 0)
+    }
+    #[doc = "Bit 28 - wifi force ISO"]
+    #[inline(always)]
+    pub fn wifi_force_iso(&self) -> WIFI_FORCE_ISO_R {
+        WIFI_FORCE_ISO_R::new(((self.bits >> 28) & 1) != 0)
+    }
+    #[doc = "Bit 29 - wifi force no ISO"]
+    #[inline(always)]
+    pub fn wifi_force_noiso(&self) -> WIFI_FORCE_NOISO_R {
+        WIFI_FORCE_NOISO_R::new(((self.bits >> 29) & 1) != 0)
+    }
+    #[doc = "Bit 30 - digital core force ISO"]
+    #[inline(always)]
+    pub fn dg_wrap_force_iso(&self) -> DG_WRAP_FORCE_ISO_R {
+        DG_WRAP_FORCE_ISO_R::new(((self.bits >> 30) & 1) != 0)
+    }
+    #[doc = "Bit 31 - digita core force no ISO"]
+    #[inline(always)]
+    pub fn dg_wrap_force_noiso(&self) -> DG_WRAP_FORCE_NOISO_R {
+        DG_WRAP_FORCE_NOISO_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DIG_ISO")
+            .field("force_off", &self.force_off())
+            .field("force_on", &self.force_on())
+            .field("dg_pad_autohold", &self.dg_pad_autohold())
+            .field("dg_pad_autohold_en", &self.dg_pad_autohold_en())
+            .field("dg_pad_force_noiso", &self.dg_pad_force_noiso())
+            .field("dg_pad_force_iso", &self.dg_pad_force_iso())
+            .field("dg_pad_force_unhold", &self.dg_pad_force_unhold())
+            .field("dg_pad_force_hold", &self.dg_pad_force_hold())
+            .field("bt_force_iso", &self.bt_force_iso())
+            .field("bt_force_noiso", &self.bt_force_noiso())
+            .field("dg_peri_force_iso", &self.dg_peri_force_iso())
+            .field("dg_peri_force_noiso", &self.dg_peri_force_noiso())
+            .field("cpu_top_force_iso", &self.cpu_top_force_iso())
+            .field("cpu_top_force_noiso", &self.cpu_top_force_noiso())
+            .field("wifi_force_iso", &self.wifi_force_iso())
+            .field("wifi_force_noiso", &self.wifi_force_noiso())
+            .field("dg_wrap_force_iso", &self.dg_wrap_force_iso())
+            .field("dg_wrap_force_noiso", &self.dg_wrap_force_noiso())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 7 - No public"]
+    #[inline(always)]
+    pub fn force_off(&mut self) -> FORCE_OFF_W<DIG_ISO_SPEC> {
+        FORCE_OFF_W::new(self, 7)
+    }
+    #[doc = "Bit 8 - No public"]
+    #[inline(always)]
+    pub fn force_on(&mut self) -> FORCE_ON_W<DIG_ISO_SPEC> {
+        FORCE_ON_W::new(self, 8)
+    }
+    #[doc = "Bit 10 - wtite only register to clear digital pad auto-hold"]
+    #[inline(always)]
+    pub fn clr_dg_pad_autohold(&mut self) -> CLR_DG_PAD_AUTOHOLD_W<DIG_ISO_SPEC> {
+        CLR_DG_PAD_AUTOHOLD_W::new(self, 10)
+    }
+    #[doc = "Bit 11 - digital pad enable auto-hold"]
+    #[inline(always)]
+    pub fn dg_pad_autohold_en(&mut self) -> DG_PAD_AUTOHOLD_EN_W<DIG_ISO_SPEC> {
+        DG_PAD_AUTOHOLD_EN_W::new(self, 11)
+    }
+    #[doc = "Bit 12 - digital pad force no ISO"]
+    #[inline(always)]
+    pub fn dg_pad_force_noiso(&mut self) -> DG_PAD_FORCE_NOISO_W<DIG_ISO_SPEC> {
+        DG_PAD_FORCE_NOISO_W::new(self, 12)
+    }
+    #[doc = "Bit 13 - digital pad force ISO"]
+    #[inline(always)]
+    pub fn dg_pad_force_iso(&mut self) -> DG_PAD_FORCE_ISO_W<DIG_ISO_SPEC> {
+        DG_PAD_FORCE_ISO_W::new(self, 13)
+    }
+    #[doc = "Bit 14 - digital pad force un-hold"]
+    #[inline(always)]
+    pub fn dg_pad_force_unhold(&mut self) -> DG_PAD_FORCE_UNHOLD_W<DIG_ISO_SPEC> {
+        DG_PAD_FORCE_UNHOLD_W::new(self, 14)
+    }
+    #[doc = "Bit 15 - digital pad force hold"]
+    #[inline(always)]
+    pub fn dg_pad_force_hold(&mut self) -> DG_PAD_FORCE_HOLD_W<DIG_ISO_SPEC> {
+        DG_PAD_FORCE_HOLD_W::new(self, 15)
+    }
+    #[doc = "Bit 22 - internal SRAM 2 force ISO"]
+    #[inline(always)]
+    pub fn bt_force_iso(&mut self) -> BT_FORCE_ISO_W<DIG_ISO_SPEC> {
+        BT_FORCE_ISO_W::new(self, 22)
+    }
+    #[doc = "Bit 23 - internal SRAM 2 force no ISO"]
+    #[inline(always)]
+    pub fn bt_force_noiso(&mut self) -> BT_FORCE_NOISO_W<DIG_ISO_SPEC> {
+        BT_FORCE_NOISO_W::new(self, 23)
+    }
+    #[doc = "Bit 24 - internal SRAM 3 force ISO"]
+    #[inline(always)]
+    pub fn dg_peri_force_iso(&mut self) -> DG_PERI_FORCE_ISO_W<DIG_ISO_SPEC> {
+        DG_PERI_FORCE_ISO_W::new(self, 24)
+    }
+    #[doc = "Bit 25 - internal SRAM 3 force no ISO"]
+    #[inline(always)]
+    pub fn dg_peri_force_noiso(&mut self) -> DG_PERI_FORCE_NOISO_W<DIG_ISO_SPEC> {
+        DG_PERI_FORCE_NOISO_W::new(self, 25)
+    }
+    #[doc = "Bit 26 - internal SRAM 4 force ISO"]
+    #[inline(always)]
+    pub fn cpu_top_force_iso(&mut self) -> CPU_TOP_FORCE_ISO_W<DIG_ISO_SPEC> {
+        CPU_TOP_FORCE_ISO_W::new(self, 26)
+    }
+    #[doc = "Bit 27 - internal SRAM 4 force no ISO"]
+    #[inline(always)]
+    pub fn cpu_top_force_noiso(&mut self) -> CPU_TOP_FORCE_NOISO_W<DIG_ISO_SPEC> {
+        CPU_TOP_FORCE_NOISO_W::new(self, 27)
+    }
+    #[doc = "Bit 28 - wifi force ISO"]
+    #[inline(always)]
+    pub fn wifi_force_iso(&mut self) -> WIFI_FORCE_ISO_W<DIG_ISO_SPEC> {
+        WIFI_FORCE_ISO_W::new(self, 28)
+    }
+    #[doc = "Bit 29 - wifi force no ISO"]
+    #[inline(always)]
+    pub fn wifi_force_noiso(&mut self) -> WIFI_FORCE_NOISO_W<DIG_ISO_SPEC> {
+        WIFI_FORCE_NOISO_W::new(self, 29)
+    }
+    #[doc = "Bit 30 - digital core force ISO"]
+    #[inline(always)]
+    pub fn dg_wrap_force_iso(&mut self) -> DG_WRAP_FORCE_ISO_W<DIG_ISO_SPEC> {
+        DG_WRAP_FORCE_ISO_W::new(self, 30)
+    }
+    #[doc = "Bit 31 - digita core force no ISO"]
+    #[inline(always)]
+    pub fn dg_wrap_force_noiso(&mut self) -> DG_WRAP_FORCE_NOISO_W<DIG_ISO_SPEC> {
+        DG_WRAP_FORCE_NOISO_W::new(self, 31)
+    }
+}
+#[doc = "congigure digital power isolation\n\nYou can [`read`](crate::Reg::read) this register and get [`dig_iso::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dig_iso::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DIG_ISO_SPEC;
+impl crate::RegisterSpec for DIG_ISO_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`dig_iso::R`](R) reader structure"]
+impl crate::Readable for DIG_ISO_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`dig_iso::W`](W) writer structure"]
+impl crate::Writable for DIG_ISO_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DIG_ISO to value 0xaa80_5080"]
+impl crate::Resettable for DIG_ISO_SPEC {
+    const RESET_VALUE: u32 = 0xaa80_5080;
+}

vendor/esp32s3/src/rtc_cntl/dig_pad_hold.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `DIG_PAD_HOLD` reader"]
+pub type R = crate::R<DIG_PAD_HOLD_SPEC>;
+#[doc = "Register `DIG_PAD_HOLD` writer"]
+pub type W = crate::W<DIG_PAD_HOLD_SPEC>;
+#[doc = "Field `DIG_PAD_HOLD` reader - configure digtal pad hold"]
+pub type DIG_PAD_HOLD_R = crate::FieldReader<u32>;
+#[doc = "Field `DIG_PAD_HOLD` writer - configure digtal pad hold"]
+pub type DIG_PAD_HOLD_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - configure digtal pad hold"]
+    #[inline(always)]
+    pub fn dig_pad_hold(&self) -> DIG_PAD_HOLD_R {
+        DIG_PAD_HOLD_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DIG_PAD_HOLD")
+            .field("dig_pad_hold", &self.dig_pad_hold())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - configure digtal pad hold"]
+    #[inline(always)]
+    pub fn dig_pad_hold(&mut self) -> DIG_PAD_HOLD_W<DIG_PAD_HOLD_SPEC> {
+        DIG_PAD_HOLD_W::new(self, 0)
+    }
+}
+#[doc = "configure digtal pad hold\n\nYou can [`read`](crate::Reg::read) this register and get [`dig_pad_hold::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dig_pad_hold::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DIG_PAD_HOLD_SPEC;
+impl crate::RegisterSpec for DIG_PAD_HOLD_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`dig_pad_hold::R`](R) reader structure"]
+impl crate::Readable for DIG_PAD_HOLD_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`dig_pad_hold::W`](W) writer structure"]
+impl crate::Writable for DIG_PAD_HOLD_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DIG_PAD_HOLD to value 0"]
+impl crate::Resettable for DIG_PAD_HOLD_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_cntl/dig_pwc.rs

@@ -0,0 +1,287 @@
+#[doc = "Register `DIG_PWC` reader"]
+pub type R = crate::R<DIG_PWC_SPEC>;
+#[doc = "Register `DIG_PWC` writer"]
+pub type W = crate::W<DIG_PWC_SPEC>;
+#[doc = "Field `LSLP_MEM_FORCE_PD` reader - memories in digital core force PD in sleep"]
+pub type LSLP_MEM_FORCE_PD_R = crate::BitReader;
+#[doc = "Field `LSLP_MEM_FORCE_PD` writer - memories in digital core force PD in sleep"]
+pub type LSLP_MEM_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `LSLP_MEM_FORCE_PU` reader - memories in digital core force no PD in sleep"]
+pub type LSLP_MEM_FORCE_PU_R = crate::BitReader;
+#[doc = "Field `LSLP_MEM_FORCE_PU` writer - memories in digital core force no PD in sleep"]
+pub type LSLP_MEM_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `BT_FORCE_PD` reader - internal SRAM 2 force power down"]
+pub type BT_FORCE_PD_R = crate::BitReader;
+#[doc = "Field `BT_FORCE_PD` writer - internal SRAM 2 force power down"]
+pub type BT_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `BT_FORCE_PU` reader - internal SRAM 2 force power up"]
+pub type BT_FORCE_PU_R = crate::BitReader;
+#[doc = "Field `BT_FORCE_PU` writer - internal SRAM 2 force power up"]
+pub type BT_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DG_PERI_FORCE_PD` reader - internal SRAM 3 force power down"]
+pub type DG_PERI_FORCE_PD_R = crate::BitReader;
+#[doc = "Field `DG_PERI_FORCE_PD` writer - internal SRAM 3 force power down"]
+pub type DG_PERI_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DG_PERI_FORCE_PU` reader - internal SRAM 3 force power up"]
+pub type DG_PERI_FORCE_PU_R = crate::BitReader;
+#[doc = "Field `DG_PERI_FORCE_PU` writer - internal SRAM 3 force power up"]
+pub type DG_PERI_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `WIFI_FORCE_PD` reader - wifi force power down"]
+pub type WIFI_FORCE_PD_R = crate::BitReader;
+#[doc = "Field `WIFI_FORCE_PD` writer - wifi force power down"]
+pub type WIFI_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `WIFI_FORCE_PU` reader - wifi force power up"]
+pub type WIFI_FORCE_PU_R = crate::BitReader;
+#[doc = "Field `WIFI_FORCE_PU` writer - wifi force power up"]
+pub type WIFI_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DG_WRAP_FORCE_PD` reader - digital core force power down"]
+pub type DG_WRAP_FORCE_PD_R = crate::BitReader;
+#[doc = "Field `DG_WRAP_FORCE_PD` writer - digital core force power down"]
+pub type DG_WRAP_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DG_WRAP_FORCE_PU` reader - digital core force power up"]
+pub type DG_WRAP_FORCE_PU_R = crate::BitReader;
+#[doc = "Field `DG_WRAP_FORCE_PU` writer - digital core force power up"]
+pub type DG_WRAP_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CPU_TOP_FORCE_PD` reader - digital dcdc force power down"]
+pub type CPU_TOP_FORCE_PD_R = crate::BitReader;
+#[doc = "Field `CPU_TOP_FORCE_PD` writer - digital dcdc force power down"]
+pub type CPU_TOP_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CPU_TOP_FORCE_PU` reader - digital dcdc force power up"]
+pub type CPU_TOP_FORCE_PU_R = crate::BitReader;
+#[doc = "Field `CPU_TOP_FORCE_PU` writer - digital dcdc force power up"]
+pub type CPU_TOP_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `BT_PD_EN` reader - enable power down internal SRAM 2 in sleep"]
+pub type BT_PD_EN_R = crate::BitReader;
+#[doc = "Field `BT_PD_EN` writer - enable power down internal SRAM 2 in sleep"]
+pub type BT_PD_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DG_PERI_PD_EN` reader - enable power down internal SRAM 3 in sleep"]
+pub type DG_PERI_PD_EN_R = crate::BitReader;
+#[doc = "Field `DG_PERI_PD_EN` writer - enable power down internal SRAM 3 in sleep"]
+pub type DG_PERI_PD_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CPU_TOP_PD_EN` reader - enable power down internal SRAM 4 in sleep"]
+pub type CPU_TOP_PD_EN_R = crate::BitReader;
+#[doc = "Field `CPU_TOP_PD_EN` writer - enable power down internal SRAM 4 in sleep"]
+pub type CPU_TOP_PD_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `WIFI_PD_EN` reader - enable power down wifi in sleep"]
+pub type WIFI_PD_EN_R = crate::BitReader;
+#[doc = "Field `WIFI_PD_EN` writer - enable power down wifi in sleep"]
+pub type WIFI_PD_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DG_WRAP_PD_EN` reader - enable power down all digital logic"]
+pub type DG_WRAP_PD_EN_R = crate::BitReader;
+#[doc = "Field `DG_WRAP_PD_EN` writer - enable power down all digital logic"]
+pub type DG_WRAP_PD_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 3 - memories in digital core force PD in sleep"]
+    #[inline(always)]
+    pub fn lslp_mem_force_pd(&self) -> LSLP_MEM_FORCE_PD_R {
+        LSLP_MEM_FORCE_PD_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - memories in digital core force no PD in sleep"]
+    #[inline(always)]
+    pub fn lslp_mem_force_pu(&self) -> LSLP_MEM_FORCE_PU_R {
+        LSLP_MEM_FORCE_PU_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 11 - internal SRAM 2 force power down"]
+    #[inline(always)]
+    pub fn bt_force_pd(&self) -> BT_FORCE_PD_R {
+        BT_FORCE_PD_R::new(((self.bits >> 11) & 1) != 0)
+    }
+    #[doc = "Bit 12 - internal SRAM 2 force power up"]
+    #[inline(always)]
+    pub fn bt_force_pu(&self) -> BT_FORCE_PU_R {
+        BT_FORCE_PU_R::new(((self.bits >> 12) & 1) != 0)
+    }
+    #[doc = "Bit 13 - internal SRAM 3 force power down"]
+    #[inline(always)]
+    pub fn dg_peri_force_pd(&self) -> DG_PERI_FORCE_PD_R {
+        DG_PERI_FORCE_PD_R::new(((self.bits >> 13) & 1) != 0)
+    }
+    #[doc = "Bit 14 - internal SRAM 3 force power up"]
+    #[inline(always)]
+    pub fn dg_peri_force_pu(&self) -> DG_PERI_FORCE_PU_R {
+        DG_PERI_FORCE_PU_R::new(((self.bits >> 14) & 1) != 0)
+    }
+    #[doc = "Bit 17 - wifi force power down"]
+    #[inline(always)]
+    pub fn wifi_force_pd(&self) -> WIFI_FORCE_PD_R {
+        WIFI_FORCE_PD_R::new(((self.bits >> 17) & 1) != 0)
+    }
+    #[doc = "Bit 18 - wifi force power up"]
+    #[inline(always)]
+    pub fn wifi_force_pu(&self) -> WIFI_FORCE_PU_R {
+        WIFI_FORCE_PU_R::new(((self.bits >> 18) & 1) != 0)
+    }
+    #[doc = "Bit 19 - digital core force power down"]
+    #[inline(always)]
+    pub fn dg_wrap_force_pd(&self) -> DG_WRAP_FORCE_PD_R {
+        DG_WRAP_FORCE_PD_R::new(((self.bits >> 19) & 1) != 0)
+    }
+    #[doc = "Bit 20 - digital core force power up"]
+    #[inline(always)]
+    pub fn dg_wrap_force_pu(&self) -> DG_WRAP_FORCE_PU_R {
+        DG_WRAP_FORCE_PU_R::new(((self.bits >> 20) & 1) != 0)
+    }
+    #[doc = "Bit 21 - digital dcdc force power down"]
+    #[inline(always)]
+    pub fn cpu_top_force_pd(&self) -> CPU_TOP_FORCE_PD_R {
+        CPU_TOP_FORCE_PD_R::new(((self.bits >> 21) & 1) != 0)
+    }
+    #[doc = "Bit 22 - digital dcdc force power up"]
+    #[inline(always)]
+    pub fn cpu_top_force_pu(&self) -> CPU_TOP_FORCE_PU_R {
+        CPU_TOP_FORCE_PU_R::new(((self.bits >> 22) & 1) != 0)
+    }
+    #[doc = "Bit 27 - enable power down internal SRAM 2 in sleep"]
+    #[inline(always)]
+    pub fn bt_pd_en(&self) -> BT_PD_EN_R {
+        BT_PD_EN_R::new(((self.bits >> 27) & 1) != 0)
+    }
+    #[doc = "Bit 28 - enable power down internal SRAM 3 in sleep"]
+    #[inline(always)]
+    pub fn dg_peri_pd_en(&self) -> DG_PERI_PD_EN_R {
+        DG_PERI_PD_EN_R::new(((self.bits >> 28) & 1) != 0)
+    }
+    #[doc = "Bit 29 - enable power down internal SRAM 4 in sleep"]
+    #[inline(always)]
+    pub fn cpu_top_pd_en(&self) -> CPU_TOP_PD_EN_R {
+        CPU_TOP_PD_EN_R::new(((self.bits >> 29) & 1) != 0)
+    }
+    #[doc = "Bit 30 - enable power down wifi in sleep"]
+    #[inline(always)]
+    pub fn wifi_pd_en(&self) -> WIFI_PD_EN_R {
+        WIFI_PD_EN_R::new(((self.bits >> 30) & 1) != 0)
+    }
+    #[doc = "Bit 31 - enable power down all digital logic"]
+    #[inline(always)]
+    pub fn dg_wrap_pd_en(&self) -> DG_WRAP_PD_EN_R {
+        DG_WRAP_PD_EN_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DIG_PWC")
+            .field("lslp_mem_force_pd", &self.lslp_mem_force_pd())
+            .field("lslp_mem_force_pu", &self.lslp_mem_force_pu())
+            .field("bt_force_pd", &self.bt_force_pd())
+            .field("bt_force_pu", &self.bt_force_pu())
+            .field("dg_peri_force_pd", &self.dg_peri_force_pd())
+            .field("dg_peri_force_pu", &self.dg_peri_force_pu())
+            .field("wifi_force_pd", &self.wifi_force_pd())
+            .field("wifi_force_pu", &self.wifi_force_pu())
+            .field("dg_wrap_force_pd", &self.dg_wrap_force_pd())
+            .field("dg_wrap_force_pu", &self.dg_wrap_force_pu())
+            .field("cpu_top_force_pd", &self.cpu_top_force_pd())
+            .field("cpu_top_force_pu", &self.cpu_top_force_pu())
+            .field("bt_pd_en", &self.bt_pd_en())
+            .field("dg_peri_pd_en", &self.dg_peri_pd_en())
+            .field("cpu_top_pd_en", &self.cpu_top_pd_en())
+            .field("wifi_pd_en", &self.wifi_pd_en())
+            .field("dg_wrap_pd_en", &self.dg_wrap_pd_en())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 3 - memories in digital core force PD in sleep"]
+    #[inline(always)]
+    pub fn lslp_mem_force_pd(&mut self) -> LSLP_MEM_FORCE_PD_W<DIG_PWC_SPEC> {
+        LSLP_MEM_FORCE_PD_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - memories in digital core force no PD in sleep"]
+    #[inline(always)]
+    pub fn lslp_mem_force_pu(&mut self) -> LSLP_MEM_FORCE_PU_W<DIG_PWC_SPEC> {
+        LSLP_MEM_FORCE_PU_W::new(self, 4)
+    }
+    #[doc = "Bit 11 - internal SRAM 2 force power down"]
+    #[inline(always)]
+    pub fn bt_force_pd(&mut self) -> BT_FORCE_PD_W<DIG_PWC_SPEC> {
+        BT_FORCE_PD_W::new(self, 11)
+    }
+    #[doc = "Bit 12 - internal SRAM 2 force power up"]
+    #[inline(always)]
+    pub fn bt_force_pu(&mut self) -> BT_FORCE_PU_W<DIG_PWC_SPEC> {
+        BT_FORCE_PU_W::new(self, 12)
+    }
+    #[doc = "Bit 13 - internal SRAM 3 force power down"]
+    #[inline(always)]
+    pub fn dg_peri_force_pd(&mut self) -> DG_PERI_FORCE_PD_W<DIG_PWC_SPEC> {
+        DG_PERI_FORCE_PD_W::new(self, 13)
+    }
+    #[doc = "Bit 14 - internal SRAM 3 force power up"]
+    #[inline(always)]
+    pub fn dg_peri_force_pu(&mut self) -> DG_PERI_FORCE_PU_W<DIG_PWC_SPEC> {
+        DG_PERI_FORCE_PU_W::new(self, 14)
+    }
+    #[doc = "Bit 17 - wifi force power down"]
+    #[inline(always)]
+    pub fn wifi_force_pd(&mut self) -> WIFI_FORCE_PD_W<DIG_PWC_SPEC> {
+        WIFI_FORCE_PD_W::new(self, 17)
+    }
+    #[doc = "Bit 18 - wifi force power up"]
+    #[inline(always)]
+    pub fn wifi_force_pu(&mut self) -> WIFI_FORCE_PU_W<DIG_PWC_SPEC> {
+        WIFI_FORCE_PU_W::new(self, 18)
+    }
+    #[doc = "Bit 19 - digital core force power down"]
+    #[inline(always)]
+    pub fn dg_wrap_force_pd(&mut self) -> DG_WRAP_FORCE_PD_W<DIG_PWC_SPEC> {
+        DG_WRAP_FORCE_PD_W::new(self, 19)
+    }
+    #[doc = "Bit 20 - digital core force power up"]
+    #[inline(always)]
+    pub fn dg_wrap_force_pu(&mut self) -> DG_WRAP_FORCE_PU_W<DIG_PWC_SPEC> {
+        DG_WRAP_FORCE_PU_W::new(self, 20)
+    }
+    #[doc = "Bit 21 - digital dcdc force power down"]
+    #[inline(always)]
+    pub fn cpu_top_force_pd(&mut self) -> CPU_TOP_FORCE_PD_W<DIG_PWC_SPEC> {
+        CPU_TOP_FORCE_PD_W::new(self, 21)
+    }
+    #[doc = "Bit 22 - digital dcdc force power up"]
+    #[inline(always)]
+    pub fn cpu_top_force_pu(&mut self) -> CPU_TOP_FORCE_PU_W<DIG_PWC_SPEC> {
+        CPU_TOP_FORCE_PU_W::new(self, 22)
+    }
+    #[doc = "Bit 27 - enable power down internal SRAM 2 in sleep"]
+    #[inline(always)]
+    pub fn bt_pd_en(&mut self) -> BT_PD_EN_W<DIG_PWC_SPEC> {
+        BT_PD_EN_W::new(self, 27)
+    }
+    #[doc = "Bit 28 - enable power down internal SRAM 3 in sleep"]
+    #[inline(always)]
+    pub fn dg_peri_pd_en(&mut self) -> DG_PERI_PD_EN_W<DIG_PWC_SPEC> {
+        DG_PERI_PD_EN_W::new(self, 28)
+    }
+    #[doc = "Bit 29 - enable power down internal SRAM 4 in sleep"]
+    #[inline(always)]
+    pub fn cpu_top_pd_en(&mut self) -> CPU_TOP_PD_EN_W<DIG_PWC_SPEC> {
+        CPU_TOP_PD_EN_W::new(self, 29)
+    }
+    #[doc = "Bit 30 - enable power down wifi in sleep"]
+    #[inline(always)]
+    pub fn wifi_pd_en(&mut self) -> WIFI_PD_EN_W<DIG_PWC_SPEC> {
+        WIFI_PD_EN_W::new(self, 30)
+    }
+    #[doc = "Bit 31 - enable power down all digital logic"]
+    #[inline(always)]
+    pub fn dg_wrap_pd_en(&mut self) -> DG_WRAP_PD_EN_W<DIG_PWC_SPEC> {
+        DG_WRAP_PD_EN_W::new(self, 31)
+    }
+}
+#[doc = "configure digital power\n\nYou can [`read`](crate::Reg::read) this register and get [`dig_pwc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dig_pwc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DIG_PWC_SPEC;
+impl crate::RegisterSpec for DIG_PWC_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`dig_pwc::R`](R) reader structure"]
+impl crate::Readable for DIG_PWC_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`dig_pwc::W`](W) writer structure"]
+impl crate::Writable for DIG_PWC_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DIG_PWC to value 0x0054_5010"]
+impl crate::Resettable for DIG_PWC_SPEC {
+    const RESET_VALUE: u32 = 0x0054_5010;
+}

vendor/esp32s3/src/rtc_cntl/ext_wakeup1.rs

@@ -0,0 +1,54 @@
+#[doc = "Register `EXT_WAKEUP1` reader"]
+pub type R = crate::R<EXT_WAKEUP1_SPEC>;
+#[doc = "Register `EXT_WAKEUP1` writer"]
+pub type W = crate::W<EXT_WAKEUP1_SPEC>;
+#[doc = "Field `EXT_WAKEUP1_SEL` reader - Bitmap to select RTC pads for ext wakeup1"]
+pub type EXT_WAKEUP1_SEL_R = crate::FieldReader<u32>;
+#[doc = "Field `EXT_WAKEUP1_SEL` writer - Bitmap to select RTC pads for ext wakeup1"]
+pub type EXT_WAKEUP1_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>;
+#[doc = "Field `EXT_WAKEUP1_STATUS_CLR` writer - clear ext wakeup1 status"]
+pub type EXT_WAKEUP1_STATUS_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 0:21 - Bitmap to select RTC pads for ext wakeup1"]
+    #[inline(always)]
+    pub fn ext_wakeup1_sel(&self) -> EXT_WAKEUP1_SEL_R {
+        EXT_WAKEUP1_SEL_R::new(self.bits & 0x003f_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("EXT_WAKEUP1")
+            .field("ext_wakeup1_sel", &self.ext_wakeup1_sel())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:21 - Bitmap to select RTC pads for ext wakeup1"]
+    #[inline(always)]
+    pub fn ext_wakeup1_sel(&mut self) -> EXT_WAKEUP1_SEL_W<EXT_WAKEUP1_SPEC> {
+        EXT_WAKEUP1_SEL_W::new(self, 0)
+    }
+    #[doc = "Bit 22 - clear ext wakeup1 status"]
+    #[inline(always)]
+    pub fn ext_wakeup1_status_clr(&mut self) -> EXT_WAKEUP1_STATUS_CLR_W<EXT_WAKEUP1_SPEC> {
+        EXT_WAKEUP1_STATUS_CLR_W::new(self, 22)
+    }
+}
+#[doc = "configure ext1 wakeup\n\nYou can [`read`](crate::Reg::read) this register and get [`ext_wakeup1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ext_wakeup1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct EXT_WAKEUP1_SPEC;
+impl crate::RegisterSpec for EXT_WAKEUP1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`ext_wakeup1::R`](R) reader structure"]
+impl crate::Readable for EXT_WAKEUP1_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`ext_wakeup1::W`](W) writer structure"]
+impl crate::Writable for EXT_WAKEUP1_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets EXT_WAKEUP1 to value 0"]
+impl crate::Resettable for EXT_WAKEUP1_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_cntl/ext_wakeup1_status.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `EXT_WAKEUP1_STATUS` reader"]
+pub type R = crate::R<EXT_WAKEUP1_STATUS_SPEC>;
+#[doc = "Field `EXT_WAKEUP1_STATUS` reader - ext wakeup1 status"]
+pub type EXT_WAKEUP1_STATUS_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:21 - ext wakeup1 status"]
+    #[inline(always)]
+    pub fn ext_wakeup1_status(&self) -> EXT_WAKEUP1_STATUS_R {
+        EXT_WAKEUP1_STATUS_R::new(self.bits & 0x003f_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("EXT_WAKEUP1_STATUS")
+            .field("ext_wakeup1_status", &self.ext_wakeup1_status())
+            .finish()
+    }
+}
+#[doc = "check ext wakeup1 status\n\nYou can [`read`](crate::Reg::read) this register and get [`ext_wakeup1_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct EXT_WAKEUP1_STATUS_SPEC;
+impl crate::RegisterSpec for EXT_WAKEUP1_STATUS_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`ext_wakeup1_status::R`](R) reader structure"]
+impl crate::Readable for EXT_WAKEUP1_STATUS_SPEC {}
+#[doc = "`reset()` method sets EXT_WAKEUP1_STATUS to value 0"]
+impl crate::Resettable for EXT_WAKEUP1_STATUS_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_cntl/ext_wakeup_conf.rs

@@ -0,0 +1,77 @@
+#[doc = "Register `EXT_WAKEUP_CONF` reader"]
+pub type R = crate::R<EXT_WAKEUP_CONF_SPEC>;
+#[doc = "Register `EXT_WAKEUP_CONF` writer"]
+pub type W = crate::W<EXT_WAKEUP_CONF_SPEC>;
+#[doc = "Field `GPIO_WAKEUP_FILTER` reader - enable filter for gpio wakeup event"]
+pub type GPIO_WAKEUP_FILTER_R = crate::BitReader;
+#[doc = "Field `GPIO_WAKEUP_FILTER` writer - enable filter for gpio wakeup event"]
+pub type GPIO_WAKEUP_FILTER_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `EXT_WAKEUP0_LV` reader - 0: external wakeup at low level, 1: external wakeup at high level"]
+pub type EXT_WAKEUP0_LV_R = crate::BitReader;
+#[doc = "Field `EXT_WAKEUP0_LV` writer - 0: external wakeup at low level, 1: external wakeup at high level"]
+pub type EXT_WAKEUP0_LV_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `EXT_WAKEUP1_LV` reader - 0: external wakeup at low level, 1: external wakeup at high level"]
+pub type EXT_WAKEUP1_LV_R = crate::BitReader;
+#[doc = "Field `EXT_WAKEUP1_LV` writer - 0: external wakeup at low level, 1: external wakeup at high level"]
+pub type EXT_WAKEUP1_LV_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 29 - enable filter for gpio wakeup event"]
+    #[inline(always)]
+    pub fn gpio_wakeup_filter(&self) -> GPIO_WAKEUP_FILTER_R {
+        GPIO_WAKEUP_FILTER_R::new(((self.bits >> 29) & 1) != 0)
+    }
+    #[doc = "Bit 30 - 0: external wakeup at low level, 1: external wakeup at high level"]
+    #[inline(always)]
+    pub fn ext_wakeup0_lv(&self) -> EXT_WAKEUP0_LV_R {
+        EXT_WAKEUP0_LV_R::new(((self.bits >> 30) & 1) != 0)
+    }
+    #[doc = "Bit 31 - 0: external wakeup at low level, 1: external wakeup at high level"]
+    #[inline(always)]
+    pub fn ext_wakeup1_lv(&self) -> EXT_WAKEUP1_LV_R {
+        EXT_WAKEUP1_LV_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("EXT_WAKEUP_CONF")
+            .field("gpio_wakeup_filter", &self.gpio_wakeup_filter())
+            .field("ext_wakeup0_lv", &self.ext_wakeup0_lv())
+            .field("ext_wakeup1_lv", &self.ext_wakeup1_lv())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 29 - enable filter for gpio wakeup event"]
+    #[inline(always)]
+    pub fn gpio_wakeup_filter(&mut self) -> GPIO_WAKEUP_FILTER_W<EXT_WAKEUP_CONF_SPEC> {
+        GPIO_WAKEUP_FILTER_W::new(self, 29)
+    }
+    #[doc = "Bit 30 - 0: external wakeup at low level, 1: external wakeup at high level"]
+    #[inline(always)]
+    pub fn ext_wakeup0_lv(&mut self) -> EXT_WAKEUP0_LV_W<EXT_WAKEUP_CONF_SPEC> {
+        EXT_WAKEUP0_LV_W::new(self, 30)
+    }
+    #[doc = "Bit 31 - 0: external wakeup at low level, 1: external wakeup at high level"]
+    #[inline(always)]
+    pub fn ext_wakeup1_lv(&mut self) -> EXT_WAKEUP1_LV_W<EXT_WAKEUP_CONF_SPEC> {
+        EXT_WAKEUP1_LV_W::new(self, 31)
+    }
+}
+#[doc = "ext wakeup configure\n\nYou can [`read`](crate::Reg::read) this register and get [`ext_wakeup_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ext_wakeup_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct EXT_WAKEUP_CONF_SPEC;
+impl crate::RegisterSpec for EXT_WAKEUP_CONF_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`ext_wakeup_conf::R`](R) reader structure"]
+impl crate::Readable for EXT_WAKEUP_CONF_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`ext_wakeup_conf::W`](W) writer structure"]
+impl crate::Writable for EXT_WAKEUP_CONF_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets EXT_WAKEUP_CONF to value 0"]
+impl crate::Resettable for EXT_WAKEUP_CONF_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_cntl/ext_xtl_conf.rs

@@ -0,0 +1,295 @@
+#[doc = "Register `EXT_XTL_CONF` reader"]
+pub type R = crate::R<EXT_XTL_CONF_SPEC>;
+#[doc = "Register `EXT_XTL_CONF` writer"]
+pub type W = crate::W<EXT_XTL_CONF_SPEC>;
+#[doc = "Field `XTAL32K_WDT_EN` reader - xtal 32k watch dog enable"]
+pub type XTAL32K_WDT_EN_R = crate::BitReader;
+#[doc = "Field `XTAL32K_WDT_EN` writer - xtal 32k watch dog enable"]
+pub type XTAL32K_WDT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `XTAL32K_WDT_CLK_FO` reader - xtal 32k watch dog clock force on"]
+pub type XTAL32K_WDT_CLK_FO_R = crate::BitReader;
+#[doc = "Field `XTAL32K_WDT_CLK_FO` writer - xtal 32k watch dog clock force on"]
+pub type XTAL32K_WDT_CLK_FO_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `XTAL32K_WDT_RESET` reader - xtal 32k watch dog sw reset"]
+pub type XTAL32K_WDT_RESET_R = crate::BitReader;
+#[doc = "Field `XTAL32K_WDT_RESET` writer - xtal 32k watch dog sw reset"]
+pub type XTAL32K_WDT_RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `XTAL32K_EXT_CLK_FO` reader - xtal 32k external xtal clock force on"]
+pub type XTAL32K_EXT_CLK_FO_R = crate::BitReader;
+#[doc = "Field `XTAL32K_EXT_CLK_FO` writer - xtal 32k external xtal clock force on"]
+pub type XTAL32K_EXT_CLK_FO_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `XTAL32K_AUTO_BACKUP` reader - xtal 32k switch to back up clock when xtal is dead"]
+pub type XTAL32K_AUTO_BACKUP_R = crate::BitReader;
+#[doc = "Field `XTAL32K_AUTO_BACKUP` writer - xtal 32k switch to back up clock when xtal is dead"]
+pub type XTAL32K_AUTO_BACKUP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `XTAL32K_AUTO_RESTART` reader - xtal 32k restart xtal when xtal is dead"]
+pub type XTAL32K_AUTO_RESTART_R = crate::BitReader;
+#[doc = "Field `XTAL32K_AUTO_RESTART` writer - xtal 32k restart xtal when xtal is dead"]
+pub type XTAL32K_AUTO_RESTART_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `XTAL32K_AUTO_RETURN` reader - xtal 32k switch back xtal when xtal is restarted"]
+pub type XTAL32K_AUTO_RETURN_R = crate::BitReader;
+#[doc = "Field `XTAL32K_AUTO_RETURN` writer - xtal 32k switch back xtal when xtal is restarted"]
+pub type XTAL32K_AUTO_RETURN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `XTAL32K_XPD_FORCE` reader - Xtal 32k xpd control by sw or fsm"]
+pub type XTAL32K_XPD_FORCE_R = crate::BitReader;
+#[doc = "Field `XTAL32K_XPD_FORCE` writer - Xtal 32k xpd control by sw or fsm"]
+pub type XTAL32K_XPD_FORCE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ENCKINIT_XTAL_32K` reader - apply an internal clock to help xtal 32k to start"]
+pub type ENCKINIT_XTAL_32K_R = crate::BitReader;
+#[doc = "Field `ENCKINIT_XTAL_32K` writer - apply an internal clock to help xtal 32k to start"]
+pub type ENCKINIT_XTAL_32K_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DBUF_XTAL_32K` reader - 0: single-end buffer 1: differential buffer"]
+pub type DBUF_XTAL_32K_R = crate::BitReader;
+#[doc = "Field `DBUF_XTAL_32K` writer - 0: single-end buffer 1: differential buffer"]
+pub type DBUF_XTAL_32K_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DGM_XTAL_32K` reader - xtal_32k gm control"]
+pub type DGM_XTAL_32K_R = crate::FieldReader;
+#[doc = "Field `DGM_XTAL_32K` writer - xtal_32k gm control"]
+pub type DGM_XTAL_32K_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `DRES_XTAL_32K` reader - DRES_XTAL_32K"]
+pub type DRES_XTAL_32K_R = crate::FieldReader;
+#[doc = "Field `DRES_XTAL_32K` writer - DRES_XTAL_32K"]
+pub type DRES_XTAL_32K_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `XPD_XTAL_32K` reader - XPD_XTAL_32K"]
+pub type XPD_XTAL_32K_R = crate::BitReader;
+#[doc = "Field `XPD_XTAL_32K` writer - XPD_XTAL_32K"]
+pub type XPD_XTAL_32K_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DAC_XTAL_32K` reader - DAC_XTAL_32K"]
+pub type DAC_XTAL_32K_R = crate::FieldReader;
+#[doc = "Field `DAC_XTAL_32K` writer - DAC_XTAL_32K"]
+pub type DAC_XTAL_32K_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `WDT_STATE` reader - state of 32k_wdt"]
+pub type WDT_STATE_R = crate::FieldReader;
+#[doc = "Field `XTAL32K_GPIO_SEL` reader - XTAL_32K sel. 0: external XTAL_32K, 1: CLK from RTC pad X32P_C"]
+pub type XTAL32K_GPIO_SEL_R = crate::BitReader;
+#[doc = "Field `XTAL32K_GPIO_SEL` writer - XTAL_32K sel. 0: external XTAL_32K, 1: CLK from RTC pad X32P_C"]
+pub type XTAL32K_GPIO_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `XTL_EXT_CTR_LV` reader - 0: power down XTAL at high level, 1: power down XTAL at low level"]
+pub type XTL_EXT_CTR_LV_R = crate::BitReader;
+#[doc = "Field `XTL_EXT_CTR_LV` writer - 0: power down XTAL at high level, 1: power down XTAL at low level"]
+pub type XTL_EXT_CTR_LV_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `XTL_EXT_CTR_EN` reader - Reserved register"]
+pub type XTL_EXT_CTR_EN_R = crate::BitReader;
+#[doc = "Field `XTL_EXT_CTR_EN` writer - Reserved register"]
+pub type XTL_EXT_CTR_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - xtal 32k watch dog enable"]
+    #[inline(always)]
+    pub fn xtal32k_wdt_en(&self) -> XTAL32K_WDT_EN_R {
+        XTAL32K_WDT_EN_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - xtal 32k watch dog clock force on"]
+    #[inline(always)]
+    pub fn xtal32k_wdt_clk_fo(&self) -> XTAL32K_WDT_CLK_FO_R {
+        XTAL32K_WDT_CLK_FO_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - xtal 32k watch dog sw reset"]
+    #[inline(always)]
+    pub fn xtal32k_wdt_reset(&self) -> XTAL32K_WDT_RESET_R {
+        XTAL32K_WDT_RESET_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - xtal 32k external xtal clock force on"]
+    #[inline(always)]
+    pub fn xtal32k_ext_clk_fo(&self) -> XTAL32K_EXT_CLK_FO_R {
+        XTAL32K_EXT_CLK_FO_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - xtal 32k switch to back up clock when xtal is dead"]
+    #[inline(always)]
+    pub fn xtal32k_auto_backup(&self) -> XTAL32K_AUTO_BACKUP_R {
+        XTAL32K_AUTO_BACKUP_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - xtal 32k restart xtal when xtal is dead"]
+    #[inline(always)]
+    pub fn xtal32k_auto_restart(&self) -> XTAL32K_AUTO_RESTART_R {
+        XTAL32K_AUTO_RESTART_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - xtal 32k switch back xtal when xtal is restarted"]
+    #[inline(always)]
+    pub fn xtal32k_auto_return(&self) -> XTAL32K_AUTO_RETURN_R {
+        XTAL32K_AUTO_RETURN_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - Xtal 32k xpd control by sw or fsm"]
+    #[inline(always)]
+    pub fn xtal32k_xpd_force(&self) -> XTAL32K_XPD_FORCE_R {
+        XTAL32K_XPD_FORCE_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - apply an internal clock to help xtal 32k to start"]
+    #[inline(always)]
+    pub fn enckinit_xtal_32k(&self) -> ENCKINIT_XTAL_32K_R {
+        ENCKINIT_XTAL_32K_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - 0: single-end buffer 1: differential buffer"]
+    #[inline(always)]
+    pub fn dbuf_xtal_32k(&self) -> DBUF_XTAL_32K_R {
+        DBUF_XTAL_32K_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bits 10:12 - xtal_32k gm control"]
+    #[inline(always)]
+    pub fn dgm_xtal_32k(&self) -> DGM_XTAL_32K_R {
+        DGM_XTAL_32K_R::new(((self.bits >> 10) & 7) as u8)
+    }
+    #[doc = "Bits 13:15 - DRES_XTAL_32K"]
+    #[inline(always)]
+    pub fn dres_xtal_32k(&self) -> DRES_XTAL_32K_R {
+        DRES_XTAL_32K_R::new(((self.bits >> 13) & 7) as u8)
+    }
+    #[doc = "Bit 16 - XPD_XTAL_32K"]
+    #[inline(always)]
+    pub fn xpd_xtal_32k(&self) -> XPD_XTAL_32K_R {
+        XPD_XTAL_32K_R::new(((self.bits >> 16) & 1) != 0)
+    }
+    #[doc = "Bits 17:19 - DAC_XTAL_32K"]
+    #[inline(always)]
+    pub fn dac_xtal_32k(&self) -> DAC_XTAL_32K_R {
+        DAC_XTAL_32K_R::new(((self.bits >> 17) & 7) as u8)
+    }
+    #[doc = "Bits 20:22 - state of 32k_wdt"]
+    #[inline(always)]
+    pub fn wdt_state(&self) -> WDT_STATE_R {
+        WDT_STATE_R::new(((self.bits >> 20) & 7) as u8)
+    }
+    #[doc = "Bit 23 - XTAL_32K sel. 0: external XTAL_32K, 1: CLK from RTC pad X32P_C"]
+    #[inline(always)]
+    pub fn xtal32k_gpio_sel(&self) -> XTAL32K_GPIO_SEL_R {
+        XTAL32K_GPIO_SEL_R::new(((self.bits >> 23) & 1) != 0)
+    }
+    #[doc = "Bit 30 - 0: power down XTAL at high level, 1: power down XTAL at low level"]
+    #[inline(always)]
+    pub fn xtl_ext_ctr_lv(&self) -> XTL_EXT_CTR_LV_R {
+        XTL_EXT_CTR_LV_R::new(((self.bits >> 30) & 1) != 0)
+    }
+    #[doc = "Bit 31 - Reserved register"]
+    #[inline(always)]
+    pub fn xtl_ext_ctr_en(&self) -> XTL_EXT_CTR_EN_R {
+        XTL_EXT_CTR_EN_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("EXT_XTL_CONF")
+            .field("xtal32k_wdt_en", &self.xtal32k_wdt_en())
+            .field("xtal32k_wdt_clk_fo", &self.xtal32k_wdt_clk_fo())
+            .field("xtal32k_wdt_reset", &self.xtal32k_wdt_reset())
+            .field("xtal32k_ext_clk_fo", &self.xtal32k_ext_clk_fo())
+            .field("xtal32k_auto_backup", &self.xtal32k_auto_backup())
+            .field("xtal32k_auto_restart", &self.xtal32k_auto_restart())
+            .field("xtal32k_auto_return", &self.xtal32k_auto_return())
+            .field("xtal32k_xpd_force", &self.xtal32k_xpd_force())
+            .field("enckinit_xtal_32k", &self.enckinit_xtal_32k())
+            .field("dbuf_xtal_32k", &self.dbuf_xtal_32k())
+            .field("dgm_xtal_32k", &self.dgm_xtal_32k())
+            .field("dres_xtal_32k", &self.dres_xtal_32k())
+            .field("xpd_xtal_32k", &self.xpd_xtal_32k())
+            .field("dac_xtal_32k", &self.dac_xtal_32k())
+            .field("wdt_state", &self.wdt_state())
+            .field("xtal32k_gpio_sel", &self.xtal32k_gpio_sel())
+            .field("xtl_ext_ctr_lv", &self.xtl_ext_ctr_lv())
+            .field("xtl_ext_ctr_en", &self.xtl_ext_ctr_en())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - xtal 32k watch dog enable"]
+    #[inline(always)]
+    pub fn xtal32k_wdt_en(&mut self) -> XTAL32K_WDT_EN_W<EXT_XTL_CONF_SPEC> {
+        XTAL32K_WDT_EN_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - xtal 32k watch dog clock force on"]
+    #[inline(always)]
+    pub fn xtal32k_wdt_clk_fo(&mut self) -> XTAL32K_WDT_CLK_FO_W<EXT_XTL_CONF_SPEC> {
+        XTAL32K_WDT_CLK_FO_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - xtal 32k watch dog sw reset"]
+    #[inline(always)]
+    pub fn xtal32k_wdt_reset(&mut self) -> XTAL32K_WDT_RESET_W<EXT_XTL_CONF_SPEC> {
+        XTAL32K_WDT_RESET_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - xtal 32k external xtal clock force on"]
+    #[inline(always)]
+    pub fn xtal32k_ext_clk_fo(&mut self) -> XTAL32K_EXT_CLK_FO_W<EXT_XTL_CONF_SPEC> {
+        XTAL32K_EXT_CLK_FO_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - xtal 32k switch to back up clock when xtal is dead"]
+    #[inline(always)]
+    pub fn xtal32k_auto_backup(&mut self) -> XTAL32K_AUTO_BACKUP_W<EXT_XTL_CONF_SPEC> {
+        XTAL32K_AUTO_BACKUP_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - xtal 32k restart xtal when xtal is dead"]
+    #[inline(always)]
+    pub fn xtal32k_auto_restart(&mut self) -> XTAL32K_AUTO_RESTART_W<EXT_XTL_CONF_SPEC> {
+        XTAL32K_AUTO_RESTART_W::new(self, 5)
+    }
+    #[doc = "Bit 6 - xtal 32k switch back xtal when xtal is restarted"]
+    #[inline(always)]
+    pub fn xtal32k_auto_return(&mut self) -> XTAL32K_AUTO_RETURN_W<EXT_XTL_CONF_SPEC> {
+        XTAL32K_AUTO_RETURN_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - Xtal 32k xpd control by sw or fsm"]
+    #[inline(always)]
+    pub fn xtal32k_xpd_force(&mut self) -> XTAL32K_XPD_FORCE_W<EXT_XTL_CONF_SPEC> {
+        XTAL32K_XPD_FORCE_W::new(self, 7)
+    }
+    #[doc = "Bit 8 - apply an internal clock to help xtal 32k to start"]
+    #[inline(always)]
+    pub fn enckinit_xtal_32k(&mut self) -> ENCKINIT_XTAL_32K_W<EXT_XTL_CONF_SPEC> {
+        ENCKINIT_XTAL_32K_W::new(self, 8)
+    }
+    #[doc = "Bit 9 - 0: single-end buffer 1: differential buffer"]
+    #[inline(always)]
+    pub fn dbuf_xtal_32k(&mut self) -> DBUF_XTAL_32K_W<EXT_XTL_CONF_SPEC> {
+        DBUF_XTAL_32K_W::new(self, 9)
+    }
+    #[doc = "Bits 10:12 - xtal_32k gm control"]
+    #[inline(always)]
+    pub fn dgm_xtal_32k(&mut self) -> DGM_XTAL_32K_W<EXT_XTL_CONF_SPEC> {
+        DGM_XTAL_32K_W::new(self, 10)
+    }
+    #[doc = "Bits 13:15 - DRES_XTAL_32K"]
+    #[inline(always)]
+    pub fn dres_xtal_32k(&mut self) -> DRES_XTAL_32K_W<EXT_XTL_CONF_SPEC> {
+        DRES_XTAL_32K_W::new(self, 13)
+    }
+    #[doc = "Bit 16 - XPD_XTAL_32K"]
+    #[inline(always)]
+    pub fn xpd_xtal_32k(&mut self) -> XPD_XTAL_32K_W<EXT_XTL_CONF_SPEC> {
+        XPD_XTAL_32K_W::new(self, 16)
+    }
+    #[doc = "Bits 17:19 - DAC_XTAL_32K"]
+    #[inline(always)]
+    pub fn dac_xtal_32k(&mut self) -> DAC_XTAL_32K_W<EXT_XTL_CONF_SPEC> {
+        DAC_XTAL_32K_W::new(self, 17)
+    }
+    #[doc = "Bit 23 - XTAL_32K sel. 0: external XTAL_32K, 1: CLK from RTC pad X32P_C"]
+    #[inline(always)]
+    pub fn xtal32k_gpio_sel(&mut self) -> XTAL32K_GPIO_SEL_W<EXT_XTL_CONF_SPEC> {
+        XTAL32K_GPIO_SEL_W::new(self, 23)
+    }
+    #[doc = "Bit 30 - 0: power down XTAL at high level, 1: power down XTAL at low level"]
+    #[inline(always)]
+    pub fn xtl_ext_ctr_lv(&mut self) -> XTL_EXT_CTR_LV_W<EXT_XTL_CONF_SPEC> {
+        XTL_EXT_CTR_LV_W::new(self, 30)
+    }
+    #[doc = "Bit 31 - Reserved register"]
+    #[inline(always)]
+    pub fn xtl_ext_ctr_en(&mut self) -> XTL_EXT_CTR_EN_W<EXT_XTL_CONF_SPEC> {
+        XTL_EXT_CTR_EN_W::new(self, 31)
+    }
+}
+#[doc = "Reserved register\n\nYou can [`read`](crate::Reg::read) this register and get [`ext_xtl_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ext_xtl_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct EXT_XTL_CONF_SPEC;
+impl crate::RegisterSpec for EXT_XTL_CONF_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`ext_xtl_conf::R`](R) reader structure"]
+impl crate::Readable for EXT_XTL_CONF_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`ext_xtl_conf::W`](W) writer structure"]
+impl crate::Writable for EXT_XTL_CONF_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets EXT_XTL_CONF to value 0x0006_6c80"]
+impl crate::Resettable for EXT_XTL_CONF_SPEC {
+    const RESET_VALUE: u32 = 0x0006_6c80;
+}

vendor/esp32s3/src/rtc_cntl/fib_sel.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `FIB_SEL` reader"]
+pub type R = crate::R<FIB_SEL_SPEC>;
+#[doc = "Register `FIB_SEL` writer"]
+pub type W = crate::W<FIB_SEL_SPEC>;
+#[doc = "Field `FIB_SEL` reader - No public"]
+pub type FIB_SEL_R = crate::FieldReader;
+#[doc = "Field `FIB_SEL` writer - No public"]
+pub type FIB_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+impl R {
+    #[doc = "Bits 0:2 - No public"]
+    #[inline(always)]
+    pub fn fib_sel(&self) -> FIB_SEL_R {
+        FIB_SEL_R::new((self.bits & 7) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("FIB_SEL")
+            .field("fib_sel", &self.fib_sel())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:2 - No public"]
+    #[inline(always)]
+    pub fn fib_sel(&mut self) -> FIB_SEL_W<FIB_SEL_SPEC> {
+        FIB_SEL_W::new(self, 0)
+    }
+}
+#[doc = "No public\n\nYou can [`read`](crate::Reg::read) this register and get [`fib_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fib_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct FIB_SEL_SPEC;
+impl crate::RegisterSpec for FIB_SEL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`fib_sel::R`](R) reader structure"]
+impl crate::Readable for FIB_SEL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`fib_sel::W`](W) writer structure"]
+impl crate::Writable for FIB_SEL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets FIB_SEL to value 0x07"]
+impl crate::Resettable for FIB_SEL_SPEC {
+    const RESET_VALUE: u32 = 0x07;
+}

vendor/esp32s3/src/rtc_cntl/int_clr.rs

@@ -0,0 +1,172 @@
+#[doc = "Register `INT_CLR` writer"]
+pub type W = crate::W<INT_CLR_SPEC>;
+#[doc = "Field `SLP_WAKEUP` writer - Clear sleep wakeup interrupt state"]
+pub type SLP_WAKEUP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `SLP_REJECT` writer - Clear sleep reject interrupt state"]
+pub type SLP_REJECT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `SDIO_IDLE` writer - Clear SDIO idle interrupt state"]
+pub type SDIO_IDLE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `WDT` writer - Clear RTC WDT interrupt state"]
+pub type WDT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TOUCH_SCAN_DONE` writer - clear touch scan done interrupt raw"]
+pub type TOUCH_SCAN_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `ULP_CP` writer - Clear ULP-coprocessor interrupt state"]
+pub type ULP_CP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TOUCH_DONE` writer - Clear touch done interrupt state"]
+pub type TOUCH_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TOUCH_ACTIVE` writer - Clear touch active interrupt state"]
+pub type TOUCH_ACTIVE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TOUCH_INACTIVE` writer - Clear touch inactive interrupt state"]
+pub type TOUCH_INACTIVE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `BROWN_OUT` writer - Clear brown out interrupt state"]
+pub type BROWN_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `MAIN_TIMER` writer - Clear RTC main timer interrupt state"]
+pub type MAIN_TIMER_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `SARADC1` writer - Clear saradc1 interrupt state"]
+pub type SARADC1_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TSENS` writer - Clear tsens interrupt state"]
+pub type TSENS_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `COCPU` writer - Clear riscV cocpu interrupt state"]
+pub type COCPU_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `SARADC2` writer - Clear saradc2 interrupt state"]
+pub type SARADC2_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `SWD` writer - Clear super watch dog interrupt state"]
+pub type SWD_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `XTAL32K_DEAD` writer - Clear RTC WDT interrupt state"]
+pub type XTAL32K_DEAD_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `COCPU_TRAP` writer - Clear cocpu trap interrupt state"]
+pub type COCPU_TRAP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TOUCH_TIMEOUT` writer - Clear touch timeout interrupt state"]
+pub type TOUCH_TIMEOUT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `GLITCH_DET` writer - Clear glitch det interrupt state"]
+pub type GLITCH_DET_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TOUCH_APPROACH_LOOP_DONE` writer - cleartouch approach mode loop interrupt state"]
+pub type TOUCH_APPROACH_LOOP_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "(not readable)")
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Clear sleep wakeup interrupt state"]
+    #[inline(always)]
+    pub fn slp_wakeup(&mut self) -> SLP_WAKEUP_W<INT_CLR_SPEC> {
+        SLP_WAKEUP_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - Clear sleep reject interrupt state"]
+    #[inline(always)]
+    pub fn slp_reject(&mut self) -> SLP_REJECT_W<INT_CLR_SPEC> {
+        SLP_REJECT_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - Clear SDIO idle interrupt state"]
+    #[inline(always)]
+    pub fn sdio_idle(&mut self) -> SDIO_IDLE_W<INT_CLR_SPEC> {
+        SDIO_IDLE_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - Clear RTC WDT interrupt state"]
+    #[inline(always)]
+    pub fn wdt(&mut self) -> WDT_W<INT_CLR_SPEC> {
+        WDT_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - clear touch scan done interrupt raw"]
+    #[inline(always)]
+    pub fn touch_scan_done(&mut self) -> TOUCH_SCAN_DONE_W<INT_CLR_SPEC> {
+        TOUCH_SCAN_DONE_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - Clear ULP-coprocessor interrupt state"]
+    #[inline(always)]
+    pub fn ulp_cp(&mut self) -> ULP_CP_W<INT_CLR_SPEC> {
+        ULP_CP_W::new(self, 5)
+    }
+    #[doc = "Bit 6 - Clear touch done interrupt state"]
+    #[inline(always)]
+    pub fn touch_done(&mut self) -> TOUCH_DONE_W<INT_CLR_SPEC> {
+        TOUCH_DONE_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - Clear touch active interrupt state"]
+    #[inline(always)]
+    pub fn touch_active(&mut self) -> TOUCH_ACTIVE_W<INT_CLR_SPEC> {
+        TOUCH_ACTIVE_W::new(self, 7)
+    }
+    #[doc = "Bit 8 - Clear touch inactive interrupt state"]
+    #[inline(always)]
+    pub fn touch_inactive(&mut self) -> TOUCH_INACTIVE_W<INT_CLR_SPEC> {
+        TOUCH_INACTIVE_W::new(self, 8)
+    }
+    #[doc = "Bit 9 - Clear brown out interrupt state"]
+    #[inline(always)]
+    pub fn brown_out(&mut self) -> BROWN_OUT_W<INT_CLR_SPEC> {
+        BROWN_OUT_W::new(self, 9)
+    }
+    #[doc = "Bit 10 - Clear RTC main timer interrupt state"]
+    #[inline(always)]
+    pub fn main_timer(&mut self) -> MAIN_TIMER_W<INT_CLR_SPEC> {
+        MAIN_TIMER_W::new(self, 10)
+    }
+    #[doc = "Bit 11 - Clear saradc1 interrupt state"]
+    #[inline(always)]
+    pub fn saradc1(&mut self) -> SARADC1_W<INT_CLR_SPEC> {
+        SARADC1_W::new(self, 11)
+    }
+    #[doc = "Bit 12 - Clear tsens interrupt state"]
+    #[inline(always)]
+    pub fn tsens(&mut self) -> TSENS_W<INT_CLR_SPEC> {
+        TSENS_W::new(self, 12)
+    }
+    #[doc = "Bit 13 - Clear riscV cocpu interrupt state"]
+    #[inline(always)]
+    pub fn cocpu(&mut self) -> COCPU_W<INT_CLR_SPEC> {
+        COCPU_W::new(self, 13)
+    }
+    #[doc = "Bit 14 - Clear saradc2 interrupt state"]
+    #[inline(always)]
+    pub fn saradc2(&mut self) -> SARADC2_W<INT_CLR_SPEC> {
+        SARADC2_W::new(self, 14)
+    }
+    #[doc = "Bit 15 - Clear super watch dog interrupt state"]
+    #[inline(always)]
+    pub fn swd(&mut self) -> SWD_W<INT_CLR_SPEC> {
+        SWD_W::new(self, 15)
+    }
+    #[doc = "Bit 16 - Clear RTC WDT interrupt state"]
+    #[inline(always)]
+    pub fn xtal32k_dead(&mut self) -> XTAL32K_DEAD_W<INT_CLR_SPEC> {
+        XTAL32K_DEAD_W::new(self, 16)
+    }
+    #[doc = "Bit 17 - Clear cocpu trap interrupt state"]
+    #[inline(always)]
+    pub fn cocpu_trap(&mut self) -> COCPU_TRAP_W<INT_CLR_SPEC> {
+        COCPU_TRAP_W::new(self, 17)
+    }
+    #[doc = "Bit 18 - Clear touch timeout interrupt state"]
+    #[inline(always)]
+    pub fn touch_timeout(&mut self) -> TOUCH_TIMEOUT_W<INT_CLR_SPEC> {
+        TOUCH_TIMEOUT_W::new(self, 18)
+    }
+    #[doc = "Bit 19 - Clear glitch det interrupt state"]
+    #[inline(always)]
+    pub fn glitch_det(&mut self) -> GLITCH_DET_W<INT_CLR_SPEC> {
+        GLITCH_DET_W::new(self, 19)
+    }
+    #[doc = "Bit 20 - cleartouch approach mode loop interrupt state"]
+    #[inline(always)]
+    pub fn touch_approach_loop_done(&mut self) -> TOUCH_APPROACH_LOOP_DONE_W<INT_CLR_SPEC> {
+        TOUCH_APPROACH_LOOP_DONE_W::new(self, 20)
+    }
+}
+#[doc = "rtc interrupt register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct INT_CLR_SPEC;
+impl crate::RegisterSpec for INT_CLR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
+impl crate::Writable for INT_CLR_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x001f_ffff;
+}
+#[doc = "`reset()` method sets INT_CLR to value 0"]
+impl crate::Resettable for INT_CLR_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_cntl/int_ena.rs

@@ -0,0 +1,347 @@
+#[doc = "Register `INT_ENA` reader"]
+pub type R = crate::R<INT_ENA_SPEC>;
+#[doc = "Register `INT_ENA` writer"]
+pub type W = crate::W<INT_ENA_SPEC>;
+#[doc = "Field `SLP_WAKEUP` reader - enable sleep wakeup interrupt"]
+pub type SLP_WAKEUP_R = crate::BitReader;
+#[doc = "Field `SLP_WAKEUP` writer - enable sleep wakeup interrupt"]
+pub type SLP_WAKEUP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SLP_REJECT` reader - enable sleep reject interrupt"]
+pub type SLP_REJECT_R = crate::BitReader;
+#[doc = "Field `SLP_REJECT` writer - enable sleep reject interrupt"]
+pub type SLP_REJECT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SDIO_IDLE` reader - enable SDIO idle interrupt"]
+pub type SDIO_IDLE_R = crate::BitReader;
+#[doc = "Field `SDIO_IDLE` writer - enable SDIO idle interrupt"]
+pub type SDIO_IDLE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `WDT` reader - enable RTC WDT interrupt"]
+pub type WDT_R = crate::BitReader;
+#[doc = "Field `WDT` writer - enable RTC WDT interrupt"]
+pub type WDT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TOUCH_SCAN_DONE` reader - enable touch scan done interrupt"]
+pub type TOUCH_SCAN_DONE_R = crate::BitReader;
+#[doc = "Field `TOUCH_SCAN_DONE` writer - enable touch scan done interrupt"]
+pub type TOUCH_SCAN_DONE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ULP_CP` reader - enable ULP-coprocessor interrupt"]
+pub type ULP_CP_R = crate::BitReader;
+#[doc = "Field `ULP_CP` writer - enable ULP-coprocessor interrupt"]
+pub type ULP_CP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TOUCH_DONE` reader - enable touch done interrupt"]
+pub type TOUCH_DONE_R = crate::BitReader;
+#[doc = "Field `TOUCH_DONE` writer - enable touch done interrupt"]
+pub type TOUCH_DONE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TOUCH_ACTIVE` reader - enable touch active interrupt"]
+pub type TOUCH_ACTIVE_R = crate::BitReader;
+#[doc = "Field `TOUCH_ACTIVE` writer - enable touch active interrupt"]
+pub type TOUCH_ACTIVE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TOUCH_INACTIVE` reader - enable touch inactive interrupt"]
+pub type TOUCH_INACTIVE_R = crate::BitReader;
+#[doc = "Field `TOUCH_INACTIVE` writer - enable touch inactive interrupt"]
+pub type TOUCH_INACTIVE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `BROWN_OUT` reader - enable brown out interrupt"]
+pub type BROWN_OUT_R = crate::BitReader;
+#[doc = "Field `BROWN_OUT` writer - enable brown out interrupt"]
+pub type BROWN_OUT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `MAIN_TIMER` reader - enable RTC main timer interrupt"]
+pub type MAIN_TIMER_R = crate::BitReader;
+#[doc = "Field `MAIN_TIMER` writer - enable RTC main timer interrupt"]
+pub type MAIN_TIMER_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SARADC1` reader - enable saradc1 interrupt"]
+pub type SARADC1_R = crate::BitReader;
+#[doc = "Field `SARADC1` writer - enable saradc1 interrupt"]
+pub type SARADC1_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TSENS` reader - enable tsens interrupt"]
+pub type TSENS_R = crate::BitReader;
+#[doc = "Field `TSENS` writer - enable tsens interrupt"]
+pub type TSENS_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `COCPU` reader - enable riscV cocpu interrupt"]
+pub type COCPU_R = crate::BitReader;
+#[doc = "Field `COCPU` writer - enable riscV cocpu interrupt"]
+pub type COCPU_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SARADC2` reader - enable saradc2 interrupt"]
+pub type SARADC2_R = crate::BitReader;
+#[doc = "Field `SARADC2` writer - enable saradc2 interrupt"]
+pub type SARADC2_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SWD` reader - enable super watch dog interrupt"]
+pub type SWD_R = crate::BitReader;
+#[doc = "Field `SWD` writer - enable super watch dog interrupt"]
+pub type SWD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `XTAL32K_DEAD` reader - enable xtal32k_dead interrupt"]
+pub type XTAL32K_DEAD_R = crate::BitReader;
+#[doc = "Field `XTAL32K_DEAD` writer - enable xtal32k_dead interrupt"]
+pub type XTAL32K_DEAD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `COCPU_TRAP` reader - enable cocpu trap interrupt"]
+pub type COCPU_TRAP_R = crate::BitReader;
+#[doc = "Field `COCPU_TRAP` writer - enable cocpu trap interrupt"]
+pub type COCPU_TRAP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TOUCH_TIMEOUT` reader - enable touch timeout interrupt"]
+pub type TOUCH_TIMEOUT_R = crate::BitReader;
+#[doc = "Field `TOUCH_TIMEOUT` writer - enable touch timeout interrupt"]
+pub type TOUCH_TIMEOUT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `GLITCH_DET` reader - enbale gitch det interrupt"]
+pub type GLITCH_DET_R = crate::BitReader;
+#[doc = "Field `GLITCH_DET` writer - enbale gitch det interrupt"]
+pub type GLITCH_DET_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TOUCH_APPROACH_LOOP_DONE` reader - touch approach mode loop interrupt"]
+pub type TOUCH_APPROACH_LOOP_DONE_R = crate::BitReader;
+#[doc = "Field `TOUCH_APPROACH_LOOP_DONE` writer - touch approach mode loop interrupt"]
+pub type TOUCH_APPROACH_LOOP_DONE_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - enable sleep wakeup interrupt"]
+    #[inline(always)]
+    pub fn slp_wakeup(&self) -> SLP_WAKEUP_R {
+        SLP_WAKEUP_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - enable sleep reject interrupt"]
+    #[inline(always)]
+    pub fn slp_reject(&self) -> SLP_REJECT_R {
+        SLP_REJECT_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - enable SDIO idle interrupt"]
+    #[inline(always)]
+    pub fn sdio_idle(&self) -> SDIO_IDLE_R {
+        SDIO_IDLE_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - enable RTC WDT interrupt"]
+    #[inline(always)]
+    pub fn wdt(&self) -> WDT_R {
+        WDT_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - enable touch scan done interrupt"]
+    #[inline(always)]
+    pub fn touch_scan_done(&self) -> TOUCH_SCAN_DONE_R {
+        TOUCH_SCAN_DONE_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - enable ULP-coprocessor interrupt"]
+    #[inline(always)]
+    pub fn ulp_cp(&self) -> ULP_CP_R {
+        ULP_CP_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - enable touch done interrupt"]
+    #[inline(always)]
+    pub fn touch_done(&self) -> TOUCH_DONE_R {
+        TOUCH_DONE_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - enable touch active interrupt"]
+    #[inline(always)]
+    pub fn touch_active(&self) -> TOUCH_ACTIVE_R {
+        TOUCH_ACTIVE_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - enable touch inactive interrupt"]
+    #[inline(always)]
+    pub fn touch_inactive(&self) -> TOUCH_INACTIVE_R {
+        TOUCH_INACTIVE_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - enable brown out interrupt"]
+    #[inline(always)]
+    pub fn brown_out(&self) -> BROWN_OUT_R {
+        BROWN_OUT_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 10 - enable RTC main timer interrupt"]
+    #[inline(always)]
+    pub fn main_timer(&self) -> MAIN_TIMER_R {
+        MAIN_TIMER_R::new(((self.bits >> 10) & 1) != 0)
+    }
+    #[doc = "Bit 11 - enable saradc1 interrupt"]
+    #[inline(always)]
+    pub fn saradc1(&self) -> SARADC1_R {
+        SARADC1_R::new(((self.bits >> 11) & 1) != 0)
+    }
+    #[doc = "Bit 12 - enable tsens interrupt"]
+    #[inline(always)]
+    pub fn tsens(&self) -> TSENS_R {
+        TSENS_R::new(((self.bits >> 12) & 1) != 0)
+    }
+    #[doc = "Bit 13 - enable riscV cocpu interrupt"]
+    #[inline(always)]
+    pub fn cocpu(&self) -> COCPU_R {
+        COCPU_R::new(((self.bits >> 13) & 1) != 0)
+    }
+    #[doc = "Bit 14 - enable saradc2 interrupt"]
+    #[inline(always)]
+    pub fn saradc2(&self) -> SARADC2_R {
+        SARADC2_R::new(((self.bits >> 14) & 1) != 0)
+    }
+    #[doc = "Bit 15 - enable super watch dog interrupt"]
+    #[inline(always)]
+    pub fn swd(&self) -> SWD_R {
+        SWD_R::new(((self.bits >> 15) & 1) != 0)
+    }
+    #[doc = "Bit 16 - enable xtal32k_dead interrupt"]
+    #[inline(always)]
+    pub fn xtal32k_dead(&self) -> XTAL32K_DEAD_R {
+        XTAL32K_DEAD_R::new(((self.bits >> 16) & 1) != 0)
+    }
+    #[doc = "Bit 17 - enable cocpu trap interrupt"]
+    #[inline(always)]
+    pub fn cocpu_trap(&self) -> COCPU_TRAP_R {
+        COCPU_TRAP_R::new(((self.bits >> 17) & 1) != 0)
+    }
+    #[doc = "Bit 18 - enable touch timeout interrupt"]
+    #[inline(always)]
+    pub fn touch_timeout(&self) -> TOUCH_TIMEOUT_R {
+        TOUCH_TIMEOUT_R::new(((self.bits >> 18) & 1) != 0)
+    }
+    #[doc = "Bit 19 - enbale gitch det interrupt"]
+    #[inline(always)]
+    pub fn glitch_det(&self) -> GLITCH_DET_R {
+        GLITCH_DET_R::new(((self.bits >> 19) & 1) != 0)
+    }
+    #[doc = "Bit 20 - touch approach mode loop interrupt"]
+    #[inline(always)]
+    pub fn touch_approach_loop_done(&self) -> TOUCH_APPROACH_LOOP_DONE_R {
+        TOUCH_APPROACH_LOOP_DONE_R::new(((self.bits >> 20) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("INT_ENA")
+            .field("slp_wakeup", &self.slp_wakeup())
+            .field("slp_reject", &self.slp_reject())
+            .field("sdio_idle", &self.sdio_idle())
+            .field("wdt", &self.wdt())
+            .field("touch_scan_done", &self.touch_scan_done())
+            .field("ulp_cp", &self.ulp_cp())
+            .field("touch_done", &self.touch_done())
+            .field("touch_active", &self.touch_active())
+            .field("touch_inactive", &self.touch_inactive())
+            .field("brown_out", &self.brown_out())
+            .field("main_timer", &self.main_timer())
+            .field("saradc1", &self.saradc1())
+            .field("tsens", &self.tsens())
+            .field("cocpu", &self.cocpu())
+            .field("saradc2", &self.saradc2())
+            .field("swd", &self.swd())
+            .field("xtal32k_dead", &self.xtal32k_dead())
+            .field("cocpu_trap", &self.cocpu_trap())
+            .field("touch_timeout", &self.touch_timeout())
+            .field("glitch_det", &self.glitch_det())
+            .field("touch_approach_loop_done", &self.touch_approach_loop_done())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - enable sleep wakeup interrupt"]
+    #[inline(always)]
+    pub fn slp_wakeup(&mut self) -> SLP_WAKEUP_W<INT_ENA_SPEC> {
+        SLP_WAKEUP_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - enable sleep reject interrupt"]
+    #[inline(always)]
+    pub fn slp_reject(&mut self) -> SLP_REJECT_W<INT_ENA_SPEC> {
+        SLP_REJECT_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - enable SDIO idle interrupt"]
+    #[inline(always)]
+    pub fn sdio_idle(&mut self) -> SDIO_IDLE_W<INT_ENA_SPEC> {
+        SDIO_IDLE_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - enable RTC WDT interrupt"]
+    #[inline(always)]
+    pub fn wdt(&mut self) -> WDT_W<INT_ENA_SPEC> {
+        WDT_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - enable touch scan done interrupt"]
+    #[inline(always)]
+    pub fn touch_scan_done(&mut self) -> TOUCH_SCAN_DONE_W<INT_ENA_SPEC> {
+        TOUCH_SCAN_DONE_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - enable ULP-coprocessor interrupt"]
+    #[inline(always)]
+    pub fn ulp_cp(&mut self) -> ULP_CP_W<INT_ENA_SPEC> {
+        ULP_CP_W::new(self, 5)
+    }
+    #[doc = "Bit 6 - enable touch done interrupt"]
+    #[inline(always)]
+    pub fn touch_done(&mut self) -> TOUCH_DONE_W<INT_ENA_SPEC> {
+        TOUCH_DONE_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - enable touch active interrupt"]
+    #[inline(always)]
+    pub fn touch_active(&mut self) -> TOUCH_ACTIVE_W<INT_ENA_SPEC> {
+        TOUCH_ACTIVE_W::new(self, 7)
+    }
+    #[doc = "Bit 8 - enable touch inactive interrupt"]
+    #[inline(always)]
+    pub fn touch_inactive(&mut self) -> TOUCH_INACTIVE_W<INT_ENA_SPEC> {
+        TOUCH_INACTIVE_W::new(self, 8)
+    }
+    #[doc = "Bit 9 - enable brown out interrupt"]
+    #[inline(always)]
+    pub fn brown_out(&mut self) -> BROWN_OUT_W<INT_ENA_SPEC> {
+        BROWN_OUT_W::new(self, 9)
+    }
+    #[doc = "Bit 10 - enable RTC main timer interrupt"]
+    #[inline(always)]
+    pub fn main_timer(&mut self) -> MAIN_TIMER_W<INT_ENA_SPEC> {
+        MAIN_TIMER_W::new(self, 10)
+    }
+    #[doc = "Bit 11 - enable saradc1 interrupt"]
+    #[inline(always)]
+    pub fn saradc1(&mut self) -> SARADC1_W<INT_ENA_SPEC> {
+        SARADC1_W::new(self, 11)
+    }
+    #[doc = "Bit 12 - enable tsens interrupt"]
+    #[inline(always)]
+    pub fn tsens(&mut self) -> TSENS_W<INT_ENA_SPEC> {
+        TSENS_W::new(self, 12)
+    }
+    #[doc = "Bit 13 - enable riscV cocpu interrupt"]
+    #[inline(always)]
+    pub fn cocpu(&mut self) -> COCPU_W<INT_ENA_SPEC> {
+        COCPU_W::new(self, 13)
+    }
+    #[doc = "Bit 14 - enable saradc2 interrupt"]
+    #[inline(always)]
+    pub fn saradc2(&mut self) -> SARADC2_W<INT_ENA_SPEC> {
+        SARADC2_W::new(self, 14)
+    }
+    #[doc = "Bit 15 - enable super watch dog interrupt"]
+    #[inline(always)]
+    pub fn swd(&mut self) -> SWD_W<INT_ENA_SPEC> {
+        SWD_W::new(self, 15)
+    }
+    #[doc = "Bit 16 - enable xtal32k_dead interrupt"]
+    #[inline(always)]
+    pub fn xtal32k_dead(&mut self) -> XTAL32K_DEAD_W<INT_ENA_SPEC> {
+        XTAL32K_DEAD_W::new(self, 16)
+    }
+    #[doc = "Bit 17 - enable cocpu trap interrupt"]
+    #[inline(always)]
+    pub fn cocpu_trap(&mut self) -> COCPU_TRAP_W<INT_ENA_SPEC> {
+        COCPU_TRAP_W::new(self, 17)
+    }
+    #[doc = "Bit 18 - enable touch timeout interrupt"]
+    #[inline(always)]
+    pub fn touch_timeout(&mut self) -> TOUCH_TIMEOUT_W<INT_ENA_SPEC> {
+        TOUCH_TIMEOUT_W::new(self, 18)
+    }
+    #[doc = "Bit 19 - enbale gitch det interrupt"]
+    #[inline(always)]
+    pub fn glitch_det(&mut self) -> GLITCH_DET_W<INT_ENA_SPEC> {
+        GLITCH_DET_W::new(self, 19)
+    }
+    #[doc = "Bit 20 - touch approach mode loop interrupt"]
+    #[inline(always)]
+    pub fn touch_approach_loop_done(&mut self) -> TOUCH_APPROACH_LOOP_DONE_W<INT_ENA_SPEC> {
+        TOUCH_APPROACH_LOOP_DONE_W::new(self, 20)
+    }
+}
+#[doc = "configure rtc interrupt register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct INT_ENA_SPEC;
+impl crate::RegisterSpec for INT_ENA_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"]
+impl crate::Readable for INT_ENA_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"]
+impl crate::Writable for INT_ENA_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets INT_ENA to value 0"]
+impl crate::Resettable for INT_ENA_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_cntl/int_ena_rtc_w1tc.rs

@@ -0,0 +1,174 @@
+#[doc = "Register `INT_ENA_RTC_W1TC` writer"]
+pub type W = crate::W<INT_ENA_RTC_W1TC_SPEC>;
+#[doc = "Field `SLP_WAKEUP` writer - enable sleep wakeup interrupt"]
+pub type SLP_WAKEUP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `SLP_REJECT` writer - enable sleep reject interrupt"]
+pub type SLP_REJECT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `SDIO_IDLE` writer - enable SDIO idle interrupt"]
+pub type SDIO_IDLE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `WDT` writer - enable RTC WDT interrupt"]
+pub type WDT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TOUCH_SCAN_DONE` writer - enable touch scan done interrupt"]
+pub type TOUCH_SCAN_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `ULP_CP` writer - enable ULP-coprocessor interrupt"]
+pub type ULP_CP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TOUCH_DONE` writer - enable touch done interrupt"]
+pub type TOUCH_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TOUCH_ACTIVE` writer - enable touch active interrupt"]
+pub type TOUCH_ACTIVE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TOUCH_INACTIVE` writer - enable touch inactive interrupt"]
+pub type TOUCH_INACTIVE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `BROWN_OUT` writer - enable brown out interrupt"]
+pub type BROWN_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `MAIN_TIMER` writer - enable RTC main timer interrupt"]
+pub type MAIN_TIMER_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `SARADC1` writer - enable saradc1 interrupt"]
+pub type SARADC1_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TSENS` writer - enable tsens interrupt"]
+pub type TSENS_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `COCPU` writer - enable riscV cocpu interrupt"]
+pub type COCPU_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `SARADC2` writer - enable saradc2 interrupt"]
+pub type SARADC2_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `SWD` writer - enable super watch dog interrupt"]
+pub type SWD_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `XTAL32K_DEAD` writer - enable xtal32k_dead interrupt"]
+pub type XTAL32K_DEAD_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `COCPU_TRAP` writer - enable cocpu trap interrupt"]
+pub type COCPU_TRAP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TOUCH_TIMEOUT` writer - enable touch timeout interrupt"]
+pub type TOUCH_TIMEOUT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `GLITCH_DET` writer - enbale gitch det interrupt"]
+pub type GLITCH_DET_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TOUCH_APPROACH_LOOP_DONE` writer - enbale touch approach_loop done interrupt"]
+pub type TOUCH_APPROACH_LOOP_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for crate::generic::Reg<INT_ENA_RTC_W1TC_SPEC> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "(not readable)")
+    }
+}
+impl W {
+    #[doc = "Bit 0 - enable sleep wakeup interrupt"]
+    #[inline(always)]
+    pub fn slp_wakeup(&mut self) -> SLP_WAKEUP_W<INT_ENA_RTC_W1TC_SPEC> {
+        SLP_WAKEUP_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - enable sleep reject interrupt"]
+    #[inline(always)]
+    pub fn slp_reject(&mut self) -> SLP_REJECT_W<INT_ENA_RTC_W1TC_SPEC> {
+        SLP_REJECT_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - enable SDIO idle interrupt"]
+    #[inline(always)]
+    pub fn sdio_idle(&mut self) -> SDIO_IDLE_W<INT_ENA_RTC_W1TC_SPEC> {
+        SDIO_IDLE_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - enable RTC WDT interrupt"]
+    #[inline(always)]
+    pub fn wdt(&mut self) -> WDT_W<INT_ENA_RTC_W1TC_SPEC> {
+        WDT_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - enable touch scan done interrupt"]
+    #[inline(always)]
+    pub fn touch_scan_done(&mut self) -> TOUCH_SCAN_DONE_W<INT_ENA_RTC_W1TC_SPEC> {
+        TOUCH_SCAN_DONE_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - enable ULP-coprocessor interrupt"]
+    #[inline(always)]
+    pub fn ulp_cp(&mut self) -> ULP_CP_W<INT_ENA_RTC_W1TC_SPEC> {
+        ULP_CP_W::new(self, 5)
+    }
+    #[doc = "Bit 6 - enable touch done interrupt"]
+    #[inline(always)]
+    pub fn touch_done(&mut self) -> TOUCH_DONE_W<INT_ENA_RTC_W1TC_SPEC> {
+        TOUCH_DONE_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - enable touch active interrupt"]
+    #[inline(always)]
+    pub fn touch_active(&mut self) -> TOUCH_ACTIVE_W<INT_ENA_RTC_W1TC_SPEC> {
+        TOUCH_ACTIVE_W::new(self, 7)
+    }
+    #[doc = "Bit 8 - enable touch inactive interrupt"]
+    #[inline(always)]
+    pub fn touch_inactive(&mut self) -> TOUCH_INACTIVE_W<INT_ENA_RTC_W1TC_SPEC> {
+        TOUCH_INACTIVE_W::new(self, 8)
+    }
+    #[doc = "Bit 9 - enable brown out interrupt"]
+    #[inline(always)]
+    pub fn brown_out(&mut self) -> BROWN_OUT_W<INT_ENA_RTC_W1TC_SPEC> {
+        BROWN_OUT_W::new(self, 9)
+    }
+    #[doc = "Bit 10 - enable RTC main timer interrupt"]
+    #[inline(always)]
+    pub fn main_timer(&mut self) -> MAIN_TIMER_W<INT_ENA_RTC_W1TC_SPEC> {
+        MAIN_TIMER_W::new(self, 10)
+    }
+    #[doc = "Bit 11 - enable saradc1 interrupt"]
+    #[inline(always)]
+    pub fn saradc1(&mut self) -> SARADC1_W<INT_ENA_RTC_W1TC_SPEC> {
+        SARADC1_W::new(self, 11)
+    }
+    #[doc = "Bit 12 - enable tsens interrupt"]
+    #[inline(always)]
+    pub fn tsens(&mut self) -> TSENS_W<INT_ENA_RTC_W1TC_SPEC> {
+        TSENS_W::new(self, 12)
+    }
+    #[doc = "Bit 13 - enable riscV cocpu interrupt"]
+    #[inline(always)]
+    pub fn cocpu(&mut self) -> COCPU_W<INT_ENA_RTC_W1TC_SPEC> {
+        COCPU_W::new(self, 13)
+    }
+    #[doc = "Bit 14 - enable saradc2 interrupt"]
+    #[inline(always)]
+    pub fn saradc2(&mut self) -> SARADC2_W<INT_ENA_RTC_W1TC_SPEC> {
+        SARADC2_W::new(self, 14)
+    }
+    #[doc = "Bit 15 - enable super watch dog interrupt"]
+    #[inline(always)]
+    pub fn swd(&mut self) -> SWD_W<INT_ENA_RTC_W1TC_SPEC> {
+        SWD_W::new(self, 15)
+    }
+    #[doc = "Bit 16 - enable xtal32k_dead interrupt"]
+    #[inline(always)]
+    pub fn xtal32k_dead(&mut self) -> XTAL32K_DEAD_W<INT_ENA_RTC_W1TC_SPEC> {
+        XTAL32K_DEAD_W::new(self, 16)
+    }
+    #[doc = "Bit 17 - enable cocpu trap interrupt"]
+    #[inline(always)]
+    pub fn cocpu_trap(&mut self) -> COCPU_TRAP_W<INT_ENA_RTC_W1TC_SPEC> {
+        COCPU_TRAP_W::new(self, 17)
+    }
+    #[doc = "Bit 18 - enable touch timeout interrupt"]
+    #[inline(always)]
+    pub fn touch_timeout(&mut self) -> TOUCH_TIMEOUT_W<INT_ENA_RTC_W1TC_SPEC> {
+        TOUCH_TIMEOUT_W::new(self, 18)
+    }
+    #[doc = "Bit 19 - enbale gitch det interrupt"]
+    #[inline(always)]
+    pub fn glitch_det(&mut self) -> GLITCH_DET_W<INT_ENA_RTC_W1TC_SPEC> {
+        GLITCH_DET_W::new(self, 19)
+    }
+    #[doc = "Bit 20 - enbale touch approach_loop done interrupt"]
+    #[inline(always)]
+    pub fn touch_approach_loop_done(
+        &mut self,
+    ) -> TOUCH_APPROACH_LOOP_DONE_W<INT_ENA_RTC_W1TC_SPEC> {
+        TOUCH_APPROACH_LOOP_DONE_W::new(self, 20)
+    }
+}
+#[doc = "oneset clr rtc interrupt enable\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena_rtc_w1tc::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct INT_ENA_RTC_W1TC_SPEC;
+impl crate::RegisterSpec for INT_ENA_RTC_W1TC_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [`int_ena_rtc_w1tc::W`](W) writer structure"]
+impl crate::Writable for INT_ENA_RTC_W1TC_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x001f_ffff;
+}
+#[doc = "`reset()` method sets INT_ENA_RTC_W1TC to value 0"]
+impl crate::Resettable for INT_ENA_RTC_W1TC_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_cntl/int_ena_rtc_w1ts.rs

@@ -0,0 +1,174 @@
+#[doc = "Register `INT_ENA_RTC_W1TS` writer"]
+pub type W = crate::W<INT_ENA_RTC_W1TS_SPEC>;
+#[doc = "Field `SLP_WAKEUP` writer - enable sleep wakeup interrupt"]
+pub type SLP_WAKEUP_W<'a, REG> = crate::BitWriter1S<'a, REG>;
+#[doc = "Field `SLP_REJECT` writer - enable sleep reject interrupt"]
+pub type SLP_REJECT_W<'a, REG> = crate::BitWriter1S<'a, REG>;
+#[doc = "Field `SDIO_IDLE` writer - enable SDIO idle interrupt"]
+pub type SDIO_IDLE_W<'a, REG> = crate::BitWriter1S<'a, REG>;
+#[doc = "Field `WDT` writer - enable RTC WDT interrupt"]
+pub type WDT_W<'a, REG> = crate::BitWriter1S<'a, REG>;
+#[doc = "Field `TOUCH_SCAN_DONE` writer - enable touch scan done interrupt"]
+pub type TOUCH_SCAN_DONE_W<'a, REG> = crate::BitWriter1S<'a, REG>;
+#[doc = "Field `ULP_CP` writer - enable ULP-coprocessor interrupt"]
+pub type ULP_CP_W<'a, REG> = crate::BitWriter1S<'a, REG>;
+#[doc = "Field `TOUCH_DONE` writer - enable touch done interrupt"]
+pub type TOUCH_DONE_W<'a, REG> = crate::BitWriter1S<'a, REG>;
+#[doc = "Field `TOUCH_ACTIVE` writer - enable touch active interrupt"]
+pub type TOUCH_ACTIVE_W<'a, REG> = crate::BitWriter1S<'a, REG>;
+#[doc = "Field `TOUCH_INACTIVE` writer - enable touch inactive interrupt"]
+pub type TOUCH_INACTIVE_W<'a, REG> = crate::BitWriter1S<'a, REG>;
+#[doc = "Field `BROWN_OUT` writer - enable brown out interrupt"]
+pub type BROWN_OUT_W<'a, REG> = crate::BitWriter1S<'a, REG>;
+#[doc = "Field `MAIN_TIMER` writer - enable RTC main timer interrupt"]
+pub type MAIN_TIMER_W<'a, REG> = crate::BitWriter1S<'a, REG>;
+#[doc = "Field `SARADC1` writer - enable saradc1 interrupt"]
+pub type SARADC1_W<'a, REG> = crate::BitWriter1S<'a, REG>;
+#[doc = "Field `TSENS` writer - enable tsens interrupt"]
+pub type TSENS_W<'a, REG> = crate::BitWriter1S<'a, REG>;
+#[doc = "Field `COCPU` writer - enable riscV cocpu interrupt"]
+pub type COCPU_W<'a, REG> = crate::BitWriter1S<'a, REG>;
+#[doc = "Field `SARADC2` writer - enable saradc2 interrupt"]
+pub type SARADC2_W<'a, REG> = crate::BitWriter1S<'a, REG>;
+#[doc = "Field `SWD` writer - enable super watch dog interrupt"]
+pub type SWD_W<'a, REG> = crate::BitWriter1S<'a, REG>;
+#[doc = "Field `XTAL32K_DEAD` writer - enable xtal32k_dead interrupt"]
+pub type XTAL32K_DEAD_W<'a, REG> = crate::BitWriter1S<'a, REG>;
+#[doc = "Field `COCPU_TRAP` writer - enable cocpu trap interrupt"]
+pub type COCPU_TRAP_W<'a, REG> = crate::BitWriter1S<'a, REG>;
+#[doc = "Field `TOUCH_TIMEOUT` writer - enable touch timeout interrupt"]
+pub type TOUCH_TIMEOUT_W<'a, REG> = crate::BitWriter1S<'a, REG>;
+#[doc = "Field `GLITCH_DET` writer - enbale gitch det interrupt"]
+pub type GLITCH_DET_W<'a, REG> = crate::BitWriter1S<'a, REG>;
+#[doc = "Field `TOUCH_APPROACH_LOOP_DONE` writer - enbale touch approach_loop done interrupt"]
+pub type TOUCH_APPROACH_LOOP_DONE_W<'a, REG> = crate::BitWriter1S<'a, REG>;
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for crate::generic::Reg<INT_ENA_RTC_W1TS_SPEC> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "(not readable)")
+    }
+}
+impl W {
+    #[doc = "Bit 0 - enable sleep wakeup interrupt"]
+    #[inline(always)]
+    pub fn slp_wakeup(&mut self) -> SLP_WAKEUP_W<INT_ENA_RTC_W1TS_SPEC> {
+        SLP_WAKEUP_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - enable sleep reject interrupt"]
+    #[inline(always)]
+    pub fn slp_reject(&mut self) -> SLP_REJECT_W<INT_ENA_RTC_W1TS_SPEC> {
+        SLP_REJECT_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - enable SDIO idle interrupt"]
+    #[inline(always)]
+    pub fn sdio_idle(&mut self) -> SDIO_IDLE_W<INT_ENA_RTC_W1TS_SPEC> {
+        SDIO_IDLE_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - enable RTC WDT interrupt"]
+    #[inline(always)]
+    pub fn wdt(&mut self) -> WDT_W<INT_ENA_RTC_W1TS_SPEC> {
+        WDT_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - enable touch scan done interrupt"]
+    #[inline(always)]
+    pub fn touch_scan_done(&mut self) -> TOUCH_SCAN_DONE_W<INT_ENA_RTC_W1TS_SPEC> {
+        TOUCH_SCAN_DONE_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - enable ULP-coprocessor interrupt"]
+    #[inline(always)]
+    pub fn ulp_cp(&mut self) -> ULP_CP_W<INT_ENA_RTC_W1TS_SPEC> {
+        ULP_CP_W::new(self, 5)
+    }
+    #[doc = "Bit 6 - enable touch done interrupt"]
+    #[inline(always)]
+    pub fn touch_done(&mut self) -> TOUCH_DONE_W<INT_ENA_RTC_W1TS_SPEC> {
+        TOUCH_DONE_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - enable touch active interrupt"]
+    #[inline(always)]
+    pub fn touch_active(&mut self) -> TOUCH_ACTIVE_W<INT_ENA_RTC_W1TS_SPEC> {
+        TOUCH_ACTIVE_W::new(self, 7)
+    }
+    #[doc = "Bit 8 - enable touch inactive interrupt"]
+    #[inline(always)]
+    pub fn touch_inactive(&mut self) -> TOUCH_INACTIVE_W<INT_ENA_RTC_W1TS_SPEC> {
+        TOUCH_INACTIVE_W::new(self, 8)
+    }
+    #[doc = "Bit 9 - enable brown out interrupt"]
+    #[inline(always)]
+    pub fn brown_out(&mut self) -> BROWN_OUT_W<INT_ENA_RTC_W1TS_SPEC> {
+        BROWN_OUT_W::new(self, 9)
+    }
+    #[doc = "Bit 10 - enable RTC main timer interrupt"]
+    #[inline(always)]
+    pub fn main_timer(&mut self) -> MAIN_TIMER_W<INT_ENA_RTC_W1TS_SPEC> {
+        MAIN_TIMER_W::new(self, 10)
+    }
+    #[doc = "Bit 11 - enable saradc1 interrupt"]
+    #[inline(always)]
+    pub fn saradc1(&mut self) -> SARADC1_W<INT_ENA_RTC_W1TS_SPEC> {
+        SARADC1_W::new(self, 11)
+    }
+    #[doc = "Bit 12 - enable tsens interrupt"]
+    #[inline(always)]
+    pub fn tsens(&mut self) -> TSENS_W<INT_ENA_RTC_W1TS_SPEC> {
+        TSENS_W::new(self, 12)
+    }
+    #[doc = "Bit 13 - enable riscV cocpu interrupt"]
+    #[inline(always)]
+    pub fn cocpu(&mut self) -> COCPU_W<INT_ENA_RTC_W1TS_SPEC> {
+        COCPU_W::new(self, 13)
+    }
+    #[doc = "Bit 14 - enable saradc2 interrupt"]
+    #[inline(always)]
+    pub fn saradc2(&mut self) -> SARADC2_W<INT_ENA_RTC_W1TS_SPEC> {
+        SARADC2_W::new(self, 14)
+    }
+    #[doc = "Bit 15 - enable super watch dog interrupt"]
+    #[inline(always)]
+    pub fn swd(&mut self) -> SWD_W<INT_ENA_RTC_W1TS_SPEC> {
+        SWD_W::new(self, 15)
+    }
+    #[doc = "Bit 16 - enable xtal32k_dead interrupt"]
+    #[inline(always)]
+    pub fn xtal32k_dead(&mut self) -> XTAL32K_DEAD_W<INT_ENA_RTC_W1TS_SPEC> {
+        XTAL32K_DEAD_W::new(self, 16)
+    }
+    #[doc = "Bit 17 - enable cocpu trap interrupt"]
+    #[inline(always)]
+    pub fn cocpu_trap(&mut self) -> COCPU_TRAP_W<INT_ENA_RTC_W1TS_SPEC> {
+        COCPU_TRAP_W::new(self, 17)
+    }
+    #[doc = "Bit 18 - enable touch timeout interrupt"]
+    #[inline(always)]
+    pub fn touch_timeout(&mut self) -> TOUCH_TIMEOUT_W<INT_ENA_RTC_W1TS_SPEC> {
+        TOUCH_TIMEOUT_W::new(self, 18)
+    }
+    #[doc = "Bit 19 - enbale gitch det interrupt"]
+    #[inline(always)]
+    pub fn glitch_det(&mut self) -> GLITCH_DET_W<INT_ENA_RTC_W1TS_SPEC> {
+        GLITCH_DET_W::new(self, 19)
+    }
+    #[doc = "Bit 20 - enbale touch approach_loop done interrupt"]
+    #[inline(always)]
+    pub fn touch_approach_loop_done(
+        &mut self,
+    ) -> TOUCH_APPROACH_LOOP_DONE_W<INT_ENA_RTC_W1TS_SPEC> {
+        TOUCH_APPROACH_LOOP_DONE_W::new(self, 20)
+    }
+}
+#[doc = "oneset rtc interrupt\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena_rtc_w1ts::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct INT_ENA_RTC_W1TS_SPEC;
+impl crate::RegisterSpec for INT_ENA_RTC_W1TS_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [`int_ena_rtc_w1ts::W`](W) writer structure"]
+impl crate::Writable for INT_ENA_RTC_W1TS_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x001f_ffff;
+}
+#[doc = "`reset()` method sets INT_ENA_RTC_W1TS to value 0"]
+impl crate::Resettable for INT_ENA_RTC_W1TS_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_cntl/int_raw.rs

@@ -0,0 +1,207 @@
+#[doc = "Register `INT_RAW` reader"]
+pub type R = crate::R<INT_RAW_SPEC>;
+#[doc = "Register `INT_RAW` writer"]
+pub type W = crate::W<INT_RAW_SPEC>;
+#[doc = "Field `SLP_WAKEUP` reader - sleep wakeup interrupt raw"]
+pub type SLP_WAKEUP_R = crate::BitReader;
+#[doc = "Field `SLP_REJECT` reader - sleep reject interrupt raw"]
+pub type SLP_REJECT_R = crate::BitReader;
+#[doc = "Field `SDIO_IDLE` reader - SDIO idle interrupt raw"]
+pub type SDIO_IDLE_R = crate::BitReader;
+#[doc = "Field `WDT` reader - RTC WDT interrupt raw"]
+pub type WDT_R = crate::BitReader;
+#[doc = "Field `TOUCH_SCAN_DONE` reader - enable touch scan done interrupt raw"]
+pub type TOUCH_SCAN_DONE_R = crate::BitReader;
+#[doc = "Field `ULP_CP` reader - ULP-coprocessor interrupt raw"]
+pub type ULP_CP_R = crate::BitReader;
+#[doc = "Field `TOUCH_DONE` reader - touch interrupt raw"]
+pub type TOUCH_DONE_R = crate::BitReader;
+#[doc = "Field `TOUCH_ACTIVE` reader - touch active interrupt raw"]
+pub type TOUCH_ACTIVE_R = crate::BitReader;
+#[doc = "Field `TOUCH_INACTIVE` reader - touch inactive interrupt raw"]
+pub type TOUCH_INACTIVE_R = crate::BitReader;
+#[doc = "Field `BROWN_OUT` reader - brown out interrupt raw"]
+pub type BROWN_OUT_R = crate::BitReader;
+#[doc = "Field `MAIN_TIMER` reader - RTC main timer interrupt raw"]
+pub type MAIN_TIMER_R = crate::BitReader;
+#[doc = "Field `SARADC1` reader - saradc1 interrupt raw"]
+pub type SARADC1_R = crate::BitReader;
+#[doc = "Field `TSENS` reader - tsens interrupt raw"]
+pub type TSENS_R = crate::BitReader;
+#[doc = "Field `COCPU` reader - riscV cocpu interrupt raw"]
+pub type COCPU_R = crate::BitReader;
+#[doc = "Field `SARADC2` reader - saradc2 interrupt raw"]
+pub type SARADC2_R = crate::BitReader;
+#[doc = "Field `SWD` reader - super watch dog interrupt raw"]
+pub type SWD_R = crate::BitReader;
+#[doc = "Field `XTAL32K_DEAD` reader - xtal32k dead detection interrupt raw"]
+pub type XTAL32K_DEAD_R = crate::BitReader;
+#[doc = "Field `COCPU_TRAP` reader - cocpu trap interrupt raw"]
+pub type COCPU_TRAP_R = crate::BitReader;
+#[doc = "Field `TOUCH_TIMEOUT` reader - touch timeout interrupt raw"]
+pub type TOUCH_TIMEOUT_R = crate::BitReader;
+#[doc = "Field `GLITCH_DET` reader - glitch_det_interrupt_raw"]
+pub type GLITCH_DET_R = crate::BitReader;
+#[doc = "Field `TOUCH_APPROACH_LOOP_DONE` reader - touch approach mode loop interrupt raw"]
+pub type TOUCH_APPROACH_LOOP_DONE_R = crate::BitReader;
+#[doc = "Field `TOUCH_APPROACH_LOOP_DONE` writer - touch approach mode loop interrupt raw"]
+pub type TOUCH_APPROACH_LOOP_DONE_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - sleep wakeup interrupt raw"]
+    #[inline(always)]
+    pub fn slp_wakeup(&self) -> SLP_WAKEUP_R {
+        SLP_WAKEUP_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - sleep reject interrupt raw"]
+    #[inline(always)]
+    pub fn slp_reject(&self) -> SLP_REJECT_R {
+        SLP_REJECT_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - SDIO idle interrupt raw"]
+    #[inline(always)]
+    pub fn sdio_idle(&self) -> SDIO_IDLE_R {
+        SDIO_IDLE_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - RTC WDT interrupt raw"]
+    #[inline(always)]
+    pub fn wdt(&self) -> WDT_R {
+        WDT_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - enable touch scan done interrupt raw"]
+    #[inline(always)]
+    pub fn touch_scan_done(&self) -> TOUCH_SCAN_DONE_R {
+        TOUCH_SCAN_DONE_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - ULP-coprocessor interrupt raw"]
+    #[inline(always)]
+    pub fn ulp_cp(&self) -> ULP_CP_R {
+        ULP_CP_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - touch interrupt raw"]
+    #[inline(always)]
+    pub fn touch_done(&self) -> TOUCH_DONE_R {
+        TOUCH_DONE_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - touch active interrupt raw"]
+    #[inline(always)]
+    pub fn touch_active(&self) -> TOUCH_ACTIVE_R {
+        TOUCH_ACTIVE_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - touch inactive interrupt raw"]
+    #[inline(always)]
+    pub fn touch_inactive(&self) -> TOUCH_INACTIVE_R {
+        TOUCH_INACTIVE_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - brown out interrupt raw"]
+    #[inline(always)]
+    pub fn brown_out(&self) -> BROWN_OUT_R {
+        BROWN_OUT_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 10 - RTC main timer interrupt raw"]
+    #[inline(always)]
+    pub fn main_timer(&self) -> MAIN_TIMER_R {
+        MAIN_TIMER_R::new(((self.bits >> 10) & 1) != 0)
+    }
+    #[doc = "Bit 11 - saradc1 interrupt raw"]
+    #[inline(always)]
+    pub fn saradc1(&self) -> SARADC1_R {
+        SARADC1_R::new(((self.bits >> 11) & 1) != 0)
+    }
+    #[doc = "Bit 12 - tsens interrupt raw"]
+    #[inline(always)]
+    pub fn tsens(&self) -> TSENS_R {
+        TSENS_R::new(((self.bits >> 12) & 1) != 0)
+    }
+    #[doc = "Bit 13 - riscV cocpu interrupt raw"]
+    #[inline(always)]
+    pub fn cocpu(&self) -> COCPU_R {
+        COCPU_R::new(((self.bits >> 13) & 1) != 0)
+    }
+    #[doc = "Bit 14 - saradc2 interrupt raw"]
+    #[inline(always)]
+    pub fn saradc2(&self) -> SARADC2_R {
+        SARADC2_R::new(((self.bits >> 14) & 1) != 0)
+    }
+    #[doc = "Bit 15 - super watch dog interrupt raw"]
+    #[inline(always)]
+    pub fn swd(&self) -> SWD_R {
+        SWD_R::new(((self.bits >> 15) & 1) != 0)
+    }
+    #[doc = "Bit 16 - xtal32k dead detection interrupt raw"]
+    #[inline(always)]
+    pub fn xtal32k_dead(&self) -> XTAL32K_DEAD_R {
+        XTAL32K_DEAD_R::new(((self.bits >> 16) & 1) != 0)
+    }
+    #[doc = "Bit 17 - cocpu trap interrupt raw"]
+    #[inline(always)]
+    pub fn cocpu_trap(&self) -> COCPU_TRAP_R {
+        COCPU_TRAP_R::new(((self.bits >> 17) & 1) != 0)
+    }
+    #[doc = "Bit 18 - touch timeout interrupt raw"]
+    #[inline(always)]
+    pub fn touch_timeout(&self) -> TOUCH_TIMEOUT_R {
+        TOUCH_TIMEOUT_R::new(((self.bits >> 18) & 1) != 0)
+    }
+    #[doc = "Bit 19 - glitch_det_interrupt_raw"]
+    #[inline(always)]
+    pub fn glitch_det(&self) -> GLITCH_DET_R {
+        GLITCH_DET_R::new(((self.bits >> 19) & 1) != 0)
+    }
+    #[doc = "Bit 20 - touch approach mode loop interrupt raw"]
+    #[inline(always)]
+    pub fn touch_approach_loop_done(&self) -> TOUCH_APPROACH_LOOP_DONE_R {
+        TOUCH_APPROACH_LOOP_DONE_R::new(((self.bits >> 20) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("INT_RAW")
+            .field("slp_wakeup", &self.slp_wakeup())
+            .field("slp_reject", &self.slp_reject())
+            .field("sdio_idle", &self.sdio_idle())
+            .field("wdt", &self.wdt())
+            .field("touch_scan_done", &self.touch_scan_done())
+            .field("ulp_cp", &self.ulp_cp())
+            .field("touch_done", &self.touch_done())
+            .field("touch_active", &self.touch_active())
+            .field("touch_inactive", &self.touch_inactive())
+            .field("brown_out", &self.brown_out())
+            .field("main_timer", &self.main_timer())
+            .field("saradc1", &self.saradc1())
+            .field("tsens", &self.tsens())
+            .field("cocpu", &self.cocpu())
+            .field("saradc2", &self.saradc2())
+            .field("swd", &self.swd())
+            .field("xtal32k_dead", &self.xtal32k_dead())
+            .field("cocpu_trap", &self.cocpu_trap())
+            .field("touch_timeout", &self.touch_timeout())
+            .field("glitch_det", &self.glitch_det())
+            .field("touch_approach_loop_done", &self.touch_approach_loop_done())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 20 - touch approach mode loop interrupt raw"]
+    #[inline(always)]
+    pub fn touch_approach_loop_done(&mut self) -> TOUCH_APPROACH_LOOP_DONE_W<INT_RAW_SPEC> {
+        TOUCH_APPROACH_LOOP_DONE_W::new(self, 20)
+    }
+}
+#[doc = "rtc interrupt register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_raw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_raw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct INT_RAW_SPEC;
+impl crate::RegisterSpec for INT_RAW_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"]
+impl crate::Readable for INT_RAW_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`int_raw::W`](W) writer structure"]
+impl crate::Writable for INT_RAW_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets INT_RAW to value 0"]
+impl crate::Resettable for INT_RAW_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_cntl/int_st.rs

@@ -0,0 +1,190 @@
+#[doc = "Register `INT_ST` reader"]
+pub type R = crate::R<INT_ST_SPEC>;
+#[doc = "Field `SLP_WAKEUP` reader - sleep wakeup interrupt state"]
+pub type SLP_WAKEUP_R = crate::BitReader;
+#[doc = "Field `SLP_REJECT` reader - sleep reject interrupt state"]
+pub type SLP_REJECT_R = crate::BitReader;
+#[doc = "Field `SDIO_IDLE` reader - SDIO idle interrupt state"]
+pub type SDIO_IDLE_R = crate::BitReader;
+#[doc = "Field `WDT` reader - RTC WDT interrupt state"]
+pub type WDT_R = crate::BitReader;
+#[doc = "Field `TOUCH_SCAN_DONE` reader - enable touch scan done interrupt raw"]
+pub type TOUCH_SCAN_DONE_R = crate::BitReader;
+#[doc = "Field `ULP_CP` reader - ULP-coprocessor interrupt state"]
+pub type ULP_CP_R = crate::BitReader;
+#[doc = "Field `TOUCH_DONE` reader - touch done interrupt state"]
+pub type TOUCH_DONE_R = crate::BitReader;
+#[doc = "Field `TOUCH_ACTIVE` reader - touch active interrupt state"]
+pub type TOUCH_ACTIVE_R = crate::BitReader;
+#[doc = "Field `TOUCH_INACTIVE` reader - touch inactive interrupt state"]
+pub type TOUCH_INACTIVE_R = crate::BitReader;
+#[doc = "Field `BROWN_OUT` reader - brown out interrupt state"]
+pub type BROWN_OUT_R = crate::BitReader;
+#[doc = "Field `MAIN_TIMER` reader - RTC main timer interrupt state"]
+pub type MAIN_TIMER_R = crate::BitReader;
+#[doc = "Field `SARADC1` reader - saradc1 interrupt state"]
+pub type SARADC1_R = crate::BitReader;
+#[doc = "Field `TSENS` reader - tsens interrupt state"]
+pub type TSENS_R = crate::BitReader;
+#[doc = "Field `COCPU` reader - riscV cocpu interrupt state"]
+pub type COCPU_R = crate::BitReader;
+#[doc = "Field `SARADC2` reader - saradc2 interrupt state"]
+pub type SARADC2_R = crate::BitReader;
+#[doc = "Field `SWD` reader - super watch dog interrupt state"]
+pub type SWD_R = crate::BitReader;
+#[doc = "Field `XTAL32K_DEAD` reader - xtal32k dead detection interrupt state"]
+pub type XTAL32K_DEAD_R = crate::BitReader;
+#[doc = "Field `COCPU_TRAP` reader - cocpu trap interrupt state"]
+pub type COCPU_TRAP_R = crate::BitReader;
+#[doc = "Field `TOUCH_TIMEOUT` reader - Touch timeout interrupt state"]
+pub type TOUCH_TIMEOUT_R = crate::BitReader;
+#[doc = "Field `GLITCH_DET` reader - glitch_det_interrupt state"]
+pub type GLITCH_DET_R = crate::BitReader;
+#[doc = "Field `TOUCH_APPROACH_LOOP_DONE` reader - touch approach mode loop interrupt state"]
+pub type TOUCH_APPROACH_LOOP_DONE_R = crate::BitReader;
+impl R {
+    #[doc = "Bit 0 - sleep wakeup interrupt state"]
+    #[inline(always)]
+    pub fn slp_wakeup(&self) -> SLP_WAKEUP_R {
+        SLP_WAKEUP_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - sleep reject interrupt state"]
+    #[inline(always)]
+    pub fn slp_reject(&self) -> SLP_REJECT_R {
+        SLP_REJECT_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - SDIO idle interrupt state"]
+    #[inline(always)]
+    pub fn sdio_idle(&self) -> SDIO_IDLE_R {
+        SDIO_IDLE_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - RTC WDT interrupt state"]
+    #[inline(always)]
+    pub fn wdt(&self) -> WDT_R {
+        WDT_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - enable touch scan done interrupt raw"]
+    #[inline(always)]
+    pub fn touch_scan_done(&self) -> TOUCH_SCAN_DONE_R {
+        TOUCH_SCAN_DONE_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - ULP-coprocessor interrupt state"]
+    #[inline(always)]
+    pub fn ulp_cp(&self) -> ULP_CP_R {
+        ULP_CP_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - touch done interrupt state"]
+    #[inline(always)]
+    pub fn touch_done(&self) -> TOUCH_DONE_R {
+        TOUCH_DONE_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - touch active interrupt state"]
+    #[inline(always)]
+    pub fn touch_active(&self) -> TOUCH_ACTIVE_R {
+        TOUCH_ACTIVE_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - touch inactive interrupt state"]
+    #[inline(always)]
+    pub fn touch_inactive(&self) -> TOUCH_INACTIVE_R {
+        TOUCH_INACTIVE_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - brown out interrupt state"]
+    #[inline(always)]
+    pub fn brown_out(&self) -> BROWN_OUT_R {
+        BROWN_OUT_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 10 - RTC main timer interrupt state"]
+    #[inline(always)]
+    pub fn main_timer(&self) -> MAIN_TIMER_R {
+        MAIN_TIMER_R::new(((self.bits >> 10) & 1) != 0)
+    }
+    #[doc = "Bit 11 - saradc1 interrupt state"]
+    #[inline(always)]
+    pub fn saradc1(&self) -> SARADC1_R {
+        SARADC1_R::new(((self.bits >> 11) & 1) != 0)
+    }
+    #[doc = "Bit 12 - tsens interrupt state"]
+    #[inline(always)]
+    pub fn tsens(&self) -> TSENS_R {
+        TSENS_R::new(((self.bits >> 12) & 1) != 0)
+    }
+    #[doc = "Bit 13 - riscV cocpu interrupt state"]
+    #[inline(always)]
+    pub fn cocpu(&self) -> COCPU_R {
+        COCPU_R::new(((self.bits >> 13) & 1) != 0)
+    }
+    #[doc = "Bit 14 - saradc2 interrupt state"]
+    #[inline(always)]
+    pub fn saradc2(&self) -> SARADC2_R {
+        SARADC2_R::new(((self.bits >> 14) & 1) != 0)
+    }
+    #[doc = "Bit 15 - super watch dog interrupt state"]
+    #[inline(always)]
+    pub fn swd(&self) -> SWD_R {
+        SWD_R::new(((self.bits >> 15) & 1) != 0)
+    }
+    #[doc = "Bit 16 - xtal32k dead detection interrupt state"]
+    #[inline(always)]
+    pub fn xtal32k_dead(&self) -> XTAL32K_DEAD_R {
+        XTAL32K_DEAD_R::new(((self.bits >> 16) & 1) != 0)
+    }
+    #[doc = "Bit 17 - cocpu trap interrupt state"]
+    #[inline(always)]
+    pub fn cocpu_trap(&self) -> COCPU_TRAP_R {
+        COCPU_TRAP_R::new(((self.bits >> 17) & 1) != 0)
+    }
+    #[doc = "Bit 18 - Touch timeout interrupt state"]
+    #[inline(always)]
+    pub fn touch_timeout(&self) -> TOUCH_TIMEOUT_R {
+        TOUCH_TIMEOUT_R::new(((self.bits >> 18) & 1) != 0)
+    }
+    #[doc = "Bit 19 - glitch_det_interrupt state"]
+    #[inline(always)]
+    pub fn glitch_det(&self) -> GLITCH_DET_R {
+        GLITCH_DET_R::new(((self.bits >> 19) & 1) != 0)
+    }
+    #[doc = "Bit 20 - touch approach mode loop interrupt state"]
+    #[inline(always)]
+    pub fn touch_approach_loop_done(&self) -> TOUCH_APPROACH_LOOP_DONE_R {
+        TOUCH_APPROACH_LOOP_DONE_R::new(((self.bits >> 20) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("INT_ST")
+            .field("slp_wakeup", &self.slp_wakeup())
+            .field("slp_reject", &self.slp_reject())
+            .field("sdio_idle", &self.sdio_idle())
+            .field("wdt", &self.wdt())
+            .field("touch_scan_done", &self.touch_scan_done())
+            .field("ulp_cp", &self.ulp_cp())
+            .field("touch_done", &self.touch_done())
+            .field("touch_active", &self.touch_active())
+            .field("touch_inactive", &self.touch_inactive())
+            .field("brown_out", &self.brown_out())
+            .field("main_timer", &self.main_timer())
+            .field("saradc1", &self.saradc1())
+            .field("tsens", &self.tsens())
+            .field("cocpu", &self.cocpu())
+            .field("saradc2", &self.saradc2())
+            .field("swd", &self.swd())
+            .field("xtal32k_dead", &self.xtal32k_dead())
+            .field("cocpu_trap", &self.cocpu_trap())
+            .field("touch_timeout", &self.touch_timeout())
+            .field("glitch_det", &self.glitch_det())
+            .field("touch_approach_loop_done", &self.touch_approach_loop_done())
+            .finish()
+    }
+}
+#[doc = "rtc interrupt register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct INT_ST_SPEC;
+impl crate::RegisterSpec for INT_ST_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`int_st::R`](R) reader structure"]
+impl crate::Readable for INT_ST_SPEC {}
+#[doc = "`reset()` method sets INT_ST to value 0"]
+impl crate::Resettable for INT_ST_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_cntl/low_power_st.rs

@@ -0,0 +1,246 @@
+#[doc = "Register `LOW_POWER_ST` reader"]
+pub type R = crate::R<LOW_POWER_ST_SPEC>;
+#[doc = "Field `XPD_ROM0` reader - rom0 power down"]
+pub type XPD_ROM0_R = crate::BitReader;
+#[doc = "Field `XPD_DIG_DCDC` reader - External DCDC power down"]
+pub type XPD_DIG_DCDC_R = crate::BitReader;
+#[doc = "Field `PERI_ISO` reader - rtc peripheral iso"]
+pub type PERI_ISO_R = crate::BitReader;
+#[doc = "Field `XPD_RTC_PERI` reader - rtc peripheral power down"]
+pub type XPD_RTC_PERI_R = crate::BitReader;
+#[doc = "Field `WIFI_ISO` reader - wifi iso"]
+pub type WIFI_ISO_R = crate::BitReader;
+#[doc = "Field `XPD_WIFI` reader - wifi wrap power down"]
+pub type XPD_WIFI_R = crate::BitReader;
+#[doc = "Field `DIG_ISO` reader - digital wrap iso"]
+pub type DIG_ISO_R = crate::BitReader;
+#[doc = "Field `XPD_DIG` reader - digital wrap power down"]
+pub type XPD_DIG_R = crate::BitReader;
+#[doc = "Field `TOUCH_STATE_START` reader - touch should start to work"]
+pub type TOUCH_STATE_START_R = crate::BitReader;
+#[doc = "Field `TOUCH_STATE_SWITCH` reader - touch is about to working. Switch rtc main state"]
+pub type TOUCH_STATE_SWITCH_R = crate::BitReader;
+#[doc = "Field `TOUCH_STATE_SLP` reader - touch is in sleep state"]
+pub type TOUCH_STATE_SLP_R = crate::BitReader;
+#[doc = "Field `TOUCH_STATE_DONE` reader - touch is done"]
+pub type TOUCH_STATE_DONE_R = crate::BitReader;
+#[doc = "Field `COCPU_STATE_START` reader - ulp/cocpu should start to work"]
+pub type COCPU_STATE_START_R = crate::BitReader;
+#[doc = "Field `COCPU_STATE_SWITCH` reader - ulp/cocpu is about to working. Switch rtc main state"]
+pub type COCPU_STATE_SWITCH_R = crate::BitReader;
+#[doc = "Field `COCPU_STATE_SLP` reader - ulp/cocpu is in sleep state"]
+pub type COCPU_STATE_SLP_R = crate::BitReader;
+#[doc = "Field `COCPU_STATE_DONE` reader - ulp/cocpu is done"]
+pub type COCPU_STATE_DONE_R = crate::BitReader;
+#[doc = "Field `MAIN_STATE_XTAL_ISO` reader - no use any more"]
+pub type MAIN_STATE_XTAL_ISO_R = crate::BitReader;
+#[doc = "Field `MAIN_STATE_PLL_ON` reader - rtc main state machine is in states that pll should be running"]
+pub type MAIN_STATE_PLL_ON_R = crate::BitReader;
+#[doc = "Field `RDY_FOR_WAKEUP` reader - rtc is ready to receive wake up trigger from wake up source"]
+pub type RDY_FOR_WAKEUP_R = crate::BitReader;
+#[doc = "Field `MAIN_STATE_WAIT_END` reader - rtc main state machine has been waited for some cycles"]
+pub type MAIN_STATE_WAIT_END_R = crate::BitReader;
+#[doc = "Field `IN_WAKEUP_STATE` reader - rtc main state machine is in the states of wakeup process"]
+pub type IN_WAKEUP_STATE_R = crate::BitReader;
+#[doc = "Field `IN_LOW_POWER_STATE` reader - rtc main state machine is in the states of low power"]
+pub type IN_LOW_POWER_STATE_R = crate::BitReader;
+#[doc = "Field `MAIN_STATE_IN_WAIT_8M` reader - rtc main state machine is in wait 8m state"]
+pub type MAIN_STATE_IN_WAIT_8M_R = crate::BitReader;
+#[doc = "Field `MAIN_STATE_IN_WAIT_PLL` reader - rtc main state machine is in wait pll state"]
+pub type MAIN_STATE_IN_WAIT_PLL_R = crate::BitReader;
+#[doc = "Field `MAIN_STATE_IN_WAIT_XTL` reader - rtc main state machine is in wait xtal state"]
+pub type MAIN_STATE_IN_WAIT_XTL_R = crate::BitReader;
+#[doc = "Field `MAIN_STATE_IN_SLP` reader - rtc main state machine is in sleep state"]
+pub type MAIN_STATE_IN_SLP_R = crate::BitReader;
+#[doc = "Field `MAIN_STATE_IN_IDLE` reader - rtc main state machine is in idle state"]
+pub type MAIN_STATE_IN_IDLE_R = crate::BitReader;
+#[doc = "Field `MAIN_STATE` reader - rtc main state machine status"]
+pub type MAIN_STATE_R = crate::FieldReader;
+impl R {
+    #[doc = "Bit 0 - rom0 power down"]
+    #[inline(always)]
+    pub fn xpd_rom0(&self) -> XPD_ROM0_R {
+        XPD_ROM0_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 2 - External DCDC power down"]
+    #[inline(always)]
+    pub fn xpd_dig_dcdc(&self) -> XPD_DIG_DCDC_R {
+        XPD_DIG_DCDC_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - rtc peripheral iso"]
+    #[inline(always)]
+    pub fn peri_iso(&self) -> PERI_ISO_R {
+        PERI_ISO_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - rtc peripheral power down"]
+    #[inline(always)]
+    pub fn xpd_rtc_peri(&self) -> XPD_RTC_PERI_R {
+        XPD_RTC_PERI_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - wifi iso"]
+    #[inline(always)]
+    pub fn wifi_iso(&self) -> WIFI_ISO_R {
+        WIFI_ISO_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - wifi wrap power down"]
+    #[inline(always)]
+    pub fn xpd_wifi(&self) -> XPD_WIFI_R {
+        XPD_WIFI_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - digital wrap iso"]
+    #[inline(always)]
+    pub fn dig_iso(&self) -> DIG_ISO_R {
+        DIG_ISO_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - digital wrap power down"]
+    #[inline(always)]
+    pub fn xpd_dig(&self) -> XPD_DIG_R {
+        XPD_DIG_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - touch should start to work"]
+    #[inline(always)]
+    pub fn touch_state_start(&self) -> TOUCH_STATE_START_R {
+        TOUCH_STATE_START_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 10 - touch is about to working. Switch rtc main state"]
+    #[inline(always)]
+    pub fn touch_state_switch(&self) -> TOUCH_STATE_SWITCH_R {
+        TOUCH_STATE_SWITCH_R::new(((self.bits >> 10) & 1) != 0)
+    }
+    #[doc = "Bit 11 - touch is in sleep state"]
+    #[inline(always)]
+    pub fn touch_state_slp(&self) -> TOUCH_STATE_SLP_R {
+        TOUCH_STATE_SLP_R::new(((self.bits >> 11) & 1) != 0)
+    }
+    #[doc = "Bit 12 - touch is done"]
+    #[inline(always)]
+    pub fn touch_state_done(&self) -> TOUCH_STATE_DONE_R {
+        TOUCH_STATE_DONE_R::new(((self.bits >> 12) & 1) != 0)
+    }
+    #[doc = "Bit 13 - ulp/cocpu should start to work"]
+    #[inline(always)]
+    pub fn cocpu_state_start(&self) -> COCPU_STATE_START_R {
+        COCPU_STATE_START_R::new(((self.bits >> 13) & 1) != 0)
+    }
+    #[doc = "Bit 14 - ulp/cocpu is about to working. Switch rtc main state"]
+    #[inline(always)]
+    pub fn cocpu_state_switch(&self) -> COCPU_STATE_SWITCH_R {
+        COCPU_STATE_SWITCH_R::new(((self.bits >> 14) & 1) != 0)
+    }
+    #[doc = "Bit 15 - ulp/cocpu is in sleep state"]
+    #[inline(always)]
+    pub fn cocpu_state_slp(&self) -> COCPU_STATE_SLP_R {
+        COCPU_STATE_SLP_R::new(((self.bits >> 15) & 1) != 0)
+    }
+    #[doc = "Bit 16 - ulp/cocpu is done"]
+    #[inline(always)]
+    pub fn cocpu_state_done(&self) -> COCPU_STATE_DONE_R {
+        COCPU_STATE_DONE_R::new(((self.bits >> 16) & 1) != 0)
+    }
+    #[doc = "Bit 17 - no use any more"]
+    #[inline(always)]
+    pub fn main_state_xtal_iso(&self) -> MAIN_STATE_XTAL_ISO_R {
+        MAIN_STATE_XTAL_ISO_R::new(((self.bits >> 17) & 1) != 0)
+    }
+    #[doc = "Bit 18 - rtc main state machine is in states that pll should be running"]
+    #[inline(always)]
+    pub fn main_state_pll_on(&self) -> MAIN_STATE_PLL_ON_R {
+        MAIN_STATE_PLL_ON_R::new(((self.bits >> 18) & 1) != 0)
+    }
+    #[doc = "Bit 19 - rtc is ready to receive wake up trigger from wake up source"]
+    #[inline(always)]
+    pub fn rdy_for_wakeup(&self) -> RDY_FOR_WAKEUP_R {
+        RDY_FOR_WAKEUP_R::new(((self.bits >> 19) & 1) != 0)
+    }
+    #[doc = "Bit 20 - rtc main state machine has been waited for some cycles"]
+    #[inline(always)]
+    pub fn main_state_wait_end(&self) -> MAIN_STATE_WAIT_END_R {
+        MAIN_STATE_WAIT_END_R::new(((self.bits >> 20) & 1) != 0)
+    }
+    #[doc = "Bit 21 - rtc main state machine is in the states of wakeup process"]
+    #[inline(always)]
+    pub fn in_wakeup_state(&self) -> IN_WAKEUP_STATE_R {
+        IN_WAKEUP_STATE_R::new(((self.bits >> 21) & 1) != 0)
+    }
+    #[doc = "Bit 22 - rtc main state machine is in the states of low power"]
+    #[inline(always)]
+    pub fn in_low_power_state(&self) -> IN_LOW_POWER_STATE_R {
+        IN_LOW_POWER_STATE_R::new(((self.bits >> 22) & 1) != 0)
+    }
+    #[doc = "Bit 23 - rtc main state machine is in wait 8m state"]
+    #[inline(always)]
+    pub fn main_state_in_wait_8m(&self) -> MAIN_STATE_IN_WAIT_8M_R {
+        MAIN_STATE_IN_WAIT_8M_R::new(((self.bits >> 23) & 1) != 0)
+    }
+    #[doc = "Bit 24 - rtc main state machine is in wait pll state"]
+    #[inline(always)]
+    pub fn main_state_in_wait_pll(&self) -> MAIN_STATE_IN_WAIT_PLL_R {
+        MAIN_STATE_IN_WAIT_PLL_R::new(((self.bits >> 24) & 1) != 0)
+    }
+    #[doc = "Bit 25 - rtc main state machine is in wait xtal state"]
+    #[inline(always)]
+    pub fn main_state_in_wait_xtl(&self) -> MAIN_STATE_IN_WAIT_XTL_R {
+        MAIN_STATE_IN_WAIT_XTL_R::new(((self.bits >> 25) & 1) != 0)
+    }
+    #[doc = "Bit 26 - rtc main state machine is in sleep state"]
+    #[inline(always)]
+    pub fn main_state_in_slp(&self) -> MAIN_STATE_IN_SLP_R {
+        MAIN_STATE_IN_SLP_R::new(((self.bits >> 26) & 1) != 0)
+    }
+    #[doc = "Bit 27 - rtc main state machine is in idle state"]
+    #[inline(always)]
+    pub fn main_state_in_idle(&self) -> MAIN_STATE_IN_IDLE_R {
+        MAIN_STATE_IN_IDLE_R::new(((self.bits >> 27) & 1) != 0)
+    }
+    #[doc = "Bits 28:31 - rtc main state machine status"]
+    #[inline(always)]
+    pub fn main_state(&self) -> MAIN_STATE_R {
+        MAIN_STATE_R::new(((self.bits >> 28) & 0x0f) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("LOW_POWER_ST")
+            .field("xpd_rom0", &self.xpd_rom0())
+            .field("xpd_dig_dcdc", &self.xpd_dig_dcdc())
+            .field("peri_iso", &self.peri_iso())
+            .field("xpd_rtc_peri", &self.xpd_rtc_peri())
+            .field("wifi_iso", &self.wifi_iso())
+            .field("xpd_wifi", &self.xpd_wifi())
+            .field("dig_iso", &self.dig_iso())
+            .field("xpd_dig", &self.xpd_dig())
+            .field("touch_state_start", &self.touch_state_start())
+            .field("touch_state_switch", &self.touch_state_switch())
+            .field("touch_state_slp", &self.touch_state_slp())
+            .field("touch_state_done", &self.touch_state_done())
+            .field("cocpu_state_start", &self.cocpu_state_start())
+            .field("cocpu_state_switch", &self.cocpu_state_switch())
+            .field("cocpu_state_slp", &self.cocpu_state_slp())
+            .field("cocpu_state_done", &self.cocpu_state_done())
+            .field("main_state_xtal_iso", &self.main_state_xtal_iso())
+            .field("main_state_pll_on", &self.main_state_pll_on())
+            .field("rdy_for_wakeup", &self.rdy_for_wakeup())
+            .field("main_state_wait_end", &self.main_state_wait_end())
+            .field("in_wakeup_state", &self.in_wakeup_state())
+            .field("in_low_power_state", &self.in_low_power_state())
+            .field("main_state_in_wait_8m", &self.main_state_in_wait_8m())
+            .field("main_state_in_wait_pll", &self.main_state_in_wait_pll())
+            .field("main_state_in_wait_xtl", &self.main_state_in_wait_xtl())
+            .field("main_state_in_slp", &self.main_state_in_slp())
+            .field("main_state_in_idle", &self.main_state_in_idle())
+            .field("main_state", &self.main_state())
+            .finish()
+    }
+}
+#[doc = "reserved register\n\nYou can [`read`](crate::Reg::read) this register and get [`low_power_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct LOW_POWER_ST_SPEC;
+impl crate::RegisterSpec for LOW_POWER_ST_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`low_power_st::R`](R) reader structure"]
+impl crate::Readable for LOW_POWER_ST_SPEC {}
+#[doc = "`reset()` method sets LOW_POWER_ST to value 0"]
+impl crate::Resettable for LOW_POWER_ST_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_cntl/option1.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `OPTION1` reader"]
+pub type R = crate::R<OPTION1_SPEC>;
+#[doc = "Register `OPTION1` writer"]
+pub type W = crate::W<OPTION1_SPEC>;
+#[doc = "Field `FORCE_DOWNLOAD_BOOT` reader - force chip entry download boot by sw"]
+pub type FORCE_DOWNLOAD_BOOT_R = crate::BitReader;
+#[doc = "Field `FORCE_DOWNLOAD_BOOT` writer - force chip entry download boot by sw"]
+pub type FORCE_DOWNLOAD_BOOT_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - force chip entry download boot by sw"]
+    #[inline(always)]
+    pub fn force_download_boot(&self) -> FORCE_DOWNLOAD_BOOT_R {
+        FORCE_DOWNLOAD_BOOT_R::new((self.bits & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("OPTION1")
+            .field("force_download_boot", &self.force_download_boot())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - force chip entry download boot by sw"]
+    #[inline(always)]
+    pub fn force_download_boot(&mut self) -> FORCE_DOWNLOAD_BOOT_W<OPTION1_SPEC> {
+        FORCE_DOWNLOAD_BOOT_W::new(self, 0)
+    }
+}
+#[doc = "rtc common configure\n\nYou can [`read`](crate::Reg::read) this register and get [`option1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`option1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct OPTION1_SPEC;
+impl crate::RegisterSpec for OPTION1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`option1::R`](R) reader structure"]
+impl crate::Readable for OPTION1_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`option1::W`](W) writer structure"]
+impl crate::Writable for OPTION1_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets OPTION1 to value 0"]
+impl crate::Resettable for OPTION1_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_cntl/options0.rs

@@ -0,0 +1,338 @@
+#[doc = "Register `OPTIONS0` reader"]
+pub type R = crate::R<OPTIONS0_SPEC>;
+#[doc = "Register `OPTIONS0` writer"]
+pub type W = crate::W<OPTIONS0_SPEC>;
+#[doc = "Field `SW_STALL_APPCPU_C0` reader - {reg_sw_stall_appcpu_c1\\[5:0\\], reg_sw_stall_appcpu_c0\\[1:0\\]} == 0x86 will stall APP CPU"]
+pub type SW_STALL_APPCPU_C0_R = crate::FieldReader;
+#[doc = "Field `SW_STALL_APPCPU_C0` writer - {reg_sw_stall_appcpu_c1\\[5:0\\], reg_sw_stall_appcpu_c0\\[1:0\\]} == 0x86 will stall APP CPU"]
+pub type SW_STALL_APPCPU_C0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `SW_STALL_PROCPU_C0` reader - {reg_sw_stall_procpu_c1\\[5:0\\], reg_sw_stall_procpu_c0\\[1:0\\]} == 0x86 will stall PRO CPU"]
+pub type SW_STALL_PROCPU_C0_R = crate::FieldReader;
+#[doc = "Field `SW_STALL_PROCPU_C0` writer - {reg_sw_stall_procpu_c1\\[5:0\\], reg_sw_stall_procpu_c0\\[1:0\\]} == 0x86 will stall PRO CPU"]
+pub type SW_STALL_PROCPU_C0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `SW_APPCPU_RST` writer - APP CPU SW reset"]
+pub type SW_APPCPU_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SW_PROCPU_RST` writer - PRO CPU SW reset"]
+pub type SW_PROCPU_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `BB_I2C_FORCE_PD` reader - BB_I2C force power down"]
+pub type BB_I2C_FORCE_PD_R = crate::BitReader;
+#[doc = "Field `BB_I2C_FORCE_PD` writer - BB_I2C force power down"]
+pub type BB_I2C_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `BB_I2C_FORCE_PU` reader - BB_I2C force power up"]
+pub type BB_I2C_FORCE_PU_R = crate::BitReader;
+#[doc = "Field `BB_I2C_FORCE_PU` writer - BB_I2C force power up"]
+pub type BB_I2C_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `BBPLL_I2C_FORCE_PD` reader - BB_PLL _I2C force power down"]
+pub type BBPLL_I2C_FORCE_PD_R = crate::BitReader;
+#[doc = "Field `BBPLL_I2C_FORCE_PD` writer - BB_PLL _I2C force power down"]
+pub type BBPLL_I2C_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `BBPLL_I2C_FORCE_PU` reader - BB_PLL_I2C force power up"]
+pub type BBPLL_I2C_FORCE_PU_R = crate::BitReader;
+#[doc = "Field `BBPLL_I2C_FORCE_PU` writer - BB_PLL_I2C force power up"]
+pub type BBPLL_I2C_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `BBPLL_FORCE_PD` reader - BB_PLL force power down"]
+pub type BBPLL_FORCE_PD_R = crate::BitReader;
+#[doc = "Field `BBPLL_FORCE_PD` writer - BB_PLL force power down"]
+pub type BBPLL_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `BBPLL_FORCE_PU` reader - BB_PLL force power up"]
+pub type BBPLL_FORCE_PU_R = crate::BitReader;
+#[doc = "Field `BBPLL_FORCE_PU` writer - BB_PLL force power up"]
+pub type BBPLL_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `XTL_FORCE_PD` reader - crystall force power down"]
+pub type XTL_FORCE_PD_R = crate::BitReader;
+#[doc = "Field `XTL_FORCE_PD` writer - crystall force power down"]
+pub type XTL_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `XTL_FORCE_PU` reader - crystall force power up"]
+pub type XTL_FORCE_PU_R = crate::BitReader;
+#[doc = "Field `XTL_FORCE_PU` writer - crystall force power up"]
+pub type XTL_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `XTL_EN_WAIT` reader - wait bias_sleep and current source wakeup"]
+pub type XTL_EN_WAIT_R = crate::FieldReader;
+#[doc = "Field `XTL_EN_WAIT` writer - wait bias_sleep and current source wakeup"]
+pub type XTL_EN_WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `XTL_FORCE_ISO` reader - No public"]
+pub type XTL_FORCE_ISO_R = crate::BitReader;
+#[doc = "Field `XTL_FORCE_ISO` writer - No public"]
+pub type XTL_FORCE_ISO_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PLL_FORCE_ISO` reader - No public"]
+pub type PLL_FORCE_ISO_R = crate::BitReader;
+#[doc = "Field `PLL_FORCE_ISO` writer - No public"]
+pub type PLL_FORCE_ISO_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ANALOG_FORCE_ISO` reader - No public"]
+pub type ANALOG_FORCE_ISO_R = crate::BitReader;
+#[doc = "Field `ANALOG_FORCE_ISO` writer - No public"]
+pub type ANALOG_FORCE_ISO_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `XTL_FORCE_NOISO` reader - No public"]
+pub type XTL_FORCE_NOISO_R = crate::BitReader;
+#[doc = "Field `XTL_FORCE_NOISO` writer - No public"]
+pub type XTL_FORCE_NOISO_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PLL_FORCE_NOISO` reader - No public"]
+pub type PLL_FORCE_NOISO_R = crate::BitReader;
+#[doc = "Field `PLL_FORCE_NOISO` writer - No public"]
+pub type PLL_FORCE_NOISO_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ANALOG_FORCE_NOISO` reader - No public"]
+pub type ANALOG_FORCE_NOISO_R = crate::BitReader;
+#[doc = "Field `ANALOG_FORCE_NOISO` writer - No public"]
+pub type ANALOG_FORCE_NOISO_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DG_WRAP_FORCE_RST` reader - digital wrap force reset in deep sleep"]
+pub type DG_WRAP_FORCE_RST_R = crate::BitReader;
+#[doc = "Field `DG_WRAP_FORCE_RST` writer - digital wrap force reset in deep sleep"]
+pub type DG_WRAP_FORCE_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DG_WRAP_FORCE_NORST` reader - digital core force no reset in deep sleep"]
+pub type DG_WRAP_FORCE_NORST_R = crate::BitReader;
+#[doc = "Field `DG_WRAP_FORCE_NORST` writer - digital core force no reset in deep sleep"]
+pub type DG_WRAP_FORCE_NORST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SW_SYS_RST` writer - SW system reset"]
+pub type SW_SYS_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 0:1 - {reg_sw_stall_appcpu_c1\\[5:0\\], reg_sw_stall_appcpu_c0\\[1:0\\]} == 0x86 will stall APP CPU"]
+    #[inline(always)]
+    pub fn sw_stall_appcpu_c0(&self) -> SW_STALL_APPCPU_C0_R {
+        SW_STALL_APPCPU_C0_R::new((self.bits & 3) as u8)
+    }
+    #[doc = "Bits 2:3 - {reg_sw_stall_procpu_c1\\[5:0\\], reg_sw_stall_procpu_c0\\[1:0\\]} == 0x86 will stall PRO CPU"]
+    #[inline(always)]
+    pub fn sw_stall_procpu_c0(&self) -> SW_STALL_PROCPU_C0_R {
+        SW_STALL_PROCPU_C0_R::new(((self.bits >> 2) & 3) as u8)
+    }
+    #[doc = "Bit 6 - BB_I2C force power down"]
+    #[inline(always)]
+    pub fn bb_i2c_force_pd(&self) -> BB_I2C_FORCE_PD_R {
+        BB_I2C_FORCE_PD_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - BB_I2C force power up"]
+    #[inline(always)]
+    pub fn bb_i2c_force_pu(&self) -> BB_I2C_FORCE_PU_R {
+        BB_I2C_FORCE_PU_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - BB_PLL _I2C force power down"]
+    #[inline(always)]
+    pub fn bbpll_i2c_force_pd(&self) -> BBPLL_I2C_FORCE_PD_R {
+        BBPLL_I2C_FORCE_PD_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - BB_PLL_I2C force power up"]
+    #[inline(always)]
+    pub fn bbpll_i2c_force_pu(&self) -> BBPLL_I2C_FORCE_PU_R {
+        BBPLL_I2C_FORCE_PU_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 10 - BB_PLL force power down"]
+    #[inline(always)]
+    pub fn bbpll_force_pd(&self) -> BBPLL_FORCE_PD_R {
+        BBPLL_FORCE_PD_R::new(((self.bits >> 10) & 1) != 0)
+    }
+    #[doc = "Bit 11 - BB_PLL force power up"]
+    #[inline(always)]
+    pub fn bbpll_force_pu(&self) -> BBPLL_FORCE_PU_R {
+        BBPLL_FORCE_PU_R::new(((self.bits >> 11) & 1) != 0)
+    }
+    #[doc = "Bit 12 - crystall force power down"]
+    #[inline(always)]
+    pub fn xtl_force_pd(&self) -> XTL_FORCE_PD_R {
+        XTL_FORCE_PD_R::new(((self.bits >> 12) & 1) != 0)
+    }
+    #[doc = "Bit 13 - crystall force power up"]
+    #[inline(always)]
+    pub fn xtl_force_pu(&self) -> XTL_FORCE_PU_R {
+        XTL_FORCE_PU_R::new(((self.bits >> 13) & 1) != 0)
+    }
+    #[doc = "Bits 14:17 - wait bias_sleep and current source wakeup"]
+    #[inline(always)]
+    pub fn xtl_en_wait(&self) -> XTL_EN_WAIT_R {
+        XTL_EN_WAIT_R::new(((self.bits >> 14) & 0x0f) as u8)
+    }
+    #[doc = "Bit 23 - No public"]
+    #[inline(always)]
+    pub fn xtl_force_iso(&self) -> XTL_FORCE_ISO_R {
+        XTL_FORCE_ISO_R::new(((self.bits >> 23) & 1) != 0)
+    }
+    #[doc = "Bit 24 - No public"]
+    #[inline(always)]
+    pub fn pll_force_iso(&self) -> PLL_FORCE_ISO_R {
+        PLL_FORCE_ISO_R::new(((self.bits >> 24) & 1) != 0)
+    }
+    #[doc = "Bit 25 - No public"]
+    #[inline(always)]
+    pub fn analog_force_iso(&self) -> ANALOG_FORCE_ISO_R {
+        ANALOG_FORCE_ISO_R::new(((self.bits >> 25) & 1) != 0)
+    }
+    #[doc = "Bit 26 - No public"]
+    #[inline(always)]
+    pub fn xtl_force_noiso(&self) -> XTL_FORCE_NOISO_R {
+        XTL_FORCE_NOISO_R::new(((self.bits >> 26) & 1) != 0)
+    }
+    #[doc = "Bit 27 - No public"]
+    #[inline(always)]
+    pub fn pll_force_noiso(&self) -> PLL_FORCE_NOISO_R {
+        PLL_FORCE_NOISO_R::new(((self.bits >> 27) & 1) != 0)
+    }
+    #[doc = "Bit 28 - No public"]
+    #[inline(always)]
+    pub fn analog_force_noiso(&self) -> ANALOG_FORCE_NOISO_R {
+        ANALOG_FORCE_NOISO_R::new(((self.bits >> 28) & 1) != 0)
+    }
+    #[doc = "Bit 29 - digital wrap force reset in deep sleep"]
+    #[inline(always)]
+    pub fn dg_wrap_force_rst(&self) -> DG_WRAP_FORCE_RST_R {
+        DG_WRAP_FORCE_RST_R::new(((self.bits >> 29) & 1) != 0)
+    }
+    #[doc = "Bit 30 - digital core force no reset in deep sleep"]
+    #[inline(always)]
+    pub fn dg_wrap_force_norst(&self) -> DG_WRAP_FORCE_NORST_R {
+        DG_WRAP_FORCE_NORST_R::new(((self.bits >> 30) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("OPTIONS0")
+            .field("sw_stall_appcpu_c0", &self.sw_stall_appcpu_c0())
+            .field("sw_stall_procpu_c0", &self.sw_stall_procpu_c0())
+            .field("bb_i2c_force_pd", &self.bb_i2c_force_pd())
+            .field("bb_i2c_force_pu", &self.bb_i2c_force_pu())
+            .field("bbpll_i2c_force_pd", &self.bbpll_i2c_force_pd())
+            .field("bbpll_i2c_force_pu", &self.bbpll_i2c_force_pu())
+            .field("bbpll_force_pd", &self.bbpll_force_pd())
+            .field("bbpll_force_pu", &self.bbpll_force_pu())
+            .field("xtl_force_pd", &self.xtl_force_pd())
+            .field("xtl_force_pu", &self.xtl_force_pu())
+            .field("xtl_en_wait", &self.xtl_en_wait())
+            .field("xtl_force_iso", &self.xtl_force_iso())
+            .field("pll_force_iso", &self.pll_force_iso())
+            .field("analog_force_iso", &self.analog_force_iso())
+            .field("xtl_force_noiso", &self.xtl_force_noiso())
+            .field("pll_force_noiso", &self.pll_force_noiso())
+            .field("analog_force_noiso", &self.analog_force_noiso())
+            .field("dg_wrap_force_rst", &self.dg_wrap_force_rst())
+            .field("dg_wrap_force_norst", &self.dg_wrap_force_norst())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:1 - {reg_sw_stall_appcpu_c1\\[5:0\\], reg_sw_stall_appcpu_c0\\[1:0\\]} == 0x86 will stall APP CPU"]
+    #[inline(always)]
+    pub fn sw_stall_appcpu_c0(&mut self) -> SW_STALL_APPCPU_C0_W<OPTIONS0_SPEC> {
+        SW_STALL_APPCPU_C0_W::new(self, 0)
+    }
+    #[doc = "Bits 2:3 - {reg_sw_stall_procpu_c1\\[5:0\\], reg_sw_stall_procpu_c0\\[1:0\\]} == 0x86 will stall PRO CPU"]
+    #[inline(always)]
+    pub fn sw_stall_procpu_c0(&mut self) -> SW_STALL_PROCPU_C0_W<OPTIONS0_SPEC> {
+        SW_STALL_PROCPU_C0_W::new(self, 2)
+    }
+    #[doc = "Bit 4 - APP CPU SW reset"]
+    #[inline(always)]
+    pub fn sw_appcpu_rst(&mut self) -> SW_APPCPU_RST_W<OPTIONS0_SPEC> {
+        SW_APPCPU_RST_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - PRO CPU SW reset"]
+    #[inline(always)]
+    pub fn sw_procpu_rst(&mut self) -> SW_PROCPU_RST_W<OPTIONS0_SPEC> {
+        SW_PROCPU_RST_W::new(self, 5)
+    }
+    #[doc = "Bit 6 - BB_I2C force power down"]
+    #[inline(always)]
+    pub fn bb_i2c_force_pd(&mut self) -> BB_I2C_FORCE_PD_W<OPTIONS0_SPEC> {
+        BB_I2C_FORCE_PD_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - BB_I2C force power up"]
+    #[inline(always)]
+    pub fn bb_i2c_force_pu(&mut self) -> BB_I2C_FORCE_PU_W<OPTIONS0_SPEC> {
+        BB_I2C_FORCE_PU_W::new(self, 7)
+    }
+    #[doc = "Bit 8 - BB_PLL _I2C force power down"]
+    #[inline(always)]
+    pub fn bbpll_i2c_force_pd(&mut self) -> BBPLL_I2C_FORCE_PD_W<OPTIONS0_SPEC> {
+        BBPLL_I2C_FORCE_PD_W::new(self, 8)
+    }
+    #[doc = "Bit 9 - BB_PLL_I2C force power up"]
+    #[inline(always)]
+    pub fn bbpll_i2c_force_pu(&mut self) -> BBPLL_I2C_FORCE_PU_W<OPTIONS0_SPEC> {
+        BBPLL_I2C_FORCE_PU_W::new(self, 9)
+    }
+    #[doc = "Bit 10 - BB_PLL force power down"]
+    #[inline(always)]
+    pub fn bbpll_force_pd(&mut self) -> BBPLL_FORCE_PD_W<OPTIONS0_SPEC> {
+        BBPLL_FORCE_PD_W::new(self, 10)
+    }
+    #[doc = "Bit 11 - BB_PLL force power up"]
+    #[inline(always)]
+    pub fn bbpll_force_pu(&mut self) -> BBPLL_FORCE_PU_W<OPTIONS0_SPEC> {
+        BBPLL_FORCE_PU_W::new(self, 11)
+    }
+    #[doc = "Bit 12 - crystall force power down"]
+    #[inline(always)]
+    pub fn xtl_force_pd(&mut self) -> XTL_FORCE_PD_W<OPTIONS0_SPEC> {
+        XTL_FORCE_PD_W::new(self, 12)
+    }
+    #[doc = "Bit 13 - crystall force power up"]
+    #[inline(always)]
+    pub fn xtl_force_pu(&mut self) -> XTL_FORCE_PU_W<OPTIONS0_SPEC> {
+        XTL_FORCE_PU_W::new(self, 13)
+    }
+    #[doc = "Bits 14:17 - wait bias_sleep and current source wakeup"]
+    #[inline(always)]
+    pub fn xtl_en_wait(&mut self) -> XTL_EN_WAIT_W<OPTIONS0_SPEC> {
+        XTL_EN_WAIT_W::new(self, 14)
+    }
+    #[doc = "Bit 23 - No public"]
+    #[inline(always)]
+    pub fn xtl_force_iso(&mut self) -> XTL_FORCE_ISO_W<OPTIONS0_SPEC> {
+        XTL_FORCE_ISO_W::new(self, 23)
+    }
+    #[doc = "Bit 24 - No public"]
+    #[inline(always)]
+    pub fn pll_force_iso(&mut self) -> PLL_FORCE_ISO_W<OPTIONS0_SPEC> {
+        PLL_FORCE_ISO_W::new(self, 24)
+    }
+    #[doc = "Bit 25 - No public"]
+    #[inline(always)]
+    pub fn analog_force_iso(&mut self) -> ANALOG_FORCE_ISO_W<OPTIONS0_SPEC> {
+        ANALOG_FORCE_ISO_W::new(self, 25)
+    }
+    #[doc = "Bit 26 - No public"]
+    #[inline(always)]
+    pub fn xtl_force_noiso(&mut self) -> XTL_FORCE_NOISO_W<OPTIONS0_SPEC> {
+        XTL_FORCE_NOISO_W::new(self, 26)
+    }
+    #[doc = "Bit 27 - No public"]
+    #[inline(always)]
+    pub fn pll_force_noiso(&mut self) -> PLL_FORCE_NOISO_W<OPTIONS0_SPEC> {
+        PLL_FORCE_NOISO_W::new(self, 27)
+    }
+    #[doc = "Bit 28 - No public"]
+    #[inline(always)]
+    pub fn analog_force_noiso(&mut self) -> ANALOG_FORCE_NOISO_W<OPTIONS0_SPEC> {
+        ANALOG_FORCE_NOISO_W::new(self, 28)
+    }
+    #[doc = "Bit 29 - digital wrap force reset in deep sleep"]
+    #[inline(always)]
+    pub fn dg_wrap_force_rst(&mut self) -> DG_WRAP_FORCE_RST_W<OPTIONS0_SPEC> {
+        DG_WRAP_FORCE_RST_W::new(self, 29)
+    }
+    #[doc = "Bit 30 - digital core force no reset in deep sleep"]
+    #[inline(always)]
+    pub fn dg_wrap_force_norst(&mut self) -> DG_WRAP_FORCE_NORST_W<OPTIONS0_SPEC> {
+        DG_WRAP_FORCE_NORST_W::new(self, 30)
+    }
+    #[doc = "Bit 31 - SW system reset"]
+    #[inline(always)]
+    pub fn sw_sys_rst(&mut self) -> SW_SYS_RST_W<OPTIONS0_SPEC> {
+        SW_SYS_RST_W::new(self, 31)
+    }
+}
+#[doc = "RTC common configure register\n\nYou can [`read`](crate::Reg::read) this register and get [`options0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`options0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct OPTIONS0_SPEC;
+impl crate::RegisterSpec for OPTIONS0_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`options0::R`](R) reader structure"]
+impl crate::Readable for OPTIONS0_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`options0::W`](W) writer structure"]
+impl crate::Writable for OPTIONS0_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets OPTIONS0 to value 0x1c00_a000"]
+impl crate::Resettable for OPTIONS0_SPEC {
+    const RESET_VALUE: u32 = 0x1c00_a000;
+}

vendor/esp32s3/src/rtc_cntl/pad_hold.rs

@@ -0,0 +1,362 @@
+#[doc = "Register `PAD_HOLD` reader"]
+pub type R = crate::R<PAD_HOLD_SPEC>;
+#[doc = "Register `PAD_HOLD` writer"]
+pub type W = crate::W<PAD_HOLD_SPEC>;
+#[doc = "Field `TOUCH_PAD0_HOLD` reader - hold rtc pad0"]
+pub type TOUCH_PAD0_HOLD_R = crate::BitReader;
+#[doc = "Field `TOUCH_PAD0_HOLD` writer - hold rtc pad0"]
+pub type TOUCH_PAD0_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TOUCH_PAD1_HOLD` reader - hold rtc pad-1"]
+pub type TOUCH_PAD1_HOLD_R = crate::BitReader;
+#[doc = "Field `TOUCH_PAD1_HOLD` writer - hold rtc pad-1"]
+pub type TOUCH_PAD1_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TOUCH_PAD2_HOLD` reader - hold rtc pad-2"]
+pub type TOUCH_PAD2_HOLD_R = crate::BitReader;
+#[doc = "Field `TOUCH_PAD2_HOLD` writer - hold rtc pad-2"]
+pub type TOUCH_PAD2_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TOUCH_PAD3_HOLD` reader - hold rtc pad-3"]
+pub type TOUCH_PAD3_HOLD_R = crate::BitReader;
+#[doc = "Field `TOUCH_PAD3_HOLD` writer - hold rtc pad-3"]
+pub type TOUCH_PAD3_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TOUCH_PAD4_HOLD` reader - hold rtc pad-4"]
+pub type TOUCH_PAD4_HOLD_R = crate::BitReader;
+#[doc = "Field `TOUCH_PAD4_HOLD` writer - hold rtc pad-4"]
+pub type TOUCH_PAD4_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TOUCH_PAD5_HOLD` reader - hold rtc pad-5"]
+pub type TOUCH_PAD5_HOLD_R = crate::BitReader;
+#[doc = "Field `TOUCH_PAD5_HOLD` writer - hold rtc pad-5"]
+pub type TOUCH_PAD5_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TOUCH_PAD6_HOLD` reader - hold rtc pad-6"]
+pub type TOUCH_PAD6_HOLD_R = crate::BitReader;
+#[doc = "Field `TOUCH_PAD6_HOLD` writer - hold rtc pad-6"]
+pub type TOUCH_PAD6_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TOUCH_PAD7_HOLD` reader - hold rtc pad-7"]
+pub type TOUCH_PAD7_HOLD_R = crate::BitReader;
+#[doc = "Field `TOUCH_PAD7_HOLD` writer - hold rtc pad-7"]
+pub type TOUCH_PAD7_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TOUCH_PAD8_HOLD` reader - hold rtc pad-8"]
+pub type TOUCH_PAD8_HOLD_R = crate::BitReader;
+#[doc = "Field `TOUCH_PAD8_HOLD` writer - hold rtc pad-8"]
+pub type TOUCH_PAD8_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TOUCH_PAD9_HOLD` reader - hold rtc pad-9"]
+pub type TOUCH_PAD9_HOLD_R = crate::BitReader;
+#[doc = "Field `TOUCH_PAD9_HOLD` writer - hold rtc pad-9"]
+pub type TOUCH_PAD9_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TOUCH_PAD10_HOLD` reader - hold rtc pad-10"]
+pub type TOUCH_PAD10_HOLD_R = crate::BitReader;
+#[doc = "Field `TOUCH_PAD10_HOLD` writer - hold rtc pad-10"]
+pub type TOUCH_PAD10_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TOUCH_PAD11_HOLD` reader - hold rtc pad-11"]
+pub type TOUCH_PAD11_HOLD_R = crate::BitReader;
+#[doc = "Field `TOUCH_PAD11_HOLD` writer - hold rtc pad-11"]
+pub type TOUCH_PAD11_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TOUCH_PAD12_HOLD` reader - hold rtc pad-12"]
+pub type TOUCH_PAD12_HOLD_R = crate::BitReader;
+#[doc = "Field `TOUCH_PAD12_HOLD` writer - hold rtc pad-12"]
+pub type TOUCH_PAD12_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TOUCH_PAD13_HOLD` reader - hold rtc pad-13"]
+pub type TOUCH_PAD13_HOLD_R = crate::BitReader;
+#[doc = "Field `TOUCH_PAD13_HOLD` writer - hold rtc pad-13"]
+pub type TOUCH_PAD13_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TOUCH_PAD14_HOLD` reader - hold rtc pad-14"]
+pub type TOUCH_PAD14_HOLD_R = crate::BitReader;
+#[doc = "Field `TOUCH_PAD14_HOLD` writer - hold rtc pad-14"]
+pub type TOUCH_PAD14_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `X32P_HOLD` reader - hold rtc pad-15"]
+pub type X32P_HOLD_R = crate::BitReader;
+#[doc = "Field `X32P_HOLD` writer - hold rtc pad-15"]
+pub type X32P_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `X32N_HOLD` reader - hold rtc pad-16"]
+pub type X32N_HOLD_R = crate::BitReader;
+#[doc = "Field `X32N_HOLD` writer - hold rtc pad-16"]
+pub type X32N_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PDAC1_HOLD` reader - hold rtc pad-17"]
+pub type PDAC1_HOLD_R = crate::BitReader;
+#[doc = "Field `PDAC1_HOLD` writer - hold rtc pad-17"]
+pub type PDAC1_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PDAC2_HOLD` reader - hold rtc pad-18"]
+pub type PDAC2_HOLD_R = crate::BitReader;
+#[doc = "Field `PDAC2_HOLD` writer - hold rtc pad-18"]
+pub type PDAC2_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PAD19_HOLD` reader - hold rtc pad-19"]
+pub type PAD19_HOLD_R = crate::BitReader;
+#[doc = "Field `PAD19_HOLD` writer - hold rtc pad-19"]
+pub type PAD19_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PAD20_HOLD` reader - hold rtc pad-20"]
+pub type PAD20_HOLD_R = crate::BitReader;
+#[doc = "Field `PAD20_HOLD` writer - hold rtc pad-20"]
+pub type PAD20_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PAD21_HOLD` reader - hold rtc pad-21"]
+pub type PAD21_HOLD_R = crate::BitReader;
+#[doc = "Field `PAD21_HOLD` writer - hold rtc pad-21"]
+pub type PAD21_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - hold rtc pad0"]
+    #[inline(always)]
+    pub fn touch_pad0_hold(&self) -> TOUCH_PAD0_HOLD_R {
+        TOUCH_PAD0_HOLD_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - hold rtc pad-1"]
+    #[inline(always)]
+    pub fn touch_pad1_hold(&self) -> TOUCH_PAD1_HOLD_R {
+        TOUCH_PAD1_HOLD_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - hold rtc pad-2"]
+    #[inline(always)]
+    pub fn touch_pad2_hold(&self) -> TOUCH_PAD2_HOLD_R {
+        TOUCH_PAD2_HOLD_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - hold rtc pad-3"]
+    #[inline(always)]
+    pub fn touch_pad3_hold(&self) -> TOUCH_PAD3_HOLD_R {
+        TOUCH_PAD3_HOLD_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - hold rtc pad-4"]
+    #[inline(always)]
+    pub fn touch_pad4_hold(&self) -> TOUCH_PAD4_HOLD_R {
+        TOUCH_PAD4_HOLD_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - hold rtc pad-5"]
+    #[inline(always)]
+    pub fn touch_pad5_hold(&self) -> TOUCH_PAD5_HOLD_R {
+        TOUCH_PAD5_HOLD_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - hold rtc pad-6"]
+    #[inline(always)]
+    pub fn touch_pad6_hold(&self) -> TOUCH_PAD6_HOLD_R {
+        TOUCH_PAD6_HOLD_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - hold rtc pad-7"]
+    #[inline(always)]
+    pub fn touch_pad7_hold(&self) -> TOUCH_PAD7_HOLD_R {
+        TOUCH_PAD7_HOLD_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - hold rtc pad-8"]
+    #[inline(always)]
+    pub fn touch_pad8_hold(&self) -> TOUCH_PAD8_HOLD_R {
+        TOUCH_PAD8_HOLD_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - hold rtc pad-9"]
+    #[inline(always)]
+    pub fn touch_pad9_hold(&self) -> TOUCH_PAD9_HOLD_R {
+        TOUCH_PAD9_HOLD_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 10 - hold rtc pad-10"]
+    #[inline(always)]
+    pub fn touch_pad10_hold(&self) -> TOUCH_PAD10_HOLD_R {
+        TOUCH_PAD10_HOLD_R::new(((self.bits >> 10) & 1) != 0)
+    }
+    #[doc = "Bit 11 - hold rtc pad-11"]
+    #[inline(always)]
+    pub fn touch_pad11_hold(&self) -> TOUCH_PAD11_HOLD_R {
+        TOUCH_PAD11_HOLD_R::new(((self.bits >> 11) & 1) != 0)
+    }
+    #[doc = "Bit 12 - hold rtc pad-12"]
+    #[inline(always)]
+    pub fn touch_pad12_hold(&self) -> TOUCH_PAD12_HOLD_R {
+        TOUCH_PAD12_HOLD_R::new(((self.bits >> 12) & 1) != 0)
+    }
+    #[doc = "Bit 13 - hold rtc pad-13"]
+    #[inline(always)]
+    pub fn touch_pad13_hold(&self) -> TOUCH_PAD13_HOLD_R {
+        TOUCH_PAD13_HOLD_R::new(((self.bits >> 13) & 1) != 0)
+    }
+    #[doc = "Bit 14 - hold rtc pad-14"]
+    #[inline(always)]
+    pub fn touch_pad14_hold(&self) -> TOUCH_PAD14_HOLD_R {
+        TOUCH_PAD14_HOLD_R::new(((self.bits >> 14) & 1) != 0)
+    }
+    #[doc = "Bit 15 - hold rtc pad-15"]
+    #[inline(always)]
+    pub fn x32p_hold(&self) -> X32P_HOLD_R {
+        X32P_HOLD_R::new(((self.bits >> 15) & 1) != 0)
+    }
+    #[doc = "Bit 16 - hold rtc pad-16"]
+    #[inline(always)]
+    pub fn x32n_hold(&self) -> X32N_HOLD_R {
+        X32N_HOLD_R::new(((self.bits >> 16) & 1) != 0)
+    }
+    #[doc = "Bit 17 - hold rtc pad-17"]
+    #[inline(always)]
+    pub fn pdac1_hold(&self) -> PDAC1_HOLD_R {
+        PDAC1_HOLD_R::new(((self.bits >> 17) & 1) != 0)
+    }
+    #[doc = "Bit 18 - hold rtc pad-18"]
+    #[inline(always)]
+    pub fn pdac2_hold(&self) -> PDAC2_HOLD_R {
+        PDAC2_HOLD_R::new(((self.bits >> 18) & 1) != 0)
+    }
+    #[doc = "Bit 19 - hold rtc pad-19"]
+    #[inline(always)]
+    pub fn pad19_hold(&self) -> PAD19_HOLD_R {
+        PAD19_HOLD_R::new(((self.bits >> 19) & 1) != 0)
+    }
+    #[doc = "Bit 20 - hold rtc pad-20"]
+    #[inline(always)]
+    pub fn pad20_hold(&self) -> PAD20_HOLD_R {
+        PAD20_HOLD_R::new(((self.bits >> 20) & 1) != 0)
+    }
+    #[doc = "Bit 21 - hold rtc pad-21"]
+    #[inline(always)]
+    pub fn pad21_hold(&self) -> PAD21_HOLD_R {
+        PAD21_HOLD_R::new(((self.bits >> 21) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("PAD_HOLD")
+            .field("touch_pad0_hold", &self.touch_pad0_hold())
+            .field("touch_pad1_hold", &self.touch_pad1_hold())
+            .field("touch_pad2_hold", &self.touch_pad2_hold())
+            .field("touch_pad3_hold", &self.touch_pad3_hold())
+            .field("touch_pad4_hold", &self.touch_pad4_hold())
+            .field("touch_pad5_hold", &self.touch_pad5_hold())
+            .field("touch_pad6_hold", &self.touch_pad6_hold())
+            .field("touch_pad7_hold", &self.touch_pad7_hold())
+            .field("touch_pad8_hold", &self.touch_pad8_hold())
+            .field("touch_pad9_hold", &self.touch_pad9_hold())
+            .field("touch_pad10_hold", &self.touch_pad10_hold())
+            .field("touch_pad11_hold", &self.touch_pad11_hold())
+            .field("touch_pad12_hold", &self.touch_pad12_hold())
+            .field("touch_pad13_hold", &self.touch_pad13_hold())
+            .field("touch_pad14_hold", &self.touch_pad14_hold())
+            .field("x32p_hold", &self.x32p_hold())
+            .field("x32n_hold", &self.x32n_hold())
+            .field("pdac1_hold", &self.pdac1_hold())
+            .field("pdac2_hold", &self.pdac2_hold())
+            .field("pad19_hold", &self.pad19_hold())
+            .field("pad20_hold", &self.pad20_hold())
+            .field("pad21_hold", &self.pad21_hold())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - hold rtc pad0"]
+    #[inline(always)]
+    pub fn touch_pad0_hold(&mut self) -> TOUCH_PAD0_HOLD_W<PAD_HOLD_SPEC> {
+        TOUCH_PAD0_HOLD_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - hold rtc pad-1"]
+    #[inline(always)]
+    pub fn touch_pad1_hold(&mut self) -> TOUCH_PAD1_HOLD_W<PAD_HOLD_SPEC> {
+        TOUCH_PAD1_HOLD_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - hold rtc pad-2"]
+    #[inline(always)]
+    pub fn touch_pad2_hold(&mut self) -> TOUCH_PAD2_HOLD_W<PAD_HOLD_SPEC> {
+        TOUCH_PAD2_HOLD_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - hold rtc pad-3"]
+    #[inline(always)]
+    pub fn touch_pad3_hold(&mut self) -> TOUCH_PAD3_HOLD_W<PAD_HOLD_SPEC> {
+        TOUCH_PAD3_HOLD_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - hold rtc pad-4"]
+    #[inline(always)]
+    pub fn touch_pad4_hold(&mut self) -> TOUCH_PAD4_HOLD_W<PAD_HOLD_SPEC> {
+        TOUCH_PAD4_HOLD_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - hold rtc pad-5"]
+    #[inline(always)]
+    pub fn touch_pad5_hold(&mut self) -> TOUCH_PAD5_HOLD_W<PAD_HOLD_SPEC> {
+        TOUCH_PAD5_HOLD_W::new(self, 5)
+    }
+    #[doc = "Bit 6 - hold rtc pad-6"]
+    #[inline(always)]
+    pub fn touch_pad6_hold(&mut self) -> TOUCH_PAD6_HOLD_W<PAD_HOLD_SPEC> {
+        TOUCH_PAD6_HOLD_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - hold rtc pad-7"]
+    #[inline(always)]
+    pub fn touch_pad7_hold(&mut self) -> TOUCH_PAD7_HOLD_W<PAD_HOLD_SPEC> {
+        TOUCH_PAD7_HOLD_W::new(self, 7)
+    }
+    #[doc = "Bit 8 - hold rtc pad-8"]
+    #[inline(always)]
+    pub fn touch_pad8_hold(&mut self) -> TOUCH_PAD8_HOLD_W<PAD_HOLD_SPEC> {
+        TOUCH_PAD8_HOLD_W::new(self, 8)
+    }
+    #[doc = "Bit 9 - hold rtc pad-9"]
+    #[inline(always)]
+    pub fn touch_pad9_hold(&mut self) -> TOUCH_PAD9_HOLD_W<PAD_HOLD_SPEC> {
+        TOUCH_PAD9_HOLD_W::new(self, 9)
+    }
+    #[doc = "Bit 10 - hold rtc pad-10"]
+    #[inline(always)]
+    pub fn touch_pad10_hold(&mut self) -> TOUCH_PAD10_HOLD_W<PAD_HOLD_SPEC> {
+        TOUCH_PAD10_HOLD_W::new(self, 10)
+    }
+    #[doc = "Bit 11 - hold rtc pad-11"]
+    #[inline(always)]
+    pub fn touch_pad11_hold(&mut self) -> TOUCH_PAD11_HOLD_W<PAD_HOLD_SPEC> {
+        TOUCH_PAD11_HOLD_W::new(self, 11)
+    }
+    #[doc = "Bit 12 - hold rtc pad-12"]
+    #[inline(always)]
+    pub fn touch_pad12_hold(&mut self) -> TOUCH_PAD12_HOLD_W<PAD_HOLD_SPEC> {
+        TOUCH_PAD12_HOLD_W::new(self, 12)
+    }
+    #[doc = "Bit 13 - hold rtc pad-13"]
+    #[inline(always)]
+    pub fn touch_pad13_hold(&mut self) -> TOUCH_PAD13_HOLD_W<PAD_HOLD_SPEC> {
+        TOUCH_PAD13_HOLD_W::new(self, 13)
+    }
+    #[doc = "Bit 14 - hold rtc pad-14"]
+    #[inline(always)]
+    pub fn touch_pad14_hold(&mut self) -> TOUCH_PAD14_HOLD_W<PAD_HOLD_SPEC> {
+        TOUCH_PAD14_HOLD_W::new(self, 14)
+    }
+    #[doc = "Bit 15 - hold rtc pad-15"]
+    #[inline(always)]
+    pub fn x32p_hold(&mut self) -> X32P_HOLD_W<PAD_HOLD_SPEC> {
+        X32P_HOLD_W::new(self, 15)
+    }
+    #[doc = "Bit 16 - hold rtc pad-16"]
+    #[inline(always)]
+    pub fn x32n_hold(&mut self) -> X32N_HOLD_W<PAD_HOLD_SPEC> {
+        X32N_HOLD_W::new(self, 16)
+    }
+    #[doc = "Bit 17 - hold rtc pad-17"]
+    #[inline(always)]
+    pub fn pdac1_hold(&mut self) -> PDAC1_HOLD_W<PAD_HOLD_SPEC> {
+        PDAC1_HOLD_W::new(self, 17)
+    }
+    #[doc = "Bit 18 - hold rtc pad-18"]
+    #[inline(always)]
+    pub fn pdac2_hold(&mut self) -> PDAC2_HOLD_W<PAD_HOLD_SPEC> {
+        PDAC2_HOLD_W::new(self, 18)
+    }
+    #[doc = "Bit 19 - hold rtc pad-19"]
+    #[inline(always)]
+    pub fn pad19_hold(&mut self) -> PAD19_HOLD_W<PAD_HOLD_SPEC> {
+        PAD19_HOLD_W::new(self, 19)
+    }
+    #[doc = "Bit 20 - hold rtc pad-20"]
+    #[inline(always)]
+    pub fn pad20_hold(&mut self) -> PAD20_HOLD_W<PAD_HOLD_SPEC> {
+        PAD20_HOLD_W::new(self, 20)
+    }
+    #[doc = "Bit 21 - hold rtc pad-21"]
+    #[inline(always)]
+    pub fn pad21_hold(&mut self) -> PAD21_HOLD_W<PAD_HOLD_SPEC> {
+        PAD21_HOLD_W::new(self, 21)
+    }
+}
+#[doc = "rtc pad hold configure\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_hold::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_hold::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct PAD_HOLD_SPEC;
+impl crate::RegisterSpec for PAD_HOLD_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`pad_hold::R`](R) reader structure"]
+impl crate::Readable for PAD_HOLD_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`pad_hold::W`](W) writer structure"]
+impl crate::Writable for PAD_HOLD_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets PAD_HOLD to value 0"]
+impl crate::Resettable for PAD_HOLD_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_cntl/pg_ctrl.rs

@@ -0,0 +1,107 @@
+#[doc = "Register `PG_CTRL` reader"]
+pub type R = crate::R<PG_CTRL_SPEC>;
+#[doc = "Register `PG_CTRL` writer"]
+pub type W = crate::W<PG_CTRL_SPEC>;
+#[doc = "Field `POWER_GLITCH_DSENSE` reader - GLITCH_DSENSE"]
+pub type POWER_GLITCH_DSENSE_R = crate::FieldReader;
+#[doc = "Field `POWER_GLITCH_DSENSE` writer - GLITCH_DSENSE"]
+pub type POWER_GLITCH_DSENSE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `POWER_GLITCH_FORCE_PD` reader - force power glitch disable"]
+pub type POWER_GLITCH_FORCE_PD_R = crate::BitReader;
+#[doc = "Field `POWER_GLITCH_FORCE_PD` writer - force power glitch disable"]
+pub type POWER_GLITCH_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `POWER_GLITCH_FORCE_PU` reader - force power glitch enable"]
+pub type POWER_GLITCH_FORCE_PU_R = crate::BitReader;
+#[doc = "Field `POWER_GLITCH_FORCE_PU` writer - force power glitch enable"]
+pub type POWER_GLITCH_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `POWER_GLITCH_EFUSE_SEL` reader - select use analog fib signal"]
+pub type POWER_GLITCH_EFUSE_SEL_R = crate::BitReader;
+#[doc = "Field `POWER_GLITCH_EFUSE_SEL` writer - select use analog fib signal"]
+pub type POWER_GLITCH_EFUSE_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `POWER_GLITCH_EN` reader - enable power glitch"]
+pub type POWER_GLITCH_EN_R = crate::BitReader;
+#[doc = "Field `POWER_GLITCH_EN` writer - enable power glitch"]
+pub type POWER_GLITCH_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 26:27 - GLITCH_DSENSE"]
+    #[inline(always)]
+    pub fn power_glitch_dsense(&self) -> POWER_GLITCH_DSENSE_R {
+        POWER_GLITCH_DSENSE_R::new(((self.bits >> 26) & 3) as u8)
+    }
+    #[doc = "Bit 28 - force power glitch disable"]
+    #[inline(always)]
+    pub fn power_glitch_force_pd(&self) -> POWER_GLITCH_FORCE_PD_R {
+        POWER_GLITCH_FORCE_PD_R::new(((self.bits >> 28) & 1) != 0)
+    }
+    #[doc = "Bit 29 - force power glitch enable"]
+    #[inline(always)]
+    pub fn power_glitch_force_pu(&self) -> POWER_GLITCH_FORCE_PU_R {
+        POWER_GLITCH_FORCE_PU_R::new(((self.bits >> 29) & 1) != 0)
+    }
+    #[doc = "Bit 30 - select use analog fib signal"]
+    #[inline(always)]
+    pub fn power_glitch_efuse_sel(&self) -> POWER_GLITCH_EFUSE_SEL_R {
+        POWER_GLITCH_EFUSE_SEL_R::new(((self.bits >> 30) & 1) != 0)
+    }
+    #[doc = "Bit 31 - enable power glitch"]
+    #[inline(always)]
+    pub fn power_glitch_en(&self) -> POWER_GLITCH_EN_R {
+        POWER_GLITCH_EN_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("PG_CTRL")
+            .field("power_glitch_dsense", &self.power_glitch_dsense())
+            .field("power_glitch_force_pd", &self.power_glitch_force_pd())
+            .field("power_glitch_force_pu", &self.power_glitch_force_pu())
+            .field("power_glitch_efuse_sel", &self.power_glitch_efuse_sel())
+            .field("power_glitch_en", &self.power_glitch_en())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 26:27 - GLITCH_DSENSE"]
+    #[inline(always)]
+    pub fn power_glitch_dsense(&mut self) -> POWER_GLITCH_DSENSE_W<PG_CTRL_SPEC> {
+        POWER_GLITCH_DSENSE_W::new(self, 26)
+    }
+    #[doc = "Bit 28 - force power glitch disable"]
+    #[inline(always)]
+    pub fn power_glitch_force_pd(&mut self) -> POWER_GLITCH_FORCE_PD_W<PG_CTRL_SPEC> {
+        POWER_GLITCH_FORCE_PD_W::new(self, 28)
+    }
+    #[doc = "Bit 29 - force power glitch enable"]
+    #[inline(always)]
+    pub fn power_glitch_force_pu(&mut self) -> POWER_GLITCH_FORCE_PU_W<PG_CTRL_SPEC> {
+        POWER_GLITCH_FORCE_PU_W::new(self, 29)
+    }
+    #[doc = "Bit 30 - select use analog fib signal"]
+    #[inline(always)]
+    pub fn power_glitch_efuse_sel(&mut self) -> POWER_GLITCH_EFUSE_SEL_W<PG_CTRL_SPEC> {
+        POWER_GLITCH_EFUSE_SEL_W::new(self, 30)
+    }
+    #[doc = "Bit 31 - enable power glitch"]
+    #[inline(always)]
+    pub fn power_glitch_en(&mut self) -> POWER_GLITCH_EN_W<PG_CTRL_SPEC> {
+        POWER_GLITCH_EN_W::new(self, 31)
+    }
+}
+#[doc = "configure power glitch\n\nYou can [`read`](crate::Reg::read) this register and get [`pg_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pg_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct PG_CTRL_SPEC;
+impl crate::RegisterSpec for PG_CTRL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`pg_ctrl::R`](R) reader structure"]
+impl crate::Readable for PG_CTRL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`pg_ctrl::W`](W) writer structure"]
+impl crate::Writable for PG_CTRL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets PG_CTRL to value 0"]
+impl crate::Resettable for PG_CTRL_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_cntl/pwc.rs

@@ -0,0 +1,272 @@
+#[doc = "Register `PWC` reader"]
+pub type R = crate::R<PWC_SPEC>;
+#[doc = "Register `PWC` writer"]
+pub type W = crate::W<PWC_SPEC>;
+#[doc = "Field `FASTMEM_FORCE_NOISO` reader - Fast RTC memory force no ISO"]
+pub type FASTMEM_FORCE_NOISO_R = crate::BitReader;
+#[doc = "Field `FASTMEM_FORCE_NOISO` writer - Fast RTC memory force no ISO"]
+pub type FASTMEM_FORCE_NOISO_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FASTMEM_FORCE_ISO` reader - Fast RTC memory force ISO"]
+pub type FASTMEM_FORCE_ISO_R = crate::BitReader;
+#[doc = "Field `FASTMEM_FORCE_ISO` writer - Fast RTC memory force ISO"]
+pub type FASTMEM_FORCE_ISO_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SLOWMEM_FORCE_NOISO` reader - RTC memory force no ISO"]
+pub type SLOWMEM_FORCE_NOISO_R = crate::BitReader;
+#[doc = "Field `SLOWMEM_FORCE_NOISO` writer - RTC memory force no ISO"]
+pub type SLOWMEM_FORCE_NOISO_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SLOWMEM_FORCE_ISO` reader - RTC memory force ISO"]
+pub type SLOWMEM_FORCE_ISO_R = crate::BitReader;
+#[doc = "Field `SLOWMEM_FORCE_ISO` writer - RTC memory force ISO"]
+pub type SLOWMEM_FORCE_ISO_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FORCE_ISO` reader - rtc_peri force ISO"]
+pub type FORCE_ISO_R = crate::BitReader;
+#[doc = "Field `FORCE_ISO` writer - rtc_peri force ISO"]
+pub type FORCE_ISO_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FORCE_NOISO` reader - rtc_peri force no ISO"]
+pub type FORCE_NOISO_R = crate::BitReader;
+#[doc = "Field `FORCE_NOISO` writer - rtc_peri force no ISO"]
+pub type FORCE_NOISO_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FASTMEM_FOLW_CPU` reader - 1: Fast RTC memory PD following CPU, 0: fast RTC memory PD following RTC state machine"]
+pub type FASTMEM_FOLW_CPU_R = crate::BitReader;
+#[doc = "Field `FASTMEM_FOLW_CPU` writer - 1: Fast RTC memory PD following CPU, 0: fast RTC memory PD following RTC state machine"]
+pub type FASTMEM_FOLW_CPU_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FASTMEM_FORCE_LPD` reader - Fast RTC memory force PD"]
+pub type FASTMEM_FORCE_LPD_R = crate::BitReader;
+#[doc = "Field `FASTMEM_FORCE_LPD` writer - Fast RTC memory force PD"]
+pub type FASTMEM_FORCE_LPD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FASTMEM_FORCE_LPU` reader - Fast RTC memory force no PD"]
+pub type FASTMEM_FORCE_LPU_R = crate::BitReader;
+#[doc = "Field `FASTMEM_FORCE_LPU` writer - Fast RTC memory force no PD"]
+pub type FASTMEM_FORCE_LPU_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SLOWMEM_FOLW_CPU` reader - 1: RTC memory PD following CPU, 0: RTC memory PD following RTC state machine"]
+pub type SLOWMEM_FOLW_CPU_R = crate::BitReader;
+#[doc = "Field `SLOWMEM_FOLW_CPU` writer - 1: RTC memory PD following CPU, 0: RTC memory PD following RTC state machine"]
+pub type SLOWMEM_FOLW_CPU_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SLOWMEM_FORCE_LPD` reader - RTC memory force PD"]
+pub type SLOWMEM_FORCE_LPD_R = crate::BitReader;
+#[doc = "Field `SLOWMEM_FORCE_LPD` writer - RTC memory force PD"]
+pub type SLOWMEM_FORCE_LPD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SLOWMEM_FORCE_LPU` reader - RTC memory force no PD"]
+pub type SLOWMEM_FORCE_LPU_R = crate::BitReader;
+#[doc = "Field `SLOWMEM_FORCE_LPU` writer - RTC memory force no PD"]
+pub type SLOWMEM_FORCE_LPU_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FORCE_PD` reader - rtc_peri force power down"]
+pub type FORCE_PD_R = crate::BitReader;
+#[doc = "Field `FORCE_PD` writer - rtc_peri force power down"]
+pub type FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FORCE_PU` reader - rtc_peri force power up"]
+pub type FORCE_PU_R = crate::BitReader;
+#[doc = "Field `FORCE_PU` writer - rtc_peri force power up"]
+pub type FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PD_EN` reader - enable power down rtc_peri in sleep"]
+pub type PD_EN_R = crate::BitReader;
+#[doc = "Field `PD_EN` writer - enable power down rtc_peri in sleep"]
+pub type PD_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PAD_FORCE_HOLD` reader - rtc pad force hold"]
+pub type PAD_FORCE_HOLD_R = crate::BitReader;
+#[doc = "Field `PAD_FORCE_HOLD` writer - rtc pad force hold"]
+pub type PAD_FORCE_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Fast RTC memory force no ISO"]
+    #[inline(always)]
+    pub fn fastmem_force_noiso(&self) -> FASTMEM_FORCE_NOISO_R {
+        FASTMEM_FORCE_NOISO_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Fast RTC memory force ISO"]
+    #[inline(always)]
+    pub fn fastmem_force_iso(&self) -> FASTMEM_FORCE_ISO_R {
+        FASTMEM_FORCE_ISO_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - RTC memory force no ISO"]
+    #[inline(always)]
+    pub fn slowmem_force_noiso(&self) -> SLOWMEM_FORCE_NOISO_R {
+        SLOWMEM_FORCE_NOISO_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - RTC memory force ISO"]
+    #[inline(always)]
+    pub fn slowmem_force_iso(&self) -> SLOWMEM_FORCE_ISO_R {
+        SLOWMEM_FORCE_ISO_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - rtc_peri force ISO"]
+    #[inline(always)]
+    pub fn force_iso(&self) -> FORCE_ISO_R {
+        FORCE_ISO_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - rtc_peri force no ISO"]
+    #[inline(always)]
+    pub fn force_noiso(&self) -> FORCE_NOISO_R {
+        FORCE_NOISO_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - 1: Fast RTC memory PD following CPU, 0: fast RTC memory PD following RTC state machine"]
+    #[inline(always)]
+    pub fn fastmem_folw_cpu(&self) -> FASTMEM_FOLW_CPU_R {
+        FASTMEM_FOLW_CPU_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - Fast RTC memory force PD"]
+    #[inline(always)]
+    pub fn fastmem_force_lpd(&self) -> FASTMEM_FORCE_LPD_R {
+        FASTMEM_FORCE_LPD_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - Fast RTC memory force no PD"]
+    #[inline(always)]
+    pub fn fastmem_force_lpu(&self) -> FASTMEM_FORCE_LPU_R {
+        FASTMEM_FORCE_LPU_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - 1: RTC memory PD following CPU, 0: RTC memory PD following RTC state machine"]
+    #[inline(always)]
+    pub fn slowmem_folw_cpu(&self) -> SLOWMEM_FOLW_CPU_R {
+        SLOWMEM_FOLW_CPU_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 10 - RTC memory force PD"]
+    #[inline(always)]
+    pub fn slowmem_force_lpd(&self) -> SLOWMEM_FORCE_LPD_R {
+        SLOWMEM_FORCE_LPD_R::new(((self.bits >> 10) & 1) != 0)
+    }
+    #[doc = "Bit 11 - RTC memory force no PD"]
+    #[inline(always)]
+    pub fn slowmem_force_lpu(&self) -> SLOWMEM_FORCE_LPU_R {
+        SLOWMEM_FORCE_LPU_R::new(((self.bits >> 11) & 1) != 0)
+    }
+    #[doc = "Bit 18 - rtc_peri force power down"]
+    #[inline(always)]
+    pub fn force_pd(&self) -> FORCE_PD_R {
+        FORCE_PD_R::new(((self.bits >> 18) & 1) != 0)
+    }
+    #[doc = "Bit 19 - rtc_peri force power up"]
+    #[inline(always)]
+    pub fn force_pu(&self) -> FORCE_PU_R {
+        FORCE_PU_R::new(((self.bits >> 19) & 1) != 0)
+    }
+    #[doc = "Bit 20 - enable power down rtc_peri in sleep"]
+    #[inline(always)]
+    pub fn pd_en(&self) -> PD_EN_R {
+        PD_EN_R::new(((self.bits >> 20) & 1) != 0)
+    }
+    #[doc = "Bit 21 - rtc pad force hold"]
+    #[inline(always)]
+    pub fn pad_force_hold(&self) -> PAD_FORCE_HOLD_R {
+        PAD_FORCE_HOLD_R::new(((self.bits >> 21) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("PWC")
+            .field("fastmem_force_noiso", &self.fastmem_force_noiso())
+            .field("fastmem_force_iso", &self.fastmem_force_iso())
+            .field("slowmem_force_noiso", &self.slowmem_force_noiso())
+            .field("slowmem_force_iso", &self.slowmem_force_iso())
+            .field("force_iso", &self.force_iso())
+            .field("force_noiso", &self.force_noiso())
+            .field("fastmem_folw_cpu", &self.fastmem_folw_cpu())
+            .field("fastmem_force_lpd", &self.fastmem_force_lpd())
+            .field("fastmem_force_lpu", &self.fastmem_force_lpu())
+            .field("slowmem_folw_cpu", &self.slowmem_folw_cpu())
+            .field("slowmem_force_lpd", &self.slowmem_force_lpd())
+            .field("slowmem_force_lpu", &self.slowmem_force_lpu())
+            .field("force_pd", &self.force_pd())
+            .field("force_pu", &self.force_pu())
+            .field("pd_en", &self.pd_en())
+            .field("pad_force_hold", &self.pad_force_hold())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Fast RTC memory force no ISO"]
+    #[inline(always)]
+    pub fn fastmem_force_noiso(&mut self) -> FASTMEM_FORCE_NOISO_W<PWC_SPEC> {
+        FASTMEM_FORCE_NOISO_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - Fast RTC memory force ISO"]
+    #[inline(always)]
+    pub fn fastmem_force_iso(&mut self) -> FASTMEM_FORCE_ISO_W<PWC_SPEC> {
+        FASTMEM_FORCE_ISO_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - RTC memory force no ISO"]
+    #[inline(always)]
+    pub fn slowmem_force_noiso(&mut self) -> SLOWMEM_FORCE_NOISO_W<PWC_SPEC> {
+        SLOWMEM_FORCE_NOISO_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - RTC memory force ISO"]
+    #[inline(always)]
+    pub fn slowmem_force_iso(&mut self) -> SLOWMEM_FORCE_ISO_W<PWC_SPEC> {
+        SLOWMEM_FORCE_ISO_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - rtc_peri force ISO"]
+    #[inline(always)]
+    pub fn force_iso(&mut self) -> FORCE_ISO_W<PWC_SPEC> {
+        FORCE_ISO_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - rtc_peri force no ISO"]
+    #[inline(always)]
+    pub fn force_noiso(&mut self) -> FORCE_NOISO_W<PWC_SPEC> {
+        FORCE_NOISO_W::new(self, 5)
+    }
+    #[doc = "Bit 6 - 1: Fast RTC memory PD following CPU, 0: fast RTC memory PD following RTC state machine"]
+    #[inline(always)]
+    pub fn fastmem_folw_cpu(&mut self) -> FASTMEM_FOLW_CPU_W<PWC_SPEC> {
+        FASTMEM_FOLW_CPU_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - Fast RTC memory force PD"]
+    #[inline(always)]
+    pub fn fastmem_force_lpd(&mut self) -> FASTMEM_FORCE_LPD_W<PWC_SPEC> {
+        FASTMEM_FORCE_LPD_W::new(self, 7)
+    }
+    #[doc = "Bit 8 - Fast RTC memory force no PD"]
+    #[inline(always)]
+    pub fn fastmem_force_lpu(&mut self) -> FASTMEM_FORCE_LPU_W<PWC_SPEC> {
+        FASTMEM_FORCE_LPU_W::new(self, 8)
+    }
+    #[doc = "Bit 9 - 1: RTC memory PD following CPU, 0: RTC memory PD following RTC state machine"]
+    #[inline(always)]
+    pub fn slowmem_folw_cpu(&mut self) -> SLOWMEM_FOLW_CPU_W<PWC_SPEC> {
+        SLOWMEM_FOLW_CPU_W::new(self, 9)
+    }
+    #[doc = "Bit 10 - RTC memory force PD"]
+    #[inline(always)]
+    pub fn slowmem_force_lpd(&mut self) -> SLOWMEM_FORCE_LPD_W<PWC_SPEC> {
+        SLOWMEM_FORCE_LPD_W::new(self, 10)
+    }
+    #[doc = "Bit 11 - RTC memory force no PD"]
+    #[inline(always)]
+    pub fn slowmem_force_lpu(&mut self) -> SLOWMEM_FORCE_LPU_W<PWC_SPEC> {
+        SLOWMEM_FORCE_LPU_W::new(self, 11)
+    }
+    #[doc = "Bit 18 - rtc_peri force power down"]
+    #[inline(always)]
+    pub fn force_pd(&mut self) -> FORCE_PD_W<PWC_SPEC> {
+        FORCE_PD_W::new(self, 18)
+    }
+    #[doc = "Bit 19 - rtc_peri force power up"]
+    #[inline(always)]
+    pub fn force_pu(&mut self) -> FORCE_PU_W<PWC_SPEC> {
+        FORCE_PU_W::new(self, 19)
+    }
+    #[doc = "Bit 20 - enable power down rtc_peri in sleep"]
+    #[inline(always)]
+    pub fn pd_en(&mut self) -> PD_EN_W<PWC_SPEC> {
+        PD_EN_W::new(self, 20)
+    }
+    #[doc = "Bit 21 - rtc pad force hold"]
+    #[inline(always)]
+    pub fn pad_force_hold(&mut self) -> PAD_FORCE_HOLD_W<PWC_SPEC> {
+        PAD_FORCE_HOLD_W::new(self, 21)
+    }
+}
+#[doc = "configure rtc power\n\nYou can [`read`](crate::Reg::read) this register and get [`pwc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct PWC_SPEC;
+impl crate::RegisterSpec for PWC_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`pwc::R`](R) reader structure"]
+impl crate::Readable for PWC_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`pwc::W`](W) writer structure"]
+impl crate::Writable for PWC_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets PWC to value 0x0925"]
+impl crate::Resettable for PWC_SPEC {
+    const RESET_VALUE: u32 = 0x0925;
+}

vendor/esp32s3/src/rtc_cntl/regulator_drv_ctrl.rs

@@ -0,0 +1,94 @@
+#[doc = "Register `REGULATOR_DRV_CTRL` reader"]
+pub type R = crate::R<REGULATOR_DRV_CTRL_SPEC>;
+#[doc = "Register `REGULATOR_DRV_CTRL` writer"]
+pub type W = crate::W<REGULATOR_DRV_CTRL_SPEC>;
+#[doc = "Field `REGULATOR_DRV_B_MONITOR` reader - No public"]
+pub type REGULATOR_DRV_B_MONITOR_R = crate::FieldReader;
+#[doc = "Field `REGULATOR_DRV_B_MONITOR` writer - No public"]
+pub type REGULATOR_DRV_B_MONITOR_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
+#[doc = "Field `REGULATOR_DRV_B_SLP` reader - No public"]
+pub type REGULATOR_DRV_B_SLP_R = crate::FieldReader;
+#[doc = "Field `REGULATOR_DRV_B_SLP` writer - No public"]
+pub type REGULATOR_DRV_B_SLP_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
+#[doc = "Field `DG_VDD_DRV_B_SLP` reader - No public"]
+pub type DG_VDD_DRV_B_SLP_R = crate::FieldReader;
+#[doc = "Field `DG_VDD_DRV_B_SLP` writer - No public"]
+pub type DG_VDD_DRV_B_SLP_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+#[doc = "Field `DG_VDD_DRV_B_MONITOR` reader - No public"]
+pub type DG_VDD_DRV_B_MONITOR_R = crate::FieldReader;
+#[doc = "Field `DG_VDD_DRV_B_MONITOR` writer - No public"]
+pub type DG_VDD_DRV_B_MONITOR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+impl R {
+    #[doc = "Bits 0:5 - No public"]
+    #[inline(always)]
+    pub fn regulator_drv_b_monitor(&self) -> REGULATOR_DRV_B_MONITOR_R {
+        REGULATOR_DRV_B_MONITOR_R::new((self.bits & 0x3f) as u8)
+    }
+    #[doc = "Bits 6:11 - No public"]
+    #[inline(always)]
+    pub fn regulator_drv_b_slp(&self) -> REGULATOR_DRV_B_SLP_R {
+        REGULATOR_DRV_B_SLP_R::new(((self.bits >> 6) & 0x3f) as u8)
+    }
+    #[doc = "Bits 12:19 - No public"]
+    #[inline(always)]
+    pub fn dg_vdd_drv_b_slp(&self) -> DG_VDD_DRV_B_SLP_R {
+        DG_VDD_DRV_B_SLP_R::new(((self.bits >> 12) & 0xff) as u8)
+    }
+    #[doc = "Bits 20:27 - No public"]
+    #[inline(always)]
+    pub fn dg_vdd_drv_b_monitor(&self) -> DG_VDD_DRV_B_MONITOR_R {
+        DG_VDD_DRV_B_MONITOR_R::new(((self.bits >> 20) & 0xff) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("REGULATOR_DRV_CTRL")
+            .field("regulator_drv_b_monitor", &self.regulator_drv_b_monitor())
+            .field("regulator_drv_b_slp", &self.regulator_drv_b_slp())
+            .field("dg_vdd_drv_b_slp", &self.dg_vdd_drv_b_slp())
+            .field("dg_vdd_drv_b_monitor", &self.dg_vdd_drv_b_monitor())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:5 - No public"]
+    #[inline(always)]
+    pub fn regulator_drv_b_monitor(
+        &mut self,
+    ) -> REGULATOR_DRV_B_MONITOR_W<REGULATOR_DRV_CTRL_SPEC> {
+        REGULATOR_DRV_B_MONITOR_W::new(self, 0)
+    }
+    #[doc = "Bits 6:11 - No public"]
+    #[inline(always)]
+    pub fn regulator_drv_b_slp(&mut self) -> REGULATOR_DRV_B_SLP_W<REGULATOR_DRV_CTRL_SPEC> {
+        REGULATOR_DRV_B_SLP_W::new(self, 6)
+    }
+    #[doc = "Bits 12:19 - No public"]
+    #[inline(always)]
+    pub fn dg_vdd_drv_b_slp(&mut self) -> DG_VDD_DRV_B_SLP_W<REGULATOR_DRV_CTRL_SPEC> {
+        DG_VDD_DRV_B_SLP_W::new(self, 12)
+    }
+    #[doc = "Bits 20:27 - No public"]
+    #[inline(always)]
+    pub fn dg_vdd_drv_b_monitor(&mut self) -> DG_VDD_DRV_B_MONITOR_W<REGULATOR_DRV_CTRL_SPEC> {
+        DG_VDD_DRV_B_MONITOR_W::new(self, 20)
+    }
+}
+#[doc = "No public\n\nYou can [`read`](crate::Reg::read) this register and get [`regulator_drv_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`regulator_drv_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct REGULATOR_DRV_CTRL_SPEC;
+impl crate::RegisterSpec for REGULATOR_DRV_CTRL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`regulator_drv_ctrl::R`](R) reader structure"]
+impl crate::Readable for REGULATOR_DRV_CTRL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`regulator_drv_ctrl::W`](W) writer structure"]
+impl crate::Writable for REGULATOR_DRV_CTRL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets REGULATOR_DRV_CTRL to value 0"]
+impl crate::Resettable for REGULATOR_DRV_CTRL_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_cntl/reset_state.rs

@@ -0,0 +1,198 @@
+#[doc = "Register `RESET_STATE` reader"]
+pub type R = crate::R<RESET_STATE_SPEC>;
+#[doc = "Register `RESET_STATE` writer"]
+pub type W = crate::W<RESET_STATE_SPEC>;
+#[doc = "Field `RESET_CAUSE_PROCPU` reader - reset cause of PRO CPU"]
+pub type RESET_CAUSE_PROCPU_R = crate::FieldReader;
+#[doc = "Field `RESET_CAUSE_APPCPU` reader - reset cause of APP CPU"]
+pub type RESET_CAUSE_APPCPU_R = crate::FieldReader;
+#[doc = "Field `APPCPU_STAT_VECTOR_SEL` reader - APP CPU state vector sel"]
+pub type APPCPU_STAT_VECTOR_SEL_R = crate::BitReader;
+#[doc = "Field `APPCPU_STAT_VECTOR_SEL` writer - APP CPU state vector sel"]
+pub type APPCPU_STAT_VECTOR_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PROCPU_STAT_VECTOR_SEL` reader - PRO CPU state vector sel"]
+pub type PROCPU_STAT_VECTOR_SEL_R = crate::BitReader;
+#[doc = "Field `PROCPU_STAT_VECTOR_SEL` writer - PRO CPU state vector sel"]
+pub type PROCPU_STAT_VECTOR_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RESET_FLAG_PROCPU` reader - PRO CPU reset_flag"]
+pub type RESET_FLAG_PROCPU_R = crate::BitReader;
+#[doc = "Field `RESET_FLAG_APPCPU` reader - APP CPU reset flag"]
+pub type RESET_FLAG_APPCPU_R = crate::BitReader;
+#[doc = "Field `RESET_FLAG_PROCPU_CLR` writer - clear PRO CPU reset_flag"]
+pub type RESET_FLAG_PROCPU_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RESET_FLAG_APPCPU_CLR` writer - clear APP CPU reset flag"]
+pub type RESET_FLAG_APPCPU_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `APPCPU_OCD_HALT_ON_RESET` reader - APPCPU OcdHaltOnReset"]
+pub type APPCPU_OCD_HALT_ON_RESET_R = crate::BitReader;
+#[doc = "Field `APPCPU_OCD_HALT_ON_RESET` writer - APPCPU OcdHaltOnReset"]
+pub type APPCPU_OCD_HALT_ON_RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PROCPU_OCD_HALT_ON_RESET` reader - PROCPU OcdHaltOnReset"]
+pub type PROCPU_OCD_HALT_ON_RESET_R = crate::BitReader;
+#[doc = "Field `PROCPU_OCD_HALT_ON_RESET` writer - PROCPU OcdHaltOnReset"]
+pub type PROCPU_OCD_HALT_ON_RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RESET_FLAG_JTAG_PROCPU` reader - jtag reset flag"]
+pub type RESET_FLAG_JTAG_PROCPU_R = crate::BitReader;
+#[doc = "Field `RESET_FLAG_JTAG_APPCPU` reader - jtag reset flag"]
+pub type RESET_FLAG_JTAG_APPCPU_R = crate::BitReader;
+#[doc = "Field `RESET_FLAG_JTAG_PROCPU_CLR` writer - clear jtag reset flag"]
+pub type RESET_FLAG_JTAG_PROCPU_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RESET_FLAG_JTAG_APPCPU_CLR` writer - clear jtag reset flag"]
+pub type RESET_FLAG_JTAG_APPCPU_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `APP_DRESET_MASK` reader - bypass cpu1 dreset"]
+pub type APP_DRESET_MASK_R = crate::BitReader;
+#[doc = "Field `APP_DRESET_MASK` writer - bypass cpu1 dreset"]
+pub type APP_DRESET_MASK_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PRO_DRESET_MASK` reader - bypass cpu0 dreset"]
+pub type PRO_DRESET_MASK_R = crate::BitReader;
+#[doc = "Field `PRO_DRESET_MASK` writer - bypass cpu0 dreset"]
+pub type PRO_DRESET_MASK_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 0:5 - reset cause of PRO CPU"]
+    #[inline(always)]
+    pub fn reset_cause_procpu(&self) -> RESET_CAUSE_PROCPU_R {
+        RESET_CAUSE_PROCPU_R::new((self.bits & 0x3f) as u8)
+    }
+    #[doc = "Bits 6:11 - reset cause of APP CPU"]
+    #[inline(always)]
+    pub fn reset_cause_appcpu(&self) -> RESET_CAUSE_APPCPU_R {
+        RESET_CAUSE_APPCPU_R::new(((self.bits >> 6) & 0x3f) as u8)
+    }
+    #[doc = "Bit 12 - APP CPU state vector sel"]
+    #[inline(always)]
+    pub fn appcpu_stat_vector_sel(&self) -> APPCPU_STAT_VECTOR_SEL_R {
+        APPCPU_STAT_VECTOR_SEL_R::new(((self.bits >> 12) & 1) != 0)
+    }
+    #[doc = "Bit 13 - PRO CPU state vector sel"]
+    #[inline(always)]
+    pub fn procpu_stat_vector_sel(&self) -> PROCPU_STAT_VECTOR_SEL_R {
+        PROCPU_STAT_VECTOR_SEL_R::new(((self.bits >> 13) & 1) != 0)
+    }
+    #[doc = "Bit 14 - PRO CPU reset_flag"]
+    #[inline(always)]
+    pub fn reset_flag_procpu(&self) -> RESET_FLAG_PROCPU_R {
+        RESET_FLAG_PROCPU_R::new(((self.bits >> 14) & 1) != 0)
+    }
+    #[doc = "Bit 15 - APP CPU reset flag"]
+    #[inline(always)]
+    pub fn reset_flag_appcpu(&self) -> RESET_FLAG_APPCPU_R {
+        RESET_FLAG_APPCPU_R::new(((self.bits >> 15) & 1) != 0)
+    }
+    #[doc = "Bit 18 - APPCPU OcdHaltOnReset"]
+    #[inline(always)]
+    pub fn appcpu_ocd_halt_on_reset(&self) -> APPCPU_OCD_HALT_ON_RESET_R {
+        APPCPU_OCD_HALT_ON_RESET_R::new(((self.bits >> 18) & 1) != 0)
+    }
+    #[doc = "Bit 19 - PROCPU OcdHaltOnReset"]
+    #[inline(always)]
+    pub fn procpu_ocd_halt_on_reset(&self) -> PROCPU_OCD_HALT_ON_RESET_R {
+        PROCPU_OCD_HALT_ON_RESET_R::new(((self.bits >> 19) & 1) != 0)
+    }
+    #[doc = "Bit 20 - jtag reset flag"]
+    #[inline(always)]
+    pub fn reset_flag_jtag_procpu(&self) -> RESET_FLAG_JTAG_PROCPU_R {
+        RESET_FLAG_JTAG_PROCPU_R::new(((self.bits >> 20) & 1) != 0)
+    }
+    #[doc = "Bit 21 - jtag reset flag"]
+    #[inline(always)]
+    pub fn reset_flag_jtag_appcpu(&self) -> RESET_FLAG_JTAG_APPCPU_R {
+        RESET_FLAG_JTAG_APPCPU_R::new(((self.bits >> 21) & 1) != 0)
+    }
+    #[doc = "Bit 24 - bypass cpu1 dreset"]
+    #[inline(always)]
+    pub fn app_dreset_mask(&self) -> APP_DRESET_MASK_R {
+        APP_DRESET_MASK_R::new(((self.bits >> 24) & 1) != 0)
+    }
+    #[doc = "Bit 25 - bypass cpu0 dreset"]
+    #[inline(always)]
+    pub fn pro_dreset_mask(&self) -> PRO_DRESET_MASK_R {
+        PRO_DRESET_MASK_R::new(((self.bits >> 25) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("RESET_STATE")
+            .field("reset_cause_procpu", &self.reset_cause_procpu())
+            .field("reset_cause_appcpu", &self.reset_cause_appcpu())
+            .field("appcpu_stat_vector_sel", &self.appcpu_stat_vector_sel())
+            .field("procpu_stat_vector_sel", &self.procpu_stat_vector_sel())
+            .field("reset_flag_procpu", &self.reset_flag_procpu())
+            .field("reset_flag_appcpu", &self.reset_flag_appcpu())
+            .field("appcpu_ocd_halt_on_reset", &self.appcpu_ocd_halt_on_reset())
+            .field("procpu_ocd_halt_on_reset", &self.procpu_ocd_halt_on_reset())
+            .field("reset_flag_jtag_procpu", &self.reset_flag_jtag_procpu())
+            .field("reset_flag_jtag_appcpu", &self.reset_flag_jtag_appcpu())
+            .field("app_dreset_mask", &self.app_dreset_mask())
+            .field("pro_dreset_mask", &self.pro_dreset_mask())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 12 - APP CPU state vector sel"]
+    #[inline(always)]
+    pub fn appcpu_stat_vector_sel(&mut self) -> APPCPU_STAT_VECTOR_SEL_W<RESET_STATE_SPEC> {
+        APPCPU_STAT_VECTOR_SEL_W::new(self, 12)
+    }
+    #[doc = "Bit 13 - PRO CPU state vector sel"]
+    #[inline(always)]
+    pub fn procpu_stat_vector_sel(&mut self) -> PROCPU_STAT_VECTOR_SEL_W<RESET_STATE_SPEC> {
+        PROCPU_STAT_VECTOR_SEL_W::new(self, 13)
+    }
+    #[doc = "Bit 16 - clear PRO CPU reset_flag"]
+    #[inline(always)]
+    pub fn reset_flag_procpu_clr(&mut self) -> RESET_FLAG_PROCPU_CLR_W<RESET_STATE_SPEC> {
+        RESET_FLAG_PROCPU_CLR_W::new(self, 16)
+    }
+    #[doc = "Bit 17 - clear APP CPU reset flag"]
+    #[inline(always)]
+    pub fn reset_flag_appcpu_clr(&mut self) -> RESET_FLAG_APPCPU_CLR_W<RESET_STATE_SPEC> {
+        RESET_FLAG_APPCPU_CLR_W::new(self, 17)
+    }
+    #[doc = "Bit 18 - APPCPU OcdHaltOnReset"]
+    #[inline(always)]
+    pub fn appcpu_ocd_halt_on_reset(&mut self) -> APPCPU_OCD_HALT_ON_RESET_W<RESET_STATE_SPEC> {
+        APPCPU_OCD_HALT_ON_RESET_W::new(self, 18)
+    }
+    #[doc = "Bit 19 - PROCPU OcdHaltOnReset"]
+    #[inline(always)]
+    pub fn procpu_ocd_halt_on_reset(&mut self) -> PROCPU_OCD_HALT_ON_RESET_W<RESET_STATE_SPEC> {
+        PROCPU_OCD_HALT_ON_RESET_W::new(self, 19)
+    }
+    #[doc = "Bit 22 - clear jtag reset flag"]
+    #[inline(always)]
+    pub fn reset_flag_jtag_procpu_clr(&mut self) -> RESET_FLAG_JTAG_PROCPU_CLR_W<RESET_STATE_SPEC> {
+        RESET_FLAG_JTAG_PROCPU_CLR_W::new(self, 22)
+    }
+    #[doc = "Bit 23 - clear jtag reset flag"]
+    #[inline(always)]
+    pub fn reset_flag_jtag_appcpu_clr(&mut self) -> RESET_FLAG_JTAG_APPCPU_CLR_W<RESET_STATE_SPEC> {
+        RESET_FLAG_JTAG_APPCPU_CLR_W::new(self, 23)
+    }
+    #[doc = "Bit 24 - bypass cpu1 dreset"]
+    #[inline(always)]
+    pub fn app_dreset_mask(&mut self) -> APP_DRESET_MASK_W<RESET_STATE_SPEC> {
+        APP_DRESET_MASK_W::new(self, 24)
+    }
+    #[doc = "Bit 25 - bypass cpu0 dreset"]
+    #[inline(always)]
+    pub fn pro_dreset_mask(&mut self) -> PRO_DRESET_MASK_W<RESET_STATE_SPEC> {
+        PRO_DRESET_MASK_W::new(self, 25)
+    }
+}
+#[doc = "get reset state\n\nYou can [`read`](crate::Reg::read) this register and get [`reset_state::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reset_state::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct RESET_STATE_SPEC;
+impl crate::RegisterSpec for RESET_STATE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`reset_state::R`](R) reader structure"]
+impl crate::Readable for RESET_STATE_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`reset_state::W`](W) writer structure"]
+impl crate::Writable for RESET_STATE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets RESET_STATE to value 0x3000"]
+impl crate::Resettable for RESET_STATE_SPEC {
+    const RESET_VALUE: u32 = 0x3000;
+}

vendor/esp32s3/src/rtc_cntl/retention_ctrl.rs

@@ -0,0 +1,137 @@
+#[doc = "Register `RETENTION_CTRL` reader"]
+pub type R = crate::R<RETENTION_CTRL_SPEC>;
+#[doc = "Register `RETENTION_CTRL` writer"]
+pub type W = crate::W<RETENTION_CTRL_SPEC>;
+#[doc = "Field `RETENTION_TAG_MODE` reader - No public"]
+pub type RETENTION_TAG_MODE_R = crate::FieldReader;
+#[doc = "Field `RETENTION_TAG_MODE` writer - No public"]
+pub type RETENTION_TAG_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `RETENTION_TARGET` reader - congfigure retention target cpu and/or tag"]
+pub type RETENTION_TARGET_R = crate::FieldReader;
+#[doc = "Field `RETENTION_TARGET` writer - congfigure retention target cpu and/or tag"]
+pub type RETENTION_TARGET_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `RETENTION_CLK_SEL` reader - No public"]
+pub type RETENTION_CLK_SEL_R = crate::BitReader;
+#[doc = "Field `RETENTION_CLK_SEL` writer - No public"]
+pub type RETENTION_CLK_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RETENTION_DONE_WAIT` reader - wait retention done cycle"]
+pub type RETENTION_DONE_WAIT_R = crate::FieldReader;
+#[doc = "Field `RETENTION_DONE_WAIT` writer - wait retention done cycle"]
+pub type RETENTION_DONE_WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `RETENTION_CLKOFF_WAIT` reader - wait clk off cycle"]
+pub type RETENTION_CLKOFF_WAIT_R = crate::FieldReader;
+#[doc = "Field `RETENTION_CLKOFF_WAIT` writer - wait clk off cycle"]
+pub type RETENTION_CLKOFF_WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `RETENTION_EN` reader - enable retention"]
+pub type RETENTION_EN_R = crate::BitReader;
+#[doc = "Field `RETENTION_EN` writer - enable retention"]
+pub type RETENTION_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RETENTION_WAIT` reader - wait cycles for rention operation"]
+pub type RETENTION_WAIT_R = crate::FieldReader;
+#[doc = "Field `RETENTION_WAIT` writer - wait cycles for rention operation"]
+pub type RETENTION_WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
+impl R {
+    #[doc = "Bits 10:13 - No public"]
+    #[inline(always)]
+    pub fn retention_tag_mode(&self) -> RETENTION_TAG_MODE_R {
+        RETENTION_TAG_MODE_R::new(((self.bits >> 10) & 0x0f) as u8)
+    }
+    #[doc = "Bits 14:15 - congfigure retention target cpu and/or tag"]
+    #[inline(always)]
+    pub fn retention_target(&self) -> RETENTION_TARGET_R {
+        RETENTION_TARGET_R::new(((self.bits >> 14) & 3) as u8)
+    }
+    #[doc = "Bit 16 - No public"]
+    #[inline(always)]
+    pub fn retention_clk_sel(&self) -> RETENTION_CLK_SEL_R {
+        RETENTION_CLK_SEL_R::new(((self.bits >> 16) & 1) != 0)
+    }
+    #[doc = "Bits 17:19 - wait retention done cycle"]
+    #[inline(always)]
+    pub fn retention_done_wait(&self) -> RETENTION_DONE_WAIT_R {
+        RETENTION_DONE_WAIT_R::new(((self.bits >> 17) & 7) as u8)
+    }
+    #[doc = "Bits 20:23 - wait clk off cycle"]
+    #[inline(always)]
+    pub fn retention_clkoff_wait(&self) -> RETENTION_CLKOFF_WAIT_R {
+        RETENTION_CLKOFF_WAIT_R::new(((self.bits >> 20) & 0x0f) as u8)
+    }
+    #[doc = "Bit 24 - enable retention"]
+    #[inline(always)]
+    pub fn retention_en(&self) -> RETENTION_EN_R {
+        RETENTION_EN_R::new(((self.bits >> 24) & 1) != 0)
+    }
+    #[doc = "Bits 25:31 - wait cycles for rention operation"]
+    #[inline(always)]
+    pub fn retention_wait(&self) -> RETENTION_WAIT_R {
+        RETENTION_WAIT_R::new(((self.bits >> 25) & 0x7f) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("RETENTION_CTRL")
+            .field("retention_tag_mode", &self.retention_tag_mode())
+            .field("retention_target", &self.retention_target())
+            .field("retention_clk_sel", &self.retention_clk_sel())
+            .field("retention_done_wait", &self.retention_done_wait())
+            .field("retention_clkoff_wait", &self.retention_clkoff_wait())
+            .field("retention_en", &self.retention_en())
+            .field("retention_wait", &self.retention_wait())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 10:13 - No public"]
+    #[inline(always)]
+    pub fn retention_tag_mode(&mut self) -> RETENTION_TAG_MODE_W<RETENTION_CTRL_SPEC> {
+        RETENTION_TAG_MODE_W::new(self, 10)
+    }
+    #[doc = "Bits 14:15 - congfigure retention target cpu and/or tag"]
+    #[inline(always)]
+    pub fn retention_target(&mut self) -> RETENTION_TARGET_W<RETENTION_CTRL_SPEC> {
+        RETENTION_TARGET_W::new(self, 14)
+    }
+    #[doc = "Bit 16 - No public"]
+    #[inline(always)]
+    pub fn retention_clk_sel(&mut self) -> RETENTION_CLK_SEL_W<RETENTION_CTRL_SPEC> {
+        RETENTION_CLK_SEL_W::new(self, 16)
+    }
+    #[doc = "Bits 17:19 - wait retention done cycle"]
+    #[inline(always)]
+    pub fn retention_done_wait(&mut self) -> RETENTION_DONE_WAIT_W<RETENTION_CTRL_SPEC> {
+        RETENTION_DONE_WAIT_W::new(self, 17)
+    }
+    #[doc = "Bits 20:23 - wait clk off cycle"]
+    #[inline(always)]
+    pub fn retention_clkoff_wait(&mut self) -> RETENTION_CLKOFF_WAIT_W<RETENTION_CTRL_SPEC> {
+        RETENTION_CLKOFF_WAIT_W::new(self, 20)
+    }
+    #[doc = "Bit 24 - enable retention"]
+    #[inline(always)]
+    pub fn retention_en(&mut self) -> RETENTION_EN_W<RETENTION_CTRL_SPEC> {
+        RETENTION_EN_W::new(self, 24)
+    }
+    #[doc = "Bits 25:31 - wait cycles for rention operation"]
+    #[inline(always)]
+    pub fn retention_wait(&mut self) -> RETENTION_WAIT_W<RETENTION_CTRL_SPEC> {
+        RETENTION_WAIT_W::new(self, 25)
+    }
+}
+#[doc = "configure retention\n\nYou can [`read`](crate::Reg::read) this register and get [`retention_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`retention_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct RETENTION_CTRL_SPEC;
+impl crate::RegisterSpec for RETENTION_CTRL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`retention_ctrl::R`](R) reader structure"]
+impl crate::Readable for RETENTION_CTRL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`retention_ctrl::W`](W) writer structure"]
+impl crate::Writable for RETENTION_CTRL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets RETENTION_CTRL to value 0x2834_0000"]
+impl crate::Resettable for RETENTION_CTRL_SPEC {
+    const RESET_VALUE: u32 = 0x2834_0000;
+}

vendor/esp32s3/src/rtc_cntl/rtc.rs

@@ -0,0 +1,122 @@
+#[doc = "Register `RTC` reader"]
+pub type R = crate::R<RTC_SPEC>;
+#[doc = "Register `RTC` writer"]
+pub type W = crate::W<RTC_SPEC>;
+#[doc = "Field `DIG_REG_CAL_EN` reader - enable dig regulator cali"]
+pub type DIG_REG_CAL_EN_R = crate::BitReader;
+#[doc = "Field `DIG_REG_CAL_EN` writer - enable dig regulator cali"]
+pub type DIG_REG_CAL_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SCK_DCAP` reader - SCK_DCAP"]
+pub type SCK_DCAP_R = crate::FieldReader;
+#[doc = "Field `SCK_DCAP` writer - SCK_DCAP"]
+pub type SCK_DCAP_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+#[doc = "Field `DBOOST_FORCE_PD` reader - RTC_DBOOST force power down"]
+pub type DBOOST_FORCE_PD_R = crate::BitReader;
+#[doc = "Field `DBOOST_FORCE_PD` writer - RTC_DBOOST force power down"]
+pub type DBOOST_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DBOOST_FORCE_PU` reader - RTC_DBOOST force power up"]
+pub type DBOOST_FORCE_PU_R = crate::BitReader;
+#[doc = "Field `DBOOST_FORCE_PU` writer - RTC_DBOOST force power up"]
+pub type DBOOST_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `REGULATOR_FORCE_PD` reader - RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower )"]
+pub type REGULATOR_FORCE_PD_R = crate::BitReader;
+#[doc = "Field `REGULATOR_FORCE_PD` writer - RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower )"]
+pub type REGULATOR_FORCE_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `REGULATOR_FORCE_PU` reader - RTC_REG force power on (for RTC_REG power down means decrease the voltage to 0.8v or lower )"]
+pub type REGULATOR_FORCE_PU_R = crate::BitReader;
+#[doc = "Field `REGULATOR_FORCE_PU` writer - RTC_REG force power on (for RTC_REG power down means decrease the voltage to 0.8v or lower )"]
+pub type REGULATOR_FORCE_PU_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 7 - enable dig regulator cali"]
+    #[inline(always)]
+    pub fn dig_reg_cal_en(&self) -> DIG_REG_CAL_EN_R {
+        DIG_REG_CAL_EN_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bits 14:21 - SCK_DCAP"]
+    #[inline(always)]
+    pub fn sck_dcap(&self) -> SCK_DCAP_R {
+        SCK_DCAP_R::new(((self.bits >> 14) & 0xff) as u8)
+    }
+    #[doc = "Bit 28 - RTC_DBOOST force power down"]
+    #[inline(always)]
+    pub fn dboost_force_pd(&self) -> DBOOST_FORCE_PD_R {
+        DBOOST_FORCE_PD_R::new(((self.bits >> 28) & 1) != 0)
+    }
+    #[doc = "Bit 29 - RTC_DBOOST force power up"]
+    #[inline(always)]
+    pub fn dboost_force_pu(&self) -> DBOOST_FORCE_PU_R {
+        DBOOST_FORCE_PU_R::new(((self.bits >> 29) & 1) != 0)
+    }
+    #[doc = "Bit 30 - RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower )"]
+    #[inline(always)]
+    pub fn regulator_force_pd(&self) -> REGULATOR_FORCE_PD_R {
+        REGULATOR_FORCE_PD_R::new(((self.bits >> 30) & 1) != 0)
+    }
+    #[doc = "Bit 31 - RTC_REG force power on (for RTC_REG power down means decrease the voltage to 0.8v or lower )"]
+    #[inline(always)]
+    pub fn regulator_force_pu(&self) -> REGULATOR_FORCE_PU_R {
+        REGULATOR_FORCE_PU_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("RTC")
+            .field("dig_reg_cal_en", &self.dig_reg_cal_en())
+            .field("sck_dcap", &self.sck_dcap())
+            .field("dboost_force_pd", &self.dboost_force_pd())
+            .field("dboost_force_pu", &self.dboost_force_pu())
+            .field("regulator_force_pd", &self.regulator_force_pd())
+            .field("regulator_force_pu", &self.regulator_force_pu())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 7 - enable dig regulator cali"]
+    #[inline(always)]
+    pub fn dig_reg_cal_en(&mut self) -> DIG_REG_CAL_EN_W<RTC_SPEC> {
+        DIG_REG_CAL_EN_W::new(self, 7)
+    }
+    #[doc = "Bits 14:21 - SCK_DCAP"]
+    #[inline(always)]
+    pub fn sck_dcap(&mut self) -> SCK_DCAP_W<RTC_SPEC> {
+        SCK_DCAP_W::new(self, 14)
+    }
+    #[doc = "Bit 28 - RTC_DBOOST force power down"]
+    #[inline(always)]
+    pub fn dboost_force_pd(&mut self) -> DBOOST_FORCE_PD_W<RTC_SPEC> {
+        DBOOST_FORCE_PD_W::new(self, 28)
+    }
+    #[doc = "Bit 29 - RTC_DBOOST force power up"]
+    #[inline(always)]
+    pub fn dboost_force_pu(&mut self) -> DBOOST_FORCE_PU_W<RTC_SPEC> {
+        DBOOST_FORCE_PU_W::new(self, 29)
+    }
+    #[doc = "Bit 30 - RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower )"]
+    #[inline(always)]
+    pub fn regulator_force_pd(&mut self) -> REGULATOR_FORCE_PD_W<RTC_SPEC> {
+        REGULATOR_FORCE_PD_W::new(self, 30)
+    }
+    #[doc = "Bit 31 - RTC_REG force power on (for RTC_REG power down means decrease the voltage to 0.8v or lower )"]
+    #[inline(always)]
+    pub fn regulator_force_pu(&mut self) -> REGULATOR_FORCE_PU_W<RTC_SPEC> {
+        REGULATOR_FORCE_PU_W::new(self, 31)
+    }
+}
+#[doc = "configure rtc regulator\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct RTC_SPEC;
+impl crate::RegisterSpec for RTC_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`rtc::R`](R) reader structure"]
+impl crate::Readable for RTC_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`rtc::W`](W) writer structure"]
+impl crate::Writable for RTC_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets RTC to value 0xa000_0000"]
+impl crate::Resettable for RTC_SPEC {
+    const RESET_VALUE: u32 = 0xa000_0000;
+}

vendor/esp32s3/src/rtc_cntl/sdio_act_conf.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `SDIO_ACT_CONF` reader"]
+pub type R = crate::R<SDIO_ACT_CONF_SPEC>;
+#[doc = "Register `SDIO_ACT_CONF` writer"]
+pub type W = crate::W<SDIO_ACT_CONF_SPEC>;
+#[doc = "Field `SDIO_ACT_DNUM` reader - No public"]
+pub type SDIO_ACT_DNUM_R = crate::FieldReader<u16>;
+#[doc = "Field `SDIO_ACT_DNUM` writer - No public"]
+pub type SDIO_ACT_DNUM_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
+impl R {
+    #[doc = "Bits 22:31 - No public"]
+    #[inline(always)]
+    pub fn sdio_act_dnum(&self) -> SDIO_ACT_DNUM_R {
+        SDIO_ACT_DNUM_R::new(((self.bits >> 22) & 0x03ff) as u16)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SDIO_ACT_CONF")
+            .field("sdio_act_dnum", &self.sdio_act_dnum())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 22:31 - No public"]
+    #[inline(always)]
+    pub fn sdio_act_dnum(&mut self) -> SDIO_ACT_DNUM_W<SDIO_ACT_CONF_SPEC> {
+        SDIO_ACT_DNUM_W::new(self, 22)
+    }
+}
+#[doc = "No public\n\nYou can [`read`](crate::Reg::read) this register and get [`sdio_act_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdio_act_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SDIO_ACT_CONF_SPEC;
+impl crate::RegisterSpec for SDIO_ACT_CONF_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sdio_act_conf::R`](R) reader structure"]
+impl crate::Readable for SDIO_ACT_CONF_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sdio_act_conf::W`](W) writer structure"]
+impl crate::Writable for SDIO_ACT_CONF_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SDIO_ACT_CONF to value 0"]
+impl crate::Resettable for SDIO_ACT_CONF_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_cntl/sdio_conf.rs

@@ -0,0 +1,265 @@
+#[doc = "Register `SDIO_CONF` reader"]
+pub type R = crate::R<SDIO_CONF_SPEC>;
+#[doc = "Register `SDIO_CONF` writer"]
+pub type W = crate::W<SDIO_CONF_SPEC>;
+#[doc = "Field `SDIO_TIMER_TARGET` reader - timer count to apply reg_sdio_dcap after sdio power on"]
+pub type SDIO_TIMER_TARGET_R = crate::FieldReader;
+#[doc = "Field `SDIO_TIMER_TARGET` writer - timer count to apply reg_sdio_dcap after sdio power on"]
+pub type SDIO_TIMER_TARGET_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+#[doc = "Field `SDIO_DTHDRV` reader - Tieh = 1 mode drive ability. Initially set to 0 to limit charge current, set to 3 after several us."]
+pub type SDIO_DTHDRV_R = crate::FieldReader;
+#[doc = "Field `SDIO_DTHDRV` writer - Tieh = 1 mode drive ability. Initially set to 0 to limit charge current, set to 3 after several us."]
+pub type SDIO_DTHDRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `SDIO_DCAP` reader - ability to prevent LDO from overshoot"]
+pub type SDIO_DCAP_R = crate::FieldReader;
+#[doc = "Field `SDIO_DCAP` writer - ability to prevent LDO from overshoot"]
+pub type SDIO_DCAP_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `SDIO_INITI` reader - add resistor from ldo output to ground. 0: no res, 1: 6k,2:4k,3:2k"]
+pub type SDIO_INITI_R = crate::FieldReader;
+#[doc = "Field `SDIO_INITI` writer - add resistor from ldo output to ground. 0: no res, 1: 6k,2:4k,3:2k"]
+pub type SDIO_INITI_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `SDIO_EN_INITI` reader - 0 to set init\\[1:0\\]=0"]
+pub type SDIO_EN_INITI_R = crate::BitReader;
+#[doc = "Field `SDIO_EN_INITI` writer - 0 to set init\\[1:0\\]=0"]
+pub type SDIO_EN_INITI_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SDIO_DCURLIM` reader - tune current limit threshold when tieh = 0. About 800mA/(8+d)"]
+pub type SDIO_DCURLIM_R = crate::FieldReader;
+#[doc = "Field `SDIO_DCURLIM` writer - tune current limit threshold when tieh = 0. About 800mA/(8+d)"]
+pub type SDIO_DCURLIM_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `SDIO_MODECURLIM` reader - select current limit mode"]
+pub type SDIO_MODECURLIM_R = crate::BitReader;
+#[doc = "Field `SDIO_MODECURLIM` writer - select current limit mode"]
+pub type SDIO_MODECURLIM_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SDIO_ENCURLIM` reader - enable current limit"]
+pub type SDIO_ENCURLIM_R = crate::BitReader;
+#[doc = "Field `SDIO_ENCURLIM` writer - enable current limit"]
+pub type SDIO_ENCURLIM_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SDIO_REG_PD_EN` reader - power down SDIO_REG in sleep. Only active when reg_sdio_force = 0"]
+pub type SDIO_REG_PD_EN_R = crate::BitReader;
+#[doc = "Field `SDIO_REG_PD_EN` writer - power down SDIO_REG in sleep. Only active when reg_sdio_force = 0"]
+pub type SDIO_REG_PD_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SDIO_FORCE` reader - 1: use SW option to control SDIO_REG, 0: use state machine"]
+pub type SDIO_FORCE_R = crate::BitReader;
+#[doc = "Field `SDIO_FORCE` writer - 1: use SW option to control SDIO_REG, 0: use state machine"]
+pub type SDIO_FORCE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SDIO_TIEH` reader - SW option for SDIO_TIEH. Only active when reg_sdio_force = 1"]
+pub type SDIO_TIEH_R = crate::BitReader;
+#[doc = "Field `SDIO_TIEH` writer - SW option for SDIO_TIEH. Only active when reg_sdio_force = 1"]
+pub type SDIO_TIEH_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `REG1P8_READY` reader - read only register for REG1P8_READY"]
+pub type REG1P8_READY_R = crate::BitReader;
+#[doc = "Field `DREFL_SDIO` reader - SW option for DREFL_SDIO. Only active when reg_sdio_force = 1"]
+pub type DREFL_SDIO_R = crate::FieldReader;
+#[doc = "Field `DREFL_SDIO` writer - SW option for DREFL_SDIO. Only active when reg_sdio_force = 1"]
+pub type DREFL_SDIO_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `DREFM_SDIO` reader - SW option for DREFM_SDIO. Only active when reg_sdio_force = 1"]
+pub type DREFM_SDIO_R = crate::FieldReader;
+#[doc = "Field `DREFM_SDIO` writer - SW option for DREFM_SDIO. Only active when reg_sdio_force = 1"]
+pub type DREFM_SDIO_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `DREFH_SDIO` reader - SW option for DREFH_SDIO. Only active when reg_sdio_force = 1"]
+pub type DREFH_SDIO_R = crate::FieldReader;
+#[doc = "Field `DREFH_SDIO` writer - SW option for DREFH_SDIO. Only active when reg_sdio_force = 1"]
+pub type DREFH_SDIO_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `XPD_SDIO` reader - power on flash regulator"]
+pub type XPD_SDIO_R = crate::BitReader;
+#[doc = "Field `XPD_SDIO` writer - power on flash regulator"]
+pub type XPD_SDIO_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 0:7 - timer count to apply reg_sdio_dcap after sdio power on"]
+    #[inline(always)]
+    pub fn sdio_timer_target(&self) -> SDIO_TIMER_TARGET_R {
+        SDIO_TIMER_TARGET_R::new((self.bits & 0xff) as u8)
+    }
+    #[doc = "Bits 9:10 - Tieh = 1 mode drive ability. Initially set to 0 to limit charge current, set to 3 after several us."]
+    #[inline(always)]
+    pub fn sdio_dthdrv(&self) -> SDIO_DTHDRV_R {
+        SDIO_DTHDRV_R::new(((self.bits >> 9) & 3) as u8)
+    }
+    #[doc = "Bits 11:12 - ability to prevent LDO from overshoot"]
+    #[inline(always)]
+    pub fn sdio_dcap(&self) -> SDIO_DCAP_R {
+        SDIO_DCAP_R::new(((self.bits >> 11) & 3) as u8)
+    }
+    #[doc = "Bits 13:14 - add resistor from ldo output to ground. 0: no res, 1: 6k,2:4k,3:2k"]
+    #[inline(always)]
+    pub fn sdio_initi(&self) -> SDIO_INITI_R {
+        SDIO_INITI_R::new(((self.bits >> 13) & 3) as u8)
+    }
+    #[doc = "Bit 15 - 0 to set init\\[1:0\\]=0"]
+    #[inline(always)]
+    pub fn sdio_en_initi(&self) -> SDIO_EN_INITI_R {
+        SDIO_EN_INITI_R::new(((self.bits >> 15) & 1) != 0)
+    }
+    #[doc = "Bits 16:18 - tune current limit threshold when tieh = 0. About 800mA/(8+d)"]
+    #[inline(always)]
+    pub fn sdio_dcurlim(&self) -> SDIO_DCURLIM_R {
+        SDIO_DCURLIM_R::new(((self.bits >> 16) & 7) as u8)
+    }
+    #[doc = "Bit 19 - select current limit mode"]
+    #[inline(always)]
+    pub fn sdio_modecurlim(&self) -> SDIO_MODECURLIM_R {
+        SDIO_MODECURLIM_R::new(((self.bits >> 19) & 1) != 0)
+    }
+    #[doc = "Bit 20 - enable current limit"]
+    #[inline(always)]
+    pub fn sdio_encurlim(&self) -> SDIO_ENCURLIM_R {
+        SDIO_ENCURLIM_R::new(((self.bits >> 20) & 1) != 0)
+    }
+    #[doc = "Bit 21 - power down SDIO_REG in sleep. Only active when reg_sdio_force = 0"]
+    #[inline(always)]
+    pub fn sdio_reg_pd_en(&self) -> SDIO_REG_PD_EN_R {
+        SDIO_REG_PD_EN_R::new(((self.bits >> 21) & 1) != 0)
+    }
+    #[doc = "Bit 22 - 1: use SW option to control SDIO_REG, 0: use state machine"]
+    #[inline(always)]
+    pub fn sdio_force(&self) -> SDIO_FORCE_R {
+        SDIO_FORCE_R::new(((self.bits >> 22) & 1) != 0)
+    }
+    #[doc = "Bit 23 - SW option for SDIO_TIEH. Only active when reg_sdio_force = 1"]
+    #[inline(always)]
+    pub fn sdio_tieh(&self) -> SDIO_TIEH_R {
+        SDIO_TIEH_R::new(((self.bits >> 23) & 1) != 0)
+    }
+    #[doc = "Bit 24 - read only register for REG1P8_READY"]
+    #[inline(always)]
+    pub fn reg1p8_ready(&self) -> REG1P8_READY_R {
+        REG1P8_READY_R::new(((self.bits >> 24) & 1) != 0)
+    }
+    #[doc = "Bits 25:26 - SW option for DREFL_SDIO. Only active when reg_sdio_force = 1"]
+    #[inline(always)]
+    pub fn drefl_sdio(&self) -> DREFL_SDIO_R {
+        DREFL_SDIO_R::new(((self.bits >> 25) & 3) as u8)
+    }
+    #[doc = "Bits 27:28 - SW option for DREFM_SDIO. Only active when reg_sdio_force = 1"]
+    #[inline(always)]
+    pub fn drefm_sdio(&self) -> DREFM_SDIO_R {
+        DREFM_SDIO_R::new(((self.bits >> 27) & 3) as u8)
+    }
+    #[doc = "Bits 29:30 - SW option for DREFH_SDIO. Only active when reg_sdio_force = 1"]
+    #[inline(always)]
+    pub fn drefh_sdio(&self) -> DREFH_SDIO_R {
+        DREFH_SDIO_R::new(((self.bits >> 29) & 3) as u8)
+    }
+    #[doc = "Bit 31 - power on flash regulator"]
+    #[inline(always)]
+    pub fn xpd_sdio(&self) -> XPD_SDIO_R {
+        XPD_SDIO_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SDIO_CONF")
+            .field("sdio_timer_target", &self.sdio_timer_target())
+            .field("sdio_dthdrv", &self.sdio_dthdrv())
+            .field("sdio_dcap", &self.sdio_dcap())
+            .field("sdio_initi", &self.sdio_initi())
+            .field("sdio_en_initi", &self.sdio_en_initi())
+            .field("sdio_dcurlim", &self.sdio_dcurlim())
+            .field("sdio_modecurlim", &self.sdio_modecurlim())
+            .field("sdio_encurlim", &self.sdio_encurlim())
+            .field("sdio_reg_pd_en", &self.sdio_reg_pd_en())
+            .field("sdio_force", &self.sdio_force())
+            .field("sdio_tieh", &self.sdio_tieh())
+            .field("reg1p8_ready", &self.reg1p8_ready())
+            .field("drefl_sdio", &self.drefl_sdio())
+            .field("drefm_sdio", &self.drefm_sdio())
+            .field("drefh_sdio", &self.drefh_sdio())
+            .field("xpd_sdio", &self.xpd_sdio())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - timer count to apply reg_sdio_dcap after sdio power on"]
+    #[inline(always)]
+    pub fn sdio_timer_target(&mut self) -> SDIO_TIMER_TARGET_W<SDIO_CONF_SPEC> {
+        SDIO_TIMER_TARGET_W::new(self, 0)
+    }
+    #[doc = "Bits 9:10 - Tieh = 1 mode drive ability. Initially set to 0 to limit charge current, set to 3 after several us."]
+    #[inline(always)]
+    pub fn sdio_dthdrv(&mut self) -> SDIO_DTHDRV_W<SDIO_CONF_SPEC> {
+        SDIO_DTHDRV_W::new(self, 9)
+    }
+    #[doc = "Bits 11:12 - ability to prevent LDO from overshoot"]
+    #[inline(always)]
+    pub fn sdio_dcap(&mut self) -> SDIO_DCAP_W<SDIO_CONF_SPEC> {
+        SDIO_DCAP_W::new(self, 11)
+    }
+    #[doc = "Bits 13:14 - add resistor from ldo output to ground. 0: no res, 1: 6k,2:4k,3:2k"]
+    #[inline(always)]
+    pub fn sdio_initi(&mut self) -> SDIO_INITI_W<SDIO_CONF_SPEC> {
+        SDIO_INITI_W::new(self, 13)
+    }
+    #[doc = "Bit 15 - 0 to set init\\[1:0\\]=0"]
+    #[inline(always)]
+    pub fn sdio_en_initi(&mut self) -> SDIO_EN_INITI_W<SDIO_CONF_SPEC> {
+        SDIO_EN_INITI_W::new(self, 15)
+    }
+    #[doc = "Bits 16:18 - tune current limit threshold when tieh = 0. About 800mA/(8+d)"]
+    #[inline(always)]
+    pub fn sdio_dcurlim(&mut self) -> SDIO_DCURLIM_W<SDIO_CONF_SPEC> {
+        SDIO_DCURLIM_W::new(self, 16)
+    }
+    #[doc = "Bit 19 - select current limit mode"]
+    #[inline(always)]
+    pub fn sdio_modecurlim(&mut self) -> SDIO_MODECURLIM_W<SDIO_CONF_SPEC> {
+        SDIO_MODECURLIM_W::new(self, 19)
+    }
+    #[doc = "Bit 20 - enable current limit"]
+    #[inline(always)]
+    pub fn sdio_encurlim(&mut self) -> SDIO_ENCURLIM_W<SDIO_CONF_SPEC> {
+        SDIO_ENCURLIM_W::new(self, 20)
+    }
+    #[doc = "Bit 21 - power down SDIO_REG in sleep. Only active when reg_sdio_force = 0"]
+    #[inline(always)]
+    pub fn sdio_reg_pd_en(&mut self) -> SDIO_REG_PD_EN_W<SDIO_CONF_SPEC> {
+        SDIO_REG_PD_EN_W::new(self, 21)
+    }
+    #[doc = "Bit 22 - 1: use SW option to control SDIO_REG, 0: use state machine"]
+    #[inline(always)]
+    pub fn sdio_force(&mut self) -> SDIO_FORCE_W<SDIO_CONF_SPEC> {
+        SDIO_FORCE_W::new(self, 22)
+    }
+    #[doc = "Bit 23 - SW option for SDIO_TIEH. Only active when reg_sdio_force = 1"]
+    #[inline(always)]
+    pub fn sdio_tieh(&mut self) -> SDIO_TIEH_W<SDIO_CONF_SPEC> {
+        SDIO_TIEH_W::new(self, 23)
+    }
+    #[doc = "Bits 25:26 - SW option for DREFL_SDIO. Only active when reg_sdio_force = 1"]
+    #[inline(always)]
+    pub fn drefl_sdio(&mut self) -> DREFL_SDIO_W<SDIO_CONF_SPEC> {
+        DREFL_SDIO_W::new(self, 25)
+    }
+    #[doc = "Bits 27:28 - SW option for DREFM_SDIO. Only active when reg_sdio_force = 1"]
+    #[inline(always)]
+    pub fn drefm_sdio(&mut self) -> DREFM_SDIO_W<SDIO_CONF_SPEC> {
+        DREFM_SDIO_W::new(self, 27)
+    }
+    #[doc = "Bits 29:30 - SW option for DREFH_SDIO. Only active when reg_sdio_force = 1"]
+    #[inline(always)]
+    pub fn drefh_sdio(&mut self) -> DREFH_SDIO_W<SDIO_CONF_SPEC> {
+        DREFH_SDIO_W::new(self, 29)
+    }
+    #[doc = "Bit 31 - power on flash regulator"]
+    #[inline(always)]
+    pub fn xpd_sdio(&mut self) -> XPD_SDIO_W<SDIO_CONF_SPEC> {
+        XPD_SDIO_W::new(self, 31)
+    }
+}
+#[doc = "configure flash power\n\nYou can [`read`](crate::Reg::read) this register and get [`sdio_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdio_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SDIO_CONF_SPEC;
+impl crate::RegisterSpec for SDIO_CONF_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sdio_conf::R`](R) reader structure"]
+impl crate::Readable for SDIO_CONF_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sdio_conf::W`](W) writer structure"]
+impl crate::Writable for SDIO_CONF_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SDIO_CONF to value 0x0ab0_be0a"]
+impl crate::Resettable for SDIO_CONF_SPEC {
+    const RESET_VALUE: u32 = 0x0ab0_be0a;
+}

vendor/esp32s3/src/rtc_cntl/slow_clk_conf.rs

@@ -0,0 +1,77 @@
+#[doc = "Register `SLOW_CLK_CONF` reader"]
+pub type R = crate::R<SLOW_CLK_CONF_SPEC>;
+#[doc = "Register `SLOW_CLK_CONF` writer"]
+pub type W = crate::W<SLOW_CLK_CONF_SPEC>;
+#[doc = "Field `ANA_CLK_DIV_VLD` reader - used to sync div bus. clear vld before set reg_rtc_ana_clk_div, then set vld to actually switch the clk"]
+pub type ANA_CLK_DIV_VLD_R = crate::BitReader;
+#[doc = "Field `ANA_CLK_DIV_VLD` writer - used to sync div bus. clear vld before set reg_rtc_ana_clk_div, then set vld to actually switch the clk"]
+pub type ANA_CLK_DIV_VLD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ANA_CLK_DIV` reader - rtc clk div"]
+pub type ANA_CLK_DIV_R = crate::FieldReader;
+#[doc = "Field `ANA_CLK_DIV` writer - rtc clk div"]
+pub type ANA_CLK_DIV_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+#[doc = "Field `SLOW_CLK_NEXT_EDGE` reader - No public"]
+pub type SLOW_CLK_NEXT_EDGE_R = crate::BitReader;
+#[doc = "Field `SLOW_CLK_NEXT_EDGE` writer - No public"]
+pub type SLOW_CLK_NEXT_EDGE_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 22 - used to sync div bus. clear vld before set reg_rtc_ana_clk_div, then set vld to actually switch the clk"]
+    #[inline(always)]
+    pub fn ana_clk_div_vld(&self) -> ANA_CLK_DIV_VLD_R {
+        ANA_CLK_DIV_VLD_R::new(((self.bits >> 22) & 1) != 0)
+    }
+    #[doc = "Bits 23:30 - rtc clk div"]
+    #[inline(always)]
+    pub fn ana_clk_div(&self) -> ANA_CLK_DIV_R {
+        ANA_CLK_DIV_R::new(((self.bits >> 23) & 0xff) as u8)
+    }
+    #[doc = "Bit 31 - No public"]
+    #[inline(always)]
+    pub fn slow_clk_next_edge(&self) -> SLOW_CLK_NEXT_EDGE_R {
+        SLOW_CLK_NEXT_EDGE_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SLOW_CLK_CONF")
+            .field("ana_clk_div_vld", &self.ana_clk_div_vld())
+            .field("ana_clk_div", &self.ana_clk_div())
+            .field("slow_clk_next_edge", &self.slow_clk_next_edge())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 22 - used to sync div bus. clear vld before set reg_rtc_ana_clk_div, then set vld to actually switch the clk"]
+    #[inline(always)]
+    pub fn ana_clk_div_vld(&mut self) -> ANA_CLK_DIV_VLD_W<SLOW_CLK_CONF_SPEC> {
+        ANA_CLK_DIV_VLD_W::new(self, 22)
+    }
+    #[doc = "Bits 23:30 - rtc clk div"]
+    #[inline(always)]
+    pub fn ana_clk_div(&mut self) -> ANA_CLK_DIV_W<SLOW_CLK_CONF_SPEC> {
+        ANA_CLK_DIV_W::new(self, 23)
+    }
+    #[doc = "Bit 31 - No public"]
+    #[inline(always)]
+    pub fn slow_clk_next_edge(&mut self) -> SLOW_CLK_NEXT_EDGE_W<SLOW_CLK_CONF_SPEC> {
+        SLOW_CLK_NEXT_EDGE_W::new(self, 31)
+    }
+}
+#[doc = "configure slow clk\n\nYou can [`read`](crate::Reg::read) this register and get [`slow_clk_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slow_clk_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SLOW_CLK_CONF_SPEC;
+impl crate::RegisterSpec for SLOW_CLK_CONF_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`slow_clk_conf::R`](R) reader structure"]
+impl crate::Readable for SLOW_CLK_CONF_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`slow_clk_conf::W`](W) writer structure"]
+impl crate::Writable for SLOW_CLK_CONF_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SLOW_CLK_CONF to value 0x0040_0000"]
+impl crate::Resettable for SLOW_CLK_CONF_SPEC {
+    const RESET_VALUE: u32 = 0x0040_0000;
+}

vendor/esp32s3/src/rtc_cntl/slp_reject_cause.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `SLP_REJECT_CAUSE` reader"]
+pub type R = crate::R<SLP_REJECT_CAUSE_SPEC>;
+#[doc = "Field `REJECT_CAUSE` reader - sleep reject cause"]
+pub type REJECT_CAUSE_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:17 - sleep reject cause"]
+    #[inline(always)]
+    pub fn reject_cause(&self) -> REJECT_CAUSE_R {
+        REJECT_CAUSE_R::new(self.bits & 0x0003_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SLP_REJECT_CAUSE")
+            .field("reject_cause", &self.reject_cause())
+            .finish()
+    }
+}
+#[doc = "get reject casue\n\nYou can [`read`](crate::Reg::read) this register and get [`slp_reject_cause::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SLP_REJECT_CAUSE_SPEC;
+impl crate::RegisterSpec for SLP_REJECT_CAUSE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`slp_reject_cause::R`](R) reader structure"]
+impl crate::Readable for SLP_REJECT_CAUSE_SPEC {}
+#[doc = "`reset()` method sets SLP_REJECT_CAUSE to value 0"]
+impl crate::Resettable for SLP_REJECT_CAUSE_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_cntl/slp_reject_conf.rs

@@ -0,0 +1,77 @@
+#[doc = "Register `SLP_REJECT_CONF` reader"]
+pub type R = crate::R<SLP_REJECT_CONF_SPEC>;
+#[doc = "Register `SLP_REJECT_CONF` writer"]
+pub type W = crate::W<SLP_REJECT_CONF_SPEC>;
+#[doc = "Field `SLEEP_REJECT_ENA` reader - sleep reject enable"]
+pub type SLEEP_REJECT_ENA_R = crate::FieldReader<u32>;
+#[doc = "Field `SLEEP_REJECT_ENA` writer - sleep reject enable"]
+pub type SLEEP_REJECT_ENA_W<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>;
+#[doc = "Field `LIGHT_SLP_REJECT_EN` reader - enable reject for light sleep"]
+pub type LIGHT_SLP_REJECT_EN_R = crate::BitReader;
+#[doc = "Field `LIGHT_SLP_REJECT_EN` writer - enable reject for light sleep"]
+pub type LIGHT_SLP_REJECT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DEEP_SLP_REJECT_EN` reader - enable reject for deep sleep"]
+pub type DEEP_SLP_REJECT_EN_R = crate::BitReader;
+#[doc = "Field `DEEP_SLP_REJECT_EN` writer - enable reject for deep sleep"]
+pub type DEEP_SLP_REJECT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 12:29 - sleep reject enable"]
+    #[inline(always)]
+    pub fn sleep_reject_ena(&self) -> SLEEP_REJECT_ENA_R {
+        SLEEP_REJECT_ENA_R::new((self.bits >> 12) & 0x0003_ffff)
+    }
+    #[doc = "Bit 30 - enable reject for light sleep"]
+    #[inline(always)]
+    pub fn light_slp_reject_en(&self) -> LIGHT_SLP_REJECT_EN_R {
+        LIGHT_SLP_REJECT_EN_R::new(((self.bits >> 30) & 1) != 0)
+    }
+    #[doc = "Bit 31 - enable reject for deep sleep"]
+    #[inline(always)]
+    pub fn deep_slp_reject_en(&self) -> DEEP_SLP_REJECT_EN_R {
+        DEEP_SLP_REJECT_EN_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SLP_REJECT_CONF")
+            .field("sleep_reject_ena", &self.sleep_reject_ena())
+            .field("light_slp_reject_en", &self.light_slp_reject_en())
+            .field("deep_slp_reject_en", &self.deep_slp_reject_en())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 12:29 - sleep reject enable"]
+    #[inline(always)]
+    pub fn sleep_reject_ena(&mut self) -> SLEEP_REJECT_ENA_W<SLP_REJECT_CONF_SPEC> {
+        SLEEP_REJECT_ENA_W::new(self, 12)
+    }
+    #[doc = "Bit 30 - enable reject for light sleep"]
+    #[inline(always)]
+    pub fn light_slp_reject_en(&mut self) -> LIGHT_SLP_REJECT_EN_W<SLP_REJECT_CONF_SPEC> {
+        LIGHT_SLP_REJECT_EN_W::new(self, 30)
+    }
+    #[doc = "Bit 31 - enable reject for deep sleep"]
+    #[inline(always)]
+    pub fn deep_slp_reject_en(&mut self) -> DEEP_SLP_REJECT_EN_W<SLP_REJECT_CONF_SPEC> {
+        DEEP_SLP_REJECT_EN_W::new(self, 31)
+    }
+}
+#[doc = "reject sleep register\n\nYou can [`read`](crate::Reg::read) this register and get [`slp_reject_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slp_reject_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SLP_REJECT_CONF_SPEC;
+impl crate::RegisterSpec for SLP_REJECT_CONF_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`slp_reject_conf::R`](R) reader structure"]
+impl crate::Readable for SLP_REJECT_CONF_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`slp_reject_conf::W`](W) writer structure"]
+impl crate::Writable for SLP_REJECT_CONF_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SLP_REJECT_CONF to value 0"]
+impl crate::Resettable for SLP_REJECT_CONF_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_cntl/slp_timer0.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `SLP_TIMER0` reader"]
+pub type R = crate::R<SLP_TIMER0_SPEC>;
+#[doc = "Register `SLP_TIMER0` writer"]
+pub type W = crate::W<SLP_TIMER0_SPEC>;
+#[doc = "Field `SLP_VAL_LO` reader - RTC sleep timer low 32 bits"]
+pub type SLP_VAL_LO_R = crate::FieldReader<u32>;
+#[doc = "Field `SLP_VAL_LO` writer - RTC sleep timer low 32 bits"]
+pub type SLP_VAL_LO_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - RTC sleep timer low 32 bits"]
+    #[inline(always)]
+    pub fn slp_val_lo(&self) -> SLP_VAL_LO_R {
+        SLP_VAL_LO_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SLP_TIMER0")
+            .field("slp_val_lo", &self.slp_val_lo())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - RTC sleep timer low 32 bits"]
+    #[inline(always)]
+    pub fn slp_val_lo(&mut self) -> SLP_VAL_LO_W<SLP_TIMER0_SPEC> {
+        SLP_VAL_LO_W::new(self, 0)
+    }
+}
+#[doc = "configure min sleep time\n\nYou can [`read`](crate::Reg::read) this register and get [`slp_timer0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slp_timer0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SLP_TIMER0_SPEC;
+impl crate::RegisterSpec for SLP_TIMER0_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`slp_timer0::R`](R) reader structure"]
+impl crate::Readable for SLP_TIMER0_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`slp_timer0::W`](W) writer structure"]
+impl crate::Writable for SLP_TIMER0_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SLP_TIMER0 to value 0"]
+impl crate::Resettable for SLP_TIMER0_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_cntl/slp_timer1.rs

@@ -0,0 +1,54 @@
+#[doc = "Register `SLP_TIMER1` reader"]
+pub type R = crate::R<SLP_TIMER1_SPEC>;
+#[doc = "Register `SLP_TIMER1` writer"]
+pub type W = crate::W<SLP_TIMER1_SPEC>;
+#[doc = "Field `SLP_VAL_HI` reader - RTC sleep timer high 16 bits"]
+pub type SLP_VAL_HI_R = crate::FieldReader<u16>;
+#[doc = "Field `SLP_VAL_HI` writer - RTC sleep timer high 16 bits"]
+pub type SLP_VAL_HI_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
+#[doc = "Field `MAIN_TIMER_ALARM_EN` writer - timer alarm enable bit"]
+pub type MAIN_TIMER_ALARM_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 0:15 - RTC sleep timer high 16 bits"]
+    #[inline(always)]
+    pub fn slp_val_hi(&self) -> SLP_VAL_HI_R {
+        SLP_VAL_HI_R::new((self.bits & 0xffff) as u16)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SLP_TIMER1")
+            .field("slp_val_hi", &self.slp_val_hi())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:15 - RTC sleep timer high 16 bits"]
+    #[inline(always)]
+    pub fn slp_val_hi(&mut self) -> SLP_VAL_HI_W<SLP_TIMER1_SPEC> {
+        SLP_VAL_HI_W::new(self, 0)
+    }
+    #[doc = "Bit 16 - timer alarm enable bit"]
+    #[inline(always)]
+    pub fn main_timer_alarm_en(&mut self) -> MAIN_TIMER_ALARM_EN_W<SLP_TIMER1_SPEC> {
+        MAIN_TIMER_ALARM_EN_W::new(self, 16)
+    }
+}
+#[doc = "configure sleep time hi\n\nYou can [`read`](crate::Reg::read) this register and get [`slp_timer1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slp_timer1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SLP_TIMER1_SPEC;
+impl crate::RegisterSpec for SLP_TIMER1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`slp_timer1::R`](R) reader structure"]
+impl crate::Readable for SLP_TIMER1_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`slp_timer1::W`](W) writer structure"]
+impl crate::Writable for SLP_TIMER1_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SLP_TIMER1 to value 0"]
+impl crate::Resettable for SLP_TIMER1_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_cntl/slp_wakeup_cause.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `SLP_WAKEUP_CAUSE` reader"]
+pub type R = crate::R<SLP_WAKEUP_CAUSE_SPEC>;
+#[doc = "Field `WAKEUP_CAUSE` reader - sleep wakeup cause"]
+pub type WAKEUP_CAUSE_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:16 - sleep wakeup cause"]
+    #[inline(always)]
+    pub fn wakeup_cause(&self) -> WAKEUP_CAUSE_R {
+        WAKEUP_CAUSE_R::new(self.bits & 0x0001_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SLP_WAKEUP_CAUSE")
+            .field("wakeup_cause", &self.wakeup_cause())
+            .finish()
+    }
+}
+#[doc = "get wakeup cause\n\nYou can [`read`](crate::Reg::read) this register and get [`slp_wakeup_cause::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SLP_WAKEUP_CAUSE_SPEC;
+impl crate::RegisterSpec for SLP_WAKEUP_CAUSE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`slp_wakeup_cause::R`](R) reader structure"]
+impl crate::Readable for SLP_WAKEUP_CAUSE_SPEC {}
+#[doc = "`reset()` method sets SLP_WAKEUP_CAUSE to value 0"]
+impl crate::Resettable for SLP_WAKEUP_CAUSE_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_cntl/state0.rs

@@ -0,0 +1,114 @@
+#[doc = "Register `STATE0` reader"]
+pub type R = crate::R<STATE0_SPEC>;
+#[doc = "Register `STATE0` writer"]
+pub type W = crate::W<STATE0_SPEC>;
+#[doc = "Field `SW_CPU_INT` writer - rtc software interrupt to main cpu"]
+pub type SW_CPU_INT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SLP_REJECT_CAUSE_CLR` writer - clear rtc sleep reject cause"]
+pub type SLP_REJECT_CAUSE_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `APB2RTC_BRIDGE_SEL` reader - 1: APB to RTC using bridge, 0: APB to RTC using sync"]
+pub type APB2RTC_BRIDGE_SEL_R = crate::BitReader;
+#[doc = "Field `APB2RTC_BRIDGE_SEL` writer - 1: APB to RTC using bridge, 0: APB to RTC using sync"]
+pub type APB2RTC_BRIDGE_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SDIO_ACTIVE_IND` reader - SDIO active indication"]
+pub type SDIO_ACTIVE_IND_R = crate::BitReader;
+#[doc = "Field `SLP_WAKEUP` reader - leep wakeup bit"]
+pub type SLP_WAKEUP_R = crate::BitReader;
+#[doc = "Field `SLP_WAKEUP` writer - leep wakeup bit"]
+pub type SLP_WAKEUP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SLP_REJECT` reader - leep reject bit"]
+pub type SLP_REJECT_R = crate::BitReader;
+#[doc = "Field `SLP_REJECT` writer - leep reject bit"]
+pub type SLP_REJECT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SLEEP_EN` reader - sleep enable bit"]
+pub type SLEEP_EN_R = crate::BitReader;
+#[doc = "Field `SLEEP_EN` writer - sleep enable bit"]
+pub type SLEEP_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 22 - 1: APB to RTC using bridge, 0: APB to RTC using sync"]
+    #[inline(always)]
+    pub fn apb2rtc_bridge_sel(&self) -> APB2RTC_BRIDGE_SEL_R {
+        APB2RTC_BRIDGE_SEL_R::new(((self.bits >> 22) & 1) != 0)
+    }
+    #[doc = "Bit 28 - SDIO active indication"]
+    #[inline(always)]
+    pub fn sdio_active_ind(&self) -> SDIO_ACTIVE_IND_R {
+        SDIO_ACTIVE_IND_R::new(((self.bits >> 28) & 1) != 0)
+    }
+    #[doc = "Bit 29 - leep wakeup bit"]
+    #[inline(always)]
+    pub fn slp_wakeup(&self) -> SLP_WAKEUP_R {
+        SLP_WAKEUP_R::new(((self.bits >> 29) & 1) != 0)
+    }
+    #[doc = "Bit 30 - leep reject bit"]
+    #[inline(always)]
+    pub fn slp_reject(&self) -> SLP_REJECT_R {
+        SLP_REJECT_R::new(((self.bits >> 30) & 1) != 0)
+    }
+    #[doc = "Bit 31 - sleep enable bit"]
+    #[inline(always)]
+    pub fn sleep_en(&self) -> SLEEP_EN_R {
+        SLEEP_EN_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("STATE0")
+            .field("apb2rtc_bridge_sel", &self.apb2rtc_bridge_sel())
+            .field("sdio_active_ind", &self.sdio_active_ind())
+            .field("slp_wakeup", &self.slp_wakeup())
+            .field("slp_reject", &self.slp_reject())
+            .field("sleep_en", &self.sleep_en())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - rtc software interrupt to main cpu"]
+    #[inline(always)]
+    pub fn sw_cpu_int(&mut self) -> SW_CPU_INT_W<STATE0_SPEC> {
+        SW_CPU_INT_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - clear rtc sleep reject cause"]
+    #[inline(always)]
+    pub fn slp_reject_cause_clr(&mut self) -> SLP_REJECT_CAUSE_CLR_W<STATE0_SPEC> {
+        SLP_REJECT_CAUSE_CLR_W::new(self, 1)
+    }
+    #[doc = "Bit 22 - 1: APB to RTC using bridge, 0: APB to RTC using sync"]
+    #[inline(always)]
+    pub fn apb2rtc_bridge_sel(&mut self) -> APB2RTC_BRIDGE_SEL_W<STATE0_SPEC> {
+        APB2RTC_BRIDGE_SEL_W::new(self, 22)
+    }
+    #[doc = "Bit 29 - leep wakeup bit"]
+    #[inline(always)]
+    pub fn slp_wakeup(&mut self) -> SLP_WAKEUP_W<STATE0_SPEC> {
+        SLP_WAKEUP_W::new(self, 29)
+    }
+    #[doc = "Bit 30 - leep reject bit"]
+    #[inline(always)]
+    pub fn slp_reject(&mut self) -> SLP_REJECT_W<STATE0_SPEC> {
+        SLP_REJECT_W::new(self, 30)
+    }
+    #[doc = "Bit 31 - sleep enable bit"]
+    #[inline(always)]
+    pub fn sleep_en(&mut self) -> SLEEP_EN_W<STATE0_SPEC> {
+        SLEEP_EN_W::new(self, 31)
+    }
+}
+#[doc = "configure chip sleep\n\nYou can [`read`](crate::Reg::read) this register and get [`state0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`state0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct STATE0_SPEC;
+impl crate::RegisterSpec for STATE0_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`state0::R`](R) reader structure"]
+impl crate::Readable for STATE0_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`state0::W`](W) writer structure"]
+impl crate::Writable for STATE0_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets STATE0 to value 0"]
+impl crate::Resettable for STATE0_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_cntl/store0.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `STORE0` reader"]
+pub type R = crate::R<STORE0_SPEC>;
+#[doc = "Register `STORE0` writer"]
+pub type W = crate::W<STORE0_SPEC>;
+#[doc = "Field `SCRATCH0` reader - Reserved register"]
+pub type SCRATCH0_R = crate::FieldReader<u32>;
+#[doc = "Field `SCRATCH0` writer - Reserved register"]
+pub type SCRATCH0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - Reserved register"]
+    #[inline(always)]
+    pub fn scratch0(&self) -> SCRATCH0_R {
+        SCRATCH0_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("STORE0")
+            .field("scratch0", &self.scratch0())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Reserved register"]
+    #[inline(always)]
+    pub fn scratch0(&mut self) -> SCRATCH0_W<STORE0_SPEC> {
+        SCRATCH0_W::new(self, 0)
+    }
+}
+#[doc = "Reserved register\n\nYou can [`read`](crate::Reg::read) this register and get [`store0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`store0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct STORE0_SPEC;
+impl crate::RegisterSpec for STORE0_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`store0::R`](R) reader structure"]
+impl crate::Readable for STORE0_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`store0::W`](W) writer structure"]
+impl crate::Writable for STORE0_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets STORE0 to value 0"]
+impl crate::Resettable for STORE0_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_cntl/store1.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `STORE1` reader"]
+pub type R = crate::R<STORE1_SPEC>;
+#[doc = "Register `STORE1` writer"]
+pub type W = crate::W<STORE1_SPEC>;
+#[doc = "Field `SCRATCH1` reader - Reserved register"]
+pub type SCRATCH1_R = crate::FieldReader<u32>;
+#[doc = "Field `SCRATCH1` writer - Reserved register"]
+pub type SCRATCH1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - Reserved register"]
+    #[inline(always)]
+    pub fn scratch1(&self) -> SCRATCH1_R {
+        SCRATCH1_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("STORE1")
+            .field("scratch1", &self.scratch1())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Reserved register"]
+    #[inline(always)]
+    pub fn scratch1(&mut self) -> SCRATCH1_W<STORE1_SPEC> {
+        SCRATCH1_W::new(self, 0)
+    }
+}
+#[doc = "Reserved register\n\nYou can [`read`](crate::Reg::read) this register and get [`store1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`store1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct STORE1_SPEC;
+impl crate::RegisterSpec for STORE1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`store1::R`](R) reader structure"]
+impl crate::Readable for STORE1_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`store1::W`](W) writer structure"]
+impl crate::Writable for STORE1_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets STORE1 to value 0"]
+impl crate::Resettable for STORE1_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_cntl/store2.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `STORE2` reader"]
+pub type R = crate::R<STORE2_SPEC>;
+#[doc = "Register `STORE2` writer"]
+pub type W = crate::W<STORE2_SPEC>;
+#[doc = "Field `SCRATCH2` reader - Reserved register"]
+pub type SCRATCH2_R = crate::FieldReader<u32>;
+#[doc = "Field `SCRATCH2` writer - Reserved register"]
+pub type SCRATCH2_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - Reserved register"]
+    #[inline(always)]
+    pub fn scratch2(&self) -> SCRATCH2_R {
+        SCRATCH2_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("STORE2")
+            .field("scratch2", &self.scratch2())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Reserved register"]
+    #[inline(always)]
+    pub fn scratch2(&mut self) -> SCRATCH2_W<STORE2_SPEC> {
+        SCRATCH2_W::new(self, 0)
+    }
+}
+#[doc = "Reserved register\n\nYou can [`read`](crate::Reg::read) this register and get [`store2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`store2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct STORE2_SPEC;
+impl crate::RegisterSpec for STORE2_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`store2::R`](R) reader structure"]
+impl crate::Readable for STORE2_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`store2::W`](W) writer structure"]
+impl crate::Writable for STORE2_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets STORE2 to value 0"]
+impl crate::Resettable for STORE2_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_cntl/store3.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `STORE3` reader"]
+pub type R = crate::R<STORE3_SPEC>;
+#[doc = "Register `STORE3` writer"]
+pub type W = crate::W<STORE3_SPEC>;
+#[doc = "Field `SCRATCH3` reader - Reserved register"]
+pub type SCRATCH3_R = crate::FieldReader<u32>;
+#[doc = "Field `SCRATCH3` writer - Reserved register"]
+pub type SCRATCH3_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - Reserved register"]
+    #[inline(always)]
+    pub fn scratch3(&self) -> SCRATCH3_R {
+        SCRATCH3_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("STORE3")
+            .field("scratch3", &self.scratch3())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Reserved register"]
+    #[inline(always)]
+    pub fn scratch3(&mut self) -> SCRATCH3_W<STORE3_SPEC> {
+        SCRATCH3_W::new(self, 0)
+    }
+}
+#[doc = "Reserved register\n\nYou can [`read`](crate::Reg::read) this register and get [`store3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`store3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct STORE3_SPEC;
+impl crate::RegisterSpec for STORE3_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`store3::R`](R) reader structure"]
+impl crate::Readable for STORE3_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`store3::W`](W) writer structure"]
+impl crate::Writable for STORE3_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets STORE3 to value 0"]
+impl crate::Resettable for STORE3_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_cntl/store4.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `STORE4` reader"]
+pub type R = crate::R<STORE4_SPEC>;
+#[doc = "Register `STORE4` writer"]
+pub type W = crate::W<STORE4_SPEC>;
+#[doc = "Field `SCRATCH4` reader - reserved register"]
+pub type SCRATCH4_R = crate::FieldReader<u32>;
+#[doc = "Field `SCRATCH4` writer - reserved register"]
+pub type SCRATCH4_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - reserved register"]
+    #[inline(always)]
+    pub fn scratch4(&self) -> SCRATCH4_R {
+        SCRATCH4_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("STORE4")
+            .field("scratch4", &self.scratch4())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - reserved register"]
+    #[inline(always)]
+    pub fn scratch4(&mut self) -> SCRATCH4_W<STORE4_SPEC> {
+        SCRATCH4_W::new(self, 0)
+    }
+}
+#[doc = "reserved register\n\nYou can [`read`](crate::Reg::read) this register and get [`store4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`store4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct STORE4_SPEC;
+impl crate::RegisterSpec for STORE4_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`store4::R`](R) reader structure"]
+impl crate::Readable for STORE4_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`store4::W`](W) writer structure"]
+impl crate::Writable for STORE4_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets STORE4 to value 0"]
+impl crate::Resettable for STORE4_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_cntl/store5.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `STORE5` reader"]
+pub type R = crate::R<STORE5_SPEC>;
+#[doc = "Register `STORE5` writer"]
+pub type W = crate::W<STORE5_SPEC>;
+#[doc = "Field `SCRATCH5` reader - reserved register"]
+pub type SCRATCH5_R = crate::FieldReader<u32>;
+#[doc = "Field `SCRATCH5` writer - reserved register"]
+pub type SCRATCH5_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - reserved register"]
+    #[inline(always)]
+    pub fn scratch5(&self) -> SCRATCH5_R {
+        SCRATCH5_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("STORE5")
+            .field("scratch5", &self.scratch5())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - reserved register"]
+    #[inline(always)]
+    pub fn scratch5(&mut self) -> SCRATCH5_W<STORE5_SPEC> {
+        SCRATCH5_W::new(self, 0)
+    }
+}
+#[doc = "reserved register\n\nYou can [`read`](crate::Reg::read) this register and get [`store5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`store5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct STORE5_SPEC;
+impl crate::RegisterSpec for STORE5_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`store5::R`](R) reader structure"]
+impl crate::Readable for STORE5_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`store5::W`](W) writer structure"]
+impl crate::Writable for STORE5_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets STORE5 to value 0"]
+impl crate::Resettable for STORE5_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_cntl/store6.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `STORE6` reader"]
+pub type R = crate::R<STORE6_SPEC>;
+#[doc = "Register `STORE6` writer"]
+pub type W = crate::W<STORE6_SPEC>;
+#[doc = "Field `SCRATCH6` reader - reserved register"]
+pub type SCRATCH6_R = crate::FieldReader<u32>;
+#[doc = "Field `SCRATCH6` writer - reserved register"]
+pub type SCRATCH6_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - reserved register"]
+    #[inline(always)]
+    pub fn scratch6(&self) -> SCRATCH6_R {
+        SCRATCH6_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("STORE6")
+            .field("scratch6", &self.scratch6())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - reserved register"]
+    #[inline(always)]
+    pub fn scratch6(&mut self) -> SCRATCH6_W<STORE6_SPEC> {
+        SCRATCH6_W::new(self, 0)
+    }
+}
+#[doc = "reserved register\n\nYou can [`read`](crate::Reg::read) this register and get [`store6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`store6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct STORE6_SPEC;
+impl crate::RegisterSpec for STORE6_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`store6::R`](R) reader structure"]
+impl crate::Readable for STORE6_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`store6::W`](W) writer structure"]
+impl crate::Writable for STORE6_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets STORE6 to value 0"]
+impl crate::Resettable for STORE6_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_cntl/store7.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `STORE7` reader"]
+pub type R = crate::R<STORE7_SPEC>;
+#[doc = "Register `STORE7` writer"]
+pub type W = crate::W<STORE7_SPEC>;
+#[doc = "Field `SCRATCH7` reader - reserved register"]
+pub type SCRATCH7_R = crate::FieldReader<u32>;
+#[doc = "Field `SCRATCH7` writer - reserved register"]
+pub type SCRATCH7_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - reserved register"]
+    #[inline(always)]
+    pub fn scratch7(&self) -> SCRATCH7_R {
+        SCRATCH7_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("STORE7")
+            .field("scratch7", &self.scratch7())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - reserved register"]
+    #[inline(always)]
+    pub fn scratch7(&mut self) -> SCRATCH7_W<STORE7_SPEC> {
+        SCRATCH7_W::new(self, 0)
+    }
+}
+#[doc = "reserved register\n\nYou can [`read`](crate::Reg::read) this register and get [`store7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`store7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct STORE7_SPEC;
+impl crate::RegisterSpec for STORE7_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`store7::R`](R) reader structure"]
+impl crate::Readable for STORE7_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`store7::W`](W) writer structure"]
+impl crate::Writable for STORE7_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets STORE7 to value 0"]
+impl crate::Resettable for STORE7_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_cntl/sw_cpu_stall.rs

@@ -0,0 +1,62 @@
+#[doc = "Register `SW_CPU_STALL` reader"]
+pub type R = crate::R<SW_CPU_STALL_SPEC>;
+#[doc = "Register `SW_CPU_STALL` writer"]
+pub type W = crate::W<SW_CPU_STALL_SPEC>;
+#[doc = "Field `SW_STALL_APPCPU_C1` reader - {reg_sw_stall_appcpu_c1\\[5:0\\], reg_sw_stall_appcpu_c0\\[1:0\\]} == 0x86 will stall APP CPU"]
+pub type SW_STALL_APPCPU_C1_R = crate::FieldReader;
+#[doc = "Field `SW_STALL_APPCPU_C1` writer - {reg_sw_stall_appcpu_c1\\[5:0\\], reg_sw_stall_appcpu_c0\\[1:0\\]} == 0x86 will stall APP CPU"]
+pub type SW_STALL_APPCPU_C1_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
+#[doc = "Field `SW_STALL_PROCPU_C1` reader - {reg_sw_stall_appcpu_c1\\[5:0\\], reg_sw_stall_appcpu_c0\\[1:0\\]} == 0x86 will stall APP CPU"]
+pub type SW_STALL_PROCPU_C1_R = crate::FieldReader;
+#[doc = "Field `SW_STALL_PROCPU_C1` writer - {reg_sw_stall_appcpu_c1\\[5:0\\], reg_sw_stall_appcpu_c0\\[1:0\\]} == 0x86 will stall APP CPU"]
+pub type SW_STALL_PROCPU_C1_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
+impl R {
+    #[doc = "Bits 20:25 - {reg_sw_stall_appcpu_c1\\[5:0\\], reg_sw_stall_appcpu_c0\\[1:0\\]} == 0x86 will stall APP CPU"]
+    #[inline(always)]
+    pub fn sw_stall_appcpu_c1(&self) -> SW_STALL_APPCPU_C1_R {
+        SW_STALL_APPCPU_C1_R::new(((self.bits >> 20) & 0x3f) as u8)
+    }
+    #[doc = "Bits 26:31 - {reg_sw_stall_appcpu_c1\\[5:0\\], reg_sw_stall_appcpu_c0\\[1:0\\]} == 0x86 will stall APP CPU"]
+    #[inline(always)]
+    pub fn sw_stall_procpu_c1(&self) -> SW_STALL_PROCPU_C1_R {
+        SW_STALL_PROCPU_C1_R::new(((self.bits >> 26) & 0x3f) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SW_CPU_STALL")
+            .field("sw_stall_appcpu_c1", &self.sw_stall_appcpu_c1())
+            .field("sw_stall_procpu_c1", &self.sw_stall_procpu_c1())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 20:25 - {reg_sw_stall_appcpu_c1\\[5:0\\], reg_sw_stall_appcpu_c0\\[1:0\\]} == 0x86 will stall APP CPU"]
+    #[inline(always)]
+    pub fn sw_stall_appcpu_c1(&mut self) -> SW_STALL_APPCPU_C1_W<SW_CPU_STALL_SPEC> {
+        SW_STALL_APPCPU_C1_W::new(self, 20)
+    }
+    #[doc = "Bits 26:31 - {reg_sw_stall_appcpu_c1\\[5:0\\], reg_sw_stall_appcpu_c0\\[1:0\\]} == 0x86 will stall APP CPU"]
+    #[inline(always)]
+    pub fn sw_stall_procpu_c1(&mut self) -> SW_STALL_PROCPU_C1_W<SW_CPU_STALL_SPEC> {
+        SW_STALL_PROCPU_C1_W::new(self, 26)
+    }
+}
+#[doc = "configure cpu stall by sw\n\nYou can [`read`](crate::Reg::read) this register and get [`sw_cpu_stall::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_cpu_stall::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SW_CPU_STALL_SPEC;
+impl crate::RegisterSpec for SW_CPU_STALL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sw_cpu_stall::R`](R) reader structure"]
+impl crate::Readable for SW_CPU_STALL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sw_cpu_stall::W`](W) writer structure"]
+impl crate::Writable for SW_CPU_STALL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SW_CPU_STALL to value 0"]
+impl crate::Resettable for SW_CPU_STALL_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_cntl/swd_conf.rs

@@ -0,0 +1,122 @@
+#[doc = "Register `SWD_CONF` reader"]
+pub type R = crate::R<SWD_CONF_SPEC>;
+#[doc = "Register `SWD_CONF` writer"]
+pub type W = crate::W<SWD_CONF_SPEC>;
+#[doc = "Field `SWD_RESET_FLAG` reader - swd reset flag"]
+pub type SWD_RESET_FLAG_R = crate::BitReader;
+#[doc = "Field `SWD_FEED_INT` reader - swd interrupt for feeding"]
+pub type SWD_FEED_INT_R = crate::BitReader;
+#[doc = "Field `SWD_BYPASS_RST` reader - bypass super watch dog reset"]
+pub type SWD_BYPASS_RST_R = crate::BitReader;
+#[doc = "Field `SWD_BYPASS_RST` writer - bypass super watch dog reset"]
+pub type SWD_BYPASS_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SWD_SIGNAL_WIDTH` reader - adjust signal width send to swd"]
+pub type SWD_SIGNAL_WIDTH_R = crate::FieldReader<u16>;
+#[doc = "Field `SWD_SIGNAL_WIDTH` writer - adjust signal width send to swd"]
+pub type SWD_SIGNAL_WIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
+#[doc = "Field `SWD_RST_FLAG_CLR` writer - reset swd reset flag"]
+pub type SWD_RST_FLAG_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SWD_FEED` writer - Sw feed swd"]
+pub type SWD_FEED_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SWD_DISABLE` reader - disabel SWD"]
+pub type SWD_DISABLE_R = crate::BitReader;
+#[doc = "Field `SWD_DISABLE` writer - disabel SWD"]
+pub type SWD_DISABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SWD_AUTO_FEED_EN` reader - automatically feed swd when int comes"]
+pub type SWD_AUTO_FEED_EN_R = crate::BitReader;
+#[doc = "Field `SWD_AUTO_FEED_EN` writer - automatically feed swd when int comes"]
+pub type SWD_AUTO_FEED_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - swd reset flag"]
+    #[inline(always)]
+    pub fn swd_reset_flag(&self) -> SWD_RESET_FLAG_R {
+        SWD_RESET_FLAG_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - swd interrupt for feeding"]
+    #[inline(always)]
+    pub fn swd_feed_int(&self) -> SWD_FEED_INT_R {
+        SWD_FEED_INT_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 17 - bypass super watch dog reset"]
+    #[inline(always)]
+    pub fn swd_bypass_rst(&self) -> SWD_BYPASS_RST_R {
+        SWD_BYPASS_RST_R::new(((self.bits >> 17) & 1) != 0)
+    }
+    #[doc = "Bits 18:27 - adjust signal width send to swd"]
+    #[inline(always)]
+    pub fn swd_signal_width(&self) -> SWD_SIGNAL_WIDTH_R {
+        SWD_SIGNAL_WIDTH_R::new(((self.bits >> 18) & 0x03ff) as u16)
+    }
+    #[doc = "Bit 30 - disabel SWD"]
+    #[inline(always)]
+    pub fn swd_disable(&self) -> SWD_DISABLE_R {
+        SWD_DISABLE_R::new(((self.bits >> 30) & 1) != 0)
+    }
+    #[doc = "Bit 31 - automatically feed swd when int comes"]
+    #[inline(always)]
+    pub fn swd_auto_feed_en(&self) -> SWD_AUTO_FEED_EN_R {
+        SWD_AUTO_FEED_EN_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SWD_CONF")
+            .field("swd_reset_flag", &self.swd_reset_flag())
+            .field("swd_feed_int", &self.swd_feed_int())
+            .field("swd_bypass_rst", &self.swd_bypass_rst())
+            .field("swd_signal_width", &self.swd_signal_width())
+            .field("swd_disable", &self.swd_disable())
+            .field("swd_auto_feed_en", &self.swd_auto_feed_en())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 17 - bypass super watch dog reset"]
+    #[inline(always)]
+    pub fn swd_bypass_rst(&mut self) -> SWD_BYPASS_RST_W<SWD_CONF_SPEC> {
+        SWD_BYPASS_RST_W::new(self, 17)
+    }
+    #[doc = "Bits 18:27 - adjust signal width send to swd"]
+    #[inline(always)]
+    pub fn swd_signal_width(&mut self) -> SWD_SIGNAL_WIDTH_W<SWD_CONF_SPEC> {
+        SWD_SIGNAL_WIDTH_W::new(self, 18)
+    }
+    #[doc = "Bit 28 - reset swd reset flag"]
+    #[inline(always)]
+    pub fn swd_rst_flag_clr(&mut self) -> SWD_RST_FLAG_CLR_W<SWD_CONF_SPEC> {
+        SWD_RST_FLAG_CLR_W::new(self, 28)
+    }
+    #[doc = "Bit 29 - Sw feed swd"]
+    #[inline(always)]
+    pub fn swd_feed(&mut self) -> SWD_FEED_W<SWD_CONF_SPEC> {
+        SWD_FEED_W::new(self, 29)
+    }
+    #[doc = "Bit 30 - disabel SWD"]
+    #[inline(always)]
+    pub fn swd_disable(&mut self) -> SWD_DISABLE_W<SWD_CONF_SPEC> {
+        SWD_DISABLE_W::new(self, 30)
+    }
+    #[doc = "Bit 31 - automatically feed swd when int comes"]
+    #[inline(always)]
+    pub fn swd_auto_feed_en(&mut self) -> SWD_AUTO_FEED_EN_W<SWD_CONF_SPEC> {
+        SWD_AUTO_FEED_EN_W::new(self, 31)
+    }
+}
+#[doc = "congfigure super watch dog\n\nYou can [`read`](crate::Reg::read) this register and get [`swd_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`swd_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SWD_CONF_SPEC;
+impl crate::RegisterSpec for SWD_CONF_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`swd_conf::R`](R) reader structure"]
+impl crate::Readable for SWD_CONF_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`swd_conf::W`](W) writer structure"]
+impl crate::Writable for SWD_CONF_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SWD_CONF to value 0x04b0_0000"]
+impl crate::Resettable for SWD_CONF_SPEC {
+    const RESET_VALUE: u32 = 0x04b0_0000;
+}

vendor/esp32s3/src/rtc_cntl/swd_wprotect.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `SWD_WPROTECT` reader"]
+pub type R = crate::R<SWD_WPROTECT_SPEC>;
+#[doc = "Register `SWD_WPROTECT` writer"]
+pub type W = crate::W<SWD_WPROTECT_SPEC>;
+#[doc = "Field `SWD_WKEY` reader - super watch dog key"]
+pub type SWD_WKEY_R = crate::FieldReader<u32>;
+#[doc = "Field `SWD_WKEY` writer - super watch dog key"]
+pub type SWD_WKEY_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - super watch dog key"]
+    #[inline(always)]
+    pub fn swd_wkey(&self) -> SWD_WKEY_R {
+        SWD_WKEY_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SWD_WPROTECT")
+            .field("swd_wkey", &self.swd_wkey())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - super watch dog key"]
+    #[inline(always)]
+    pub fn swd_wkey(&mut self) -> SWD_WKEY_W<SWD_WPROTECT_SPEC> {
+        SWD_WKEY_W::new(self, 0)
+    }
+}
+#[doc = "super watch dog key\n\nYou can [`read`](crate::Reg::read) this register and get [`swd_wprotect::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`swd_wprotect::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SWD_WPROTECT_SPEC;
+impl crate::RegisterSpec for SWD_WPROTECT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`swd_wprotect::R`](R) reader structure"]
+impl crate::Readable for SWD_WPROTECT_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`swd_wprotect::W`](W) writer structure"]
+impl crate::Writable for SWD_WPROTECT_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SWD_WPROTECT to value 0x8f1d_312a"]
+impl crate::Resettable for SWD_WPROTECT_SPEC {
+    const RESET_VALUE: u32 = 0x8f1d_312a;
+}

vendor/esp32s3/src/rtc_cntl/time_high0.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `TIME_HIGH0` reader"]
+pub type R = crate::R<TIME_HIGH0_SPEC>;
+#[doc = "Field `TIMER_VALUE0_HIGH` reader - RTC timer high 16 bits"]
+pub type TIMER_VALUE0_HIGH_R = crate::FieldReader<u16>;
+impl R {
+    #[doc = "Bits 0:15 - RTC timer high 16 bits"]
+    #[inline(always)]
+    pub fn timer_value0_high(&self) -> TIMER_VALUE0_HIGH_R {
+        TIMER_VALUE0_HIGH_R::new((self.bits & 0xffff) as u16)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("TIME_HIGH0")
+            .field("timer_value0_high", &self.timer_value0_high())
+            .finish()
+    }
+}
+#[doc = "read rtc_main timer high bits\n\nYou can [`read`](crate::Reg::read) this register and get [`time_high0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct TIME_HIGH0_SPEC;
+impl crate::RegisterSpec for TIME_HIGH0_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`time_high0::R`](R) reader structure"]
+impl crate::Readable for TIME_HIGH0_SPEC {}
+#[doc = "`reset()` method sets TIME_HIGH0 to value 0"]
+impl crate::Resettable for TIME_HIGH0_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_cntl/time_high1.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `TIME_HIGH1` reader"]
+pub type R = crate::R<TIME_HIGH1_SPEC>;
+#[doc = "Field `TIMER_VALUE1_HIGH` reader - RTC timer high 16 bits"]
+pub type TIMER_VALUE1_HIGH_R = crate::FieldReader<u16>;
+impl R {
+    #[doc = "Bits 0:15 - RTC timer high 16 bits"]
+    #[inline(always)]
+    pub fn timer_value1_high(&self) -> TIMER_VALUE1_HIGH_R {
+        TIMER_VALUE1_HIGH_R::new((self.bits & 0xffff) as u16)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("TIME_HIGH1")
+            .field("timer_value1_high", &self.timer_value1_high())
+            .finish()
+    }
+}
+#[doc = "RTC timer high 16 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`time_high1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct TIME_HIGH1_SPEC;
+impl crate::RegisterSpec for TIME_HIGH1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`time_high1::R`](R) reader structure"]
+impl crate::Readable for TIME_HIGH1_SPEC {}
+#[doc = "`reset()` method sets TIME_HIGH1 to value 0"]
+impl crate::Resettable for TIME_HIGH1_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_cntl/time_low0.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `TIME_LOW0` reader"]
+pub type R = crate::R<TIME_LOW0_SPEC>;
+#[doc = "Field `TIMER_VALUE0_LOW` reader - RTC timer low 32 bits"]
+pub type TIMER_VALUE0_LOW_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - RTC timer low 32 bits"]
+    #[inline(always)]
+    pub fn timer_value0_low(&self) -> TIMER_VALUE0_LOW_R {
+        TIMER_VALUE0_LOW_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("TIME_LOW0")
+            .field("timer_value0_low", &self.timer_value0_low())
+            .finish()
+    }
+}
+#[doc = "read rtc_main timer low bits\n\nYou can [`read`](crate::Reg::read) this register and get [`time_low0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct TIME_LOW0_SPEC;
+impl crate::RegisterSpec for TIME_LOW0_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`time_low0::R`](R) reader structure"]
+impl crate::Readable for TIME_LOW0_SPEC {}
+#[doc = "`reset()` method sets TIME_LOW0 to value 0"]
+impl crate::Resettable for TIME_LOW0_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_cntl/time_low1.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `TIME_LOW1` reader"]
+pub type R = crate::R<TIME_LOW1_SPEC>;
+#[doc = "Field `TIMER_VALUE1_LOW` reader - RTC timer low 32 bits"]
+pub type TIMER_VALUE1_LOW_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - RTC timer low 32 bits"]
+    #[inline(always)]
+    pub fn timer_value1_low(&self) -> TIMER_VALUE1_LOW_R {
+        TIMER_VALUE1_LOW_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("TIME_LOW1")
+            .field("timer_value1_low", &self.timer_value1_low())
+            .finish()
+    }
+}
+#[doc = "RTC timer low 32 bits\n\nYou can [`read`](crate::Reg::read) this register and get [`time_low1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct TIME_LOW1_SPEC;
+impl crate::RegisterSpec for TIME_LOW1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`time_low1::R`](R) reader structure"]
+impl crate::Readable for TIME_LOW1_SPEC {}
+#[doc = "`reset()` method sets TIME_LOW1 to value 0"]
+impl crate::Resettable for TIME_LOW1_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_cntl/time_update.rs

@@ -0,0 +1,84 @@
+#[doc = "Register `TIME_UPDATE` reader"]
+pub type R = crate::R<TIME_UPDATE_SPEC>;
+#[doc = "Register `TIME_UPDATE` writer"]
+pub type W = crate::W<TIME_UPDATE_SPEC>;
+#[doc = "Field `TIMER_SYS_STALL` reader - Enable to record system stall time"]
+pub type TIMER_SYS_STALL_R = crate::BitReader;
+#[doc = "Field `TIMER_SYS_STALL` writer - Enable to record system stall time"]
+pub type TIMER_SYS_STALL_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER_XTL_OFF` reader - Enable to record 40M XTAL OFF time"]
+pub type TIMER_XTL_OFF_R = crate::BitReader;
+#[doc = "Field `TIMER_XTL_OFF` writer - Enable to record 40M XTAL OFF time"]
+pub type TIMER_XTL_OFF_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER_SYS_RST` reader - enable to record system reset time"]
+pub type TIMER_SYS_RST_R = crate::BitReader;
+#[doc = "Field `TIMER_SYS_RST` writer - enable to record system reset time"]
+pub type TIMER_SYS_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIME_UPDATE` writer - Set 1: to update register with RTC timer"]
+pub type TIME_UPDATE_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 27 - Enable to record system stall time"]
+    #[inline(always)]
+    pub fn timer_sys_stall(&self) -> TIMER_SYS_STALL_R {
+        TIMER_SYS_STALL_R::new(((self.bits >> 27) & 1) != 0)
+    }
+    #[doc = "Bit 28 - Enable to record 40M XTAL OFF time"]
+    #[inline(always)]
+    pub fn timer_xtl_off(&self) -> TIMER_XTL_OFF_R {
+        TIMER_XTL_OFF_R::new(((self.bits >> 28) & 1) != 0)
+    }
+    #[doc = "Bit 29 - enable to record system reset time"]
+    #[inline(always)]
+    pub fn timer_sys_rst(&self) -> TIMER_SYS_RST_R {
+        TIMER_SYS_RST_R::new(((self.bits >> 29) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("TIME_UPDATE")
+            .field("timer_sys_stall", &self.timer_sys_stall())
+            .field("timer_xtl_off", &self.timer_xtl_off())
+            .field("timer_sys_rst", &self.timer_sys_rst())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 27 - Enable to record system stall time"]
+    #[inline(always)]
+    pub fn timer_sys_stall(&mut self) -> TIMER_SYS_STALL_W<TIME_UPDATE_SPEC> {
+        TIMER_SYS_STALL_W::new(self, 27)
+    }
+    #[doc = "Bit 28 - Enable to record 40M XTAL OFF time"]
+    #[inline(always)]
+    pub fn timer_xtl_off(&mut self) -> TIMER_XTL_OFF_W<TIME_UPDATE_SPEC> {
+        TIMER_XTL_OFF_W::new(self, 28)
+    }
+    #[doc = "Bit 29 - enable to record system reset time"]
+    #[inline(always)]
+    pub fn timer_sys_rst(&mut self) -> TIMER_SYS_RST_W<TIME_UPDATE_SPEC> {
+        TIMER_SYS_RST_W::new(self, 29)
+    }
+    #[doc = "Bit 31 - Set 1: to update register with RTC timer"]
+    #[inline(always)]
+    pub fn time_update(&mut self) -> TIME_UPDATE_W<TIME_UPDATE_SPEC> {
+        TIME_UPDATE_W::new(self, 31)
+    }
+}
+#[doc = "update rtc main timer\n\nYou can [`read`](crate::Reg::read) this register and get [`time_update::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`time_update::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct TIME_UPDATE_SPEC;
+impl crate::RegisterSpec for TIME_UPDATE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`time_update::R`](R) reader structure"]
+impl crate::Readable for TIME_UPDATE_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`time_update::W`](W) writer structure"]
+impl crate::Writable for TIME_UPDATE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets TIME_UPDATE to value 0"]
+impl crate::Resettable for TIME_UPDATE_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_cntl/timer1.rs

@@ -0,0 +1,107 @@
+#[doc = "Register `TIMER1` reader"]
+pub type R = crate::R<TIMER1_SPEC>;
+#[doc = "Register `TIMER1` writer"]
+pub type W = crate::W<TIMER1_SPEC>;
+#[doc = "Field `CPU_STALL_EN` reader - CPU stall enable bit"]
+pub type CPU_STALL_EN_R = crate::BitReader;
+#[doc = "Field `CPU_STALL_EN` writer - CPU stall enable bit"]
+pub type CPU_STALL_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CPU_STALL_WAIT` reader - CPU stall wait cycles in fast_clk_rtc"]
+pub type CPU_STALL_WAIT_R = crate::FieldReader;
+#[doc = "Field `CPU_STALL_WAIT` writer - CPU stall wait cycles in fast_clk_rtc"]
+pub type CPU_STALL_WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
+#[doc = "Field `CK8M_WAIT` reader - CK8M wait cycles in slow_clk_rtc"]
+pub type CK8M_WAIT_R = crate::FieldReader;
+#[doc = "Field `CK8M_WAIT` writer - CK8M wait cycles in slow_clk_rtc"]
+pub type CK8M_WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+#[doc = "Field `XTL_BUF_WAIT` reader - XTAL wait cycles in slow_clk_rtc"]
+pub type XTL_BUF_WAIT_R = crate::FieldReader<u16>;
+#[doc = "Field `XTL_BUF_WAIT` writer - XTAL wait cycles in slow_clk_rtc"]
+pub type XTL_BUF_WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
+#[doc = "Field `PLL_BUF_WAIT` reader - PLL wait cycles in slow_clk_rtc"]
+pub type PLL_BUF_WAIT_R = crate::FieldReader;
+#[doc = "Field `PLL_BUF_WAIT` writer - PLL wait cycles in slow_clk_rtc"]
+pub type PLL_BUF_WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+impl R {
+    #[doc = "Bit 0 - CPU stall enable bit"]
+    #[inline(always)]
+    pub fn cpu_stall_en(&self) -> CPU_STALL_EN_R {
+        CPU_STALL_EN_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bits 1:5 - CPU stall wait cycles in fast_clk_rtc"]
+    #[inline(always)]
+    pub fn cpu_stall_wait(&self) -> CPU_STALL_WAIT_R {
+        CPU_STALL_WAIT_R::new(((self.bits >> 1) & 0x1f) as u8)
+    }
+    #[doc = "Bits 6:13 - CK8M wait cycles in slow_clk_rtc"]
+    #[inline(always)]
+    pub fn ck8m_wait(&self) -> CK8M_WAIT_R {
+        CK8M_WAIT_R::new(((self.bits >> 6) & 0xff) as u8)
+    }
+    #[doc = "Bits 14:23 - XTAL wait cycles in slow_clk_rtc"]
+    #[inline(always)]
+    pub fn xtl_buf_wait(&self) -> XTL_BUF_WAIT_R {
+        XTL_BUF_WAIT_R::new(((self.bits >> 14) & 0x03ff) as u16)
+    }
+    #[doc = "Bits 24:31 - PLL wait cycles in slow_clk_rtc"]
+    #[inline(always)]
+    pub fn pll_buf_wait(&self) -> PLL_BUF_WAIT_R {
+        PLL_BUF_WAIT_R::new(((self.bits >> 24) & 0xff) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("TIMER1")
+            .field("cpu_stall_en", &self.cpu_stall_en())
+            .field("cpu_stall_wait", &self.cpu_stall_wait())
+            .field("ck8m_wait", &self.ck8m_wait())
+            .field("xtl_buf_wait", &self.xtl_buf_wait())
+            .field("pll_buf_wait", &self.pll_buf_wait())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - CPU stall enable bit"]
+    #[inline(always)]
+    pub fn cpu_stall_en(&mut self) -> CPU_STALL_EN_W<TIMER1_SPEC> {
+        CPU_STALL_EN_W::new(self, 0)
+    }
+    #[doc = "Bits 1:5 - CPU stall wait cycles in fast_clk_rtc"]
+    #[inline(always)]
+    pub fn cpu_stall_wait(&mut self) -> CPU_STALL_WAIT_W<TIMER1_SPEC> {
+        CPU_STALL_WAIT_W::new(self, 1)
+    }
+    #[doc = "Bits 6:13 - CK8M wait cycles in slow_clk_rtc"]
+    #[inline(always)]
+    pub fn ck8m_wait(&mut self) -> CK8M_WAIT_W<TIMER1_SPEC> {
+        CK8M_WAIT_W::new(self, 6)
+    }
+    #[doc = "Bits 14:23 - XTAL wait cycles in slow_clk_rtc"]
+    #[inline(always)]
+    pub fn xtl_buf_wait(&mut self) -> XTL_BUF_WAIT_W<TIMER1_SPEC> {
+        XTL_BUF_WAIT_W::new(self, 14)
+    }
+    #[doc = "Bits 24:31 - PLL wait cycles in slow_clk_rtc"]
+    #[inline(always)]
+    pub fn pll_buf_wait(&mut self) -> PLL_BUF_WAIT_W<TIMER1_SPEC> {
+        PLL_BUF_WAIT_W::new(self, 24)
+    }
+}
+#[doc = "rtc state wait time\n\nYou can [`read`](crate::Reg::read) this register and get [`timer1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct TIMER1_SPEC;
+impl crate::RegisterSpec for TIMER1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`timer1::R`](R) reader structure"]
+impl crate::Readable for TIMER1_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`timer1::W`](W) writer structure"]
+impl crate::Writable for TIMER1_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets TIMER1 to value 0x2814_0403"]
+impl crate::Resettable for TIMER1_SPEC {
+    const RESET_VALUE: u32 = 0x2814_0403;
+}

vendor/esp32s3/src/rtc_cntl/timer2.rs

@@ -0,0 +1,62 @@
+#[doc = "Register `TIMER2` reader"]
+pub type R = crate::R<TIMER2_SPEC>;
+#[doc = "Register `TIMER2` writer"]
+pub type W = crate::W<TIMER2_SPEC>;
+#[doc = "Field `ULPCP_TOUCH_START_WAIT` reader - wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller start to work"]
+pub type ULPCP_TOUCH_START_WAIT_R = crate::FieldReader<u16>;
+#[doc = "Field `ULPCP_TOUCH_START_WAIT` writer - wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller start to work"]
+pub type ULPCP_TOUCH_START_WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
+#[doc = "Field `MIN_TIME_CK8M_OFF` reader - minimal cycles in slow_clk_rtc for CK8M in power down state"]
+pub type MIN_TIME_CK8M_OFF_R = crate::FieldReader;
+#[doc = "Field `MIN_TIME_CK8M_OFF` writer - minimal cycles in slow_clk_rtc for CK8M in power down state"]
+pub type MIN_TIME_CK8M_OFF_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+impl R {
+    #[doc = "Bits 15:23 - wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller start to work"]
+    #[inline(always)]
+    pub fn ulpcp_touch_start_wait(&self) -> ULPCP_TOUCH_START_WAIT_R {
+        ULPCP_TOUCH_START_WAIT_R::new(((self.bits >> 15) & 0x01ff) as u16)
+    }
+    #[doc = "Bits 24:31 - minimal cycles in slow_clk_rtc for CK8M in power down state"]
+    #[inline(always)]
+    pub fn min_time_ck8m_off(&self) -> MIN_TIME_CK8M_OFF_R {
+        MIN_TIME_CK8M_OFF_R::new(((self.bits >> 24) & 0xff) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("TIMER2")
+            .field("ulpcp_touch_start_wait", &self.ulpcp_touch_start_wait())
+            .field("min_time_ck8m_off", &self.min_time_ck8m_off())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 15:23 - wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller start to work"]
+    #[inline(always)]
+    pub fn ulpcp_touch_start_wait(&mut self) -> ULPCP_TOUCH_START_WAIT_W<TIMER2_SPEC> {
+        ULPCP_TOUCH_START_WAIT_W::new(self, 15)
+    }
+    #[doc = "Bits 24:31 - minimal cycles in slow_clk_rtc for CK8M in power down state"]
+    #[inline(always)]
+    pub fn min_time_ck8m_off(&mut self) -> MIN_TIME_CK8M_OFF_W<TIMER2_SPEC> {
+        MIN_TIME_CK8M_OFF_W::new(self, 24)
+    }
+}
+#[doc = "rtc monitor state delay time\n\nYou can [`read`](crate::Reg::read) this register and get [`timer2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct TIMER2_SPEC;
+impl crate::RegisterSpec for TIMER2_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`timer2::R`](R) reader structure"]
+impl crate::Readable for TIMER2_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`timer2::W`](W) writer structure"]
+impl crate::Writable for TIMER2_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets TIMER2 to value 0x0108_0000"]
+impl crate::Resettable for TIMER2_SPEC {
+    const RESET_VALUE: u32 = 0x0108_0000;
+}

vendor/esp32s3/src/rtc_cntl/timer3.rs

@@ -0,0 +1,92 @@
+#[doc = "Register `TIMER3` reader"]
+pub type R = crate::R<TIMER3_SPEC>;
+#[doc = "Register `TIMER3` writer"]
+pub type W = crate::W<TIMER3_SPEC>;
+#[doc = "Field `WIFI_WAIT_TIMER` reader - No public"]
+pub type WIFI_WAIT_TIMER_R = crate::FieldReader<u16>;
+#[doc = "Field `WIFI_WAIT_TIMER` writer - No public"]
+pub type WIFI_WAIT_TIMER_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
+#[doc = "Field `WIFI_POWERUP_TIMER` reader - No public"]
+pub type WIFI_POWERUP_TIMER_R = crate::FieldReader;
+#[doc = "Field `WIFI_POWERUP_TIMER` writer - No public"]
+pub type WIFI_POWERUP_TIMER_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
+#[doc = "Field `BT_WAIT_TIMER` reader - No public"]
+pub type BT_WAIT_TIMER_R = crate::FieldReader<u16>;
+#[doc = "Field `BT_WAIT_TIMER` writer - No public"]
+pub type BT_WAIT_TIMER_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
+#[doc = "Field `BT_POWERUP_TIMER` reader - No public"]
+pub type BT_POWERUP_TIMER_R = crate::FieldReader;
+#[doc = "Field `BT_POWERUP_TIMER` writer - No public"]
+pub type BT_POWERUP_TIMER_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
+impl R {
+    #[doc = "Bits 0:8 - No public"]
+    #[inline(always)]
+    pub fn wifi_wait_timer(&self) -> WIFI_WAIT_TIMER_R {
+        WIFI_WAIT_TIMER_R::new((self.bits & 0x01ff) as u16)
+    }
+    #[doc = "Bits 9:15 - No public"]
+    #[inline(always)]
+    pub fn wifi_powerup_timer(&self) -> WIFI_POWERUP_TIMER_R {
+        WIFI_POWERUP_TIMER_R::new(((self.bits >> 9) & 0x7f) as u8)
+    }
+    #[doc = "Bits 16:24 - No public"]
+    #[inline(always)]
+    pub fn bt_wait_timer(&self) -> BT_WAIT_TIMER_R {
+        BT_WAIT_TIMER_R::new(((self.bits >> 16) & 0x01ff) as u16)
+    }
+    #[doc = "Bits 25:31 - No public"]
+    #[inline(always)]
+    pub fn bt_powerup_timer(&self) -> BT_POWERUP_TIMER_R {
+        BT_POWERUP_TIMER_R::new(((self.bits >> 25) & 0x7f) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("TIMER3")
+            .field("wifi_wait_timer", &self.wifi_wait_timer())
+            .field("wifi_powerup_timer", &self.wifi_powerup_timer())
+            .field("bt_wait_timer", &self.bt_wait_timer())
+            .field("bt_powerup_timer", &self.bt_powerup_timer())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:8 - No public"]
+    #[inline(always)]
+    pub fn wifi_wait_timer(&mut self) -> WIFI_WAIT_TIMER_W<TIMER3_SPEC> {
+        WIFI_WAIT_TIMER_W::new(self, 0)
+    }
+    #[doc = "Bits 9:15 - No public"]
+    #[inline(always)]
+    pub fn wifi_powerup_timer(&mut self) -> WIFI_POWERUP_TIMER_W<TIMER3_SPEC> {
+        WIFI_POWERUP_TIMER_W::new(self, 9)
+    }
+    #[doc = "Bits 16:24 - No public"]
+    #[inline(always)]
+    pub fn bt_wait_timer(&mut self) -> BT_WAIT_TIMER_W<TIMER3_SPEC> {
+        BT_WAIT_TIMER_W::new(self, 16)
+    }
+    #[doc = "Bits 25:31 - No public"]
+    #[inline(always)]
+    pub fn bt_powerup_timer(&mut self) -> BT_POWERUP_TIMER_W<TIMER3_SPEC> {
+        BT_POWERUP_TIMER_W::new(self, 25)
+    }
+}
+#[doc = "No public\n\nYou can [`read`](crate::Reg::read) this register and get [`timer3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct TIMER3_SPEC;
+impl crate::RegisterSpec for TIMER3_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`timer3::R`](R) reader structure"]
+impl crate::Readable for TIMER3_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`timer3::W`](W) writer structure"]
+impl crate::Writable for TIMER3_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets TIMER3 to value 0x1416_0a08"]
+impl crate::Resettable for TIMER3_SPEC {
+    const RESET_VALUE: u32 = 0x1416_0a08;
+}

vendor/esp32s3/src/rtc_cntl/timer4.rs

@@ -0,0 +1,92 @@
+#[doc = "Register `TIMER4` reader"]
+pub type R = crate::R<TIMER4_SPEC>;
+#[doc = "Register `TIMER4` writer"]
+pub type W = crate::W<TIMER4_SPEC>;
+#[doc = "Field `WAIT_TIMER` reader - No public"]
+pub type WAIT_TIMER_R = crate::FieldReader<u16>;
+#[doc = "Field `WAIT_TIMER` writer - No public"]
+pub type WAIT_TIMER_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
+#[doc = "Field `POWERUP_TIMER` reader - No public"]
+pub type POWERUP_TIMER_R = crate::FieldReader;
+#[doc = "Field `POWERUP_TIMER` writer - No public"]
+pub type POWERUP_TIMER_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
+#[doc = "Field `DG_WRAP_WAIT_TIMER` reader - No public"]
+pub type DG_WRAP_WAIT_TIMER_R = crate::FieldReader<u16>;
+#[doc = "Field `DG_WRAP_WAIT_TIMER` writer - No public"]
+pub type DG_WRAP_WAIT_TIMER_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
+#[doc = "Field `DG_WRAP_POWERUP_TIMER` reader - No public"]
+pub type DG_WRAP_POWERUP_TIMER_R = crate::FieldReader;
+#[doc = "Field `DG_WRAP_POWERUP_TIMER` writer - No public"]
+pub type DG_WRAP_POWERUP_TIMER_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
+impl R {
+    #[doc = "Bits 0:8 - No public"]
+    #[inline(always)]
+    pub fn wait_timer(&self) -> WAIT_TIMER_R {
+        WAIT_TIMER_R::new((self.bits & 0x01ff) as u16)
+    }
+    #[doc = "Bits 9:15 - No public"]
+    #[inline(always)]
+    pub fn powerup_timer(&self) -> POWERUP_TIMER_R {
+        POWERUP_TIMER_R::new(((self.bits >> 9) & 0x7f) as u8)
+    }
+    #[doc = "Bits 16:24 - No public"]
+    #[inline(always)]
+    pub fn dg_wrap_wait_timer(&self) -> DG_WRAP_WAIT_TIMER_R {
+        DG_WRAP_WAIT_TIMER_R::new(((self.bits >> 16) & 0x01ff) as u16)
+    }
+    #[doc = "Bits 25:31 - No public"]
+    #[inline(always)]
+    pub fn dg_wrap_powerup_timer(&self) -> DG_WRAP_POWERUP_TIMER_R {
+        DG_WRAP_POWERUP_TIMER_R::new(((self.bits >> 25) & 0x7f) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("TIMER4")
+            .field("wait_timer", &self.wait_timer())
+            .field("powerup_timer", &self.powerup_timer())
+            .field("dg_wrap_wait_timer", &self.dg_wrap_wait_timer())
+            .field("dg_wrap_powerup_timer", &self.dg_wrap_powerup_timer())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:8 - No public"]
+    #[inline(always)]
+    pub fn wait_timer(&mut self) -> WAIT_TIMER_W<TIMER4_SPEC> {
+        WAIT_TIMER_W::new(self, 0)
+    }
+    #[doc = "Bits 9:15 - No public"]
+    #[inline(always)]
+    pub fn powerup_timer(&mut self) -> POWERUP_TIMER_W<TIMER4_SPEC> {
+        POWERUP_TIMER_W::new(self, 9)
+    }
+    #[doc = "Bits 16:24 - No public"]
+    #[inline(always)]
+    pub fn dg_wrap_wait_timer(&mut self) -> DG_WRAP_WAIT_TIMER_W<TIMER4_SPEC> {
+        DG_WRAP_WAIT_TIMER_W::new(self, 16)
+    }
+    #[doc = "Bits 25:31 - No public"]
+    #[inline(always)]
+    pub fn dg_wrap_powerup_timer(&mut self) -> DG_WRAP_POWERUP_TIMER_W<TIMER4_SPEC> {
+        DG_WRAP_POWERUP_TIMER_W::new(self, 25)
+    }
+}
+#[doc = "No public\n\nYou can [`read`](crate::Reg::read) this register and get [`timer4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct TIMER4_SPEC;
+impl crate::RegisterSpec for TIMER4_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`timer4::R`](R) reader structure"]
+impl crate::Readable for TIMER4_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`timer4::W`](W) writer structure"]
+impl crate::Writable for TIMER4_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets TIMER4 to value 0x1020_0a08"]
+impl crate::Resettable for TIMER4_SPEC {
+    const RESET_VALUE: u32 = 0x1020_0a08;
+}

vendor/esp32s3/src/rtc_cntl/timer5.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `TIMER5` reader"]
+pub type R = crate::R<TIMER5_SPEC>;
+#[doc = "Register `TIMER5` writer"]
+pub type W = crate::W<TIMER5_SPEC>;
+#[doc = "Field `MIN_SLP_VAL` reader - minimal sleep cycles in slow_clk_rtc"]
+pub type MIN_SLP_VAL_R = crate::FieldReader;
+#[doc = "Field `MIN_SLP_VAL` writer - minimal sleep cycles in slow_clk_rtc"]
+pub type MIN_SLP_VAL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+impl R {
+    #[doc = "Bits 8:15 - minimal sleep cycles in slow_clk_rtc"]
+    #[inline(always)]
+    pub fn min_slp_val(&self) -> MIN_SLP_VAL_R {
+        MIN_SLP_VAL_R::new(((self.bits >> 8) & 0xff) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("TIMER5")
+            .field("min_slp_val", &self.min_slp_val())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 8:15 - minimal sleep cycles in slow_clk_rtc"]
+    #[inline(always)]
+    pub fn min_slp_val(&mut self) -> MIN_SLP_VAL_W<TIMER5_SPEC> {
+        MIN_SLP_VAL_W::new(self, 8)
+    }
+}
+#[doc = "configure min sleep time\n\nYou can [`read`](crate::Reg::read) this register and get [`timer5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct TIMER5_SPEC;
+impl crate::RegisterSpec for TIMER5_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`timer5::R`](R) reader structure"]
+impl crate::Readable for TIMER5_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`timer5::W`](W) writer structure"]
+impl crate::Writable for TIMER5_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets TIMER5 to value 0x8000"]
+impl crate::Resettable for TIMER5_SPEC {
+    const RESET_VALUE: u32 = 0x8000;
+}

vendor/esp32s3/src/rtc_cntl/timer6.rs

@@ -0,0 +1,92 @@
+#[doc = "Register `TIMER6` reader"]
+pub type R = crate::R<TIMER6_SPEC>;
+#[doc = "Register `TIMER6` writer"]
+pub type W = crate::W<TIMER6_SPEC>;
+#[doc = "Field `CPU_TOP_WAIT_TIMER` reader - No public"]
+pub type CPU_TOP_WAIT_TIMER_R = crate::FieldReader<u16>;
+#[doc = "Field `CPU_TOP_WAIT_TIMER` writer - No public"]
+pub type CPU_TOP_WAIT_TIMER_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
+#[doc = "Field `CPU_TOP_POWERUP_TIMER` reader - No public"]
+pub type CPU_TOP_POWERUP_TIMER_R = crate::FieldReader;
+#[doc = "Field `CPU_TOP_POWERUP_TIMER` writer - No public"]
+pub type CPU_TOP_POWERUP_TIMER_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
+#[doc = "Field `DG_PERI_WAIT_TIMER` reader - No public"]
+pub type DG_PERI_WAIT_TIMER_R = crate::FieldReader<u16>;
+#[doc = "Field `DG_PERI_WAIT_TIMER` writer - No public"]
+pub type DG_PERI_WAIT_TIMER_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
+#[doc = "Field `DG_PERI_POWERUP_TIMER` reader - No public"]
+pub type DG_PERI_POWERUP_TIMER_R = crate::FieldReader;
+#[doc = "Field `DG_PERI_POWERUP_TIMER` writer - No public"]
+pub type DG_PERI_POWERUP_TIMER_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
+impl R {
+    #[doc = "Bits 0:8 - No public"]
+    #[inline(always)]
+    pub fn cpu_top_wait_timer(&self) -> CPU_TOP_WAIT_TIMER_R {
+        CPU_TOP_WAIT_TIMER_R::new((self.bits & 0x01ff) as u16)
+    }
+    #[doc = "Bits 9:15 - No public"]
+    #[inline(always)]
+    pub fn cpu_top_powerup_timer(&self) -> CPU_TOP_POWERUP_TIMER_R {
+        CPU_TOP_POWERUP_TIMER_R::new(((self.bits >> 9) & 0x7f) as u8)
+    }
+    #[doc = "Bits 16:24 - No public"]
+    #[inline(always)]
+    pub fn dg_peri_wait_timer(&self) -> DG_PERI_WAIT_TIMER_R {
+        DG_PERI_WAIT_TIMER_R::new(((self.bits >> 16) & 0x01ff) as u16)
+    }
+    #[doc = "Bits 25:31 - No public"]
+    #[inline(always)]
+    pub fn dg_peri_powerup_timer(&self) -> DG_PERI_POWERUP_TIMER_R {
+        DG_PERI_POWERUP_TIMER_R::new(((self.bits >> 25) & 0x7f) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("TIMER6")
+            .field("cpu_top_wait_timer", &self.cpu_top_wait_timer())
+            .field("cpu_top_powerup_timer", &self.cpu_top_powerup_timer())
+            .field("dg_peri_wait_timer", &self.dg_peri_wait_timer())
+            .field("dg_peri_powerup_timer", &self.dg_peri_powerup_timer())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:8 - No public"]
+    #[inline(always)]
+    pub fn cpu_top_wait_timer(&mut self) -> CPU_TOP_WAIT_TIMER_W<TIMER6_SPEC> {
+        CPU_TOP_WAIT_TIMER_W::new(self, 0)
+    }
+    #[doc = "Bits 9:15 - No public"]
+    #[inline(always)]
+    pub fn cpu_top_powerup_timer(&mut self) -> CPU_TOP_POWERUP_TIMER_W<TIMER6_SPEC> {
+        CPU_TOP_POWERUP_TIMER_W::new(self, 9)
+    }
+    #[doc = "Bits 16:24 - No public"]
+    #[inline(always)]
+    pub fn dg_peri_wait_timer(&mut self) -> DG_PERI_WAIT_TIMER_W<TIMER6_SPEC> {
+        DG_PERI_WAIT_TIMER_W::new(self, 16)
+    }
+    #[doc = "Bits 25:31 - No public"]
+    #[inline(always)]
+    pub fn dg_peri_powerup_timer(&mut self) -> DG_PERI_POWERUP_TIMER_W<TIMER6_SPEC> {
+        DG_PERI_POWERUP_TIMER_W::new(self, 25)
+    }
+}
+#[doc = "No public\n\nYou can [`read`](crate::Reg::read) this register and get [`timer6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct TIMER6_SPEC;
+impl crate::RegisterSpec for TIMER6_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`timer6::R`](R) reader structure"]
+impl crate::Readable for TIMER6_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`timer6::W`](W) writer structure"]
+impl crate::Writable for TIMER6_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets TIMER6 to value 0x1020_0a08"]
+impl crate::Resettable for TIMER6_SPEC {
+    const RESET_VALUE: u32 = 0x1020_0a08;
+}

vendor/esp32s3/src/rtc_cntl/touch_approach.rs

@@ -0,0 +1,54 @@
+#[doc = "Register `TOUCH_APPROACH` reader"]
+pub type R = crate::R<TOUCH_APPROACH_SPEC>;
+#[doc = "Register `TOUCH_APPROACH` writer"]
+pub type W = crate::W<TOUCH_APPROACH_SPEC>;
+#[doc = "Field `TOUCH_SLP_CHANNEL_CLR` writer - clear touch slp channel"]
+pub type TOUCH_SLP_CHANNEL_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TOUCH_APPROACH_MEAS_TIME` reader - approach pads total meas times"]
+pub type TOUCH_APPROACH_MEAS_TIME_R = crate::FieldReader;
+#[doc = "Field `TOUCH_APPROACH_MEAS_TIME` writer - approach pads total meas times"]
+pub type TOUCH_APPROACH_MEAS_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+impl R {
+    #[doc = "Bits 24:31 - approach pads total meas times"]
+    #[inline(always)]
+    pub fn touch_approach_meas_time(&self) -> TOUCH_APPROACH_MEAS_TIME_R {
+        TOUCH_APPROACH_MEAS_TIME_R::new(((self.bits >> 24) & 0xff) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("TOUCH_APPROACH")
+            .field("touch_approach_meas_time", &self.touch_approach_meas_time())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 23 - clear touch slp channel"]
+    #[inline(always)]
+    pub fn touch_slp_channel_clr(&mut self) -> TOUCH_SLP_CHANNEL_CLR_W<TOUCH_APPROACH_SPEC> {
+        TOUCH_SLP_CHANNEL_CLR_W::new(self, 23)
+    }
+    #[doc = "Bits 24:31 - approach pads total meas times"]
+    #[inline(always)]
+    pub fn touch_approach_meas_time(&mut self) -> TOUCH_APPROACH_MEAS_TIME_W<TOUCH_APPROACH_SPEC> {
+        TOUCH_APPROACH_MEAS_TIME_W::new(self, 24)
+    }
+}
+#[doc = "configure touch controller\n\nYou can [`read`](crate::Reg::read) this register and get [`touch_approach::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`touch_approach::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct TOUCH_APPROACH_SPEC;
+impl crate::RegisterSpec for TOUCH_APPROACH_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`touch_approach::R`](R) reader structure"]
+impl crate::Readable for TOUCH_APPROACH_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`touch_approach::W`](W) writer structure"]
+impl crate::Writable for TOUCH_APPROACH_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets TOUCH_APPROACH to value 0x5000_0000"]
+impl crate::Resettable for TOUCH_APPROACH_SPEC {
+    const RESET_VALUE: u32 = 0x5000_0000;
+}

vendor/esp32s3/src/rtc_cntl/touch_ctrl1.rs

@@ -0,0 +1,62 @@
+#[doc = "Register `TOUCH_CTRL1` reader"]
+pub type R = crate::R<TOUCH_CTRL1_SPEC>;
+#[doc = "Register `TOUCH_CTRL1` writer"]
+pub type W = crate::W<TOUCH_CTRL1_SPEC>;
+#[doc = "Field `TOUCH_SLEEP_CYCLES` reader - sleep cycles for timer"]
+pub type TOUCH_SLEEP_CYCLES_R = crate::FieldReader<u16>;
+#[doc = "Field `TOUCH_SLEEP_CYCLES` writer - sleep cycles for timer"]
+pub type TOUCH_SLEEP_CYCLES_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
+#[doc = "Field `TOUCH_MEAS_NUM` reader - the meas length (in 8MHz)"]
+pub type TOUCH_MEAS_NUM_R = crate::FieldReader<u16>;
+#[doc = "Field `TOUCH_MEAS_NUM` writer - the meas length (in 8MHz)"]
+pub type TOUCH_MEAS_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
+impl R {
+    #[doc = "Bits 0:15 - sleep cycles for timer"]
+    #[inline(always)]
+    pub fn touch_sleep_cycles(&self) -> TOUCH_SLEEP_CYCLES_R {
+        TOUCH_SLEEP_CYCLES_R::new((self.bits & 0xffff) as u16)
+    }
+    #[doc = "Bits 16:31 - the meas length (in 8MHz)"]
+    #[inline(always)]
+    pub fn touch_meas_num(&self) -> TOUCH_MEAS_NUM_R {
+        TOUCH_MEAS_NUM_R::new(((self.bits >> 16) & 0xffff) as u16)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("TOUCH_CTRL1")
+            .field("touch_sleep_cycles", &self.touch_sleep_cycles())
+            .field("touch_meas_num", &self.touch_meas_num())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:15 - sleep cycles for timer"]
+    #[inline(always)]
+    pub fn touch_sleep_cycles(&mut self) -> TOUCH_SLEEP_CYCLES_W<TOUCH_CTRL1_SPEC> {
+        TOUCH_SLEEP_CYCLES_W::new(self, 0)
+    }
+    #[doc = "Bits 16:31 - the meas length (in 8MHz)"]
+    #[inline(always)]
+    pub fn touch_meas_num(&mut self) -> TOUCH_MEAS_NUM_W<TOUCH_CTRL1_SPEC> {
+        TOUCH_MEAS_NUM_W::new(self, 16)
+    }
+}
+#[doc = "configure touch controller\n\nYou can [`read`](crate::Reg::read) this register and get [`touch_ctrl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`touch_ctrl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct TOUCH_CTRL1_SPEC;
+impl crate::RegisterSpec for TOUCH_CTRL1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`touch_ctrl1::R`](R) reader structure"]
+impl crate::Readable for TOUCH_CTRL1_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`touch_ctrl1::W`](W) writer structure"]
+impl crate::Writable for TOUCH_CTRL1_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets TOUCH_CTRL1 to value 0x1000_0100"]
+impl crate::Resettable for TOUCH_CTRL1_SPEC {
+    const RESET_VALUE: u32 = 0x1000_0100;
+}

vendor/esp32s3/src/rtc_cntl/touch_ctrl2.rs

@@ -0,0 +1,272 @@
+#[doc = "Register `TOUCH_CTRL2` reader"]
+pub type R = crate::R<TOUCH_CTRL2_SPEC>;
+#[doc = "Register `TOUCH_CTRL2` writer"]
+pub type W = crate::W<TOUCH_CTRL2_SPEC>;
+#[doc = "Field `TOUCH_DRANGE` reader - TOUCH_DRANGE"]
+pub type TOUCH_DRANGE_R = crate::FieldReader;
+#[doc = "Field `TOUCH_DRANGE` writer - TOUCH_DRANGE"]
+pub type TOUCH_DRANGE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `TOUCH_DREFL` reader - TOUCH_DREFL"]
+pub type TOUCH_DREFL_R = crate::FieldReader;
+#[doc = "Field `TOUCH_DREFL` writer - TOUCH_DREFL"]
+pub type TOUCH_DREFL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `TOUCH_DREFH` reader - TOUCH_DREFH"]
+pub type TOUCH_DREFH_R = crate::FieldReader;
+#[doc = "Field `TOUCH_DREFH` writer - TOUCH_DREFH"]
+pub type TOUCH_DREFH_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `TOUCH_XPD_BIAS` reader - TOUCH_XPD_BIAS"]
+pub type TOUCH_XPD_BIAS_R = crate::BitReader;
+#[doc = "Field `TOUCH_XPD_BIAS` writer - TOUCH_XPD_BIAS"]
+pub type TOUCH_XPD_BIAS_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TOUCH_REFC` reader - TOUCH pad0 reference cap"]
+pub type TOUCH_REFC_R = crate::FieldReader;
+#[doc = "Field `TOUCH_REFC` writer - TOUCH pad0 reference cap"]
+pub type TOUCH_REFC_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `TOUCH_DBIAS` reader - 1:use self bias 0:use bandgap bias"]
+pub type TOUCH_DBIAS_R = crate::BitReader;
+#[doc = "Field `TOUCH_DBIAS` writer - 1:use self bias 0:use bandgap bias"]
+pub type TOUCH_DBIAS_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TOUCH_SLP_TIMER_EN` reader - touch timer enable bit"]
+pub type TOUCH_SLP_TIMER_EN_R = crate::BitReader;
+#[doc = "Field `TOUCH_SLP_TIMER_EN` writer - touch timer enable bit"]
+pub type TOUCH_SLP_TIMER_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TOUCH_START_FSM_EN` reader - 1: TOUCH_START & TOUCH_XPD is controlled by touch fsm"]
+pub type TOUCH_START_FSM_EN_R = crate::BitReader;
+#[doc = "Field `TOUCH_START_FSM_EN` writer - 1: TOUCH_START & TOUCH_XPD is controlled by touch fsm"]
+pub type TOUCH_START_FSM_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TOUCH_START_EN` reader - 1: start touch fsm"]
+pub type TOUCH_START_EN_R = crate::BitReader;
+#[doc = "Field `TOUCH_START_EN` writer - 1: start touch fsm"]
+pub type TOUCH_START_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TOUCH_START_FORCE` reader - 1: to start touch fsm by SW"]
+pub type TOUCH_START_FORCE_R = crate::BitReader;
+#[doc = "Field `TOUCH_START_FORCE` writer - 1: to start touch fsm by SW"]
+pub type TOUCH_START_FORCE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TOUCH_XPD_WAIT` reader - the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD"]
+pub type TOUCH_XPD_WAIT_R = crate::FieldReader;
+#[doc = "Field `TOUCH_XPD_WAIT` writer - the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD"]
+pub type TOUCH_XPD_WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+#[doc = "Field `TOUCH_SLP_CYC_DIV` reader - when a touch pad is active sleep cycle could be divided by this number"]
+pub type TOUCH_SLP_CYC_DIV_R = crate::FieldReader;
+#[doc = "Field `TOUCH_SLP_CYC_DIV` writer - when a touch pad is active sleep cycle could be divided by this number"]
+pub type TOUCH_SLP_CYC_DIV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `TOUCH_TIMER_FORCE_DONE` reader - force touch timer done"]
+pub type TOUCH_TIMER_FORCE_DONE_R = crate::FieldReader;
+#[doc = "Field `TOUCH_TIMER_FORCE_DONE` writer - force touch timer done"]
+pub type TOUCH_TIMER_FORCE_DONE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `TOUCH_RESET` reader - reset upgrade touch"]
+pub type TOUCH_RESET_R = crate::BitReader;
+#[doc = "Field `TOUCH_RESET` writer - reset upgrade touch"]
+pub type TOUCH_RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TOUCH_CLK_FO` reader - touch clock force on"]
+pub type TOUCH_CLK_FO_R = crate::BitReader;
+#[doc = "Field `TOUCH_CLK_FO` writer - touch clock force on"]
+pub type TOUCH_CLK_FO_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TOUCH_CLKGATE_EN` reader - touch clock enable"]
+pub type TOUCH_CLKGATE_EN_R = crate::BitReader;
+#[doc = "Field `TOUCH_CLKGATE_EN` writer - touch clock enable"]
+pub type TOUCH_CLKGATE_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 2:3 - TOUCH_DRANGE"]
+    #[inline(always)]
+    pub fn touch_drange(&self) -> TOUCH_DRANGE_R {
+        TOUCH_DRANGE_R::new(((self.bits >> 2) & 3) as u8)
+    }
+    #[doc = "Bits 4:5 - TOUCH_DREFL"]
+    #[inline(always)]
+    pub fn touch_drefl(&self) -> TOUCH_DREFL_R {
+        TOUCH_DREFL_R::new(((self.bits >> 4) & 3) as u8)
+    }
+    #[doc = "Bits 6:7 - TOUCH_DREFH"]
+    #[inline(always)]
+    pub fn touch_drefh(&self) -> TOUCH_DREFH_R {
+        TOUCH_DREFH_R::new(((self.bits >> 6) & 3) as u8)
+    }
+    #[doc = "Bit 8 - TOUCH_XPD_BIAS"]
+    #[inline(always)]
+    pub fn touch_xpd_bias(&self) -> TOUCH_XPD_BIAS_R {
+        TOUCH_XPD_BIAS_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bits 9:11 - TOUCH pad0 reference cap"]
+    #[inline(always)]
+    pub fn touch_refc(&self) -> TOUCH_REFC_R {
+        TOUCH_REFC_R::new(((self.bits >> 9) & 7) as u8)
+    }
+    #[doc = "Bit 12 - 1:use self bias 0:use bandgap bias"]
+    #[inline(always)]
+    pub fn touch_dbias(&self) -> TOUCH_DBIAS_R {
+        TOUCH_DBIAS_R::new(((self.bits >> 12) & 1) != 0)
+    }
+    #[doc = "Bit 13 - touch timer enable bit"]
+    #[inline(always)]
+    pub fn touch_slp_timer_en(&self) -> TOUCH_SLP_TIMER_EN_R {
+        TOUCH_SLP_TIMER_EN_R::new(((self.bits >> 13) & 1) != 0)
+    }
+    #[doc = "Bit 14 - 1: TOUCH_START & TOUCH_XPD is controlled by touch fsm"]
+    #[inline(always)]
+    pub fn touch_start_fsm_en(&self) -> TOUCH_START_FSM_EN_R {
+        TOUCH_START_FSM_EN_R::new(((self.bits >> 14) & 1) != 0)
+    }
+    #[doc = "Bit 15 - 1: start touch fsm"]
+    #[inline(always)]
+    pub fn touch_start_en(&self) -> TOUCH_START_EN_R {
+        TOUCH_START_EN_R::new(((self.bits >> 15) & 1) != 0)
+    }
+    #[doc = "Bit 16 - 1: to start touch fsm by SW"]
+    #[inline(always)]
+    pub fn touch_start_force(&self) -> TOUCH_START_FORCE_R {
+        TOUCH_START_FORCE_R::new(((self.bits >> 16) & 1) != 0)
+    }
+    #[doc = "Bits 17:24 - the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD"]
+    #[inline(always)]
+    pub fn touch_xpd_wait(&self) -> TOUCH_XPD_WAIT_R {
+        TOUCH_XPD_WAIT_R::new(((self.bits >> 17) & 0xff) as u8)
+    }
+    #[doc = "Bits 25:26 - when a touch pad is active sleep cycle could be divided by this number"]
+    #[inline(always)]
+    pub fn touch_slp_cyc_div(&self) -> TOUCH_SLP_CYC_DIV_R {
+        TOUCH_SLP_CYC_DIV_R::new(((self.bits >> 25) & 3) as u8)
+    }
+    #[doc = "Bits 27:28 - force touch timer done"]
+    #[inline(always)]
+    pub fn touch_timer_force_done(&self) -> TOUCH_TIMER_FORCE_DONE_R {
+        TOUCH_TIMER_FORCE_DONE_R::new(((self.bits >> 27) & 3) as u8)
+    }
+    #[doc = "Bit 29 - reset upgrade touch"]
+    #[inline(always)]
+    pub fn touch_reset(&self) -> TOUCH_RESET_R {
+        TOUCH_RESET_R::new(((self.bits >> 29) & 1) != 0)
+    }
+    #[doc = "Bit 30 - touch clock force on"]
+    #[inline(always)]
+    pub fn touch_clk_fo(&self) -> TOUCH_CLK_FO_R {
+        TOUCH_CLK_FO_R::new(((self.bits >> 30) & 1) != 0)
+    }
+    #[doc = "Bit 31 - touch clock enable"]
+    #[inline(always)]
+    pub fn touch_clkgate_en(&self) -> TOUCH_CLKGATE_EN_R {
+        TOUCH_CLKGATE_EN_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("TOUCH_CTRL2")
+            .field("touch_drange", &self.touch_drange())
+            .field("touch_drefl", &self.touch_drefl())
+            .field("touch_drefh", &self.touch_drefh())
+            .field("touch_xpd_bias", &self.touch_xpd_bias())
+            .field("touch_refc", &self.touch_refc())
+            .field("touch_dbias", &self.touch_dbias())
+            .field("touch_slp_timer_en", &self.touch_slp_timer_en())
+            .field("touch_start_fsm_en", &self.touch_start_fsm_en())
+            .field("touch_start_en", &self.touch_start_en())
+            .field("touch_start_force", &self.touch_start_force())
+            .field("touch_xpd_wait", &self.touch_xpd_wait())
+            .field("touch_slp_cyc_div", &self.touch_slp_cyc_div())
+            .field("touch_timer_force_done", &self.touch_timer_force_done())
+            .field("touch_reset", &self.touch_reset())
+            .field("touch_clk_fo", &self.touch_clk_fo())
+            .field("touch_clkgate_en", &self.touch_clkgate_en())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 2:3 - TOUCH_DRANGE"]
+    #[inline(always)]
+    pub fn touch_drange(&mut self) -> TOUCH_DRANGE_W<TOUCH_CTRL2_SPEC> {
+        TOUCH_DRANGE_W::new(self, 2)
+    }
+    #[doc = "Bits 4:5 - TOUCH_DREFL"]
+    #[inline(always)]
+    pub fn touch_drefl(&mut self) -> TOUCH_DREFL_W<TOUCH_CTRL2_SPEC> {
+        TOUCH_DREFL_W::new(self, 4)
+    }
+    #[doc = "Bits 6:7 - TOUCH_DREFH"]
+    #[inline(always)]
+    pub fn touch_drefh(&mut self) -> TOUCH_DREFH_W<TOUCH_CTRL2_SPEC> {
+        TOUCH_DREFH_W::new(self, 6)
+    }
+    #[doc = "Bit 8 - TOUCH_XPD_BIAS"]
+    #[inline(always)]
+    pub fn touch_xpd_bias(&mut self) -> TOUCH_XPD_BIAS_W<TOUCH_CTRL2_SPEC> {
+        TOUCH_XPD_BIAS_W::new(self, 8)
+    }
+    #[doc = "Bits 9:11 - TOUCH pad0 reference cap"]
+    #[inline(always)]
+    pub fn touch_refc(&mut self) -> TOUCH_REFC_W<TOUCH_CTRL2_SPEC> {
+        TOUCH_REFC_W::new(self, 9)
+    }
+    #[doc = "Bit 12 - 1:use self bias 0:use bandgap bias"]
+    #[inline(always)]
+    pub fn touch_dbias(&mut self) -> TOUCH_DBIAS_W<TOUCH_CTRL2_SPEC> {
+        TOUCH_DBIAS_W::new(self, 12)
+    }
+    #[doc = "Bit 13 - touch timer enable bit"]
+    #[inline(always)]
+    pub fn touch_slp_timer_en(&mut self) -> TOUCH_SLP_TIMER_EN_W<TOUCH_CTRL2_SPEC> {
+        TOUCH_SLP_TIMER_EN_W::new(self, 13)
+    }
+    #[doc = "Bit 14 - 1: TOUCH_START & TOUCH_XPD is controlled by touch fsm"]
+    #[inline(always)]
+    pub fn touch_start_fsm_en(&mut self) -> TOUCH_START_FSM_EN_W<TOUCH_CTRL2_SPEC> {
+        TOUCH_START_FSM_EN_W::new(self, 14)
+    }
+    #[doc = "Bit 15 - 1: start touch fsm"]
+    #[inline(always)]
+    pub fn touch_start_en(&mut self) -> TOUCH_START_EN_W<TOUCH_CTRL2_SPEC> {
+        TOUCH_START_EN_W::new(self, 15)
+    }
+    #[doc = "Bit 16 - 1: to start touch fsm by SW"]
+    #[inline(always)]
+    pub fn touch_start_force(&mut self) -> TOUCH_START_FORCE_W<TOUCH_CTRL2_SPEC> {
+        TOUCH_START_FORCE_W::new(self, 16)
+    }
+    #[doc = "Bits 17:24 - the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD"]
+    #[inline(always)]
+    pub fn touch_xpd_wait(&mut self) -> TOUCH_XPD_WAIT_W<TOUCH_CTRL2_SPEC> {
+        TOUCH_XPD_WAIT_W::new(self, 17)
+    }
+    #[doc = "Bits 25:26 - when a touch pad is active sleep cycle could be divided by this number"]
+    #[inline(always)]
+    pub fn touch_slp_cyc_div(&mut self) -> TOUCH_SLP_CYC_DIV_W<TOUCH_CTRL2_SPEC> {
+        TOUCH_SLP_CYC_DIV_W::new(self, 25)
+    }
+    #[doc = "Bits 27:28 - force touch timer done"]
+    #[inline(always)]
+    pub fn touch_timer_force_done(&mut self) -> TOUCH_TIMER_FORCE_DONE_W<TOUCH_CTRL2_SPEC> {
+        TOUCH_TIMER_FORCE_DONE_W::new(self, 27)
+    }
+    #[doc = "Bit 29 - reset upgrade touch"]
+    #[inline(always)]
+    pub fn touch_reset(&mut self) -> TOUCH_RESET_W<TOUCH_CTRL2_SPEC> {
+        TOUCH_RESET_W::new(self, 29)
+    }
+    #[doc = "Bit 30 - touch clock force on"]
+    #[inline(always)]
+    pub fn touch_clk_fo(&mut self) -> TOUCH_CLK_FO_W<TOUCH_CTRL2_SPEC> {
+        TOUCH_CLK_FO_W::new(self, 30)
+    }
+    #[doc = "Bit 31 - touch clock enable"]
+    #[inline(always)]
+    pub fn touch_clkgate_en(&mut self) -> TOUCH_CLKGATE_EN_W<TOUCH_CTRL2_SPEC> {
+        TOUCH_CLKGATE_EN_W::new(self, 31)
+    }
+}
+#[doc = "configure touch controller\n\nYou can [`read`](crate::Reg::read) this register and get [`touch_ctrl2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`touch_ctrl2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct TOUCH_CTRL2_SPEC;
+impl crate::RegisterSpec for TOUCH_CTRL2_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`touch_ctrl2::R`](R) reader structure"]
+impl crate::Readable for TOUCH_CTRL2_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`touch_ctrl2::W`](W) writer structure"]
+impl crate::Writable for TOUCH_CTRL2_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets TOUCH_CTRL2 to value 0x0008_40cc"]
+impl crate::Resettable for TOUCH_CTRL2_SPEC {
+    const RESET_VALUE: u32 = 0x0008_40cc;
+}

vendor/esp32s3/src/rtc_cntl/touch_dac.rs

@@ -0,0 +1,182 @@
+#[doc = "Register `TOUCH_DAC` reader"]
+pub type R = crate::R<TOUCH_DAC_SPEC>;
+#[doc = "Register `TOUCH_DAC` writer"]
+pub type W = crate::W<TOUCH_DAC_SPEC>;
+#[doc = "Field `TOUCH_PAD9_DAC` reader - configure touch pad dac9"]
+pub type TOUCH_PAD9_DAC_R = crate::FieldReader;
+#[doc = "Field `TOUCH_PAD9_DAC` writer - configure touch pad dac9"]
+pub type TOUCH_PAD9_DAC_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `TOUCH_PAD8_DAC` reader - configure touch pad dac8"]
+pub type TOUCH_PAD8_DAC_R = crate::FieldReader;
+#[doc = "Field `TOUCH_PAD8_DAC` writer - configure touch pad dac8"]
+pub type TOUCH_PAD8_DAC_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `TOUCH_PAD7_DAC` reader - configure touch pad dac7"]
+pub type TOUCH_PAD7_DAC_R = crate::FieldReader;
+#[doc = "Field `TOUCH_PAD7_DAC` writer - configure touch pad dac7"]
+pub type TOUCH_PAD7_DAC_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `TOUCH_PAD6_DAC` reader - configure touch pad dac6"]
+pub type TOUCH_PAD6_DAC_R = crate::FieldReader;
+#[doc = "Field `TOUCH_PAD6_DAC` writer - configure touch pad dac6"]
+pub type TOUCH_PAD6_DAC_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `TOUCH_PAD5_DAC` reader - configure touch pad dac5"]
+pub type TOUCH_PAD5_DAC_R = crate::FieldReader;
+#[doc = "Field `TOUCH_PAD5_DAC` writer - configure touch pad dac5"]
+pub type TOUCH_PAD5_DAC_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `TOUCH_PAD4_DAC` reader - configure touch pad dac4"]
+pub type TOUCH_PAD4_DAC_R = crate::FieldReader;
+#[doc = "Field `TOUCH_PAD4_DAC` writer - configure touch pad dac4"]
+pub type TOUCH_PAD4_DAC_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `TOUCH_PAD3_DAC` reader - configure touch pad dac3"]
+pub type TOUCH_PAD3_DAC_R = crate::FieldReader;
+#[doc = "Field `TOUCH_PAD3_DAC` writer - configure touch pad dac3"]
+pub type TOUCH_PAD3_DAC_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `TOUCH_PAD2_DAC` reader - configure touch pad dac2"]
+pub type TOUCH_PAD2_DAC_R = crate::FieldReader;
+#[doc = "Field `TOUCH_PAD2_DAC` writer - configure touch pad dac2"]
+pub type TOUCH_PAD2_DAC_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `TOUCH_PAD1_DAC` reader - configure touch pad dac1"]
+pub type TOUCH_PAD1_DAC_R = crate::FieldReader;
+#[doc = "Field `TOUCH_PAD1_DAC` writer - configure touch pad dac1"]
+pub type TOUCH_PAD1_DAC_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `TOUCH_PAD0_DAC` reader - configure touch pad dac0"]
+pub type TOUCH_PAD0_DAC_R = crate::FieldReader;
+#[doc = "Field `TOUCH_PAD0_DAC` writer - configure touch pad dac0"]
+pub type TOUCH_PAD0_DAC_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+impl R {
+    #[doc = "Bits 2:4 - configure touch pad dac9"]
+    #[inline(always)]
+    pub fn touch_pad9_dac(&self) -> TOUCH_PAD9_DAC_R {
+        TOUCH_PAD9_DAC_R::new(((self.bits >> 2) & 7) as u8)
+    }
+    #[doc = "Bits 5:7 - configure touch pad dac8"]
+    #[inline(always)]
+    pub fn touch_pad8_dac(&self) -> TOUCH_PAD8_DAC_R {
+        TOUCH_PAD8_DAC_R::new(((self.bits >> 5) & 7) as u8)
+    }
+    #[doc = "Bits 8:10 - configure touch pad dac7"]
+    #[inline(always)]
+    pub fn touch_pad7_dac(&self) -> TOUCH_PAD7_DAC_R {
+        TOUCH_PAD7_DAC_R::new(((self.bits >> 8) & 7) as u8)
+    }
+    #[doc = "Bits 11:13 - configure touch pad dac6"]
+    #[inline(always)]
+    pub fn touch_pad6_dac(&self) -> TOUCH_PAD6_DAC_R {
+        TOUCH_PAD6_DAC_R::new(((self.bits >> 11) & 7) as u8)
+    }
+    #[doc = "Bits 14:16 - configure touch pad dac5"]
+    #[inline(always)]
+    pub fn touch_pad5_dac(&self) -> TOUCH_PAD5_DAC_R {
+        TOUCH_PAD5_DAC_R::new(((self.bits >> 14) & 7) as u8)
+    }
+    #[doc = "Bits 17:19 - configure touch pad dac4"]
+    #[inline(always)]
+    pub fn touch_pad4_dac(&self) -> TOUCH_PAD4_DAC_R {
+        TOUCH_PAD4_DAC_R::new(((self.bits >> 17) & 7) as u8)
+    }
+    #[doc = "Bits 20:22 - configure touch pad dac3"]
+    #[inline(always)]
+    pub fn touch_pad3_dac(&self) -> TOUCH_PAD3_DAC_R {
+        TOUCH_PAD3_DAC_R::new(((self.bits >> 20) & 7) as u8)
+    }
+    #[doc = "Bits 23:25 - configure touch pad dac2"]
+    #[inline(always)]
+    pub fn touch_pad2_dac(&self) -> TOUCH_PAD2_DAC_R {
+        TOUCH_PAD2_DAC_R::new(((self.bits >> 23) & 7) as u8)
+    }
+    #[doc = "Bits 26:28 - configure touch pad dac1"]
+    #[inline(always)]
+    pub fn touch_pad1_dac(&self) -> TOUCH_PAD1_DAC_R {
+        TOUCH_PAD1_DAC_R::new(((self.bits >> 26) & 7) as u8)
+    }
+    #[doc = "Bits 29:31 - configure touch pad dac0"]
+    #[inline(always)]
+    pub fn touch_pad0_dac(&self) -> TOUCH_PAD0_DAC_R {
+        TOUCH_PAD0_DAC_R::new(((self.bits >> 29) & 7) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("TOUCH_DAC")
+            .field("touch_pad9_dac", &self.touch_pad9_dac())
+            .field("touch_pad8_dac", &self.touch_pad8_dac())
+            .field("touch_pad7_dac", &self.touch_pad7_dac())
+            .field("touch_pad6_dac", &self.touch_pad6_dac())
+            .field("touch_pad5_dac", &self.touch_pad5_dac())
+            .field("touch_pad4_dac", &self.touch_pad4_dac())
+            .field("touch_pad3_dac", &self.touch_pad3_dac())
+            .field("touch_pad2_dac", &self.touch_pad2_dac())
+            .field("touch_pad1_dac", &self.touch_pad1_dac())
+            .field("touch_pad0_dac", &self.touch_pad0_dac())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 2:4 - configure touch pad dac9"]
+    #[inline(always)]
+    pub fn touch_pad9_dac(&mut self) -> TOUCH_PAD9_DAC_W<TOUCH_DAC_SPEC> {
+        TOUCH_PAD9_DAC_W::new(self, 2)
+    }
+    #[doc = "Bits 5:7 - configure touch pad dac8"]
+    #[inline(always)]
+    pub fn touch_pad8_dac(&mut self) -> TOUCH_PAD8_DAC_W<TOUCH_DAC_SPEC> {
+        TOUCH_PAD8_DAC_W::new(self, 5)
+    }
+    #[doc = "Bits 8:10 - configure touch pad dac7"]
+    #[inline(always)]
+    pub fn touch_pad7_dac(&mut self) -> TOUCH_PAD7_DAC_W<TOUCH_DAC_SPEC> {
+        TOUCH_PAD7_DAC_W::new(self, 8)
+    }
+    #[doc = "Bits 11:13 - configure touch pad dac6"]
+    #[inline(always)]
+    pub fn touch_pad6_dac(&mut self) -> TOUCH_PAD6_DAC_W<TOUCH_DAC_SPEC> {
+        TOUCH_PAD6_DAC_W::new(self, 11)
+    }
+    #[doc = "Bits 14:16 - configure touch pad dac5"]
+    #[inline(always)]
+    pub fn touch_pad5_dac(&mut self) -> TOUCH_PAD5_DAC_W<TOUCH_DAC_SPEC> {
+        TOUCH_PAD5_DAC_W::new(self, 14)
+    }
+    #[doc = "Bits 17:19 - configure touch pad dac4"]
+    #[inline(always)]
+    pub fn touch_pad4_dac(&mut self) -> TOUCH_PAD4_DAC_W<TOUCH_DAC_SPEC> {
+        TOUCH_PAD4_DAC_W::new(self, 17)
+    }
+    #[doc = "Bits 20:22 - configure touch pad dac3"]
+    #[inline(always)]
+    pub fn touch_pad3_dac(&mut self) -> TOUCH_PAD3_DAC_W<TOUCH_DAC_SPEC> {
+        TOUCH_PAD3_DAC_W::new(self, 20)
+    }
+    #[doc = "Bits 23:25 - configure touch pad dac2"]
+    #[inline(always)]
+    pub fn touch_pad2_dac(&mut self) -> TOUCH_PAD2_DAC_W<TOUCH_DAC_SPEC> {
+        TOUCH_PAD2_DAC_W::new(self, 23)
+    }
+    #[doc = "Bits 26:28 - configure touch pad dac1"]
+    #[inline(always)]
+    pub fn touch_pad1_dac(&mut self) -> TOUCH_PAD1_DAC_W<TOUCH_DAC_SPEC> {
+        TOUCH_PAD1_DAC_W::new(self, 26)
+    }
+    #[doc = "Bits 29:31 - configure touch pad dac0"]
+    #[inline(always)]
+    pub fn touch_pad0_dac(&mut self) -> TOUCH_PAD0_DAC_W<TOUCH_DAC_SPEC> {
+        TOUCH_PAD0_DAC_W::new(self, 29)
+    }
+}
+#[doc = "configure touch dac\n\nYou can [`read`](crate::Reg::read) this register and get [`touch_dac::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`touch_dac::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct TOUCH_DAC_SPEC;
+impl crate::RegisterSpec for TOUCH_DAC_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`touch_dac::R`](R) reader structure"]
+impl crate::Readable for TOUCH_DAC_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`touch_dac::W`](W) writer structure"]
+impl crate::Writable for TOUCH_DAC_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets TOUCH_DAC to value 0"]
+impl crate::Resettable for TOUCH_DAC_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_cntl/touch_dac1.rs

@@ -0,0 +1,107 @@
+#[doc = "Register `TOUCH_DAC1` reader"]
+pub type R = crate::R<TOUCH_DAC1_SPEC>;
+#[doc = "Register `TOUCH_DAC1` writer"]
+pub type W = crate::W<TOUCH_DAC1_SPEC>;
+#[doc = "Field `TOUCH_PAD14_DAC` reader - configure touch pad dac14"]
+pub type TOUCH_PAD14_DAC_R = crate::FieldReader;
+#[doc = "Field `TOUCH_PAD14_DAC` writer - configure touch pad dac14"]
+pub type TOUCH_PAD14_DAC_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `TOUCH_PAD13_DAC` reader - configure touch pad dac13"]
+pub type TOUCH_PAD13_DAC_R = crate::FieldReader;
+#[doc = "Field `TOUCH_PAD13_DAC` writer - configure touch pad dac13"]
+pub type TOUCH_PAD13_DAC_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `TOUCH_PAD12_DAC` reader - configure touch pad dac12"]
+pub type TOUCH_PAD12_DAC_R = crate::FieldReader;
+#[doc = "Field `TOUCH_PAD12_DAC` writer - configure touch pad dac12"]
+pub type TOUCH_PAD12_DAC_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `TOUCH_PAD11_DAC` reader - configure touch pad dac11"]
+pub type TOUCH_PAD11_DAC_R = crate::FieldReader;
+#[doc = "Field `TOUCH_PAD11_DAC` writer - configure touch pad dac11"]
+pub type TOUCH_PAD11_DAC_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `TOUCH_PAD10_DAC` reader - configure touch pad dac10"]
+pub type TOUCH_PAD10_DAC_R = crate::FieldReader;
+#[doc = "Field `TOUCH_PAD10_DAC` writer - configure touch pad dac10"]
+pub type TOUCH_PAD10_DAC_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+impl R {
+    #[doc = "Bits 17:19 - configure touch pad dac14"]
+    #[inline(always)]
+    pub fn touch_pad14_dac(&self) -> TOUCH_PAD14_DAC_R {
+        TOUCH_PAD14_DAC_R::new(((self.bits >> 17) & 7) as u8)
+    }
+    #[doc = "Bits 20:22 - configure touch pad dac13"]
+    #[inline(always)]
+    pub fn touch_pad13_dac(&self) -> TOUCH_PAD13_DAC_R {
+        TOUCH_PAD13_DAC_R::new(((self.bits >> 20) & 7) as u8)
+    }
+    #[doc = "Bits 23:25 - configure touch pad dac12"]
+    #[inline(always)]
+    pub fn touch_pad12_dac(&self) -> TOUCH_PAD12_DAC_R {
+        TOUCH_PAD12_DAC_R::new(((self.bits >> 23) & 7) as u8)
+    }
+    #[doc = "Bits 26:28 - configure touch pad dac11"]
+    #[inline(always)]
+    pub fn touch_pad11_dac(&self) -> TOUCH_PAD11_DAC_R {
+        TOUCH_PAD11_DAC_R::new(((self.bits >> 26) & 7) as u8)
+    }
+    #[doc = "Bits 29:31 - configure touch pad dac10"]
+    #[inline(always)]
+    pub fn touch_pad10_dac(&self) -> TOUCH_PAD10_DAC_R {
+        TOUCH_PAD10_DAC_R::new(((self.bits >> 29) & 7) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("TOUCH_DAC1")
+            .field("touch_pad14_dac", &self.touch_pad14_dac())
+            .field("touch_pad13_dac", &self.touch_pad13_dac())
+            .field("touch_pad12_dac", &self.touch_pad12_dac())
+            .field("touch_pad11_dac", &self.touch_pad11_dac())
+            .field("touch_pad10_dac", &self.touch_pad10_dac())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 17:19 - configure touch pad dac14"]
+    #[inline(always)]
+    pub fn touch_pad14_dac(&mut self) -> TOUCH_PAD14_DAC_W<TOUCH_DAC1_SPEC> {
+        TOUCH_PAD14_DAC_W::new(self, 17)
+    }
+    #[doc = "Bits 20:22 - configure touch pad dac13"]
+    #[inline(always)]
+    pub fn touch_pad13_dac(&mut self) -> TOUCH_PAD13_DAC_W<TOUCH_DAC1_SPEC> {
+        TOUCH_PAD13_DAC_W::new(self, 20)
+    }
+    #[doc = "Bits 23:25 - configure touch pad dac12"]
+    #[inline(always)]
+    pub fn touch_pad12_dac(&mut self) -> TOUCH_PAD12_DAC_W<TOUCH_DAC1_SPEC> {
+        TOUCH_PAD12_DAC_W::new(self, 23)
+    }
+    #[doc = "Bits 26:28 - configure touch pad dac11"]
+    #[inline(always)]
+    pub fn touch_pad11_dac(&mut self) -> TOUCH_PAD11_DAC_W<TOUCH_DAC1_SPEC> {
+        TOUCH_PAD11_DAC_W::new(self, 26)
+    }
+    #[doc = "Bits 29:31 - configure touch pad dac10"]
+    #[inline(always)]
+    pub fn touch_pad10_dac(&mut self) -> TOUCH_PAD10_DAC_W<TOUCH_DAC1_SPEC> {
+        TOUCH_PAD10_DAC_W::new(self, 29)
+    }
+}
+#[doc = "configure touch dac\n\nYou can [`read`](crate::Reg::read) this register and get [`touch_dac1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`touch_dac1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct TOUCH_DAC1_SPEC;
+impl crate::RegisterSpec for TOUCH_DAC1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`touch_dac1::R`](R) reader structure"]
+impl crate::Readable for TOUCH_DAC1_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`touch_dac1::W`](W) writer structure"]
+impl crate::Writable for TOUCH_DAC1_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets TOUCH_DAC1 to value 0"]
+impl crate::Resettable for TOUCH_DAC1_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_cntl/touch_filter_ctrl.rs

@@ -0,0 +1,204 @@
+#[doc = "Register `TOUCH_FILTER_CTRL` reader"]
+pub type R = crate::R<TOUCH_FILTER_CTRL_SPEC>;
+#[doc = "Register `TOUCH_FILTER_CTRL` writer"]
+pub type W = crate::W<TOUCH_FILTER_CTRL_SPEC>;
+#[doc = "Field `TOUCH_BYPASS_NEG_NOISE_THRES` reader - bypass neg noise thres"]
+pub type TOUCH_BYPASS_NEG_NOISE_THRES_R = crate::BitReader;
+#[doc = "Field `TOUCH_BYPASS_NEG_NOISE_THRES` writer - bypass neg noise thres"]
+pub type TOUCH_BYPASS_NEG_NOISE_THRES_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TOUCH_BYPASS_NOISE_THRES` reader - bypaas noise thres"]
+pub type TOUCH_BYPASS_NOISE_THRES_R = crate::BitReader;
+#[doc = "Field `TOUCH_BYPASS_NOISE_THRES` writer - bypaas noise thres"]
+pub type TOUCH_BYPASS_NOISE_THRES_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TOUCH_SMOOTH_LVL` reader - smooth filter factor"]
+pub type TOUCH_SMOOTH_LVL_R = crate::FieldReader;
+#[doc = "Field `TOUCH_SMOOTH_LVL` writer - smooth filter factor"]
+pub type TOUCH_SMOOTH_LVL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `TOUCH_JITTER_STEP` reader - touch jitter step"]
+pub type TOUCH_JITTER_STEP_R = crate::FieldReader;
+#[doc = "Field `TOUCH_JITTER_STEP` writer - touch jitter step"]
+pub type TOUCH_JITTER_STEP_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `TOUCH_NEG_NOISE_LIMIT` reader - negative threshold counter limit"]
+pub type TOUCH_NEG_NOISE_LIMIT_R = crate::FieldReader;
+#[doc = "Field `TOUCH_NEG_NOISE_LIMIT` writer - negative threshold counter limit"]
+pub type TOUCH_NEG_NOISE_LIMIT_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `TOUCH_NEG_NOISE_THRES` reader - neg noise thres"]
+pub type TOUCH_NEG_NOISE_THRES_R = crate::FieldReader;
+#[doc = "Field `TOUCH_NEG_NOISE_THRES` writer - neg noise thres"]
+pub type TOUCH_NEG_NOISE_THRES_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `TOUCH_NOISE_THRES` reader - noise thres"]
+pub type TOUCH_NOISE_THRES_R = crate::FieldReader;
+#[doc = "Field `TOUCH_NOISE_THRES` writer - noise thres"]
+pub type TOUCH_NOISE_THRES_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `TOUCH_HYSTERESIS` reader - hysteresis"]
+pub type TOUCH_HYSTERESIS_R = crate::FieldReader;
+#[doc = "Field `TOUCH_HYSTERESIS` writer - hysteresis"]
+pub type TOUCH_HYSTERESIS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `TOUCH_DEBOUNCE` reader - debounce counter"]
+pub type TOUCH_DEBOUNCE_R = crate::FieldReader;
+#[doc = "Field `TOUCH_DEBOUNCE` writer - debounce counter"]
+pub type TOUCH_DEBOUNCE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `TOUCH_FILTER_MODE` reader - 0: IIR ? 1: IIR ? 2: IIR 1/8 3: Jitter"]
+pub type TOUCH_FILTER_MODE_R = crate::FieldReader;
+#[doc = "Field `TOUCH_FILTER_MODE` writer - 0: IIR ? 1: IIR ? 2: IIR 1/8 3: Jitter"]
+pub type TOUCH_FILTER_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `TOUCH_FILTER_EN` reader - touch filter enable"]
+pub type TOUCH_FILTER_EN_R = crate::BitReader;
+#[doc = "Field `TOUCH_FILTER_EN` writer - touch filter enable"]
+pub type TOUCH_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 7 - bypass neg noise thres"]
+    #[inline(always)]
+    pub fn touch_bypass_neg_noise_thres(&self) -> TOUCH_BYPASS_NEG_NOISE_THRES_R {
+        TOUCH_BYPASS_NEG_NOISE_THRES_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - bypaas noise thres"]
+    #[inline(always)]
+    pub fn touch_bypass_noise_thres(&self) -> TOUCH_BYPASS_NOISE_THRES_R {
+        TOUCH_BYPASS_NOISE_THRES_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bits 9:10 - smooth filter factor"]
+    #[inline(always)]
+    pub fn touch_smooth_lvl(&self) -> TOUCH_SMOOTH_LVL_R {
+        TOUCH_SMOOTH_LVL_R::new(((self.bits >> 9) & 3) as u8)
+    }
+    #[doc = "Bits 11:14 - touch jitter step"]
+    #[inline(always)]
+    pub fn touch_jitter_step(&self) -> TOUCH_JITTER_STEP_R {
+        TOUCH_JITTER_STEP_R::new(((self.bits >> 11) & 0x0f) as u8)
+    }
+    #[doc = "Bits 15:18 - negative threshold counter limit"]
+    #[inline(always)]
+    pub fn touch_neg_noise_limit(&self) -> TOUCH_NEG_NOISE_LIMIT_R {
+        TOUCH_NEG_NOISE_LIMIT_R::new(((self.bits >> 15) & 0x0f) as u8)
+    }
+    #[doc = "Bits 19:20 - neg noise thres"]
+    #[inline(always)]
+    pub fn touch_neg_noise_thres(&self) -> TOUCH_NEG_NOISE_THRES_R {
+        TOUCH_NEG_NOISE_THRES_R::new(((self.bits >> 19) & 3) as u8)
+    }
+    #[doc = "Bits 21:22 - noise thres"]
+    #[inline(always)]
+    pub fn touch_noise_thres(&self) -> TOUCH_NOISE_THRES_R {
+        TOUCH_NOISE_THRES_R::new(((self.bits >> 21) & 3) as u8)
+    }
+    #[doc = "Bits 23:24 - hysteresis"]
+    #[inline(always)]
+    pub fn touch_hysteresis(&self) -> TOUCH_HYSTERESIS_R {
+        TOUCH_HYSTERESIS_R::new(((self.bits >> 23) & 3) as u8)
+    }
+    #[doc = "Bits 25:27 - debounce counter"]
+    #[inline(always)]
+    pub fn touch_debounce(&self) -> TOUCH_DEBOUNCE_R {
+        TOUCH_DEBOUNCE_R::new(((self.bits >> 25) & 7) as u8)
+    }
+    #[doc = "Bits 28:30 - 0: IIR ? 1: IIR ? 2: IIR 1/8 3: Jitter"]
+    #[inline(always)]
+    pub fn touch_filter_mode(&self) -> TOUCH_FILTER_MODE_R {
+        TOUCH_FILTER_MODE_R::new(((self.bits >> 28) & 7) as u8)
+    }
+    #[doc = "Bit 31 - touch filter enable"]
+    #[inline(always)]
+    pub fn touch_filter_en(&self) -> TOUCH_FILTER_EN_R {
+        TOUCH_FILTER_EN_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("TOUCH_FILTER_CTRL")
+            .field(
+                "touch_bypass_neg_noise_thres",
+                &self.touch_bypass_neg_noise_thres(),
+            )
+            .field("touch_bypass_noise_thres", &self.touch_bypass_noise_thres())
+            .field("touch_smooth_lvl", &self.touch_smooth_lvl())
+            .field("touch_jitter_step", &self.touch_jitter_step())
+            .field("touch_neg_noise_limit", &self.touch_neg_noise_limit())
+            .field("touch_neg_noise_thres", &self.touch_neg_noise_thres())
+            .field("touch_noise_thres", &self.touch_noise_thres())
+            .field("touch_hysteresis", &self.touch_hysteresis())
+            .field("touch_debounce", &self.touch_debounce())
+            .field("touch_filter_mode", &self.touch_filter_mode())
+            .field("touch_filter_en", &self.touch_filter_en())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 7 - bypass neg noise thres"]
+    #[inline(always)]
+    pub fn touch_bypass_neg_noise_thres(
+        &mut self,
+    ) -> TOUCH_BYPASS_NEG_NOISE_THRES_W<TOUCH_FILTER_CTRL_SPEC> {
+        TOUCH_BYPASS_NEG_NOISE_THRES_W::new(self, 7)
+    }
+    #[doc = "Bit 8 - bypaas noise thres"]
+    #[inline(always)]
+    pub fn touch_bypass_noise_thres(
+        &mut self,
+    ) -> TOUCH_BYPASS_NOISE_THRES_W<TOUCH_FILTER_CTRL_SPEC> {
+        TOUCH_BYPASS_NOISE_THRES_W::new(self, 8)
+    }
+    #[doc = "Bits 9:10 - smooth filter factor"]
+    #[inline(always)]
+    pub fn touch_smooth_lvl(&mut self) -> TOUCH_SMOOTH_LVL_W<TOUCH_FILTER_CTRL_SPEC> {
+        TOUCH_SMOOTH_LVL_W::new(self, 9)
+    }
+    #[doc = "Bits 11:14 - touch jitter step"]
+    #[inline(always)]
+    pub fn touch_jitter_step(&mut self) -> TOUCH_JITTER_STEP_W<TOUCH_FILTER_CTRL_SPEC> {
+        TOUCH_JITTER_STEP_W::new(self, 11)
+    }
+    #[doc = "Bits 15:18 - negative threshold counter limit"]
+    #[inline(always)]
+    pub fn touch_neg_noise_limit(&mut self) -> TOUCH_NEG_NOISE_LIMIT_W<TOUCH_FILTER_CTRL_SPEC> {
+        TOUCH_NEG_NOISE_LIMIT_W::new(self, 15)
+    }
+    #[doc = "Bits 19:20 - neg noise thres"]
+    #[inline(always)]
+    pub fn touch_neg_noise_thres(&mut self) -> TOUCH_NEG_NOISE_THRES_W<TOUCH_FILTER_CTRL_SPEC> {
+        TOUCH_NEG_NOISE_THRES_W::new(self, 19)
+    }
+    #[doc = "Bits 21:22 - noise thres"]
+    #[inline(always)]
+    pub fn touch_noise_thres(&mut self) -> TOUCH_NOISE_THRES_W<TOUCH_FILTER_CTRL_SPEC> {
+        TOUCH_NOISE_THRES_W::new(self, 21)
+    }
+    #[doc = "Bits 23:24 - hysteresis"]
+    #[inline(always)]
+    pub fn touch_hysteresis(&mut self) -> TOUCH_HYSTERESIS_W<TOUCH_FILTER_CTRL_SPEC> {
+        TOUCH_HYSTERESIS_W::new(self, 23)
+    }
+    #[doc = "Bits 25:27 - debounce counter"]
+    #[inline(always)]
+    pub fn touch_debounce(&mut self) -> TOUCH_DEBOUNCE_W<TOUCH_FILTER_CTRL_SPEC> {
+        TOUCH_DEBOUNCE_W::new(self, 25)
+    }
+    #[doc = "Bits 28:30 - 0: IIR ? 1: IIR ? 2: IIR 1/8 3: Jitter"]
+    #[inline(always)]
+    pub fn touch_filter_mode(&mut self) -> TOUCH_FILTER_MODE_W<TOUCH_FILTER_CTRL_SPEC> {
+        TOUCH_FILTER_MODE_W::new(self, 28)
+    }
+    #[doc = "Bit 31 - touch filter enable"]
+    #[inline(always)]
+    pub fn touch_filter_en(&mut self) -> TOUCH_FILTER_EN_W<TOUCH_FILTER_CTRL_SPEC> {
+        TOUCH_FILTER_EN_W::new(self, 31)
+    }
+}
+#[doc = "configure touch controller\n\nYou can [`read`](crate::Reg::read) this register and get [`touch_filter_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`touch_filter_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct TOUCH_FILTER_CTRL_SPEC;
+impl crate::RegisterSpec for TOUCH_FILTER_CTRL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`touch_filter_ctrl::R`](R) reader structure"]
+impl crate::Readable for TOUCH_FILTER_CTRL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`touch_filter_ctrl::W`](W) writer structure"]
+impl crate::Writable for TOUCH_FILTER_CTRL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets TOUCH_FILTER_CTRL to value 0x96aa_8800"]
+impl crate::Resettable for TOUCH_FILTER_CTRL_SPEC {
+    const RESET_VALUE: u32 = 0x96aa_8800;
+}

vendor/esp32s3/src/rtc_cntl/touch_scan_ctrl.rs

@@ -0,0 +1,142 @@
+#[doc = "Register `TOUCH_SCAN_CTRL` reader"]
+pub type R = crate::R<TOUCH_SCAN_CTRL_SPEC>;
+#[doc = "Register `TOUCH_SCAN_CTRL` writer"]
+pub type W = crate::W<TOUCH_SCAN_CTRL_SPEC>;
+#[doc = "Field `TOUCH_DENOISE_RES` reader - De-noise resolution: 12/10/8/4 bit"]
+pub type TOUCH_DENOISE_RES_R = crate::FieldReader;
+#[doc = "Field `TOUCH_DENOISE_RES` writer - De-noise resolution: 12/10/8/4 bit"]
+pub type TOUCH_DENOISE_RES_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `TOUCH_DENOISE_EN` reader - touch pad0 will be used to de-noise"]
+pub type TOUCH_DENOISE_EN_R = crate::BitReader;
+#[doc = "Field `TOUCH_DENOISE_EN` writer - touch pad0 will be used to de-noise"]
+pub type TOUCH_DENOISE_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TOUCH_INACTIVE_CONNECTION` reader - inactive touch pads connect to 1: gnd 0: HighZ"]
+pub type TOUCH_INACTIVE_CONNECTION_R = crate::BitReader;
+#[doc = "Field `TOUCH_INACTIVE_CONNECTION` writer - inactive touch pads connect to 1: gnd 0: HighZ"]
+pub type TOUCH_INACTIVE_CONNECTION_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TOUCH_SHIELD_PAD_EN` reader - touch pad14 will be used as shield"]
+pub type TOUCH_SHIELD_PAD_EN_R = crate::BitReader;
+#[doc = "Field `TOUCH_SHIELD_PAD_EN` writer - touch pad14 will be used as shield"]
+pub type TOUCH_SHIELD_PAD_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TOUCH_SCAN_PAD_MAP` reader - touch scan mode pad enable map"]
+pub type TOUCH_SCAN_PAD_MAP_R = crate::FieldReader<u16>;
+#[doc = "Field `TOUCH_SCAN_PAD_MAP` writer - touch scan mode pad enable map"]
+pub type TOUCH_SCAN_PAD_MAP_W<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>;
+#[doc = "Field `TOUCH_BUFDRV` reader - touch7 buffer driver strength"]
+pub type TOUCH_BUFDRV_R = crate::FieldReader;
+#[doc = "Field `TOUCH_BUFDRV` writer - touch7 buffer driver strength"]
+pub type TOUCH_BUFDRV_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `TOUCH_OUT_RING` reader - select out ring pad"]
+pub type TOUCH_OUT_RING_R = crate::FieldReader;
+#[doc = "Field `TOUCH_OUT_RING` writer - select out ring pad"]
+pub type TOUCH_OUT_RING_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+impl R {
+    #[doc = "Bits 0:1 - De-noise resolution: 12/10/8/4 bit"]
+    #[inline(always)]
+    pub fn touch_denoise_res(&self) -> TOUCH_DENOISE_RES_R {
+        TOUCH_DENOISE_RES_R::new((self.bits & 3) as u8)
+    }
+    #[doc = "Bit 2 - touch pad0 will be used to de-noise"]
+    #[inline(always)]
+    pub fn touch_denoise_en(&self) -> TOUCH_DENOISE_EN_R {
+        TOUCH_DENOISE_EN_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 8 - inactive touch pads connect to 1: gnd 0: HighZ"]
+    #[inline(always)]
+    pub fn touch_inactive_connection(&self) -> TOUCH_INACTIVE_CONNECTION_R {
+        TOUCH_INACTIVE_CONNECTION_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - touch pad14 will be used as shield"]
+    #[inline(always)]
+    pub fn touch_shield_pad_en(&self) -> TOUCH_SHIELD_PAD_EN_R {
+        TOUCH_SHIELD_PAD_EN_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bits 10:24 - touch scan mode pad enable map"]
+    #[inline(always)]
+    pub fn touch_scan_pad_map(&self) -> TOUCH_SCAN_PAD_MAP_R {
+        TOUCH_SCAN_PAD_MAP_R::new(((self.bits >> 10) & 0x7fff) as u16)
+    }
+    #[doc = "Bits 25:27 - touch7 buffer driver strength"]
+    #[inline(always)]
+    pub fn touch_bufdrv(&self) -> TOUCH_BUFDRV_R {
+        TOUCH_BUFDRV_R::new(((self.bits >> 25) & 7) as u8)
+    }
+    #[doc = "Bits 28:31 - select out ring pad"]
+    #[inline(always)]
+    pub fn touch_out_ring(&self) -> TOUCH_OUT_RING_R {
+        TOUCH_OUT_RING_R::new(((self.bits >> 28) & 0x0f) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("TOUCH_SCAN_CTRL")
+            .field("touch_denoise_res", &self.touch_denoise_res())
+            .field("touch_denoise_en", &self.touch_denoise_en())
+            .field(
+                "touch_inactive_connection",
+                &self.touch_inactive_connection(),
+            )
+            .field("touch_shield_pad_en", &self.touch_shield_pad_en())
+            .field("touch_scan_pad_map", &self.touch_scan_pad_map())
+            .field("touch_bufdrv", &self.touch_bufdrv())
+            .field("touch_out_ring", &self.touch_out_ring())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:1 - De-noise resolution: 12/10/8/4 bit"]
+    #[inline(always)]
+    pub fn touch_denoise_res(&mut self) -> TOUCH_DENOISE_RES_W<TOUCH_SCAN_CTRL_SPEC> {
+        TOUCH_DENOISE_RES_W::new(self, 0)
+    }
+    #[doc = "Bit 2 - touch pad0 will be used to de-noise"]
+    #[inline(always)]
+    pub fn touch_denoise_en(&mut self) -> TOUCH_DENOISE_EN_W<TOUCH_SCAN_CTRL_SPEC> {
+        TOUCH_DENOISE_EN_W::new(self, 2)
+    }
+    #[doc = "Bit 8 - inactive touch pads connect to 1: gnd 0: HighZ"]
+    #[inline(always)]
+    pub fn touch_inactive_connection(
+        &mut self,
+    ) -> TOUCH_INACTIVE_CONNECTION_W<TOUCH_SCAN_CTRL_SPEC> {
+        TOUCH_INACTIVE_CONNECTION_W::new(self, 8)
+    }
+    #[doc = "Bit 9 - touch pad14 will be used as shield"]
+    #[inline(always)]
+    pub fn touch_shield_pad_en(&mut self) -> TOUCH_SHIELD_PAD_EN_W<TOUCH_SCAN_CTRL_SPEC> {
+        TOUCH_SHIELD_PAD_EN_W::new(self, 9)
+    }
+    #[doc = "Bits 10:24 - touch scan mode pad enable map"]
+    #[inline(always)]
+    pub fn touch_scan_pad_map(&mut self) -> TOUCH_SCAN_PAD_MAP_W<TOUCH_SCAN_CTRL_SPEC> {
+        TOUCH_SCAN_PAD_MAP_W::new(self, 10)
+    }
+    #[doc = "Bits 25:27 - touch7 buffer driver strength"]
+    #[inline(always)]
+    pub fn touch_bufdrv(&mut self) -> TOUCH_BUFDRV_W<TOUCH_SCAN_CTRL_SPEC> {
+        TOUCH_BUFDRV_W::new(self, 25)
+    }
+    #[doc = "Bits 28:31 - select out ring pad"]
+    #[inline(always)]
+    pub fn touch_out_ring(&mut self) -> TOUCH_OUT_RING_W<TOUCH_SCAN_CTRL_SPEC> {
+        TOUCH_OUT_RING_W::new(self, 28)
+    }
+}
+#[doc = "configure touch controller\n\nYou can [`read`](crate::Reg::read) this register and get [`touch_scan_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`touch_scan_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct TOUCH_SCAN_CTRL_SPEC;
+impl crate::RegisterSpec for TOUCH_SCAN_CTRL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`touch_scan_ctrl::R`](R) reader structure"]
+impl crate::Readable for TOUCH_SCAN_CTRL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`touch_scan_ctrl::W`](W) writer structure"]
+impl crate::Writable for TOUCH_SCAN_CTRL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets TOUCH_SCAN_CTRL to value 0xf000_0102"]
+impl crate::Resettable for TOUCH_SCAN_CTRL_SPEC {
+    const RESET_VALUE: u32 = 0xf000_0102;
+}

vendor/esp32s3/src/rtc_cntl/touch_slp_thres.rs

@@ -0,0 +1,77 @@
+#[doc = "Register `TOUCH_SLP_THRES` reader"]
+pub type R = crate::R<TOUCH_SLP_THRES_SPEC>;
+#[doc = "Register `TOUCH_SLP_THRES` writer"]
+pub type W = crate::W<TOUCH_SLP_THRES_SPEC>;
+#[doc = "Field `TOUCH_SLP_TH` reader - the threshold for sleep touch pad"]
+pub type TOUCH_SLP_TH_R = crate::FieldReader<u32>;
+#[doc = "Field `TOUCH_SLP_TH` writer - the threshold for sleep touch pad"]
+pub type TOUCH_SLP_TH_W<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>;
+#[doc = "Field `TOUCH_SLP_APPROACH_EN` reader - sleep pad approach function enable"]
+pub type TOUCH_SLP_APPROACH_EN_R = crate::BitReader;
+#[doc = "Field `TOUCH_SLP_APPROACH_EN` writer - sleep pad approach function enable"]
+pub type TOUCH_SLP_APPROACH_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TOUCH_SLP_PAD` reader - configure which pad as slp pad"]
+pub type TOUCH_SLP_PAD_R = crate::FieldReader;
+#[doc = "Field `TOUCH_SLP_PAD` writer - configure which pad as slp pad"]
+pub type TOUCH_SLP_PAD_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
+impl R {
+    #[doc = "Bits 0:21 - the threshold for sleep touch pad"]
+    #[inline(always)]
+    pub fn touch_slp_th(&self) -> TOUCH_SLP_TH_R {
+        TOUCH_SLP_TH_R::new(self.bits & 0x003f_ffff)
+    }
+    #[doc = "Bit 26 - sleep pad approach function enable"]
+    #[inline(always)]
+    pub fn touch_slp_approach_en(&self) -> TOUCH_SLP_APPROACH_EN_R {
+        TOUCH_SLP_APPROACH_EN_R::new(((self.bits >> 26) & 1) != 0)
+    }
+    #[doc = "Bits 27:31 - configure which pad as slp pad"]
+    #[inline(always)]
+    pub fn touch_slp_pad(&self) -> TOUCH_SLP_PAD_R {
+        TOUCH_SLP_PAD_R::new(((self.bits >> 27) & 0x1f) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("TOUCH_SLP_THRES")
+            .field("touch_slp_th", &self.touch_slp_th())
+            .field("touch_slp_approach_en", &self.touch_slp_approach_en())
+            .field("touch_slp_pad", &self.touch_slp_pad())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:21 - the threshold for sleep touch pad"]
+    #[inline(always)]
+    pub fn touch_slp_th(&mut self) -> TOUCH_SLP_TH_W<TOUCH_SLP_THRES_SPEC> {
+        TOUCH_SLP_TH_W::new(self, 0)
+    }
+    #[doc = "Bit 26 - sleep pad approach function enable"]
+    #[inline(always)]
+    pub fn touch_slp_approach_en(&mut self) -> TOUCH_SLP_APPROACH_EN_W<TOUCH_SLP_THRES_SPEC> {
+        TOUCH_SLP_APPROACH_EN_W::new(self, 26)
+    }
+    #[doc = "Bits 27:31 - configure which pad as slp pad"]
+    #[inline(always)]
+    pub fn touch_slp_pad(&mut self) -> TOUCH_SLP_PAD_W<TOUCH_SLP_THRES_SPEC> {
+        TOUCH_SLP_PAD_W::new(self, 27)
+    }
+}
+#[doc = "configure touch controller\n\nYou can [`read`](crate::Reg::read) this register and get [`touch_slp_thres::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`touch_slp_thres::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct TOUCH_SLP_THRES_SPEC;
+impl crate::RegisterSpec for TOUCH_SLP_THRES_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`touch_slp_thres::R`](R) reader structure"]
+impl crate::Readable for TOUCH_SLP_THRES_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`touch_slp_thres::W`](W) writer structure"]
+impl crate::Writable for TOUCH_SLP_THRES_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets TOUCH_SLP_THRES to value 0x7800_0000"]
+impl crate::Resettable for TOUCH_SLP_THRES_SPEC {
+    const RESET_VALUE: u32 = 0x7800_0000;
+}

vendor/esp32s3/src/rtc_cntl/touch_timeout_ctrl.rs

@@ -0,0 +1,62 @@
+#[doc = "Register `TOUCH_TIMEOUT_CTRL` reader"]
+pub type R = crate::R<TOUCH_TIMEOUT_CTRL_SPEC>;
+#[doc = "Register `TOUCH_TIMEOUT_CTRL` writer"]
+pub type W = crate::W<TOUCH_TIMEOUT_CTRL_SPEC>;
+#[doc = "Field `TOUCH_TIMEOUT_NUM` reader - configure touch timerout time"]
+pub type TOUCH_TIMEOUT_NUM_R = crate::FieldReader<u32>;
+#[doc = "Field `TOUCH_TIMEOUT_NUM` writer - configure touch timerout time"]
+pub type TOUCH_TIMEOUT_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>;
+#[doc = "Field `TOUCH_TIMEOUT_EN` reader - enable touch timerout"]
+pub type TOUCH_TIMEOUT_EN_R = crate::BitReader;
+#[doc = "Field `TOUCH_TIMEOUT_EN` writer - enable touch timerout"]
+pub type TOUCH_TIMEOUT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 0:21 - configure touch timerout time"]
+    #[inline(always)]
+    pub fn touch_timeout_num(&self) -> TOUCH_TIMEOUT_NUM_R {
+        TOUCH_TIMEOUT_NUM_R::new(self.bits & 0x003f_ffff)
+    }
+    #[doc = "Bit 22 - enable touch timerout"]
+    #[inline(always)]
+    pub fn touch_timeout_en(&self) -> TOUCH_TIMEOUT_EN_R {
+        TOUCH_TIMEOUT_EN_R::new(((self.bits >> 22) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("TOUCH_TIMEOUT_CTRL")
+            .field("touch_timeout_num", &self.touch_timeout_num())
+            .field("touch_timeout_en", &self.touch_timeout_en())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:21 - configure touch timerout time"]
+    #[inline(always)]
+    pub fn touch_timeout_num(&mut self) -> TOUCH_TIMEOUT_NUM_W<TOUCH_TIMEOUT_CTRL_SPEC> {
+        TOUCH_TIMEOUT_NUM_W::new(self, 0)
+    }
+    #[doc = "Bit 22 - enable touch timerout"]
+    #[inline(always)]
+    pub fn touch_timeout_en(&mut self) -> TOUCH_TIMEOUT_EN_W<TOUCH_TIMEOUT_CTRL_SPEC> {
+        TOUCH_TIMEOUT_EN_W::new(self, 22)
+    }
+}
+#[doc = "configure touch controller\n\nYou can [`read`](crate::Reg::read) this register and get [`touch_timeout_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`touch_timeout_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct TOUCH_TIMEOUT_CTRL_SPEC;
+impl crate::RegisterSpec for TOUCH_TIMEOUT_CTRL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`touch_timeout_ctrl::R`](R) reader structure"]
+impl crate::Readable for TOUCH_TIMEOUT_CTRL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`touch_timeout_ctrl::W`](W) writer structure"]
+impl crate::Writable for TOUCH_TIMEOUT_CTRL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets TOUCH_TIMEOUT_CTRL to value 0x007f_ffff"]
+impl crate::Resettable for TOUCH_TIMEOUT_CTRL_SPEC {
+    const RESET_VALUE: u32 = 0x007f_ffff;
+}

vendor/esp32s3/src/rtc_cntl/ulp_cp_ctrl.rs

@@ -0,0 +1,129 @@
+#[doc = "Register `ULP_CP_CTRL` reader"]
+pub type R = crate::R<ULP_CP_CTRL_SPEC>;
+#[doc = "Register `ULP_CP_CTRL` writer"]
+pub type W = crate::W<ULP_CP_CTRL_SPEC>;
+#[doc = "Field `ULP_CP_MEM_ADDR_INIT` reader - No public"]
+pub type ULP_CP_MEM_ADDR_INIT_R = crate::FieldReader<u16>;
+#[doc = "Field `ULP_CP_MEM_ADDR_INIT` writer - No public"]
+pub type ULP_CP_MEM_ADDR_INIT_W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>;
+#[doc = "Field `ULP_CP_MEM_ADDR_SIZE` reader - No public"]
+pub type ULP_CP_MEM_ADDR_SIZE_R = crate::FieldReader<u16>;
+#[doc = "Field `ULP_CP_MEM_ADDR_SIZE` writer - No public"]
+pub type ULP_CP_MEM_ADDR_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>;
+#[doc = "Field `ULP_CP_MEM_OFFST_CLR` writer - No public"]
+pub type ULP_CP_MEM_OFFST_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ULP_CP_CLK_FO` reader - ulp coprocessor clk force on"]
+pub type ULP_CP_CLK_FO_R = crate::BitReader;
+#[doc = "Field `ULP_CP_CLK_FO` writer - ulp coprocessor clk force on"]
+pub type ULP_CP_CLK_FO_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ULP_CP_RESET` reader - ulp coprocessor clk software reset"]
+pub type ULP_CP_RESET_R = crate::BitReader;
+#[doc = "Field `ULP_CP_RESET` writer - ulp coprocessor clk software reset"]
+pub type ULP_CP_RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ULP_CP_FORCE_START_TOP` reader - 1: ULP-coprocessor is started by SW"]
+pub type ULP_CP_FORCE_START_TOP_R = crate::BitReader;
+#[doc = "Field `ULP_CP_FORCE_START_TOP` writer - 1: ULP-coprocessor is started by SW"]
+pub type ULP_CP_FORCE_START_TOP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ULP_CP_START_TOP` reader - Write 1 to start ULP-coprocessor"]
+pub type ULP_CP_START_TOP_R = crate::BitReader;
+#[doc = "Field `ULP_CP_START_TOP` writer - Write 1 to start ULP-coprocessor"]
+pub type ULP_CP_START_TOP_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 0:10 - No public"]
+    #[inline(always)]
+    pub fn ulp_cp_mem_addr_init(&self) -> ULP_CP_MEM_ADDR_INIT_R {
+        ULP_CP_MEM_ADDR_INIT_R::new((self.bits & 0x07ff) as u16)
+    }
+    #[doc = "Bits 11:21 - No public"]
+    #[inline(always)]
+    pub fn ulp_cp_mem_addr_size(&self) -> ULP_CP_MEM_ADDR_SIZE_R {
+        ULP_CP_MEM_ADDR_SIZE_R::new(((self.bits >> 11) & 0x07ff) as u16)
+    }
+    #[doc = "Bit 28 - ulp coprocessor clk force on"]
+    #[inline(always)]
+    pub fn ulp_cp_clk_fo(&self) -> ULP_CP_CLK_FO_R {
+        ULP_CP_CLK_FO_R::new(((self.bits >> 28) & 1) != 0)
+    }
+    #[doc = "Bit 29 - ulp coprocessor clk software reset"]
+    #[inline(always)]
+    pub fn ulp_cp_reset(&self) -> ULP_CP_RESET_R {
+        ULP_CP_RESET_R::new(((self.bits >> 29) & 1) != 0)
+    }
+    #[doc = "Bit 30 - 1: ULP-coprocessor is started by SW"]
+    #[inline(always)]
+    pub fn ulp_cp_force_start_top(&self) -> ULP_CP_FORCE_START_TOP_R {
+        ULP_CP_FORCE_START_TOP_R::new(((self.bits >> 30) & 1) != 0)
+    }
+    #[doc = "Bit 31 - Write 1 to start ULP-coprocessor"]
+    #[inline(always)]
+    pub fn ulp_cp_start_top(&self) -> ULP_CP_START_TOP_R {
+        ULP_CP_START_TOP_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("ULP_CP_CTRL")
+            .field("ulp_cp_mem_addr_init", &self.ulp_cp_mem_addr_init())
+            .field("ulp_cp_mem_addr_size", &self.ulp_cp_mem_addr_size())
+            .field("ulp_cp_clk_fo", &self.ulp_cp_clk_fo())
+            .field("ulp_cp_reset", &self.ulp_cp_reset())
+            .field("ulp_cp_force_start_top", &self.ulp_cp_force_start_top())
+            .field("ulp_cp_start_top", &self.ulp_cp_start_top())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:10 - No public"]
+    #[inline(always)]
+    pub fn ulp_cp_mem_addr_init(&mut self) -> ULP_CP_MEM_ADDR_INIT_W<ULP_CP_CTRL_SPEC> {
+        ULP_CP_MEM_ADDR_INIT_W::new(self, 0)
+    }
+    #[doc = "Bits 11:21 - No public"]
+    #[inline(always)]
+    pub fn ulp_cp_mem_addr_size(&mut self) -> ULP_CP_MEM_ADDR_SIZE_W<ULP_CP_CTRL_SPEC> {
+        ULP_CP_MEM_ADDR_SIZE_W::new(self, 11)
+    }
+    #[doc = "Bit 22 - No public"]
+    #[inline(always)]
+    pub fn ulp_cp_mem_offst_clr(&mut self) -> ULP_CP_MEM_OFFST_CLR_W<ULP_CP_CTRL_SPEC> {
+        ULP_CP_MEM_OFFST_CLR_W::new(self, 22)
+    }
+    #[doc = "Bit 28 - ulp coprocessor clk force on"]
+    #[inline(always)]
+    pub fn ulp_cp_clk_fo(&mut self) -> ULP_CP_CLK_FO_W<ULP_CP_CTRL_SPEC> {
+        ULP_CP_CLK_FO_W::new(self, 28)
+    }
+    #[doc = "Bit 29 - ulp coprocessor clk software reset"]
+    #[inline(always)]
+    pub fn ulp_cp_reset(&mut self) -> ULP_CP_RESET_W<ULP_CP_CTRL_SPEC> {
+        ULP_CP_RESET_W::new(self, 29)
+    }
+    #[doc = "Bit 30 - 1: ULP-coprocessor is started by SW"]
+    #[inline(always)]
+    pub fn ulp_cp_force_start_top(&mut self) -> ULP_CP_FORCE_START_TOP_W<ULP_CP_CTRL_SPEC> {
+        ULP_CP_FORCE_START_TOP_W::new(self, 30)
+    }
+    #[doc = "Bit 31 - Write 1 to start ULP-coprocessor"]
+    #[inline(always)]
+    pub fn ulp_cp_start_top(&mut self) -> ULP_CP_START_TOP_W<ULP_CP_CTRL_SPEC> {
+        ULP_CP_START_TOP_W::new(self, 31)
+    }
+}
+#[doc = "configure ulp\n\nYou can [`read`](crate::Reg::read) this register and get [`ulp_cp_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ulp_cp_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ULP_CP_CTRL_SPEC;
+impl crate::RegisterSpec for ULP_CP_CTRL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`ulp_cp_ctrl::R`](R) reader structure"]
+impl crate::Readable for ULP_CP_CTRL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`ulp_cp_ctrl::W`](W) writer structure"]
+impl crate::Writable for ULP_CP_CTRL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets ULP_CP_CTRL to value 0x0010_0200"]
+impl crate::Resettable for ULP_CP_CTRL_SPEC {
+    const RESET_VALUE: u32 = 0x0010_0200;
+}

vendor/esp32s3/src/rtc_cntl/ulp_cp_timer.rs

@@ -0,0 +1,84 @@
+#[doc = "Register `ULP_CP_TIMER` reader"]
+pub type R = crate::R<ULP_CP_TIMER_SPEC>;
+#[doc = "Register `ULP_CP_TIMER` writer"]
+pub type W = crate::W<ULP_CP_TIMER_SPEC>;
+#[doc = "Field `ULP_CP_PC_INIT` reader - ULP-coprocessor PC initial address"]
+pub type ULP_CP_PC_INIT_R = crate::FieldReader<u16>;
+#[doc = "Field `ULP_CP_PC_INIT` writer - ULP-coprocessor PC initial address"]
+pub type ULP_CP_PC_INIT_W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>;
+#[doc = "Field `ULP_CP_GPIO_WAKEUP_ENA` reader - ULP-coprocessor wakeup by GPIO enable"]
+pub type ULP_CP_GPIO_WAKEUP_ENA_R = crate::BitReader;
+#[doc = "Field `ULP_CP_GPIO_WAKEUP_ENA` writer - ULP-coprocessor wakeup by GPIO enable"]
+pub type ULP_CP_GPIO_WAKEUP_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ULP_CP_GPIO_WAKEUP_CLR` writer - ULP-coprocessor wakeup by GPIO state clear"]
+pub type ULP_CP_GPIO_WAKEUP_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ULP_CP_SLP_TIMER_EN` reader - ULP-coprocessor timer enable bit"]
+pub type ULP_CP_SLP_TIMER_EN_R = crate::BitReader;
+#[doc = "Field `ULP_CP_SLP_TIMER_EN` writer - ULP-coprocessor timer enable bit"]
+pub type ULP_CP_SLP_TIMER_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 0:10 - ULP-coprocessor PC initial address"]
+    #[inline(always)]
+    pub fn ulp_cp_pc_init(&self) -> ULP_CP_PC_INIT_R {
+        ULP_CP_PC_INIT_R::new((self.bits & 0x07ff) as u16)
+    }
+    #[doc = "Bit 29 - ULP-coprocessor wakeup by GPIO enable"]
+    #[inline(always)]
+    pub fn ulp_cp_gpio_wakeup_ena(&self) -> ULP_CP_GPIO_WAKEUP_ENA_R {
+        ULP_CP_GPIO_WAKEUP_ENA_R::new(((self.bits >> 29) & 1) != 0)
+    }
+    #[doc = "Bit 31 - ULP-coprocessor timer enable bit"]
+    #[inline(always)]
+    pub fn ulp_cp_slp_timer_en(&self) -> ULP_CP_SLP_TIMER_EN_R {
+        ULP_CP_SLP_TIMER_EN_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("ULP_CP_TIMER")
+            .field("ulp_cp_pc_init", &self.ulp_cp_pc_init())
+            .field("ulp_cp_gpio_wakeup_ena", &self.ulp_cp_gpio_wakeup_ena())
+            .field("ulp_cp_slp_timer_en", &self.ulp_cp_slp_timer_en())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:10 - ULP-coprocessor PC initial address"]
+    #[inline(always)]
+    pub fn ulp_cp_pc_init(&mut self) -> ULP_CP_PC_INIT_W<ULP_CP_TIMER_SPEC> {
+        ULP_CP_PC_INIT_W::new(self, 0)
+    }
+    #[doc = "Bit 29 - ULP-coprocessor wakeup by GPIO enable"]
+    #[inline(always)]
+    pub fn ulp_cp_gpio_wakeup_ena(&mut self) -> ULP_CP_GPIO_WAKEUP_ENA_W<ULP_CP_TIMER_SPEC> {
+        ULP_CP_GPIO_WAKEUP_ENA_W::new(self, 29)
+    }
+    #[doc = "Bit 30 - ULP-coprocessor wakeup by GPIO state clear"]
+    #[inline(always)]
+    pub fn ulp_cp_gpio_wakeup_clr(&mut self) -> ULP_CP_GPIO_WAKEUP_CLR_W<ULP_CP_TIMER_SPEC> {
+        ULP_CP_GPIO_WAKEUP_CLR_W::new(self, 30)
+    }
+    #[doc = "Bit 31 - ULP-coprocessor timer enable bit"]
+    #[inline(always)]
+    pub fn ulp_cp_slp_timer_en(&mut self) -> ULP_CP_SLP_TIMER_EN_W<ULP_CP_TIMER_SPEC> {
+        ULP_CP_SLP_TIMER_EN_W::new(self, 31)
+    }
+}
+#[doc = "configure ulp\n\nYou can [`read`](crate::Reg::read) this register and get [`ulp_cp_timer::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ulp_cp_timer::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ULP_CP_TIMER_SPEC;
+impl crate::RegisterSpec for ULP_CP_TIMER_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`ulp_cp_timer::R`](R) reader structure"]
+impl crate::Readable for ULP_CP_TIMER_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`ulp_cp_timer::W`](W) writer structure"]
+impl crate::Writable for ULP_CP_TIMER_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets ULP_CP_TIMER to value 0"]
+impl crate::Resettable for ULP_CP_TIMER_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_cntl/ulp_cp_timer_1.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `ULP_CP_TIMER_1` reader"]
+pub type R = crate::R<ULP_CP_TIMER_1_SPEC>;
+#[doc = "Register `ULP_CP_TIMER_1` writer"]
+pub type W = crate::W<ULP_CP_TIMER_1_SPEC>;
+#[doc = "Field `ULP_CP_TIMER_SLP_CYCLE` reader - sleep cycles for ULP-coprocessor timer"]
+pub type ULP_CP_TIMER_SLP_CYCLE_R = crate::FieldReader<u32>;
+#[doc = "Field `ULP_CP_TIMER_SLP_CYCLE` writer - sleep cycles for ULP-coprocessor timer"]
+pub type ULP_CP_TIMER_SLP_CYCLE_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
+impl R {
+    #[doc = "Bits 8:31 - sleep cycles for ULP-coprocessor timer"]
+    #[inline(always)]
+    pub fn ulp_cp_timer_slp_cycle(&self) -> ULP_CP_TIMER_SLP_CYCLE_R {
+        ULP_CP_TIMER_SLP_CYCLE_R::new((self.bits >> 8) & 0x00ff_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("ULP_CP_TIMER_1")
+            .field("ulp_cp_timer_slp_cycle", &self.ulp_cp_timer_slp_cycle())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 8:31 - sleep cycles for ULP-coprocessor timer"]
+    #[inline(always)]
+    pub fn ulp_cp_timer_slp_cycle(&mut self) -> ULP_CP_TIMER_SLP_CYCLE_W<ULP_CP_TIMER_1_SPEC> {
+        ULP_CP_TIMER_SLP_CYCLE_W::new(self, 8)
+    }
+}
+#[doc = "configure ulp sleep time\n\nYou can [`read`](crate::Reg::read) this register and get [`ulp_cp_timer_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ulp_cp_timer_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ULP_CP_TIMER_1_SPEC;
+impl crate::RegisterSpec for ULP_CP_TIMER_1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`ulp_cp_timer_1::R`](R) reader structure"]
+impl crate::Readable for ULP_CP_TIMER_1_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`ulp_cp_timer_1::W`](W) writer structure"]
+impl crate::Writable for ULP_CP_TIMER_1_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets ULP_CP_TIMER_1 to value 0xc800"]
+impl crate::Resettable for ULP_CP_TIMER_1_SPEC {
+    const RESET_VALUE: u32 = 0xc800;
+}

vendor/esp32s3/src/rtc_cntl/usb_conf.rs

@@ -0,0 +1,317 @@
+#[doc = "Register `USB_CONF` reader"]
+pub type R = crate::R<USB_CONF_SPEC>;
+#[doc = "Register `USB_CONF` writer"]
+pub type W = crate::W<USB_CONF_SPEC>;
+#[doc = "Field `USB_VREFH` reader - reg_usb_vrefh"]
+pub type USB_VREFH_R = crate::FieldReader;
+#[doc = "Field `USB_VREFH` writer - reg_usb_vrefh"]
+pub type USB_VREFH_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `USB_VREFL` reader - reg_usb_vrefl"]
+pub type USB_VREFL_R = crate::FieldReader;
+#[doc = "Field `USB_VREFL` writer - reg_usb_vrefl"]
+pub type USB_VREFL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `USB_VREF_OVERRIDE` reader - reg_usb_vref_override"]
+pub type USB_VREF_OVERRIDE_R = crate::BitReader;
+#[doc = "Field `USB_VREF_OVERRIDE` writer - reg_usb_vref_override"]
+pub type USB_VREF_OVERRIDE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `USB_PAD_PULL_OVERRIDE` reader - reg_usb_pad_pull_override"]
+pub type USB_PAD_PULL_OVERRIDE_R = crate::BitReader;
+#[doc = "Field `USB_PAD_PULL_OVERRIDE` writer - reg_usb_pad_pull_override"]
+pub type USB_PAD_PULL_OVERRIDE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `USB_DP_PULLUP` reader - reg_usb_dp_pullup"]
+pub type USB_DP_PULLUP_R = crate::BitReader;
+#[doc = "Field `USB_DP_PULLUP` writer - reg_usb_dp_pullup"]
+pub type USB_DP_PULLUP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `USB_DP_PULLDOWN` reader - reg_usb_dp_pulldown"]
+pub type USB_DP_PULLDOWN_R = crate::BitReader;
+#[doc = "Field `USB_DP_PULLDOWN` writer - reg_usb_dp_pulldown"]
+pub type USB_DP_PULLDOWN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `USB_DM_PULLUP` reader - reg_usb_dm_pullup"]
+pub type USB_DM_PULLUP_R = crate::BitReader;
+#[doc = "Field `USB_DM_PULLUP` writer - reg_usb_dm_pullup"]
+pub type USB_DM_PULLUP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `USB_DM_PULLDOWN` reader - reg_usb_dm_pulldown"]
+pub type USB_DM_PULLDOWN_R = crate::BitReader;
+#[doc = "Field `USB_DM_PULLDOWN` writer - reg_usb_dm_pulldown"]
+pub type USB_DM_PULLDOWN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `USB_PULLUP_VALUE` reader - reg_usb_pullup_value"]
+pub type USB_PULLUP_VALUE_R = crate::BitReader;
+#[doc = "Field `USB_PULLUP_VALUE` writer - reg_usb_pullup_value"]
+pub type USB_PULLUP_VALUE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `USB_PAD_ENABLE_OVERRIDE` reader - reg_usb_pad_enable_override"]
+pub type USB_PAD_ENABLE_OVERRIDE_R = crate::BitReader;
+#[doc = "Field `USB_PAD_ENABLE_OVERRIDE` writer - reg_usb_pad_enable_override"]
+pub type USB_PAD_ENABLE_OVERRIDE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `USB_PAD_ENABLE` reader - reg_usb_pad_enable"]
+pub type USB_PAD_ENABLE_R = crate::BitReader;
+#[doc = "Field `USB_PAD_ENABLE` writer - reg_usb_pad_enable"]
+pub type USB_PAD_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `USB_TXM` reader - reg_usb_txm"]
+pub type USB_TXM_R = crate::BitReader;
+#[doc = "Field `USB_TXM` writer - reg_usb_txm"]
+pub type USB_TXM_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `USB_TXP` reader - reg_usb_txp"]
+pub type USB_TXP_R = crate::BitReader;
+#[doc = "Field `USB_TXP` writer - reg_usb_txp"]
+pub type USB_TXP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `USB_TX_EN` reader - reg_usb_tx_en"]
+pub type USB_TX_EN_R = crate::BitReader;
+#[doc = "Field `USB_TX_EN` writer - reg_usb_tx_en"]
+pub type USB_TX_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `USB_TX_EN_OVERRIDE` reader - reg_usb_tx_en_override"]
+pub type USB_TX_EN_OVERRIDE_R = crate::BitReader;
+#[doc = "Field `USB_TX_EN_OVERRIDE` writer - reg_usb_tx_en_override"]
+pub type USB_TX_EN_OVERRIDE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `USB_RESET_DISABLE` reader - reg_usb_reset_disable"]
+pub type USB_RESET_DISABLE_R = crate::BitReader;
+#[doc = "Field `USB_RESET_DISABLE` writer - reg_usb_reset_disable"]
+pub type USB_RESET_DISABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `IO_MUX_RESET_DISABLE` reader - reg_io_mux_reset_disable"]
+pub type IO_MUX_RESET_DISABLE_R = crate::BitReader;
+#[doc = "Field `IO_MUX_RESET_DISABLE` writer - reg_io_mux_reset_disable"]
+pub type IO_MUX_RESET_DISABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SW_USB_PHY_SEL` reader - reg_sw_usb_phy_sel"]
+pub type SW_USB_PHY_SEL_R = crate::BitReader;
+#[doc = "Field `SW_USB_PHY_SEL` writer - reg_sw_usb_phy_sel"]
+pub type SW_USB_PHY_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SW_HW_USB_PHY_SEL` reader - reg_sw_hw_usb_phy_sel"]
+pub type SW_HW_USB_PHY_SEL_R = crate::BitReader;
+#[doc = "Field `SW_HW_USB_PHY_SEL` writer - reg_sw_hw_usb_phy_sel"]
+pub type SW_HW_USB_PHY_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 0:1 - reg_usb_vrefh"]
+    #[inline(always)]
+    pub fn usb_vrefh(&self) -> USB_VREFH_R {
+        USB_VREFH_R::new((self.bits & 3) as u8)
+    }
+    #[doc = "Bits 2:3 - reg_usb_vrefl"]
+    #[inline(always)]
+    pub fn usb_vrefl(&self) -> USB_VREFL_R {
+        USB_VREFL_R::new(((self.bits >> 2) & 3) as u8)
+    }
+    #[doc = "Bit 4 - reg_usb_vref_override"]
+    #[inline(always)]
+    pub fn usb_vref_override(&self) -> USB_VREF_OVERRIDE_R {
+        USB_VREF_OVERRIDE_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - reg_usb_pad_pull_override"]
+    #[inline(always)]
+    pub fn usb_pad_pull_override(&self) -> USB_PAD_PULL_OVERRIDE_R {
+        USB_PAD_PULL_OVERRIDE_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - reg_usb_dp_pullup"]
+    #[inline(always)]
+    pub fn usb_dp_pullup(&self) -> USB_DP_PULLUP_R {
+        USB_DP_PULLUP_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - reg_usb_dp_pulldown"]
+    #[inline(always)]
+    pub fn usb_dp_pulldown(&self) -> USB_DP_PULLDOWN_R {
+        USB_DP_PULLDOWN_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - reg_usb_dm_pullup"]
+    #[inline(always)]
+    pub fn usb_dm_pullup(&self) -> USB_DM_PULLUP_R {
+        USB_DM_PULLUP_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - reg_usb_dm_pulldown"]
+    #[inline(always)]
+    pub fn usb_dm_pulldown(&self) -> USB_DM_PULLDOWN_R {
+        USB_DM_PULLDOWN_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 10 - reg_usb_pullup_value"]
+    #[inline(always)]
+    pub fn usb_pullup_value(&self) -> USB_PULLUP_VALUE_R {
+        USB_PULLUP_VALUE_R::new(((self.bits >> 10) & 1) != 0)
+    }
+    #[doc = "Bit 11 - reg_usb_pad_enable_override"]
+    #[inline(always)]
+    pub fn usb_pad_enable_override(&self) -> USB_PAD_ENABLE_OVERRIDE_R {
+        USB_PAD_ENABLE_OVERRIDE_R::new(((self.bits >> 11) & 1) != 0)
+    }
+    #[doc = "Bit 12 - reg_usb_pad_enable"]
+    #[inline(always)]
+    pub fn usb_pad_enable(&self) -> USB_PAD_ENABLE_R {
+        USB_PAD_ENABLE_R::new(((self.bits >> 12) & 1) != 0)
+    }
+    #[doc = "Bit 13 - reg_usb_txm"]
+    #[inline(always)]
+    pub fn usb_txm(&self) -> USB_TXM_R {
+        USB_TXM_R::new(((self.bits >> 13) & 1) != 0)
+    }
+    #[doc = "Bit 14 - reg_usb_txp"]
+    #[inline(always)]
+    pub fn usb_txp(&self) -> USB_TXP_R {
+        USB_TXP_R::new(((self.bits >> 14) & 1) != 0)
+    }
+    #[doc = "Bit 15 - reg_usb_tx_en"]
+    #[inline(always)]
+    pub fn usb_tx_en(&self) -> USB_TX_EN_R {
+        USB_TX_EN_R::new(((self.bits >> 15) & 1) != 0)
+    }
+    #[doc = "Bit 16 - reg_usb_tx_en_override"]
+    #[inline(always)]
+    pub fn usb_tx_en_override(&self) -> USB_TX_EN_OVERRIDE_R {
+        USB_TX_EN_OVERRIDE_R::new(((self.bits >> 16) & 1) != 0)
+    }
+    #[doc = "Bit 17 - reg_usb_reset_disable"]
+    #[inline(always)]
+    pub fn usb_reset_disable(&self) -> USB_RESET_DISABLE_R {
+        USB_RESET_DISABLE_R::new(((self.bits >> 17) & 1) != 0)
+    }
+    #[doc = "Bit 18 - reg_io_mux_reset_disable"]
+    #[inline(always)]
+    pub fn io_mux_reset_disable(&self) -> IO_MUX_RESET_DISABLE_R {
+        IO_MUX_RESET_DISABLE_R::new(((self.bits >> 18) & 1) != 0)
+    }
+    #[doc = "Bit 19 - reg_sw_usb_phy_sel"]
+    #[inline(always)]
+    pub fn sw_usb_phy_sel(&self) -> SW_USB_PHY_SEL_R {
+        SW_USB_PHY_SEL_R::new(((self.bits >> 19) & 1) != 0)
+    }
+    #[doc = "Bit 20 - reg_sw_hw_usb_phy_sel"]
+    #[inline(always)]
+    pub fn sw_hw_usb_phy_sel(&self) -> SW_HW_USB_PHY_SEL_R {
+        SW_HW_USB_PHY_SEL_R::new(((self.bits >> 20) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("USB_CONF")
+            .field("usb_vrefh", &self.usb_vrefh())
+            .field("usb_vrefl", &self.usb_vrefl())
+            .field("usb_vref_override", &self.usb_vref_override())
+            .field("usb_pad_pull_override", &self.usb_pad_pull_override())
+            .field("usb_dp_pullup", &self.usb_dp_pullup())
+            .field("usb_dp_pulldown", &self.usb_dp_pulldown())
+            .field("usb_dm_pullup", &self.usb_dm_pullup())
+            .field("usb_dm_pulldown", &self.usb_dm_pulldown())
+            .field("usb_pullup_value", &self.usb_pullup_value())
+            .field("usb_pad_enable_override", &self.usb_pad_enable_override())
+            .field("usb_pad_enable", &self.usb_pad_enable())
+            .field("usb_txm", &self.usb_txm())
+            .field("usb_txp", &self.usb_txp())
+            .field("usb_tx_en", &self.usb_tx_en())
+            .field("usb_tx_en_override", &self.usb_tx_en_override())
+            .field("usb_reset_disable", &self.usb_reset_disable())
+            .field("io_mux_reset_disable", &self.io_mux_reset_disable())
+            .field("sw_usb_phy_sel", &self.sw_usb_phy_sel())
+            .field("sw_hw_usb_phy_sel", &self.sw_hw_usb_phy_sel())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:1 - reg_usb_vrefh"]
+    #[inline(always)]
+    pub fn usb_vrefh(&mut self) -> USB_VREFH_W<USB_CONF_SPEC> {
+        USB_VREFH_W::new(self, 0)
+    }
+    #[doc = "Bits 2:3 - reg_usb_vrefl"]
+    #[inline(always)]
+    pub fn usb_vrefl(&mut self) -> USB_VREFL_W<USB_CONF_SPEC> {
+        USB_VREFL_W::new(self, 2)
+    }
+    #[doc = "Bit 4 - reg_usb_vref_override"]
+    #[inline(always)]
+    pub fn usb_vref_override(&mut self) -> USB_VREF_OVERRIDE_W<USB_CONF_SPEC> {
+        USB_VREF_OVERRIDE_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - reg_usb_pad_pull_override"]
+    #[inline(always)]
+    pub fn usb_pad_pull_override(&mut self) -> USB_PAD_PULL_OVERRIDE_W<USB_CONF_SPEC> {
+        USB_PAD_PULL_OVERRIDE_W::new(self, 5)
+    }
+    #[doc = "Bit 6 - reg_usb_dp_pullup"]
+    #[inline(always)]
+    pub fn usb_dp_pullup(&mut self) -> USB_DP_PULLUP_W<USB_CONF_SPEC> {
+        USB_DP_PULLUP_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - reg_usb_dp_pulldown"]
+    #[inline(always)]
+    pub fn usb_dp_pulldown(&mut self) -> USB_DP_PULLDOWN_W<USB_CONF_SPEC> {
+        USB_DP_PULLDOWN_W::new(self, 7)
+    }
+    #[doc = "Bit 8 - reg_usb_dm_pullup"]
+    #[inline(always)]
+    pub fn usb_dm_pullup(&mut self) -> USB_DM_PULLUP_W<USB_CONF_SPEC> {
+        USB_DM_PULLUP_W::new(self, 8)
+    }
+    #[doc = "Bit 9 - reg_usb_dm_pulldown"]
+    #[inline(always)]
+    pub fn usb_dm_pulldown(&mut self) -> USB_DM_PULLDOWN_W<USB_CONF_SPEC> {
+        USB_DM_PULLDOWN_W::new(self, 9)
+    }
+    #[doc = "Bit 10 - reg_usb_pullup_value"]
+    #[inline(always)]
+    pub fn usb_pullup_value(&mut self) -> USB_PULLUP_VALUE_W<USB_CONF_SPEC> {
+        USB_PULLUP_VALUE_W::new(self, 10)
+    }
+    #[doc = "Bit 11 - reg_usb_pad_enable_override"]
+    #[inline(always)]
+    pub fn usb_pad_enable_override(&mut self) -> USB_PAD_ENABLE_OVERRIDE_W<USB_CONF_SPEC> {
+        USB_PAD_ENABLE_OVERRIDE_W::new(self, 11)
+    }
+    #[doc = "Bit 12 - reg_usb_pad_enable"]
+    #[inline(always)]
+    pub fn usb_pad_enable(&mut self) -> USB_PAD_ENABLE_W<USB_CONF_SPEC> {
+        USB_PAD_ENABLE_W::new(self, 12)
+    }
+    #[doc = "Bit 13 - reg_usb_txm"]
+    #[inline(always)]
+    pub fn usb_txm(&mut self) -> USB_TXM_W<USB_CONF_SPEC> {
+        USB_TXM_W::new(self, 13)
+    }
+    #[doc = "Bit 14 - reg_usb_txp"]
+    #[inline(always)]
+    pub fn usb_txp(&mut self) -> USB_TXP_W<USB_CONF_SPEC> {
+        USB_TXP_W::new(self, 14)
+    }
+    #[doc = "Bit 15 - reg_usb_tx_en"]
+    #[inline(always)]
+    pub fn usb_tx_en(&mut self) -> USB_TX_EN_W<USB_CONF_SPEC> {
+        USB_TX_EN_W::new(self, 15)
+    }
+    #[doc = "Bit 16 - reg_usb_tx_en_override"]
+    #[inline(always)]
+    pub fn usb_tx_en_override(&mut self) -> USB_TX_EN_OVERRIDE_W<USB_CONF_SPEC> {
+        USB_TX_EN_OVERRIDE_W::new(self, 16)
+    }
+    #[doc = "Bit 17 - reg_usb_reset_disable"]
+    #[inline(always)]
+    pub fn usb_reset_disable(&mut self) -> USB_RESET_DISABLE_W<USB_CONF_SPEC> {
+        USB_RESET_DISABLE_W::new(self, 17)
+    }
+    #[doc = "Bit 18 - reg_io_mux_reset_disable"]
+    #[inline(always)]
+    pub fn io_mux_reset_disable(&mut self) -> IO_MUX_RESET_DISABLE_W<USB_CONF_SPEC> {
+        IO_MUX_RESET_DISABLE_W::new(self, 18)
+    }
+    #[doc = "Bit 19 - reg_sw_usb_phy_sel"]
+    #[inline(always)]
+    pub fn sw_usb_phy_sel(&mut self) -> SW_USB_PHY_SEL_W<USB_CONF_SPEC> {
+        SW_USB_PHY_SEL_W::new(self, 19)
+    }
+    #[doc = "Bit 20 - reg_sw_hw_usb_phy_sel"]
+    #[inline(always)]
+    pub fn sw_hw_usb_phy_sel(&mut self) -> SW_HW_USB_PHY_SEL_W<USB_CONF_SPEC> {
+        SW_HW_USB_PHY_SEL_W::new(self, 20)
+    }
+}
+#[doc = "usb configure\n\nYou can [`read`](crate::Reg::read) this register and get [`usb_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usb_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct USB_CONF_SPEC;
+impl crate::RegisterSpec for USB_CONF_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`usb_conf::R`](R) reader structure"]
+impl crate::Readable for USB_CONF_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`usb_conf::W`](W) writer structure"]
+impl crate::Writable for USB_CONF_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets USB_CONF to value 0"]
+impl crate::Resettable for USB_CONF_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_cntl/wakeup_state.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `WAKEUP_STATE` reader"]
+pub type R = crate::R<WAKEUP_STATE_SPEC>;
+#[doc = "Register `WAKEUP_STATE` writer"]
+pub type W = crate::W<WAKEUP_STATE_SPEC>;
+#[doc = "Field `WAKEUP_ENA` reader - wakeup enable bitmap"]
+pub type WAKEUP_ENA_R = crate::FieldReader<u32>;
+#[doc = "Field `WAKEUP_ENA` writer - wakeup enable bitmap"]
+pub type WAKEUP_ENA_W<'a, REG> = crate::FieldWriter<'a, REG, 17, u32>;
+impl R {
+    #[doc = "Bits 15:31 - wakeup enable bitmap"]
+    #[inline(always)]
+    pub fn wakeup_ena(&self) -> WAKEUP_ENA_R {
+        WAKEUP_ENA_R::new((self.bits >> 15) & 0x0001_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("WAKEUP_STATE")
+            .field("wakeup_ena", &self.wakeup_ena())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 15:31 - wakeup enable bitmap"]
+    #[inline(always)]
+    pub fn wakeup_ena(&mut self) -> WAKEUP_ENA_W<WAKEUP_STATE_SPEC> {
+        WAKEUP_ENA_W::new(self, 15)
+    }
+}
+#[doc = "configure wakeup state\n\nYou can [`read`](crate::Reg::read) this register and get [`wakeup_state::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wakeup_state::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct WAKEUP_STATE_SPEC;
+impl crate::RegisterSpec for WAKEUP_STATE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`wakeup_state::R`](R) reader structure"]
+impl crate::Readable for WAKEUP_STATE_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`wakeup_state::W`](W) writer structure"]
+impl crate::Writable for WAKEUP_STATE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets WAKEUP_STATE to value 0x0006_0000"]
+impl crate::Resettable for WAKEUP_STATE_SPEC {
+    const RESET_VALUE: u32 = 0x0006_0000;
+}

vendor/esp32s3/src/rtc_cntl/wdtconfig0.rs

@@ -0,0 +1,227 @@
+#[doc = "Register `WDTCONFIG0` reader"]
+pub type R = crate::R<WDTCONFIG0_SPEC>;
+#[doc = "Register `WDTCONFIG0` writer"]
+pub type W = crate::W<WDTCONFIG0_SPEC>;
+#[doc = "Field `WDT_CHIP_RESET_WIDTH` reader - chip reset siginal pulse width"]
+pub type WDT_CHIP_RESET_WIDTH_R = crate::FieldReader;
+#[doc = "Field `WDT_CHIP_RESET_WIDTH` writer - chip reset siginal pulse width"]
+pub type WDT_CHIP_RESET_WIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+#[doc = "Field `WDT_CHIP_RESET_EN` reader - wdt reset whole chip enable"]
+pub type WDT_CHIP_RESET_EN_R = crate::BitReader;
+#[doc = "Field `WDT_CHIP_RESET_EN` writer - wdt reset whole chip enable"]
+pub type WDT_CHIP_RESET_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `WDT_PAUSE_IN_SLP` reader - pause WDT in sleep"]
+pub type WDT_PAUSE_IN_SLP_R = crate::BitReader;
+#[doc = "Field `WDT_PAUSE_IN_SLP` writer - pause WDT in sleep"]
+pub type WDT_PAUSE_IN_SLP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `WDT_APPCPU_RESET_EN` reader - enable WDT reset APP CPU"]
+pub type WDT_APPCPU_RESET_EN_R = crate::BitReader;
+#[doc = "Field `WDT_APPCPU_RESET_EN` writer - enable WDT reset APP CPU"]
+pub type WDT_APPCPU_RESET_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `WDT_PROCPU_RESET_EN` reader - enable WDT reset PRO CPU"]
+pub type WDT_PROCPU_RESET_EN_R = crate::BitReader;
+#[doc = "Field `WDT_PROCPU_RESET_EN` writer - enable WDT reset PRO CPU"]
+pub type WDT_PROCPU_RESET_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `WDT_FLASHBOOT_MOD_EN` reader - enable WDT in flash boot"]
+pub type WDT_FLASHBOOT_MOD_EN_R = crate::BitReader;
+#[doc = "Field `WDT_FLASHBOOT_MOD_EN` writer - enable WDT in flash boot"]
+pub type WDT_FLASHBOOT_MOD_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `WDT_SYS_RESET_LENGTH` reader - system reset counter length"]
+pub type WDT_SYS_RESET_LENGTH_R = crate::FieldReader;
+#[doc = "Field `WDT_SYS_RESET_LENGTH` writer - system reset counter length"]
+pub type WDT_SYS_RESET_LENGTH_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `WDT_CPU_RESET_LENGTH` reader - CPU reset counter length"]
+pub type WDT_CPU_RESET_LENGTH_R = crate::FieldReader;
+#[doc = "Field `WDT_CPU_RESET_LENGTH` writer - CPU reset counter length"]
+pub type WDT_CPU_RESET_LENGTH_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `WDT_STG3` reader - 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en"]
+pub type WDT_STG3_R = crate::FieldReader;
+#[doc = "Field `WDT_STG3` writer - 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en"]
+pub type WDT_STG3_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `WDT_STG2` reader - 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en"]
+pub type WDT_STG2_R = crate::FieldReader;
+#[doc = "Field `WDT_STG2` writer - 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en"]
+pub type WDT_STG2_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `WDT_STG1` reader - 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en"]
+pub type WDT_STG1_R = crate::FieldReader;
+#[doc = "Field `WDT_STG1` writer - 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en"]
+pub type WDT_STG1_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `WDT_STG0` reader - 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en"]
+pub type WDT_STG0_R = crate::FieldReader;
+#[doc = "Field `WDT_STG0` writer - 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en"]
+pub type WDT_STG0_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `WDT_EN` reader - enable rtc watch dog"]
+pub type WDT_EN_R = crate::BitReader;
+#[doc = "Field `WDT_EN` writer - enable rtc watch dog"]
+pub type WDT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 0:7 - chip reset siginal pulse width"]
+    #[inline(always)]
+    pub fn wdt_chip_reset_width(&self) -> WDT_CHIP_RESET_WIDTH_R {
+        WDT_CHIP_RESET_WIDTH_R::new((self.bits & 0xff) as u8)
+    }
+    #[doc = "Bit 8 - wdt reset whole chip enable"]
+    #[inline(always)]
+    pub fn wdt_chip_reset_en(&self) -> WDT_CHIP_RESET_EN_R {
+        WDT_CHIP_RESET_EN_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - pause WDT in sleep"]
+    #[inline(always)]
+    pub fn wdt_pause_in_slp(&self) -> WDT_PAUSE_IN_SLP_R {
+        WDT_PAUSE_IN_SLP_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 10 - enable WDT reset APP CPU"]
+    #[inline(always)]
+    pub fn wdt_appcpu_reset_en(&self) -> WDT_APPCPU_RESET_EN_R {
+        WDT_APPCPU_RESET_EN_R::new(((self.bits >> 10) & 1) != 0)
+    }
+    #[doc = "Bit 11 - enable WDT reset PRO CPU"]
+    #[inline(always)]
+    pub fn wdt_procpu_reset_en(&self) -> WDT_PROCPU_RESET_EN_R {
+        WDT_PROCPU_RESET_EN_R::new(((self.bits >> 11) & 1) != 0)
+    }
+    #[doc = "Bit 12 - enable WDT in flash boot"]
+    #[inline(always)]
+    pub fn wdt_flashboot_mod_en(&self) -> WDT_FLASHBOOT_MOD_EN_R {
+        WDT_FLASHBOOT_MOD_EN_R::new(((self.bits >> 12) & 1) != 0)
+    }
+    #[doc = "Bits 13:15 - system reset counter length"]
+    #[inline(always)]
+    pub fn wdt_sys_reset_length(&self) -> WDT_SYS_RESET_LENGTH_R {
+        WDT_SYS_RESET_LENGTH_R::new(((self.bits >> 13) & 7) as u8)
+    }
+    #[doc = "Bits 16:18 - CPU reset counter length"]
+    #[inline(always)]
+    pub fn wdt_cpu_reset_length(&self) -> WDT_CPU_RESET_LENGTH_R {
+        WDT_CPU_RESET_LENGTH_R::new(((self.bits >> 16) & 7) as u8)
+    }
+    #[doc = "Bits 19:21 - 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en"]
+    #[inline(always)]
+    pub fn wdt_stg3(&self) -> WDT_STG3_R {
+        WDT_STG3_R::new(((self.bits >> 19) & 7) as u8)
+    }
+    #[doc = "Bits 22:24 - 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en"]
+    #[inline(always)]
+    pub fn wdt_stg2(&self) -> WDT_STG2_R {
+        WDT_STG2_R::new(((self.bits >> 22) & 7) as u8)
+    }
+    #[doc = "Bits 25:27 - 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en"]
+    #[inline(always)]
+    pub fn wdt_stg1(&self) -> WDT_STG1_R {
+        WDT_STG1_R::new(((self.bits >> 25) & 7) as u8)
+    }
+    #[doc = "Bits 28:30 - 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en"]
+    #[inline(always)]
+    pub fn wdt_stg0(&self) -> WDT_STG0_R {
+        WDT_STG0_R::new(((self.bits >> 28) & 7) as u8)
+    }
+    #[doc = "Bit 31 - enable rtc watch dog"]
+    #[inline(always)]
+    pub fn wdt_en(&self) -> WDT_EN_R {
+        WDT_EN_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("WDTCONFIG0")
+            .field("wdt_chip_reset_width", &self.wdt_chip_reset_width())
+            .field("wdt_chip_reset_en", &self.wdt_chip_reset_en())
+            .field("wdt_pause_in_slp", &self.wdt_pause_in_slp())
+            .field("wdt_appcpu_reset_en", &self.wdt_appcpu_reset_en())
+            .field("wdt_procpu_reset_en", &self.wdt_procpu_reset_en())
+            .field("wdt_flashboot_mod_en", &self.wdt_flashboot_mod_en())
+            .field("wdt_sys_reset_length", &self.wdt_sys_reset_length())
+            .field("wdt_cpu_reset_length", &self.wdt_cpu_reset_length())
+            .field("wdt_stg3", &self.wdt_stg3())
+            .field("wdt_stg2", &self.wdt_stg2())
+            .field("wdt_stg1", &self.wdt_stg1())
+            .field("wdt_stg0", &self.wdt_stg0())
+            .field("wdt_en", &self.wdt_en())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - chip reset siginal pulse width"]
+    #[inline(always)]
+    pub fn wdt_chip_reset_width(&mut self) -> WDT_CHIP_RESET_WIDTH_W<WDTCONFIG0_SPEC> {
+        WDT_CHIP_RESET_WIDTH_W::new(self, 0)
+    }
+    #[doc = "Bit 8 - wdt reset whole chip enable"]
+    #[inline(always)]
+    pub fn wdt_chip_reset_en(&mut self) -> WDT_CHIP_RESET_EN_W<WDTCONFIG0_SPEC> {
+        WDT_CHIP_RESET_EN_W::new(self, 8)
+    }
+    #[doc = "Bit 9 - pause WDT in sleep"]
+    #[inline(always)]
+    pub fn wdt_pause_in_slp(&mut self) -> WDT_PAUSE_IN_SLP_W<WDTCONFIG0_SPEC> {
+        WDT_PAUSE_IN_SLP_W::new(self, 9)
+    }
+    #[doc = "Bit 10 - enable WDT reset APP CPU"]
+    #[inline(always)]
+    pub fn wdt_appcpu_reset_en(&mut self) -> WDT_APPCPU_RESET_EN_W<WDTCONFIG0_SPEC> {
+        WDT_APPCPU_RESET_EN_W::new(self, 10)
+    }
+    #[doc = "Bit 11 - enable WDT reset PRO CPU"]
+    #[inline(always)]
+    pub fn wdt_procpu_reset_en(&mut self) -> WDT_PROCPU_RESET_EN_W<WDTCONFIG0_SPEC> {
+        WDT_PROCPU_RESET_EN_W::new(self, 11)
+    }
+    #[doc = "Bit 12 - enable WDT in flash boot"]
+    #[inline(always)]
+    pub fn wdt_flashboot_mod_en(&mut self) -> WDT_FLASHBOOT_MOD_EN_W<WDTCONFIG0_SPEC> {
+        WDT_FLASHBOOT_MOD_EN_W::new(self, 12)
+    }
+    #[doc = "Bits 13:15 - system reset counter length"]
+    #[inline(always)]
+    pub fn wdt_sys_reset_length(&mut self) -> WDT_SYS_RESET_LENGTH_W<WDTCONFIG0_SPEC> {
+        WDT_SYS_RESET_LENGTH_W::new(self, 13)
+    }
+    #[doc = "Bits 16:18 - CPU reset counter length"]
+    #[inline(always)]
+    pub fn wdt_cpu_reset_length(&mut self) -> WDT_CPU_RESET_LENGTH_W<WDTCONFIG0_SPEC> {
+        WDT_CPU_RESET_LENGTH_W::new(self, 16)
+    }
+    #[doc = "Bits 19:21 - 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en"]
+    #[inline(always)]
+    pub fn wdt_stg3(&mut self) -> WDT_STG3_W<WDTCONFIG0_SPEC> {
+        WDT_STG3_W::new(self, 19)
+    }
+    #[doc = "Bits 22:24 - 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en"]
+    #[inline(always)]
+    pub fn wdt_stg2(&mut self) -> WDT_STG2_W<WDTCONFIG0_SPEC> {
+        WDT_STG2_W::new(self, 22)
+    }
+    #[doc = "Bits 25:27 - 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en"]
+    #[inline(always)]
+    pub fn wdt_stg1(&mut self) -> WDT_STG1_W<WDTCONFIG0_SPEC> {
+        WDT_STG1_W::new(self, 25)
+    }
+    #[doc = "Bits 28:30 - 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en"]
+    #[inline(always)]
+    pub fn wdt_stg0(&mut self) -> WDT_STG0_W<WDTCONFIG0_SPEC> {
+        WDT_STG0_W::new(self, 28)
+    }
+    #[doc = "Bit 31 - enable rtc watch dog"]
+    #[inline(always)]
+    pub fn wdt_en(&mut self) -> WDT_EN_W<WDTCONFIG0_SPEC> {
+        WDT_EN_W::new(self, 31)
+    }
+}
+#[doc = "configure rtc watch dog\n\nYou can [`read`](crate::Reg::read) this register and get [`wdtconfig0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdtconfig0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct WDTCONFIG0_SPEC;
+impl crate::RegisterSpec for WDTCONFIG0_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`wdtconfig0::R`](R) reader structure"]
+impl crate::Readable for WDTCONFIG0_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`wdtconfig0::W`](W) writer structure"]
+impl crate::Writable for WDTCONFIG0_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets WDTCONFIG0 to value 0x0001_3214"]
+impl crate::Resettable for WDTCONFIG0_SPEC {
+    const RESET_VALUE: u32 = 0x0001_3214;
+}

vendor/esp32s3/src/rtc_cntl/wdtconfig1.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `WDTCONFIG1` reader"]
+pub type R = crate::R<WDTCONFIG1_SPEC>;
+#[doc = "Register `WDTCONFIG1` writer"]
+pub type W = crate::W<WDTCONFIG1_SPEC>;
+#[doc = "Field `WDT_STG0_HOLD` reader - stage0 hold time"]
+pub type WDT_STG0_HOLD_R = crate::FieldReader<u32>;
+#[doc = "Field `WDT_STG0_HOLD` writer - stage0 hold time"]
+pub type WDT_STG0_HOLD_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - stage0 hold time"]
+    #[inline(always)]
+    pub fn wdt_stg0_hold(&self) -> WDT_STG0_HOLD_R {
+        WDT_STG0_HOLD_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("WDTCONFIG1")
+            .field("wdt_stg0_hold", &self.wdt_stg0_hold())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - stage0 hold time"]
+    #[inline(always)]
+    pub fn wdt_stg0_hold(&mut self) -> WDT_STG0_HOLD_W<WDTCONFIG1_SPEC> {
+        WDT_STG0_HOLD_W::new(self, 0)
+    }
+}
+#[doc = "stage0 hold time\n\nYou can [`read`](crate::Reg::read) this register and get [`wdtconfig1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdtconfig1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct WDTCONFIG1_SPEC;
+impl crate::RegisterSpec for WDTCONFIG1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`wdtconfig1::R`](R) reader structure"]
+impl crate::Readable for WDTCONFIG1_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`wdtconfig1::W`](W) writer structure"]
+impl crate::Writable for WDTCONFIG1_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets WDTCONFIG1 to value 0x0003_0d40"]
+impl crate::Resettable for WDTCONFIG1_SPEC {
+    const RESET_VALUE: u32 = 0x0003_0d40;
+}

vendor/esp32s3/src/rtc_cntl/wdtconfig2.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `WDTCONFIG2` reader"]
+pub type R = crate::R<WDTCONFIG2_SPEC>;
+#[doc = "Register `WDTCONFIG2` writer"]
+pub type W = crate::W<WDTCONFIG2_SPEC>;
+#[doc = "Field `WDT_STG1_HOLD` reader - stage1 hold time"]
+pub type WDT_STG1_HOLD_R = crate::FieldReader<u32>;
+#[doc = "Field `WDT_STG1_HOLD` writer - stage1 hold time"]
+pub type WDT_STG1_HOLD_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - stage1 hold time"]
+    #[inline(always)]
+    pub fn wdt_stg1_hold(&self) -> WDT_STG1_HOLD_R {
+        WDT_STG1_HOLD_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("WDTCONFIG2")
+            .field("wdt_stg1_hold", &self.wdt_stg1_hold())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - stage1 hold time"]
+    #[inline(always)]
+    pub fn wdt_stg1_hold(&mut self) -> WDT_STG1_HOLD_W<WDTCONFIG2_SPEC> {
+        WDT_STG1_HOLD_W::new(self, 0)
+    }
+}
+#[doc = "stage1 hold time\n\nYou can [`read`](crate::Reg::read) this register and get [`wdtconfig2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdtconfig2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct WDTCONFIG2_SPEC;
+impl crate::RegisterSpec for WDTCONFIG2_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`wdtconfig2::R`](R) reader structure"]
+impl crate::Readable for WDTCONFIG2_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`wdtconfig2::W`](W) writer structure"]
+impl crate::Writable for WDTCONFIG2_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets WDTCONFIG2 to value 0x0001_3880"]
+impl crate::Resettable for WDTCONFIG2_SPEC {
+    const RESET_VALUE: u32 = 0x0001_3880;
+}

vendor/esp32s3/src/rtc_cntl/wdtconfig3.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `WDTCONFIG3` reader"]
+pub type R = crate::R<WDTCONFIG3_SPEC>;
+#[doc = "Register `WDTCONFIG3` writer"]
+pub type W = crate::W<WDTCONFIG3_SPEC>;
+#[doc = "Field `WDT_STG2_HOLD` reader - stage2 hold time"]
+pub type WDT_STG2_HOLD_R = crate::FieldReader<u32>;
+#[doc = "Field `WDT_STG2_HOLD` writer - stage2 hold time"]
+pub type WDT_STG2_HOLD_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - stage2 hold time"]
+    #[inline(always)]
+    pub fn wdt_stg2_hold(&self) -> WDT_STG2_HOLD_R {
+        WDT_STG2_HOLD_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("WDTCONFIG3")
+            .field("wdt_stg2_hold", &self.wdt_stg2_hold())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - stage2 hold time"]
+    #[inline(always)]
+    pub fn wdt_stg2_hold(&mut self) -> WDT_STG2_HOLD_W<WDTCONFIG3_SPEC> {
+        WDT_STG2_HOLD_W::new(self, 0)
+    }
+}
+#[doc = "stage2 hold time\n\nYou can [`read`](crate::Reg::read) this register and get [`wdtconfig3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdtconfig3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct WDTCONFIG3_SPEC;
+impl crate::RegisterSpec for WDTCONFIG3_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`wdtconfig3::R`](R) reader structure"]
+impl crate::Readable for WDTCONFIG3_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`wdtconfig3::W`](W) writer structure"]
+impl crate::Writable for WDTCONFIG3_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets WDTCONFIG3 to value 0x0fff"]
+impl crate::Resettable for WDTCONFIG3_SPEC {
+    const RESET_VALUE: u32 = 0x0fff;
+}

vendor/esp32s3/src/rtc_cntl/wdtconfig4.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `WDTCONFIG4` reader"]
+pub type R = crate::R<WDTCONFIG4_SPEC>;
+#[doc = "Register `WDTCONFIG4` writer"]
+pub type W = crate::W<WDTCONFIG4_SPEC>;
+#[doc = "Field `WDT_STG3_HOLD` reader - stage3 hold time"]
+pub type WDT_STG3_HOLD_R = crate::FieldReader<u32>;
+#[doc = "Field `WDT_STG3_HOLD` writer - stage3 hold time"]
+pub type WDT_STG3_HOLD_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - stage3 hold time"]
+    #[inline(always)]
+    pub fn wdt_stg3_hold(&self) -> WDT_STG3_HOLD_R {
+        WDT_STG3_HOLD_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("WDTCONFIG4")
+            .field("wdt_stg3_hold", &self.wdt_stg3_hold())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - stage3 hold time"]
+    #[inline(always)]
+    pub fn wdt_stg3_hold(&mut self) -> WDT_STG3_HOLD_W<WDTCONFIG4_SPEC> {
+        WDT_STG3_HOLD_W::new(self, 0)
+    }
+}
+#[doc = "stage3 hold time\n\nYou can [`read`](crate::Reg::read) this register and get [`wdtconfig4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdtconfig4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct WDTCONFIG4_SPEC;
+impl crate::RegisterSpec for WDTCONFIG4_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`wdtconfig4::R`](R) reader structure"]
+impl crate::Readable for WDTCONFIG4_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`wdtconfig4::W`](W) writer structure"]
+impl crate::Writable for WDTCONFIG4_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets WDTCONFIG4 to value 0x0fff"]
+impl crate::Resettable for WDTCONFIG4_SPEC {
+    const RESET_VALUE: u32 = 0x0fff;
+}

vendor/esp32s3/src/rtc_cntl/wdtfeed.rs

@@ -0,0 +1,32 @@
+#[doc = "Register `WDTFEED` writer"]
+pub type W = crate::W<WDTFEED_SPEC>;
+#[doc = "Field `WDT_FEED` writer - rtc wdt feed"]
+pub type WDT_FEED_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for crate::generic::Reg<WDTFEED_SPEC> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "(not readable)")
+    }
+}
+impl W {
+    #[doc = "Bit 31 - rtc wdt feed"]
+    #[inline(always)]
+    pub fn wdt_feed(&mut self) -> WDT_FEED_W<WDTFEED_SPEC> {
+        WDT_FEED_W::new(self, 31)
+    }
+}
+#[doc = "rtc wdt feed\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdtfeed::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct WDTFEED_SPEC;
+impl crate::RegisterSpec for WDTFEED_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [`wdtfeed::W`](W) writer structure"]
+impl crate::Writable for WDTFEED_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets WDTFEED to value 0"]
+impl crate::Resettable for WDTFEED_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_cntl/wdtwprotect.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `WDTWPROTECT` reader"]
+pub type R = crate::R<WDTWPROTECT_SPEC>;
+#[doc = "Register `WDTWPROTECT` writer"]
+pub type W = crate::W<WDTWPROTECT_SPEC>;
+#[doc = "Field `WDT_WKEY` reader - rtc watch dog key"]
+pub type WDT_WKEY_R = crate::FieldReader<u32>;
+#[doc = "Field `WDT_WKEY` writer - rtc watch dog key"]
+pub type WDT_WKEY_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - rtc watch dog key"]
+    #[inline(always)]
+    pub fn wdt_wkey(&self) -> WDT_WKEY_R {
+        WDT_WKEY_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("WDTWPROTECT")
+            .field("wdt_wkey", &self.wdt_wkey())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - rtc watch dog key"]
+    #[inline(always)]
+    pub fn wdt_wkey(&mut self) -> WDT_WKEY_W<WDTWPROTECT_SPEC> {
+        WDT_WKEY_W::new(self, 0)
+    }
+}
+#[doc = "configure rtc watch dog\n\nYou can [`read`](crate::Reg::read) this register and get [`wdtwprotect::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdtwprotect::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct WDTWPROTECT_SPEC;
+impl crate::RegisterSpec for WDTWPROTECT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`wdtwprotect::R`](R) reader structure"]
+impl crate::Readable for WDTWPROTECT_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`wdtwprotect::W`](W) writer structure"]
+impl crate::Writable for WDTWPROTECT_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets WDTWPROTECT to value 0x50d8_3aa1"]
+impl crate::Resettable for WDTWPROTECT_SPEC {
+    const RESET_VALUE: u32 = 0x50d8_3aa1;
+}

vendor/esp32s3/src/rtc_cntl/xtal32k_clk_factor.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `XTAL32K_CLK_FACTOR` reader"]
+pub type R = crate::R<XTAL32K_CLK_FACTOR_SPEC>;
+#[doc = "Register `XTAL32K_CLK_FACTOR` writer"]
+pub type W = crate::W<XTAL32K_CLK_FACTOR_SPEC>;
+#[doc = "Field `XTAL32K_CLK_FACTOR` reader - xtal 32k watch dog backup clock factor"]
+pub type XTAL32K_CLK_FACTOR_R = crate::FieldReader<u32>;
+#[doc = "Field `XTAL32K_CLK_FACTOR` writer - xtal 32k watch dog backup clock factor"]
+pub type XTAL32K_CLK_FACTOR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - xtal 32k watch dog backup clock factor"]
+    #[inline(always)]
+    pub fn xtal32k_clk_factor(&self) -> XTAL32K_CLK_FACTOR_R {
+        XTAL32K_CLK_FACTOR_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("XTAL32K_CLK_FACTOR")
+            .field("xtal32k_clk_factor", &self.xtal32k_clk_factor())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - xtal 32k watch dog backup clock factor"]
+    #[inline(always)]
+    pub fn xtal32k_clk_factor(&mut self) -> XTAL32K_CLK_FACTOR_W<XTAL32K_CLK_FACTOR_SPEC> {
+        XTAL32K_CLK_FACTOR_W::new(self, 0)
+    }
+}
+#[doc = "xtal 32k watch dog backup clock factor\n\nYou can [`read`](crate::Reg::read) this register and get [`xtal32k_clk_factor::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`xtal32k_clk_factor::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct XTAL32K_CLK_FACTOR_SPEC;
+impl crate::RegisterSpec for XTAL32K_CLK_FACTOR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`xtal32k_clk_factor::R`](R) reader structure"]
+impl crate::Readable for XTAL32K_CLK_FACTOR_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`xtal32k_clk_factor::W`](W) writer structure"]
+impl crate::Writable for XTAL32K_CLK_FACTOR_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets XTAL32K_CLK_FACTOR to value 0"]
+impl crate::Resettable for XTAL32K_CLK_FACTOR_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_cntl/xtal32k_conf.rs

@@ -0,0 +1,92 @@
+#[doc = "Register `XTAL32K_CONF` reader"]
+pub type R = crate::R<XTAL32K_CONF_SPEC>;
+#[doc = "Register `XTAL32K_CONF` writer"]
+pub type W = crate::W<XTAL32K_CONF_SPEC>;
+#[doc = "Field `XTAL32K_RETURN_WAIT` reader - cycles to wait to return noral xtal 32k"]
+pub type XTAL32K_RETURN_WAIT_R = crate::FieldReader;
+#[doc = "Field `XTAL32K_RETURN_WAIT` writer - cycles to wait to return noral xtal 32k"]
+pub type XTAL32K_RETURN_WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `XTAL32K_RESTART_WAIT` reader - cycles to wait to repower on xtal 32k"]
+pub type XTAL32K_RESTART_WAIT_R = crate::FieldReader<u16>;
+#[doc = "Field `XTAL32K_RESTART_WAIT` writer - cycles to wait to repower on xtal 32k"]
+pub type XTAL32K_RESTART_WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
+#[doc = "Field `XTAL32K_WDT_TIMEOUT` reader - If no clock detected for this amount of time 32k is regarded as dead"]
+pub type XTAL32K_WDT_TIMEOUT_R = crate::FieldReader;
+#[doc = "Field `XTAL32K_WDT_TIMEOUT` writer - If no clock detected for this amount of time 32k is regarded as dead"]
+pub type XTAL32K_WDT_TIMEOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+#[doc = "Field `XTAL32K_STABLE_THRES` reader - if restarted xtal32k period is smaller than this, it is regarded as stable"]
+pub type XTAL32K_STABLE_THRES_R = crate::FieldReader;
+#[doc = "Field `XTAL32K_STABLE_THRES` writer - if restarted xtal32k period is smaller than this, it is regarded as stable"]
+pub type XTAL32K_STABLE_THRES_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+impl R {
+    #[doc = "Bits 0:3 - cycles to wait to return noral xtal 32k"]
+    #[inline(always)]
+    pub fn xtal32k_return_wait(&self) -> XTAL32K_RETURN_WAIT_R {
+        XTAL32K_RETURN_WAIT_R::new((self.bits & 0x0f) as u8)
+    }
+    #[doc = "Bits 4:19 - cycles to wait to repower on xtal 32k"]
+    #[inline(always)]
+    pub fn xtal32k_restart_wait(&self) -> XTAL32K_RESTART_WAIT_R {
+        XTAL32K_RESTART_WAIT_R::new(((self.bits >> 4) & 0xffff) as u16)
+    }
+    #[doc = "Bits 20:27 - If no clock detected for this amount of time 32k is regarded as dead"]
+    #[inline(always)]
+    pub fn xtal32k_wdt_timeout(&self) -> XTAL32K_WDT_TIMEOUT_R {
+        XTAL32K_WDT_TIMEOUT_R::new(((self.bits >> 20) & 0xff) as u8)
+    }
+    #[doc = "Bits 28:31 - if restarted xtal32k period is smaller than this, it is regarded as stable"]
+    #[inline(always)]
+    pub fn xtal32k_stable_thres(&self) -> XTAL32K_STABLE_THRES_R {
+        XTAL32K_STABLE_THRES_R::new(((self.bits >> 28) & 0x0f) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("XTAL32K_CONF")
+            .field("xtal32k_return_wait", &self.xtal32k_return_wait())
+            .field("xtal32k_restart_wait", &self.xtal32k_restart_wait())
+            .field("xtal32k_wdt_timeout", &self.xtal32k_wdt_timeout())
+            .field("xtal32k_stable_thres", &self.xtal32k_stable_thres())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:3 - cycles to wait to return noral xtal 32k"]
+    #[inline(always)]
+    pub fn xtal32k_return_wait(&mut self) -> XTAL32K_RETURN_WAIT_W<XTAL32K_CONF_SPEC> {
+        XTAL32K_RETURN_WAIT_W::new(self, 0)
+    }
+    #[doc = "Bits 4:19 - cycles to wait to repower on xtal 32k"]
+    #[inline(always)]
+    pub fn xtal32k_restart_wait(&mut self) -> XTAL32K_RESTART_WAIT_W<XTAL32K_CONF_SPEC> {
+        XTAL32K_RESTART_WAIT_W::new(self, 4)
+    }
+    #[doc = "Bits 20:27 - If no clock detected for this amount of time 32k is regarded as dead"]
+    #[inline(always)]
+    pub fn xtal32k_wdt_timeout(&mut self) -> XTAL32K_WDT_TIMEOUT_W<XTAL32K_CONF_SPEC> {
+        XTAL32K_WDT_TIMEOUT_W::new(self, 20)
+    }
+    #[doc = "Bits 28:31 - if restarted xtal32k period is smaller than this, it is regarded as stable"]
+    #[inline(always)]
+    pub fn xtal32k_stable_thres(&mut self) -> XTAL32K_STABLE_THRES_W<XTAL32K_CONF_SPEC> {
+        XTAL32K_STABLE_THRES_W::new(self, 28)
+    }
+}
+#[doc = "configure xtal32k\n\nYou can [`read`](crate::Reg::read) this register and get [`xtal32k_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`xtal32k_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct XTAL32K_CONF_SPEC;
+impl crate::RegisterSpec for XTAL32K_CONF_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`xtal32k_conf::R`](R) reader structure"]
+impl crate::Readable for XTAL32K_CONF_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`xtal32k_conf::W`](W) writer structure"]
+impl crate::Writable for XTAL32K_CONF_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets XTAL32K_CONF to value 0x0ff0_0000"]
+impl crate::Resettable for XTAL32K_CONF_SPEC {
+    const RESET_VALUE: u32 = 0x0ff0_0000;
+}