feat: add display UI with splash screen, dashboard, and RSSI sparkline
Implement full SSD1306 OLED display support: - Splash screen on boot (1.5s) with project name, version, board - Dashboard showing radio state, config, counters, RSSI/SNR - RSSI history sparkline (64-sample ring buffer, 2px-wide bars) - DisplayOn/DisplayOff host commands routed via dedicated channel - Pure render functions against generic DrawTarget (no hardware coupling) - Display on/off control bypasses radio task entirely Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
This commit is contained in:
17624 files changed
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Vendored
+55
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#[doc = "Register `CMD%s` reader"]
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pub type R = crate::R<CMD_SPEC>;
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#[doc = "Register `CMD%s` writer"]
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pub type W = crate::W<CMD_SPEC>;
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#[doc = "Field `COMMAND` reader - command0"]
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pub type COMMAND_R = crate::FieldReader<u16>;
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#[doc = "Field `COMMAND` writer - command0"]
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pub type COMMAND_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>;
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#[doc = "Field `COMMAND_DONE` reader - command0_done"]
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pub type COMMAND_DONE_R = crate::BitReader;
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impl R {
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#[doc = "Bits 0:13 - command0"]
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#[inline(always)]
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pub fn command(&self) -> COMMAND_R {
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COMMAND_R::new((self.bits & 0x3fff) as u16)
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}
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#[doc = "Bit 31 - command0_done"]
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#[inline(always)]
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pub fn command_done(&self) -> COMMAND_DONE_R {
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COMMAND_DONE_R::new(((self.bits >> 31) & 1) != 0)
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}
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}
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#[cfg(feature = "impl-register-debug")]
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impl core::fmt::Debug for R {
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fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
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f.debug_struct("CMD")
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.field("command", &self.command())
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.field("command_done", &self.command_done())
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.finish()
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}
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}
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impl W {
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#[doc = "Bits 0:13 - command0"]
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#[inline(always)]
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pub fn command(&mut self) -> COMMAND_W<CMD_SPEC> {
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COMMAND_W::new(self, 0)
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}
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}
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#[doc = "I2C command%s register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
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pub struct CMD_SPEC;
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impl crate::RegisterSpec for CMD_SPEC {
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type Ux = u32;
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}
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#[doc = "`read()` method returns [`cmd::R`](R) reader structure"]
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impl crate::Readable for CMD_SPEC {}
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#[doc = "`write(|w| ..)` method takes [`cmd::W`](W) writer structure"]
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impl crate::Writable for CMD_SPEC {
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type Safety = crate::Unsafe;
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const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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}
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#[doc = "`reset()` method sets CMD%s to value 0x0903"]
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impl crate::Resettable for CMD_SPEC {
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const RESET_VALUE: u32 = 0x0903;
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}
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Vendored
+167
@@ -0,0 +1,167 @@
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#[doc = "Register `CTRL` reader"]
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pub type R = crate::R<CTRL_SPEC>;
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#[doc = "Register `CTRL` writer"]
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pub type W = crate::W<CTRL_SPEC>;
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#[doc = "Field `SDA_FORCE_OUT` reader - 1=push pull,0=open drain"]
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pub type SDA_FORCE_OUT_R = crate::BitReader;
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#[doc = "Field `SDA_FORCE_OUT` writer - 1=push pull,0=open drain"]
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pub type SDA_FORCE_OUT_W<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `SCL_FORCE_OUT` reader - 1=push pull,0=open drain"]
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pub type SCL_FORCE_OUT_R = crate::BitReader;
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#[doc = "Field `SCL_FORCE_OUT` writer - 1=push pull,0=open drain"]
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pub type SCL_FORCE_OUT_W<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `MS_MODE` reader - 1=master,0=slave"]
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pub type MS_MODE_R = crate::BitReader;
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#[doc = "Field `MS_MODE` writer - 1=master,0=slave"]
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pub type MS_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `TRANS_START` reader - force start"]
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pub type TRANS_START_R = crate::BitReader;
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#[doc = "Field `TRANS_START` writer - force start"]
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pub type TRANS_START_W<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `TX_LSB_FIRST` reader - transit lsb first"]
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pub type TX_LSB_FIRST_R = crate::BitReader;
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#[doc = "Field `TX_LSB_FIRST` writer - transit lsb first"]
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pub type TX_LSB_FIRST_W<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `RX_LSB_FIRST` reader - receive lsb first"]
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pub type RX_LSB_FIRST_R = crate::BitReader;
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#[doc = "Field `RX_LSB_FIRST` writer - receive lsb first"]
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pub type RX_LSB_FIRST_W<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `I2C_CTRL_CLK_GATE_EN` reader - configure i2c ctrl clk enable"]
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pub type I2C_CTRL_CLK_GATE_EN_R = crate::BitReader;
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#[doc = "Field `I2C_CTRL_CLK_GATE_EN` writer - configure i2c ctrl clk enable"]
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pub type I2C_CTRL_CLK_GATE_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `I2C_RESET` reader - rtc i2c sw reset"]
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pub type I2C_RESET_R = crate::BitReader;
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#[doc = "Field `I2C_RESET` writer - rtc i2c sw reset"]
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pub type I2C_RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `I2CCLK_EN` reader - rtc i2c reg clk gating"]
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pub type I2CCLK_EN_R = crate::BitReader;
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#[doc = "Field `I2CCLK_EN` writer - rtc i2c reg clk gating"]
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pub type I2CCLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
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impl R {
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#[doc = "Bit 0 - 1=push pull,0=open drain"]
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#[inline(always)]
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pub fn sda_force_out(&self) -> SDA_FORCE_OUT_R {
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SDA_FORCE_OUT_R::new((self.bits & 1) != 0)
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}
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#[doc = "Bit 1 - 1=push pull,0=open drain"]
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#[inline(always)]
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pub fn scl_force_out(&self) -> SCL_FORCE_OUT_R {
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SCL_FORCE_OUT_R::new(((self.bits >> 1) & 1) != 0)
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}
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#[doc = "Bit 2 - 1=master,0=slave"]
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#[inline(always)]
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pub fn ms_mode(&self) -> MS_MODE_R {
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MS_MODE_R::new(((self.bits >> 2) & 1) != 0)
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}
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#[doc = "Bit 3 - force start"]
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#[inline(always)]
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pub fn trans_start(&self) -> TRANS_START_R {
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TRANS_START_R::new(((self.bits >> 3) & 1) != 0)
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}
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#[doc = "Bit 4 - transit lsb first"]
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#[inline(always)]
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pub fn tx_lsb_first(&self) -> TX_LSB_FIRST_R {
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TX_LSB_FIRST_R::new(((self.bits >> 4) & 1) != 0)
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}
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#[doc = "Bit 5 - receive lsb first"]
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#[inline(always)]
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pub fn rx_lsb_first(&self) -> RX_LSB_FIRST_R {
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RX_LSB_FIRST_R::new(((self.bits >> 5) & 1) != 0)
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}
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#[doc = "Bit 29 - configure i2c ctrl clk enable"]
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#[inline(always)]
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pub fn i2c_ctrl_clk_gate_en(&self) -> I2C_CTRL_CLK_GATE_EN_R {
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I2C_CTRL_CLK_GATE_EN_R::new(((self.bits >> 29) & 1) != 0)
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}
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#[doc = "Bit 30 - rtc i2c sw reset"]
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#[inline(always)]
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pub fn i2c_reset(&self) -> I2C_RESET_R {
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I2C_RESET_R::new(((self.bits >> 30) & 1) != 0)
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}
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#[doc = "Bit 31 - rtc i2c reg clk gating"]
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#[inline(always)]
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pub fn i2cclk_en(&self) -> I2CCLK_EN_R {
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I2CCLK_EN_R::new(((self.bits >> 31) & 1) != 0)
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}
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}
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#[cfg(feature = "impl-register-debug")]
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impl core::fmt::Debug for R {
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fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
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f.debug_struct("CTRL")
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.field("sda_force_out", &self.sda_force_out())
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.field("scl_force_out", &self.scl_force_out())
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.field("ms_mode", &self.ms_mode())
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.field("trans_start", &self.trans_start())
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.field("tx_lsb_first", &self.tx_lsb_first())
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.field("rx_lsb_first", &self.rx_lsb_first())
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.field("i2c_ctrl_clk_gate_en", &self.i2c_ctrl_clk_gate_en())
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.field("i2c_reset", &self.i2c_reset())
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.field("i2cclk_en", &self.i2cclk_en())
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.finish()
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}
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}
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impl W {
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#[doc = "Bit 0 - 1=push pull,0=open drain"]
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#[inline(always)]
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pub fn sda_force_out(&mut self) -> SDA_FORCE_OUT_W<CTRL_SPEC> {
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SDA_FORCE_OUT_W::new(self, 0)
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}
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#[doc = "Bit 1 - 1=push pull,0=open drain"]
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#[inline(always)]
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pub fn scl_force_out(&mut self) -> SCL_FORCE_OUT_W<CTRL_SPEC> {
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SCL_FORCE_OUT_W::new(self, 1)
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}
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#[doc = "Bit 2 - 1=master,0=slave"]
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#[inline(always)]
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pub fn ms_mode(&mut self) -> MS_MODE_W<CTRL_SPEC> {
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MS_MODE_W::new(self, 2)
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}
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#[doc = "Bit 3 - force start"]
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#[inline(always)]
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pub fn trans_start(&mut self) -> TRANS_START_W<CTRL_SPEC> {
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TRANS_START_W::new(self, 3)
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}
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#[doc = "Bit 4 - transit lsb first"]
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#[inline(always)]
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pub fn tx_lsb_first(&mut self) -> TX_LSB_FIRST_W<CTRL_SPEC> {
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TX_LSB_FIRST_W::new(self, 4)
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}
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#[doc = "Bit 5 - receive lsb first"]
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#[inline(always)]
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pub fn rx_lsb_first(&mut self) -> RX_LSB_FIRST_W<CTRL_SPEC> {
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RX_LSB_FIRST_W::new(self, 5)
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}
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#[doc = "Bit 29 - configure i2c ctrl clk enable"]
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#[inline(always)]
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pub fn i2c_ctrl_clk_gate_en(&mut self) -> I2C_CTRL_CLK_GATE_EN_W<CTRL_SPEC> {
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I2C_CTRL_CLK_GATE_EN_W::new(self, 29)
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}
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#[doc = "Bit 30 - rtc i2c sw reset"]
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#[inline(always)]
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pub fn i2c_reset(&mut self) -> I2C_RESET_W<CTRL_SPEC> {
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I2C_RESET_W::new(self, 30)
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}
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#[doc = "Bit 31 - rtc i2c reg clk gating"]
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#[inline(always)]
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pub fn i2cclk_en(&mut self) -> I2CCLK_EN_W<CTRL_SPEC> {
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I2CCLK_EN_W::new(self, 31)
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}
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}
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#[doc = "configure i2c ctrl\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
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pub struct CTRL_SPEC;
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impl crate::RegisterSpec for CTRL_SPEC {
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type Ux = u32;
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}
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#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"]
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impl crate::Readable for CTRL_SPEC {}
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#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
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impl crate::Writable for CTRL_SPEC {
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type Safety = crate::Unsafe;
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const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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}
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#[doc = "`reset()` method sets CTRL to value 0"]
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impl crate::Resettable for CTRL_SPEC {
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const RESET_VALUE: u32 = 0;
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}
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Vendored
+63
@@ -0,0 +1,63 @@
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#[doc = "Register `DATA` reader"]
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pub type R = crate::R<DATA_SPEC>;
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#[doc = "Register `DATA` writer"]
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pub type W = crate::W<DATA_SPEC>;
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#[doc = "Field `I2C_RDATA` reader - data received"]
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pub type I2C_RDATA_R = crate::FieldReader;
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#[doc = "Field `SLAVE_TX_DATA` reader - data sent by slave"]
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pub type SLAVE_TX_DATA_R = crate::FieldReader;
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#[doc = "Field `SLAVE_TX_DATA` writer - data sent by slave"]
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pub type SLAVE_TX_DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
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#[doc = "Field `I2C_DONE` reader - i2c done"]
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pub type I2C_DONE_R = crate::BitReader;
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impl R {
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#[doc = "Bits 0:7 - data received"]
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#[inline(always)]
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pub fn i2c_rdata(&self) -> I2C_RDATA_R {
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I2C_RDATA_R::new((self.bits & 0xff) as u8)
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}
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#[doc = "Bits 8:15 - data sent by slave"]
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#[inline(always)]
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pub fn slave_tx_data(&self) -> SLAVE_TX_DATA_R {
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SLAVE_TX_DATA_R::new(((self.bits >> 8) & 0xff) as u8)
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}
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#[doc = "Bit 31 - i2c done"]
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#[inline(always)]
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pub fn i2c_done(&self) -> I2C_DONE_R {
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I2C_DONE_R::new(((self.bits >> 31) & 1) != 0)
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}
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}
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#[cfg(feature = "impl-register-debug")]
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impl core::fmt::Debug for R {
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fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
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f.debug_struct("DATA")
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.field("i2c_rdata", &self.i2c_rdata())
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.field("slave_tx_data", &self.slave_tx_data())
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.field("i2c_done", &self.i2c_done())
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.finish()
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}
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}
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impl W {
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#[doc = "Bits 8:15 - data sent by slave"]
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#[inline(always)]
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pub fn slave_tx_data(&mut self) -> SLAVE_TX_DATA_W<DATA_SPEC> {
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SLAVE_TX_DATA_W::new(self, 8)
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}
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}
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#[doc = "get i2c data status\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
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pub struct DATA_SPEC;
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impl crate::RegisterSpec for DATA_SPEC {
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type Ux = u32;
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}
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#[doc = "`read()` method returns [`data::R`](R) reader structure"]
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impl crate::Readable for DATA_SPEC {}
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#[doc = "`write(|w| ..)` method takes [`data::W`](W) writer structure"]
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impl crate::Writable for DATA_SPEC {
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type Safety = crate::Unsafe;
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const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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}
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#[doc = "`reset()` method sets DATA to value 0"]
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impl crate::Resettable for DATA_SPEC {
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const RESET_VALUE: u32 = 0;
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}
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Vendored
+47
@@ -0,0 +1,47 @@
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#[doc = "Register `DATE` reader"]
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pub type R = crate::R<DATE_SPEC>;
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#[doc = "Register `DATE` writer"]
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pub type W = crate::W<DATE_SPEC>;
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#[doc = "Field `I2C_DATE` reader - version"]
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pub type I2C_DATE_R = crate::FieldReader<u32>;
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#[doc = "Field `I2C_DATE` writer - version"]
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pub type I2C_DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>;
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||||
impl R {
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||||
#[doc = "Bits 0:27 - version"]
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#[inline(always)]
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||||
pub fn i2c_date(&self) -> I2C_DATE_R {
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I2C_DATE_R::new(self.bits & 0x0fff_ffff)
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||||
}
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}
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||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
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||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
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f.debug_struct("DATE")
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.field("i2c_date", &self.i2c_date())
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.finish()
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}
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||||
}
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impl W {
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||||
#[doc = "Bits 0:27 - version"]
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||||
#[inline(always)]
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||||
pub fn i2c_date(&mut self) -> I2C_DATE_W<DATE_SPEC> {
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I2C_DATE_W::new(self, 0)
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||||
}
|
||||
}
|
||||
#[doc = "version register\n\nYou can [`read`](crate::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct DATE_SPEC;
|
||||
impl crate::RegisterSpec for DATE_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`date::R`](R) reader structure"]
|
||||
impl crate::Readable for DATE_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"]
|
||||
impl crate::Writable for DATE_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets DATE to value 0x0190_5310"]
|
||||
impl crate::Resettable for DATE_SPEC {
|
||||
const RESET_VALUE: u32 = 0x0190_5310;
|
||||
}
|
||||
+88
@@ -0,0 +1,88 @@
|
||||
#[doc = "Register `INT_CLR` writer"]
|
||||
pub type W = crate::W<INT_CLR_SPEC>;
|
||||
#[doc = "Field `SLAVE_TRAN_COMP` writer - clear slave transit complete interrupt"]
|
||||
pub type SLAVE_TRAN_COMP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
|
||||
#[doc = "Field `ARBITRATION_LOST` writer - clear arbitration lost interrupt"]
|
||||
pub type ARBITRATION_LOST_W<'a, REG> = crate::BitWriter1C<'a, REG>;
|
||||
#[doc = "Field `MASTER_TRAN_COMP` writer - clear master transit complete interrupt"]
|
||||
pub type MASTER_TRAN_COMP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
|
||||
#[doc = "Field `TRANS_COMPLETE` writer - clear transit complete interrupt"]
|
||||
pub type TRANS_COMPLETE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
|
||||
#[doc = "Field `TIME_OUT` writer - clear time out interrupt"]
|
||||
pub type TIME_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
|
||||
#[doc = "Field `ACK_ERR` writer - clear ack error interrupt"]
|
||||
pub type ACK_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
|
||||
#[doc = "Field `RX_DATA` writer - clear receive data interrupt"]
|
||||
pub type RX_DATA_W<'a, REG> = crate::BitWriter1C<'a, REG>;
|
||||
#[doc = "Field `TX_DATA` writer - clear transit load data complete interrupt"]
|
||||
pub type TX_DATA_W<'a, REG> = crate::BitWriter1C<'a, REG>;
|
||||
#[doc = "Field `DETECT_START` writer - clear detect start interrupt"]
|
||||
pub type DETECT_START_W<'a, REG> = crate::BitWriter1C<'a, REG>;
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
|
||||
write!(f, "(not readable)")
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bit 0 - clear slave transit complete interrupt"]
|
||||
#[inline(always)]
|
||||
pub fn slave_tran_comp(&mut self) -> SLAVE_TRAN_COMP_W<INT_CLR_SPEC> {
|
||||
SLAVE_TRAN_COMP_W::new(self, 0)
|
||||
}
|
||||
#[doc = "Bit 1 - clear arbitration lost interrupt"]
|
||||
#[inline(always)]
|
||||
pub fn arbitration_lost(&mut self) -> ARBITRATION_LOST_W<INT_CLR_SPEC> {
|
||||
ARBITRATION_LOST_W::new(self, 1)
|
||||
}
|
||||
#[doc = "Bit 2 - clear master transit complete interrupt"]
|
||||
#[inline(always)]
|
||||
pub fn master_tran_comp(&mut self) -> MASTER_TRAN_COMP_W<INT_CLR_SPEC> {
|
||||
MASTER_TRAN_COMP_W::new(self, 2)
|
||||
}
|
||||
#[doc = "Bit 3 - clear transit complete interrupt"]
|
||||
#[inline(always)]
|
||||
pub fn trans_complete(&mut self) -> TRANS_COMPLETE_W<INT_CLR_SPEC> {
|
||||
TRANS_COMPLETE_W::new(self, 3)
|
||||
}
|
||||
#[doc = "Bit 4 - clear time out interrupt"]
|
||||
#[inline(always)]
|
||||
pub fn time_out(&mut self) -> TIME_OUT_W<INT_CLR_SPEC> {
|
||||
TIME_OUT_W::new(self, 4)
|
||||
}
|
||||
#[doc = "Bit 5 - clear ack error interrupt"]
|
||||
#[inline(always)]
|
||||
pub fn ack_err(&mut self) -> ACK_ERR_W<INT_CLR_SPEC> {
|
||||
ACK_ERR_W::new(self, 5)
|
||||
}
|
||||
#[doc = "Bit 6 - clear receive data interrupt"]
|
||||
#[inline(always)]
|
||||
pub fn rx_data(&mut self) -> RX_DATA_W<INT_CLR_SPEC> {
|
||||
RX_DATA_W::new(self, 6)
|
||||
}
|
||||
#[doc = "Bit 7 - clear transit load data complete interrupt"]
|
||||
#[inline(always)]
|
||||
pub fn tx_data(&mut self) -> TX_DATA_W<INT_CLR_SPEC> {
|
||||
TX_DATA_W::new(self, 7)
|
||||
}
|
||||
#[doc = "Bit 8 - clear detect start interrupt"]
|
||||
#[inline(always)]
|
||||
pub fn detect_start(&mut self) -> DETECT_START_W<INT_CLR_SPEC> {
|
||||
DETECT_START_W::new(self, 8)
|
||||
}
|
||||
}
|
||||
#[doc = "interrupt clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct INT_CLR_SPEC;
|
||||
impl crate::RegisterSpec for INT_CLR_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
|
||||
impl crate::Writable for INT_CLR_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x01ff;
|
||||
}
|
||||
#[doc = "`reset()` method sets INT_CLR to value 0"]
|
||||
impl crate::Resettable for INT_CLR_SPEC {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
+167
@@ -0,0 +1,167 @@
|
||||
#[doc = "Register `INT_ENA` reader"]
|
||||
pub type R = crate::R<INT_ENA_SPEC>;
|
||||
#[doc = "Register `INT_ENA` writer"]
|
||||
pub type W = crate::W<INT_ENA_SPEC>;
|
||||
#[doc = "Field `SLAVE_TRAN_COMP` reader - enable slave transit complete interrupt"]
|
||||
pub type SLAVE_TRAN_COMP_R = crate::BitReader;
|
||||
#[doc = "Field `SLAVE_TRAN_COMP` writer - enable slave transit complete interrupt"]
|
||||
pub type SLAVE_TRAN_COMP_W<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `ARBITRATION_LOST` reader - enable arbitration lost interrupt"]
|
||||
pub type ARBITRATION_LOST_R = crate::BitReader;
|
||||
#[doc = "Field `ARBITRATION_LOST` writer - enable arbitration lost interrupt"]
|
||||
pub type ARBITRATION_LOST_W<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `MASTER_TRAN_COMP` reader - enable master transit complete interrupt"]
|
||||
pub type MASTER_TRAN_COMP_R = crate::BitReader;
|
||||
#[doc = "Field `MASTER_TRAN_COMP` writer - enable master transit complete interrupt"]
|
||||
pub type MASTER_TRAN_COMP_W<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `TRANS_COMPLETE` reader - enable transit complete interrupt"]
|
||||
pub type TRANS_COMPLETE_R = crate::BitReader;
|
||||
#[doc = "Field `TRANS_COMPLETE` writer - enable transit complete interrupt"]
|
||||
pub type TRANS_COMPLETE_W<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `TIME_OUT` reader - enable time out interrupt"]
|
||||
pub type TIME_OUT_R = crate::BitReader;
|
||||
#[doc = "Field `TIME_OUT` writer - enable time out interrupt"]
|
||||
pub type TIME_OUT_W<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `ACK_ERR` reader - enable eack error interrupt"]
|
||||
pub type ACK_ERR_R = crate::BitReader;
|
||||
#[doc = "Field `ACK_ERR` writer - enable eack error interrupt"]
|
||||
pub type ACK_ERR_W<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `RX_DATA` reader - enable receive data interrupt"]
|
||||
pub type RX_DATA_R = crate::BitReader;
|
||||
#[doc = "Field `RX_DATA` writer - enable receive data interrupt"]
|
||||
pub type RX_DATA_W<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `TX_DATA` reader - enable transit data interrupt"]
|
||||
pub type TX_DATA_R = crate::BitReader;
|
||||
#[doc = "Field `TX_DATA` writer - enable transit data interrupt"]
|
||||
pub type TX_DATA_W<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `DETECT_START` reader - enable detect start interrupt"]
|
||||
pub type DETECT_START_R = crate::BitReader;
|
||||
#[doc = "Field `DETECT_START` writer - enable detect start interrupt"]
|
||||
pub type DETECT_START_W<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
impl R {
|
||||
#[doc = "Bit 0 - enable slave transit complete interrupt"]
|
||||
#[inline(always)]
|
||||
pub fn slave_tran_comp(&self) -> SLAVE_TRAN_COMP_R {
|
||||
SLAVE_TRAN_COMP_R::new((self.bits & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 1 - enable arbitration lost interrupt"]
|
||||
#[inline(always)]
|
||||
pub fn arbitration_lost(&self) -> ARBITRATION_LOST_R {
|
||||
ARBITRATION_LOST_R::new(((self.bits >> 1) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 2 - enable master transit complete interrupt"]
|
||||
#[inline(always)]
|
||||
pub fn master_tran_comp(&self) -> MASTER_TRAN_COMP_R {
|
||||
MASTER_TRAN_COMP_R::new(((self.bits >> 2) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 3 - enable transit complete interrupt"]
|
||||
#[inline(always)]
|
||||
pub fn trans_complete(&self) -> TRANS_COMPLETE_R {
|
||||
TRANS_COMPLETE_R::new(((self.bits >> 3) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 4 - enable time out interrupt"]
|
||||
#[inline(always)]
|
||||
pub fn time_out(&self) -> TIME_OUT_R {
|
||||
TIME_OUT_R::new(((self.bits >> 4) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 5 - enable eack error interrupt"]
|
||||
#[inline(always)]
|
||||
pub fn ack_err(&self) -> ACK_ERR_R {
|
||||
ACK_ERR_R::new(((self.bits >> 5) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 6 - enable receive data interrupt"]
|
||||
#[inline(always)]
|
||||
pub fn rx_data(&self) -> RX_DATA_R {
|
||||
RX_DATA_R::new(((self.bits >> 6) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 7 - enable transit data interrupt"]
|
||||
#[inline(always)]
|
||||
pub fn tx_data(&self) -> TX_DATA_R {
|
||||
TX_DATA_R::new(((self.bits >> 7) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 8 - enable detect start interrupt"]
|
||||
#[inline(always)]
|
||||
pub fn detect_start(&self) -> DETECT_START_R {
|
||||
DETECT_START_R::new(((self.bits >> 8) & 1) != 0)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("INT_ENA")
|
||||
.field("slave_tran_comp", &self.slave_tran_comp())
|
||||
.field("arbitration_lost", &self.arbitration_lost())
|
||||
.field("master_tran_comp", &self.master_tran_comp())
|
||||
.field("trans_complete", &self.trans_complete())
|
||||
.field("time_out", &self.time_out())
|
||||
.field("ack_err", &self.ack_err())
|
||||
.field("rx_data", &self.rx_data())
|
||||
.field("tx_data", &self.tx_data())
|
||||
.field("detect_start", &self.detect_start())
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bit 0 - enable slave transit complete interrupt"]
|
||||
#[inline(always)]
|
||||
pub fn slave_tran_comp(&mut self) -> SLAVE_TRAN_COMP_W<INT_ENA_SPEC> {
|
||||
SLAVE_TRAN_COMP_W::new(self, 0)
|
||||
}
|
||||
#[doc = "Bit 1 - enable arbitration lost interrupt"]
|
||||
#[inline(always)]
|
||||
pub fn arbitration_lost(&mut self) -> ARBITRATION_LOST_W<INT_ENA_SPEC> {
|
||||
ARBITRATION_LOST_W::new(self, 1)
|
||||
}
|
||||
#[doc = "Bit 2 - enable master transit complete interrupt"]
|
||||
#[inline(always)]
|
||||
pub fn master_tran_comp(&mut self) -> MASTER_TRAN_COMP_W<INT_ENA_SPEC> {
|
||||
MASTER_TRAN_COMP_W::new(self, 2)
|
||||
}
|
||||
#[doc = "Bit 3 - enable transit complete interrupt"]
|
||||
#[inline(always)]
|
||||
pub fn trans_complete(&mut self) -> TRANS_COMPLETE_W<INT_ENA_SPEC> {
|
||||
TRANS_COMPLETE_W::new(self, 3)
|
||||
}
|
||||
#[doc = "Bit 4 - enable time out interrupt"]
|
||||
#[inline(always)]
|
||||
pub fn time_out(&mut self) -> TIME_OUT_W<INT_ENA_SPEC> {
|
||||
TIME_OUT_W::new(self, 4)
|
||||
}
|
||||
#[doc = "Bit 5 - enable eack error interrupt"]
|
||||
#[inline(always)]
|
||||
pub fn ack_err(&mut self) -> ACK_ERR_W<INT_ENA_SPEC> {
|
||||
ACK_ERR_W::new(self, 5)
|
||||
}
|
||||
#[doc = "Bit 6 - enable receive data interrupt"]
|
||||
#[inline(always)]
|
||||
pub fn rx_data(&mut self) -> RX_DATA_W<INT_ENA_SPEC> {
|
||||
RX_DATA_W::new(self, 6)
|
||||
}
|
||||
#[doc = "Bit 7 - enable transit data interrupt"]
|
||||
#[inline(always)]
|
||||
pub fn tx_data(&mut self) -> TX_DATA_W<INT_ENA_SPEC> {
|
||||
TX_DATA_W::new(self, 7)
|
||||
}
|
||||
#[doc = "Bit 8 - enable detect start interrupt"]
|
||||
#[inline(always)]
|
||||
pub fn detect_start(&mut self) -> DETECT_START_W<INT_ENA_SPEC> {
|
||||
DETECT_START_W::new(self, 8)
|
||||
}
|
||||
}
|
||||
#[doc = "interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct INT_ENA_SPEC;
|
||||
impl crate::RegisterSpec for INT_ENA_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"]
|
||||
impl crate::Readable for INT_ENA_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"]
|
||||
impl crate::Writable for INT_ENA_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets INT_ENA to value 0"]
|
||||
impl crate::Resettable for INT_ENA_SPEC {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
+94
@@ -0,0 +1,94 @@
|
||||
#[doc = "Register `INT_RAW` reader"]
|
||||
pub type R = crate::R<INT_RAW_SPEC>;
|
||||
#[doc = "Field `SLAVE_TRAN_COMP` reader - slave transit complete interrupt raw"]
|
||||
pub type SLAVE_TRAN_COMP_R = crate::BitReader;
|
||||
#[doc = "Field `ARBITRATION_LOST` reader - arbitration lost interrupt raw"]
|
||||
pub type ARBITRATION_LOST_R = crate::BitReader;
|
||||
#[doc = "Field `MASTER_TRAN_COMP` reader - master transit complete interrupt raw"]
|
||||
pub type MASTER_TRAN_COMP_R = crate::BitReader;
|
||||
#[doc = "Field `TRANS_COMPLETE` reader - transit complete interrupt raw"]
|
||||
pub type TRANS_COMPLETE_R = crate::BitReader;
|
||||
#[doc = "Field `TIME_OUT` reader - time out interrupt raw"]
|
||||
pub type TIME_OUT_R = crate::BitReader;
|
||||
#[doc = "Field `ACK_ERR` reader - ack error interrupt raw"]
|
||||
pub type ACK_ERR_R = crate::BitReader;
|
||||
#[doc = "Field `RX_DATA` reader - receive data interrupt raw"]
|
||||
pub type RX_DATA_R = crate::BitReader;
|
||||
#[doc = "Field `TX_DATA` reader - transit data interrupt raw"]
|
||||
pub type TX_DATA_R = crate::BitReader;
|
||||
#[doc = "Field `DETECT_START` reader - detect start interrupt raw"]
|
||||
pub type DETECT_START_R = crate::BitReader;
|
||||
impl R {
|
||||
#[doc = "Bit 0 - slave transit complete interrupt raw"]
|
||||
#[inline(always)]
|
||||
pub fn slave_tran_comp(&self) -> SLAVE_TRAN_COMP_R {
|
||||
SLAVE_TRAN_COMP_R::new((self.bits & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 1 - arbitration lost interrupt raw"]
|
||||
#[inline(always)]
|
||||
pub fn arbitration_lost(&self) -> ARBITRATION_LOST_R {
|
||||
ARBITRATION_LOST_R::new(((self.bits >> 1) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 2 - master transit complete interrupt raw"]
|
||||
#[inline(always)]
|
||||
pub fn master_tran_comp(&self) -> MASTER_TRAN_COMP_R {
|
||||
MASTER_TRAN_COMP_R::new(((self.bits >> 2) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 3 - transit complete interrupt raw"]
|
||||
#[inline(always)]
|
||||
pub fn trans_complete(&self) -> TRANS_COMPLETE_R {
|
||||
TRANS_COMPLETE_R::new(((self.bits >> 3) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 4 - time out interrupt raw"]
|
||||
#[inline(always)]
|
||||
pub fn time_out(&self) -> TIME_OUT_R {
|
||||
TIME_OUT_R::new(((self.bits >> 4) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 5 - ack error interrupt raw"]
|
||||
#[inline(always)]
|
||||
pub fn ack_err(&self) -> ACK_ERR_R {
|
||||
ACK_ERR_R::new(((self.bits >> 5) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 6 - receive data interrupt raw"]
|
||||
#[inline(always)]
|
||||
pub fn rx_data(&self) -> RX_DATA_R {
|
||||
RX_DATA_R::new(((self.bits >> 6) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 7 - transit data interrupt raw"]
|
||||
#[inline(always)]
|
||||
pub fn tx_data(&self) -> TX_DATA_R {
|
||||
TX_DATA_R::new(((self.bits >> 7) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 8 - detect start interrupt raw"]
|
||||
#[inline(always)]
|
||||
pub fn detect_start(&self) -> DETECT_START_R {
|
||||
DETECT_START_R::new(((self.bits >> 8) & 1) != 0)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("INT_RAW")
|
||||
.field("slave_tran_comp", &self.slave_tran_comp())
|
||||
.field("arbitration_lost", &self.arbitration_lost())
|
||||
.field("master_tran_comp", &self.master_tran_comp())
|
||||
.field("trans_complete", &self.trans_complete())
|
||||
.field("time_out", &self.time_out())
|
||||
.field("ack_err", &self.ack_err())
|
||||
.field("rx_data", &self.rx_data())
|
||||
.field("tx_data", &self.tx_data())
|
||||
.field("detect_start", &self.detect_start())
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
#[doc = "interrupt raw register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_raw::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct INT_RAW_SPEC;
|
||||
impl crate::RegisterSpec for INT_RAW_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"]
|
||||
impl crate::Readable for INT_RAW_SPEC {}
|
||||
#[doc = "`reset()` method sets INT_RAW to value 0"]
|
||||
impl crate::Resettable for INT_RAW_SPEC {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
Vendored
+94
@@ -0,0 +1,94 @@
|
||||
#[doc = "Register `INT_ST` reader"]
|
||||
pub type R = crate::R<INT_ST_SPEC>;
|
||||
#[doc = "Field `SLAVE_TRAN_COMP` reader - slave transit complete interrupt state"]
|
||||
pub type SLAVE_TRAN_COMP_R = crate::BitReader;
|
||||
#[doc = "Field `ARBITRATION_LOST` reader - arbitration lost interrupt state"]
|
||||
pub type ARBITRATION_LOST_R = crate::BitReader;
|
||||
#[doc = "Field `MASTER_TRAN_COMP` reader - master transit complete interrupt state"]
|
||||
pub type MASTER_TRAN_COMP_R = crate::BitReader;
|
||||
#[doc = "Field `TRANS_COMPLETE` reader - transit complete interrupt state"]
|
||||
pub type TRANS_COMPLETE_R = crate::BitReader;
|
||||
#[doc = "Field `TIME_OUT` reader - time out interrupt state"]
|
||||
pub type TIME_OUT_R = crate::BitReader;
|
||||
#[doc = "Field `ACK_ERR` reader - ack error interrupt state"]
|
||||
pub type ACK_ERR_R = crate::BitReader;
|
||||
#[doc = "Field `RX_DATA` reader - receive data interrupt state"]
|
||||
pub type RX_DATA_R = crate::BitReader;
|
||||
#[doc = "Field `TX_DATA` reader - transit data interrupt state"]
|
||||
pub type TX_DATA_R = crate::BitReader;
|
||||
#[doc = "Field `DETECT_START` reader - detect start interrupt state"]
|
||||
pub type DETECT_START_R = crate::BitReader;
|
||||
impl R {
|
||||
#[doc = "Bit 0 - slave transit complete interrupt state"]
|
||||
#[inline(always)]
|
||||
pub fn slave_tran_comp(&self) -> SLAVE_TRAN_COMP_R {
|
||||
SLAVE_TRAN_COMP_R::new((self.bits & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 1 - arbitration lost interrupt state"]
|
||||
#[inline(always)]
|
||||
pub fn arbitration_lost(&self) -> ARBITRATION_LOST_R {
|
||||
ARBITRATION_LOST_R::new(((self.bits >> 1) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 2 - master transit complete interrupt state"]
|
||||
#[inline(always)]
|
||||
pub fn master_tran_comp(&self) -> MASTER_TRAN_COMP_R {
|
||||
MASTER_TRAN_COMP_R::new(((self.bits >> 2) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 3 - transit complete interrupt state"]
|
||||
#[inline(always)]
|
||||
pub fn trans_complete(&self) -> TRANS_COMPLETE_R {
|
||||
TRANS_COMPLETE_R::new(((self.bits >> 3) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 4 - time out interrupt state"]
|
||||
#[inline(always)]
|
||||
pub fn time_out(&self) -> TIME_OUT_R {
|
||||
TIME_OUT_R::new(((self.bits >> 4) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 5 - ack error interrupt state"]
|
||||
#[inline(always)]
|
||||
pub fn ack_err(&self) -> ACK_ERR_R {
|
||||
ACK_ERR_R::new(((self.bits >> 5) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 6 - receive data interrupt state"]
|
||||
#[inline(always)]
|
||||
pub fn rx_data(&self) -> RX_DATA_R {
|
||||
RX_DATA_R::new(((self.bits >> 6) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 7 - transit data interrupt state"]
|
||||
#[inline(always)]
|
||||
pub fn tx_data(&self) -> TX_DATA_R {
|
||||
TX_DATA_R::new(((self.bits >> 7) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 8 - detect start interrupt state"]
|
||||
#[inline(always)]
|
||||
pub fn detect_start(&self) -> DETECT_START_R {
|
||||
DETECT_START_R::new(((self.bits >> 8) & 1) != 0)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("INT_ST")
|
||||
.field("slave_tran_comp", &self.slave_tran_comp())
|
||||
.field("arbitration_lost", &self.arbitration_lost())
|
||||
.field("master_tran_comp", &self.master_tran_comp())
|
||||
.field("trans_complete", &self.trans_complete())
|
||||
.field("time_out", &self.time_out())
|
||||
.field("ack_err", &self.ack_err())
|
||||
.field("rx_data", &self.rx_data())
|
||||
.field("tx_data", &self.tx_data())
|
||||
.field("detect_start", &self.detect_start())
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
#[doc = "interrupt state register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct INT_ST_SPEC;
|
||||
impl crate::RegisterSpec for INT_ST_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`int_st::R`](R) reader structure"]
|
||||
impl crate::Readable for INT_ST_SPEC {}
|
||||
#[doc = "`reset()` method sets INT_ST to value 0"]
|
||||
impl crate::Resettable for INT_ST_SPEC {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
+47
@@ -0,0 +1,47 @@
|
||||
#[doc = "Register `SCL_HIGH` reader"]
|
||||
pub type R = crate::R<SCL_HIGH_SPEC>;
|
||||
#[doc = "Register `SCL_HIGH` writer"]
|
||||
pub type W = crate::W<SCL_HIGH_SPEC>;
|
||||
#[doc = "Field `PERIOD` reader - time period that scl = 1"]
|
||||
pub type PERIOD_R = crate::FieldReader<u32>;
|
||||
#[doc = "Field `PERIOD` writer - time period that scl = 1"]
|
||||
pub type PERIOD_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:19 - time period that scl = 1"]
|
||||
#[inline(always)]
|
||||
pub fn period(&self) -> PERIOD_R {
|
||||
PERIOD_R::new(self.bits & 0x000f_ffff)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("SCL_HIGH")
|
||||
.field("period", &self.period())
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:19 - time period that scl = 1"]
|
||||
#[inline(always)]
|
||||
pub fn period(&mut self) -> PERIOD_W<SCL_HIGH_SPEC> {
|
||||
PERIOD_W::new(self, 0)
|
||||
}
|
||||
}
|
||||
#[doc = "configure high scl period\n\nYou can [`read`](crate::Reg::read) this register and get [`scl_high::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scl_high::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct SCL_HIGH_SPEC;
|
||||
impl crate::RegisterSpec for SCL_HIGH_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`scl_high::R`](R) reader structure"]
|
||||
impl crate::Readable for SCL_HIGH_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`scl_high::W`](W) writer structure"]
|
||||
impl crate::Writable for SCL_HIGH_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets SCL_HIGH to value 0x0100"]
|
||||
impl crate::Resettable for SCL_HIGH_SPEC {
|
||||
const RESET_VALUE: u32 = 0x0100;
|
||||
}
|
||||
+47
@@ -0,0 +1,47 @@
|
||||
#[doc = "Register `SCL_LOW` reader"]
|
||||
pub type R = crate::R<SCL_LOW_SPEC>;
|
||||
#[doc = "Register `SCL_LOW` writer"]
|
||||
pub type W = crate::W<SCL_LOW_SPEC>;
|
||||
#[doc = "Field `PERIOD` reader - time period that scl =0"]
|
||||
pub type PERIOD_R = crate::FieldReader<u32>;
|
||||
#[doc = "Field `PERIOD` writer - time period that scl =0"]
|
||||
pub type PERIOD_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:19 - time period that scl =0"]
|
||||
#[inline(always)]
|
||||
pub fn period(&self) -> PERIOD_R {
|
||||
PERIOD_R::new(self.bits & 0x000f_ffff)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("SCL_LOW")
|
||||
.field("period", &self.period())
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:19 - time period that scl =0"]
|
||||
#[inline(always)]
|
||||
pub fn period(&mut self) -> PERIOD_W<SCL_LOW_SPEC> {
|
||||
PERIOD_W::new(self, 0)
|
||||
}
|
||||
}
|
||||
#[doc = "configure low scl period\n\nYou can [`read`](crate::Reg::read) this register and get [`scl_low::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scl_low::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct SCL_LOW_SPEC;
|
||||
impl crate::RegisterSpec for SCL_LOW_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`scl_low::R`](R) reader structure"]
|
||||
impl crate::Readable for SCL_LOW_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`scl_low::W`](W) writer structure"]
|
||||
impl crate::Writable for SCL_LOW_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets SCL_LOW to value 0x0100"]
|
||||
impl crate::Resettable for SCL_LOW_SPEC {
|
||||
const RESET_VALUE: u32 = 0x0100;
|
||||
}
|
||||
+47
@@ -0,0 +1,47 @@
|
||||
#[doc = "Register `SCL_START_PERIOD` reader"]
|
||||
pub type R = crate::R<SCL_START_PERIOD_SPEC>;
|
||||
#[doc = "Register `SCL_START_PERIOD` writer"]
|
||||
pub type W = crate::W<SCL_START_PERIOD_SPEC>;
|
||||
#[doc = "Field `SCL_START_PERIOD` reader - time period for SCL to toggle after I2C start is triggered"]
|
||||
pub type SCL_START_PERIOD_R = crate::FieldReader<u32>;
|
||||
#[doc = "Field `SCL_START_PERIOD` writer - time period for SCL to toggle after I2C start is triggered"]
|
||||
pub type SCL_START_PERIOD_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:19 - time period for SCL to toggle after I2C start is triggered"]
|
||||
#[inline(always)]
|
||||
pub fn scl_start_period(&self) -> SCL_START_PERIOD_R {
|
||||
SCL_START_PERIOD_R::new(self.bits & 0x000f_ffff)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("SCL_START_PERIOD")
|
||||
.field("scl_start_period", &self.scl_start_period())
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:19 - time period for SCL to toggle after I2C start is triggered"]
|
||||
#[inline(always)]
|
||||
pub fn scl_start_period(&mut self) -> SCL_START_PERIOD_W<SCL_START_PERIOD_SPEC> {
|
||||
SCL_START_PERIOD_W::new(self, 0)
|
||||
}
|
||||
}
|
||||
#[doc = "configure scl start period\n\nYou can [`read`](crate::Reg::read) this register and get [`scl_start_period::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scl_start_period::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct SCL_START_PERIOD_SPEC;
|
||||
impl crate::RegisterSpec for SCL_START_PERIOD_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`scl_start_period::R`](R) reader structure"]
|
||||
impl crate::Readable for SCL_START_PERIOD_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`scl_start_period::W`](W) writer structure"]
|
||||
impl crate::Writable for SCL_START_PERIOD_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets SCL_START_PERIOD to value 0x08"]
|
||||
impl crate::Resettable for SCL_START_PERIOD_SPEC {
|
||||
const RESET_VALUE: u32 = 0x08;
|
||||
}
|
||||
+47
@@ -0,0 +1,47 @@
|
||||
#[doc = "Register `SCL_STOP_PERIOD` reader"]
|
||||
pub type R = crate::R<SCL_STOP_PERIOD_SPEC>;
|
||||
#[doc = "Register `SCL_STOP_PERIOD` writer"]
|
||||
pub type W = crate::W<SCL_STOP_PERIOD_SPEC>;
|
||||
#[doc = "Field `SCL_STOP_PERIOD` reader - time period for SCL to stop after I2C end is triggered"]
|
||||
pub type SCL_STOP_PERIOD_R = crate::FieldReader<u32>;
|
||||
#[doc = "Field `SCL_STOP_PERIOD` writer - time period for SCL to stop after I2C end is triggered"]
|
||||
pub type SCL_STOP_PERIOD_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:19 - time period for SCL to stop after I2C end is triggered"]
|
||||
#[inline(always)]
|
||||
pub fn scl_stop_period(&self) -> SCL_STOP_PERIOD_R {
|
||||
SCL_STOP_PERIOD_R::new(self.bits & 0x000f_ffff)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("SCL_STOP_PERIOD")
|
||||
.field("scl_stop_period", &self.scl_stop_period())
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:19 - time period for SCL to stop after I2C end is triggered"]
|
||||
#[inline(always)]
|
||||
pub fn scl_stop_period(&mut self) -> SCL_STOP_PERIOD_W<SCL_STOP_PERIOD_SPEC> {
|
||||
SCL_STOP_PERIOD_W::new(self, 0)
|
||||
}
|
||||
}
|
||||
#[doc = "configure scl stop period\n\nYou can [`read`](crate::Reg::read) this register and get [`scl_stop_period::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scl_stop_period::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct SCL_STOP_PERIOD_SPEC;
|
||||
impl crate::RegisterSpec for SCL_STOP_PERIOD_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`scl_stop_period::R`](R) reader structure"]
|
||||
impl crate::Readable for SCL_STOP_PERIOD_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`scl_stop_period::W`](W) writer structure"]
|
||||
impl crate::Writable for SCL_STOP_PERIOD_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets SCL_STOP_PERIOD to value 0x08"]
|
||||
impl crate::Resettable for SCL_STOP_PERIOD_SPEC {
|
||||
const RESET_VALUE: u32 = 0x08;
|
||||
}
|
||||
+47
@@ -0,0 +1,47 @@
|
||||
#[doc = "Register `SDA_DUTY` reader"]
|
||||
pub type R = crate::R<SDA_DUTY_SPEC>;
|
||||
#[doc = "Register `SDA_DUTY` writer"]
|
||||
pub type W = crate::W<SDA_DUTY_SPEC>;
|
||||
#[doc = "Field `NUM` reader - time period for SDA to toggle after SCL goes low"]
|
||||
pub type NUM_R = crate::FieldReader<u32>;
|
||||
#[doc = "Field `NUM` writer - time period for SDA to toggle after SCL goes low"]
|
||||
pub type NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:19 - time period for SDA to toggle after SCL goes low"]
|
||||
#[inline(always)]
|
||||
pub fn num(&self) -> NUM_R {
|
||||
NUM_R::new(self.bits & 0x000f_ffff)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("SDA_DUTY")
|
||||
.field("num", &self.num())
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:19 - time period for SDA to toggle after SCL goes low"]
|
||||
#[inline(always)]
|
||||
pub fn num(&mut self) -> NUM_W<SDA_DUTY_SPEC> {
|
||||
NUM_W::new(self, 0)
|
||||
}
|
||||
}
|
||||
#[doc = "configure sda duty\n\nYou can [`read`](crate::Reg::read) this register and get [`sda_duty::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sda_duty::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct SDA_DUTY_SPEC;
|
||||
impl crate::RegisterSpec for SDA_DUTY_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`sda_duty::R`](R) reader structure"]
|
||||
impl crate::Readable for SDA_DUTY_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`sda_duty::W`](W) writer structure"]
|
||||
impl crate::Writable for SDA_DUTY_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets SDA_DUTY to value 0x10"]
|
||||
impl crate::Resettable for SDA_DUTY_SPEC {
|
||||
const RESET_VALUE: u32 = 0x10;
|
||||
}
|
||||
+62
@@ -0,0 +1,62 @@
|
||||
#[doc = "Register `SLAVE_ADDR` reader"]
|
||||
pub type R = crate::R<SLAVE_ADDR_SPEC>;
|
||||
#[doc = "Register `SLAVE_ADDR` writer"]
|
||||
pub type W = crate::W<SLAVE_ADDR_SPEC>;
|
||||
#[doc = "Field `SLAVE_ADDR` reader - slave address"]
|
||||
pub type SLAVE_ADDR_R = crate::FieldReader<u16>;
|
||||
#[doc = "Field `SLAVE_ADDR` writer - slave address"]
|
||||
pub type SLAVE_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>;
|
||||
#[doc = "Field `ADDR_10BIT_EN` reader - i2c 10bit mode enable"]
|
||||
pub type ADDR_10BIT_EN_R = crate::BitReader;
|
||||
#[doc = "Field `ADDR_10BIT_EN` writer - i2c 10bit mode enable"]
|
||||
pub type ADDR_10BIT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:14 - slave address"]
|
||||
#[inline(always)]
|
||||
pub fn slave_addr(&self) -> SLAVE_ADDR_R {
|
||||
SLAVE_ADDR_R::new((self.bits & 0x7fff) as u16)
|
||||
}
|
||||
#[doc = "Bit 31 - i2c 10bit mode enable"]
|
||||
#[inline(always)]
|
||||
pub fn addr_10bit_en(&self) -> ADDR_10BIT_EN_R {
|
||||
ADDR_10BIT_EN_R::new(((self.bits >> 31) & 1) != 0)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("SLAVE_ADDR")
|
||||
.field("slave_addr", &self.slave_addr())
|
||||
.field("addr_10bit_en", &self.addr_10bit_en())
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:14 - slave address"]
|
||||
#[inline(always)]
|
||||
pub fn slave_addr(&mut self) -> SLAVE_ADDR_W<SLAVE_ADDR_SPEC> {
|
||||
SLAVE_ADDR_W::new(self, 0)
|
||||
}
|
||||
#[doc = "Bit 31 - i2c 10bit mode enable"]
|
||||
#[inline(always)]
|
||||
pub fn addr_10bit_en(&mut self) -> ADDR_10BIT_EN_W<SLAVE_ADDR_SPEC> {
|
||||
ADDR_10BIT_EN_W::new(self, 31)
|
||||
}
|
||||
}
|
||||
#[doc = "configure slave id\n\nYou can [`read`](crate::Reg::read) this register and get [`slave_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slave_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct SLAVE_ADDR_SPEC;
|
||||
impl crate::RegisterSpec for SLAVE_ADDR_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`slave_addr::R`](R) reader structure"]
|
||||
impl crate::Readable for SLAVE_ADDR_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`slave_addr::W`](W) writer structure"]
|
||||
impl crate::Writable for SLAVE_ADDR_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets SLAVE_ADDR to value 0"]
|
||||
impl crate::Resettable for SLAVE_ADDR_SPEC {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
Vendored
+102
@@ -0,0 +1,102 @@
|
||||
#[doc = "Register `STATUS` reader"]
|
||||
pub type R = crate::R<STATUS_SPEC>;
|
||||
#[doc = "Field `ACK_REC` reader - ack response"]
|
||||
pub type ACK_REC_R = crate::BitReader;
|
||||
#[doc = "Field `SLAVE_RW` reader - slave read or write"]
|
||||
pub type SLAVE_RW_R = crate::BitReader;
|
||||
#[doc = "Field `ARB_LOST` reader - arbitration is lost"]
|
||||
pub type ARB_LOST_R = crate::BitReader;
|
||||
#[doc = "Field `BUS_BUSY` reader - bus is busy"]
|
||||
pub type BUS_BUSY_R = crate::BitReader;
|
||||
#[doc = "Field `SLAVE_ADDRESSED` reader - slave reg sub address"]
|
||||
pub type SLAVE_ADDRESSED_R = crate::BitReader;
|
||||
#[doc = "Field `BYTE_TRANS` reader - One byte transit done"]
|
||||
pub type BYTE_TRANS_R = crate::BitReader;
|
||||
#[doc = "Field `OP_CNT` reader - which operation is working"]
|
||||
pub type OP_CNT_R = crate::FieldReader;
|
||||
#[doc = "Field `SHIFT` reader - shifter content"]
|
||||
pub type SHIFT_R = crate::FieldReader;
|
||||
#[doc = "Field `SCL_MAIN_STATE_LAST` reader - i2c last main status"]
|
||||
pub type SCL_MAIN_STATE_LAST_R = crate::FieldReader;
|
||||
#[doc = "Field `SCL_STATE_LAST` reader - scl last status"]
|
||||
pub type SCL_STATE_LAST_R = crate::FieldReader;
|
||||
impl R {
|
||||
#[doc = "Bit 0 - ack response"]
|
||||
#[inline(always)]
|
||||
pub fn ack_rec(&self) -> ACK_REC_R {
|
||||
ACK_REC_R::new((self.bits & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 1 - slave read or write"]
|
||||
#[inline(always)]
|
||||
pub fn slave_rw(&self) -> SLAVE_RW_R {
|
||||
SLAVE_RW_R::new(((self.bits >> 1) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 2 - arbitration is lost"]
|
||||
#[inline(always)]
|
||||
pub fn arb_lost(&self) -> ARB_LOST_R {
|
||||
ARB_LOST_R::new(((self.bits >> 2) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 3 - bus is busy"]
|
||||
#[inline(always)]
|
||||
pub fn bus_busy(&self) -> BUS_BUSY_R {
|
||||
BUS_BUSY_R::new(((self.bits >> 3) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 4 - slave reg sub address"]
|
||||
#[inline(always)]
|
||||
pub fn slave_addressed(&self) -> SLAVE_ADDRESSED_R {
|
||||
SLAVE_ADDRESSED_R::new(((self.bits >> 4) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 5 - One byte transit done"]
|
||||
#[inline(always)]
|
||||
pub fn byte_trans(&self) -> BYTE_TRANS_R {
|
||||
BYTE_TRANS_R::new(((self.bits >> 5) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bits 6:7 - which operation is working"]
|
||||
#[inline(always)]
|
||||
pub fn op_cnt(&self) -> OP_CNT_R {
|
||||
OP_CNT_R::new(((self.bits >> 6) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 16:23 - shifter content"]
|
||||
#[inline(always)]
|
||||
pub fn shift(&self) -> SHIFT_R {
|
||||
SHIFT_R::new(((self.bits >> 16) & 0xff) as u8)
|
||||
}
|
||||
#[doc = "Bits 24:26 - i2c last main status"]
|
||||
#[inline(always)]
|
||||
pub fn scl_main_state_last(&self) -> SCL_MAIN_STATE_LAST_R {
|
||||
SCL_MAIN_STATE_LAST_R::new(((self.bits >> 24) & 7) as u8)
|
||||
}
|
||||
#[doc = "Bits 28:30 - scl last status"]
|
||||
#[inline(always)]
|
||||
pub fn scl_state_last(&self) -> SCL_STATE_LAST_R {
|
||||
SCL_STATE_LAST_R::new(((self.bits >> 28) & 7) as u8)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("STATUS")
|
||||
.field("ack_rec", &self.ack_rec())
|
||||
.field("slave_rw", &self.slave_rw())
|
||||
.field("arb_lost", &self.arb_lost())
|
||||
.field("bus_busy", &self.bus_busy())
|
||||
.field("slave_addressed", &self.slave_addressed())
|
||||
.field("byte_trans", &self.byte_trans())
|
||||
.field("op_cnt", &self.op_cnt())
|
||||
.field("shift", &self.shift())
|
||||
.field("scl_main_state_last", &self.scl_main_state_last())
|
||||
.field("scl_state_last", &self.scl_state_last())
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
#[doc = "get i2c status\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct STATUS_SPEC;
|
||||
impl crate::RegisterSpec for STATUS_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`status::R`](R) reader structure"]
|
||||
impl crate::Readable for STATUS_SPEC {}
|
||||
#[doc = "`reset()` method sets STATUS to value 0"]
|
||||
impl crate::Resettable for STATUS_SPEC {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
Vendored
+47
@@ -0,0 +1,47 @@
|
||||
#[doc = "Register `TO` reader"]
|
||||
pub type R = crate::R<TO_SPEC>;
|
||||
#[doc = "Register `TO` writer"]
|
||||
pub type W = crate::W<TO_SPEC>;
|
||||
#[doc = "Field `TIME_OUT` reader - time out threshold"]
|
||||
pub type TIME_OUT_R = crate::FieldReader<u32>;
|
||||
#[doc = "Field `TIME_OUT` writer - time out threshold"]
|
||||
pub type TIME_OUT_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:19 - time out threshold"]
|
||||
#[inline(always)]
|
||||
pub fn time_out(&self) -> TIME_OUT_R {
|
||||
TIME_OUT_R::new(self.bits & 0x000f_ffff)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("TO")
|
||||
.field("time_out", &self.time_out())
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:19 - time out threshold"]
|
||||
#[inline(always)]
|
||||
pub fn time_out(&mut self) -> TIME_OUT_W<TO_SPEC> {
|
||||
TIME_OUT_W::new(self, 0)
|
||||
}
|
||||
}
|
||||
#[doc = "configure time out\n\nYou can [`read`](crate::Reg::read) this register and get [`to::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`to::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct TO_SPEC;
|
||||
impl crate::RegisterSpec for TO_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`to::R`](R) reader structure"]
|
||||
impl crate::Readable for TO_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`to::W`](W) writer structure"]
|
||||
impl crate::Writable for TO_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets TO to value 0x0001_0000"]
|
||||
impl crate::Resettable for TO_SPEC {
|
||||
const RESET_VALUE: u32 = 0x0001_0000;
|
||||
}
|
||||
Reference in new issue
Block a user