feat: add display UI with splash screen, dashboard, and RSSI sparkline

Implement full SSD1306 OLED display support:
- Splash screen on boot (1.5s) with project name, version, board
- Dashboard showing radio state, config, counters, RSSI/SNR
- RSSI history sparkline (64-sample ring buffer, 2px-wide bars)
- DisplayOn/DisplayOff host commands routed via dedicated channel
- Pure render functions against generic DrawTarget (no hardware coupling)
- Display on/off control bypasses radio task entirely

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>

vendor/esp32s3/src/rtc_io/date.rs

@@ -0,0 +1,45 @@
+#[doc = "Register `DATE` reader"]
+pub type R = crate::R<DATE_SPEC>;
+#[doc = "Register `DATE` writer"]
+pub type W = crate::W<DATE_SPEC>;
+#[doc = "Field `DATE` reader - version"]
+pub type DATE_R = crate::FieldReader<u32>;
+#[doc = "Field `DATE` writer - version"]
+pub type DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>;
+impl R {
+    #[doc = "Bits 0:27 - version"]
+    #[inline(always)]
+    pub fn date(&self) -> DATE_R {
+        DATE_R::new(self.bits & 0x0fff_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DATE").field("date", &self.date()).finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:27 - version"]
+    #[inline(always)]
+    pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
+        DATE_W::new(self, 0)
+    }
+}
+#[doc = "version\n\nYou can [`read`](crate::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DATE_SPEC;
+impl crate::RegisterSpec for DATE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`date::R`](R) reader structure"]
+impl crate::Readable for DATE_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"]
+impl crate::Writable for DATE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DATE to value 0x0210_1180"]
+impl crate::Resettable for DATE_SPEC {
+    const RESET_VALUE: u32 = 0x0210_1180;
+}

vendor/esp32s3/src/rtc_io/enable_w1tc.rs

@@ -0,0 +1,32 @@
+#[doc = "Register `ENABLE_W1TC` writer"]
+pub type W = crate::W<ENABLE_W1TC_SPEC>;
+#[doc = "Field `ENABLE_W1TC` writer - RTC GPIO 0 ~ 21 enable write 1 to clear"]
+pub type ENABLE_W1TC_W<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>;
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for crate::generic::Reg<ENABLE_W1TC_SPEC> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "(not readable)")
+    }
+}
+impl W {
+    #[doc = "Bits 10:31 - RTC GPIO 0 ~ 21 enable write 1 to clear"]
+    #[inline(always)]
+    pub fn enable_w1tc(&mut self) -> ENABLE_W1TC_W<ENABLE_W1TC_SPEC> {
+        ENABLE_W1TC_W::new(self, 10)
+    }
+}
+#[doc = "one clear RTC GPIO output enable\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`enable_w1tc::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ENABLE_W1TC_SPEC;
+impl crate::RegisterSpec for ENABLE_W1TC_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [`enable_w1tc::W`](W) writer structure"]
+impl crate::Writable for ENABLE_W1TC_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets ENABLE_W1TC to value 0"]
+impl crate::Resettable for ENABLE_W1TC_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_io/ext_wakeup0.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `EXT_WAKEUP0` reader"]
+pub type R = crate::R<EXT_WAKEUP0_SPEC>;
+#[doc = "Register `EXT_WAKEUP0` writer"]
+pub type W = crate::W<EXT_WAKEUP0_SPEC>;
+#[doc = "Field `SEL` reader - ******* Description configure***"]
+pub type SEL_R = crate::FieldReader;
+#[doc = "Field `SEL` writer - ******* Description configure***"]
+pub type SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
+impl R {
+    #[doc = "Bits 27:31 - ******* Description configure***"]
+    #[inline(always)]
+    pub fn sel(&self) -> SEL_R {
+        SEL_R::new(((self.bits >> 27) & 0x1f) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("EXT_WAKEUP0")
+            .field("sel", &self.sel())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 27:31 - ******* Description configure***"]
+    #[inline(always)]
+    pub fn sel(&mut self) -> SEL_W<EXT_WAKEUP0_SPEC> {
+        SEL_W::new(self, 27)
+    }
+}
+#[doc = "configure EXT0 wakeup\n\nYou can [`read`](crate::Reg::read) this register and get [`ext_wakeup0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ext_wakeup0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct EXT_WAKEUP0_SPEC;
+impl crate::RegisterSpec for EXT_WAKEUP0_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`ext_wakeup0::R`](R) reader structure"]
+impl crate::Readable for EXT_WAKEUP0_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`ext_wakeup0::W`](W) writer structure"]
+impl crate::Writable for EXT_WAKEUP0_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets EXT_WAKEUP0 to value 0"]
+impl crate::Resettable for EXT_WAKEUP0_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_io/pad_dac1.rs

@@ -0,0 +1,212 @@
+#[doc = "Register `PAD_DAC1` reader"]
+pub type R = crate::R<PAD_DAC1_SPEC>;
+#[doc = "Register `PAD_DAC1` writer"]
+pub type W = crate::W<PAD_DAC1_SPEC>;
+#[doc = "Field `PDAC1_DAC` reader - PDAC1_DAC"]
+pub type PDAC1_DAC_R = crate::FieldReader;
+#[doc = "Field `PDAC1_DAC` writer - PDAC1_DAC"]
+pub type PDAC1_DAC_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+#[doc = "Field `PDAC1_XPD_DAC` reader - PDAC1_XPD_DAC"]
+pub type PDAC1_XPD_DAC_R = crate::BitReader;
+#[doc = "Field `PDAC1_XPD_DAC` writer - PDAC1_XPD_DAC"]
+pub type PDAC1_XPD_DAC_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PDAC1_DAC_XPD_FORCE` reader - 1: use reg_pdac1_xpd_dac to control PDAC1_XPD_DAC,0: use SAR ADC FSM to control PDAC1_XPD_DAC"]
+pub type PDAC1_DAC_XPD_FORCE_R = crate::BitReader;
+#[doc = "Field `PDAC1_DAC_XPD_FORCE` writer - 1: use reg_pdac1_xpd_dac to control PDAC1_XPD_DAC,0: use SAR ADC FSM to control PDAC1_XPD_DAC"]
+pub type PDAC1_DAC_XPD_FORCE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PDAC1_FUN_IE` reader - input enable in work mode"]
+pub type PDAC1_FUN_IE_R = crate::BitReader;
+#[doc = "Field `PDAC1_FUN_IE` writer - input enable in work mode"]
+pub type PDAC1_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PDAC1_SLP_OE` reader - output enable in sleep mode"]
+pub type PDAC1_SLP_OE_R = crate::BitReader;
+#[doc = "Field `PDAC1_SLP_OE` writer - output enable in sleep mode"]
+pub type PDAC1_SLP_OE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PDAC1_SLP_IE` reader - input enable in sleep mode"]
+pub type PDAC1_SLP_IE_R = crate::BitReader;
+#[doc = "Field `PDAC1_SLP_IE` writer - input enable in sleep mode"]
+pub type PDAC1_SLP_IE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PDAC1_SLP_SEL` reader - 1: enable sleep mode during sleep,0: no sleep mode"]
+pub type PDAC1_SLP_SEL_R = crate::BitReader;
+#[doc = "Field `PDAC1_SLP_SEL` writer - 1: enable sleep mode during sleep,0: no sleep mode"]
+pub type PDAC1_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PDAC1_FUN_SEL` reader - PDAC1 function sel"]
+pub type PDAC1_FUN_SEL_R = crate::FieldReader;
+#[doc = "Field `PDAC1_FUN_SEL` writer - PDAC1 function sel"]
+pub type PDAC1_FUN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `PDAC1_MUX_SEL` reader - 1: use RTC GPIO,0: use digital GPIO"]
+pub type PDAC1_MUX_SEL_R = crate::BitReader;
+#[doc = "Field `PDAC1_MUX_SEL` writer - 1: use RTC GPIO,0: use digital GPIO"]
+pub type PDAC1_MUX_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PDAC1_RUE` reader - PDAC1_RUE"]
+pub type PDAC1_RUE_R = crate::BitReader;
+#[doc = "Field `PDAC1_RUE` writer - PDAC1_RUE"]
+pub type PDAC1_RUE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PDAC1_RDE` reader - PDAC1_RDE"]
+pub type PDAC1_RDE_R = crate::BitReader;
+#[doc = "Field `PDAC1_RDE` writer - PDAC1_RDE"]
+pub type PDAC1_RDE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PDAC1_DRV` reader - PDAC1_DRV"]
+pub type PDAC1_DRV_R = crate::FieldReader;
+#[doc = "Field `PDAC1_DRV` writer - PDAC1_DRV"]
+pub type PDAC1_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+impl R {
+    #[doc = "Bits 3:10 - PDAC1_DAC"]
+    #[inline(always)]
+    pub fn pdac1_dac(&self) -> PDAC1_DAC_R {
+        PDAC1_DAC_R::new(((self.bits >> 3) & 0xff) as u8)
+    }
+    #[doc = "Bit 11 - PDAC1_XPD_DAC"]
+    #[inline(always)]
+    pub fn pdac1_xpd_dac(&self) -> PDAC1_XPD_DAC_R {
+        PDAC1_XPD_DAC_R::new(((self.bits >> 11) & 1) != 0)
+    }
+    #[doc = "Bit 12 - 1: use reg_pdac1_xpd_dac to control PDAC1_XPD_DAC,0: use SAR ADC FSM to control PDAC1_XPD_DAC"]
+    #[inline(always)]
+    pub fn pdac1_dac_xpd_force(&self) -> PDAC1_DAC_XPD_FORCE_R {
+        PDAC1_DAC_XPD_FORCE_R::new(((self.bits >> 12) & 1) != 0)
+    }
+    #[doc = "Bit 13 - input enable in work mode"]
+    #[inline(always)]
+    pub fn pdac1_fun_ie(&self) -> PDAC1_FUN_IE_R {
+        PDAC1_FUN_IE_R::new(((self.bits >> 13) & 1) != 0)
+    }
+    #[doc = "Bit 14 - output enable in sleep mode"]
+    #[inline(always)]
+    pub fn pdac1_slp_oe(&self) -> PDAC1_SLP_OE_R {
+        PDAC1_SLP_OE_R::new(((self.bits >> 14) & 1) != 0)
+    }
+    #[doc = "Bit 15 - input enable in sleep mode"]
+    #[inline(always)]
+    pub fn pdac1_slp_ie(&self) -> PDAC1_SLP_IE_R {
+        PDAC1_SLP_IE_R::new(((self.bits >> 15) & 1) != 0)
+    }
+    #[doc = "Bit 16 - 1: enable sleep mode during sleep,0: no sleep mode"]
+    #[inline(always)]
+    pub fn pdac1_slp_sel(&self) -> PDAC1_SLP_SEL_R {
+        PDAC1_SLP_SEL_R::new(((self.bits >> 16) & 1) != 0)
+    }
+    #[doc = "Bits 17:18 - PDAC1 function sel"]
+    #[inline(always)]
+    pub fn pdac1_fun_sel(&self) -> PDAC1_FUN_SEL_R {
+        PDAC1_FUN_SEL_R::new(((self.bits >> 17) & 3) as u8)
+    }
+    #[doc = "Bit 19 - 1: use RTC GPIO,0: use digital GPIO"]
+    #[inline(always)]
+    pub fn pdac1_mux_sel(&self) -> PDAC1_MUX_SEL_R {
+        PDAC1_MUX_SEL_R::new(((self.bits >> 19) & 1) != 0)
+    }
+    #[doc = "Bit 27 - PDAC1_RUE"]
+    #[inline(always)]
+    pub fn pdac1_rue(&self) -> PDAC1_RUE_R {
+        PDAC1_RUE_R::new(((self.bits >> 27) & 1) != 0)
+    }
+    #[doc = "Bit 28 - PDAC1_RDE"]
+    #[inline(always)]
+    pub fn pdac1_rde(&self) -> PDAC1_RDE_R {
+        PDAC1_RDE_R::new(((self.bits >> 28) & 1) != 0)
+    }
+    #[doc = "Bits 29:30 - PDAC1_DRV"]
+    #[inline(always)]
+    pub fn pdac1_drv(&self) -> PDAC1_DRV_R {
+        PDAC1_DRV_R::new(((self.bits >> 29) & 3) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("PAD_DAC1")
+            .field("pdac1_dac", &self.pdac1_dac())
+            .field("pdac1_xpd_dac", &self.pdac1_xpd_dac())
+            .field("pdac1_dac_xpd_force", &self.pdac1_dac_xpd_force())
+            .field("pdac1_fun_ie", &self.pdac1_fun_ie())
+            .field("pdac1_slp_oe", &self.pdac1_slp_oe())
+            .field("pdac1_slp_ie", &self.pdac1_slp_ie())
+            .field("pdac1_slp_sel", &self.pdac1_slp_sel())
+            .field("pdac1_fun_sel", &self.pdac1_fun_sel())
+            .field("pdac1_mux_sel", &self.pdac1_mux_sel())
+            .field("pdac1_rue", &self.pdac1_rue())
+            .field("pdac1_rde", &self.pdac1_rde())
+            .field("pdac1_drv", &self.pdac1_drv())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 3:10 - PDAC1_DAC"]
+    #[inline(always)]
+    pub fn pdac1_dac(&mut self) -> PDAC1_DAC_W<PAD_DAC1_SPEC> {
+        PDAC1_DAC_W::new(self, 3)
+    }
+    #[doc = "Bit 11 - PDAC1_XPD_DAC"]
+    #[inline(always)]
+    pub fn pdac1_xpd_dac(&mut self) -> PDAC1_XPD_DAC_W<PAD_DAC1_SPEC> {
+        PDAC1_XPD_DAC_W::new(self, 11)
+    }
+    #[doc = "Bit 12 - 1: use reg_pdac1_xpd_dac to control PDAC1_XPD_DAC,0: use SAR ADC FSM to control PDAC1_XPD_DAC"]
+    #[inline(always)]
+    pub fn pdac1_dac_xpd_force(&mut self) -> PDAC1_DAC_XPD_FORCE_W<PAD_DAC1_SPEC> {
+        PDAC1_DAC_XPD_FORCE_W::new(self, 12)
+    }
+    #[doc = "Bit 13 - input enable in work mode"]
+    #[inline(always)]
+    pub fn pdac1_fun_ie(&mut self) -> PDAC1_FUN_IE_W<PAD_DAC1_SPEC> {
+        PDAC1_FUN_IE_W::new(self, 13)
+    }
+    #[doc = "Bit 14 - output enable in sleep mode"]
+    #[inline(always)]
+    pub fn pdac1_slp_oe(&mut self) -> PDAC1_SLP_OE_W<PAD_DAC1_SPEC> {
+        PDAC1_SLP_OE_W::new(self, 14)
+    }
+    #[doc = "Bit 15 - input enable in sleep mode"]
+    #[inline(always)]
+    pub fn pdac1_slp_ie(&mut self) -> PDAC1_SLP_IE_W<PAD_DAC1_SPEC> {
+        PDAC1_SLP_IE_W::new(self, 15)
+    }
+    #[doc = "Bit 16 - 1: enable sleep mode during sleep,0: no sleep mode"]
+    #[inline(always)]
+    pub fn pdac1_slp_sel(&mut self) -> PDAC1_SLP_SEL_W<PAD_DAC1_SPEC> {
+        PDAC1_SLP_SEL_W::new(self, 16)
+    }
+    #[doc = "Bits 17:18 - PDAC1 function sel"]
+    #[inline(always)]
+    pub fn pdac1_fun_sel(&mut self) -> PDAC1_FUN_SEL_W<PAD_DAC1_SPEC> {
+        PDAC1_FUN_SEL_W::new(self, 17)
+    }
+    #[doc = "Bit 19 - 1: use RTC GPIO,0: use digital GPIO"]
+    #[inline(always)]
+    pub fn pdac1_mux_sel(&mut self) -> PDAC1_MUX_SEL_W<PAD_DAC1_SPEC> {
+        PDAC1_MUX_SEL_W::new(self, 19)
+    }
+    #[doc = "Bit 27 - PDAC1_RUE"]
+    #[inline(always)]
+    pub fn pdac1_rue(&mut self) -> PDAC1_RUE_W<PAD_DAC1_SPEC> {
+        PDAC1_RUE_W::new(self, 27)
+    }
+    #[doc = "Bit 28 - PDAC1_RDE"]
+    #[inline(always)]
+    pub fn pdac1_rde(&mut self) -> PDAC1_RDE_W<PAD_DAC1_SPEC> {
+        PDAC1_RDE_W::new(self, 28)
+    }
+    #[doc = "Bits 29:30 - PDAC1_DRV"]
+    #[inline(always)]
+    pub fn pdac1_drv(&mut self) -> PDAC1_DRV_W<PAD_DAC1_SPEC> {
+        PDAC1_DRV_W::new(self, 29)
+    }
+}
+#[doc = "configure RTC PAD17\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_dac1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_dac1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct PAD_DAC1_SPEC;
+impl crate::RegisterSpec for PAD_DAC1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`pad_dac1::R`](R) reader structure"]
+impl crate::Readable for PAD_DAC1_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`pad_dac1::W`](W) writer structure"]
+impl crate::Writable for PAD_DAC1_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets PAD_DAC1 to value 0x4000_0000"]
+impl crate::Resettable for PAD_DAC1_SPEC {
+    const RESET_VALUE: u32 = 0x4000_0000;
+}

vendor/esp32s3/src/rtc_io/pad_dac2.rs

@@ -0,0 +1,212 @@
+#[doc = "Register `PAD_DAC2` reader"]
+pub type R = crate::R<PAD_DAC2_SPEC>;
+#[doc = "Register `PAD_DAC2` writer"]
+pub type W = crate::W<PAD_DAC2_SPEC>;
+#[doc = "Field `PDAC2_DAC` reader - PDAC2_DAC"]
+pub type PDAC2_DAC_R = crate::FieldReader;
+#[doc = "Field `PDAC2_DAC` writer - PDAC2_DAC"]
+pub type PDAC2_DAC_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+#[doc = "Field `PDAC2_XPD_DAC` reader - PDAC2_XPD_DAC"]
+pub type PDAC2_XPD_DAC_R = crate::BitReader;
+#[doc = "Field `PDAC2_XPD_DAC` writer - PDAC2_XPD_DAC"]
+pub type PDAC2_XPD_DAC_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PDAC2_DAC_XPD_FORCE` reader - 1: use reg_pdac2_xpd_dac to control PDAC2_XPD_DAC,0: use SAR ADC FSM to control PDAC2_XPD_DAC"]
+pub type PDAC2_DAC_XPD_FORCE_R = crate::BitReader;
+#[doc = "Field `PDAC2_DAC_XPD_FORCE` writer - 1: use reg_pdac2_xpd_dac to control PDAC2_XPD_DAC,0: use SAR ADC FSM to control PDAC2_XPD_DAC"]
+pub type PDAC2_DAC_XPD_FORCE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PDAC2_FUN_IE` reader - input enable in work mode"]
+pub type PDAC2_FUN_IE_R = crate::BitReader;
+#[doc = "Field `PDAC2_FUN_IE` writer - input enable in work mode"]
+pub type PDAC2_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PDAC2_SLP_OE` reader - output enable in sleep mode"]
+pub type PDAC2_SLP_OE_R = crate::BitReader;
+#[doc = "Field `PDAC2_SLP_OE` writer - output enable in sleep mode"]
+pub type PDAC2_SLP_OE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PDAC2_SLP_IE` reader - input enable in sleep mode"]
+pub type PDAC2_SLP_IE_R = crate::BitReader;
+#[doc = "Field `PDAC2_SLP_IE` writer - input enable in sleep mode"]
+pub type PDAC2_SLP_IE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PDAC2_SLP_SEL` reader - 1: enable sleep mode during sleep,0: no sleep mode"]
+pub type PDAC2_SLP_SEL_R = crate::BitReader;
+#[doc = "Field `PDAC2_SLP_SEL` writer - 1: enable sleep mode during sleep,0: no sleep mode"]
+pub type PDAC2_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PDAC2_FUN_SEL` reader - PDAC1 function sel"]
+pub type PDAC2_FUN_SEL_R = crate::FieldReader;
+#[doc = "Field `PDAC2_FUN_SEL` writer - PDAC1 function sel"]
+pub type PDAC2_FUN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `PDAC2_MUX_SEL` reader - 1: use RTC GPIO,0: use digital GPIO"]
+pub type PDAC2_MUX_SEL_R = crate::BitReader;
+#[doc = "Field `PDAC2_MUX_SEL` writer - 1: use RTC GPIO,0: use digital GPIO"]
+pub type PDAC2_MUX_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PDAC2_RUE` reader - PDAC2_RUE"]
+pub type PDAC2_RUE_R = crate::BitReader;
+#[doc = "Field `PDAC2_RUE` writer - PDAC2_RUE"]
+pub type PDAC2_RUE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PDAC2_RDE` reader - PDAC2_RDE"]
+pub type PDAC2_RDE_R = crate::BitReader;
+#[doc = "Field `PDAC2_RDE` writer - PDAC2_RDE"]
+pub type PDAC2_RDE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PDAC2_DRV` reader - PDAC2_DRV"]
+pub type PDAC2_DRV_R = crate::FieldReader;
+#[doc = "Field `PDAC2_DRV` writer - PDAC2_DRV"]
+pub type PDAC2_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+impl R {
+    #[doc = "Bits 3:10 - PDAC2_DAC"]
+    #[inline(always)]
+    pub fn pdac2_dac(&self) -> PDAC2_DAC_R {
+        PDAC2_DAC_R::new(((self.bits >> 3) & 0xff) as u8)
+    }
+    #[doc = "Bit 11 - PDAC2_XPD_DAC"]
+    #[inline(always)]
+    pub fn pdac2_xpd_dac(&self) -> PDAC2_XPD_DAC_R {
+        PDAC2_XPD_DAC_R::new(((self.bits >> 11) & 1) != 0)
+    }
+    #[doc = "Bit 12 - 1: use reg_pdac2_xpd_dac to control PDAC2_XPD_DAC,0: use SAR ADC FSM to control PDAC2_XPD_DAC"]
+    #[inline(always)]
+    pub fn pdac2_dac_xpd_force(&self) -> PDAC2_DAC_XPD_FORCE_R {
+        PDAC2_DAC_XPD_FORCE_R::new(((self.bits >> 12) & 1) != 0)
+    }
+    #[doc = "Bit 13 - input enable in work mode"]
+    #[inline(always)]
+    pub fn pdac2_fun_ie(&self) -> PDAC2_FUN_IE_R {
+        PDAC2_FUN_IE_R::new(((self.bits >> 13) & 1) != 0)
+    }
+    #[doc = "Bit 14 - output enable in sleep mode"]
+    #[inline(always)]
+    pub fn pdac2_slp_oe(&self) -> PDAC2_SLP_OE_R {
+        PDAC2_SLP_OE_R::new(((self.bits >> 14) & 1) != 0)
+    }
+    #[doc = "Bit 15 - input enable in sleep mode"]
+    #[inline(always)]
+    pub fn pdac2_slp_ie(&self) -> PDAC2_SLP_IE_R {
+        PDAC2_SLP_IE_R::new(((self.bits >> 15) & 1) != 0)
+    }
+    #[doc = "Bit 16 - 1: enable sleep mode during sleep,0: no sleep mode"]
+    #[inline(always)]
+    pub fn pdac2_slp_sel(&self) -> PDAC2_SLP_SEL_R {
+        PDAC2_SLP_SEL_R::new(((self.bits >> 16) & 1) != 0)
+    }
+    #[doc = "Bits 17:18 - PDAC1 function sel"]
+    #[inline(always)]
+    pub fn pdac2_fun_sel(&self) -> PDAC2_FUN_SEL_R {
+        PDAC2_FUN_SEL_R::new(((self.bits >> 17) & 3) as u8)
+    }
+    #[doc = "Bit 19 - 1: use RTC GPIO,0: use digital GPIO"]
+    #[inline(always)]
+    pub fn pdac2_mux_sel(&self) -> PDAC2_MUX_SEL_R {
+        PDAC2_MUX_SEL_R::new(((self.bits >> 19) & 1) != 0)
+    }
+    #[doc = "Bit 27 - PDAC2_RUE"]
+    #[inline(always)]
+    pub fn pdac2_rue(&self) -> PDAC2_RUE_R {
+        PDAC2_RUE_R::new(((self.bits >> 27) & 1) != 0)
+    }
+    #[doc = "Bit 28 - PDAC2_RDE"]
+    #[inline(always)]
+    pub fn pdac2_rde(&self) -> PDAC2_RDE_R {
+        PDAC2_RDE_R::new(((self.bits >> 28) & 1) != 0)
+    }
+    #[doc = "Bits 29:30 - PDAC2_DRV"]
+    #[inline(always)]
+    pub fn pdac2_drv(&self) -> PDAC2_DRV_R {
+        PDAC2_DRV_R::new(((self.bits >> 29) & 3) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("PAD_DAC2")
+            .field("pdac2_dac", &self.pdac2_dac())
+            .field("pdac2_xpd_dac", &self.pdac2_xpd_dac())
+            .field("pdac2_dac_xpd_force", &self.pdac2_dac_xpd_force())
+            .field("pdac2_fun_ie", &self.pdac2_fun_ie())
+            .field("pdac2_slp_oe", &self.pdac2_slp_oe())
+            .field("pdac2_slp_ie", &self.pdac2_slp_ie())
+            .field("pdac2_slp_sel", &self.pdac2_slp_sel())
+            .field("pdac2_fun_sel", &self.pdac2_fun_sel())
+            .field("pdac2_mux_sel", &self.pdac2_mux_sel())
+            .field("pdac2_rue", &self.pdac2_rue())
+            .field("pdac2_rde", &self.pdac2_rde())
+            .field("pdac2_drv", &self.pdac2_drv())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 3:10 - PDAC2_DAC"]
+    #[inline(always)]
+    pub fn pdac2_dac(&mut self) -> PDAC2_DAC_W<PAD_DAC2_SPEC> {
+        PDAC2_DAC_W::new(self, 3)
+    }
+    #[doc = "Bit 11 - PDAC2_XPD_DAC"]
+    #[inline(always)]
+    pub fn pdac2_xpd_dac(&mut self) -> PDAC2_XPD_DAC_W<PAD_DAC2_SPEC> {
+        PDAC2_XPD_DAC_W::new(self, 11)
+    }
+    #[doc = "Bit 12 - 1: use reg_pdac2_xpd_dac to control PDAC2_XPD_DAC,0: use SAR ADC FSM to control PDAC2_XPD_DAC"]
+    #[inline(always)]
+    pub fn pdac2_dac_xpd_force(&mut self) -> PDAC2_DAC_XPD_FORCE_W<PAD_DAC2_SPEC> {
+        PDAC2_DAC_XPD_FORCE_W::new(self, 12)
+    }
+    #[doc = "Bit 13 - input enable in work mode"]
+    #[inline(always)]
+    pub fn pdac2_fun_ie(&mut self) -> PDAC2_FUN_IE_W<PAD_DAC2_SPEC> {
+        PDAC2_FUN_IE_W::new(self, 13)
+    }
+    #[doc = "Bit 14 - output enable in sleep mode"]
+    #[inline(always)]
+    pub fn pdac2_slp_oe(&mut self) -> PDAC2_SLP_OE_W<PAD_DAC2_SPEC> {
+        PDAC2_SLP_OE_W::new(self, 14)
+    }
+    #[doc = "Bit 15 - input enable in sleep mode"]
+    #[inline(always)]
+    pub fn pdac2_slp_ie(&mut self) -> PDAC2_SLP_IE_W<PAD_DAC2_SPEC> {
+        PDAC2_SLP_IE_W::new(self, 15)
+    }
+    #[doc = "Bit 16 - 1: enable sleep mode during sleep,0: no sleep mode"]
+    #[inline(always)]
+    pub fn pdac2_slp_sel(&mut self) -> PDAC2_SLP_SEL_W<PAD_DAC2_SPEC> {
+        PDAC2_SLP_SEL_W::new(self, 16)
+    }
+    #[doc = "Bits 17:18 - PDAC1 function sel"]
+    #[inline(always)]
+    pub fn pdac2_fun_sel(&mut self) -> PDAC2_FUN_SEL_W<PAD_DAC2_SPEC> {
+        PDAC2_FUN_SEL_W::new(self, 17)
+    }
+    #[doc = "Bit 19 - 1: use RTC GPIO,0: use digital GPIO"]
+    #[inline(always)]
+    pub fn pdac2_mux_sel(&mut self) -> PDAC2_MUX_SEL_W<PAD_DAC2_SPEC> {
+        PDAC2_MUX_SEL_W::new(self, 19)
+    }
+    #[doc = "Bit 27 - PDAC2_RUE"]
+    #[inline(always)]
+    pub fn pdac2_rue(&mut self) -> PDAC2_RUE_W<PAD_DAC2_SPEC> {
+        PDAC2_RUE_W::new(self, 27)
+    }
+    #[doc = "Bit 28 - PDAC2_RDE"]
+    #[inline(always)]
+    pub fn pdac2_rde(&mut self) -> PDAC2_RDE_W<PAD_DAC2_SPEC> {
+        PDAC2_RDE_W::new(self, 28)
+    }
+    #[doc = "Bits 29:30 - PDAC2_DRV"]
+    #[inline(always)]
+    pub fn pdac2_drv(&mut self) -> PDAC2_DRV_W<PAD_DAC2_SPEC> {
+        PDAC2_DRV_W::new(self, 29)
+    }
+}
+#[doc = "configure RTC PAD18\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_dac2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_dac2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct PAD_DAC2_SPEC;
+impl crate::RegisterSpec for PAD_DAC2_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`pad_dac2::R`](R) reader structure"]
+impl crate::Readable for PAD_DAC2_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`pad_dac2::W`](W) writer structure"]
+impl crate::Writable for PAD_DAC2_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets PAD_DAC2 to value 0x4000_0000"]
+impl crate::Resettable for PAD_DAC2_SPEC {
+    const RESET_VALUE: u32 = 0x4000_0000;
+}

vendor/esp32s3/src/rtc_io/pin.rs

@@ -0,0 +1,77 @@
+#[doc = "Register `PIN%s` reader"]
+pub type R = crate::R<PIN_SPEC>;
+#[doc = "Register `PIN%s` writer"]
+pub type W = crate::W<PIN_SPEC>;
+#[doc = "Field `PAD_DRIVER` reader - if set to 0: normal output, if set to 1: open drain"]
+pub type PAD_DRIVER_R = crate::BitReader;
+#[doc = "Field `PAD_DRIVER` writer - if set to 0: normal output, if set to 1: open drain"]
+pub type PAD_DRIVER_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `INT_TYPE` reader - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"]
+pub type INT_TYPE_R = crate::FieldReader;
+#[doc = "Field `INT_TYPE` writer - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"]
+pub type INT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `WAKEUP_ENABLE` reader - RTC GPIO wakeup enable bit"]
+pub type WAKEUP_ENABLE_R = crate::BitReader;
+#[doc = "Field `WAKEUP_ENABLE` writer - RTC GPIO wakeup enable bit"]
+pub type WAKEUP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"]
+    #[inline(always)]
+    pub fn pad_driver(&self) -> PAD_DRIVER_R {
+        PAD_DRIVER_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bits 7:9 - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"]
+    #[inline(always)]
+    pub fn int_type(&self) -> INT_TYPE_R {
+        INT_TYPE_R::new(((self.bits >> 7) & 7) as u8)
+    }
+    #[doc = "Bit 10 - RTC GPIO wakeup enable bit"]
+    #[inline(always)]
+    pub fn wakeup_enable(&self) -> WAKEUP_ENABLE_R {
+        WAKEUP_ENABLE_R::new(((self.bits >> 10) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("PIN")
+            .field("pad_driver", &self.pad_driver())
+            .field("int_type", &self.int_type())
+            .field("wakeup_enable", &self.wakeup_enable())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"]
+    #[inline(always)]
+    pub fn pad_driver(&mut self) -> PAD_DRIVER_W<PIN_SPEC> {
+        PAD_DRIVER_W::new(self, 2)
+    }
+    #[doc = "Bits 7:9 - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"]
+    #[inline(always)]
+    pub fn int_type(&mut self) -> INT_TYPE_W<PIN_SPEC> {
+        INT_TYPE_W::new(self, 7)
+    }
+    #[doc = "Bit 10 - RTC GPIO wakeup enable bit"]
+    #[inline(always)]
+    pub fn wakeup_enable(&mut self) -> WAKEUP_ENABLE_W<PIN_SPEC> {
+        WAKEUP_ENABLE_W::new(self, 10)
+    }
+}
+#[doc = "configure RTC GPIO%s\n\nYou can [`read`](crate::Reg::read) this register and get [`pin::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pin::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct PIN_SPEC;
+impl crate::RegisterSpec for PIN_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`pin::R`](R) reader structure"]
+impl crate::Readable for PIN_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`pin::W`](W) writer structure"]
+impl crate::Writable for PIN_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets PIN%s to value 0"]
+impl crate::Resettable for PIN_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_io/rtc_debug_sel.rs

@@ -0,0 +1,122 @@
+#[doc = "Register `RTC_DEBUG_SEL` reader"]
+pub type R = crate::R<RTC_DEBUG_SEL_SPEC>;
+#[doc = "Register `RTC_DEBUG_SEL` writer"]
+pub type W = crate::W<RTC_DEBUG_SEL_SPEC>;
+#[doc = "Field `RTC_DEBUG_SEL0` reader - configure rtc debug"]
+pub type RTC_DEBUG_SEL0_R = crate::FieldReader;
+#[doc = "Field `RTC_DEBUG_SEL0` writer - configure rtc debug"]
+pub type RTC_DEBUG_SEL0_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
+#[doc = "Field `RTC_DEBUG_SEL1` reader - configure rtc debug"]
+pub type RTC_DEBUG_SEL1_R = crate::FieldReader;
+#[doc = "Field `RTC_DEBUG_SEL1` writer - configure rtc debug"]
+pub type RTC_DEBUG_SEL1_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
+#[doc = "Field `RTC_DEBUG_SEL2` reader - configure rtc debug"]
+pub type RTC_DEBUG_SEL2_R = crate::FieldReader;
+#[doc = "Field `RTC_DEBUG_SEL2` writer - configure rtc debug"]
+pub type RTC_DEBUG_SEL2_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
+#[doc = "Field `RTC_DEBUG_SEL3` reader - configure rtc debug"]
+pub type RTC_DEBUG_SEL3_R = crate::FieldReader;
+#[doc = "Field `RTC_DEBUG_SEL3` writer - configure rtc debug"]
+pub type RTC_DEBUG_SEL3_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
+#[doc = "Field `RTC_DEBUG_SEL4` reader - configure rtc debug"]
+pub type RTC_DEBUG_SEL4_R = crate::FieldReader;
+#[doc = "Field `RTC_DEBUG_SEL4` writer - configure rtc debug"]
+pub type RTC_DEBUG_SEL4_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
+#[doc = "Field `RTC_DEBUG_12M_NO_GATING` reader - configure rtc debug"]
+pub type RTC_DEBUG_12M_NO_GATING_R = crate::BitReader;
+#[doc = "Field `RTC_DEBUG_12M_NO_GATING` writer - configure rtc debug"]
+pub type RTC_DEBUG_12M_NO_GATING_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 0:4 - configure rtc debug"]
+    #[inline(always)]
+    pub fn rtc_debug_sel0(&self) -> RTC_DEBUG_SEL0_R {
+        RTC_DEBUG_SEL0_R::new((self.bits & 0x1f) as u8)
+    }
+    #[doc = "Bits 5:9 - configure rtc debug"]
+    #[inline(always)]
+    pub fn rtc_debug_sel1(&self) -> RTC_DEBUG_SEL1_R {
+        RTC_DEBUG_SEL1_R::new(((self.bits >> 5) & 0x1f) as u8)
+    }
+    #[doc = "Bits 10:14 - configure rtc debug"]
+    #[inline(always)]
+    pub fn rtc_debug_sel2(&self) -> RTC_DEBUG_SEL2_R {
+        RTC_DEBUG_SEL2_R::new(((self.bits >> 10) & 0x1f) as u8)
+    }
+    #[doc = "Bits 15:19 - configure rtc debug"]
+    #[inline(always)]
+    pub fn rtc_debug_sel3(&self) -> RTC_DEBUG_SEL3_R {
+        RTC_DEBUG_SEL3_R::new(((self.bits >> 15) & 0x1f) as u8)
+    }
+    #[doc = "Bits 20:24 - configure rtc debug"]
+    #[inline(always)]
+    pub fn rtc_debug_sel4(&self) -> RTC_DEBUG_SEL4_R {
+        RTC_DEBUG_SEL4_R::new(((self.bits >> 20) & 0x1f) as u8)
+    }
+    #[doc = "Bit 25 - configure rtc debug"]
+    #[inline(always)]
+    pub fn rtc_debug_12m_no_gating(&self) -> RTC_DEBUG_12M_NO_GATING_R {
+        RTC_DEBUG_12M_NO_GATING_R::new(((self.bits >> 25) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("RTC_DEBUG_SEL")
+            .field("rtc_debug_sel0", &self.rtc_debug_sel0())
+            .field("rtc_debug_sel1", &self.rtc_debug_sel1())
+            .field("rtc_debug_sel2", &self.rtc_debug_sel2())
+            .field("rtc_debug_sel3", &self.rtc_debug_sel3())
+            .field("rtc_debug_sel4", &self.rtc_debug_sel4())
+            .field("rtc_debug_12m_no_gating", &self.rtc_debug_12m_no_gating())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:4 - configure rtc debug"]
+    #[inline(always)]
+    pub fn rtc_debug_sel0(&mut self) -> RTC_DEBUG_SEL0_W<RTC_DEBUG_SEL_SPEC> {
+        RTC_DEBUG_SEL0_W::new(self, 0)
+    }
+    #[doc = "Bits 5:9 - configure rtc debug"]
+    #[inline(always)]
+    pub fn rtc_debug_sel1(&mut self) -> RTC_DEBUG_SEL1_W<RTC_DEBUG_SEL_SPEC> {
+        RTC_DEBUG_SEL1_W::new(self, 5)
+    }
+    #[doc = "Bits 10:14 - configure rtc debug"]
+    #[inline(always)]
+    pub fn rtc_debug_sel2(&mut self) -> RTC_DEBUG_SEL2_W<RTC_DEBUG_SEL_SPEC> {
+        RTC_DEBUG_SEL2_W::new(self, 10)
+    }
+    #[doc = "Bits 15:19 - configure rtc debug"]
+    #[inline(always)]
+    pub fn rtc_debug_sel3(&mut self) -> RTC_DEBUG_SEL3_W<RTC_DEBUG_SEL_SPEC> {
+        RTC_DEBUG_SEL3_W::new(self, 15)
+    }
+    #[doc = "Bits 20:24 - configure rtc debug"]
+    #[inline(always)]
+    pub fn rtc_debug_sel4(&mut self) -> RTC_DEBUG_SEL4_W<RTC_DEBUG_SEL_SPEC> {
+        RTC_DEBUG_SEL4_W::new(self, 20)
+    }
+    #[doc = "Bit 25 - configure rtc debug"]
+    #[inline(always)]
+    pub fn rtc_debug_12m_no_gating(&mut self) -> RTC_DEBUG_12M_NO_GATING_W<RTC_DEBUG_SEL_SPEC> {
+        RTC_DEBUG_12M_NO_GATING_W::new(self, 25)
+    }
+}
+#[doc = "configure rtc debug\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_debug_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_debug_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct RTC_DEBUG_SEL_SPEC;
+impl crate::RegisterSpec for RTC_DEBUG_SEL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`rtc_debug_sel::R`](R) reader structure"]
+impl crate::Readable for RTC_DEBUG_SEL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`rtc_debug_sel::W`](W) writer structure"]
+impl crate::Writable for RTC_DEBUG_SEL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets RTC_DEBUG_SEL to value 0"]
+impl crate::Resettable for RTC_DEBUG_SEL_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_io/rtc_gpio_enable.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `RTC_GPIO_ENABLE` reader"]
+pub type R = crate::R<RTC_GPIO_ENABLE_SPEC>;
+#[doc = "Register `RTC_GPIO_ENABLE` writer"]
+pub type W = crate::W<RTC_GPIO_ENABLE_SPEC>;
+#[doc = "Field `RTC_GPIO_ENABLE` reader - RTC GPIO 0 ~ 21 enable"]
+pub type RTC_GPIO_ENABLE_R = crate::FieldReader<u32>;
+#[doc = "Field `RTC_GPIO_ENABLE` writer - RTC GPIO 0 ~ 21 enable"]
+pub type RTC_GPIO_ENABLE_W<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>;
+impl R {
+    #[doc = "Bits 10:31 - RTC GPIO 0 ~ 21 enable"]
+    #[inline(always)]
+    pub fn rtc_gpio_enable(&self) -> RTC_GPIO_ENABLE_R {
+        RTC_GPIO_ENABLE_R::new((self.bits >> 10) & 0x003f_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("RTC_GPIO_ENABLE")
+            .field("rtc_gpio_enable", &self.rtc_gpio_enable())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 10:31 - RTC GPIO 0 ~ 21 enable"]
+    #[inline(always)]
+    pub fn rtc_gpio_enable(&mut self) -> RTC_GPIO_ENABLE_W<RTC_GPIO_ENABLE_SPEC> {
+        RTC_GPIO_ENABLE_W::new(self, 10)
+    }
+}
+#[doc = "Configure RTC GPIO output enable\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_gpio_enable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_gpio_enable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct RTC_GPIO_ENABLE_SPEC;
+impl crate::RegisterSpec for RTC_GPIO_ENABLE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`rtc_gpio_enable::R`](R) reader structure"]
+impl crate::Readable for RTC_GPIO_ENABLE_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`rtc_gpio_enable::W`](W) writer structure"]
+impl crate::Writable for RTC_GPIO_ENABLE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets RTC_GPIO_ENABLE to value 0"]
+impl crate::Resettable for RTC_GPIO_ENABLE_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_io/rtc_gpio_enable_w1ts.rs

@@ -0,0 +1,32 @@
+#[doc = "Register `RTC_GPIO_ENABLE_W1TS` writer"]
+pub type W = crate::W<RTC_GPIO_ENABLE_W1TS_SPEC>;
+#[doc = "Field `RTC_GPIO_ENABLE_W1TS` writer - RTC GPIO 0 ~ 21 enable write 1 to set"]
+pub type RTC_GPIO_ENABLE_W1TS_W<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>;
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for crate::generic::Reg<RTC_GPIO_ENABLE_W1TS_SPEC> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "(not readable)")
+    }
+}
+impl W {
+    #[doc = "Bits 10:31 - RTC GPIO 0 ~ 21 enable write 1 to set"]
+    #[inline(always)]
+    pub fn rtc_gpio_enable_w1ts(&mut self) -> RTC_GPIO_ENABLE_W1TS_W<RTC_GPIO_ENABLE_W1TS_SPEC> {
+        RTC_GPIO_ENABLE_W1TS_W::new(self, 10)
+    }
+}
+#[doc = "one set RTC GPIO output enable\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_gpio_enable_w1ts::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct RTC_GPIO_ENABLE_W1TS_SPEC;
+impl crate::RegisterSpec for RTC_GPIO_ENABLE_W1TS_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [`rtc_gpio_enable_w1ts::W`](W) writer structure"]
+impl crate::Writable for RTC_GPIO_ENABLE_W1TS_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets RTC_GPIO_ENABLE_W1TS to value 0"]
+impl crate::Resettable for RTC_GPIO_ENABLE_W1TS_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_io/rtc_gpio_in.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `RTC_GPIO_IN` reader"]
+pub type R = crate::R<RTC_GPIO_IN_SPEC>;
+#[doc = "Field `NEXT` reader - RTC GPIO input data"]
+pub type NEXT_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 10:31 - RTC GPIO input data"]
+    #[inline(always)]
+    pub fn next(&self) -> NEXT_R {
+        NEXT_R::new((self.bits >> 10) & 0x003f_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("RTC_GPIO_IN")
+            .field("next", &self.next())
+            .finish()
+    }
+}
+#[doc = "RTC GPIO input data\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_gpio_in::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct RTC_GPIO_IN_SPEC;
+impl crate::RegisterSpec for RTC_GPIO_IN_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`rtc_gpio_in::R`](R) reader structure"]
+impl crate::Readable for RTC_GPIO_IN_SPEC {}
+#[doc = "`reset()` method sets RTC_GPIO_IN to value 0"]
+impl crate::Resettable for RTC_GPIO_IN_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_io/rtc_gpio_out.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `RTC_GPIO_OUT` reader"]
+pub type R = crate::R<RTC_GPIO_OUT_SPEC>;
+#[doc = "Register `RTC_GPIO_OUT` writer"]
+pub type W = crate::W<RTC_GPIO_OUT_SPEC>;
+#[doc = "Field `DATA` reader - RTC GPIO 0 ~ 21 output data"]
+pub type DATA_R = crate::FieldReader<u32>;
+#[doc = "Field `DATA` writer - RTC GPIO 0 ~ 21 output data"]
+pub type DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>;
+impl R {
+    #[doc = "Bits 10:31 - RTC GPIO 0 ~ 21 output data"]
+    #[inline(always)]
+    pub fn data(&self) -> DATA_R {
+        DATA_R::new((self.bits >> 10) & 0x003f_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("RTC_GPIO_OUT")
+            .field("data", &self.data())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 10:31 - RTC GPIO 0 ~ 21 output data"]
+    #[inline(always)]
+    pub fn data(&mut self) -> DATA_W<RTC_GPIO_OUT_SPEC> {
+        DATA_W::new(self, 10)
+    }
+}
+#[doc = "RTC GPIO 0 ~ 21 output data register\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_gpio_out::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_gpio_out::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct RTC_GPIO_OUT_SPEC;
+impl crate::RegisterSpec for RTC_GPIO_OUT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`rtc_gpio_out::R`](R) reader structure"]
+impl crate::Readable for RTC_GPIO_OUT_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`rtc_gpio_out::W`](W) writer structure"]
+impl crate::Writable for RTC_GPIO_OUT_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets RTC_GPIO_OUT to value 0"]
+impl crate::Resettable for RTC_GPIO_OUT_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_io/rtc_gpio_out_w1tc.rs

@@ -0,0 +1,32 @@
+#[doc = "Register `RTC_GPIO_OUT_W1TC` writer"]
+pub type W = crate::W<RTC_GPIO_OUT_W1TC_SPEC>;
+#[doc = "Field `RTC_GPIO_OUT_DATA_W1TC` writer - RTC GPIO 0 ~ 21 output data write 1 to clear"]
+pub type RTC_GPIO_OUT_DATA_W1TC_W<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>;
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for crate::generic::Reg<RTC_GPIO_OUT_W1TC_SPEC> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "(not readable)")
+    }
+}
+impl W {
+    #[doc = "Bits 10:31 - RTC GPIO 0 ~ 21 output data write 1 to clear"]
+    #[inline(always)]
+    pub fn rtc_gpio_out_data_w1tc(&mut self) -> RTC_GPIO_OUT_DATA_W1TC_W<RTC_GPIO_OUT_W1TC_SPEC> {
+        RTC_GPIO_OUT_DATA_W1TC_W::new(self, 10)
+    }
+}
+#[doc = "one clear RTC GPIO output data\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_gpio_out_w1tc::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct RTC_GPIO_OUT_W1TC_SPEC;
+impl crate::RegisterSpec for RTC_GPIO_OUT_W1TC_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [`rtc_gpio_out_w1tc::W`](W) writer structure"]
+impl crate::Writable for RTC_GPIO_OUT_W1TC_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets RTC_GPIO_OUT_W1TC to value 0"]
+impl crate::Resettable for RTC_GPIO_OUT_W1TC_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_io/rtc_gpio_out_w1ts.rs

@@ -0,0 +1,32 @@
+#[doc = "Register `RTC_GPIO_OUT_W1TS` writer"]
+pub type W = crate::W<RTC_GPIO_OUT_W1TS_SPEC>;
+#[doc = "Field `RTC_GPIO_OUT_DATA_W1TS` writer - RTC GPIO 0 ~ 21 output data write 1 to set"]
+pub type RTC_GPIO_OUT_DATA_W1TS_W<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>;
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for crate::generic::Reg<RTC_GPIO_OUT_W1TS_SPEC> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "(not readable)")
+    }
+}
+impl W {
+    #[doc = "Bits 10:31 - RTC GPIO 0 ~ 21 output data write 1 to set"]
+    #[inline(always)]
+    pub fn rtc_gpio_out_data_w1ts(&mut self) -> RTC_GPIO_OUT_DATA_W1TS_W<RTC_GPIO_OUT_W1TS_SPEC> {
+        RTC_GPIO_OUT_DATA_W1TS_W::new(self, 10)
+    }
+}
+#[doc = "one set RTC GPIO output data\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_gpio_out_w1ts::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct RTC_GPIO_OUT_W1TS_SPEC;
+impl crate::RegisterSpec for RTC_GPIO_OUT_W1TS_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [`rtc_gpio_out_w1ts::W`](W) writer structure"]
+impl crate::Writable for RTC_GPIO_OUT_W1TS_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets RTC_GPIO_OUT_W1TS to value 0"]
+impl crate::Resettable for RTC_GPIO_OUT_W1TS_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_io/rtc_gpio_status.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `RTC_GPIO_STATUS` reader"]
+pub type R = crate::R<RTC_GPIO_STATUS_SPEC>;
+#[doc = "Register `RTC_GPIO_STATUS` writer"]
+pub type W = crate::W<RTC_GPIO_STATUS_SPEC>;
+#[doc = "Field `INT` reader - RTC GPIO 0 ~ 21 interrupt status"]
+pub type INT_R = crate::FieldReader<u32>;
+#[doc = "Field `INT` writer - RTC GPIO 0 ~ 21 interrupt status"]
+pub type INT_W<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>;
+impl R {
+    #[doc = "Bits 10:31 - RTC GPIO 0 ~ 21 interrupt status"]
+    #[inline(always)]
+    pub fn int(&self) -> INT_R {
+        INT_R::new((self.bits >> 10) & 0x003f_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("RTC_GPIO_STATUS")
+            .field("int", &self.int())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 10:31 - RTC GPIO 0 ~ 21 interrupt status"]
+    #[inline(always)]
+    pub fn int(&mut self) -> INT_W<RTC_GPIO_STATUS_SPEC> {
+        INT_W::new(self, 10)
+    }
+}
+#[doc = "RTC GPIO 0 ~ 21 interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_gpio_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_gpio_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct RTC_GPIO_STATUS_SPEC;
+impl crate::RegisterSpec for RTC_GPIO_STATUS_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`rtc_gpio_status::R`](R) reader structure"]
+impl crate::Readable for RTC_GPIO_STATUS_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`rtc_gpio_status::W`](W) writer structure"]
+impl crate::Writable for RTC_GPIO_STATUS_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets RTC_GPIO_STATUS to value 0"]
+impl crate::Resettable for RTC_GPIO_STATUS_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_io/rtc_gpio_status_w1tc.rs

@@ -0,0 +1,34 @@
+#[doc = "Register `RTC_GPIO_STATUS_W1TC` writer"]
+pub type W = crate::W<RTC_GPIO_STATUS_W1TC_SPEC>;
+#[doc = "Field `RTC_GPIO_STATUS_INT_W1TC` writer - RTC GPIO 0 ~ 21 interrupt status write 1 to clear"]
+pub type RTC_GPIO_STATUS_INT_W1TC_W<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>;
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for crate::generic::Reg<RTC_GPIO_STATUS_W1TC_SPEC> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "(not readable)")
+    }
+}
+impl W {
+    #[doc = "Bits 10:31 - RTC GPIO 0 ~ 21 interrupt status write 1 to clear"]
+    #[inline(always)]
+    pub fn rtc_gpio_status_int_w1tc(
+        &mut self,
+    ) -> RTC_GPIO_STATUS_INT_W1TC_W<RTC_GPIO_STATUS_W1TC_SPEC> {
+        RTC_GPIO_STATUS_INT_W1TC_W::new(self, 10)
+    }
+}
+#[doc = "One clear RTC GPIO 0 ~ 21 interrupt status\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_gpio_status_w1tc::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct RTC_GPIO_STATUS_W1TC_SPEC;
+impl crate::RegisterSpec for RTC_GPIO_STATUS_W1TC_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [`rtc_gpio_status_w1tc::W`](W) writer structure"]
+impl crate::Writable for RTC_GPIO_STATUS_W1TC_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets RTC_GPIO_STATUS_W1TC to value 0"]
+impl crate::Resettable for RTC_GPIO_STATUS_W1TC_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_io/rtc_gpio_status_w1ts.rs

@@ -0,0 +1,34 @@
+#[doc = "Register `RTC_GPIO_STATUS_W1TS` writer"]
+pub type W = crate::W<RTC_GPIO_STATUS_W1TS_SPEC>;
+#[doc = "Field `RTC_GPIO_STATUS_INT_W1TS` writer - RTC GPIO 0 ~ 21 interrupt status write 1 to set"]
+pub type RTC_GPIO_STATUS_INT_W1TS_W<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>;
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for crate::generic::Reg<RTC_GPIO_STATUS_W1TS_SPEC> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "(not readable)")
+    }
+}
+impl W {
+    #[doc = "Bits 10:31 - RTC GPIO 0 ~ 21 interrupt status write 1 to set"]
+    #[inline(always)]
+    pub fn rtc_gpio_status_int_w1ts(
+        &mut self,
+    ) -> RTC_GPIO_STATUS_INT_W1TS_W<RTC_GPIO_STATUS_W1TS_SPEC> {
+        RTC_GPIO_STATUS_INT_W1TS_W::new(self, 10)
+    }
+}
+#[doc = "One set RTC GPIO 0 ~ 21 interrupt status\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_gpio_status_w1ts::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct RTC_GPIO_STATUS_W1TS_SPEC;
+impl crate::RegisterSpec for RTC_GPIO_STATUS_W1TS_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [`rtc_gpio_status_w1ts::W`](W) writer structure"]
+impl crate::Writable for RTC_GPIO_STATUS_W1TS_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets RTC_GPIO_STATUS_W1TS to value 0"]
+impl crate::Resettable for RTC_GPIO_STATUS_W1TS_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_io/rtc_pad19.rs

@@ -0,0 +1,167 @@
+#[doc = "Register `RTC_PAD19` reader"]
+pub type R = crate::R<RTC_PAD19_SPEC>;
+#[doc = "Register `RTC_PAD19` writer"]
+pub type W = crate::W<RTC_PAD19_SPEC>;
+#[doc = "Field `FUN_IE` reader - input enable in work mode"]
+pub type FUN_IE_R = crate::BitReader;
+#[doc = "Field `FUN_IE` writer - input enable in work mode"]
+pub type FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SLP_OE` reader - output enable in sleep mode"]
+pub type SLP_OE_R = crate::BitReader;
+#[doc = "Field `SLP_OE` writer - output enable in sleep mode"]
+pub type SLP_OE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SLP_IE` reader - input enable in sleep mode"]
+pub type SLP_IE_R = crate::BitReader;
+#[doc = "Field `SLP_IE` writer - input enable in sleep mode"]
+pub type SLP_IE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SLP_SEL` reader - 1: enable sleep mode during sleep,0: no sleep mode"]
+pub type SLP_SEL_R = crate::BitReader;
+#[doc = "Field `SLP_SEL` writer - 1: enable sleep mode during sleep,0: no sleep mode"]
+pub type SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FUN_SEL` reader - function sel"]
+pub type FUN_SEL_R = crate::FieldReader;
+#[doc = "Field `FUN_SEL` writer - function sel"]
+pub type FUN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `MUX_SEL` reader - 1: use RTC GPIO,0: use digital GPIO"]
+pub type MUX_SEL_R = crate::BitReader;
+#[doc = "Field `MUX_SEL` writer - 1: use RTC GPIO,0: use digital GPIO"]
+pub type MUX_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RUE` reader - RUE"]
+pub type RUE_R = crate::BitReader;
+#[doc = "Field `RUE` writer - RUE"]
+pub type RUE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RDE` reader - RDE"]
+pub type RDE_R = crate::BitReader;
+#[doc = "Field `RDE` writer - RDE"]
+pub type RDE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DRV` reader - DRV"]
+pub type DRV_R = crate::FieldReader;
+#[doc = "Field `DRV` writer - DRV"]
+pub type DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+impl R {
+    #[doc = "Bit 13 - input enable in work mode"]
+    #[inline(always)]
+    pub fn fun_ie(&self) -> FUN_IE_R {
+        FUN_IE_R::new(((self.bits >> 13) & 1) != 0)
+    }
+    #[doc = "Bit 14 - output enable in sleep mode"]
+    #[inline(always)]
+    pub fn slp_oe(&self) -> SLP_OE_R {
+        SLP_OE_R::new(((self.bits >> 14) & 1) != 0)
+    }
+    #[doc = "Bit 15 - input enable in sleep mode"]
+    #[inline(always)]
+    pub fn slp_ie(&self) -> SLP_IE_R {
+        SLP_IE_R::new(((self.bits >> 15) & 1) != 0)
+    }
+    #[doc = "Bit 16 - 1: enable sleep mode during sleep,0: no sleep mode"]
+    #[inline(always)]
+    pub fn slp_sel(&self) -> SLP_SEL_R {
+        SLP_SEL_R::new(((self.bits >> 16) & 1) != 0)
+    }
+    #[doc = "Bits 17:18 - function sel"]
+    #[inline(always)]
+    pub fn fun_sel(&self) -> FUN_SEL_R {
+        FUN_SEL_R::new(((self.bits >> 17) & 3) as u8)
+    }
+    #[doc = "Bit 19 - 1: use RTC GPIO,0: use digital GPIO"]
+    #[inline(always)]
+    pub fn mux_sel(&self) -> MUX_SEL_R {
+        MUX_SEL_R::new(((self.bits >> 19) & 1) != 0)
+    }
+    #[doc = "Bit 27 - RUE"]
+    #[inline(always)]
+    pub fn rue(&self) -> RUE_R {
+        RUE_R::new(((self.bits >> 27) & 1) != 0)
+    }
+    #[doc = "Bit 28 - RDE"]
+    #[inline(always)]
+    pub fn rde(&self) -> RDE_R {
+        RDE_R::new(((self.bits >> 28) & 1) != 0)
+    }
+    #[doc = "Bits 29:30 - DRV"]
+    #[inline(always)]
+    pub fn drv(&self) -> DRV_R {
+        DRV_R::new(((self.bits >> 29) & 3) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("RTC_PAD19")
+            .field("fun_ie", &self.fun_ie())
+            .field("slp_oe", &self.slp_oe())
+            .field("slp_ie", &self.slp_ie())
+            .field("slp_sel", &self.slp_sel())
+            .field("fun_sel", &self.fun_sel())
+            .field("mux_sel", &self.mux_sel())
+            .field("rue", &self.rue())
+            .field("rde", &self.rde())
+            .field("drv", &self.drv())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 13 - input enable in work mode"]
+    #[inline(always)]
+    pub fn fun_ie(&mut self) -> FUN_IE_W<RTC_PAD19_SPEC> {
+        FUN_IE_W::new(self, 13)
+    }
+    #[doc = "Bit 14 - output enable in sleep mode"]
+    #[inline(always)]
+    pub fn slp_oe(&mut self) -> SLP_OE_W<RTC_PAD19_SPEC> {
+        SLP_OE_W::new(self, 14)
+    }
+    #[doc = "Bit 15 - input enable in sleep mode"]
+    #[inline(always)]
+    pub fn slp_ie(&mut self) -> SLP_IE_W<RTC_PAD19_SPEC> {
+        SLP_IE_W::new(self, 15)
+    }
+    #[doc = "Bit 16 - 1: enable sleep mode during sleep,0: no sleep mode"]
+    #[inline(always)]
+    pub fn slp_sel(&mut self) -> SLP_SEL_W<RTC_PAD19_SPEC> {
+        SLP_SEL_W::new(self, 16)
+    }
+    #[doc = "Bits 17:18 - function sel"]
+    #[inline(always)]
+    pub fn fun_sel(&mut self) -> FUN_SEL_W<RTC_PAD19_SPEC> {
+        FUN_SEL_W::new(self, 17)
+    }
+    #[doc = "Bit 19 - 1: use RTC GPIO,0: use digital GPIO"]
+    #[inline(always)]
+    pub fn mux_sel(&mut self) -> MUX_SEL_W<RTC_PAD19_SPEC> {
+        MUX_SEL_W::new(self, 19)
+    }
+    #[doc = "Bit 27 - RUE"]
+    #[inline(always)]
+    pub fn rue(&mut self) -> RUE_W<RTC_PAD19_SPEC> {
+        RUE_W::new(self, 27)
+    }
+    #[doc = "Bit 28 - RDE"]
+    #[inline(always)]
+    pub fn rde(&mut self) -> RDE_W<RTC_PAD19_SPEC> {
+        RDE_W::new(self, 28)
+    }
+    #[doc = "Bits 29:30 - DRV"]
+    #[inline(always)]
+    pub fn drv(&mut self) -> DRV_W<RTC_PAD19_SPEC> {
+        DRV_W::new(self, 29)
+    }
+}
+#[doc = "configure RTC PAD19\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_pad19::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_pad19::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct RTC_PAD19_SPEC;
+impl crate::RegisterSpec for RTC_PAD19_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`rtc_pad19::R`](R) reader structure"]
+impl crate::Readable for RTC_PAD19_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`rtc_pad19::W`](W) writer structure"]
+impl crate::Writable for RTC_PAD19_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets RTC_PAD19 to value 0x5000_0000"]
+impl crate::Resettable for RTC_PAD19_SPEC {
+    const RESET_VALUE: u32 = 0x5000_0000;
+}

vendor/esp32s3/src/rtc_io/rtc_pad20.rs

@@ -0,0 +1,167 @@
+#[doc = "Register `RTC_PAD20` reader"]
+pub type R = crate::R<RTC_PAD20_SPEC>;
+#[doc = "Register `RTC_PAD20` writer"]
+pub type W = crate::W<RTC_PAD20_SPEC>;
+#[doc = "Field `FUN_IE` reader - input enable in work mode"]
+pub type FUN_IE_R = crate::BitReader;
+#[doc = "Field `FUN_IE` writer - input enable in work mode"]
+pub type FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SLP_OE` reader - output enable in sleep mode"]
+pub type SLP_OE_R = crate::BitReader;
+#[doc = "Field `SLP_OE` writer - output enable in sleep mode"]
+pub type SLP_OE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SLP_IE` reader - input enable in sleep mode"]
+pub type SLP_IE_R = crate::BitReader;
+#[doc = "Field `SLP_IE` writer - input enable in sleep mode"]
+pub type SLP_IE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SLP_SEL` reader - 1: enable sleep mode during sleep,0: no sleep mode"]
+pub type SLP_SEL_R = crate::BitReader;
+#[doc = "Field `SLP_SEL` writer - 1: enable sleep mode during sleep,0: no sleep mode"]
+pub type SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FUN_SEL` reader - function sel"]
+pub type FUN_SEL_R = crate::FieldReader;
+#[doc = "Field `FUN_SEL` writer - function sel"]
+pub type FUN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `MUX_SEL` reader - 1: use RTC GPIO,0: use digital GPIO"]
+pub type MUX_SEL_R = crate::BitReader;
+#[doc = "Field `MUX_SEL` writer - 1: use RTC GPIO,0: use digital GPIO"]
+pub type MUX_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RUE` reader - RUE"]
+pub type RUE_R = crate::BitReader;
+#[doc = "Field `RUE` writer - RUE"]
+pub type RUE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RDE` reader - RDE"]
+pub type RDE_R = crate::BitReader;
+#[doc = "Field `RDE` writer - RDE"]
+pub type RDE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DRV` reader - DRV"]
+pub type DRV_R = crate::FieldReader;
+#[doc = "Field `DRV` writer - DRV"]
+pub type DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+impl R {
+    #[doc = "Bit 13 - input enable in work mode"]
+    #[inline(always)]
+    pub fn fun_ie(&self) -> FUN_IE_R {
+        FUN_IE_R::new(((self.bits >> 13) & 1) != 0)
+    }
+    #[doc = "Bit 14 - output enable in sleep mode"]
+    #[inline(always)]
+    pub fn slp_oe(&self) -> SLP_OE_R {
+        SLP_OE_R::new(((self.bits >> 14) & 1) != 0)
+    }
+    #[doc = "Bit 15 - input enable in sleep mode"]
+    #[inline(always)]
+    pub fn slp_ie(&self) -> SLP_IE_R {
+        SLP_IE_R::new(((self.bits >> 15) & 1) != 0)
+    }
+    #[doc = "Bit 16 - 1: enable sleep mode during sleep,0: no sleep mode"]
+    #[inline(always)]
+    pub fn slp_sel(&self) -> SLP_SEL_R {
+        SLP_SEL_R::new(((self.bits >> 16) & 1) != 0)
+    }
+    #[doc = "Bits 17:18 - function sel"]
+    #[inline(always)]
+    pub fn fun_sel(&self) -> FUN_SEL_R {
+        FUN_SEL_R::new(((self.bits >> 17) & 3) as u8)
+    }
+    #[doc = "Bit 19 - 1: use RTC GPIO,0: use digital GPIO"]
+    #[inline(always)]
+    pub fn mux_sel(&self) -> MUX_SEL_R {
+        MUX_SEL_R::new(((self.bits >> 19) & 1) != 0)
+    }
+    #[doc = "Bit 27 - RUE"]
+    #[inline(always)]
+    pub fn rue(&self) -> RUE_R {
+        RUE_R::new(((self.bits >> 27) & 1) != 0)
+    }
+    #[doc = "Bit 28 - RDE"]
+    #[inline(always)]
+    pub fn rde(&self) -> RDE_R {
+        RDE_R::new(((self.bits >> 28) & 1) != 0)
+    }
+    #[doc = "Bits 29:30 - DRV"]
+    #[inline(always)]
+    pub fn drv(&self) -> DRV_R {
+        DRV_R::new(((self.bits >> 29) & 3) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("RTC_PAD20")
+            .field("fun_ie", &self.fun_ie())
+            .field("slp_oe", &self.slp_oe())
+            .field("slp_ie", &self.slp_ie())
+            .field("slp_sel", &self.slp_sel())
+            .field("fun_sel", &self.fun_sel())
+            .field("mux_sel", &self.mux_sel())
+            .field("rue", &self.rue())
+            .field("rde", &self.rde())
+            .field("drv", &self.drv())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 13 - input enable in work mode"]
+    #[inline(always)]
+    pub fn fun_ie(&mut self) -> FUN_IE_W<RTC_PAD20_SPEC> {
+        FUN_IE_W::new(self, 13)
+    }
+    #[doc = "Bit 14 - output enable in sleep mode"]
+    #[inline(always)]
+    pub fn slp_oe(&mut self) -> SLP_OE_W<RTC_PAD20_SPEC> {
+        SLP_OE_W::new(self, 14)
+    }
+    #[doc = "Bit 15 - input enable in sleep mode"]
+    #[inline(always)]
+    pub fn slp_ie(&mut self) -> SLP_IE_W<RTC_PAD20_SPEC> {
+        SLP_IE_W::new(self, 15)
+    }
+    #[doc = "Bit 16 - 1: enable sleep mode during sleep,0: no sleep mode"]
+    #[inline(always)]
+    pub fn slp_sel(&mut self) -> SLP_SEL_W<RTC_PAD20_SPEC> {
+        SLP_SEL_W::new(self, 16)
+    }
+    #[doc = "Bits 17:18 - function sel"]
+    #[inline(always)]
+    pub fn fun_sel(&mut self) -> FUN_SEL_W<RTC_PAD20_SPEC> {
+        FUN_SEL_W::new(self, 17)
+    }
+    #[doc = "Bit 19 - 1: use RTC GPIO,0: use digital GPIO"]
+    #[inline(always)]
+    pub fn mux_sel(&mut self) -> MUX_SEL_W<RTC_PAD20_SPEC> {
+        MUX_SEL_W::new(self, 19)
+    }
+    #[doc = "Bit 27 - RUE"]
+    #[inline(always)]
+    pub fn rue(&mut self) -> RUE_W<RTC_PAD20_SPEC> {
+        RUE_W::new(self, 27)
+    }
+    #[doc = "Bit 28 - RDE"]
+    #[inline(always)]
+    pub fn rde(&mut self) -> RDE_W<RTC_PAD20_SPEC> {
+        RDE_W::new(self, 28)
+    }
+    #[doc = "Bits 29:30 - DRV"]
+    #[inline(always)]
+    pub fn drv(&mut self) -> DRV_W<RTC_PAD20_SPEC> {
+        DRV_W::new(self, 29)
+    }
+}
+#[doc = "configure RTC PAD20\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_pad20::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_pad20::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct RTC_PAD20_SPEC;
+impl crate::RegisterSpec for RTC_PAD20_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`rtc_pad20::R`](R) reader structure"]
+impl crate::Readable for RTC_PAD20_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`rtc_pad20::W`](W) writer structure"]
+impl crate::Writable for RTC_PAD20_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets RTC_PAD20 to value 0x5000_0000"]
+impl crate::Resettable for RTC_PAD20_SPEC {
+    const RESET_VALUE: u32 = 0x5000_0000;
+}

vendor/esp32s3/src/rtc_io/rtc_pad21.rs

@@ -0,0 +1,167 @@
+#[doc = "Register `RTC_PAD21` reader"]
+pub type R = crate::R<RTC_PAD21_SPEC>;
+#[doc = "Register `RTC_PAD21` writer"]
+pub type W = crate::W<RTC_PAD21_SPEC>;
+#[doc = "Field `FUN_IE` reader - input enable in work mode"]
+pub type FUN_IE_R = crate::BitReader;
+#[doc = "Field `FUN_IE` writer - input enable in work mode"]
+pub type FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SLP_OE` reader - output enable in sleep mode"]
+pub type SLP_OE_R = crate::BitReader;
+#[doc = "Field `SLP_OE` writer - output enable in sleep mode"]
+pub type SLP_OE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SLP_IE` reader - input enable in sleep mode"]
+pub type SLP_IE_R = crate::BitReader;
+#[doc = "Field `SLP_IE` writer - input enable in sleep mode"]
+pub type SLP_IE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SLP_SEL` reader - 1: enable sleep mode during sleep,0: no sleep mode"]
+pub type SLP_SEL_R = crate::BitReader;
+#[doc = "Field `SLP_SEL` writer - 1: enable sleep mode during sleep,0: no sleep mode"]
+pub type SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FUN_SEL` reader - function sel"]
+pub type FUN_SEL_R = crate::FieldReader;
+#[doc = "Field `FUN_SEL` writer - function sel"]
+pub type FUN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `MUX_SEL` reader - 1: use RTC GPIO,0: use digital GPIO"]
+pub type MUX_SEL_R = crate::BitReader;
+#[doc = "Field `MUX_SEL` writer - 1: use RTC GPIO,0: use digital GPIO"]
+pub type MUX_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RUE` reader - RUE"]
+pub type RUE_R = crate::BitReader;
+#[doc = "Field `RUE` writer - RUE"]
+pub type RUE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RDE` reader - RDE"]
+pub type RDE_R = crate::BitReader;
+#[doc = "Field `RDE` writer - RDE"]
+pub type RDE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DRV` reader - DRV"]
+pub type DRV_R = crate::FieldReader;
+#[doc = "Field `DRV` writer - DRV"]
+pub type DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+impl R {
+    #[doc = "Bit 13 - input enable in work mode"]
+    #[inline(always)]
+    pub fn fun_ie(&self) -> FUN_IE_R {
+        FUN_IE_R::new(((self.bits >> 13) & 1) != 0)
+    }
+    #[doc = "Bit 14 - output enable in sleep mode"]
+    #[inline(always)]
+    pub fn slp_oe(&self) -> SLP_OE_R {
+        SLP_OE_R::new(((self.bits >> 14) & 1) != 0)
+    }
+    #[doc = "Bit 15 - input enable in sleep mode"]
+    #[inline(always)]
+    pub fn slp_ie(&self) -> SLP_IE_R {
+        SLP_IE_R::new(((self.bits >> 15) & 1) != 0)
+    }
+    #[doc = "Bit 16 - 1: enable sleep mode during sleep,0: no sleep mode"]
+    #[inline(always)]
+    pub fn slp_sel(&self) -> SLP_SEL_R {
+        SLP_SEL_R::new(((self.bits >> 16) & 1) != 0)
+    }
+    #[doc = "Bits 17:18 - function sel"]
+    #[inline(always)]
+    pub fn fun_sel(&self) -> FUN_SEL_R {
+        FUN_SEL_R::new(((self.bits >> 17) & 3) as u8)
+    }
+    #[doc = "Bit 19 - 1: use RTC GPIO,0: use digital GPIO"]
+    #[inline(always)]
+    pub fn mux_sel(&self) -> MUX_SEL_R {
+        MUX_SEL_R::new(((self.bits >> 19) & 1) != 0)
+    }
+    #[doc = "Bit 27 - RUE"]
+    #[inline(always)]
+    pub fn rue(&self) -> RUE_R {
+        RUE_R::new(((self.bits >> 27) & 1) != 0)
+    }
+    #[doc = "Bit 28 - RDE"]
+    #[inline(always)]
+    pub fn rde(&self) -> RDE_R {
+        RDE_R::new(((self.bits >> 28) & 1) != 0)
+    }
+    #[doc = "Bits 29:30 - DRV"]
+    #[inline(always)]
+    pub fn drv(&self) -> DRV_R {
+        DRV_R::new(((self.bits >> 29) & 3) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("RTC_PAD21")
+            .field("fun_ie", &self.fun_ie())
+            .field("slp_oe", &self.slp_oe())
+            .field("slp_ie", &self.slp_ie())
+            .field("slp_sel", &self.slp_sel())
+            .field("fun_sel", &self.fun_sel())
+            .field("mux_sel", &self.mux_sel())
+            .field("rue", &self.rue())
+            .field("rde", &self.rde())
+            .field("drv", &self.drv())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 13 - input enable in work mode"]
+    #[inline(always)]
+    pub fn fun_ie(&mut self) -> FUN_IE_W<RTC_PAD21_SPEC> {
+        FUN_IE_W::new(self, 13)
+    }
+    #[doc = "Bit 14 - output enable in sleep mode"]
+    #[inline(always)]
+    pub fn slp_oe(&mut self) -> SLP_OE_W<RTC_PAD21_SPEC> {
+        SLP_OE_W::new(self, 14)
+    }
+    #[doc = "Bit 15 - input enable in sleep mode"]
+    #[inline(always)]
+    pub fn slp_ie(&mut self) -> SLP_IE_W<RTC_PAD21_SPEC> {
+        SLP_IE_W::new(self, 15)
+    }
+    #[doc = "Bit 16 - 1: enable sleep mode during sleep,0: no sleep mode"]
+    #[inline(always)]
+    pub fn slp_sel(&mut self) -> SLP_SEL_W<RTC_PAD21_SPEC> {
+        SLP_SEL_W::new(self, 16)
+    }
+    #[doc = "Bits 17:18 - function sel"]
+    #[inline(always)]
+    pub fn fun_sel(&mut self) -> FUN_SEL_W<RTC_PAD21_SPEC> {
+        FUN_SEL_W::new(self, 17)
+    }
+    #[doc = "Bit 19 - 1: use RTC GPIO,0: use digital GPIO"]
+    #[inline(always)]
+    pub fn mux_sel(&mut self) -> MUX_SEL_W<RTC_PAD21_SPEC> {
+        MUX_SEL_W::new(self, 19)
+    }
+    #[doc = "Bit 27 - RUE"]
+    #[inline(always)]
+    pub fn rue(&mut self) -> RUE_W<RTC_PAD21_SPEC> {
+        RUE_W::new(self, 27)
+    }
+    #[doc = "Bit 28 - RDE"]
+    #[inline(always)]
+    pub fn rde(&mut self) -> RDE_W<RTC_PAD21_SPEC> {
+        RDE_W::new(self, 28)
+    }
+    #[doc = "Bits 29:30 - DRV"]
+    #[inline(always)]
+    pub fn drv(&mut self) -> DRV_W<RTC_PAD21_SPEC> {
+        DRV_W::new(self, 29)
+    }
+}
+#[doc = "configure RTC PAD21\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_pad21::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_pad21::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct RTC_PAD21_SPEC;
+impl crate::RegisterSpec for RTC_PAD21_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`rtc_pad21::R`](R) reader structure"]
+impl crate::Readable for RTC_PAD21_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`rtc_pad21::W`](W) writer structure"]
+impl crate::Writable for RTC_PAD21_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets RTC_PAD21 to value 0x5000_0000"]
+impl crate::Resettable for RTC_PAD21_SPEC {
+    const RESET_VALUE: u32 = 0x5000_0000;
+}

vendor/esp32s3/src/rtc_io/sar_i2c_io.rs

@@ -0,0 +1,77 @@
+#[doc = "Register `SAR_I2C_IO` reader"]
+pub type R = crate::R<SAR_I2C_IO_SPEC>;
+#[doc = "Register `SAR_I2C_IO` writer"]
+pub type W = crate::W<SAR_I2C_IO_SPEC>;
+#[doc = "Field `SAR_DEBUG_BIT_SEL` reader - ******* Description configure***"]
+pub type SAR_DEBUG_BIT_SEL_R = crate::FieldReader;
+#[doc = "Field `SAR_DEBUG_BIT_SEL` writer - ******* Description configure***"]
+pub type SAR_DEBUG_BIT_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
+#[doc = "Field `SAR_I2C_SCL_SEL` reader - ******* Description configure***"]
+pub type SAR_I2C_SCL_SEL_R = crate::FieldReader;
+#[doc = "Field `SAR_I2C_SCL_SEL` writer - ******* Description configure***"]
+pub type SAR_I2C_SCL_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `SAR_I2C_SDA_SEL` reader - ******* Description configure***"]
+pub type SAR_I2C_SDA_SEL_R = crate::FieldReader;
+#[doc = "Field `SAR_I2C_SDA_SEL` writer - ******* Description configure***"]
+pub type SAR_I2C_SDA_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+impl R {
+    #[doc = "Bits 23:27 - ******* Description configure***"]
+    #[inline(always)]
+    pub fn sar_debug_bit_sel(&self) -> SAR_DEBUG_BIT_SEL_R {
+        SAR_DEBUG_BIT_SEL_R::new(((self.bits >> 23) & 0x1f) as u8)
+    }
+    #[doc = "Bits 28:29 - ******* Description configure***"]
+    #[inline(always)]
+    pub fn sar_i2c_scl_sel(&self) -> SAR_I2C_SCL_SEL_R {
+        SAR_I2C_SCL_SEL_R::new(((self.bits >> 28) & 3) as u8)
+    }
+    #[doc = "Bits 30:31 - ******* Description configure***"]
+    #[inline(always)]
+    pub fn sar_i2c_sda_sel(&self) -> SAR_I2C_SDA_SEL_R {
+        SAR_I2C_SDA_SEL_R::new(((self.bits >> 30) & 3) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_I2C_IO")
+            .field("sar_debug_bit_sel", &self.sar_debug_bit_sel())
+            .field("sar_i2c_scl_sel", &self.sar_i2c_scl_sel())
+            .field("sar_i2c_sda_sel", &self.sar_i2c_sda_sel())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 23:27 - ******* Description configure***"]
+    #[inline(always)]
+    pub fn sar_debug_bit_sel(&mut self) -> SAR_DEBUG_BIT_SEL_W<SAR_I2C_IO_SPEC> {
+        SAR_DEBUG_BIT_SEL_W::new(self, 23)
+    }
+    #[doc = "Bits 28:29 - ******* Description configure***"]
+    #[inline(always)]
+    pub fn sar_i2c_scl_sel(&mut self) -> SAR_I2C_SCL_SEL_W<SAR_I2C_IO_SPEC> {
+        SAR_I2C_SCL_SEL_W::new(self, 28)
+    }
+    #[doc = "Bits 30:31 - ******* Description configure***"]
+    #[inline(always)]
+    pub fn sar_i2c_sda_sel(&mut self) -> SAR_I2C_SDA_SEL_W<SAR_I2C_IO_SPEC> {
+        SAR_I2C_SDA_SEL_W::new(self, 30)
+    }
+}
+#[doc = "configure rtc i2c mux\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_i2c_io::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_i2c_io::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_I2C_IO_SPEC;
+impl crate::RegisterSpec for SAR_I2C_IO_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_i2c_io::R`](R) reader structure"]
+impl crate::Readable for SAR_I2C_IO_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sar_i2c_io::W`](W) writer structure"]
+impl crate::Writable for SAR_I2C_IO_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SAR_I2C_IO to value 0"]
+impl crate::Resettable for SAR_I2C_IO_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_io/touch_ctrl.rs

@@ -0,0 +1,62 @@
+#[doc = "Register `TOUCH_CTRL` reader"]
+pub type R = crate::R<TOUCH_CTRL_SPEC>;
+#[doc = "Register `TOUCH_CTRL` writer"]
+pub type W = crate::W<TOUCH_CTRL_SPEC>;
+#[doc = "Field `IO_TOUCH_BUFSEL` reader - BUF_SEL when touch work without fsm"]
+pub type IO_TOUCH_BUFSEL_R = crate::FieldReader;
+#[doc = "Field `IO_TOUCH_BUFSEL` writer - BUF_SEL when touch work without fsm"]
+pub type IO_TOUCH_BUFSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `IO_TOUCH_BUFMODE` reader - BUF_MODE when touch work without fsm"]
+pub type IO_TOUCH_BUFMODE_R = crate::BitReader;
+#[doc = "Field `IO_TOUCH_BUFMODE` writer - BUF_MODE when touch work without fsm"]
+pub type IO_TOUCH_BUFMODE_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 0:3 - BUF_SEL when touch work without fsm"]
+    #[inline(always)]
+    pub fn io_touch_bufsel(&self) -> IO_TOUCH_BUFSEL_R {
+        IO_TOUCH_BUFSEL_R::new((self.bits & 0x0f) as u8)
+    }
+    #[doc = "Bit 4 - BUF_MODE when touch work without fsm"]
+    #[inline(always)]
+    pub fn io_touch_bufmode(&self) -> IO_TOUCH_BUFMODE_R {
+        IO_TOUCH_BUFMODE_R::new(((self.bits >> 4) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("TOUCH_CTRL")
+            .field("io_touch_bufsel", &self.io_touch_bufsel())
+            .field("io_touch_bufmode", &self.io_touch_bufmode())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:3 - BUF_SEL when touch work without fsm"]
+    #[inline(always)]
+    pub fn io_touch_bufsel(&mut self) -> IO_TOUCH_BUFSEL_W<TOUCH_CTRL_SPEC> {
+        IO_TOUCH_BUFSEL_W::new(self, 0)
+    }
+    #[doc = "Bit 4 - BUF_MODE when touch work without fsm"]
+    #[inline(always)]
+    pub fn io_touch_bufmode(&mut self) -> IO_TOUCH_BUFMODE_W<TOUCH_CTRL_SPEC> {
+        IO_TOUCH_BUFMODE_W::new(self, 4)
+    }
+}
+#[doc = "configure touch pad bufmode\n\nYou can [`read`](crate::Reg::read) this register and get [`touch_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`touch_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct TOUCH_CTRL_SPEC;
+impl crate::RegisterSpec for TOUCH_CTRL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`touch_ctrl::R`](R) reader structure"]
+impl crate::Readable for TOUCH_CTRL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`touch_ctrl::W`](W) writer structure"]
+impl crate::Writable for TOUCH_CTRL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets TOUCH_CTRL to value 0"]
+impl crate::Resettable for TOUCH_CTRL_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/rtc_io/touch_pad.rs

@@ -0,0 +1,212 @@
+#[doc = "Register `TOUCH_PAD%s` reader"]
+pub type R = crate::R<TOUCH_PAD_SPEC>;
+#[doc = "Register `TOUCH_PAD%s` writer"]
+pub type W = crate::W<TOUCH_PAD_SPEC>;
+#[doc = "Field `FUN_IE` reader - input enable in work mode"]
+pub type FUN_IE_R = crate::BitReader;
+#[doc = "Field `FUN_IE` writer - input enable in work mode"]
+pub type FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SLP_OE` reader - output enable in sleep mode"]
+pub type SLP_OE_R = crate::BitReader;
+#[doc = "Field `SLP_OE` writer - output enable in sleep mode"]
+pub type SLP_OE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SLP_IE` reader - input enable in sleep mode"]
+pub type SLP_IE_R = crate::BitReader;
+#[doc = "Field `SLP_IE` writer - input enable in sleep mode"]
+pub type SLP_IE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SLP_SEL` reader - 1: enable sleep mode during sleep,0: no sleep mode"]
+pub type SLP_SEL_R = crate::BitReader;
+#[doc = "Field `SLP_SEL` writer - 1: enable sleep mode during sleep,0: no sleep mode"]
+pub type SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FUN_SEL` reader - function sel"]
+pub type FUN_SEL_R = crate::FieldReader;
+#[doc = "Field `FUN_SEL` writer - function sel"]
+pub type FUN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `MUX_SEL` reader - 1: use RTC GPIO,0: use digital GPIO"]
+pub type MUX_SEL_R = crate::BitReader;
+#[doc = "Field `MUX_SEL` writer - 1: use RTC GPIO,0: use digital GPIO"]
+pub type MUX_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `XPD` reader - TOUCH_XPD"]
+pub type XPD_R = crate::BitReader;
+#[doc = "Field `XPD` writer - TOUCH_XPD"]
+pub type XPD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIE_OPT` reader - TOUCH_TIE_OPT"]
+pub type TIE_OPT_R = crate::BitReader;
+#[doc = "Field `TIE_OPT` writer - TOUCH_TIE_OPT"]
+pub type TIE_OPT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `START` reader - TOUCH_START"]
+pub type START_R = crate::BitReader;
+#[doc = "Field `START` writer - TOUCH_START"]
+pub type START_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RUE` reader - RUE"]
+pub type RUE_R = crate::BitReader;
+#[doc = "Field `RUE` writer - RUE"]
+pub type RUE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RDE` reader - RDE"]
+pub type RDE_R = crate::BitReader;
+#[doc = "Field `RDE` writer - RDE"]
+pub type RDE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DRV` reader - DRV"]
+pub type DRV_R = crate::FieldReader;
+#[doc = "Field `DRV` writer - DRV"]
+pub type DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+impl R {
+    #[doc = "Bit 13 - input enable in work mode"]
+    #[inline(always)]
+    pub fn fun_ie(&self) -> FUN_IE_R {
+        FUN_IE_R::new(((self.bits >> 13) & 1) != 0)
+    }
+    #[doc = "Bit 14 - output enable in sleep mode"]
+    #[inline(always)]
+    pub fn slp_oe(&self) -> SLP_OE_R {
+        SLP_OE_R::new(((self.bits >> 14) & 1) != 0)
+    }
+    #[doc = "Bit 15 - input enable in sleep mode"]
+    #[inline(always)]
+    pub fn slp_ie(&self) -> SLP_IE_R {
+        SLP_IE_R::new(((self.bits >> 15) & 1) != 0)
+    }
+    #[doc = "Bit 16 - 1: enable sleep mode during sleep,0: no sleep mode"]
+    #[inline(always)]
+    pub fn slp_sel(&self) -> SLP_SEL_R {
+        SLP_SEL_R::new(((self.bits >> 16) & 1) != 0)
+    }
+    #[doc = "Bits 17:18 - function sel"]
+    #[inline(always)]
+    pub fn fun_sel(&self) -> FUN_SEL_R {
+        FUN_SEL_R::new(((self.bits >> 17) & 3) as u8)
+    }
+    #[doc = "Bit 19 - 1: use RTC GPIO,0: use digital GPIO"]
+    #[inline(always)]
+    pub fn mux_sel(&self) -> MUX_SEL_R {
+        MUX_SEL_R::new(((self.bits >> 19) & 1) != 0)
+    }
+    #[doc = "Bit 20 - TOUCH_XPD"]
+    #[inline(always)]
+    pub fn xpd(&self) -> XPD_R {
+        XPD_R::new(((self.bits >> 20) & 1) != 0)
+    }
+    #[doc = "Bit 21 - TOUCH_TIE_OPT"]
+    #[inline(always)]
+    pub fn tie_opt(&self) -> TIE_OPT_R {
+        TIE_OPT_R::new(((self.bits >> 21) & 1) != 0)
+    }
+    #[doc = "Bit 22 - TOUCH_START"]
+    #[inline(always)]
+    pub fn start(&self) -> START_R {
+        START_R::new(((self.bits >> 22) & 1) != 0)
+    }
+    #[doc = "Bit 27 - RUE"]
+    #[inline(always)]
+    pub fn rue(&self) -> RUE_R {
+        RUE_R::new(((self.bits >> 27) & 1) != 0)
+    }
+    #[doc = "Bit 28 - RDE"]
+    #[inline(always)]
+    pub fn rde(&self) -> RDE_R {
+        RDE_R::new(((self.bits >> 28) & 1) != 0)
+    }
+    #[doc = "Bits 29:30 - DRV"]
+    #[inline(always)]
+    pub fn drv(&self) -> DRV_R {
+        DRV_R::new(((self.bits >> 29) & 3) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("TOUCH_PAD")
+            .field("fun_ie", &self.fun_ie())
+            .field("slp_oe", &self.slp_oe())
+            .field("slp_ie", &self.slp_ie())
+            .field("slp_sel", &self.slp_sel())
+            .field("fun_sel", &self.fun_sel())
+            .field("mux_sel", &self.mux_sel())
+            .field("xpd", &self.xpd())
+            .field("tie_opt", &self.tie_opt())
+            .field("start", &self.start())
+            .field("rue", &self.rue())
+            .field("rde", &self.rde())
+            .field("drv", &self.drv())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 13 - input enable in work mode"]
+    #[inline(always)]
+    pub fn fun_ie(&mut self) -> FUN_IE_W<TOUCH_PAD_SPEC> {
+        FUN_IE_W::new(self, 13)
+    }
+    #[doc = "Bit 14 - output enable in sleep mode"]
+    #[inline(always)]
+    pub fn slp_oe(&mut self) -> SLP_OE_W<TOUCH_PAD_SPEC> {
+        SLP_OE_W::new(self, 14)
+    }
+    #[doc = "Bit 15 - input enable in sleep mode"]
+    #[inline(always)]
+    pub fn slp_ie(&mut self) -> SLP_IE_W<TOUCH_PAD_SPEC> {
+        SLP_IE_W::new(self, 15)
+    }
+    #[doc = "Bit 16 - 1: enable sleep mode during sleep,0: no sleep mode"]
+    #[inline(always)]
+    pub fn slp_sel(&mut self) -> SLP_SEL_W<TOUCH_PAD_SPEC> {
+        SLP_SEL_W::new(self, 16)
+    }
+    #[doc = "Bits 17:18 - function sel"]
+    #[inline(always)]
+    pub fn fun_sel(&mut self) -> FUN_SEL_W<TOUCH_PAD_SPEC> {
+        FUN_SEL_W::new(self, 17)
+    }
+    #[doc = "Bit 19 - 1: use RTC GPIO,0: use digital GPIO"]
+    #[inline(always)]
+    pub fn mux_sel(&mut self) -> MUX_SEL_W<TOUCH_PAD_SPEC> {
+        MUX_SEL_W::new(self, 19)
+    }
+    #[doc = "Bit 20 - TOUCH_XPD"]
+    #[inline(always)]
+    pub fn xpd(&mut self) -> XPD_W<TOUCH_PAD_SPEC> {
+        XPD_W::new(self, 20)
+    }
+    #[doc = "Bit 21 - TOUCH_TIE_OPT"]
+    #[inline(always)]
+    pub fn tie_opt(&mut self) -> TIE_OPT_W<TOUCH_PAD_SPEC> {
+        TIE_OPT_W::new(self, 21)
+    }
+    #[doc = "Bit 22 - TOUCH_START"]
+    #[inline(always)]
+    pub fn start(&mut self) -> START_W<TOUCH_PAD_SPEC> {
+        START_W::new(self, 22)
+    }
+    #[doc = "Bit 27 - RUE"]
+    #[inline(always)]
+    pub fn rue(&mut self) -> RUE_W<TOUCH_PAD_SPEC> {
+        RUE_W::new(self, 27)
+    }
+    #[doc = "Bit 28 - RDE"]
+    #[inline(always)]
+    pub fn rde(&mut self) -> RDE_W<TOUCH_PAD_SPEC> {
+        RDE_W::new(self, 28)
+    }
+    #[doc = "Bits 29:30 - DRV"]
+    #[inline(always)]
+    pub fn drv(&mut self) -> DRV_W<TOUCH_PAD_SPEC> {
+        DRV_W::new(self, 29)
+    }
+}
+#[doc = "configure RTC PAD%s\n\nYou can [`read`](crate::Reg::read) this register and get [`touch_pad::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`touch_pad::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct TOUCH_PAD_SPEC;
+impl crate::RegisterSpec for TOUCH_PAD_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`touch_pad::R`](R) reader structure"]
+impl crate::Readable for TOUCH_PAD_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`touch_pad::W`](W) writer structure"]
+impl crate::Writable for TOUCH_PAD_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets TOUCH_PAD%s to value 0x5000_0000"]
+impl crate::Resettable for TOUCH_PAD_SPEC {
+    const RESET_VALUE: u32 = 0x5000_0000;
+}

vendor/esp32s3/src/rtc_io/xtal_32n_pad.rs

@@ -0,0 +1,167 @@
+#[doc = "Register `XTAL_32N_PAD` reader"]
+pub type R = crate::R<XTAL_32N_PAD_SPEC>;
+#[doc = "Register `XTAL_32N_PAD` writer"]
+pub type W = crate::W<XTAL_32N_PAD_SPEC>;
+#[doc = "Field `X32N_FUN_IE` reader - input enable in work mode"]
+pub type X32N_FUN_IE_R = crate::BitReader;
+#[doc = "Field `X32N_FUN_IE` writer - input enable in work mode"]
+pub type X32N_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `X32N_SLP_OE` reader - output enable in sleep mode"]
+pub type X32N_SLP_OE_R = crate::BitReader;
+#[doc = "Field `X32N_SLP_OE` writer - output enable in sleep mode"]
+pub type X32N_SLP_OE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `X32N_SLP_IE` reader - input enable in sleep mode"]
+pub type X32N_SLP_IE_R = crate::BitReader;
+#[doc = "Field `X32N_SLP_IE` writer - input enable in sleep mode"]
+pub type X32N_SLP_IE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `X32N_SLP_SEL` reader - 1: enable sleep mode during sleep,0: no sleep mode"]
+pub type X32N_SLP_SEL_R = crate::BitReader;
+#[doc = "Field `X32N_SLP_SEL` writer - 1: enable sleep mode during sleep,0: no sleep mode"]
+pub type X32N_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `X32N_FUN_SEL` reader - function sel"]
+pub type X32N_FUN_SEL_R = crate::FieldReader;
+#[doc = "Field `X32N_FUN_SEL` writer - function sel"]
+pub type X32N_FUN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `X32N_MUX_SEL` reader - 1: use RTC GPIO,0: use digital GPIO"]
+pub type X32N_MUX_SEL_R = crate::BitReader;
+#[doc = "Field `X32N_MUX_SEL` writer - 1: use RTC GPIO,0: use digital GPIO"]
+pub type X32N_MUX_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `X32N_RUE` reader - RUE"]
+pub type X32N_RUE_R = crate::BitReader;
+#[doc = "Field `X32N_RUE` writer - RUE"]
+pub type X32N_RUE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `X32N_RDE` reader - RDE"]
+pub type X32N_RDE_R = crate::BitReader;
+#[doc = "Field `X32N_RDE` writer - RDE"]
+pub type X32N_RDE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `X32N_DRV` reader - DRV"]
+pub type X32N_DRV_R = crate::FieldReader;
+#[doc = "Field `X32N_DRV` writer - DRV"]
+pub type X32N_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+impl R {
+    #[doc = "Bit 13 - input enable in work mode"]
+    #[inline(always)]
+    pub fn x32n_fun_ie(&self) -> X32N_FUN_IE_R {
+        X32N_FUN_IE_R::new(((self.bits >> 13) & 1) != 0)
+    }
+    #[doc = "Bit 14 - output enable in sleep mode"]
+    #[inline(always)]
+    pub fn x32n_slp_oe(&self) -> X32N_SLP_OE_R {
+        X32N_SLP_OE_R::new(((self.bits >> 14) & 1) != 0)
+    }
+    #[doc = "Bit 15 - input enable in sleep mode"]
+    #[inline(always)]
+    pub fn x32n_slp_ie(&self) -> X32N_SLP_IE_R {
+        X32N_SLP_IE_R::new(((self.bits >> 15) & 1) != 0)
+    }
+    #[doc = "Bit 16 - 1: enable sleep mode during sleep,0: no sleep mode"]
+    #[inline(always)]
+    pub fn x32n_slp_sel(&self) -> X32N_SLP_SEL_R {
+        X32N_SLP_SEL_R::new(((self.bits >> 16) & 1) != 0)
+    }
+    #[doc = "Bits 17:18 - function sel"]
+    #[inline(always)]
+    pub fn x32n_fun_sel(&self) -> X32N_FUN_SEL_R {
+        X32N_FUN_SEL_R::new(((self.bits >> 17) & 3) as u8)
+    }
+    #[doc = "Bit 19 - 1: use RTC GPIO,0: use digital GPIO"]
+    #[inline(always)]
+    pub fn x32n_mux_sel(&self) -> X32N_MUX_SEL_R {
+        X32N_MUX_SEL_R::new(((self.bits >> 19) & 1) != 0)
+    }
+    #[doc = "Bit 27 - RUE"]
+    #[inline(always)]
+    pub fn x32n_rue(&self) -> X32N_RUE_R {
+        X32N_RUE_R::new(((self.bits >> 27) & 1) != 0)
+    }
+    #[doc = "Bit 28 - RDE"]
+    #[inline(always)]
+    pub fn x32n_rde(&self) -> X32N_RDE_R {
+        X32N_RDE_R::new(((self.bits >> 28) & 1) != 0)
+    }
+    #[doc = "Bits 29:30 - DRV"]
+    #[inline(always)]
+    pub fn x32n_drv(&self) -> X32N_DRV_R {
+        X32N_DRV_R::new(((self.bits >> 29) & 3) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("XTAL_32N_PAD")
+            .field("x32n_fun_ie", &self.x32n_fun_ie())
+            .field("x32n_slp_oe", &self.x32n_slp_oe())
+            .field("x32n_slp_ie", &self.x32n_slp_ie())
+            .field("x32n_slp_sel", &self.x32n_slp_sel())
+            .field("x32n_fun_sel", &self.x32n_fun_sel())
+            .field("x32n_mux_sel", &self.x32n_mux_sel())
+            .field("x32n_rue", &self.x32n_rue())
+            .field("x32n_rde", &self.x32n_rde())
+            .field("x32n_drv", &self.x32n_drv())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 13 - input enable in work mode"]
+    #[inline(always)]
+    pub fn x32n_fun_ie(&mut self) -> X32N_FUN_IE_W<XTAL_32N_PAD_SPEC> {
+        X32N_FUN_IE_W::new(self, 13)
+    }
+    #[doc = "Bit 14 - output enable in sleep mode"]
+    #[inline(always)]
+    pub fn x32n_slp_oe(&mut self) -> X32N_SLP_OE_W<XTAL_32N_PAD_SPEC> {
+        X32N_SLP_OE_W::new(self, 14)
+    }
+    #[doc = "Bit 15 - input enable in sleep mode"]
+    #[inline(always)]
+    pub fn x32n_slp_ie(&mut self) -> X32N_SLP_IE_W<XTAL_32N_PAD_SPEC> {
+        X32N_SLP_IE_W::new(self, 15)
+    }
+    #[doc = "Bit 16 - 1: enable sleep mode during sleep,0: no sleep mode"]
+    #[inline(always)]
+    pub fn x32n_slp_sel(&mut self) -> X32N_SLP_SEL_W<XTAL_32N_PAD_SPEC> {
+        X32N_SLP_SEL_W::new(self, 16)
+    }
+    #[doc = "Bits 17:18 - function sel"]
+    #[inline(always)]
+    pub fn x32n_fun_sel(&mut self) -> X32N_FUN_SEL_W<XTAL_32N_PAD_SPEC> {
+        X32N_FUN_SEL_W::new(self, 17)
+    }
+    #[doc = "Bit 19 - 1: use RTC GPIO,0: use digital GPIO"]
+    #[inline(always)]
+    pub fn x32n_mux_sel(&mut self) -> X32N_MUX_SEL_W<XTAL_32N_PAD_SPEC> {
+        X32N_MUX_SEL_W::new(self, 19)
+    }
+    #[doc = "Bit 27 - RUE"]
+    #[inline(always)]
+    pub fn x32n_rue(&mut self) -> X32N_RUE_W<XTAL_32N_PAD_SPEC> {
+        X32N_RUE_W::new(self, 27)
+    }
+    #[doc = "Bit 28 - RDE"]
+    #[inline(always)]
+    pub fn x32n_rde(&mut self) -> X32N_RDE_W<XTAL_32N_PAD_SPEC> {
+        X32N_RDE_W::new(self, 28)
+    }
+    #[doc = "Bits 29:30 - DRV"]
+    #[inline(always)]
+    pub fn x32n_drv(&mut self) -> X32N_DRV_W<XTAL_32N_PAD_SPEC> {
+        X32N_DRV_W::new(self, 29)
+    }
+}
+#[doc = "configure RTC PAD16\n\nYou can [`read`](crate::Reg::read) this register and get [`xtal_32n_pad::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`xtal_32n_pad::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct XTAL_32N_PAD_SPEC;
+impl crate::RegisterSpec for XTAL_32N_PAD_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`xtal_32n_pad::R`](R) reader structure"]
+impl crate::Readable for XTAL_32N_PAD_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`xtal_32n_pad::W`](W) writer structure"]
+impl crate::Writable for XTAL_32N_PAD_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets XTAL_32N_PAD to value 0x4000_0000"]
+impl crate::Resettable for XTAL_32N_PAD_SPEC {
+    const RESET_VALUE: u32 = 0x4000_0000;
+}

vendor/esp32s3/src/rtc_io/xtal_32p_pad.rs

@@ -0,0 +1,167 @@
+#[doc = "Register `XTAL_32P_PAD` reader"]
+pub type R = crate::R<XTAL_32P_PAD_SPEC>;
+#[doc = "Register `XTAL_32P_PAD` writer"]
+pub type W = crate::W<XTAL_32P_PAD_SPEC>;
+#[doc = "Field `X32P_FUN_IE` reader - input enable in work mode"]
+pub type X32P_FUN_IE_R = crate::BitReader;
+#[doc = "Field `X32P_FUN_IE` writer - input enable in work mode"]
+pub type X32P_FUN_IE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `X32P_SLP_OE` reader - output enable in sleep mode"]
+pub type X32P_SLP_OE_R = crate::BitReader;
+#[doc = "Field `X32P_SLP_OE` writer - output enable in sleep mode"]
+pub type X32P_SLP_OE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `X32P_SLP_IE` reader - input enable in sleep mode"]
+pub type X32P_SLP_IE_R = crate::BitReader;
+#[doc = "Field `X32P_SLP_IE` writer - input enable in sleep mode"]
+pub type X32P_SLP_IE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `X32P_SLP_SEL` reader - 1: enable sleep mode during sleep,0: no sleep mode"]
+pub type X32P_SLP_SEL_R = crate::BitReader;
+#[doc = "Field `X32P_SLP_SEL` writer - 1: enable sleep mode during sleep,0: no sleep mode"]
+pub type X32P_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `X32P_FUN_SEL` reader - function sel"]
+pub type X32P_FUN_SEL_R = crate::FieldReader;
+#[doc = "Field `X32P_FUN_SEL` writer - function sel"]
+pub type X32P_FUN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `X32P_MUX_SEL` reader - 1: use RTC GPIO,0: use digital GPIO"]
+pub type X32P_MUX_SEL_R = crate::BitReader;
+#[doc = "Field `X32P_MUX_SEL` writer - 1: use RTC GPIO,0: use digital GPIO"]
+pub type X32P_MUX_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `X32P_RUE` reader - RUE"]
+pub type X32P_RUE_R = crate::BitReader;
+#[doc = "Field `X32P_RUE` writer - RUE"]
+pub type X32P_RUE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `X32P_RDE` reader - RDE"]
+pub type X32P_RDE_R = crate::BitReader;
+#[doc = "Field `X32P_RDE` writer - RDE"]
+pub type X32P_RDE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `X32P_DRV` reader - DRV"]
+pub type X32P_DRV_R = crate::FieldReader;
+#[doc = "Field `X32P_DRV` writer - DRV"]
+pub type X32P_DRV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+impl R {
+    #[doc = "Bit 13 - input enable in work mode"]
+    #[inline(always)]
+    pub fn x32p_fun_ie(&self) -> X32P_FUN_IE_R {
+        X32P_FUN_IE_R::new(((self.bits >> 13) & 1) != 0)
+    }
+    #[doc = "Bit 14 - output enable in sleep mode"]
+    #[inline(always)]
+    pub fn x32p_slp_oe(&self) -> X32P_SLP_OE_R {
+        X32P_SLP_OE_R::new(((self.bits >> 14) & 1) != 0)
+    }
+    #[doc = "Bit 15 - input enable in sleep mode"]
+    #[inline(always)]
+    pub fn x32p_slp_ie(&self) -> X32P_SLP_IE_R {
+        X32P_SLP_IE_R::new(((self.bits >> 15) & 1) != 0)
+    }
+    #[doc = "Bit 16 - 1: enable sleep mode during sleep,0: no sleep mode"]
+    #[inline(always)]
+    pub fn x32p_slp_sel(&self) -> X32P_SLP_SEL_R {
+        X32P_SLP_SEL_R::new(((self.bits >> 16) & 1) != 0)
+    }
+    #[doc = "Bits 17:18 - function sel"]
+    #[inline(always)]
+    pub fn x32p_fun_sel(&self) -> X32P_FUN_SEL_R {
+        X32P_FUN_SEL_R::new(((self.bits >> 17) & 3) as u8)
+    }
+    #[doc = "Bit 19 - 1: use RTC GPIO,0: use digital GPIO"]
+    #[inline(always)]
+    pub fn x32p_mux_sel(&self) -> X32P_MUX_SEL_R {
+        X32P_MUX_SEL_R::new(((self.bits >> 19) & 1) != 0)
+    }
+    #[doc = "Bit 27 - RUE"]
+    #[inline(always)]
+    pub fn x32p_rue(&self) -> X32P_RUE_R {
+        X32P_RUE_R::new(((self.bits >> 27) & 1) != 0)
+    }
+    #[doc = "Bit 28 - RDE"]
+    #[inline(always)]
+    pub fn x32p_rde(&self) -> X32P_RDE_R {
+        X32P_RDE_R::new(((self.bits >> 28) & 1) != 0)
+    }
+    #[doc = "Bits 29:30 - DRV"]
+    #[inline(always)]
+    pub fn x32p_drv(&self) -> X32P_DRV_R {
+        X32P_DRV_R::new(((self.bits >> 29) & 3) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("XTAL_32P_PAD")
+            .field("x32p_fun_ie", &self.x32p_fun_ie())
+            .field("x32p_slp_oe", &self.x32p_slp_oe())
+            .field("x32p_slp_ie", &self.x32p_slp_ie())
+            .field("x32p_slp_sel", &self.x32p_slp_sel())
+            .field("x32p_fun_sel", &self.x32p_fun_sel())
+            .field("x32p_mux_sel", &self.x32p_mux_sel())
+            .field("x32p_rue", &self.x32p_rue())
+            .field("x32p_rde", &self.x32p_rde())
+            .field("x32p_drv", &self.x32p_drv())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 13 - input enable in work mode"]
+    #[inline(always)]
+    pub fn x32p_fun_ie(&mut self) -> X32P_FUN_IE_W<XTAL_32P_PAD_SPEC> {
+        X32P_FUN_IE_W::new(self, 13)
+    }
+    #[doc = "Bit 14 - output enable in sleep mode"]
+    #[inline(always)]
+    pub fn x32p_slp_oe(&mut self) -> X32P_SLP_OE_W<XTAL_32P_PAD_SPEC> {
+        X32P_SLP_OE_W::new(self, 14)
+    }
+    #[doc = "Bit 15 - input enable in sleep mode"]
+    #[inline(always)]
+    pub fn x32p_slp_ie(&mut self) -> X32P_SLP_IE_W<XTAL_32P_PAD_SPEC> {
+        X32P_SLP_IE_W::new(self, 15)
+    }
+    #[doc = "Bit 16 - 1: enable sleep mode during sleep,0: no sleep mode"]
+    #[inline(always)]
+    pub fn x32p_slp_sel(&mut self) -> X32P_SLP_SEL_W<XTAL_32P_PAD_SPEC> {
+        X32P_SLP_SEL_W::new(self, 16)
+    }
+    #[doc = "Bits 17:18 - function sel"]
+    #[inline(always)]
+    pub fn x32p_fun_sel(&mut self) -> X32P_FUN_SEL_W<XTAL_32P_PAD_SPEC> {
+        X32P_FUN_SEL_W::new(self, 17)
+    }
+    #[doc = "Bit 19 - 1: use RTC GPIO,0: use digital GPIO"]
+    #[inline(always)]
+    pub fn x32p_mux_sel(&mut self) -> X32P_MUX_SEL_W<XTAL_32P_PAD_SPEC> {
+        X32P_MUX_SEL_W::new(self, 19)
+    }
+    #[doc = "Bit 27 - RUE"]
+    #[inline(always)]
+    pub fn x32p_rue(&mut self) -> X32P_RUE_W<XTAL_32P_PAD_SPEC> {
+        X32P_RUE_W::new(self, 27)
+    }
+    #[doc = "Bit 28 - RDE"]
+    #[inline(always)]
+    pub fn x32p_rde(&mut self) -> X32P_RDE_W<XTAL_32P_PAD_SPEC> {
+        X32P_RDE_W::new(self, 28)
+    }
+    #[doc = "Bits 29:30 - DRV"]
+    #[inline(always)]
+    pub fn x32p_drv(&mut self) -> X32P_DRV_W<XTAL_32P_PAD_SPEC> {
+        X32P_DRV_W::new(self, 29)
+    }
+}
+#[doc = "configure RTC PAD15\n\nYou can [`read`](crate::Reg::read) this register and get [`xtal_32p_pad::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`xtal_32p_pad::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct XTAL_32P_PAD_SPEC;
+impl crate::RegisterSpec for XTAL_32P_PAD_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`xtal_32p_pad::R`](R) reader structure"]
+impl crate::Readable for XTAL_32P_PAD_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`xtal_32p_pad::W`](W) writer structure"]
+impl crate::Writable for XTAL_32P_PAD_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets XTAL_32P_PAD to value 0x4000_0000"]
+impl crate::Resettable for XTAL_32P_PAD_SPEC {
+    const RESET_VALUE: u32 = 0x4000_0000;
+}

vendor/esp32s3/src/rtc_io/xtl_ext_ctr.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `XTL_EXT_CTR` reader"]
+pub type R = crate::R<XTL_EXT_CTR_SPEC>;
+#[doc = "Register `XTL_EXT_CTR` writer"]
+pub type W = crate::W<XTL_EXT_CTR_SPEC>;
+#[doc = "Field `SEL` reader - select RTC GPIO 0 ~ 17 to control XTAL"]
+pub type SEL_R = crate::FieldReader;
+#[doc = "Field `SEL` writer - select RTC GPIO 0 ~ 17 to control XTAL"]
+pub type SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
+impl R {
+    #[doc = "Bits 27:31 - select RTC GPIO 0 ~ 17 to control XTAL"]
+    #[inline(always)]
+    pub fn sel(&self) -> SEL_R {
+        SEL_R::new(((self.bits >> 27) & 0x1f) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("XTL_EXT_CTR")
+            .field("sel", &self.sel())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 27:31 - select RTC GPIO 0 ~ 17 to control XTAL"]
+    #[inline(always)]
+    pub fn sel(&mut self) -> SEL_W<XTL_EXT_CTR_SPEC> {
+        SEL_W::new(self, 27)
+    }
+}
+#[doc = "configure gpio pd XTAL\n\nYou can [`read`](crate::Reg::read) this register and get [`xtl_ext_ctr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`xtl_ext_ctr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct XTL_EXT_CTR_SPEC;
+impl crate::RegisterSpec for XTL_EXT_CTR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`xtl_ext_ctr::R`](R) reader structure"]
+impl crate::Readable for XTL_EXT_CTR_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`xtl_ext_ctr::W`](W) writer structure"]
+impl crate::Writable for XTL_EXT_CTR_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets XTL_EXT_CTR to value 0"]
+impl crate::Resettable for XTL_EXT_CTR_SPEC {
+    const RESET_VALUE: u32 = 0;
+}