feat: add display UI with splash screen, dashboard, and RSSI sparkline

Implement full SSD1306 OLED display support:
- Splash screen on boot (1.5s) with project name, version, board
- Dashboard showing radio state, config, counters, RSSI/SNR
- RSSI history sparkline (64-sample ring buffer, 2px-wide bars)
- DisplayOn/DisplayOff host commands routed via dedicated channel
- Pure render functions against generic DrawTarget (no hardware coupling)
- Display on/off control bypasses radio task entirely

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>

vendor/esp32s3/src/sdhost/blksiz.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `BLKSIZ` reader"]
+pub type R = crate::R<BLKSIZ_SPEC>;
+#[doc = "Register `BLKSIZ` writer"]
+pub type W = crate::W<BLKSIZ_SPEC>;
+#[doc = "Field `BLOCK_SIZE` reader - Block size."]
+pub type BLOCK_SIZE_R = crate::FieldReader<u16>;
+#[doc = "Field `BLOCK_SIZE` writer - Block size."]
+pub type BLOCK_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
+impl R {
+    #[doc = "Bits 0:15 - Block size."]
+    #[inline(always)]
+    pub fn block_size(&self) -> BLOCK_SIZE_R {
+        BLOCK_SIZE_R::new((self.bits & 0xffff) as u16)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("BLKSIZ")
+            .field("block_size", &self.block_size())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:15 - Block size."]
+    #[inline(always)]
+    pub fn block_size(&mut self) -> BLOCK_SIZE_W<BLKSIZ_SPEC> {
+        BLOCK_SIZE_W::new(self, 0)
+    }
+}
+#[doc = "Card data block size configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`blksiz::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`blksiz::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct BLKSIZ_SPEC;
+impl crate::RegisterSpec for BLKSIZ_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`blksiz::R`](R) reader structure"]
+impl crate::Readable for BLKSIZ_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`blksiz::W`](W) writer structure"]
+impl crate::Writable for BLKSIZ_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets BLKSIZ to value 0x0200"]
+impl crate::Resettable for BLKSIZ_SPEC {
+    const RESET_VALUE: u32 = 0x0200;
+}

vendor/esp32s3/src/sdhost/bmod.rs

@@ -0,0 +1,92 @@
+#[doc = "Register `BMOD` reader"]
+pub type R = crate::R<BMOD_SPEC>;
+#[doc = "Register `BMOD` writer"]
+pub type W = crate::W<BMOD_SPEC>;
+#[doc = "Field `SWR` reader - Software Reset. When set, the DMA Controller resets all its internal registers. It is automatically cleared after one clock cycle."]
+pub type SWR_R = crate::BitReader;
+#[doc = "Field `SWR` writer - Software Reset. When set, the DMA Controller resets all its internal registers. It is automatically cleared after one clock cycle."]
+pub type SWR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FB` reader - Fixed Burst. Controls whether the AHB Master interface performs fixed burst transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst transfers. When reset, the AHB will use SINGLE and INCR burst transfer operations."]
+pub type FB_R = crate::BitReader;
+#[doc = "Field `FB` writer - Fixed Burst. Controls whether the AHB Master interface performs fixed burst transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst transfers. When reset, the AHB will use SINGLE and INCR burst transfer operations."]
+pub type FB_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DE` reader - IDMAC Enable. When set, the IDMAC is enabled."]
+pub type DE_R = crate::BitReader;
+#[doc = "Field `DE` writer - IDMAC Enable. When set, the IDMAC is enabled."]
+pub type DE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PBL` reader - Programmable Burst Length. These bits indicate the maximum number of beats to be performed in one IDMAC???Internal DMA Control???transaction. The IDMAC will always attempt to burst as specified in PBL each time it starts a burst transfer on the host bus. The permissible values are 1, 4, 8, 16, 32, 64, 128 and 256. This value is the mirror of MSIZE of FIFOTH register. In order to change this value, write the required value to FIFOTH register. This is an encode value as follows: 000: 1-byte transfer; 001: 4-byte transfer; 010: 8-byte transfer; 011: 16-byte transfer; 100: 32-byte transfer; 101: 64-byte transfer; 110: 128-byte transfer; 111: 256-byte transfer. PBL is a read-only value and is applicable only for data access, it does not apply to descriptor access."]
+pub type PBL_R = crate::FieldReader;
+#[doc = "Field `PBL` writer - Programmable Burst Length. These bits indicate the maximum number of beats to be performed in one IDMAC???Internal DMA Control???transaction. The IDMAC will always attempt to burst as specified in PBL each time it starts a burst transfer on the host bus. The permissible values are 1, 4, 8, 16, 32, 64, 128 and 256. This value is the mirror of MSIZE of FIFOTH register. In order to change this value, write the required value to FIFOTH register. This is an encode value as follows: 000: 1-byte transfer; 001: 4-byte transfer; 010: 8-byte transfer; 011: 16-byte transfer; 100: 32-byte transfer; 101: 64-byte transfer; 110: 128-byte transfer; 111: 256-byte transfer. PBL is a read-only value and is applicable only for data access, it does not apply to descriptor access."]
+pub type PBL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+impl R {
+    #[doc = "Bit 0 - Software Reset. When set, the DMA Controller resets all its internal registers. It is automatically cleared after one clock cycle."]
+    #[inline(always)]
+    pub fn swr(&self) -> SWR_R {
+        SWR_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Fixed Burst. Controls whether the AHB Master interface performs fixed burst transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst transfers. When reset, the AHB will use SINGLE and INCR burst transfer operations."]
+    #[inline(always)]
+    pub fn fb(&self) -> FB_R {
+        FB_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 7 - IDMAC Enable. When set, the IDMAC is enabled."]
+    #[inline(always)]
+    pub fn de(&self) -> DE_R {
+        DE_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bits 8:10 - Programmable Burst Length. These bits indicate the maximum number of beats to be performed in one IDMAC???Internal DMA Control???transaction. The IDMAC will always attempt to burst as specified in PBL each time it starts a burst transfer on the host bus. The permissible values are 1, 4, 8, 16, 32, 64, 128 and 256. This value is the mirror of MSIZE of FIFOTH register. In order to change this value, write the required value to FIFOTH register. This is an encode value as follows: 000: 1-byte transfer; 001: 4-byte transfer; 010: 8-byte transfer; 011: 16-byte transfer; 100: 32-byte transfer; 101: 64-byte transfer; 110: 128-byte transfer; 111: 256-byte transfer. PBL is a read-only value and is applicable only for data access, it does not apply to descriptor access."]
+    #[inline(always)]
+    pub fn pbl(&self) -> PBL_R {
+        PBL_R::new(((self.bits >> 8) & 7) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("BMOD")
+            .field("swr", &self.swr())
+            .field("fb", &self.fb())
+            .field("de", &self.de())
+            .field("pbl", &self.pbl())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Software Reset. When set, the DMA Controller resets all its internal registers. It is automatically cleared after one clock cycle."]
+    #[inline(always)]
+    pub fn swr(&mut self) -> SWR_W<BMOD_SPEC> {
+        SWR_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - Fixed Burst. Controls whether the AHB Master interface performs fixed burst transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst transfers. When reset, the AHB will use SINGLE and INCR burst transfer operations."]
+    #[inline(always)]
+    pub fn fb(&mut self) -> FB_W<BMOD_SPEC> {
+        FB_W::new(self, 1)
+    }
+    #[doc = "Bit 7 - IDMAC Enable. When set, the IDMAC is enabled."]
+    #[inline(always)]
+    pub fn de(&mut self) -> DE_W<BMOD_SPEC> {
+        DE_W::new(self, 7)
+    }
+    #[doc = "Bits 8:10 - Programmable Burst Length. These bits indicate the maximum number of beats to be performed in one IDMAC???Internal DMA Control???transaction. The IDMAC will always attempt to burst as specified in PBL each time it starts a burst transfer on the host bus. The permissible values are 1, 4, 8, 16, 32, 64, 128 and 256. This value is the mirror of MSIZE of FIFOTH register. In order to change this value, write the required value to FIFOTH register. This is an encode value as follows: 000: 1-byte transfer; 001: 4-byte transfer; 010: 8-byte transfer; 011: 16-byte transfer; 100: 32-byte transfer; 101: 64-byte transfer; 110: 128-byte transfer; 111: 256-byte transfer. PBL is a read-only value and is applicable only for data access, it does not apply to descriptor access."]
+    #[inline(always)]
+    pub fn pbl(&mut self) -> PBL_W<BMOD_SPEC> {
+        PBL_W::new(self, 8)
+    }
+}
+#[doc = "Burst mode transfer configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`bmod::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bmod::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct BMOD_SPEC;
+impl crate::RegisterSpec for BMOD_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`bmod::R`](R) reader structure"]
+impl crate::Readable for BMOD_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`bmod::W`](W) writer structure"]
+impl crate::Writable for BMOD_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets BMOD to value 0"]
+impl crate::Resettable for BMOD_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sdhost/bufaddr.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `BUFADDR` reader"]
+pub type R = crate::R<BUFADDR_SPEC>;
+#[doc = "Field `BUFADDR` reader - Host Buffer Address Pointer, updated by IDMAC during operation and cleared on reset. This register points to the current Data Buffer Address being accessed by the IDMAC."]
+pub type BUFADDR_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - Host Buffer Address Pointer, updated by IDMAC during operation and cleared on reset. This register points to the current Data Buffer Address being accessed by the IDMAC."]
+    #[inline(always)]
+    pub fn bufaddr(&self) -> BUFADDR_R {
+        BUFADDR_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("BUFADDR")
+            .field("bufaddr", &self.bufaddr())
+            .finish()
+    }
+}
+#[doc = "Host buffer address pointer register\n\nYou can [`read`](crate::Reg::read) this register and get [`bufaddr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct BUFADDR_SPEC;
+impl crate::RegisterSpec for BUFADDR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`bufaddr::R`](R) reader structure"]
+impl crate::Readable for BUFADDR_SPEC {}
+#[doc = "`reset()` method sets BUFADDR to value 0"]
+impl crate::Resettable for BUFADDR_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sdhost/buffifo.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `BUFFIFO` reader"]
+pub type R = crate::R<BUFFIFO_SPEC>;
+#[doc = "Register `BUFFIFO` writer"]
+pub type W = crate::W<BUFFIFO_SPEC>;
+#[doc = "Field `BUFFIFO` reader - CPU write and read transmit data by FIFO. This register points to the current Data FIFO ."]
+pub type BUFFIFO_R = crate::FieldReader<u32>;
+#[doc = "Field `BUFFIFO` writer - CPU write and read transmit data by FIFO. This register points to the current Data FIFO ."]
+pub type BUFFIFO_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - CPU write and read transmit data by FIFO. This register points to the current Data FIFO ."]
+    #[inline(always)]
+    pub fn buffifo(&self) -> BUFFIFO_R {
+        BUFFIFO_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("BUFFIFO")
+            .field("buffifo", &self.buffifo())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - CPU write and read transmit data by FIFO. This register points to the current Data FIFO ."]
+    #[inline(always)]
+    pub fn buffifo(&mut self) -> BUFFIFO_W<BUFFIFO_SPEC> {
+        BUFFIFO_W::new(self, 0)
+    }
+}
+#[doc = "CPU write and read transmit data by FIFO\n\nYou can [`read`](crate::Reg::read) this register and get [`buffifo::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`buffifo::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct BUFFIFO_SPEC;
+impl crate::RegisterSpec for BUFFIFO_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`buffifo::R`](R) reader structure"]
+impl crate::Readable for BUFFIFO_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`buffifo::W`](W) writer structure"]
+impl crate::Writable for BUFFIFO_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets BUFFIFO to value 0"]
+impl crate::Resettable for BUFFIFO_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sdhost/bytcnt.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `BYTCNT` reader"]
+pub type R = crate::R<BYTCNT_SPEC>;
+#[doc = "Register `BYTCNT` writer"]
+pub type W = crate::W<BYTCNT_SPEC>;
+#[doc = "Field `BYTE_COUNT` reader - Number of bytes to be transferred, should be an integral multiple of Block Size for block transfers. For data transfers of undefined byte lengths, byte count should be set to 0. When byte count is set to 0, it is the responsibility of host to explicitly send stop/abort command to terminate data transfer."]
+pub type BYTE_COUNT_R = crate::FieldReader<u32>;
+#[doc = "Field `BYTE_COUNT` writer - Number of bytes to be transferred, should be an integral multiple of Block Size for block transfers. For data transfers of undefined byte lengths, byte count should be set to 0. When byte count is set to 0, it is the responsibility of host to explicitly send stop/abort command to terminate data transfer."]
+pub type BYTE_COUNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - Number of bytes to be transferred, should be an integral multiple of Block Size for block transfers. For data transfers of undefined byte lengths, byte count should be set to 0. When byte count is set to 0, it is the responsibility of host to explicitly send stop/abort command to terminate data transfer."]
+    #[inline(always)]
+    pub fn byte_count(&self) -> BYTE_COUNT_R {
+        BYTE_COUNT_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("BYTCNT")
+            .field("byte_count", &self.byte_count())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Number of bytes to be transferred, should be an integral multiple of Block Size for block transfers. For data transfers of undefined byte lengths, byte count should be set to 0. When byte count is set to 0, it is the responsibility of host to explicitly send stop/abort command to terminate data transfer."]
+    #[inline(always)]
+    pub fn byte_count(&mut self) -> BYTE_COUNT_W<BYTCNT_SPEC> {
+        BYTE_COUNT_W::new(self, 0)
+    }
+}
+#[doc = "Data transfer length configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`bytcnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bytcnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct BYTCNT_SPEC;
+impl crate::RegisterSpec for BYTCNT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`bytcnt::R`](R) reader structure"]
+impl crate::Readable for BYTCNT_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`bytcnt::W`](W) writer structure"]
+impl crate::Writable for BYTCNT_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets BYTCNT to value 0x0200"]
+impl crate::Resettable for BYTCNT_SPEC {
+    const RESET_VALUE: u32 = 0x0200;
+}

vendor/esp32s3/src/sdhost/cardthrctl.rs

@@ -0,0 +1,92 @@
+#[doc = "Register `CARDTHRCTL` reader"]
+pub type R = crate::R<CARDTHRCTL_SPEC>;
+#[doc = "Register `CARDTHRCTL` writer"]
+pub type W = crate::W<CARDTHRCTL_SPEC>;
+#[doc = "Field `CARDRDTHREN` reader - Card read threshold enable. 1'b0-Card read threshold disabled. 1'b1-Card read threshold enabled."]
+pub type CARDRDTHREN_R = crate::BitReader;
+#[doc = "Field `CARDRDTHREN` writer - Card read threshold enable. 1'b0-Card read threshold disabled. 1'b1-Card read threshold enabled."]
+pub type CARDRDTHREN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CARDCLRINTEN` reader - Busy clear interrupt generation: 1'b0-Busy clear interrypt disabled. 1'b1-Busy clear interrypt enabled."]
+pub type CARDCLRINTEN_R = crate::BitReader;
+#[doc = "Field `CARDCLRINTEN` writer - Busy clear interrupt generation: 1'b0-Busy clear interrypt disabled. 1'b1-Busy clear interrypt enabled."]
+pub type CARDCLRINTEN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CARDWRTHREN` reader - Applicable when HS400 mode is enabled. 1'b0-Card write Threshold disabled. 1'b1-Card write Threshold enabled."]
+pub type CARDWRTHREN_R = crate::BitReader;
+#[doc = "Field `CARDWRTHREN` writer - Applicable when HS400 mode is enabled. 1'b0-Card write Threshold disabled. 1'b1-Card write Threshold enabled."]
+pub type CARDWRTHREN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CARDTHRESHOLD` reader - The inside FIFO size is 512,This register is applicable when SDHOST_CARDERTHREN_REG is set to 1 or SDHOST_CARDRDTHREN_REG set to 1."]
+pub type CARDTHRESHOLD_R = crate::FieldReader<u16>;
+#[doc = "Field `CARDTHRESHOLD` writer - The inside FIFO size is 512,This register is applicable when SDHOST_CARDERTHREN_REG is set to 1 or SDHOST_CARDRDTHREN_REG set to 1."]
+pub type CARDTHRESHOLD_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
+impl R {
+    #[doc = "Bit 0 - Card read threshold enable. 1'b0-Card read threshold disabled. 1'b1-Card read threshold enabled."]
+    #[inline(always)]
+    pub fn cardrdthren(&self) -> CARDRDTHREN_R {
+        CARDRDTHREN_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Busy clear interrupt generation: 1'b0-Busy clear interrypt disabled. 1'b1-Busy clear interrypt enabled."]
+    #[inline(always)]
+    pub fn cardclrinten(&self) -> CARDCLRINTEN_R {
+        CARDCLRINTEN_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Applicable when HS400 mode is enabled. 1'b0-Card write Threshold disabled. 1'b1-Card write Threshold enabled."]
+    #[inline(always)]
+    pub fn cardwrthren(&self) -> CARDWRTHREN_R {
+        CARDWRTHREN_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bits 16:31 - The inside FIFO size is 512,This register is applicable when SDHOST_CARDERTHREN_REG is set to 1 or SDHOST_CARDRDTHREN_REG set to 1."]
+    #[inline(always)]
+    pub fn cardthreshold(&self) -> CARDTHRESHOLD_R {
+        CARDTHRESHOLD_R::new(((self.bits >> 16) & 0xffff) as u16)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CARDTHRCTL")
+            .field("cardrdthren", &self.cardrdthren())
+            .field("cardclrinten", &self.cardclrinten())
+            .field("cardwrthren", &self.cardwrthren())
+            .field("cardthreshold", &self.cardthreshold())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Card read threshold enable. 1'b0-Card read threshold disabled. 1'b1-Card read threshold enabled."]
+    #[inline(always)]
+    pub fn cardrdthren(&mut self) -> CARDRDTHREN_W<CARDTHRCTL_SPEC> {
+        CARDRDTHREN_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - Busy clear interrupt generation: 1'b0-Busy clear interrypt disabled. 1'b1-Busy clear interrypt enabled."]
+    #[inline(always)]
+    pub fn cardclrinten(&mut self) -> CARDCLRINTEN_W<CARDTHRCTL_SPEC> {
+        CARDCLRINTEN_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - Applicable when HS400 mode is enabled. 1'b0-Card write Threshold disabled. 1'b1-Card write Threshold enabled."]
+    #[inline(always)]
+    pub fn cardwrthren(&mut self) -> CARDWRTHREN_W<CARDTHRCTL_SPEC> {
+        CARDWRTHREN_W::new(self, 2)
+    }
+    #[doc = "Bits 16:31 - The inside FIFO size is 512,This register is applicable when SDHOST_CARDERTHREN_REG is set to 1 or SDHOST_CARDRDTHREN_REG set to 1."]
+    #[inline(always)]
+    pub fn cardthreshold(&mut self) -> CARDTHRESHOLD_W<CARDTHRCTL_SPEC> {
+        CARDTHRESHOLD_W::new(self, 16)
+    }
+}
+#[doc = "Card Threshold Control register\n\nYou can [`read`](crate::Reg::read) this register and get [`cardthrctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cardthrctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CARDTHRCTL_SPEC;
+impl crate::RegisterSpec for CARDTHRCTL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cardthrctl::R`](R) reader structure"]
+impl crate::Readable for CARDTHRCTL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`cardthrctl::W`](W) writer structure"]
+impl crate::Writable for CARDTHRCTL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CARDTHRCTL to value 0"]
+impl crate::Resettable for CARDTHRCTL_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sdhost/cdetect.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `CDETECT` reader"]
+pub type R = crate::R<CDETECT_SPEC>;
+#[doc = "Field `CARD_DETECT_N` reader - Value on sdhost_card_detect_n input ports (1 bit per card), read-only bits. 0 represents presence of card. Only NUM_CARDS number of bits are implemented."]
+pub type CARD_DETECT_N_R = crate::FieldReader;
+impl R {
+    #[doc = "Bits 0:1 - Value on sdhost_card_detect_n input ports (1 bit per card), read-only bits. 0 represents presence of card. Only NUM_CARDS number of bits are implemented."]
+    #[inline(always)]
+    pub fn card_detect_n(&self) -> CARD_DETECT_N_R {
+        CARD_DETECT_N_R::new((self.bits & 3) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CDETECT")
+            .field("card_detect_n", &self.card_detect_n())
+            .finish()
+    }
+}
+#[doc = "Card detect register\n\nYou can [`read`](crate::Reg::read) this register and get [`cdetect::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CDETECT_SPEC;
+impl crate::RegisterSpec for CDETECT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cdetect::R`](R) reader structure"]
+impl crate::Readable for CDETECT_SPEC {}
+#[doc = "`reset()` method sets CDETECT to value 0"]
+impl crate::Resettable for CDETECT_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sdhost/clk_edge_sel.rs

@@ -0,0 +1,167 @@
+#[doc = "Register `CLK_EDGE_SEL` reader"]
+pub type R = crate::R<CLK_EDGE_SEL_SPEC>;
+#[doc = "Register `CLK_EDGE_SEL` writer"]
+pub type W = crate::W<CLK_EDGE_SEL_SPEC>;
+#[doc = "Field `CCLKIN_EDGE_DRV_SEL` reader - It's used to select the clock phase of the output signal from phase 0, phase 90, phase 180, phase 270."]
+pub type CCLKIN_EDGE_DRV_SEL_R = crate::FieldReader;
+#[doc = "Field `CCLKIN_EDGE_DRV_SEL` writer - It's used to select the clock phase of the output signal from phase 0, phase 90, phase 180, phase 270."]
+pub type CCLKIN_EDGE_DRV_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `CCLKIN_EDGE_SAM_SEL` reader - It's used to select the clock phase of the input signal from phase 0, phase 90, phase 180, phase 270."]
+pub type CCLKIN_EDGE_SAM_SEL_R = crate::FieldReader;
+#[doc = "Field `CCLKIN_EDGE_SAM_SEL` writer - It's used to select the clock phase of the input signal from phase 0, phase 90, phase 180, phase 270."]
+pub type CCLKIN_EDGE_SAM_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `CCLKIN_EDGE_SLF_SEL` reader - It's used to select the clock phase of the internal signal from phase 0, phase 90, phase 180, phase 270."]
+pub type CCLKIN_EDGE_SLF_SEL_R = crate::FieldReader;
+#[doc = "Field `CCLKIN_EDGE_SLF_SEL` writer - It's used to select the clock phase of the internal signal from phase 0, phase 90, phase 180, phase 270."]
+pub type CCLKIN_EDGE_SLF_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `CCLLKIN_EDGE_H` reader - The high level of the divider clock. The value should be smaller than CCLKIN_EDGE_L."]
+pub type CCLLKIN_EDGE_H_R = crate::FieldReader;
+#[doc = "Field `CCLLKIN_EDGE_H` writer - The high level of the divider clock. The value should be smaller than CCLKIN_EDGE_L."]
+pub type CCLLKIN_EDGE_H_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `CCLLKIN_EDGE_L` reader - The low level of the divider clock. The value should be larger than CCLKIN_EDGE_H."]
+pub type CCLLKIN_EDGE_L_R = crate::FieldReader;
+#[doc = "Field `CCLLKIN_EDGE_L` writer - The low level of the divider clock. The value should be larger than CCLKIN_EDGE_H."]
+pub type CCLLKIN_EDGE_L_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `CCLLKIN_EDGE_N` reader - The clock division of cclk_in."]
+pub type CCLLKIN_EDGE_N_R = crate::FieldReader;
+#[doc = "Field `CCLLKIN_EDGE_N` writer - The clock division of cclk_in."]
+pub type CCLLKIN_EDGE_N_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `ESDIO_MODE` reader - Enable esdio mode."]
+pub type ESDIO_MODE_R = crate::BitReader;
+#[doc = "Field `ESDIO_MODE` writer - Enable esdio mode."]
+pub type ESDIO_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ESD_MODE` reader - Enable esd mode."]
+pub type ESD_MODE_R = crate::BitReader;
+#[doc = "Field `ESD_MODE` writer - Enable esd mode."]
+pub type ESD_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CCLK_EN` reader - Sdio clock enable."]
+pub type CCLK_EN_R = crate::BitReader;
+#[doc = "Field `CCLK_EN` writer - Sdio clock enable."]
+pub type CCLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 0:2 - It's used to select the clock phase of the output signal from phase 0, phase 90, phase 180, phase 270."]
+    #[inline(always)]
+    pub fn cclkin_edge_drv_sel(&self) -> CCLKIN_EDGE_DRV_SEL_R {
+        CCLKIN_EDGE_DRV_SEL_R::new((self.bits & 7) as u8)
+    }
+    #[doc = "Bits 3:5 - It's used to select the clock phase of the input signal from phase 0, phase 90, phase 180, phase 270."]
+    #[inline(always)]
+    pub fn cclkin_edge_sam_sel(&self) -> CCLKIN_EDGE_SAM_SEL_R {
+        CCLKIN_EDGE_SAM_SEL_R::new(((self.bits >> 3) & 7) as u8)
+    }
+    #[doc = "Bits 6:8 - It's used to select the clock phase of the internal signal from phase 0, phase 90, phase 180, phase 270."]
+    #[inline(always)]
+    pub fn cclkin_edge_slf_sel(&self) -> CCLKIN_EDGE_SLF_SEL_R {
+        CCLKIN_EDGE_SLF_SEL_R::new(((self.bits >> 6) & 7) as u8)
+    }
+    #[doc = "Bits 9:12 - The high level of the divider clock. The value should be smaller than CCLKIN_EDGE_L."]
+    #[inline(always)]
+    pub fn ccllkin_edge_h(&self) -> CCLLKIN_EDGE_H_R {
+        CCLLKIN_EDGE_H_R::new(((self.bits >> 9) & 0x0f) as u8)
+    }
+    #[doc = "Bits 13:16 - The low level of the divider clock. The value should be larger than CCLKIN_EDGE_H."]
+    #[inline(always)]
+    pub fn ccllkin_edge_l(&self) -> CCLLKIN_EDGE_L_R {
+        CCLLKIN_EDGE_L_R::new(((self.bits >> 13) & 0x0f) as u8)
+    }
+    #[doc = "Bits 17:20 - The clock division of cclk_in."]
+    #[inline(always)]
+    pub fn ccllkin_edge_n(&self) -> CCLLKIN_EDGE_N_R {
+        CCLLKIN_EDGE_N_R::new(((self.bits >> 17) & 0x0f) as u8)
+    }
+    #[doc = "Bit 21 - Enable esdio mode."]
+    #[inline(always)]
+    pub fn esdio_mode(&self) -> ESDIO_MODE_R {
+        ESDIO_MODE_R::new(((self.bits >> 21) & 1) != 0)
+    }
+    #[doc = "Bit 22 - Enable esd mode."]
+    #[inline(always)]
+    pub fn esd_mode(&self) -> ESD_MODE_R {
+        ESD_MODE_R::new(((self.bits >> 22) & 1) != 0)
+    }
+    #[doc = "Bit 23 - Sdio clock enable."]
+    #[inline(always)]
+    pub fn cclk_en(&self) -> CCLK_EN_R {
+        CCLK_EN_R::new(((self.bits >> 23) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CLK_EDGE_SEL")
+            .field("cclkin_edge_drv_sel", &self.cclkin_edge_drv_sel())
+            .field("cclkin_edge_sam_sel", &self.cclkin_edge_sam_sel())
+            .field("cclkin_edge_slf_sel", &self.cclkin_edge_slf_sel())
+            .field("ccllkin_edge_h", &self.ccllkin_edge_h())
+            .field("ccllkin_edge_l", &self.ccllkin_edge_l())
+            .field("ccllkin_edge_n", &self.ccllkin_edge_n())
+            .field("esdio_mode", &self.esdio_mode())
+            .field("esd_mode", &self.esd_mode())
+            .field("cclk_en", &self.cclk_en())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:2 - It's used to select the clock phase of the output signal from phase 0, phase 90, phase 180, phase 270."]
+    #[inline(always)]
+    pub fn cclkin_edge_drv_sel(&mut self) -> CCLKIN_EDGE_DRV_SEL_W<CLK_EDGE_SEL_SPEC> {
+        CCLKIN_EDGE_DRV_SEL_W::new(self, 0)
+    }
+    #[doc = "Bits 3:5 - It's used to select the clock phase of the input signal from phase 0, phase 90, phase 180, phase 270."]
+    #[inline(always)]
+    pub fn cclkin_edge_sam_sel(&mut self) -> CCLKIN_EDGE_SAM_SEL_W<CLK_EDGE_SEL_SPEC> {
+        CCLKIN_EDGE_SAM_SEL_W::new(self, 3)
+    }
+    #[doc = "Bits 6:8 - It's used to select the clock phase of the internal signal from phase 0, phase 90, phase 180, phase 270."]
+    #[inline(always)]
+    pub fn cclkin_edge_slf_sel(&mut self) -> CCLKIN_EDGE_SLF_SEL_W<CLK_EDGE_SEL_SPEC> {
+        CCLKIN_EDGE_SLF_SEL_W::new(self, 6)
+    }
+    #[doc = "Bits 9:12 - The high level of the divider clock. The value should be smaller than CCLKIN_EDGE_L."]
+    #[inline(always)]
+    pub fn ccllkin_edge_h(&mut self) -> CCLLKIN_EDGE_H_W<CLK_EDGE_SEL_SPEC> {
+        CCLLKIN_EDGE_H_W::new(self, 9)
+    }
+    #[doc = "Bits 13:16 - The low level of the divider clock. The value should be larger than CCLKIN_EDGE_H."]
+    #[inline(always)]
+    pub fn ccllkin_edge_l(&mut self) -> CCLLKIN_EDGE_L_W<CLK_EDGE_SEL_SPEC> {
+        CCLLKIN_EDGE_L_W::new(self, 13)
+    }
+    #[doc = "Bits 17:20 - The clock division of cclk_in."]
+    #[inline(always)]
+    pub fn ccllkin_edge_n(&mut self) -> CCLLKIN_EDGE_N_W<CLK_EDGE_SEL_SPEC> {
+        CCLLKIN_EDGE_N_W::new(self, 17)
+    }
+    #[doc = "Bit 21 - Enable esdio mode."]
+    #[inline(always)]
+    pub fn esdio_mode(&mut self) -> ESDIO_MODE_W<CLK_EDGE_SEL_SPEC> {
+        ESDIO_MODE_W::new(self, 21)
+    }
+    #[doc = "Bit 22 - Enable esd mode."]
+    #[inline(always)]
+    pub fn esd_mode(&mut self) -> ESD_MODE_W<CLK_EDGE_SEL_SPEC> {
+        ESD_MODE_W::new(self, 22)
+    }
+    #[doc = "Bit 23 - Sdio clock enable."]
+    #[inline(always)]
+    pub fn cclk_en(&mut self) -> CCLK_EN_W<CLK_EDGE_SEL_SPEC> {
+        CCLK_EN_W::new(self, 23)
+    }
+}
+#[doc = "SDIO control register.\n\nYou can [`read`](crate::Reg::read) this register and get [`clk_edge_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_edge_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CLK_EDGE_SEL_SPEC;
+impl crate::RegisterSpec for CLK_EDGE_SEL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`clk_edge_sel::R`](R) reader structure"]
+impl crate::Readable for CLK_EDGE_SEL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`clk_edge_sel::W`](W) writer structure"]
+impl crate::Writable for CLK_EDGE_SEL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CLK_EDGE_SEL to value 0x0082_0200"]
+impl crate::Resettable for CLK_EDGE_SEL_SPEC {
+    const RESET_VALUE: u32 = 0x0082_0200;
+}

vendor/esp32s3/src/sdhost/clkdiv.rs

@@ -0,0 +1,92 @@
+#[doc = "Register `CLKDIV` reader"]
+pub type R = crate::R<CLKDIV_SPEC>;
+#[doc = "Register `CLKDIV` writer"]
+pub type W = crate::W<CLKDIV_SPEC>;
+#[doc = "Field `CLK_DIVIDER0` reader - Clock divider0 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on."]
+pub type CLK_DIVIDER0_R = crate::FieldReader;
+#[doc = "Field `CLK_DIVIDER0` writer - Clock divider0 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on."]
+pub type CLK_DIVIDER0_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+#[doc = "Field `CLK_DIVIDER1` reader - Clock divider1 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on."]
+pub type CLK_DIVIDER1_R = crate::FieldReader;
+#[doc = "Field `CLK_DIVIDER1` writer - Clock divider1 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on."]
+pub type CLK_DIVIDER1_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+#[doc = "Field `CLK_DIVIDER2` reader - Clock divider2 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on."]
+pub type CLK_DIVIDER2_R = crate::FieldReader;
+#[doc = "Field `CLK_DIVIDER2` writer - Clock divider2 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on."]
+pub type CLK_DIVIDER2_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+#[doc = "Field `CLK_DIVIDER3` reader - Clock divider3 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on."]
+pub type CLK_DIVIDER3_R = crate::FieldReader;
+#[doc = "Field `CLK_DIVIDER3` writer - Clock divider3 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on."]
+pub type CLK_DIVIDER3_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+impl R {
+    #[doc = "Bits 0:7 - Clock divider0 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on."]
+    #[inline(always)]
+    pub fn clk_divider0(&self) -> CLK_DIVIDER0_R {
+        CLK_DIVIDER0_R::new((self.bits & 0xff) as u8)
+    }
+    #[doc = "Bits 8:15 - Clock divider1 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on."]
+    #[inline(always)]
+    pub fn clk_divider1(&self) -> CLK_DIVIDER1_R {
+        CLK_DIVIDER1_R::new(((self.bits >> 8) & 0xff) as u8)
+    }
+    #[doc = "Bits 16:23 - Clock divider2 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on."]
+    #[inline(always)]
+    pub fn clk_divider2(&self) -> CLK_DIVIDER2_R {
+        CLK_DIVIDER2_R::new(((self.bits >> 16) & 0xff) as u8)
+    }
+    #[doc = "Bits 24:31 - Clock divider3 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on."]
+    #[inline(always)]
+    pub fn clk_divider3(&self) -> CLK_DIVIDER3_R {
+        CLK_DIVIDER3_R::new(((self.bits >> 24) & 0xff) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CLKDIV")
+            .field("clk_divider0", &self.clk_divider0())
+            .field("clk_divider1", &self.clk_divider1())
+            .field("clk_divider2", &self.clk_divider2())
+            .field("clk_divider3", &self.clk_divider3())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - Clock divider0 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on."]
+    #[inline(always)]
+    pub fn clk_divider0(&mut self) -> CLK_DIVIDER0_W<CLKDIV_SPEC> {
+        CLK_DIVIDER0_W::new(self, 0)
+    }
+    #[doc = "Bits 8:15 - Clock divider1 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on."]
+    #[inline(always)]
+    pub fn clk_divider1(&mut self) -> CLK_DIVIDER1_W<CLKDIV_SPEC> {
+        CLK_DIVIDER1_W::new(self, 8)
+    }
+    #[doc = "Bits 16:23 - Clock divider2 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on."]
+    #[inline(always)]
+    pub fn clk_divider2(&mut self) -> CLK_DIVIDER2_W<CLKDIV_SPEC> {
+        CLK_DIVIDER2_W::new(self, 16)
+    }
+    #[doc = "Bits 24:31 - Clock divider3 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on."]
+    #[inline(always)]
+    pub fn clk_divider3(&mut self) -> CLK_DIVIDER3_W<CLKDIV_SPEC> {
+        CLK_DIVIDER3_W::new(self, 24)
+    }
+}
+#[doc = "Clock divider configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CLKDIV_SPEC;
+impl crate::RegisterSpec for CLKDIV_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`clkdiv::R`](R) reader structure"]
+impl crate::Readable for CLKDIV_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`clkdiv::W`](W) writer structure"]
+impl crate::Writable for CLKDIV_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CLKDIV to value 0"]
+impl crate::Resettable for CLKDIV_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sdhost/clkena.rs

@@ -0,0 +1,62 @@
+#[doc = "Register `CLKENA` reader"]
+pub type R = crate::R<CLKENA_SPEC>;
+#[doc = "Register `CLKENA` writer"]
+pub type W = crate::W<CLKENA_SPEC>;
+#[doc = "Field `CCLK_ENABLE` reader - Clock-enable control for two SD card clocks and one MMC card clock is supported. One bit per card. 0: Clock disabled; 1: Clock enabled."]
+pub type CCLK_ENABLE_R = crate::FieldReader;
+#[doc = "Field `CCLK_ENABLE` writer - Clock-enable control for two SD card clocks and one MMC card clock is supported. One bit per card. 0: Clock disabled; 1: Clock enabled."]
+pub type CCLK_ENABLE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `LP_ENABLE` reader - Disable clock when the card is in IDLE state. One bit per card. 0: clock disabled; 1: clock enabled."]
+pub type LP_ENABLE_R = crate::FieldReader;
+#[doc = "Field `LP_ENABLE` writer - Disable clock when the card is in IDLE state. One bit per card. 0: clock disabled; 1: clock enabled."]
+pub type LP_ENABLE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+impl R {
+    #[doc = "Bits 0:1 - Clock-enable control for two SD card clocks and one MMC card clock is supported. One bit per card. 0: Clock disabled; 1: Clock enabled."]
+    #[inline(always)]
+    pub fn cclk_enable(&self) -> CCLK_ENABLE_R {
+        CCLK_ENABLE_R::new((self.bits & 3) as u8)
+    }
+    #[doc = "Bits 16:17 - Disable clock when the card is in IDLE state. One bit per card. 0: clock disabled; 1: clock enabled."]
+    #[inline(always)]
+    pub fn lp_enable(&self) -> LP_ENABLE_R {
+        LP_ENABLE_R::new(((self.bits >> 16) & 3) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CLKENA")
+            .field("cclk_enable", &self.cclk_enable())
+            .field("lp_enable", &self.lp_enable())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:1 - Clock-enable control for two SD card clocks and one MMC card clock is supported. One bit per card. 0: Clock disabled; 1: Clock enabled."]
+    #[inline(always)]
+    pub fn cclk_enable(&mut self) -> CCLK_ENABLE_W<CLKENA_SPEC> {
+        CCLK_ENABLE_W::new(self, 0)
+    }
+    #[doc = "Bits 16:17 - Disable clock when the card is in IDLE state. One bit per card. 0: clock disabled; 1: clock enabled."]
+    #[inline(always)]
+    pub fn lp_enable(&mut self) -> LP_ENABLE_W<CLKENA_SPEC> {
+        LP_ENABLE_W::new(self, 16)
+    }
+}
+#[doc = "Clock enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`clkena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CLKENA_SPEC;
+impl crate::RegisterSpec for CLKENA_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`clkena::R`](R) reader structure"]
+impl crate::Readable for CLKENA_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`clkena::W`](W) writer structure"]
+impl crate::Writable for CLKENA_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CLKENA to value 0"]
+impl crate::Resettable for CLKENA_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sdhost/clksrc.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `CLKSRC` reader"]
+pub type R = crate::R<CLKSRC_SPEC>;
+#[doc = "Register `CLKSRC` writer"]
+pub type W = crate::W<CLKSRC_SPEC>;
+#[doc = "Field `CLKSRC` reader - Clock divider source for two SD cards is supported. Each card has two bits assigned to it. For example, bit\\[1:0\\] are assigned for card 0, bit\\[3:2\\] are assigned for card 1. Card 0 maps and internally routes clock divider\\[0:3\\] outputs to cclk_out\\[1:0\\] pins, depending on bit value. 00 : Clock divider 0; 01 : Clock divider 1; 10 : Clock divider 2; 11 : Clock divider 3."]
+pub type CLKSRC_R = crate::FieldReader;
+#[doc = "Field `CLKSRC` writer - Clock divider source for two SD cards is supported. Each card has two bits assigned to it. For example, bit\\[1:0\\] are assigned for card 0, bit\\[3:2\\] are assigned for card 1. Card 0 maps and internally routes clock divider\\[0:3\\] outputs to cclk_out\\[1:0\\] pins, depending on bit value. 00 : Clock divider 0; 01 : Clock divider 1; 10 : Clock divider 2; 11 : Clock divider 3."]
+pub type CLKSRC_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+impl R {
+    #[doc = "Bits 0:3 - Clock divider source for two SD cards is supported. Each card has two bits assigned to it. For example, bit\\[1:0\\] are assigned for card 0, bit\\[3:2\\] are assigned for card 1. Card 0 maps and internally routes clock divider\\[0:3\\] outputs to cclk_out\\[1:0\\] pins, depending on bit value. 00 : Clock divider 0; 01 : Clock divider 1; 10 : Clock divider 2; 11 : Clock divider 3."]
+    #[inline(always)]
+    pub fn clksrc(&self) -> CLKSRC_R {
+        CLKSRC_R::new((self.bits & 0x0f) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CLKSRC")
+            .field("clksrc", &self.clksrc())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:3 - Clock divider source for two SD cards is supported. Each card has two bits assigned to it. For example, bit\\[1:0\\] are assigned for card 0, bit\\[3:2\\] are assigned for card 1. Card 0 maps and internally routes clock divider\\[0:3\\] outputs to cclk_out\\[1:0\\] pins, depending on bit value. 00 : Clock divider 0; 01 : Clock divider 1; 10 : Clock divider 2; 11 : Clock divider 3."]
+    #[inline(always)]
+    pub fn clksrc(&mut self) -> CLKSRC_W<CLKSRC_SPEC> {
+        CLKSRC_W::new(self, 0)
+    }
+}
+#[doc = "Clock source selection register\n\nYou can [`read`](crate::Reg::read) this register and get [`clksrc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clksrc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CLKSRC_SPEC;
+impl crate::RegisterSpec for CLKSRC_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`clksrc::R`](R) reader structure"]
+impl crate::Readable for CLKSRC_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`clksrc::W`](W) writer structure"]
+impl crate::Writable for CLKSRC_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CLKSRC to value 0"]
+impl crate::Resettable for CLKSRC_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sdhost/cmd.rs

@@ -0,0 +1,290 @@
+#[doc = "Register `CMD` reader"]
+pub type R = crate::R<CMD_SPEC>;
+#[doc = "Register `CMD` writer"]
+pub type W = crate::W<CMD_SPEC>;
+#[doc = "Field `INDEX` reader - Command index."]
+pub type INDEX_R = crate::FieldReader;
+#[doc = "Field `INDEX` writer - Command index."]
+pub type INDEX_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
+#[doc = "Field `RESPONSE_EXPECT` reader - 0: No response expected from card; 1: Response expected from card."]
+pub type RESPONSE_EXPECT_R = crate::BitReader;
+#[doc = "Field `RESPONSE_EXPECT` writer - 0: No response expected from card; 1: Response expected from card."]
+pub type RESPONSE_EXPECT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RESPONSE_LENGTH` reader - 0: Short response expected from card; 1: Long response expected from card."]
+pub type RESPONSE_LENGTH_R = crate::BitReader;
+#[doc = "Field `RESPONSE_LENGTH` writer - 0: Short response expected from card; 1: Long response expected from card."]
+pub type RESPONSE_LENGTH_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CHECK_RESPONSE_CRC` reader - 0: Do not check; 1: Check response CRC. Some of command responses do not return valid CRC bits. Software should disable CRC checks for those commands in order to disable CRC checking by controller."]
+pub type CHECK_RESPONSE_CRC_R = crate::BitReader;
+#[doc = "Field `CHECK_RESPONSE_CRC` writer - 0: Do not check; 1: Check response CRC. Some of command responses do not return valid CRC bits. Software should disable CRC checks for those commands in order to disable CRC checking by controller."]
+pub type CHECK_RESPONSE_CRC_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DATA_EXPECTED` reader - 0: No data transfer expected; 1: Data transfer expected."]
+pub type DATA_EXPECTED_R = crate::BitReader;
+#[doc = "Field `DATA_EXPECTED` writer - 0: No data transfer expected; 1: Data transfer expected."]
+pub type DATA_EXPECTED_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `READ_WRITE` reader - 0: Read from card; 1: Write to card. Don't care if no data is expected from card."]
+pub type READ_WRITE_R = crate::BitReader;
+#[doc = "Field `READ_WRITE` writer - 0: Read from card; 1: Write to card. Don't care if no data is expected from card."]
+pub type READ_WRITE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TRANSFER_MODE` reader - 0: Block data transfer command; 1: Stream data transfer command. Don't care if no data expected."]
+pub type TRANSFER_MODE_R = crate::BitReader;
+#[doc = "Field `TRANSFER_MODE` writer - 0: Block data transfer command; 1: Stream data transfer command. Don't care if no data expected."]
+pub type TRANSFER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SEND_AUTO_STOP` reader - 0: No stop command is sent at the end of data transfer; 1: Send stop command at the end of data transfer."]
+pub type SEND_AUTO_STOP_R = crate::BitReader;
+#[doc = "Field `SEND_AUTO_STOP` writer - 0: No stop command is sent at the end of data transfer; 1: Send stop command at the end of data transfer."]
+pub type SEND_AUTO_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `WAIT_PRVDATA_COMPLETE` reader - 0: Send command at once, even if previous data transfer has not completed; 1: Wait for previous data transfer to complete before sending Command. The SDHOST_WAIT_PRVDATA_COMPLETE] = 0 option is typically used to query status of card during data transfer or to stop current data transfer. SDHOST_CARD_NUMBERr should be same as in previous command."]
+pub type WAIT_PRVDATA_COMPLETE_R = crate::BitReader;
+#[doc = "Field `WAIT_PRVDATA_COMPLETE` writer - 0: Send command at once, even if previous data transfer has not completed; 1: Wait for previous data transfer to complete before sending Command. The SDHOST_WAIT_PRVDATA_COMPLETE] = 0 option is typically used to query status of card during data transfer or to stop current data transfer. SDHOST_CARD_NUMBERr should be same as in previous command."]
+pub type WAIT_PRVDATA_COMPLETE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `STOP_ABORT_CMD` reader - 0: Neither stop nor abort command can stop current data transfer. If abort is sent to function-number currently selected or not in data-transfer mode, then bit should be set to 0; 1: Stop or abort command intended to stop current data transfer in progress. When open-ended or predefined data transfer is in progress, and host issues stop or abort command to stop data transfer, bit should be set so that command/data state-machines of CIU can return correctly to idle state."]
+pub type STOP_ABORT_CMD_R = crate::BitReader;
+#[doc = "Field `STOP_ABORT_CMD` writer - 0: Neither stop nor abort command can stop current data transfer. If abort is sent to function-number currently selected or not in data-transfer mode, then bit should be set to 0; 1: Stop or abort command intended to stop current data transfer in progress. When open-ended or predefined data transfer is in progress, and host issues stop or abort command to stop data transfer, bit should be set so that command/data state-machines of CIU can return correctly to idle state."]
+pub type STOP_ABORT_CMD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SEND_INITIALIZATION` reader - 0: Do not send initialization sequence (80 clocks of 1) before sending this command; 1: Send initialization sequence before sending this command. After powered on, 80 clocks must be sent to card for initialization before sending any commands to card. Bit should be set while sending first command to card so that controller will initialize clocks before sending command to card."]
+pub type SEND_INITIALIZATION_R = crate::BitReader;
+#[doc = "Field `SEND_INITIALIZATION` writer - 0: Do not send initialization sequence (80 clocks of 1) before sending this command; 1: Send initialization sequence before sending this command. After powered on, 80 clocks must be sent to card for initialization before sending any commands to card. Bit should be set while sending first command to card so that controller will initialize clocks before sending command to card."]
+pub type SEND_INITIALIZATION_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CARD_NUMBER` reader - Card number in use. Represents physical slot number of card being accessed. In SD-only mode, up to two cards are supported."]
+pub type CARD_NUMBER_R = crate::FieldReader;
+#[doc = "Field `CARD_NUMBER` writer - Card number in use. Represents physical slot number of card being accessed. In SD-only mode, up to two cards are supported."]
+pub type CARD_NUMBER_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
+#[doc = "Field `UPDATE_CLOCK_REGISTERS_ONLY` reader - 0: Normal command sequence; 1: Do not send commands, just update clock register value into card clock domain. Following register values are transferred into card clock domain: CLKDIV, CLRSRC, and CLKENA. Changes card clocks (change frequency, truncate off or on, and set low-frequency mode). This is provided in order to change clock frequency or stop clock without having to send command to cards. During normal command sequence, when sdhost_update_clock_registers_only = 0, following control registers are transferred from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, and BYTCNT. CIU uses new register values for new command sequence to card(s). When bit is set, there are no Command Done interrupts because no command is sent to SD_MMC_CEATA cards."]
+pub type UPDATE_CLOCK_REGISTERS_ONLY_R = crate::BitReader;
+#[doc = "Field `UPDATE_CLOCK_REGISTERS_ONLY` writer - 0: Normal command sequence; 1: Do not send commands, just update clock register value into card clock domain. Following register values are transferred into card clock domain: CLKDIV, CLRSRC, and CLKENA. Changes card clocks (change frequency, truncate off or on, and set low-frequency mode). This is provided in order to change clock frequency or stop clock without having to send command to cards. During normal command sequence, when sdhost_update_clock_registers_only = 0, following control registers are transferred from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, and BYTCNT. CIU uses new register values for new command sequence to card(s). When bit is set, there are no Command Done interrupts because no command is sent to SD_MMC_CEATA cards."]
+pub type UPDATE_CLOCK_REGISTERS_ONLY_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `READ_CEATA_DEVICE` reader - Read access flag. 0: Host is not performing read access (RW_REG or RW_BLK)towards CE-ATA device; 1: Host is performing read access (RW_REG or RW_BLK) towards CE-ATA device. Software should set this bit to indicate that CE-ATA device is being accessed for read transfer. This bit is used to disable read data timeout indication while performing CE-ATA read transfers. Maximum value of I/O transmission delay can be no less than 10 seconds. SD/MMC should not indicate read data timeout while waiting for data from CE-ATA device."]
+pub type READ_CEATA_DEVICE_R = crate::BitReader;
+#[doc = "Field `READ_CEATA_DEVICE` writer - Read access flag. 0: Host is not performing read access (RW_REG or RW_BLK)towards CE-ATA device; 1: Host is performing read access (RW_REG or RW_BLK) towards CE-ATA device. Software should set this bit to indicate that CE-ATA device is being accessed for read transfer. This bit is used to disable read data timeout indication while performing CE-ATA read transfers. Maximum value of I/O transmission delay can be no less than 10 seconds. SD/MMC should not indicate read data timeout while waiting for data from CE-ATA device."]
+pub type READ_CEATA_DEVICE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CCS_EXPECTED` reader - Expected Command Completion Signal (CCS) configuration. 0: Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register), or command does not expect CCS from device; 1: Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects command completion signal from CE-ATA device. If the command expects Command Completion Signal (CCS) from the CE-ATA device, the software should set this control bit. SD/MMC sets Data Transfer Over (DTO) bit in RINTSTS register and generates interrupt to host if Data Transfer Over interrupt is not masked."]
+pub type CCS_EXPECTED_R = crate::BitReader;
+#[doc = "Field `CCS_EXPECTED` writer - Expected Command Completion Signal (CCS) configuration. 0: Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register), or command does not expect CCS from device; 1: Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects command completion signal from CE-ATA device. If the command expects Command Completion Signal (CCS) from the CE-ATA device, the software should set this control bit. SD/MMC sets Data Transfer Over (DTO) bit in RINTSTS register and generates interrupt to host if Data Transfer Over interrupt is not masked."]
+pub type CCS_EXPECTED_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `USE_HOLE` reader - Use Hold Register. 0: CMD and DATA sent to card bypassing HOLD Register; 1: CMD and DATA sent to card through the HOLD Register."]
+pub type USE_HOLE_R = crate::BitReader;
+#[doc = "Field `USE_HOLE` writer - Use Hold Register. 0: CMD and DATA sent to card bypassing HOLD Register; 1: CMD and DATA sent to card through the HOLD Register."]
+pub type USE_HOLE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `START_CMD` reader - Start command. Once command is served by the CIU, this bit is automatically cleared. When this bit is set, host should not attempt to write to any command registers. If a write is attempted, hardware lock error is set in raw interrupt register. Once command is sent and a response is received from SD_MMC_CEATA cards, Command Done bit is set in the raw interrupt Register."]
+pub type START_CMD_R = crate::BitReader;
+#[doc = "Field `START_CMD` writer - Start command. Once command is served by the CIU, this bit is automatically cleared. When this bit is set, host should not attempt to write to any command registers. If a write is attempted, hardware lock error is set in raw interrupt register. Once command is sent and a response is received from SD_MMC_CEATA cards, Command Done bit is set in the raw interrupt Register."]
+pub type START_CMD_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 0:5 - Command index."]
+    #[inline(always)]
+    pub fn index(&self) -> INDEX_R {
+        INDEX_R::new((self.bits & 0x3f) as u8)
+    }
+    #[doc = "Bit 6 - 0: No response expected from card; 1: Response expected from card."]
+    #[inline(always)]
+    pub fn response_expect(&self) -> RESPONSE_EXPECT_R {
+        RESPONSE_EXPECT_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - 0: Short response expected from card; 1: Long response expected from card."]
+    #[inline(always)]
+    pub fn response_length(&self) -> RESPONSE_LENGTH_R {
+        RESPONSE_LENGTH_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - 0: Do not check; 1: Check response CRC. Some of command responses do not return valid CRC bits. Software should disable CRC checks for those commands in order to disable CRC checking by controller."]
+    #[inline(always)]
+    pub fn check_response_crc(&self) -> CHECK_RESPONSE_CRC_R {
+        CHECK_RESPONSE_CRC_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - 0: No data transfer expected; 1: Data transfer expected."]
+    #[inline(always)]
+    pub fn data_expected(&self) -> DATA_EXPECTED_R {
+        DATA_EXPECTED_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 10 - 0: Read from card; 1: Write to card. Don't care if no data is expected from card."]
+    #[inline(always)]
+    pub fn read_write(&self) -> READ_WRITE_R {
+        READ_WRITE_R::new(((self.bits >> 10) & 1) != 0)
+    }
+    #[doc = "Bit 11 - 0: Block data transfer command; 1: Stream data transfer command. Don't care if no data expected."]
+    #[inline(always)]
+    pub fn transfer_mode(&self) -> TRANSFER_MODE_R {
+        TRANSFER_MODE_R::new(((self.bits >> 11) & 1) != 0)
+    }
+    #[doc = "Bit 12 - 0: No stop command is sent at the end of data transfer; 1: Send stop command at the end of data transfer."]
+    #[inline(always)]
+    pub fn send_auto_stop(&self) -> SEND_AUTO_STOP_R {
+        SEND_AUTO_STOP_R::new(((self.bits >> 12) & 1) != 0)
+    }
+    #[doc = "Bit 13 - 0: Send command at once, even if previous data transfer has not completed; 1: Wait for previous data transfer to complete before sending Command. The SDHOST_WAIT_PRVDATA_COMPLETE] = 0 option is typically used to query status of card during data transfer or to stop current data transfer. SDHOST_CARD_NUMBERr should be same as in previous command."]
+    #[inline(always)]
+    pub fn wait_prvdata_complete(&self) -> WAIT_PRVDATA_COMPLETE_R {
+        WAIT_PRVDATA_COMPLETE_R::new(((self.bits >> 13) & 1) != 0)
+    }
+    #[doc = "Bit 14 - 0: Neither stop nor abort command can stop current data transfer. If abort is sent to function-number currently selected or not in data-transfer mode, then bit should be set to 0; 1: Stop or abort command intended to stop current data transfer in progress. When open-ended or predefined data transfer is in progress, and host issues stop or abort command to stop data transfer, bit should be set so that command/data state-machines of CIU can return correctly to idle state."]
+    #[inline(always)]
+    pub fn stop_abort_cmd(&self) -> STOP_ABORT_CMD_R {
+        STOP_ABORT_CMD_R::new(((self.bits >> 14) & 1) != 0)
+    }
+    #[doc = "Bit 15 - 0: Do not send initialization sequence (80 clocks of 1) before sending this command; 1: Send initialization sequence before sending this command. After powered on, 80 clocks must be sent to card for initialization before sending any commands to card. Bit should be set while sending first command to card so that controller will initialize clocks before sending command to card."]
+    #[inline(always)]
+    pub fn send_initialization(&self) -> SEND_INITIALIZATION_R {
+        SEND_INITIALIZATION_R::new(((self.bits >> 15) & 1) != 0)
+    }
+    #[doc = "Bits 16:20 - Card number in use. Represents physical slot number of card being accessed. In SD-only mode, up to two cards are supported."]
+    #[inline(always)]
+    pub fn card_number(&self) -> CARD_NUMBER_R {
+        CARD_NUMBER_R::new(((self.bits >> 16) & 0x1f) as u8)
+    }
+    #[doc = "Bit 21 - 0: Normal command sequence; 1: Do not send commands, just update clock register value into card clock domain. Following register values are transferred into card clock domain: CLKDIV, CLRSRC, and CLKENA. Changes card clocks (change frequency, truncate off or on, and set low-frequency mode). This is provided in order to change clock frequency or stop clock without having to send command to cards. During normal command sequence, when sdhost_update_clock_registers_only = 0, following control registers are transferred from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, and BYTCNT. CIU uses new register values for new command sequence to card(s). When bit is set, there are no Command Done interrupts because no command is sent to SD_MMC_CEATA cards."]
+    #[inline(always)]
+    pub fn update_clock_registers_only(&self) -> UPDATE_CLOCK_REGISTERS_ONLY_R {
+        UPDATE_CLOCK_REGISTERS_ONLY_R::new(((self.bits >> 21) & 1) != 0)
+    }
+    #[doc = "Bit 22 - Read access flag. 0: Host is not performing read access (RW_REG or RW_BLK)towards CE-ATA device; 1: Host is performing read access (RW_REG or RW_BLK) towards CE-ATA device. Software should set this bit to indicate that CE-ATA device is being accessed for read transfer. This bit is used to disable read data timeout indication while performing CE-ATA read transfers. Maximum value of I/O transmission delay can be no less than 10 seconds. SD/MMC should not indicate read data timeout while waiting for data from CE-ATA device."]
+    #[inline(always)]
+    pub fn read_ceata_device(&self) -> READ_CEATA_DEVICE_R {
+        READ_CEATA_DEVICE_R::new(((self.bits >> 22) & 1) != 0)
+    }
+    #[doc = "Bit 23 - Expected Command Completion Signal (CCS) configuration. 0: Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register), or command does not expect CCS from device; 1: Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects command completion signal from CE-ATA device. If the command expects Command Completion Signal (CCS) from the CE-ATA device, the software should set this control bit. SD/MMC sets Data Transfer Over (DTO) bit in RINTSTS register and generates interrupt to host if Data Transfer Over interrupt is not masked."]
+    #[inline(always)]
+    pub fn ccs_expected(&self) -> CCS_EXPECTED_R {
+        CCS_EXPECTED_R::new(((self.bits >> 23) & 1) != 0)
+    }
+    #[doc = "Bit 29 - Use Hold Register. 0: CMD and DATA sent to card bypassing HOLD Register; 1: CMD and DATA sent to card through the HOLD Register."]
+    #[inline(always)]
+    pub fn use_hole(&self) -> USE_HOLE_R {
+        USE_HOLE_R::new(((self.bits >> 29) & 1) != 0)
+    }
+    #[doc = "Bit 31 - Start command. Once command is served by the CIU, this bit is automatically cleared. When this bit is set, host should not attempt to write to any command registers. If a write is attempted, hardware lock error is set in raw interrupt register. Once command is sent and a response is received from SD_MMC_CEATA cards, Command Done bit is set in the raw interrupt Register."]
+    #[inline(always)]
+    pub fn start_cmd(&self) -> START_CMD_R {
+        START_CMD_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CMD")
+            .field("index", &self.index())
+            .field("response_expect", &self.response_expect())
+            .field("response_length", &self.response_length())
+            .field("check_response_crc", &self.check_response_crc())
+            .field("data_expected", &self.data_expected())
+            .field("read_write", &self.read_write())
+            .field("transfer_mode", &self.transfer_mode())
+            .field("send_auto_stop", &self.send_auto_stop())
+            .field("wait_prvdata_complete", &self.wait_prvdata_complete())
+            .field("stop_abort_cmd", &self.stop_abort_cmd())
+            .field("send_initialization", &self.send_initialization())
+            .field("card_number", &self.card_number())
+            .field(
+                "update_clock_registers_only",
+                &self.update_clock_registers_only(),
+            )
+            .field("read_ceata_device", &self.read_ceata_device())
+            .field("ccs_expected", &self.ccs_expected())
+            .field("use_hole", &self.use_hole())
+            .field("start_cmd", &self.start_cmd())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:5 - Command index."]
+    #[inline(always)]
+    pub fn index(&mut self) -> INDEX_W<CMD_SPEC> {
+        INDEX_W::new(self, 0)
+    }
+    #[doc = "Bit 6 - 0: No response expected from card; 1: Response expected from card."]
+    #[inline(always)]
+    pub fn response_expect(&mut self) -> RESPONSE_EXPECT_W<CMD_SPEC> {
+        RESPONSE_EXPECT_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - 0: Short response expected from card; 1: Long response expected from card."]
+    #[inline(always)]
+    pub fn response_length(&mut self) -> RESPONSE_LENGTH_W<CMD_SPEC> {
+        RESPONSE_LENGTH_W::new(self, 7)
+    }
+    #[doc = "Bit 8 - 0: Do not check; 1: Check response CRC. Some of command responses do not return valid CRC bits. Software should disable CRC checks for those commands in order to disable CRC checking by controller."]
+    #[inline(always)]
+    pub fn check_response_crc(&mut self) -> CHECK_RESPONSE_CRC_W<CMD_SPEC> {
+        CHECK_RESPONSE_CRC_W::new(self, 8)
+    }
+    #[doc = "Bit 9 - 0: No data transfer expected; 1: Data transfer expected."]
+    #[inline(always)]
+    pub fn data_expected(&mut self) -> DATA_EXPECTED_W<CMD_SPEC> {
+        DATA_EXPECTED_W::new(self, 9)
+    }
+    #[doc = "Bit 10 - 0: Read from card; 1: Write to card. Don't care if no data is expected from card."]
+    #[inline(always)]
+    pub fn read_write(&mut self) -> READ_WRITE_W<CMD_SPEC> {
+        READ_WRITE_W::new(self, 10)
+    }
+    #[doc = "Bit 11 - 0: Block data transfer command; 1: Stream data transfer command. Don't care if no data expected."]
+    #[inline(always)]
+    pub fn transfer_mode(&mut self) -> TRANSFER_MODE_W<CMD_SPEC> {
+        TRANSFER_MODE_W::new(self, 11)
+    }
+    #[doc = "Bit 12 - 0: No stop command is sent at the end of data transfer; 1: Send stop command at the end of data transfer."]
+    #[inline(always)]
+    pub fn send_auto_stop(&mut self) -> SEND_AUTO_STOP_W<CMD_SPEC> {
+        SEND_AUTO_STOP_W::new(self, 12)
+    }
+    #[doc = "Bit 13 - 0: Send command at once, even if previous data transfer has not completed; 1: Wait for previous data transfer to complete before sending Command. The SDHOST_WAIT_PRVDATA_COMPLETE] = 0 option is typically used to query status of card during data transfer or to stop current data transfer. SDHOST_CARD_NUMBERr should be same as in previous command."]
+    #[inline(always)]
+    pub fn wait_prvdata_complete(&mut self) -> WAIT_PRVDATA_COMPLETE_W<CMD_SPEC> {
+        WAIT_PRVDATA_COMPLETE_W::new(self, 13)
+    }
+    #[doc = "Bit 14 - 0: Neither stop nor abort command can stop current data transfer. If abort is sent to function-number currently selected or not in data-transfer mode, then bit should be set to 0; 1: Stop or abort command intended to stop current data transfer in progress. When open-ended or predefined data transfer is in progress, and host issues stop or abort command to stop data transfer, bit should be set so that command/data state-machines of CIU can return correctly to idle state."]
+    #[inline(always)]
+    pub fn stop_abort_cmd(&mut self) -> STOP_ABORT_CMD_W<CMD_SPEC> {
+        STOP_ABORT_CMD_W::new(self, 14)
+    }
+    #[doc = "Bit 15 - 0: Do not send initialization sequence (80 clocks of 1) before sending this command; 1: Send initialization sequence before sending this command. After powered on, 80 clocks must be sent to card for initialization before sending any commands to card. Bit should be set while sending first command to card so that controller will initialize clocks before sending command to card."]
+    #[inline(always)]
+    pub fn send_initialization(&mut self) -> SEND_INITIALIZATION_W<CMD_SPEC> {
+        SEND_INITIALIZATION_W::new(self, 15)
+    }
+    #[doc = "Bits 16:20 - Card number in use. Represents physical slot number of card being accessed. In SD-only mode, up to two cards are supported."]
+    #[inline(always)]
+    pub fn card_number(&mut self) -> CARD_NUMBER_W<CMD_SPEC> {
+        CARD_NUMBER_W::new(self, 16)
+    }
+    #[doc = "Bit 21 - 0: Normal command sequence; 1: Do not send commands, just update clock register value into card clock domain. Following register values are transferred into card clock domain: CLKDIV, CLRSRC, and CLKENA. Changes card clocks (change frequency, truncate off or on, and set low-frequency mode). This is provided in order to change clock frequency or stop clock without having to send command to cards. During normal command sequence, when sdhost_update_clock_registers_only = 0, following control registers are transferred from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, and BYTCNT. CIU uses new register values for new command sequence to card(s). When bit is set, there are no Command Done interrupts because no command is sent to SD_MMC_CEATA cards."]
+    #[inline(always)]
+    pub fn update_clock_registers_only(&mut self) -> UPDATE_CLOCK_REGISTERS_ONLY_W<CMD_SPEC> {
+        UPDATE_CLOCK_REGISTERS_ONLY_W::new(self, 21)
+    }
+    #[doc = "Bit 22 - Read access flag. 0: Host is not performing read access (RW_REG or RW_BLK)towards CE-ATA device; 1: Host is performing read access (RW_REG or RW_BLK) towards CE-ATA device. Software should set this bit to indicate that CE-ATA device is being accessed for read transfer. This bit is used to disable read data timeout indication while performing CE-ATA read transfers. Maximum value of I/O transmission delay can be no less than 10 seconds. SD/MMC should not indicate read data timeout while waiting for data from CE-ATA device."]
+    #[inline(always)]
+    pub fn read_ceata_device(&mut self) -> READ_CEATA_DEVICE_W<CMD_SPEC> {
+        READ_CEATA_DEVICE_W::new(self, 22)
+    }
+    #[doc = "Bit 23 - Expected Command Completion Signal (CCS) configuration. 0: Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register), or command does not expect CCS from device; 1: Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects command completion signal from CE-ATA device. If the command expects Command Completion Signal (CCS) from the CE-ATA device, the software should set this control bit. SD/MMC sets Data Transfer Over (DTO) bit in RINTSTS register and generates interrupt to host if Data Transfer Over interrupt is not masked."]
+    #[inline(always)]
+    pub fn ccs_expected(&mut self) -> CCS_EXPECTED_W<CMD_SPEC> {
+        CCS_EXPECTED_W::new(self, 23)
+    }
+    #[doc = "Bit 29 - Use Hold Register. 0: CMD and DATA sent to card bypassing HOLD Register; 1: CMD and DATA sent to card through the HOLD Register."]
+    #[inline(always)]
+    pub fn use_hole(&mut self) -> USE_HOLE_W<CMD_SPEC> {
+        USE_HOLE_W::new(self, 29)
+    }
+    #[doc = "Bit 31 - Start command. Once command is served by the CIU, this bit is automatically cleared. When this bit is set, host should not attempt to write to any command registers. If a write is attempted, hardware lock error is set in raw interrupt register. Once command is sent and a response is received from SD_MMC_CEATA cards, Command Done bit is set in the raw interrupt Register."]
+    #[inline(always)]
+    pub fn start_cmd(&mut self) -> START_CMD_W<CMD_SPEC> {
+        START_CMD_W::new(self, 31)
+    }
+}
+#[doc = "Command and boot configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CMD_SPEC;
+impl crate::RegisterSpec for CMD_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cmd::R`](R) reader structure"]
+impl crate::Readable for CMD_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`cmd::W`](W) writer structure"]
+impl crate::Writable for CMD_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CMD to value 0x2000_0000"]
+impl crate::Resettable for CMD_SPEC {
+    const RESET_VALUE: u32 = 0x2000_0000;
+}

vendor/esp32s3/src/sdhost/cmdarg.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `CMDARG` reader"]
+pub type R = crate::R<CMDARG_SPEC>;
+#[doc = "Register `CMDARG` writer"]
+pub type W = crate::W<CMDARG_SPEC>;
+#[doc = "Field `CMDARG` reader - Value indicates command argument to be passed to the card."]
+pub type CMDARG_R = crate::FieldReader<u32>;
+#[doc = "Field `CMDARG` writer - Value indicates command argument to be passed to the card."]
+pub type CMDARG_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - Value indicates command argument to be passed to the card."]
+    #[inline(always)]
+    pub fn cmdarg(&self) -> CMDARG_R {
+        CMDARG_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CMDARG")
+            .field("cmdarg", &self.cmdarg())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Value indicates command argument to be passed to the card."]
+    #[inline(always)]
+    pub fn cmdarg(&mut self) -> CMDARG_W<CMDARG_SPEC> {
+        CMDARG_W::new(self, 0)
+    }
+}
+#[doc = "Command argument data register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmdarg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmdarg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CMDARG_SPEC;
+impl crate::RegisterSpec for CMDARG_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cmdarg::R`](R) reader structure"]
+impl crate::Readable for CMDARG_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`cmdarg::W`](W) writer structure"]
+impl crate::Writable for CMDARG_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CMDARG to value 0"]
+impl crate::Resettable for CMDARG_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sdhost/ctrl.rs

@@ -0,0 +1,185 @@
+#[doc = "Register `CTRL` reader"]
+pub type R = crate::R<CTRL_SPEC>;
+#[doc = "Register `CTRL` writer"]
+pub type W = crate::W<CTRL_SPEC>;
+#[doc = "Field `CONTROLLER_RESET` reader - To reset controller, firmware should set this bit. This bit is auto-cleared after two AHB and two sdhost_cclk_in clock cycles."]
+pub type CONTROLLER_RESET_R = crate::BitReader;
+#[doc = "Field `CONTROLLER_RESET` writer - To reset controller, firmware should set this bit. This bit is auto-cleared after two AHB and two sdhost_cclk_in clock cycles."]
+pub type CONTROLLER_RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FIFO_RESET` reader - To reset FIFO, firmware should set bit to 1. This bit is auto-cleared after completion of reset operation. Note: FIFO pointers will be out of reset after 2 cycles of system clocks in addition to synchronization delay (2 cycles of card clock), after the fifo_reset is cleared."]
+pub type FIFO_RESET_R = crate::BitReader;
+#[doc = "Field `FIFO_RESET` writer - To reset FIFO, firmware should set bit to 1. This bit is auto-cleared after completion of reset operation. Note: FIFO pointers will be out of reset after 2 cycles of system clocks in addition to synchronization delay (2 cycles of card clock), after the fifo_reset is cleared."]
+pub type FIFO_RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DMA_RESET` reader - To reset DMA interface, firmware should set bit to 1. This bit is auto-cleared after two AHB clocks."]
+pub type DMA_RESET_R = crate::BitReader;
+#[doc = "Field `DMA_RESET` writer - To reset DMA interface, firmware should set bit to 1. This bit is auto-cleared after two AHB clocks."]
+pub type DMA_RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `INT_ENABLE` reader - Global interrupt enable/disable bit. 0: Disable; 1: Enable."]
+pub type INT_ENABLE_R = crate::BitReader;
+#[doc = "Field `INT_ENABLE` writer - Global interrupt enable/disable bit. 0: Disable; 1: Enable."]
+pub type INT_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `READ_WAIT` reader - For sending read-wait to SDIO cards."]
+pub type READ_WAIT_R = crate::BitReader;
+#[doc = "Field `READ_WAIT` writer - For sending read-wait to SDIO cards."]
+pub type READ_WAIT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SEND_IRQ_RESPONSE` reader - Bit automatically clears once response is sent. To wait for MMC card interrupts, host issues CMD40 and waits for interrupt response from MMC card(s). In the meantime, if host wants SD/MMC to exit waiting for interrupt state, it can set this bit, at which time SD/MMC command state-machine sends CMD40 response on bus and returns to idle state."]
+pub type SEND_IRQ_RESPONSE_R = crate::BitReader;
+#[doc = "Field `SEND_IRQ_RESPONSE` writer - Bit automatically clears once response is sent. To wait for MMC card interrupts, host issues CMD40 and waits for interrupt response from MMC card(s). In the meantime, if host wants SD/MMC to exit waiting for interrupt state, it can set this bit, at which time SD/MMC command state-machine sends CMD40 response on bus and returns to idle state."]
+pub type SEND_IRQ_RESPONSE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ABORT_READ_DATA` reader - After a suspend-command is issued during a read-operation, software polls the card to find when the suspend-event occurred. Once the suspend-event has occurred, software sets the bit which will reset the data state machine that is waiting for the next block of data. This bit is automatically cleared once the data state machine is reset to idle."]
+pub type ABORT_READ_DATA_R = crate::BitReader;
+#[doc = "Field `ABORT_READ_DATA` writer - After a suspend-command is issued during a read-operation, software polls the card to find when the suspend-event occurred. Once the suspend-event has occurred, software sets the bit which will reset the data state machine that is waiting for the next block of data. This bit is automatically cleared once the data state machine is reset to idle."]
+pub type ABORT_READ_DATA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SEND_CCSD` reader - When set, SD/MMC sends CCSD to the CE-ATA device. Software sets this bit only if the current command is expecting CCS (that is, RW_BLK), and if interrupts are enabled for the CE-ATA device. Once the CCSD pattern is sent to the device, SD/MMC automatically clears the SDHOST_SEND_CCSD bit. It also sets the Command Done (CD) bit in the SDHOST_RINTSTS_REG register, and generates an interrupt for the host, in case the Command Done interrupt is not masked. NOTE: Once the SDHOST_SEND_CCSD bit is set, it takes two card clock cycles to drive the CCSD on the CMD line. Due to this, within the boundary conditions the CCSD may be sent to the CE-ATA device, even if the device has signalled CCS."]
+pub type SEND_CCSD_R = crate::BitReader;
+#[doc = "Field `SEND_CCSD` writer - When set, SD/MMC sends CCSD to the CE-ATA device. Software sets this bit only if the current command is expecting CCS (that is, RW_BLK), and if interrupts are enabled for the CE-ATA device. Once the CCSD pattern is sent to the device, SD/MMC automatically clears the SDHOST_SEND_CCSD bit. It also sets the Command Done (CD) bit in the SDHOST_RINTSTS_REG register, and generates an interrupt for the host, in case the Command Done interrupt is not masked. NOTE: Once the SDHOST_SEND_CCSD bit is set, it takes two card clock cycles to drive the CCSD on the CMD line. Due to this, within the boundary conditions the CCSD may be sent to the CE-ATA device, even if the device has signalled CCS."]
+pub type SEND_CCSD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SEND_AUTO_STOP_CCSD` reader - Always Set SDHOST_SEND_AUTO_STOP_CCSD and SDHOST_SEND_CCSD bits together; SDHOST_SEND_AUTO_STOP_CCSD should not be set independently of send_ccsd. When set, SD/MMC automatically sends an internally-generated STOP command (CMD12) to the CE-ATA device. After sending this internally-generated STOP command, the Auto Command Done (ACD) bit in SDHOST_RINTSTS_REG is set and an interrupt is generated for the host, in case the ACD interrupt is not masked. After sending the Command Completion Signal Disable (CCSD), SD/MMC automatically clears the SDHOST_SEND_AUTO_STOP_CCSD bit."]
+pub type SEND_AUTO_STOP_CCSD_R = crate::BitReader;
+#[doc = "Field `SEND_AUTO_STOP_CCSD` writer - Always Set SDHOST_SEND_AUTO_STOP_CCSD and SDHOST_SEND_CCSD bits together; SDHOST_SEND_AUTO_STOP_CCSD should not be set independently of send_ccsd. When set, SD/MMC automatically sends an internally-generated STOP command (CMD12) to the CE-ATA device. After sending this internally-generated STOP command, the Auto Command Done (ACD) bit in SDHOST_RINTSTS_REG is set and an interrupt is generated for the host, in case the ACD interrupt is not masked. After sending the Command Completion Signal Disable (CCSD), SD/MMC automatically clears the SDHOST_SEND_AUTO_STOP_CCSD bit."]
+pub type SEND_AUTO_STOP_CCSD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CEATA_DEVICE_INTERRUPT_STATUS` reader - Software should appropriately write to this bit after the power-on reset or any other reset to the CE-ATA device. After reset, the CE-ATA device's interrupt is usually disabled (nIEN = 1). If the host enables the CE-ATA device's interrupt, then software should set this bit."]
+pub type CEATA_DEVICE_INTERRUPT_STATUS_R = crate::BitReader;
+#[doc = "Field `CEATA_DEVICE_INTERRUPT_STATUS` writer - Software should appropriately write to this bit after the power-on reset or any other reset to the CE-ATA device. After reset, the CE-ATA device's interrupt is usually disabled (nIEN = 1). If the host enables the CE-ATA device's interrupt, then software should set this bit."]
+pub type CEATA_DEVICE_INTERRUPT_STATUS_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - To reset controller, firmware should set this bit. This bit is auto-cleared after two AHB and two sdhost_cclk_in clock cycles."]
+    #[inline(always)]
+    pub fn controller_reset(&self) -> CONTROLLER_RESET_R {
+        CONTROLLER_RESET_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - To reset FIFO, firmware should set bit to 1. This bit is auto-cleared after completion of reset operation. Note: FIFO pointers will be out of reset after 2 cycles of system clocks in addition to synchronization delay (2 cycles of card clock), after the fifo_reset is cleared."]
+    #[inline(always)]
+    pub fn fifo_reset(&self) -> FIFO_RESET_R {
+        FIFO_RESET_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - To reset DMA interface, firmware should set bit to 1. This bit is auto-cleared after two AHB clocks."]
+    #[inline(always)]
+    pub fn dma_reset(&self) -> DMA_RESET_R {
+        DMA_RESET_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Global interrupt enable/disable bit. 0: Disable; 1: Enable."]
+    #[inline(always)]
+    pub fn int_enable(&self) -> INT_ENABLE_R {
+        INT_ENABLE_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 6 - For sending read-wait to SDIO cards."]
+    #[inline(always)]
+    pub fn read_wait(&self) -> READ_WAIT_R {
+        READ_WAIT_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - Bit automatically clears once response is sent. To wait for MMC card interrupts, host issues CMD40 and waits for interrupt response from MMC card(s). In the meantime, if host wants SD/MMC to exit waiting for interrupt state, it can set this bit, at which time SD/MMC command state-machine sends CMD40 response on bus and returns to idle state."]
+    #[inline(always)]
+    pub fn send_irq_response(&self) -> SEND_IRQ_RESPONSE_R {
+        SEND_IRQ_RESPONSE_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - After a suspend-command is issued during a read-operation, software polls the card to find when the suspend-event occurred. Once the suspend-event has occurred, software sets the bit which will reset the data state machine that is waiting for the next block of data. This bit is automatically cleared once the data state machine is reset to idle."]
+    #[inline(always)]
+    pub fn abort_read_data(&self) -> ABORT_READ_DATA_R {
+        ABORT_READ_DATA_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - When set, SD/MMC sends CCSD to the CE-ATA device. Software sets this bit only if the current command is expecting CCS (that is, RW_BLK), and if interrupts are enabled for the CE-ATA device. Once the CCSD pattern is sent to the device, SD/MMC automatically clears the SDHOST_SEND_CCSD bit. It also sets the Command Done (CD) bit in the SDHOST_RINTSTS_REG register, and generates an interrupt for the host, in case the Command Done interrupt is not masked. NOTE: Once the SDHOST_SEND_CCSD bit is set, it takes two card clock cycles to drive the CCSD on the CMD line. Due to this, within the boundary conditions the CCSD may be sent to the CE-ATA device, even if the device has signalled CCS."]
+    #[inline(always)]
+    pub fn send_ccsd(&self) -> SEND_CCSD_R {
+        SEND_CCSD_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 10 - Always Set SDHOST_SEND_AUTO_STOP_CCSD and SDHOST_SEND_CCSD bits together; SDHOST_SEND_AUTO_STOP_CCSD should not be set independently of send_ccsd. When set, SD/MMC automatically sends an internally-generated STOP command (CMD12) to the CE-ATA device. After sending this internally-generated STOP command, the Auto Command Done (ACD) bit in SDHOST_RINTSTS_REG is set and an interrupt is generated for the host, in case the ACD interrupt is not masked. After sending the Command Completion Signal Disable (CCSD), SD/MMC automatically clears the SDHOST_SEND_AUTO_STOP_CCSD bit."]
+    #[inline(always)]
+    pub fn send_auto_stop_ccsd(&self) -> SEND_AUTO_STOP_CCSD_R {
+        SEND_AUTO_STOP_CCSD_R::new(((self.bits >> 10) & 1) != 0)
+    }
+    #[doc = "Bit 11 - Software should appropriately write to this bit after the power-on reset or any other reset to the CE-ATA device. After reset, the CE-ATA device's interrupt is usually disabled (nIEN = 1). If the host enables the CE-ATA device's interrupt, then software should set this bit."]
+    #[inline(always)]
+    pub fn ceata_device_interrupt_status(&self) -> CEATA_DEVICE_INTERRUPT_STATUS_R {
+        CEATA_DEVICE_INTERRUPT_STATUS_R::new(((self.bits >> 11) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CTRL")
+            .field("controller_reset", &self.controller_reset())
+            .field("fifo_reset", &self.fifo_reset())
+            .field("dma_reset", &self.dma_reset())
+            .field("int_enable", &self.int_enable())
+            .field("read_wait", &self.read_wait())
+            .field("send_irq_response", &self.send_irq_response())
+            .field("abort_read_data", &self.abort_read_data())
+            .field("send_ccsd", &self.send_ccsd())
+            .field("send_auto_stop_ccsd", &self.send_auto_stop_ccsd())
+            .field(
+                "ceata_device_interrupt_status",
+                &self.ceata_device_interrupt_status(),
+            )
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - To reset controller, firmware should set this bit. This bit is auto-cleared after two AHB and two sdhost_cclk_in clock cycles."]
+    #[inline(always)]
+    pub fn controller_reset(&mut self) -> CONTROLLER_RESET_W<CTRL_SPEC> {
+        CONTROLLER_RESET_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - To reset FIFO, firmware should set bit to 1. This bit is auto-cleared after completion of reset operation. Note: FIFO pointers will be out of reset after 2 cycles of system clocks in addition to synchronization delay (2 cycles of card clock), after the fifo_reset is cleared."]
+    #[inline(always)]
+    pub fn fifo_reset(&mut self) -> FIFO_RESET_W<CTRL_SPEC> {
+        FIFO_RESET_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - To reset DMA interface, firmware should set bit to 1. This bit is auto-cleared after two AHB clocks."]
+    #[inline(always)]
+    pub fn dma_reset(&mut self) -> DMA_RESET_W<CTRL_SPEC> {
+        DMA_RESET_W::new(self, 2)
+    }
+    #[doc = "Bit 4 - Global interrupt enable/disable bit. 0: Disable; 1: Enable."]
+    #[inline(always)]
+    pub fn int_enable(&mut self) -> INT_ENABLE_W<CTRL_SPEC> {
+        INT_ENABLE_W::new(self, 4)
+    }
+    #[doc = "Bit 6 - For sending read-wait to SDIO cards."]
+    #[inline(always)]
+    pub fn read_wait(&mut self) -> READ_WAIT_W<CTRL_SPEC> {
+        READ_WAIT_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - Bit automatically clears once response is sent. To wait for MMC card interrupts, host issues CMD40 and waits for interrupt response from MMC card(s). In the meantime, if host wants SD/MMC to exit waiting for interrupt state, it can set this bit, at which time SD/MMC command state-machine sends CMD40 response on bus and returns to idle state."]
+    #[inline(always)]
+    pub fn send_irq_response(&mut self) -> SEND_IRQ_RESPONSE_W<CTRL_SPEC> {
+        SEND_IRQ_RESPONSE_W::new(self, 7)
+    }
+    #[doc = "Bit 8 - After a suspend-command is issued during a read-operation, software polls the card to find when the suspend-event occurred. Once the suspend-event has occurred, software sets the bit which will reset the data state machine that is waiting for the next block of data. This bit is automatically cleared once the data state machine is reset to idle."]
+    #[inline(always)]
+    pub fn abort_read_data(&mut self) -> ABORT_READ_DATA_W<CTRL_SPEC> {
+        ABORT_READ_DATA_W::new(self, 8)
+    }
+    #[doc = "Bit 9 - When set, SD/MMC sends CCSD to the CE-ATA device. Software sets this bit only if the current command is expecting CCS (that is, RW_BLK), and if interrupts are enabled for the CE-ATA device. Once the CCSD pattern is sent to the device, SD/MMC automatically clears the SDHOST_SEND_CCSD bit. It also sets the Command Done (CD) bit in the SDHOST_RINTSTS_REG register, and generates an interrupt for the host, in case the Command Done interrupt is not masked. NOTE: Once the SDHOST_SEND_CCSD bit is set, it takes two card clock cycles to drive the CCSD on the CMD line. Due to this, within the boundary conditions the CCSD may be sent to the CE-ATA device, even if the device has signalled CCS."]
+    #[inline(always)]
+    pub fn send_ccsd(&mut self) -> SEND_CCSD_W<CTRL_SPEC> {
+        SEND_CCSD_W::new(self, 9)
+    }
+    #[doc = "Bit 10 - Always Set SDHOST_SEND_AUTO_STOP_CCSD and SDHOST_SEND_CCSD bits together; SDHOST_SEND_AUTO_STOP_CCSD should not be set independently of send_ccsd. When set, SD/MMC automatically sends an internally-generated STOP command (CMD12) to the CE-ATA device. After sending this internally-generated STOP command, the Auto Command Done (ACD) bit in SDHOST_RINTSTS_REG is set and an interrupt is generated for the host, in case the ACD interrupt is not masked. After sending the Command Completion Signal Disable (CCSD), SD/MMC automatically clears the SDHOST_SEND_AUTO_STOP_CCSD bit."]
+    #[inline(always)]
+    pub fn send_auto_stop_ccsd(&mut self) -> SEND_AUTO_STOP_CCSD_W<CTRL_SPEC> {
+        SEND_AUTO_STOP_CCSD_W::new(self, 10)
+    }
+    #[doc = "Bit 11 - Software should appropriately write to this bit after the power-on reset or any other reset to the CE-ATA device. After reset, the CE-ATA device's interrupt is usually disabled (nIEN = 1). If the host enables the CE-ATA device's interrupt, then software should set this bit."]
+    #[inline(always)]
+    pub fn ceata_device_interrupt_status(&mut self) -> CEATA_DEVICE_INTERRUPT_STATUS_W<CTRL_SPEC> {
+        CEATA_DEVICE_INTERRUPT_STATUS_W::new(self, 11)
+    }
+}
+#[doc = "Control register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CTRL_SPEC;
+impl crate::RegisterSpec for CTRL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"]
+impl crate::Readable for CTRL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
+impl crate::Writable for CTRL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CTRL to value 0"]
+impl crate::Resettable for CTRL_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sdhost/ctype.rs

@@ -0,0 +1,62 @@
+#[doc = "Register `CTYPE` reader"]
+pub type R = crate::R<CTYPE_SPEC>;
+#[doc = "Register `CTYPE` writer"]
+pub type W = crate::W<CTYPE_SPEC>;
+#[doc = "Field `CARD_WIDTH4` reader - One bit per card indicates if card is 1-bit or 4-bit mode. 0: 1-bit mode; 1: 4-bit mode. Bit\\[1:0\\] correspond to card\\[1:0\\] respectively."]
+pub type CARD_WIDTH4_R = crate::FieldReader;
+#[doc = "Field `CARD_WIDTH4` writer - One bit per card indicates if card is 1-bit or 4-bit mode. 0: 1-bit mode; 1: 4-bit mode. Bit\\[1:0\\] correspond to card\\[1:0\\] respectively."]
+pub type CARD_WIDTH4_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `CARD_WIDTH8` reader - One bit per card indicates if card is in 8-bit mode. 0: Non 8-bit mode; 1: 8-bit mode. Bit\\[17:16\\] correspond to card\\[1:0\\] respectively."]
+pub type CARD_WIDTH8_R = crate::FieldReader;
+#[doc = "Field `CARD_WIDTH8` writer - One bit per card indicates if card is in 8-bit mode. 0: Non 8-bit mode; 1: 8-bit mode. Bit\\[17:16\\] correspond to card\\[1:0\\] respectively."]
+pub type CARD_WIDTH8_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+impl R {
+    #[doc = "Bits 0:1 - One bit per card indicates if card is 1-bit or 4-bit mode. 0: 1-bit mode; 1: 4-bit mode. Bit\\[1:0\\] correspond to card\\[1:0\\] respectively."]
+    #[inline(always)]
+    pub fn card_width4(&self) -> CARD_WIDTH4_R {
+        CARD_WIDTH4_R::new((self.bits & 3) as u8)
+    }
+    #[doc = "Bits 16:17 - One bit per card indicates if card is in 8-bit mode. 0: Non 8-bit mode; 1: 8-bit mode. Bit\\[17:16\\] correspond to card\\[1:0\\] respectively."]
+    #[inline(always)]
+    pub fn card_width8(&self) -> CARD_WIDTH8_R {
+        CARD_WIDTH8_R::new(((self.bits >> 16) & 3) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CTYPE")
+            .field("card_width4", &self.card_width4())
+            .field("card_width8", &self.card_width8())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:1 - One bit per card indicates if card is 1-bit or 4-bit mode. 0: 1-bit mode; 1: 4-bit mode. Bit\\[1:0\\] correspond to card\\[1:0\\] respectively."]
+    #[inline(always)]
+    pub fn card_width4(&mut self) -> CARD_WIDTH4_W<CTYPE_SPEC> {
+        CARD_WIDTH4_W::new(self, 0)
+    }
+    #[doc = "Bits 16:17 - One bit per card indicates if card is in 8-bit mode. 0: Non 8-bit mode; 1: 8-bit mode. Bit\\[17:16\\] correspond to card\\[1:0\\] respectively."]
+    #[inline(always)]
+    pub fn card_width8(&mut self) -> CARD_WIDTH8_W<CTYPE_SPEC> {
+        CARD_WIDTH8_W::new(self, 16)
+    }
+}
+#[doc = "Card bus width configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctype::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctype::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CTYPE_SPEC;
+impl crate::RegisterSpec for CTYPE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`ctype::R`](R) reader structure"]
+impl crate::Readable for CTYPE_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`ctype::W`](W) writer structure"]
+impl crate::Writable for CTYPE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CTYPE to value 0"]
+impl crate::Resettable for CTYPE_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sdhost/dbaddr.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `DBADDR` reader"]
+pub type R = crate::R<DBADDR_SPEC>;
+#[doc = "Register `DBADDR` writer"]
+pub type W = crate::W<DBADDR_SPEC>;
+#[doc = "Field `DBADDR` reader - Start of Descriptor List. Contains the base address of the First Descriptor. The LSB bits \\[1:0\\] are ignored and taken as all-zero by the IDMAC internally. Hence these LSB bits may be treated as read-only."]
+pub type DBADDR_R = crate::FieldReader<u32>;
+#[doc = "Field `DBADDR` writer - Start of Descriptor List. Contains the base address of the First Descriptor. The LSB bits \\[1:0\\] are ignored and taken as all-zero by the IDMAC internally. Hence these LSB bits may be treated as read-only."]
+pub type DBADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - Start of Descriptor List. Contains the base address of the First Descriptor. The LSB bits \\[1:0\\] are ignored and taken as all-zero by the IDMAC internally. Hence these LSB bits may be treated as read-only."]
+    #[inline(always)]
+    pub fn dbaddr(&self) -> DBADDR_R {
+        DBADDR_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DBADDR")
+            .field("dbaddr", &self.dbaddr())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Start of Descriptor List. Contains the base address of the First Descriptor. The LSB bits \\[1:0\\] are ignored and taken as all-zero by the IDMAC internally. Hence these LSB bits may be treated as read-only."]
+    #[inline(always)]
+    pub fn dbaddr(&mut self) -> DBADDR_W<DBADDR_SPEC> {
+        DBADDR_W::new(self, 0)
+    }
+}
+#[doc = "Descriptor base address register\n\nYou can [`read`](crate::Reg::read) this register and get [`dbaddr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dbaddr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DBADDR_SPEC;
+impl crate::RegisterSpec for DBADDR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`dbaddr::R`](R) reader structure"]
+impl crate::Readable for DBADDR_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`dbaddr::W`](W) writer structure"]
+impl crate::Writable for DBADDR_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DBADDR to value 0"]
+impl crate::Resettable for DBADDR_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sdhost/debnce.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `DEBNCE` reader"]
+pub type R = crate::R<DEBNCE_SPEC>;
+#[doc = "Register `DEBNCE` writer"]
+pub type W = crate::W<DEBNCE_SPEC>;
+#[doc = "Field `DEBOUNCE_COUNT` reader - Number of host clocks (clk) used by debounce filter logic. The typical debounce time is 5 \\verb+~+ 25 ms to prevent the card instability when the card is inserted or removed."]
+pub type DEBOUNCE_COUNT_R = crate::FieldReader<u32>;
+#[doc = "Field `DEBOUNCE_COUNT` writer - Number of host clocks (clk) used by debounce filter logic. The typical debounce time is 5 \\verb+~+ 25 ms to prevent the card instability when the card is inserted or removed."]
+pub type DEBOUNCE_COUNT_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
+impl R {
+    #[doc = "Bits 0:23 - Number of host clocks (clk) used by debounce filter logic. The typical debounce time is 5 \\verb+~+ 25 ms to prevent the card instability when the card is inserted or removed."]
+    #[inline(always)]
+    pub fn debounce_count(&self) -> DEBOUNCE_COUNT_R {
+        DEBOUNCE_COUNT_R::new(self.bits & 0x00ff_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DEBNCE")
+            .field("debounce_count", &self.debounce_count())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:23 - Number of host clocks (clk) used by debounce filter logic. The typical debounce time is 5 \\verb+~+ 25 ms to prevent the card instability when the card is inserted or removed."]
+    #[inline(always)]
+    pub fn debounce_count(&mut self) -> DEBOUNCE_COUNT_W<DEBNCE_SPEC> {
+        DEBOUNCE_COUNT_W::new(self, 0)
+    }
+}
+#[doc = "Debounce filter time configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`debnce::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debnce::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DEBNCE_SPEC;
+impl crate::RegisterSpec for DEBNCE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`debnce::R`](R) reader structure"]
+impl crate::Readable for DEBNCE_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`debnce::W`](W) writer structure"]
+impl crate::Writable for DEBNCE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DEBNCE to value 0"]
+impl crate::Resettable for DEBNCE_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sdhost/dscaddr.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `DSCADDR` reader"]
+pub type R = crate::R<DSCADDR_SPEC>;
+#[doc = "Field `DSCADDR` reader - Host Descriptor Address Pointer, updated by IDMAC during operation and cleared on reset. This register points to the start address of the current descriptor read by the IDMAC."]
+pub type DSCADDR_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - Host Descriptor Address Pointer, updated by IDMAC during operation and cleared on reset. This register points to the start address of the current descriptor read by the IDMAC."]
+    #[inline(always)]
+    pub fn dscaddr(&self) -> DSCADDR_R {
+        DSCADDR_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DSCADDR")
+            .field("dscaddr", &self.dscaddr())
+            .finish()
+    }
+}
+#[doc = "Host descriptor address pointer\n\nYou can [`read`](crate::Reg::read) this register and get [`dscaddr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DSCADDR_SPEC;
+impl crate::RegisterSpec for DSCADDR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`dscaddr::R`](R) reader structure"]
+impl crate::Readable for DSCADDR_SPEC {}
+#[doc = "`reset()` method sets DSCADDR to value 0"]
+impl crate::Resettable for DSCADDR_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sdhost/emmcddr.rs

@@ -0,0 +1,62 @@
+#[doc = "Register `EMMCDDR` reader"]
+pub type R = crate::R<EMMCDDR_SPEC>;
+#[doc = "Register `EMMCDDR` writer"]
+pub type W = crate::W<EMMCDDR_SPEC>;
+#[doc = "Field `HALFSTARTBIT` reader - Control for start bit detection mechanism duration of start bit.Each bit refers to one slot.Set this bit to 1 for eMMC4.5 and above,set to 0 for SD applications.For eMMC4.5,start bit can be: 1'b0-Full cycle. 1'b1-less than one full cycle."]
+pub type HALFSTARTBIT_R = crate::FieldReader;
+#[doc = "Field `HALFSTARTBIT` writer - Control for start bit detection mechanism duration of start bit.Each bit refers to one slot.Set this bit to 1 for eMMC4.5 and above,set to 0 for SD applications.For eMMC4.5,start bit can be: 1'b0-Full cycle. 1'b1-less than one full cycle."]
+pub type HALFSTARTBIT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `HS400_MODE` reader - Set 1 to enable HS400 mode."]
+pub type HS400_MODE_R = crate::BitReader;
+#[doc = "Field `HS400_MODE` writer - Set 1 to enable HS400 mode."]
+pub type HS400_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 0:1 - Control for start bit detection mechanism duration of start bit.Each bit refers to one slot.Set this bit to 1 for eMMC4.5 and above,set to 0 for SD applications.For eMMC4.5,start bit can be: 1'b0-Full cycle. 1'b1-less than one full cycle."]
+    #[inline(always)]
+    pub fn halfstartbit(&self) -> HALFSTARTBIT_R {
+        HALFSTARTBIT_R::new((self.bits & 3) as u8)
+    }
+    #[doc = "Bit 31 - Set 1 to enable HS400 mode."]
+    #[inline(always)]
+    pub fn hs400_mode(&self) -> HS400_MODE_R {
+        HS400_MODE_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("EMMCDDR")
+            .field("halfstartbit", &self.halfstartbit())
+            .field("hs400_mode", &self.hs400_mode())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:1 - Control for start bit detection mechanism duration of start bit.Each bit refers to one slot.Set this bit to 1 for eMMC4.5 and above,set to 0 for SD applications.For eMMC4.5,start bit can be: 1'b0-Full cycle. 1'b1-less than one full cycle."]
+    #[inline(always)]
+    pub fn halfstartbit(&mut self) -> HALFSTARTBIT_W<EMMCDDR_SPEC> {
+        HALFSTARTBIT_W::new(self, 0)
+    }
+    #[doc = "Bit 31 - Set 1 to enable HS400 mode."]
+    #[inline(always)]
+    pub fn hs400_mode(&mut self) -> HS400_MODE_W<EMMCDDR_SPEC> {
+        HS400_MODE_W::new(self, 31)
+    }
+}
+#[doc = "eMMC DDR register\n\nYou can [`read`](crate::Reg::read) this register and get [`emmcddr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`emmcddr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct EMMCDDR_SPEC;
+impl crate::RegisterSpec for EMMCDDR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`emmcddr::R`](R) reader structure"]
+impl crate::Readable for EMMCDDR_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`emmcddr::W`](W) writer structure"]
+impl crate::Writable for EMMCDDR_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets EMMCDDR to value 0"]
+impl crate::Resettable for EMMCDDR_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sdhost/enshift.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `ENSHIFT` reader"]
+pub type R = crate::R<ENSHIFT_SPEC>;
+#[doc = "Register `ENSHIFT` writer"]
+pub type W = crate::W<ENSHIFT_SPEC>;
+#[doc = "Field `ENABLE_SHIFT` reader - Control for the amount of phase shift provided on the default enables in the design.Two bits assigned for each card. 2'b00-Default phase shift. 2'b01-Enables shifted to next immediate positive edge. 2'b10-Enables shifted to next immediate negative edge. 2'b11-Reserved."]
+pub type ENABLE_SHIFT_R = crate::FieldReader;
+#[doc = "Field `ENABLE_SHIFT` writer - Control for the amount of phase shift provided on the default enables in the design.Two bits assigned for each card. 2'b00-Default phase shift. 2'b01-Enables shifted to next immediate positive edge. 2'b10-Enables shifted to next immediate negative edge. 2'b11-Reserved."]
+pub type ENABLE_SHIFT_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+impl R {
+    #[doc = "Bits 0:3 - Control for the amount of phase shift provided on the default enables in the design.Two bits assigned for each card. 2'b00-Default phase shift. 2'b01-Enables shifted to next immediate positive edge. 2'b10-Enables shifted to next immediate negative edge. 2'b11-Reserved."]
+    #[inline(always)]
+    pub fn enable_shift(&self) -> ENABLE_SHIFT_R {
+        ENABLE_SHIFT_R::new((self.bits & 0x0f) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("ENSHIFT")
+            .field("enable_shift", &self.enable_shift())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:3 - Control for the amount of phase shift provided on the default enables in the design.Two bits assigned for each card. 2'b00-Default phase shift. 2'b01-Enables shifted to next immediate positive edge. 2'b10-Enables shifted to next immediate negative edge. 2'b11-Reserved."]
+    #[inline(always)]
+    pub fn enable_shift(&mut self) -> ENABLE_SHIFT_W<ENSHIFT_SPEC> {
+        ENABLE_SHIFT_W::new(self, 0)
+    }
+}
+#[doc = "Enable Phase Shift register\n\nYou can [`read`](crate::Reg::read) this register and get [`enshift::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`enshift::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ENSHIFT_SPEC;
+impl crate::RegisterSpec for ENSHIFT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`enshift::R`](R) reader structure"]
+impl crate::Readable for ENSHIFT_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`enshift::W`](W) writer structure"]
+impl crate::Writable for ENSHIFT_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets ENSHIFT to value 0"]
+impl crate::Resettable for ENSHIFT_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sdhost/fifoth.rs

@@ -0,0 +1,82 @@
+#[doc = "Register `FIFOTH` reader"]
+pub type R = crate::R<FIFOTH_SPEC>;
+#[doc = "Register `FIFOTH` writer"]
+pub type W = crate::W<FIFOTH_SPEC>;
+#[doc = "Field `TX_WMARK` reader - FIFO threshold watermark level when transmitting data to card. When FIFO data count is less than or equal to this number, DMA/FIFO request is raised. If Interrupt is enabled, then interrupt occurs. During end of packet, request or interrupt is generated, regardless of threshold programming.In non-DMA mode, when transmit FIFO threshold (TXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, on last interrupt, host is responsible for filling FIFO with only required remaining bytes (not before FIFO is full or after CIU completes data transfers, because FIFO may not be empty). In DMA mode, at end of packet, if last transfer is less than burst size, DMA controller does single cycles until required bytes are transferred."]
+pub type TX_WMARK_R = crate::FieldReader<u16>;
+#[doc = "Field `TX_WMARK` writer - FIFO threshold watermark level when transmitting data to card. When FIFO data count is less than or equal to this number, DMA/FIFO request is raised. If Interrupt is enabled, then interrupt occurs. During end of packet, request or interrupt is generated, regardless of threshold programming.In non-DMA mode, when transmit FIFO threshold (TXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, on last interrupt, host is responsible for filling FIFO with only required remaining bytes (not before FIFO is full or after CIU completes data transfers, because FIFO may not be empty). In DMA mode, at end of packet, if last transfer is less than burst size, DMA controller does single cycles until required bytes are transferred."]
+pub type TX_WMARK_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
+#[doc = "Field `RX_WMARK` reader - FIFO threshold watermark level when receiving data to card.When FIFO data count reaches greater than this number , DMA/FIFO request is raised. During end of packet, request is generated regardless of threshold programming in order to complete any remaining data.In non-DMA mode, when receiver FIFO threshold (RXDR) interrupt is enabled, then interrupt is generated instead of DMA request.During end of packet, interrupt is not generated if threshold programming is larger than any remaining data. It is responsibility of host to read remaining bytes on seeing Data Transfer Done interrupt.In DMA mode, at end of packet, even if remaining bytes are less than threshold, DMA request does single transfers to flush out any remaining bytes before Data Transfer Done interrupt is set."]
+pub type RX_WMARK_R = crate::FieldReader<u16>;
+#[doc = "Field `RX_WMARK` writer - FIFO threshold watermark level when receiving data to card.When FIFO data count reaches greater than this number , DMA/FIFO request is raised. During end of packet, request is generated regardless of threshold programming in order to complete any remaining data.In non-DMA mode, when receiver FIFO threshold (RXDR) interrupt is enabled, then interrupt is generated instead of DMA request.During end of packet, interrupt is not generated if threshold programming is larger than any remaining data. It is responsibility of host to read remaining bytes on seeing Data Transfer Done interrupt.In DMA mode, at end of packet, even if remaining bytes are less than threshold, DMA request does single transfers to flush out any remaining bytes before Data Transfer Done interrupt is set."]
+pub type RX_WMARK_W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>;
+#[doc = "Field `DMA_MULTIPLE_TRANSACTION_SIZE` reader - Burst size of multiple transaction, should be programmed same as DMA controller multiple-transaction-size SDHOST_SRC/DEST_MSIZE. 000: 1-byte transfer; 001: 4-byte transfer; 010: 8-byte transfer; 011: 16-byte transfer; 100: 32-byte transfer; 101: 64-byte transfer; 110: 128-byte transfer; 111: 256-byte transfer."]
+pub type DMA_MULTIPLE_TRANSACTION_SIZE_R = crate::FieldReader;
+#[doc = "Field `DMA_MULTIPLE_TRANSACTION_SIZE` writer - Burst size of multiple transaction, should be programmed same as DMA controller multiple-transaction-size SDHOST_SRC/DEST_MSIZE. 000: 1-byte transfer; 001: 4-byte transfer; 010: 8-byte transfer; 011: 16-byte transfer; 100: 32-byte transfer; 101: 64-byte transfer; 110: 128-byte transfer; 111: 256-byte transfer."]
+pub type DMA_MULTIPLE_TRANSACTION_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+impl R {
+    #[doc = "Bits 0:11 - FIFO threshold watermark level when transmitting data to card. When FIFO data count is less than or equal to this number, DMA/FIFO request is raised. If Interrupt is enabled, then interrupt occurs. During end of packet, request or interrupt is generated, regardless of threshold programming.In non-DMA mode, when transmit FIFO threshold (TXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, on last interrupt, host is responsible for filling FIFO with only required remaining bytes (not before FIFO is full or after CIU completes data transfers, because FIFO may not be empty). In DMA mode, at end of packet, if last transfer is less than burst size, DMA controller does single cycles until required bytes are transferred."]
+    #[inline(always)]
+    pub fn tx_wmark(&self) -> TX_WMARK_R {
+        TX_WMARK_R::new((self.bits & 0x0fff) as u16)
+    }
+    #[doc = "Bits 16:26 - FIFO threshold watermark level when receiving data to card.When FIFO data count reaches greater than this number , DMA/FIFO request is raised. During end of packet, request is generated regardless of threshold programming in order to complete any remaining data.In non-DMA mode, when receiver FIFO threshold (RXDR) interrupt is enabled, then interrupt is generated instead of DMA request.During end of packet, interrupt is not generated if threshold programming is larger than any remaining data. It is responsibility of host to read remaining bytes on seeing Data Transfer Done interrupt.In DMA mode, at end of packet, even if remaining bytes are less than threshold, DMA request does single transfers to flush out any remaining bytes before Data Transfer Done interrupt is set."]
+    #[inline(always)]
+    pub fn rx_wmark(&self) -> RX_WMARK_R {
+        RX_WMARK_R::new(((self.bits >> 16) & 0x07ff) as u16)
+    }
+    #[doc = "Bits 28:30 - Burst size of multiple transaction, should be programmed same as DMA controller multiple-transaction-size SDHOST_SRC/DEST_MSIZE. 000: 1-byte transfer; 001: 4-byte transfer; 010: 8-byte transfer; 011: 16-byte transfer; 100: 32-byte transfer; 101: 64-byte transfer; 110: 128-byte transfer; 111: 256-byte transfer."]
+    #[inline(always)]
+    pub fn dma_multiple_transaction_size(&self) -> DMA_MULTIPLE_TRANSACTION_SIZE_R {
+        DMA_MULTIPLE_TRANSACTION_SIZE_R::new(((self.bits >> 28) & 7) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("FIFOTH")
+            .field("tx_wmark", &self.tx_wmark())
+            .field("rx_wmark", &self.rx_wmark())
+            .field(
+                "dma_multiple_transaction_size",
+                &self.dma_multiple_transaction_size(),
+            )
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:11 - FIFO threshold watermark level when transmitting data to card. When FIFO data count is less than or equal to this number, DMA/FIFO request is raised. If Interrupt is enabled, then interrupt occurs. During end of packet, request or interrupt is generated, regardless of threshold programming.In non-DMA mode, when transmit FIFO threshold (TXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, on last interrupt, host is responsible for filling FIFO with only required remaining bytes (not before FIFO is full or after CIU completes data transfers, because FIFO may not be empty). In DMA mode, at end of packet, if last transfer is less than burst size, DMA controller does single cycles until required bytes are transferred."]
+    #[inline(always)]
+    pub fn tx_wmark(&mut self) -> TX_WMARK_W<FIFOTH_SPEC> {
+        TX_WMARK_W::new(self, 0)
+    }
+    #[doc = "Bits 16:26 - FIFO threshold watermark level when receiving data to card.When FIFO data count reaches greater than this number , DMA/FIFO request is raised. During end of packet, request is generated regardless of threshold programming in order to complete any remaining data.In non-DMA mode, when receiver FIFO threshold (RXDR) interrupt is enabled, then interrupt is generated instead of DMA request.During end of packet, interrupt is not generated if threshold programming is larger than any remaining data. It is responsibility of host to read remaining bytes on seeing Data Transfer Done interrupt.In DMA mode, at end of packet, even if remaining bytes are less than threshold, DMA request does single transfers to flush out any remaining bytes before Data Transfer Done interrupt is set."]
+    #[inline(always)]
+    pub fn rx_wmark(&mut self) -> RX_WMARK_W<FIFOTH_SPEC> {
+        RX_WMARK_W::new(self, 16)
+    }
+    #[doc = "Bits 28:30 - Burst size of multiple transaction, should be programmed same as DMA controller multiple-transaction-size SDHOST_SRC/DEST_MSIZE. 000: 1-byte transfer; 001: 4-byte transfer; 010: 8-byte transfer; 011: 16-byte transfer; 100: 32-byte transfer; 101: 64-byte transfer; 110: 128-byte transfer; 111: 256-byte transfer."]
+    #[inline(always)]
+    pub fn dma_multiple_transaction_size(
+        &mut self,
+    ) -> DMA_MULTIPLE_TRANSACTION_SIZE_W<FIFOTH_SPEC> {
+        DMA_MULTIPLE_TRANSACTION_SIZE_W::new(self, 28)
+    }
+}
+#[doc = "FIFO configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`fifoth::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifoth::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct FIFOTH_SPEC;
+impl crate::RegisterSpec for FIFOTH_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`fifoth::R`](R) reader structure"]
+impl crate::Readable for FIFOTH_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`fifoth::W`](W) writer structure"]
+impl crate::Writable for FIFOTH_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets FIFOTH to value 0"]
+impl crate::Resettable for FIFOTH_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sdhost/hcon.rs

@@ -0,0 +1,94 @@
+#[doc = "Register `HCON` reader"]
+pub type R = crate::R<HCON_SPEC>;
+#[doc = "Field `CARD_TYPE` reader - Hardware support SDIO and MMC."]
+pub type CARD_TYPE_R = crate::BitReader;
+#[doc = "Field `CARD_NUM` reader - Support card number is 2."]
+pub type CARD_NUM_R = crate::FieldReader;
+#[doc = "Field `BUS_TYPE` reader - Register config is APB bus."]
+pub type BUS_TYPE_R = crate::BitReader;
+#[doc = "Field `DATA_WIDTH` reader - Regisger data widht is 32."]
+pub type DATA_WIDTH_R = crate::FieldReader;
+#[doc = "Field `ADDR_WIDTH` reader - Register address width is 32."]
+pub type ADDR_WIDTH_R = crate::FieldReader;
+#[doc = "Field `DMA_WIDTH` reader - DMA data witdth is 32."]
+pub type DMA_WIDTH_R = crate::FieldReader;
+#[doc = "Field `RAM_INDISE` reader - Inside RAM in SDMMC module."]
+pub type RAM_INDISE_R = crate::BitReader;
+#[doc = "Field `HOLD` reader - Have a hold regiser in data path ."]
+pub type HOLD_R = crate::BitReader;
+#[doc = "Field `NUM_CLK_DIV` reader - Have 4 clk divider in design ."]
+pub type NUM_CLK_DIV_R = crate::FieldReader;
+impl R {
+    #[doc = "Bit 0 - Hardware support SDIO and MMC."]
+    #[inline(always)]
+    pub fn card_type(&self) -> CARD_TYPE_R {
+        CARD_TYPE_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bits 1:5 - Support card number is 2."]
+    #[inline(always)]
+    pub fn card_num(&self) -> CARD_NUM_R {
+        CARD_NUM_R::new(((self.bits >> 1) & 0x1f) as u8)
+    }
+    #[doc = "Bit 6 - Register config is APB bus."]
+    #[inline(always)]
+    pub fn bus_type(&self) -> BUS_TYPE_R {
+        BUS_TYPE_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bits 7:9 - Regisger data widht is 32."]
+    #[inline(always)]
+    pub fn data_width(&self) -> DATA_WIDTH_R {
+        DATA_WIDTH_R::new(((self.bits >> 7) & 7) as u8)
+    }
+    #[doc = "Bits 10:15 - Register address width is 32."]
+    #[inline(always)]
+    pub fn addr_width(&self) -> ADDR_WIDTH_R {
+        ADDR_WIDTH_R::new(((self.bits >> 10) & 0x3f) as u8)
+    }
+    #[doc = "Bits 18:20 - DMA data witdth is 32."]
+    #[inline(always)]
+    pub fn dma_width(&self) -> DMA_WIDTH_R {
+        DMA_WIDTH_R::new(((self.bits >> 18) & 7) as u8)
+    }
+    #[doc = "Bit 21 - Inside RAM in SDMMC module."]
+    #[inline(always)]
+    pub fn ram_indise(&self) -> RAM_INDISE_R {
+        RAM_INDISE_R::new(((self.bits >> 21) & 1) != 0)
+    }
+    #[doc = "Bit 22 - Have a hold regiser in data path ."]
+    #[inline(always)]
+    pub fn hold(&self) -> HOLD_R {
+        HOLD_R::new(((self.bits >> 22) & 1) != 0)
+    }
+    #[doc = "Bits 24:25 - Have 4 clk divider in design ."]
+    #[inline(always)]
+    pub fn num_clk_div(&self) -> NUM_CLK_DIV_R {
+        NUM_CLK_DIV_R::new(((self.bits >> 24) & 3) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("HCON")
+            .field("card_type", &self.card_type())
+            .field("card_num", &self.card_num())
+            .field("bus_type", &self.bus_type())
+            .field("data_width", &self.data_width())
+            .field("addr_width", &self.addr_width())
+            .field("dma_width", &self.dma_width())
+            .field("ram_indise", &self.ram_indise())
+            .field("hold", &self.hold())
+            .field("num_clk_div", &self.num_clk_div())
+            .finish()
+    }
+}
+#[doc = "Hardware feature register\n\nYou can [`read`](crate::Reg::read) this register and get [`hcon::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct HCON_SPEC;
+impl crate::RegisterSpec for HCON_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`hcon::R`](R) reader structure"]
+impl crate::Readable for HCON_SPEC {}
+#[doc = "`reset()` method sets HCON to value 0x0344_4cc3"]
+impl crate::Resettable for HCON_SPEC {
+    const RESET_VALUE: u32 = 0x0344_4cc3;
+}

vendor/esp32s3/src/sdhost/idinten.rs

@@ -0,0 +1,137 @@
+#[doc = "Register `IDINTEN` reader"]
+pub type R = crate::R<IDINTEN_SPEC>;
+#[doc = "Register `IDINTEN` writer"]
+pub type W = crate::W<IDINTEN_SPEC>;
+#[doc = "Field `TI` reader - Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit Interrupt is enabled. When reset, Transmit Interrupt is disabled."]
+pub type TI_R = crate::BitReader;
+#[doc = "Field `TI` writer - Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit Interrupt is enabled. When reset, Transmit Interrupt is disabled."]
+pub type TI_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RI` reader - Receive Interrupt Enable. When set with Normal Interrupt Summary Enable, Receive Interrupt is enabled. When reset, Receive Interrupt is disabled."]
+pub type RI_R = crate::BitReader;
+#[doc = "Field `RI` writer - Receive Interrupt Enable. When set with Normal Interrupt Summary Enable, Receive Interrupt is enabled. When reset, Receive Interrupt is disabled."]
+pub type RI_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FBE` reader - Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable, the Fatal Bus Error Interrupt is enabled. When reset, Fatal Bus Error Enable Interrupt is disabled."]
+pub type FBE_R = crate::BitReader;
+#[doc = "Field `FBE` writer - Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable, the Fatal Bus Error Interrupt is enabled. When reset, Fatal Bus Error Enable Interrupt is disabled."]
+pub type FBE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DU` reader - Descriptor Unavailable Interrupt. When set along with Abnormal Interrupt Summary Enable, the DU interrupt is enabled."]
+pub type DU_R = crate::BitReader;
+#[doc = "Field `DU` writer - Descriptor Unavailable Interrupt. When set along with Abnormal Interrupt Summary Enable, the DU interrupt is enabled."]
+pub type DU_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CES` reader - Card Error summary Interrupt Enable. When set, it enables the Card Interrupt summary."]
+pub type CES_R = crate::BitReader;
+#[doc = "Field `CES` writer - Card Error summary Interrupt Enable. When set, it enables the Card Interrupt summary."]
+pub type CES_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `NI` reader - Normal Interrupt Summary Enable. When set, a normal interrupt is enabled. When reset, a normal interrupt is disabled. This bit enables the following bits: IDINTEN\\[0\\]: Transmit Interrupt; IDINTEN\\[1\\]: Receive Interrupt."]
+pub type NI_R = crate::BitReader;
+#[doc = "Field `NI` writer - Normal Interrupt Summary Enable. When set, a normal interrupt is enabled. When reset, a normal interrupt is disabled. This bit enables the following bits: IDINTEN\\[0\\]: Transmit Interrupt; IDINTEN\\[1\\]: Receive Interrupt."]
+pub type NI_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `AI` reader - Abnormal Interrupt Summary Enable. When set, an abnormal interrupt is enabled. This bit enables the following bits: IDINTEN\\[2\\]: Fatal Bus Error Interrupt; IDINTEN\\[4\\]: DU Interrupt."]
+pub type AI_R = crate::BitReader;
+#[doc = "Field `AI` writer - Abnormal Interrupt Summary Enable. When set, an abnormal interrupt is enabled. This bit enables the following bits: IDINTEN\\[2\\]: Fatal Bus Error Interrupt; IDINTEN\\[4\\]: DU Interrupt."]
+pub type AI_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit Interrupt is enabled. When reset, Transmit Interrupt is disabled."]
+    #[inline(always)]
+    pub fn ti(&self) -> TI_R {
+        TI_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Receive Interrupt Enable. When set with Normal Interrupt Summary Enable, Receive Interrupt is enabled. When reset, Receive Interrupt is disabled."]
+    #[inline(always)]
+    pub fn ri(&self) -> RI_R {
+        RI_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable, the Fatal Bus Error Interrupt is enabled. When reset, Fatal Bus Error Enable Interrupt is disabled."]
+    #[inline(always)]
+    pub fn fbe(&self) -> FBE_R {
+        FBE_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Descriptor Unavailable Interrupt. When set along with Abnormal Interrupt Summary Enable, the DU interrupt is enabled."]
+    #[inline(always)]
+    pub fn du(&self) -> DU_R {
+        DU_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - Card Error summary Interrupt Enable. When set, it enables the Card Interrupt summary."]
+    #[inline(always)]
+    pub fn ces(&self) -> CES_R {
+        CES_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 8 - Normal Interrupt Summary Enable. When set, a normal interrupt is enabled. When reset, a normal interrupt is disabled. This bit enables the following bits: IDINTEN\\[0\\]: Transmit Interrupt; IDINTEN\\[1\\]: Receive Interrupt."]
+    #[inline(always)]
+    pub fn ni(&self) -> NI_R {
+        NI_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - Abnormal Interrupt Summary Enable. When set, an abnormal interrupt is enabled. This bit enables the following bits: IDINTEN\\[2\\]: Fatal Bus Error Interrupt; IDINTEN\\[4\\]: DU Interrupt."]
+    #[inline(always)]
+    pub fn ai(&self) -> AI_R {
+        AI_R::new(((self.bits >> 9) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("IDINTEN")
+            .field("ti", &self.ti())
+            .field("ri", &self.ri())
+            .field("fbe", &self.fbe())
+            .field("du", &self.du())
+            .field("ces", &self.ces())
+            .field("ni", &self.ni())
+            .field("ai", &self.ai())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit Interrupt is enabled. When reset, Transmit Interrupt is disabled."]
+    #[inline(always)]
+    pub fn ti(&mut self) -> TI_W<IDINTEN_SPEC> {
+        TI_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - Receive Interrupt Enable. When set with Normal Interrupt Summary Enable, Receive Interrupt is enabled. When reset, Receive Interrupt is disabled."]
+    #[inline(always)]
+    pub fn ri(&mut self) -> RI_W<IDINTEN_SPEC> {
+        RI_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable, the Fatal Bus Error Interrupt is enabled. When reset, Fatal Bus Error Enable Interrupt is disabled."]
+    #[inline(always)]
+    pub fn fbe(&mut self) -> FBE_W<IDINTEN_SPEC> {
+        FBE_W::new(self, 2)
+    }
+    #[doc = "Bit 4 - Descriptor Unavailable Interrupt. When set along with Abnormal Interrupt Summary Enable, the DU interrupt is enabled."]
+    #[inline(always)]
+    pub fn du(&mut self) -> DU_W<IDINTEN_SPEC> {
+        DU_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - Card Error summary Interrupt Enable. When set, it enables the Card Interrupt summary."]
+    #[inline(always)]
+    pub fn ces(&mut self) -> CES_W<IDINTEN_SPEC> {
+        CES_W::new(self, 5)
+    }
+    #[doc = "Bit 8 - Normal Interrupt Summary Enable. When set, a normal interrupt is enabled. When reset, a normal interrupt is disabled. This bit enables the following bits: IDINTEN\\[0\\]: Transmit Interrupt; IDINTEN\\[1\\]: Receive Interrupt."]
+    #[inline(always)]
+    pub fn ni(&mut self) -> NI_W<IDINTEN_SPEC> {
+        NI_W::new(self, 8)
+    }
+    #[doc = "Bit 9 - Abnormal Interrupt Summary Enable. When set, an abnormal interrupt is enabled. This bit enables the following bits: IDINTEN\\[2\\]: Fatal Bus Error Interrupt; IDINTEN\\[4\\]: DU Interrupt."]
+    #[inline(always)]
+    pub fn ai(&mut self) -> AI_W<IDINTEN_SPEC> {
+        AI_W::new(self, 9)
+    }
+}
+#[doc = "IDMAC interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`idinten::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`idinten::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct IDINTEN_SPEC;
+impl crate::RegisterSpec for IDINTEN_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`idinten::R`](R) reader structure"]
+impl crate::Readable for IDINTEN_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`idinten::W`](W) writer structure"]
+impl crate::Writable for IDINTEN_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets IDINTEN to value 0"]
+impl crate::Resettable for IDINTEN_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sdhost/idsts.rs

@@ -0,0 +1,167 @@
+#[doc = "Register `IDSTS` reader"]
+pub type R = crate::R<IDSTS_SPEC>;
+#[doc = "Register `IDSTS` writer"]
+pub type W = crate::W<IDSTS_SPEC>;
+#[doc = "Field `TI` reader - Transmit Interrupt. Indicates that data transmission is finished for a descriptor. Writing 1 clears this bit."]
+pub type TI_R = crate::BitReader;
+#[doc = "Field `TI` writer - Transmit Interrupt. Indicates that data transmission is finished for a descriptor. Writing 1 clears this bit."]
+pub type TI_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RI` reader - Receive Interrupt. Indicates the completion of data reception for a descriptor. Writing 1 clears this bit."]
+pub type RI_R = crate::BitReader;
+#[doc = "Field `RI` writer - Receive Interrupt. Indicates the completion of data reception for a descriptor. Writing 1 clears this bit."]
+pub type RI_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FBE` reader - Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS\\[12:10\\]) . When this bit is set, the DMA disables all its bus accesses. Writing 1 clears this bit."]
+pub type FBE_R = crate::BitReader;
+#[doc = "Field `FBE` writer - Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS\\[12:10\\]) . When this bit is set, the DMA disables all its bus accesses. Writing 1 clears this bit."]
+pub type FBE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DU` reader - Descriptor Unavailable Interrupt. This bit is set when the descriptor is unavailable due to OWNER bit = 0 (DES0\\[31\\] = 0). Writing 1 clears this bit."]
+pub type DU_R = crate::BitReader;
+#[doc = "Field `DU` writer - Descriptor Unavailable Interrupt. This bit is set when the descriptor is unavailable due to OWNER bit = 0 (DES0\\[31\\] = 0). Writing 1 clears this bit."]
+pub type DU_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CES` reader - Card Error Summary. Indicates the status of the transaction to/from the card, also present in RINTSTS. Indicates the logical OR of the following bits: EBE : End Bit Error; RTO : Response Timeout/Boot Ack Timeout; RCRC : Response CRC; SBE : Start Bit Error; DRTO : Data Read Timeout/BDS timeout; DCRC : Data CRC for Receive; RE : Response Error. Writing 1 clears this bit. The abort condition of the IDMAC depends on the setting of this CES bit. If the CES bit is enabled, then the IDMAC aborts on a response error."]
+pub type CES_R = crate::BitReader;
+#[doc = "Field `CES` writer - Card Error Summary. Indicates the status of the transaction to/from the card, also present in RINTSTS. Indicates the logical OR of the following bits: EBE : End Bit Error; RTO : Response Timeout/Boot Ack Timeout; RCRC : Response CRC; SBE : Start Bit Error; DRTO : Data Read Timeout/BDS timeout; DCRC : Data CRC for Receive; RE : Response Error. Writing 1 clears this bit. The abort condition of the IDMAC depends on the setting of this CES bit. If the CES bit is enabled, then the IDMAC aborts on a response error."]
+pub type CES_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `NIS` reader - Normal Interrupt Summary. Logical OR of the following: IDSTS\\[0\\] : Transmit Interrupt, IDSTS\\[1\\] : Receive Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes NIS to be set is cleared. Writing 1 clears this bit."]
+pub type NIS_R = crate::BitReader;
+#[doc = "Field `NIS` writer - Normal Interrupt Summary. Logical OR of the following: IDSTS\\[0\\] : Transmit Interrupt, IDSTS\\[1\\] : Receive Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes NIS to be set is cleared. Writing 1 clears this bit."]
+pub type NIS_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `AIS` reader - Abnormal Interrupt Summary. Logical OR of the following: IDSTS\\[2\\] : Fatal Bus Interrupt, IDSTS\\[4\\] : DU bit Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared. Writing 1 clears this bit."]
+pub type AIS_R = crate::BitReader;
+#[doc = "Field `AIS` writer - Abnormal Interrupt Summary. Logical OR of the following: IDSTS\\[2\\] : Fatal Bus Interrupt, IDSTS\\[4\\] : DU bit Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared. Writing 1 clears this bit."]
+pub type AIS_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FBE_CODE` reader - Fatal Bus Error Code. Indicates the type of error that caused a Bus Error. Valid only when the Fatal Bus Error bit IDSTS\\[2\\] is set. This field does not generate an interrupt. 001: Host Abort received during transmission; 010: Host Abort received during reception; Others: Reserved."]
+pub type FBE_CODE_R = crate::FieldReader;
+#[doc = "Field `FBE_CODE` writer - Fatal Bus Error Code. Indicates the type of error that caused a Bus Error. Valid only when the Fatal Bus Error bit IDSTS\\[2\\] is set. This field does not generate an interrupt. 001: Host Abort received during transmission; 010: Host Abort received during reception; Others: Reserved."]
+pub type FBE_CODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `FSM` reader - DMAC FSM present state. 0: DMA_IDLE (idle state); 1: DMA_SUSPEND (suspend state); 2: DESC_RD (descriptor reading state); 3: DESC_CHK (descriptor checking state); 4: DMA_RD_REQ_WAIT (read-data request waiting state); 5: DMA_WR_REQ_WAIT (write-data request waiting state); 6: DMA_RD (data-read state); 7: DMA_WR (data-write state); 8: DESC_CLOSE (descriptor close state)."]
+pub type FSM_R = crate::FieldReader;
+#[doc = "Field `FSM` writer - DMAC FSM present state. 0: DMA_IDLE (idle state); 1: DMA_SUSPEND (suspend state); 2: DESC_RD (descriptor reading state); 3: DESC_CHK (descriptor checking state); 4: DMA_RD_REQ_WAIT (read-data request waiting state); 5: DMA_WR_REQ_WAIT (write-data request waiting state); 6: DMA_RD (data-read state); 7: DMA_WR (data-write state); 8: DESC_CLOSE (descriptor close state)."]
+pub type FSM_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+impl R {
+    #[doc = "Bit 0 - Transmit Interrupt. Indicates that data transmission is finished for a descriptor. Writing 1 clears this bit."]
+    #[inline(always)]
+    pub fn ti(&self) -> TI_R {
+        TI_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Receive Interrupt. Indicates the completion of data reception for a descriptor. Writing 1 clears this bit."]
+    #[inline(always)]
+    pub fn ri(&self) -> RI_R {
+        RI_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS\\[12:10\\]) . When this bit is set, the DMA disables all its bus accesses. Writing 1 clears this bit."]
+    #[inline(always)]
+    pub fn fbe(&self) -> FBE_R {
+        FBE_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Descriptor Unavailable Interrupt. This bit is set when the descriptor is unavailable due to OWNER bit = 0 (DES0\\[31\\] = 0). Writing 1 clears this bit."]
+    #[inline(always)]
+    pub fn du(&self) -> DU_R {
+        DU_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - Card Error Summary. Indicates the status of the transaction to/from the card, also present in RINTSTS. Indicates the logical OR of the following bits: EBE : End Bit Error; RTO : Response Timeout/Boot Ack Timeout; RCRC : Response CRC; SBE : Start Bit Error; DRTO : Data Read Timeout/BDS timeout; DCRC : Data CRC for Receive; RE : Response Error. Writing 1 clears this bit. The abort condition of the IDMAC depends on the setting of this CES bit. If the CES bit is enabled, then the IDMAC aborts on a response error."]
+    #[inline(always)]
+    pub fn ces(&self) -> CES_R {
+        CES_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 8 - Normal Interrupt Summary. Logical OR of the following: IDSTS\\[0\\] : Transmit Interrupt, IDSTS\\[1\\] : Receive Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes NIS to be set is cleared. Writing 1 clears this bit."]
+    #[inline(always)]
+    pub fn nis(&self) -> NIS_R {
+        NIS_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - Abnormal Interrupt Summary. Logical OR of the following: IDSTS\\[2\\] : Fatal Bus Interrupt, IDSTS\\[4\\] : DU bit Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared. Writing 1 clears this bit."]
+    #[inline(always)]
+    pub fn ais(&self) -> AIS_R {
+        AIS_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bits 10:12 - Fatal Bus Error Code. Indicates the type of error that caused a Bus Error. Valid only when the Fatal Bus Error bit IDSTS\\[2\\] is set. This field does not generate an interrupt. 001: Host Abort received during transmission; 010: Host Abort received during reception; Others: Reserved."]
+    #[inline(always)]
+    pub fn fbe_code(&self) -> FBE_CODE_R {
+        FBE_CODE_R::new(((self.bits >> 10) & 7) as u8)
+    }
+    #[doc = "Bits 13:16 - DMAC FSM present state. 0: DMA_IDLE (idle state); 1: DMA_SUSPEND (suspend state); 2: DESC_RD (descriptor reading state); 3: DESC_CHK (descriptor checking state); 4: DMA_RD_REQ_WAIT (read-data request waiting state); 5: DMA_WR_REQ_WAIT (write-data request waiting state); 6: DMA_RD (data-read state); 7: DMA_WR (data-write state); 8: DESC_CLOSE (descriptor close state)."]
+    #[inline(always)]
+    pub fn fsm(&self) -> FSM_R {
+        FSM_R::new(((self.bits >> 13) & 0x0f) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("IDSTS")
+            .field("ti", &self.ti())
+            .field("ri", &self.ri())
+            .field("fbe", &self.fbe())
+            .field("du", &self.du())
+            .field("ces", &self.ces())
+            .field("nis", &self.nis())
+            .field("ais", &self.ais())
+            .field("fbe_code", &self.fbe_code())
+            .field("fsm", &self.fsm())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Transmit Interrupt. Indicates that data transmission is finished for a descriptor. Writing 1 clears this bit."]
+    #[inline(always)]
+    pub fn ti(&mut self) -> TI_W<IDSTS_SPEC> {
+        TI_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - Receive Interrupt. Indicates the completion of data reception for a descriptor. Writing 1 clears this bit."]
+    #[inline(always)]
+    pub fn ri(&mut self) -> RI_W<IDSTS_SPEC> {
+        RI_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS\\[12:10\\]) . When this bit is set, the DMA disables all its bus accesses. Writing 1 clears this bit."]
+    #[inline(always)]
+    pub fn fbe(&mut self) -> FBE_W<IDSTS_SPEC> {
+        FBE_W::new(self, 2)
+    }
+    #[doc = "Bit 4 - Descriptor Unavailable Interrupt. This bit is set when the descriptor is unavailable due to OWNER bit = 0 (DES0\\[31\\] = 0). Writing 1 clears this bit."]
+    #[inline(always)]
+    pub fn du(&mut self) -> DU_W<IDSTS_SPEC> {
+        DU_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - Card Error Summary. Indicates the status of the transaction to/from the card, also present in RINTSTS. Indicates the logical OR of the following bits: EBE : End Bit Error; RTO : Response Timeout/Boot Ack Timeout; RCRC : Response CRC; SBE : Start Bit Error; DRTO : Data Read Timeout/BDS timeout; DCRC : Data CRC for Receive; RE : Response Error. Writing 1 clears this bit. The abort condition of the IDMAC depends on the setting of this CES bit. If the CES bit is enabled, then the IDMAC aborts on a response error."]
+    #[inline(always)]
+    pub fn ces(&mut self) -> CES_W<IDSTS_SPEC> {
+        CES_W::new(self, 5)
+    }
+    #[doc = "Bit 8 - Normal Interrupt Summary. Logical OR of the following: IDSTS\\[0\\] : Transmit Interrupt, IDSTS\\[1\\] : Receive Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes NIS to be set is cleared. Writing 1 clears this bit."]
+    #[inline(always)]
+    pub fn nis(&mut self) -> NIS_W<IDSTS_SPEC> {
+        NIS_W::new(self, 8)
+    }
+    #[doc = "Bit 9 - Abnormal Interrupt Summary. Logical OR of the following: IDSTS\\[2\\] : Fatal Bus Interrupt, IDSTS\\[4\\] : DU bit Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared. Writing 1 clears this bit."]
+    #[inline(always)]
+    pub fn ais(&mut self) -> AIS_W<IDSTS_SPEC> {
+        AIS_W::new(self, 9)
+    }
+    #[doc = "Bits 10:12 - Fatal Bus Error Code. Indicates the type of error that caused a Bus Error. Valid only when the Fatal Bus Error bit IDSTS\\[2\\] is set. This field does not generate an interrupt. 001: Host Abort received during transmission; 010: Host Abort received during reception; Others: Reserved."]
+    #[inline(always)]
+    pub fn fbe_code(&mut self) -> FBE_CODE_W<IDSTS_SPEC> {
+        FBE_CODE_W::new(self, 10)
+    }
+    #[doc = "Bits 13:16 - DMAC FSM present state. 0: DMA_IDLE (idle state); 1: DMA_SUSPEND (suspend state); 2: DESC_RD (descriptor reading state); 3: DESC_CHK (descriptor checking state); 4: DMA_RD_REQ_WAIT (read-data request waiting state); 5: DMA_WR_REQ_WAIT (write-data request waiting state); 6: DMA_RD (data-read state); 7: DMA_WR (data-write state); 8: DESC_CLOSE (descriptor close state)."]
+    #[inline(always)]
+    pub fn fsm(&mut self) -> FSM_W<IDSTS_SPEC> {
+        FSM_W::new(self, 13)
+    }
+}
+#[doc = "IDMAC status register\n\nYou can [`read`](crate::Reg::read) this register and get [`idsts::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`idsts::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct IDSTS_SPEC;
+impl crate::RegisterSpec for IDSTS_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`idsts::R`](R) reader structure"]
+impl crate::Readable for IDSTS_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`idsts::W`](W) writer structure"]
+impl crate::Writable for IDSTS_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets IDSTS to value 0"]
+impl crate::Resettable for IDSTS_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sdhost/intmask.rs

@@ -0,0 +1,62 @@
+#[doc = "Register `INTMASK` reader"]
+pub type R = crate::R<INTMASK_SPEC>;
+#[doc = "Register `INTMASK` writer"]
+pub type W = crate::W<INTMASK_SPEC>;
+#[doc = "Field `INT_MASK` reader - These bits used to mask unwanted interrupts. A value of 0 masks interrupt, and a value of 1 enables the interrupt. Bit 15 (EBE): End-bit error/no CRC error; Bit 14 (ACD): Auto command done; Bit 13 (SBE/BCI): Rx Start Bit Error; Bit 12 (HLE): Hardware locked write error; Bit 11 (FRUN): FIFO underrun/overrun error; Bit 10 (HTO): Data starvation-by-host timeout; Bit 9 (DRTO): Data read timeout; Bit 8 (RTO): Response timeout; Bit 7 (DCRC): Data CRC error; Bit 6 (RCRC): Response CRC error; Bit 5 (RXDR): Receive FIFO data request; Bit 4 (TXDR): Transmit FIFO data request; Bit 3 (DTO): Data transfer over; Bit 2 (CD): Command done; Bit 1 (RE): Response error; Bit 0 (CD): Card detect."]
+pub type INT_MASK_R = crate::FieldReader<u16>;
+#[doc = "Field `INT_MASK` writer - These bits used to mask unwanted interrupts. A value of 0 masks interrupt, and a value of 1 enables the interrupt. Bit 15 (EBE): End-bit error/no CRC error; Bit 14 (ACD): Auto command done; Bit 13 (SBE/BCI): Rx Start Bit Error; Bit 12 (HLE): Hardware locked write error; Bit 11 (FRUN): FIFO underrun/overrun error; Bit 10 (HTO): Data starvation-by-host timeout; Bit 9 (DRTO): Data read timeout; Bit 8 (RTO): Response timeout; Bit 7 (DCRC): Data CRC error; Bit 6 (RCRC): Response CRC error; Bit 5 (RXDR): Receive FIFO data request; Bit 4 (TXDR): Transmit FIFO data request; Bit 3 (DTO): Data transfer over; Bit 2 (CD): Command done; Bit 1 (RE): Response error; Bit 0 (CD): Card detect."]
+pub type INT_MASK_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
+#[doc = "Field `SDIO_INT_MASK` reader - SDIO interrupt mask, one bit for each card. Bit\\[17:16\\] correspond to card\\[15:0\\] respectively. When masked, SDIO interrupt detection for that card is disabled. 0 masks an interrupt, and 1 enables an interrupt."]
+pub type SDIO_INT_MASK_R = crate::FieldReader;
+#[doc = "Field `SDIO_INT_MASK` writer - SDIO interrupt mask, one bit for each card. Bit\\[17:16\\] correspond to card\\[15:0\\] respectively. When masked, SDIO interrupt detection for that card is disabled. 0 masks an interrupt, and 1 enables an interrupt."]
+pub type SDIO_INT_MASK_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+impl R {
+    #[doc = "Bits 0:15 - These bits used to mask unwanted interrupts. A value of 0 masks interrupt, and a value of 1 enables the interrupt. Bit 15 (EBE): End-bit error/no CRC error; Bit 14 (ACD): Auto command done; Bit 13 (SBE/BCI): Rx Start Bit Error; Bit 12 (HLE): Hardware locked write error; Bit 11 (FRUN): FIFO underrun/overrun error; Bit 10 (HTO): Data starvation-by-host timeout; Bit 9 (DRTO): Data read timeout; Bit 8 (RTO): Response timeout; Bit 7 (DCRC): Data CRC error; Bit 6 (RCRC): Response CRC error; Bit 5 (RXDR): Receive FIFO data request; Bit 4 (TXDR): Transmit FIFO data request; Bit 3 (DTO): Data transfer over; Bit 2 (CD): Command done; Bit 1 (RE): Response error; Bit 0 (CD): Card detect."]
+    #[inline(always)]
+    pub fn int_mask(&self) -> INT_MASK_R {
+        INT_MASK_R::new((self.bits & 0xffff) as u16)
+    }
+    #[doc = "Bits 16:17 - SDIO interrupt mask, one bit for each card. Bit\\[17:16\\] correspond to card\\[15:0\\] respectively. When masked, SDIO interrupt detection for that card is disabled. 0 masks an interrupt, and 1 enables an interrupt."]
+    #[inline(always)]
+    pub fn sdio_int_mask(&self) -> SDIO_INT_MASK_R {
+        SDIO_INT_MASK_R::new(((self.bits >> 16) & 3) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("INTMASK")
+            .field("int_mask", &self.int_mask())
+            .field("sdio_int_mask", &self.sdio_int_mask())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:15 - These bits used to mask unwanted interrupts. A value of 0 masks interrupt, and a value of 1 enables the interrupt. Bit 15 (EBE): End-bit error/no CRC error; Bit 14 (ACD): Auto command done; Bit 13 (SBE/BCI): Rx Start Bit Error; Bit 12 (HLE): Hardware locked write error; Bit 11 (FRUN): FIFO underrun/overrun error; Bit 10 (HTO): Data starvation-by-host timeout; Bit 9 (DRTO): Data read timeout; Bit 8 (RTO): Response timeout; Bit 7 (DCRC): Data CRC error; Bit 6 (RCRC): Response CRC error; Bit 5 (RXDR): Receive FIFO data request; Bit 4 (TXDR): Transmit FIFO data request; Bit 3 (DTO): Data transfer over; Bit 2 (CD): Command done; Bit 1 (RE): Response error; Bit 0 (CD): Card detect."]
+    #[inline(always)]
+    pub fn int_mask(&mut self) -> INT_MASK_W<INTMASK_SPEC> {
+        INT_MASK_W::new(self, 0)
+    }
+    #[doc = "Bits 16:17 - SDIO interrupt mask, one bit for each card. Bit\\[17:16\\] correspond to card\\[15:0\\] respectively. When masked, SDIO interrupt detection for that card is disabled. 0 masks an interrupt, and 1 enables an interrupt."]
+    #[inline(always)]
+    pub fn sdio_int_mask(&mut self) -> SDIO_INT_MASK_W<INTMASK_SPEC> {
+        SDIO_INT_MASK_W::new(self, 16)
+    }
+}
+#[doc = "SDIO interrupt mask register\n\nYou can [`read`](crate::Reg::read) this register and get [`intmask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intmask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct INTMASK_SPEC;
+impl crate::RegisterSpec for INTMASK_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`intmask::R`](R) reader structure"]
+impl crate::Readable for INTMASK_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`intmask::W`](W) writer structure"]
+impl crate::Writable for INTMASK_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets INTMASK to value 0"]
+impl crate::Resettable for INTMASK_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sdhost/mintsts.rs

@@ -0,0 +1,38 @@
+#[doc = "Register `MINTSTS` reader"]
+pub type R = crate::R<MINTSTS_SPEC>;
+#[doc = "Field `INT_STATUS_MSK` reader - Interrupt enabled only if corresponding bit in interrupt mask register is set. Bit 15 (EBE): End-bit error/no CRC error; Bit 14 (ACD): Auto command done; Bit 13 (SBE/BCI): RX Start Bit Error; Bit 12 (HLE): Hardware locked write error; Bit 11 (FRUN): FIFO underrun/overrun error; Bit 10 (HTO): Data starvation by host timeout (HTO); Bit 9 (DTRO): Data read timeout; Bit 8 (RTO): Response timeout; Bit 7 (DCRC): Data CRC error; Bit 6 (RCRC): Response CRC error; Bit 5 (RXDR): Receive FIFO data request; Bit 4 (TXDR): Transmit FIFO data request; Bit 3 (DTO): Data transfer over; Bit 2 (CD): Command done; Bit 1 (RE): Response error; Bit 0 (CD): Card detect."]
+pub type INT_STATUS_MSK_R = crate::FieldReader<u16>;
+#[doc = "Field `SDIO_INTERRUPT_MSK` reader - Interrupt from SDIO card, one bit for each card. Bit\\[17:16\\] correspond to card1 and card0, respectively. SDIO interrupt for card is enabled only if corresponding sdhost_sdio_int_mask bit is set in Interrupt mask register (Setting mask bit enables interrupt)."]
+pub type SDIO_INTERRUPT_MSK_R = crate::FieldReader;
+impl R {
+    #[doc = "Bits 0:15 - Interrupt enabled only if corresponding bit in interrupt mask register is set. Bit 15 (EBE): End-bit error/no CRC error; Bit 14 (ACD): Auto command done; Bit 13 (SBE/BCI): RX Start Bit Error; Bit 12 (HLE): Hardware locked write error; Bit 11 (FRUN): FIFO underrun/overrun error; Bit 10 (HTO): Data starvation by host timeout (HTO); Bit 9 (DTRO): Data read timeout; Bit 8 (RTO): Response timeout; Bit 7 (DCRC): Data CRC error; Bit 6 (RCRC): Response CRC error; Bit 5 (RXDR): Receive FIFO data request; Bit 4 (TXDR): Transmit FIFO data request; Bit 3 (DTO): Data transfer over; Bit 2 (CD): Command done; Bit 1 (RE): Response error; Bit 0 (CD): Card detect."]
+    #[inline(always)]
+    pub fn int_status_msk(&self) -> INT_STATUS_MSK_R {
+        INT_STATUS_MSK_R::new((self.bits & 0xffff) as u16)
+    }
+    #[doc = "Bits 16:17 - Interrupt from SDIO card, one bit for each card. Bit\\[17:16\\] correspond to card1 and card0, respectively. SDIO interrupt for card is enabled only if corresponding sdhost_sdio_int_mask bit is set in Interrupt mask register (Setting mask bit enables interrupt)."]
+    #[inline(always)]
+    pub fn sdio_interrupt_msk(&self) -> SDIO_INTERRUPT_MSK_R {
+        SDIO_INTERRUPT_MSK_R::new(((self.bits >> 16) & 3) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("MINTSTS")
+            .field("int_status_msk", &self.int_status_msk())
+            .field("sdio_interrupt_msk", &self.sdio_interrupt_msk())
+            .finish()
+    }
+}
+#[doc = "Masked interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`mintsts::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct MINTSTS_SPEC;
+impl crate::RegisterSpec for MINTSTS_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`mintsts::R`](R) reader structure"]
+impl crate::Readable for MINTSTS_SPEC {}
+#[doc = "`reset()` method sets MINTSTS to value 0"]
+impl crate::Resettable for MINTSTS_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sdhost/pldmnd.rs

@@ -0,0 +1,32 @@
+#[doc = "Register `PLDMND` writer"]
+pub type W = crate::W<PLDMND_SPEC>;
+#[doc = "Field `PD` writer - Poll Demand. If the OWNER bit of a descriptor is not set, the FSM goes to the Suspend state. The host needs to write any value into this register for the IDMAC FSM to resume normal descriptor fetch operation. This is a write only ."]
+pub type PD_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for crate::generic::Reg<PLDMND_SPEC> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "(not readable)")
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Poll Demand. If the OWNER bit of a descriptor is not set, the FSM goes to the Suspend state. The host needs to write any value into this register for the IDMAC FSM to resume normal descriptor fetch operation. This is a write only ."]
+    #[inline(always)]
+    pub fn pd(&mut self) -> PD_W<PLDMND_SPEC> {
+        PD_W::new(self, 0)
+    }
+}
+#[doc = "Poll demand configuration register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pldmnd::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct PLDMND_SPEC;
+impl crate::RegisterSpec for PLDMND_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [`pldmnd::W`](W) writer structure"]
+impl crate::Writable for PLDMND_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets PLDMND to value 0"]
+impl crate::Resettable for PLDMND_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sdhost/resp0.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `RESP0` reader"]
+pub type R = crate::R<RESP0_SPEC>;
+#[doc = "Field `RESPONSE0` reader - Bit\\[31:0\\] of response."]
+pub type RESPONSE0_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - Bit\\[31:0\\] of response."]
+    #[inline(always)]
+    pub fn response0(&self) -> RESPONSE0_R {
+        RESPONSE0_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("RESP0")
+            .field("response0", &self.response0())
+            .finish()
+    }
+}
+#[doc = "Response data register\n\nYou can [`read`](crate::Reg::read) this register and get [`resp0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct RESP0_SPEC;
+impl crate::RegisterSpec for RESP0_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`resp0::R`](R) reader structure"]
+impl crate::Readable for RESP0_SPEC {}
+#[doc = "`reset()` method sets RESP0 to value 0"]
+impl crate::Resettable for RESP0_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sdhost/resp1.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `RESP1` reader"]
+pub type R = crate::R<RESP1_SPEC>;
+#[doc = "Field `RESPONSE1` reader - Bit\\[63:32\\] of long response."]
+pub type RESPONSE1_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - Bit\\[63:32\\] of long response."]
+    #[inline(always)]
+    pub fn response1(&self) -> RESPONSE1_R {
+        RESPONSE1_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("RESP1")
+            .field("response1", &self.response1())
+            .finish()
+    }
+}
+#[doc = "Long response data register\n\nYou can [`read`](crate::Reg::read) this register and get [`resp1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct RESP1_SPEC;
+impl crate::RegisterSpec for RESP1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`resp1::R`](R) reader structure"]
+impl crate::Readable for RESP1_SPEC {}
+#[doc = "`reset()` method sets RESP1 to value 0"]
+impl crate::Resettable for RESP1_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sdhost/resp2.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `RESP2` reader"]
+pub type R = crate::R<RESP2_SPEC>;
+#[doc = "Field `RESPONSE2` reader - Bit\\[95:64\\] of long response."]
+pub type RESPONSE2_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - Bit\\[95:64\\] of long response."]
+    #[inline(always)]
+    pub fn response2(&self) -> RESPONSE2_R {
+        RESPONSE2_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("RESP2")
+            .field("response2", &self.response2())
+            .finish()
+    }
+}
+#[doc = "Long response data register\n\nYou can [`read`](crate::Reg::read) this register and get [`resp2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct RESP2_SPEC;
+impl crate::RegisterSpec for RESP2_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`resp2::R`](R) reader structure"]
+impl crate::Readable for RESP2_SPEC {}
+#[doc = "`reset()` method sets RESP2 to value 0"]
+impl crate::Resettable for RESP2_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sdhost/resp3.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `RESP3` reader"]
+pub type R = crate::R<RESP3_SPEC>;
+#[doc = "Field `RESPONSE3` reader - Bit\\[127:96\\] of long response."]
+pub type RESPONSE3_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - Bit\\[127:96\\] of long response."]
+    #[inline(always)]
+    pub fn response3(&self) -> RESPONSE3_R {
+        RESPONSE3_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("RESP3")
+            .field("response3", &self.response3())
+            .finish()
+    }
+}
+#[doc = "Long response data register\n\nYou can [`read`](crate::Reg::read) this register and get [`resp3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct RESP3_SPEC;
+impl crate::RegisterSpec for RESP3_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`resp3::R`](R) reader structure"]
+impl crate::Readable for RESP3_SPEC {}
+#[doc = "`reset()` method sets RESP3 to value 0"]
+impl crate::Resettable for RESP3_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sdhost/rintsts.rs

@@ -0,0 +1,62 @@
+#[doc = "Register `RINTSTS` reader"]
+pub type R = crate::R<RINTSTS_SPEC>;
+#[doc = "Register `RINTSTS` writer"]
+pub type W = crate::W<RINTSTS_SPEC>;
+#[doc = "Field `INT_STATUS_RAW` reader - Setting a bit clears the corresponding interrupt and writing 0 has no effect. Bits are logged regardless of interrupt mask status. Bit 15 (EBE): End-bit error/no CRC error; Bit 14 (ACD): Auto command done; Bit 13 (SBE/BCI): RX Start Bit Error; Bit 12 (HLE): Hardware locked write error; Bit 11 (FRUN): FIFO underrun/overrun error; Bit 10 (HTO): Data starvation by host timeout (HTO); Bit 9 (DTRO): Data read timeout; Bit 8 (RTO): Response timeout; Bit 7 (DCRC): Data CRC error; Bit 6 (RCRC): Response CRC error; Bit 5 (RXDR): Receive FIFO data request; Bit 4 (TXDR): Transmit FIFO data request; Bit 3 (DTO): Data transfer over; Bit 2 (CD): Command done; Bit 1 (RE): Response error; Bit 0 (CD): Card detect."]
+pub type INT_STATUS_RAW_R = crate::FieldReader<u16>;
+#[doc = "Field `INT_STATUS_RAW` writer - Setting a bit clears the corresponding interrupt and writing 0 has no effect. Bits are logged regardless of interrupt mask status. Bit 15 (EBE): End-bit error/no CRC error; Bit 14 (ACD): Auto command done; Bit 13 (SBE/BCI): RX Start Bit Error; Bit 12 (HLE): Hardware locked write error; Bit 11 (FRUN): FIFO underrun/overrun error; Bit 10 (HTO): Data starvation by host timeout (HTO); Bit 9 (DTRO): Data read timeout; Bit 8 (RTO): Response timeout; Bit 7 (DCRC): Data CRC error; Bit 6 (RCRC): Response CRC error; Bit 5 (RXDR): Receive FIFO data request; Bit 4 (TXDR): Transmit FIFO data request; Bit 3 (DTO): Data transfer over; Bit 2 (CD): Command done; Bit 1 (RE): Response error; Bit 0 (CD): Card detect."]
+pub type INT_STATUS_RAW_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
+#[doc = "Field `SDIO_INTERRUPT_RAW` reader - Interrupt from SDIO card, one bit for each card. Bit\\[17:16\\] correspond to card1 and card0, respectively. Setting a bit clears the corresponding interrupt bit and writing 0 has no effect. 0: No SDIO interrupt from card; 1: SDIO interrupt from card."]
+pub type SDIO_INTERRUPT_RAW_R = crate::FieldReader;
+#[doc = "Field `SDIO_INTERRUPT_RAW` writer - Interrupt from SDIO card, one bit for each card. Bit\\[17:16\\] correspond to card1 and card0, respectively. Setting a bit clears the corresponding interrupt bit and writing 0 has no effect. 0: No SDIO interrupt from card; 1: SDIO interrupt from card."]
+pub type SDIO_INTERRUPT_RAW_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+impl R {
+    #[doc = "Bits 0:15 - Setting a bit clears the corresponding interrupt and writing 0 has no effect. Bits are logged regardless of interrupt mask status. Bit 15 (EBE): End-bit error/no CRC error; Bit 14 (ACD): Auto command done; Bit 13 (SBE/BCI): RX Start Bit Error; Bit 12 (HLE): Hardware locked write error; Bit 11 (FRUN): FIFO underrun/overrun error; Bit 10 (HTO): Data starvation by host timeout (HTO); Bit 9 (DTRO): Data read timeout; Bit 8 (RTO): Response timeout; Bit 7 (DCRC): Data CRC error; Bit 6 (RCRC): Response CRC error; Bit 5 (RXDR): Receive FIFO data request; Bit 4 (TXDR): Transmit FIFO data request; Bit 3 (DTO): Data transfer over; Bit 2 (CD): Command done; Bit 1 (RE): Response error; Bit 0 (CD): Card detect."]
+    #[inline(always)]
+    pub fn int_status_raw(&self) -> INT_STATUS_RAW_R {
+        INT_STATUS_RAW_R::new((self.bits & 0xffff) as u16)
+    }
+    #[doc = "Bits 16:17 - Interrupt from SDIO card, one bit for each card. Bit\\[17:16\\] correspond to card1 and card0, respectively. Setting a bit clears the corresponding interrupt bit and writing 0 has no effect. 0: No SDIO interrupt from card; 1: SDIO interrupt from card."]
+    #[inline(always)]
+    pub fn sdio_interrupt_raw(&self) -> SDIO_INTERRUPT_RAW_R {
+        SDIO_INTERRUPT_RAW_R::new(((self.bits >> 16) & 3) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("RINTSTS")
+            .field("int_status_raw", &self.int_status_raw())
+            .field("sdio_interrupt_raw", &self.sdio_interrupt_raw())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:15 - Setting a bit clears the corresponding interrupt and writing 0 has no effect. Bits are logged regardless of interrupt mask status. Bit 15 (EBE): End-bit error/no CRC error; Bit 14 (ACD): Auto command done; Bit 13 (SBE/BCI): RX Start Bit Error; Bit 12 (HLE): Hardware locked write error; Bit 11 (FRUN): FIFO underrun/overrun error; Bit 10 (HTO): Data starvation by host timeout (HTO); Bit 9 (DTRO): Data read timeout; Bit 8 (RTO): Response timeout; Bit 7 (DCRC): Data CRC error; Bit 6 (RCRC): Response CRC error; Bit 5 (RXDR): Receive FIFO data request; Bit 4 (TXDR): Transmit FIFO data request; Bit 3 (DTO): Data transfer over; Bit 2 (CD): Command done; Bit 1 (RE): Response error; Bit 0 (CD): Card detect."]
+    #[inline(always)]
+    pub fn int_status_raw(&mut self) -> INT_STATUS_RAW_W<RINTSTS_SPEC> {
+        INT_STATUS_RAW_W::new(self, 0)
+    }
+    #[doc = "Bits 16:17 - Interrupt from SDIO card, one bit for each card. Bit\\[17:16\\] correspond to card1 and card0, respectively. Setting a bit clears the corresponding interrupt bit and writing 0 has no effect. 0: No SDIO interrupt from card; 1: SDIO interrupt from card."]
+    #[inline(always)]
+    pub fn sdio_interrupt_raw(&mut self) -> SDIO_INTERRUPT_RAW_W<RINTSTS_SPEC> {
+        SDIO_INTERRUPT_RAW_W::new(self, 16)
+    }
+}
+#[doc = "Raw interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`rintsts::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rintsts::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct RINTSTS_SPEC;
+impl crate::RegisterSpec for RINTSTS_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`rintsts::R`](R) reader structure"]
+impl crate::Readable for RINTSTS_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`rintsts::W`](W) writer structure"]
+impl crate::Writable for RINTSTS_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets RINTSTS to value 0"]
+impl crate::Resettable for RINTSTS_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sdhost/rst_n.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `RST_N` reader"]
+pub type R = crate::R<RST_N_SPEC>;
+#[doc = "Register `RST_N` writer"]
+pub type W = crate::W<RST_N_SPEC>;
+#[doc = "Field `CARD_RESET` reader - Hardware reset. 1: Active mode; 0: Reset. These bits cause the cards to enter pre-idle state, which requires them to be re-initialized. SDHOST_RST_CARD_RESET\\[0\\] should be set to 1'b0 to reset card0, SDHOST_RST_CARD_RESET\\[1\\] should be set to 1'b0 to reset card1."]
+pub type CARD_RESET_R = crate::FieldReader;
+#[doc = "Field `CARD_RESET` writer - Hardware reset. 1: Active mode; 0: Reset. These bits cause the cards to enter pre-idle state, which requires them to be re-initialized. SDHOST_RST_CARD_RESET\\[0\\] should be set to 1'b0 to reset card0, SDHOST_RST_CARD_RESET\\[1\\] should be set to 1'b0 to reset card1."]
+pub type CARD_RESET_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+impl R {
+    #[doc = "Bits 0:1 - Hardware reset. 1: Active mode; 0: Reset. These bits cause the cards to enter pre-idle state, which requires them to be re-initialized. SDHOST_RST_CARD_RESET\\[0\\] should be set to 1'b0 to reset card0, SDHOST_RST_CARD_RESET\\[1\\] should be set to 1'b0 to reset card1."]
+    #[inline(always)]
+    pub fn card_reset(&self) -> CARD_RESET_R {
+        CARD_RESET_R::new((self.bits & 3) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("RST_N")
+            .field("card_reset", &self.card_reset())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:1 - Hardware reset. 1: Active mode; 0: Reset. These bits cause the cards to enter pre-idle state, which requires them to be re-initialized. SDHOST_RST_CARD_RESET\\[0\\] should be set to 1'b0 to reset card0, SDHOST_RST_CARD_RESET\\[1\\] should be set to 1'b0 to reset card1."]
+    #[inline(always)]
+    pub fn card_reset(&mut self) -> CARD_RESET_W<RST_N_SPEC> {
+        CARD_RESET_W::new(self, 0)
+    }
+}
+#[doc = "Card reset register\n\nYou can [`read`](crate::Reg::read) this register and get [`rst_n::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rst_n::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct RST_N_SPEC;
+impl crate::RegisterSpec for RST_N_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`rst_n::R`](R) reader structure"]
+impl crate::Readable for RST_N_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`rst_n::W`](W) writer structure"]
+impl crate::Writable for RST_N_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets RST_N to value 0x01"]
+impl crate::Resettable for RST_N_SPEC {
+    const RESET_VALUE: u32 = 0x01;
+}

vendor/esp32s3/src/sdhost/status.rs

@@ -0,0 +1,102 @@
+#[doc = "Register `STATUS` reader"]
+pub type R = crate::R<STATUS_SPEC>;
+#[doc = "Field `FIFO_RX_WATERMARK` reader - FIFO reached Receive watermark level, not qualified with data transfer."]
+pub type FIFO_RX_WATERMARK_R = crate::BitReader;
+#[doc = "Field `FIFO_TX_WATERMARK` reader - FIFO reached Transmit watermark level, not qualified with data transfer."]
+pub type FIFO_TX_WATERMARK_R = crate::BitReader;
+#[doc = "Field `FIFO_EMPTY` reader - FIFO is empty status."]
+pub type FIFO_EMPTY_R = crate::BitReader;
+#[doc = "Field `FIFO_FULL` reader - FIFO is full status."]
+pub type FIFO_FULL_R = crate::BitReader;
+#[doc = "Field `COMMAND_FSM_STATES` reader - Command FSM states. 0: Idle; 1: Send init sequence; 2: Send cmd start bit; 3: Send cmd tx bit; 4: Send cmd index + arg; 5: Send cmd crc7; 6: Send cmd end bit; 7: Receive resp start bit; 8: Receive resp IRQ response; 9: Receive resp tx bit; 10: Receive resp cmd idx; 11: Receive resp data; 12: Receive resp crc7; 13: Receive resp end bit; 14: Cmd path wait NCC; 15: Wait, cmd-to-response turnaround."]
+pub type COMMAND_FSM_STATES_R = crate::FieldReader;
+#[doc = "Field `DATA_3_STATUS` reader - Raw selected sdhost_card_data\\[3\\], checks whether card is present. 0: card not present; 1: card present."]
+pub type DATA_3_STATUS_R = crate::BitReader;
+#[doc = "Field `DATA_BUSY` reader - Inverted version of raw selected sdhost_card_data\\[0\\]. 0: Card data not busy; 1: Card data busy."]
+pub type DATA_BUSY_R = crate::BitReader;
+#[doc = "Field `DATA_STATE_MC_BUSY` reader - Data transmit or receive state-machine is busy."]
+pub type DATA_STATE_MC_BUSY_R = crate::BitReader;
+#[doc = "Field `RESPONSE_INDEX` reader - Index of previous response, including any auto-stop sent by core."]
+pub type RESPONSE_INDEX_R = crate::FieldReader;
+#[doc = "Field `FIFO_COUNT` reader - FIFO count, number of filled locations in FIFO."]
+pub type FIFO_COUNT_R = crate::FieldReader<u16>;
+impl R {
+    #[doc = "Bit 0 - FIFO reached Receive watermark level, not qualified with data transfer."]
+    #[inline(always)]
+    pub fn fifo_rx_watermark(&self) -> FIFO_RX_WATERMARK_R {
+        FIFO_RX_WATERMARK_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - FIFO reached Transmit watermark level, not qualified with data transfer."]
+    #[inline(always)]
+    pub fn fifo_tx_watermark(&self) -> FIFO_TX_WATERMARK_R {
+        FIFO_TX_WATERMARK_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - FIFO is empty status."]
+    #[inline(always)]
+    pub fn fifo_empty(&self) -> FIFO_EMPTY_R {
+        FIFO_EMPTY_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - FIFO is full status."]
+    #[inline(always)]
+    pub fn fifo_full(&self) -> FIFO_FULL_R {
+        FIFO_FULL_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bits 4:7 - Command FSM states. 0: Idle; 1: Send init sequence; 2: Send cmd start bit; 3: Send cmd tx bit; 4: Send cmd index + arg; 5: Send cmd crc7; 6: Send cmd end bit; 7: Receive resp start bit; 8: Receive resp IRQ response; 9: Receive resp tx bit; 10: Receive resp cmd idx; 11: Receive resp data; 12: Receive resp crc7; 13: Receive resp end bit; 14: Cmd path wait NCC; 15: Wait, cmd-to-response turnaround."]
+    #[inline(always)]
+    pub fn command_fsm_states(&self) -> COMMAND_FSM_STATES_R {
+        COMMAND_FSM_STATES_R::new(((self.bits >> 4) & 0x0f) as u8)
+    }
+    #[doc = "Bit 8 - Raw selected sdhost_card_data\\[3\\], checks whether card is present. 0: card not present; 1: card present."]
+    #[inline(always)]
+    pub fn data_3_status(&self) -> DATA_3_STATUS_R {
+        DATA_3_STATUS_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - Inverted version of raw selected sdhost_card_data\\[0\\]. 0: Card data not busy; 1: Card data busy."]
+    #[inline(always)]
+    pub fn data_busy(&self) -> DATA_BUSY_R {
+        DATA_BUSY_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 10 - Data transmit or receive state-machine is busy."]
+    #[inline(always)]
+    pub fn data_state_mc_busy(&self) -> DATA_STATE_MC_BUSY_R {
+        DATA_STATE_MC_BUSY_R::new(((self.bits >> 10) & 1) != 0)
+    }
+    #[doc = "Bits 11:16 - Index of previous response, including any auto-stop sent by core."]
+    #[inline(always)]
+    pub fn response_index(&self) -> RESPONSE_INDEX_R {
+        RESPONSE_INDEX_R::new(((self.bits >> 11) & 0x3f) as u8)
+    }
+    #[doc = "Bits 17:29 - FIFO count, number of filled locations in FIFO."]
+    #[inline(always)]
+    pub fn fifo_count(&self) -> FIFO_COUNT_R {
+        FIFO_COUNT_R::new(((self.bits >> 17) & 0x1fff) as u16)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("STATUS")
+            .field("fifo_rx_watermark", &self.fifo_rx_watermark())
+            .field("fifo_tx_watermark", &self.fifo_tx_watermark())
+            .field("fifo_empty", &self.fifo_empty())
+            .field("fifo_full", &self.fifo_full())
+            .field("command_fsm_states", &self.command_fsm_states())
+            .field("data_3_status", &self.data_3_status())
+            .field("data_busy", &self.data_busy())
+            .field("data_state_mc_busy", &self.data_state_mc_busy())
+            .field("response_index", &self.response_index())
+            .field("fifo_count", &self.fifo_count())
+            .finish()
+    }
+}
+#[doc = "SD/MMC status register\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct STATUS_SPEC;
+impl crate::RegisterSpec for STATUS_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`status::R`](R) reader structure"]
+impl crate::Readable for STATUS_SPEC {}
+#[doc = "`reset()` method sets STATUS to value 0x0716"]
+impl crate::Resettable for STATUS_SPEC {
+    const RESET_VALUE: u32 = 0x0716;
+}

vendor/esp32s3/src/sdhost/tbbcnt.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `TBBCNT` reader"]
+pub type R = crate::R<TBBCNT_SPEC>;
+#[doc = "Field `TBBCNT` reader - Number of bytes transferred between Host/DMA memory and BIU FIFO."]
+pub type TBBCNT_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - Number of bytes transferred between Host/DMA memory and BIU FIFO."]
+    #[inline(always)]
+    pub fn tbbcnt(&self) -> TBBCNT_R {
+        TBBCNT_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("TBBCNT")
+            .field("tbbcnt", &self.tbbcnt())
+            .finish()
+    }
+}
+#[doc = "Transferred byte count register\n\nYou can [`read`](crate::Reg::read) this register and get [`tbbcnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct TBBCNT_SPEC;
+impl crate::RegisterSpec for TBBCNT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`tbbcnt::R`](R) reader structure"]
+impl crate::Readable for TBBCNT_SPEC {}
+#[doc = "`reset()` method sets TBBCNT to value 0"]
+impl crate::Resettable for TBBCNT_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sdhost/tcbcnt.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `TCBCNT` reader"]
+pub type R = crate::R<TCBCNT_SPEC>;
+#[doc = "Field `TCBCNT` reader - Number of bytes transferred by CIU unit to card."]
+pub type TCBCNT_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - Number of bytes transferred by CIU unit to card."]
+    #[inline(always)]
+    pub fn tcbcnt(&self) -> TCBCNT_R {
+        TCBCNT_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("TCBCNT")
+            .field("tcbcnt", &self.tcbcnt())
+            .finish()
+    }
+}
+#[doc = "Transferred byte count register\n\nYou can [`read`](crate::Reg::read) this register and get [`tcbcnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct TCBCNT_SPEC;
+impl crate::RegisterSpec for TCBCNT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`tcbcnt::R`](R) reader structure"]
+impl crate::Readable for TCBCNT_SPEC {}
+#[doc = "`reset()` method sets TCBCNT to value 0"]
+impl crate::Resettable for TCBCNT_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sdhost/tmout.rs

@@ -0,0 +1,62 @@
+#[doc = "Register `TMOUT` reader"]
+pub type R = crate::R<TMOUT_SPEC>;
+#[doc = "Register `TMOUT` writer"]
+pub type W = crate::W<TMOUT_SPEC>;
+#[doc = "Field `RESPONSE_TIMEOUT` reader - Response timeout value. Value is specified in terms of number of card output clocks, i.e., sdhost_cclk_out."]
+pub type RESPONSE_TIMEOUT_R = crate::FieldReader;
+#[doc = "Field `RESPONSE_TIMEOUT` writer - Response timeout value. Value is specified in terms of number of card output clocks, i.e., sdhost_cclk_out."]
+pub type RESPONSE_TIMEOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+#[doc = "Field `DATA_TIMEOUT` reader - Value for card data read timeout. This value is also used for data starvation by host timeout. The timeout counter is started only after the card clock is stopped. This value is specified in number of card output clocks, i.e. sdhost_cclk_out of the selected card. NOTE: The software timer should be used if the timeout value is in the order of 100 ms. In this case, read data timeout interrupt needs to be disabled."]
+pub type DATA_TIMEOUT_R = crate::FieldReader<u32>;
+#[doc = "Field `DATA_TIMEOUT` writer - Value for card data read timeout. This value is also used for data starvation by host timeout. The timeout counter is started only after the card clock is stopped. This value is specified in number of card output clocks, i.e. sdhost_cclk_out of the selected card. NOTE: The software timer should be used if the timeout value is in the order of 100 ms. In this case, read data timeout interrupt needs to be disabled."]
+pub type DATA_TIMEOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
+impl R {
+    #[doc = "Bits 0:7 - Response timeout value. Value is specified in terms of number of card output clocks, i.e., sdhost_cclk_out."]
+    #[inline(always)]
+    pub fn response_timeout(&self) -> RESPONSE_TIMEOUT_R {
+        RESPONSE_TIMEOUT_R::new((self.bits & 0xff) as u8)
+    }
+    #[doc = "Bits 8:31 - Value for card data read timeout. This value is also used for data starvation by host timeout. The timeout counter is started only after the card clock is stopped. This value is specified in number of card output clocks, i.e. sdhost_cclk_out of the selected card. NOTE: The software timer should be used if the timeout value is in the order of 100 ms. In this case, read data timeout interrupt needs to be disabled."]
+    #[inline(always)]
+    pub fn data_timeout(&self) -> DATA_TIMEOUT_R {
+        DATA_TIMEOUT_R::new((self.bits >> 8) & 0x00ff_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("TMOUT")
+            .field("response_timeout", &self.response_timeout())
+            .field("data_timeout", &self.data_timeout())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - Response timeout value. Value is specified in terms of number of card output clocks, i.e., sdhost_cclk_out."]
+    #[inline(always)]
+    pub fn response_timeout(&mut self) -> RESPONSE_TIMEOUT_W<TMOUT_SPEC> {
+        RESPONSE_TIMEOUT_W::new(self, 0)
+    }
+    #[doc = "Bits 8:31 - Value for card data read timeout. This value is also used for data starvation by host timeout. The timeout counter is started only after the card clock is stopped. This value is specified in number of card output clocks, i.e. sdhost_cclk_out of the selected card. NOTE: The software timer should be used if the timeout value is in the order of 100 ms. In this case, read data timeout interrupt needs to be disabled."]
+    #[inline(always)]
+    pub fn data_timeout(&mut self) -> DATA_TIMEOUT_W<TMOUT_SPEC> {
+        DATA_TIMEOUT_W::new(self, 8)
+    }
+}
+#[doc = "Data and response timeout configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`tmout::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tmout::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct TMOUT_SPEC;
+impl crate::RegisterSpec for TMOUT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`tmout::R`](R) reader structure"]
+impl crate::Readable for TMOUT_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`tmout::W`](W) writer structure"]
+impl crate::Writable for TMOUT_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets TMOUT to value 0xffff_ff40"]
+impl crate::Resettable for TMOUT_SPEC {
+    const RESET_VALUE: u32 = 0xffff_ff40;
+}

vendor/esp32s3/src/sdhost/uhs.rs

@@ -0,0 +1,45 @@
+#[doc = "Register `UHS` reader"]
+pub type R = crate::R<UHS_SPEC>;
+#[doc = "Register `UHS` writer"]
+pub type W = crate::W<UHS_SPEC>;
+#[doc = "Field `DDR` reader - DDR mode selecton,1 bit for each card. 0-Non-DDR mdoe. 1-DDR mdoe."]
+pub type DDR_R = crate::FieldReader;
+#[doc = "Field `DDR` writer - DDR mode selecton,1 bit for each card. 0-Non-DDR mdoe. 1-DDR mdoe."]
+pub type DDR_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+impl R {
+    #[doc = "Bits 16:17 - DDR mode selecton,1 bit for each card. 0-Non-DDR mdoe. 1-DDR mdoe."]
+    #[inline(always)]
+    pub fn ddr(&self) -> DDR_R {
+        DDR_R::new(((self.bits >> 16) & 3) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("UHS").field("ddr", &self.ddr()).finish()
+    }
+}
+impl W {
+    #[doc = "Bits 16:17 - DDR mode selecton,1 bit for each card. 0-Non-DDR mdoe. 1-DDR mdoe."]
+    #[inline(always)]
+    pub fn ddr(&mut self) -> DDR_W<UHS_SPEC> {
+        DDR_W::new(self, 16)
+    }
+}
+#[doc = "UHS-1 register\n\nYou can [`read`](crate::Reg::read) this register and get [`uhs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uhs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct UHS_SPEC;
+impl crate::RegisterSpec for UHS_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`uhs::R`](R) reader structure"]
+impl crate::Readable for UHS_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`uhs::W`](W) writer structure"]
+impl crate::Writable for UHS_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets UHS to value 0"]
+impl crate::Resettable for UHS_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sdhost/usrid.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `USRID` reader"]
+pub type R = crate::R<USRID_SPEC>;
+#[doc = "Register `USRID` writer"]
+pub type W = crate::W<USRID_SPEC>;
+#[doc = "Field `USRID` reader - User identification register, value set by user. Can also be used as a scratchpad register by user."]
+pub type USRID_R = crate::FieldReader<u32>;
+#[doc = "Field `USRID` writer - User identification register, value set by user. Can also be used as a scratchpad register by user."]
+pub type USRID_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - User identification register, value set by user. Can also be used as a scratchpad register by user."]
+    #[inline(always)]
+    pub fn usrid(&self) -> USRID_R {
+        USRID_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("USRID")
+            .field("usrid", &self.usrid())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - User identification register, value set by user. Can also be used as a scratchpad register by user."]
+    #[inline(always)]
+    pub fn usrid(&mut self) -> USRID_W<USRID_SPEC> {
+        USRID_W::new(self, 0)
+    }
+}
+#[doc = "User ID (scratchpad) register\n\nYou can [`read`](crate::Reg::read) this register and get [`usrid::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usrid::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct USRID_SPEC;
+impl crate::RegisterSpec for USRID_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`usrid::R`](R) reader structure"]
+impl crate::Readable for USRID_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`usrid::W`](W) writer structure"]
+impl crate::Writable for USRID_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets USRID to value 0"]
+impl crate::Resettable for USRID_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sdhost/verid.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `VERID` reader"]
+pub type R = crate::R<VERID_SPEC>;
+#[doc = "Field `VERSIONID` reader - Hardware version register. Can also be read by fireware."]
+pub type VERSIONID_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - Hardware version register. Can also be read by fireware."]
+    #[inline(always)]
+    pub fn versionid(&self) -> VERSIONID_R {
+        VERSIONID_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("VERID")
+            .field("versionid", &self.versionid())
+            .finish()
+    }
+}
+#[doc = "Version ID (scratchpad) register\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct VERID_SPEC;
+impl crate::RegisterSpec for VERID_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`verid::R`](R) reader structure"]
+impl crate::Readable for VERID_SPEC {}
+#[doc = "`reset()` method sets VERID to value 0x5432_270a"]
+impl crate::Resettable for VERID_SPEC {
+    const RESET_VALUE: u32 = 0x5432_270a;
+}

vendor/esp32s3/src/sdhost/wrtprt.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `WRTPRT` reader"]
+pub type R = crate::R<WRTPRT_SPEC>;
+#[doc = "Field `WRITE_PROTECT` reader - Value on sdhost_card_write_prt input ports (1 bit per card). 1 represents write protection. Only NUM_CARDS number of bits are implemented."]
+pub type WRITE_PROTECT_R = crate::FieldReader;
+impl R {
+    #[doc = "Bits 0:1 - Value on sdhost_card_write_prt input ports (1 bit per card). 1 represents write protection. Only NUM_CARDS number of bits are implemented."]
+    #[inline(always)]
+    pub fn write_protect(&self) -> WRITE_PROTECT_R {
+        WRITE_PROTECT_R::new((self.bits & 3) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("WRTPRT")
+            .field("write_protect", &self.write_protect())
+            .finish()
+    }
+}
+#[doc = "Card write protection (WP) status register\n\nYou can [`read`](crate::Reg::read) this register and get [`wrtprt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct WRTPRT_SPEC;
+impl crate::RegisterSpec for WRTPRT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`wrtprt::R`](R) reader structure"]
+impl crate::Readable for WRTPRT_SPEC {}
+#[doc = "`reset()` method sets WRTPRT to value 0"]
+impl crate::Resettable for WRTPRT_SPEC {
+    const RESET_VALUE: u32 = 0;
+}