feat: add display UI with splash screen, dashboard, and RSSI sparkline

Implement full SSD1306 OLED display support:
- Splash screen on boot (1.5s) with project name, version, board
- Dashboard showing radio state, config, counters, RSSI/SNR
- RSSI history sparkline (64-sample ring buffer, 2px-wide bars)
- DisplayOn/DisplayOff host commands routed via dedicated channel
- Pure render functions against generic DrawTarget (no hardware coupling)
- Display on/off control bypasses radio task entirely

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>

vendor/esp32s3/src/sens/sar_amp_ctrl1.rs

@@ -0,0 +1,62 @@
+#[doc = "Register `SAR_AMP_CTRL1` reader"]
+pub type R = crate::R<SAR_AMP_CTRL1_SPEC>;
+#[doc = "Register `SAR_AMP_CTRL1` writer"]
+pub type W = crate::W<SAR_AMP_CTRL1_SPEC>;
+#[doc = "Field `SAR_AMP_WAIT1` reader - no public"]
+pub type SAR_AMP_WAIT1_R = crate::FieldReader<u16>;
+#[doc = "Field `SAR_AMP_WAIT1` writer - no public"]
+pub type SAR_AMP_WAIT1_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
+#[doc = "Field `SAR_AMP_WAIT2` reader - no public"]
+pub type SAR_AMP_WAIT2_R = crate::FieldReader<u16>;
+#[doc = "Field `SAR_AMP_WAIT2` writer - no public"]
+pub type SAR_AMP_WAIT2_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
+impl R {
+    #[doc = "Bits 0:15 - no public"]
+    #[inline(always)]
+    pub fn sar_amp_wait1(&self) -> SAR_AMP_WAIT1_R {
+        SAR_AMP_WAIT1_R::new((self.bits & 0xffff) as u16)
+    }
+    #[doc = "Bits 16:31 - no public"]
+    #[inline(always)]
+    pub fn sar_amp_wait2(&self) -> SAR_AMP_WAIT2_R {
+        SAR_AMP_WAIT2_R::new(((self.bits >> 16) & 0xffff) as u16)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_AMP_CTRL1")
+            .field("sar_amp_wait1", &self.sar_amp_wait1())
+            .field("sar_amp_wait2", &self.sar_amp_wait2())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:15 - no public"]
+    #[inline(always)]
+    pub fn sar_amp_wait1(&mut self) -> SAR_AMP_WAIT1_W<SAR_AMP_CTRL1_SPEC> {
+        SAR_AMP_WAIT1_W::new(self, 0)
+    }
+    #[doc = "Bits 16:31 - no public"]
+    #[inline(always)]
+    pub fn sar_amp_wait2(&mut self) -> SAR_AMP_WAIT2_W<SAR_AMP_CTRL1_SPEC> {
+        SAR_AMP_WAIT2_W::new(self, 16)
+    }
+}
+#[doc = "no public\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_amp_ctrl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_amp_ctrl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_AMP_CTRL1_SPEC;
+impl crate::RegisterSpec for SAR_AMP_CTRL1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_amp_ctrl1::R`](R) reader structure"]
+impl crate::Readable for SAR_AMP_CTRL1_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sar_amp_ctrl1::W`](W) writer structure"]
+impl crate::Writable for SAR_AMP_CTRL1_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SAR_AMP_CTRL1 to value 0x000a_000a"]
+impl crate::Resettable for SAR_AMP_CTRL1_SPEC {
+    const RESET_VALUE: u32 = 0x000a_000a;
+}

vendor/esp32s3/src/sens/sar_amp_ctrl2.rs

@@ -0,0 +1,165 @@
+#[doc = "Register `SAR_AMP_CTRL2` reader"]
+pub type R = crate::R<SAR_AMP_CTRL2_SPEC>;
+#[doc = "Register `SAR_AMP_CTRL2` writer"]
+pub type W = crate::W<SAR_AMP_CTRL2_SPEC>;
+#[doc = "Field `SAR_SAR1_DAC_XPD_FSM_IDLE` reader - no public"]
+pub type SAR_SAR1_DAC_XPD_FSM_IDLE_R = crate::BitReader;
+#[doc = "Field `SAR_SAR1_DAC_XPD_FSM_IDLE` writer - no public"]
+pub type SAR_SAR1_DAC_XPD_FSM_IDLE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_XPD_SAR_AMP_FSM_IDLE` reader - no public"]
+pub type SAR_XPD_SAR_AMP_FSM_IDLE_R = crate::BitReader;
+#[doc = "Field `SAR_XPD_SAR_AMP_FSM_IDLE` writer - no public"]
+pub type SAR_XPD_SAR_AMP_FSM_IDLE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_AMP_RST_FB_FSM_IDLE` reader - no public"]
+pub type SAR_AMP_RST_FB_FSM_IDLE_R = crate::BitReader;
+#[doc = "Field `SAR_AMP_RST_FB_FSM_IDLE` writer - no public"]
+pub type SAR_AMP_RST_FB_FSM_IDLE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_AMP_SHORT_REF_FSM_IDLE` reader - no public"]
+pub type SAR_AMP_SHORT_REF_FSM_IDLE_R = crate::BitReader;
+#[doc = "Field `SAR_AMP_SHORT_REF_FSM_IDLE` writer - no public"]
+pub type SAR_AMP_SHORT_REF_FSM_IDLE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_AMP_SHORT_REF_GND_FSM_IDLE` reader - no public"]
+pub type SAR_AMP_SHORT_REF_GND_FSM_IDLE_R = crate::BitReader;
+#[doc = "Field `SAR_AMP_SHORT_REF_GND_FSM_IDLE` writer - no public"]
+pub type SAR_AMP_SHORT_REF_GND_FSM_IDLE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_XPD_SAR_FSM_IDLE` reader - no public"]
+pub type SAR_XPD_SAR_FSM_IDLE_R = crate::BitReader;
+#[doc = "Field `SAR_XPD_SAR_FSM_IDLE` writer - no public"]
+pub type SAR_XPD_SAR_FSM_IDLE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_RSTB_FSM_IDLE` reader - no public"]
+pub type SAR_RSTB_FSM_IDLE_R = crate::BitReader;
+#[doc = "Field `SAR_RSTB_FSM_IDLE` writer - no public"]
+pub type SAR_RSTB_FSM_IDLE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_AMP_WAIT3` reader - no public"]
+pub type SAR_AMP_WAIT3_R = crate::FieldReader<u16>;
+#[doc = "Field `SAR_AMP_WAIT3` writer - no public"]
+pub type SAR_AMP_WAIT3_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
+impl R {
+    #[doc = "Bit 0 - no public"]
+    #[inline(always)]
+    pub fn sar_sar1_dac_xpd_fsm_idle(&self) -> SAR_SAR1_DAC_XPD_FSM_IDLE_R {
+        SAR_SAR1_DAC_XPD_FSM_IDLE_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - no public"]
+    #[inline(always)]
+    pub fn sar_xpd_sar_amp_fsm_idle(&self) -> SAR_XPD_SAR_AMP_FSM_IDLE_R {
+        SAR_XPD_SAR_AMP_FSM_IDLE_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - no public"]
+    #[inline(always)]
+    pub fn sar_amp_rst_fb_fsm_idle(&self) -> SAR_AMP_RST_FB_FSM_IDLE_R {
+        SAR_AMP_RST_FB_FSM_IDLE_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - no public"]
+    #[inline(always)]
+    pub fn sar_amp_short_ref_fsm_idle(&self) -> SAR_AMP_SHORT_REF_FSM_IDLE_R {
+        SAR_AMP_SHORT_REF_FSM_IDLE_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - no public"]
+    #[inline(always)]
+    pub fn sar_amp_short_ref_gnd_fsm_idle(&self) -> SAR_AMP_SHORT_REF_GND_FSM_IDLE_R {
+        SAR_AMP_SHORT_REF_GND_FSM_IDLE_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - no public"]
+    #[inline(always)]
+    pub fn sar_xpd_sar_fsm_idle(&self) -> SAR_XPD_SAR_FSM_IDLE_R {
+        SAR_XPD_SAR_FSM_IDLE_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - no public"]
+    #[inline(always)]
+    pub fn sar_rstb_fsm_idle(&self) -> SAR_RSTB_FSM_IDLE_R {
+        SAR_RSTB_FSM_IDLE_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bits 16:31 - no public"]
+    #[inline(always)]
+    pub fn sar_amp_wait3(&self) -> SAR_AMP_WAIT3_R {
+        SAR_AMP_WAIT3_R::new(((self.bits >> 16) & 0xffff) as u16)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_AMP_CTRL2")
+            .field(
+                "sar_sar1_dac_xpd_fsm_idle",
+                &self.sar_sar1_dac_xpd_fsm_idle(),
+            )
+            .field("sar_xpd_sar_amp_fsm_idle", &self.sar_xpd_sar_amp_fsm_idle())
+            .field("sar_amp_rst_fb_fsm_idle", &self.sar_amp_rst_fb_fsm_idle())
+            .field(
+                "sar_amp_short_ref_fsm_idle",
+                &self.sar_amp_short_ref_fsm_idle(),
+            )
+            .field(
+                "sar_amp_short_ref_gnd_fsm_idle",
+                &self.sar_amp_short_ref_gnd_fsm_idle(),
+            )
+            .field("sar_xpd_sar_fsm_idle", &self.sar_xpd_sar_fsm_idle())
+            .field("sar_rstb_fsm_idle", &self.sar_rstb_fsm_idle())
+            .field("sar_amp_wait3", &self.sar_amp_wait3())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - no public"]
+    #[inline(always)]
+    pub fn sar_sar1_dac_xpd_fsm_idle(&mut self) -> SAR_SAR1_DAC_XPD_FSM_IDLE_W<SAR_AMP_CTRL2_SPEC> {
+        SAR_SAR1_DAC_XPD_FSM_IDLE_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - no public"]
+    #[inline(always)]
+    pub fn sar_xpd_sar_amp_fsm_idle(&mut self) -> SAR_XPD_SAR_AMP_FSM_IDLE_W<SAR_AMP_CTRL2_SPEC> {
+        SAR_XPD_SAR_AMP_FSM_IDLE_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - no public"]
+    #[inline(always)]
+    pub fn sar_amp_rst_fb_fsm_idle(&mut self) -> SAR_AMP_RST_FB_FSM_IDLE_W<SAR_AMP_CTRL2_SPEC> {
+        SAR_AMP_RST_FB_FSM_IDLE_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - no public"]
+    #[inline(always)]
+    pub fn sar_amp_short_ref_fsm_idle(
+        &mut self,
+    ) -> SAR_AMP_SHORT_REF_FSM_IDLE_W<SAR_AMP_CTRL2_SPEC> {
+        SAR_AMP_SHORT_REF_FSM_IDLE_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - no public"]
+    #[inline(always)]
+    pub fn sar_amp_short_ref_gnd_fsm_idle(
+        &mut self,
+    ) -> SAR_AMP_SHORT_REF_GND_FSM_IDLE_W<SAR_AMP_CTRL2_SPEC> {
+        SAR_AMP_SHORT_REF_GND_FSM_IDLE_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - no public"]
+    #[inline(always)]
+    pub fn sar_xpd_sar_fsm_idle(&mut self) -> SAR_XPD_SAR_FSM_IDLE_W<SAR_AMP_CTRL2_SPEC> {
+        SAR_XPD_SAR_FSM_IDLE_W::new(self, 5)
+    }
+    #[doc = "Bit 6 - no public"]
+    #[inline(always)]
+    pub fn sar_rstb_fsm_idle(&mut self) -> SAR_RSTB_FSM_IDLE_W<SAR_AMP_CTRL2_SPEC> {
+        SAR_RSTB_FSM_IDLE_W::new(self, 6)
+    }
+    #[doc = "Bits 16:31 - no public"]
+    #[inline(always)]
+    pub fn sar_amp_wait3(&mut self) -> SAR_AMP_WAIT3_W<SAR_AMP_CTRL2_SPEC> {
+        SAR_AMP_WAIT3_W::new(self, 16)
+    }
+}
+#[doc = "no public\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_amp_ctrl2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_amp_ctrl2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_AMP_CTRL2_SPEC;
+impl crate::RegisterSpec for SAR_AMP_CTRL2_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_amp_ctrl2::R`](R) reader structure"]
+impl crate::Readable for SAR_AMP_CTRL2_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sar_amp_ctrl2::W`](W) writer structure"]
+impl crate::Writable for SAR_AMP_CTRL2_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SAR_AMP_CTRL2 to value 0x000a_0000"]
+impl crate::Resettable for SAR_AMP_CTRL2_SPEC {
+    const RESET_VALUE: u32 = 0x000a_0000;
+}

vendor/esp32s3/src/sens/sar_amp_ctrl3.rs

@@ -0,0 +1,137 @@
+#[doc = "Register `SAR_AMP_CTRL3` reader"]
+pub type R = crate::R<SAR_AMP_CTRL3_SPEC>;
+#[doc = "Register `SAR_AMP_CTRL3` writer"]
+pub type W = crate::W<SAR_AMP_CTRL3_SPEC>;
+#[doc = "Field `SAR1_DAC_XPD_FSM` reader - no public"]
+pub type SAR1_DAC_XPD_FSM_R = crate::FieldReader;
+#[doc = "Field `SAR1_DAC_XPD_FSM` writer - no public"]
+pub type SAR1_DAC_XPD_FSM_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `XPD_SAR_AMP_FSM` reader - no public"]
+pub type XPD_SAR_AMP_FSM_R = crate::FieldReader;
+#[doc = "Field `XPD_SAR_AMP_FSM` writer - no public"]
+pub type XPD_SAR_AMP_FSM_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `AMP_RST_FB_FSM` reader - no public"]
+pub type AMP_RST_FB_FSM_R = crate::FieldReader;
+#[doc = "Field `AMP_RST_FB_FSM` writer - no public"]
+pub type AMP_RST_FB_FSM_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `AMP_SHORT_REF_FSM` reader - no public"]
+pub type AMP_SHORT_REF_FSM_R = crate::FieldReader;
+#[doc = "Field `AMP_SHORT_REF_FSM` writer - no public"]
+pub type AMP_SHORT_REF_FSM_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `AMP_SHORT_REF_GND_FSM` reader - no public"]
+pub type AMP_SHORT_REF_GND_FSM_R = crate::FieldReader;
+#[doc = "Field `AMP_SHORT_REF_GND_FSM` writer - no public"]
+pub type AMP_SHORT_REF_GND_FSM_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `XPD_SAR_FSM` reader - no public"]
+pub type XPD_SAR_FSM_R = crate::FieldReader;
+#[doc = "Field `XPD_SAR_FSM` writer - no public"]
+pub type XPD_SAR_FSM_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `RSTB_FSM` reader - no public"]
+pub type RSTB_FSM_R = crate::FieldReader;
+#[doc = "Field `RSTB_FSM` writer - no public"]
+pub type RSTB_FSM_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+impl R {
+    #[doc = "Bits 0:3 - no public"]
+    #[inline(always)]
+    pub fn sar1_dac_xpd_fsm(&self) -> SAR1_DAC_XPD_FSM_R {
+        SAR1_DAC_XPD_FSM_R::new((self.bits & 0x0f) as u8)
+    }
+    #[doc = "Bits 4:7 - no public"]
+    #[inline(always)]
+    pub fn xpd_sar_amp_fsm(&self) -> XPD_SAR_AMP_FSM_R {
+        XPD_SAR_AMP_FSM_R::new(((self.bits >> 4) & 0x0f) as u8)
+    }
+    #[doc = "Bits 8:11 - no public"]
+    #[inline(always)]
+    pub fn amp_rst_fb_fsm(&self) -> AMP_RST_FB_FSM_R {
+        AMP_RST_FB_FSM_R::new(((self.bits >> 8) & 0x0f) as u8)
+    }
+    #[doc = "Bits 12:15 - no public"]
+    #[inline(always)]
+    pub fn amp_short_ref_fsm(&self) -> AMP_SHORT_REF_FSM_R {
+        AMP_SHORT_REF_FSM_R::new(((self.bits >> 12) & 0x0f) as u8)
+    }
+    #[doc = "Bits 16:19 - no public"]
+    #[inline(always)]
+    pub fn amp_short_ref_gnd_fsm(&self) -> AMP_SHORT_REF_GND_FSM_R {
+        AMP_SHORT_REF_GND_FSM_R::new(((self.bits >> 16) & 0x0f) as u8)
+    }
+    #[doc = "Bits 20:23 - no public"]
+    #[inline(always)]
+    pub fn xpd_sar_fsm(&self) -> XPD_SAR_FSM_R {
+        XPD_SAR_FSM_R::new(((self.bits >> 20) & 0x0f) as u8)
+    }
+    #[doc = "Bits 24:27 - no public"]
+    #[inline(always)]
+    pub fn rstb_fsm(&self) -> RSTB_FSM_R {
+        RSTB_FSM_R::new(((self.bits >> 24) & 0x0f) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_AMP_CTRL3")
+            .field("sar1_dac_xpd_fsm", &self.sar1_dac_xpd_fsm())
+            .field("xpd_sar_amp_fsm", &self.xpd_sar_amp_fsm())
+            .field("amp_rst_fb_fsm", &self.amp_rst_fb_fsm())
+            .field("amp_short_ref_fsm", &self.amp_short_ref_fsm())
+            .field("amp_short_ref_gnd_fsm", &self.amp_short_ref_gnd_fsm())
+            .field("xpd_sar_fsm", &self.xpd_sar_fsm())
+            .field("rstb_fsm", &self.rstb_fsm())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:3 - no public"]
+    #[inline(always)]
+    pub fn sar1_dac_xpd_fsm(&mut self) -> SAR1_DAC_XPD_FSM_W<SAR_AMP_CTRL3_SPEC> {
+        SAR1_DAC_XPD_FSM_W::new(self, 0)
+    }
+    #[doc = "Bits 4:7 - no public"]
+    #[inline(always)]
+    pub fn xpd_sar_amp_fsm(&mut self) -> XPD_SAR_AMP_FSM_W<SAR_AMP_CTRL3_SPEC> {
+        XPD_SAR_AMP_FSM_W::new(self, 4)
+    }
+    #[doc = "Bits 8:11 - no public"]
+    #[inline(always)]
+    pub fn amp_rst_fb_fsm(&mut self) -> AMP_RST_FB_FSM_W<SAR_AMP_CTRL3_SPEC> {
+        AMP_RST_FB_FSM_W::new(self, 8)
+    }
+    #[doc = "Bits 12:15 - no public"]
+    #[inline(always)]
+    pub fn amp_short_ref_fsm(&mut self) -> AMP_SHORT_REF_FSM_W<SAR_AMP_CTRL3_SPEC> {
+        AMP_SHORT_REF_FSM_W::new(self, 12)
+    }
+    #[doc = "Bits 16:19 - no public"]
+    #[inline(always)]
+    pub fn amp_short_ref_gnd_fsm(&mut self) -> AMP_SHORT_REF_GND_FSM_W<SAR_AMP_CTRL3_SPEC> {
+        AMP_SHORT_REF_GND_FSM_W::new(self, 16)
+    }
+    #[doc = "Bits 20:23 - no public"]
+    #[inline(always)]
+    pub fn xpd_sar_fsm(&mut self) -> XPD_SAR_FSM_W<SAR_AMP_CTRL3_SPEC> {
+        XPD_SAR_FSM_W::new(self, 20)
+    }
+    #[doc = "Bits 24:27 - no public"]
+    #[inline(always)]
+    pub fn rstb_fsm(&mut self) -> RSTB_FSM_W<SAR_AMP_CTRL3_SPEC> {
+        RSTB_FSM_W::new(self, 24)
+    }
+}
+#[doc = "no public\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_amp_ctrl3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_amp_ctrl3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_AMP_CTRL3_SPEC;
+impl crate::RegisterSpec for SAR_AMP_CTRL3_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_amp_ctrl3::R`](R) reader structure"]
+impl crate::Readable for SAR_AMP_CTRL3_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sar_amp_ctrl3::W`](W) writer structure"]
+impl crate::Writable for SAR_AMP_CTRL3_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SAR_AMP_CTRL3 to value 0x0073_38f3"]
+impl crate::Resettable for SAR_AMP_CTRL3_SPEC {
+    const RESET_VALUE: u32 = 0x0073_38f3;
+}

vendor/esp32s3/src/sens/sar_atten1.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `SAR_ATTEN1` reader"]
+pub type R = crate::R<SAR_ATTEN1_SPEC>;
+#[doc = "Register `SAR_ATTEN1` writer"]
+pub type W = crate::W<SAR_ATTEN1_SPEC>;
+#[doc = "Field `SAR1_ATTEN` reader - 2-bit attenuation for each pad"]
+pub type SAR1_ATTEN_R = crate::FieldReader<u32>;
+#[doc = "Field `SAR1_ATTEN` writer - 2-bit attenuation for each pad"]
+pub type SAR1_ATTEN_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - 2-bit attenuation for each pad"]
+    #[inline(always)]
+    pub fn sar1_atten(&self) -> SAR1_ATTEN_R {
+        SAR1_ATTEN_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_ATTEN1")
+            .field("sar1_atten", &self.sar1_atten())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - 2-bit attenuation for each pad"]
+    #[inline(always)]
+    pub fn sar1_atten(&mut self) -> SAR1_ATTEN_W<SAR_ATTEN1_SPEC> {
+        SAR1_ATTEN_W::new(self, 0)
+    }
+}
+#[doc = "configure saradc1 controller\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_atten1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_atten1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_ATTEN1_SPEC;
+impl crate::RegisterSpec for SAR_ATTEN1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_atten1::R`](R) reader structure"]
+impl crate::Readable for SAR_ATTEN1_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sar_atten1::W`](W) writer structure"]
+impl crate::Writable for SAR_ATTEN1_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SAR_ATTEN1 to value 0xffff_ffff"]
+impl crate::Resettable for SAR_ATTEN1_SPEC {
+    const RESET_VALUE: u32 = 0xffff_ffff;
+}

vendor/esp32s3/src/sens/sar_atten2.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `SAR_ATTEN2` reader"]
+pub type R = crate::R<SAR_ATTEN2_SPEC>;
+#[doc = "Register `SAR_ATTEN2` writer"]
+pub type W = crate::W<SAR_ATTEN2_SPEC>;
+#[doc = "Field `SAR2_ATTEN` reader - 2-bit attenuation for each pad"]
+pub type SAR2_ATTEN_R = crate::FieldReader<u32>;
+#[doc = "Field `SAR2_ATTEN` writer - 2-bit attenuation for each pad"]
+pub type SAR2_ATTEN_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - 2-bit attenuation for each pad"]
+    #[inline(always)]
+    pub fn sar2_atten(&self) -> SAR2_ATTEN_R {
+        SAR2_ATTEN_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_ATTEN2")
+            .field("sar2_atten", &self.sar2_atten())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - 2-bit attenuation for each pad"]
+    #[inline(always)]
+    pub fn sar2_atten(&mut self) -> SAR2_ATTEN_W<SAR_ATTEN2_SPEC> {
+        SAR2_ATTEN_W::new(self, 0)
+    }
+}
+#[doc = "configure saradc2 controller\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_atten2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_atten2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_ATTEN2_SPEC;
+impl crate::RegisterSpec for SAR_ATTEN2_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_atten2::R`](R) reader structure"]
+impl crate::Readable for SAR_ATTEN2_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sar_atten2::W`](W) writer structure"]
+impl crate::Writable for SAR_ATTEN2_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SAR_ATTEN2 to value 0xffff_ffff"]
+impl crate::Resettable for SAR_ATTEN2_SPEC {
+    const RESET_VALUE: u32 = 0xffff_ffff;
+}

vendor/esp32s3/src/sens/sar_cocpu_debug.rs

@@ -0,0 +1,62 @@
+#[doc = "Register `SAR_COCPU_DEBUG` reader"]
+pub type R = crate::R<SAR_COCPU_DEBUG_SPEC>;
+#[doc = "Field `SAR_COCPU_PC` reader - cocpu Program counter"]
+pub type SAR_COCPU_PC_R = crate::FieldReader<u16>;
+#[doc = "Field `SAR_COCPU_MEM_VLD` reader - cocpu mem valid output"]
+pub type SAR_COCPU_MEM_VLD_R = crate::BitReader;
+#[doc = "Field `SAR_COCPU_MEM_RDY` reader - cocpu mem ready input"]
+pub type SAR_COCPU_MEM_RDY_R = crate::BitReader;
+#[doc = "Field `SAR_COCPU_MEM_WEN` reader - cocpu mem write enable output"]
+pub type SAR_COCPU_MEM_WEN_R = crate::FieldReader;
+#[doc = "Field `SAR_COCPU_MEM_ADDR` reader - cocpu mem address output"]
+pub type SAR_COCPU_MEM_ADDR_R = crate::FieldReader<u16>;
+impl R {
+    #[doc = "Bits 0:12 - cocpu Program counter"]
+    #[inline(always)]
+    pub fn sar_cocpu_pc(&self) -> SAR_COCPU_PC_R {
+        SAR_COCPU_PC_R::new((self.bits & 0x1fff) as u16)
+    }
+    #[doc = "Bit 13 - cocpu mem valid output"]
+    #[inline(always)]
+    pub fn sar_cocpu_mem_vld(&self) -> SAR_COCPU_MEM_VLD_R {
+        SAR_COCPU_MEM_VLD_R::new(((self.bits >> 13) & 1) != 0)
+    }
+    #[doc = "Bit 14 - cocpu mem ready input"]
+    #[inline(always)]
+    pub fn sar_cocpu_mem_rdy(&self) -> SAR_COCPU_MEM_RDY_R {
+        SAR_COCPU_MEM_RDY_R::new(((self.bits >> 14) & 1) != 0)
+    }
+    #[doc = "Bits 15:18 - cocpu mem write enable output"]
+    #[inline(always)]
+    pub fn sar_cocpu_mem_wen(&self) -> SAR_COCPU_MEM_WEN_R {
+        SAR_COCPU_MEM_WEN_R::new(((self.bits >> 15) & 0x0f) as u8)
+    }
+    #[doc = "Bits 19:31 - cocpu mem address output"]
+    #[inline(always)]
+    pub fn sar_cocpu_mem_addr(&self) -> SAR_COCPU_MEM_ADDR_R {
+        SAR_COCPU_MEM_ADDR_R::new(((self.bits >> 19) & 0x1fff) as u16)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_COCPU_DEBUG")
+            .field("sar_cocpu_pc", &self.sar_cocpu_pc())
+            .field("sar_cocpu_mem_vld", &self.sar_cocpu_mem_vld())
+            .field("sar_cocpu_mem_rdy", &self.sar_cocpu_mem_rdy())
+            .field("sar_cocpu_mem_wen", &self.sar_cocpu_mem_wen())
+            .field("sar_cocpu_mem_addr", &self.sar_cocpu_mem_addr())
+            .finish()
+    }
+}
+#[doc = "Ulp-riscv debug signal\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_cocpu_debug::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_COCPU_DEBUG_SPEC;
+impl crate::RegisterSpec for SAR_COCPU_DEBUG_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_cocpu_debug::R`](R) reader structure"]
+impl crate::Readable for SAR_COCPU_DEBUG_SPEC {}
+#[doc = "`reset()` method sets SAR_COCPU_DEBUG to value 0"]
+impl crate::Resettable for SAR_COCPU_DEBUG_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sens/sar_cocpu_int_clr.rs

@@ -0,0 +1,125 @@
+#[doc = "Register `SAR_COCPU_INT_CLR` writer"]
+pub type W = crate::W<SAR_COCPU_INT_CLR_SPEC>;
+#[doc = "Field `SAR_COCPU_TOUCH_DONE_INT_CLR` writer - int clear of touch done"]
+pub type SAR_COCPU_TOUCH_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_COCPU_TOUCH_INACTIVE_INT_CLR` writer - int clear of from touch inactive"]
+pub type SAR_COCPU_TOUCH_INACTIVE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_COCPU_TOUCH_ACTIVE_INT_CLR` writer - int clear of touch active"]
+pub type SAR_COCPU_TOUCH_ACTIVE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_COCPU_SARADC1_INT_CLR` writer - int clear of from saradc1"]
+pub type SAR_COCPU_SARADC1_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_COCPU_SARADC2_INT_CLR` writer - int clear of from saradc2"]
+pub type SAR_COCPU_SARADC2_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_COCPU_TSENS_INT_CLR` writer - int clear of tsens"]
+pub type SAR_COCPU_TSENS_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_COCPU_START_INT_CLR` writer - int clear of start"]
+pub type SAR_COCPU_START_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_COCPU_SW_INT_CLR` writer - int clear of software"]
+pub type SAR_COCPU_SW_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_COCPU_SWD_INT_CLR` writer - int clear of super watch dog"]
+pub type SAR_COCPU_SWD_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_COCPU_TOUCH_TIMEOUT_INT_CLR` writer - int clear of timeout done"]
+pub type SAR_COCPU_TOUCH_TIMEOUT_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR` writer - int clear of approach loop done"]
+pub type SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_COCPU_TOUCH_SCAN_DONE_INT_CLR` writer - int clear of touch scan done"]
+pub type SAR_COCPU_TOUCH_SCAN_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for crate::generic::Reg<SAR_COCPU_INT_CLR_SPEC> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "(not readable)")
+    }
+}
+impl W {
+    #[doc = "Bit 0 - int clear of touch done"]
+    #[inline(always)]
+    pub fn sar_cocpu_touch_done_int_clr(
+        &mut self,
+    ) -> SAR_COCPU_TOUCH_DONE_INT_CLR_W<SAR_COCPU_INT_CLR_SPEC> {
+        SAR_COCPU_TOUCH_DONE_INT_CLR_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - int clear of from touch inactive"]
+    #[inline(always)]
+    pub fn sar_cocpu_touch_inactive_int_clr(
+        &mut self,
+    ) -> SAR_COCPU_TOUCH_INACTIVE_INT_CLR_W<SAR_COCPU_INT_CLR_SPEC> {
+        SAR_COCPU_TOUCH_INACTIVE_INT_CLR_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - int clear of touch active"]
+    #[inline(always)]
+    pub fn sar_cocpu_touch_active_int_clr(
+        &mut self,
+    ) -> SAR_COCPU_TOUCH_ACTIVE_INT_CLR_W<SAR_COCPU_INT_CLR_SPEC> {
+        SAR_COCPU_TOUCH_ACTIVE_INT_CLR_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - int clear of from saradc1"]
+    #[inline(always)]
+    pub fn sar_cocpu_saradc1_int_clr(
+        &mut self,
+    ) -> SAR_COCPU_SARADC1_INT_CLR_W<SAR_COCPU_INT_CLR_SPEC> {
+        SAR_COCPU_SARADC1_INT_CLR_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - int clear of from saradc2"]
+    #[inline(always)]
+    pub fn sar_cocpu_saradc2_int_clr(
+        &mut self,
+    ) -> SAR_COCPU_SARADC2_INT_CLR_W<SAR_COCPU_INT_CLR_SPEC> {
+        SAR_COCPU_SARADC2_INT_CLR_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - int clear of tsens"]
+    #[inline(always)]
+    pub fn sar_cocpu_tsens_int_clr(&mut self) -> SAR_COCPU_TSENS_INT_CLR_W<SAR_COCPU_INT_CLR_SPEC> {
+        SAR_COCPU_TSENS_INT_CLR_W::new(self, 5)
+    }
+    #[doc = "Bit 6 - int clear of start"]
+    #[inline(always)]
+    pub fn sar_cocpu_start_int_clr(&mut self) -> SAR_COCPU_START_INT_CLR_W<SAR_COCPU_INT_CLR_SPEC> {
+        SAR_COCPU_START_INT_CLR_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - int clear of software"]
+    #[inline(always)]
+    pub fn sar_cocpu_sw_int_clr(&mut self) -> SAR_COCPU_SW_INT_CLR_W<SAR_COCPU_INT_CLR_SPEC> {
+        SAR_COCPU_SW_INT_CLR_W::new(self, 7)
+    }
+    #[doc = "Bit 8 - int clear of super watch dog"]
+    #[inline(always)]
+    pub fn sar_cocpu_swd_int_clr(&mut self) -> SAR_COCPU_SWD_INT_CLR_W<SAR_COCPU_INT_CLR_SPEC> {
+        SAR_COCPU_SWD_INT_CLR_W::new(self, 8)
+    }
+    #[doc = "Bit 9 - int clear of timeout done"]
+    #[inline(always)]
+    pub fn sar_cocpu_touch_timeout_int_clr(
+        &mut self,
+    ) -> SAR_COCPU_TOUCH_TIMEOUT_INT_CLR_W<SAR_COCPU_INT_CLR_SPEC> {
+        SAR_COCPU_TOUCH_TIMEOUT_INT_CLR_W::new(self, 9)
+    }
+    #[doc = "Bit 10 - int clear of approach loop done"]
+    #[inline(always)]
+    pub fn sar_cocpu_touch_approach_loop_done_int_clr(
+        &mut self,
+    ) -> SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR_W<SAR_COCPU_INT_CLR_SPEC> {
+        SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR_W::new(self, 10)
+    }
+    #[doc = "Bit 11 - int clear of touch scan done"]
+    #[inline(always)]
+    pub fn sar_cocpu_touch_scan_done_int_clr(
+        &mut self,
+    ) -> SAR_COCPU_TOUCH_SCAN_DONE_INT_CLR_W<SAR_COCPU_INT_CLR_SPEC> {
+        SAR_COCPU_TOUCH_SCAN_DONE_INT_CLR_W::new(self, 11)
+    }
+}
+#[doc = "the interrupt clear of ulp\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_cocpu_int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_COCPU_INT_CLR_SPEC;
+impl crate::RegisterSpec for SAR_COCPU_INT_CLR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [`sar_cocpu_int_clr::W`](W) writer structure"]
+impl crate::Writable for SAR_COCPU_INT_CLR_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SAR_COCPU_INT_CLR to value 0"]
+impl crate::Resettable for SAR_COCPU_INT_CLR_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sens/sar_cocpu_int_ena.rs

@@ -0,0 +1,254 @@
+#[doc = "Register `SAR_COCPU_INT_ENA` reader"]
+pub type R = crate::R<SAR_COCPU_INT_ENA_SPEC>;
+#[doc = "Register `SAR_COCPU_INT_ENA` writer"]
+pub type W = crate::W<SAR_COCPU_INT_ENA_SPEC>;
+#[doc = "Field `SAR_COCPU_TOUCH_DONE_INT_ENA` reader - int enable of touch done"]
+pub type SAR_COCPU_TOUCH_DONE_INT_ENA_R = crate::BitReader;
+#[doc = "Field `SAR_COCPU_TOUCH_DONE_INT_ENA` writer - int enable of touch done"]
+pub type SAR_COCPU_TOUCH_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_COCPU_TOUCH_INACTIVE_INT_ENA` reader - int enable of from touch inactive"]
+pub type SAR_COCPU_TOUCH_INACTIVE_INT_ENA_R = crate::BitReader;
+#[doc = "Field `SAR_COCPU_TOUCH_INACTIVE_INT_ENA` writer - int enable of from touch inactive"]
+pub type SAR_COCPU_TOUCH_INACTIVE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_COCPU_TOUCH_ACTIVE_INT_ENA` reader - int enable of touch active"]
+pub type SAR_COCPU_TOUCH_ACTIVE_INT_ENA_R = crate::BitReader;
+#[doc = "Field `SAR_COCPU_TOUCH_ACTIVE_INT_ENA` writer - int enable of touch active"]
+pub type SAR_COCPU_TOUCH_ACTIVE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_COCPU_SARADC1_INT_ENA` reader - int enable of from saradc1"]
+pub type SAR_COCPU_SARADC1_INT_ENA_R = crate::BitReader;
+#[doc = "Field `SAR_COCPU_SARADC1_INT_ENA` writer - int enable of from saradc1"]
+pub type SAR_COCPU_SARADC1_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_COCPU_SARADC2_INT_ENA` reader - int enable of from saradc2"]
+pub type SAR_COCPU_SARADC2_INT_ENA_R = crate::BitReader;
+#[doc = "Field `SAR_COCPU_SARADC2_INT_ENA` writer - int enable of from saradc2"]
+pub type SAR_COCPU_SARADC2_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_COCPU_TSENS_INT_ENA` reader - int enable of tsens"]
+pub type SAR_COCPU_TSENS_INT_ENA_R = crate::BitReader;
+#[doc = "Field `SAR_COCPU_TSENS_INT_ENA` writer - int enable of tsens"]
+pub type SAR_COCPU_TSENS_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_COCPU_START_INT_ENA` reader - int enable of start"]
+pub type SAR_COCPU_START_INT_ENA_R = crate::BitReader;
+#[doc = "Field `SAR_COCPU_START_INT_ENA` writer - int enable of start"]
+pub type SAR_COCPU_START_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_COCPU_SW_INT_ENA` reader - int enable of software"]
+pub type SAR_COCPU_SW_INT_ENA_R = crate::BitReader;
+#[doc = "Field `SAR_COCPU_SW_INT_ENA` writer - int enable of software"]
+pub type SAR_COCPU_SW_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_COCPU_SWD_INT_ENA` reader - int enable of super watch dog"]
+pub type SAR_COCPU_SWD_INT_ENA_R = crate::BitReader;
+#[doc = "Field `SAR_COCPU_SWD_INT_ENA` writer - int enable of super watch dog"]
+pub type SAR_COCPU_SWD_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_COCPU_TOUCH_TIMEOUT_INT_ENA` reader - int enable of timeout done"]
+pub type SAR_COCPU_TOUCH_TIMEOUT_INT_ENA_R = crate::BitReader;
+#[doc = "Field `SAR_COCPU_TOUCH_TIMEOUT_INT_ENA` writer - int enable of timeout done"]
+pub type SAR_COCPU_TOUCH_TIMEOUT_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA` reader - int enable of approach loop done"]
+pub type SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_R = crate::BitReader;
+#[doc = "Field `SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA` writer - int enable of approach loop done"]
+pub type SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA` reader - int enable of touch scan done"]
+pub type SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA_R = crate::BitReader;
+#[doc = "Field `SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA` writer - int enable of touch scan done"]
+pub type SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - int enable of touch done"]
+    #[inline(always)]
+    pub fn sar_cocpu_touch_done_int_ena(&self) -> SAR_COCPU_TOUCH_DONE_INT_ENA_R {
+        SAR_COCPU_TOUCH_DONE_INT_ENA_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - int enable of from touch inactive"]
+    #[inline(always)]
+    pub fn sar_cocpu_touch_inactive_int_ena(&self) -> SAR_COCPU_TOUCH_INACTIVE_INT_ENA_R {
+        SAR_COCPU_TOUCH_INACTIVE_INT_ENA_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - int enable of touch active"]
+    #[inline(always)]
+    pub fn sar_cocpu_touch_active_int_ena(&self) -> SAR_COCPU_TOUCH_ACTIVE_INT_ENA_R {
+        SAR_COCPU_TOUCH_ACTIVE_INT_ENA_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - int enable of from saradc1"]
+    #[inline(always)]
+    pub fn sar_cocpu_saradc1_int_ena(&self) -> SAR_COCPU_SARADC1_INT_ENA_R {
+        SAR_COCPU_SARADC1_INT_ENA_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - int enable of from saradc2"]
+    #[inline(always)]
+    pub fn sar_cocpu_saradc2_int_ena(&self) -> SAR_COCPU_SARADC2_INT_ENA_R {
+        SAR_COCPU_SARADC2_INT_ENA_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - int enable of tsens"]
+    #[inline(always)]
+    pub fn sar_cocpu_tsens_int_ena(&self) -> SAR_COCPU_TSENS_INT_ENA_R {
+        SAR_COCPU_TSENS_INT_ENA_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - int enable of start"]
+    #[inline(always)]
+    pub fn sar_cocpu_start_int_ena(&self) -> SAR_COCPU_START_INT_ENA_R {
+        SAR_COCPU_START_INT_ENA_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - int enable of software"]
+    #[inline(always)]
+    pub fn sar_cocpu_sw_int_ena(&self) -> SAR_COCPU_SW_INT_ENA_R {
+        SAR_COCPU_SW_INT_ENA_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - int enable of super watch dog"]
+    #[inline(always)]
+    pub fn sar_cocpu_swd_int_ena(&self) -> SAR_COCPU_SWD_INT_ENA_R {
+        SAR_COCPU_SWD_INT_ENA_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - int enable of timeout done"]
+    #[inline(always)]
+    pub fn sar_cocpu_touch_timeout_int_ena(&self) -> SAR_COCPU_TOUCH_TIMEOUT_INT_ENA_R {
+        SAR_COCPU_TOUCH_TIMEOUT_INT_ENA_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 10 - int enable of approach loop done"]
+    #[inline(always)]
+    pub fn sar_cocpu_touch_approach_loop_done_int_ena(
+        &self,
+    ) -> SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_R {
+        SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_R::new(((self.bits >> 10) & 1) != 0)
+    }
+    #[doc = "Bit 11 - int enable of touch scan done"]
+    #[inline(always)]
+    pub fn sar_cocpu_touch_scan_done_int_ena(&self) -> SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA_R {
+        SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA_R::new(((self.bits >> 11) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_COCPU_INT_ENA")
+            .field(
+                "sar_cocpu_touch_done_int_ena",
+                &self.sar_cocpu_touch_done_int_ena(),
+            )
+            .field(
+                "sar_cocpu_touch_inactive_int_ena",
+                &self.sar_cocpu_touch_inactive_int_ena(),
+            )
+            .field(
+                "sar_cocpu_touch_active_int_ena",
+                &self.sar_cocpu_touch_active_int_ena(),
+            )
+            .field(
+                "sar_cocpu_saradc1_int_ena",
+                &self.sar_cocpu_saradc1_int_ena(),
+            )
+            .field(
+                "sar_cocpu_saradc2_int_ena",
+                &self.sar_cocpu_saradc2_int_ena(),
+            )
+            .field("sar_cocpu_tsens_int_ena", &self.sar_cocpu_tsens_int_ena())
+            .field("sar_cocpu_start_int_ena", &self.sar_cocpu_start_int_ena())
+            .field("sar_cocpu_sw_int_ena", &self.sar_cocpu_sw_int_ena())
+            .field("sar_cocpu_swd_int_ena", &self.sar_cocpu_swd_int_ena())
+            .field(
+                "sar_cocpu_touch_timeout_int_ena",
+                &self.sar_cocpu_touch_timeout_int_ena(),
+            )
+            .field(
+                "sar_cocpu_touch_approach_loop_done_int_ena",
+                &self.sar_cocpu_touch_approach_loop_done_int_ena(),
+            )
+            .field(
+                "sar_cocpu_touch_scan_done_int_ena",
+                &self.sar_cocpu_touch_scan_done_int_ena(),
+            )
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - int enable of touch done"]
+    #[inline(always)]
+    pub fn sar_cocpu_touch_done_int_ena(
+        &mut self,
+    ) -> SAR_COCPU_TOUCH_DONE_INT_ENA_W<SAR_COCPU_INT_ENA_SPEC> {
+        SAR_COCPU_TOUCH_DONE_INT_ENA_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - int enable of from touch inactive"]
+    #[inline(always)]
+    pub fn sar_cocpu_touch_inactive_int_ena(
+        &mut self,
+    ) -> SAR_COCPU_TOUCH_INACTIVE_INT_ENA_W<SAR_COCPU_INT_ENA_SPEC> {
+        SAR_COCPU_TOUCH_INACTIVE_INT_ENA_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - int enable of touch active"]
+    #[inline(always)]
+    pub fn sar_cocpu_touch_active_int_ena(
+        &mut self,
+    ) -> SAR_COCPU_TOUCH_ACTIVE_INT_ENA_W<SAR_COCPU_INT_ENA_SPEC> {
+        SAR_COCPU_TOUCH_ACTIVE_INT_ENA_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - int enable of from saradc1"]
+    #[inline(always)]
+    pub fn sar_cocpu_saradc1_int_ena(
+        &mut self,
+    ) -> SAR_COCPU_SARADC1_INT_ENA_W<SAR_COCPU_INT_ENA_SPEC> {
+        SAR_COCPU_SARADC1_INT_ENA_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - int enable of from saradc2"]
+    #[inline(always)]
+    pub fn sar_cocpu_saradc2_int_ena(
+        &mut self,
+    ) -> SAR_COCPU_SARADC2_INT_ENA_W<SAR_COCPU_INT_ENA_SPEC> {
+        SAR_COCPU_SARADC2_INT_ENA_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - int enable of tsens"]
+    #[inline(always)]
+    pub fn sar_cocpu_tsens_int_ena(&mut self) -> SAR_COCPU_TSENS_INT_ENA_W<SAR_COCPU_INT_ENA_SPEC> {
+        SAR_COCPU_TSENS_INT_ENA_W::new(self, 5)
+    }
+    #[doc = "Bit 6 - int enable of start"]
+    #[inline(always)]
+    pub fn sar_cocpu_start_int_ena(&mut self) -> SAR_COCPU_START_INT_ENA_W<SAR_COCPU_INT_ENA_SPEC> {
+        SAR_COCPU_START_INT_ENA_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - int enable of software"]
+    #[inline(always)]
+    pub fn sar_cocpu_sw_int_ena(&mut self) -> SAR_COCPU_SW_INT_ENA_W<SAR_COCPU_INT_ENA_SPEC> {
+        SAR_COCPU_SW_INT_ENA_W::new(self, 7)
+    }
+    #[doc = "Bit 8 - int enable of super watch dog"]
+    #[inline(always)]
+    pub fn sar_cocpu_swd_int_ena(&mut self) -> SAR_COCPU_SWD_INT_ENA_W<SAR_COCPU_INT_ENA_SPEC> {
+        SAR_COCPU_SWD_INT_ENA_W::new(self, 8)
+    }
+    #[doc = "Bit 9 - int enable of timeout done"]
+    #[inline(always)]
+    pub fn sar_cocpu_touch_timeout_int_ena(
+        &mut self,
+    ) -> SAR_COCPU_TOUCH_TIMEOUT_INT_ENA_W<SAR_COCPU_INT_ENA_SPEC> {
+        SAR_COCPU_TOUCH_TIMEOUT_INT_ENA_W::new(self, 9)
+    }
+    #[doc = "Bit 10 - int enable of approach loop done"]
+    #[inline(always)]
+    pub fn sar_cocpu_touch_approach_loop_done_int_ena(
+        &mut self,
+    ) -> SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W<SAR_COCPU_INT_ENA_SPEC> {
+        SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W::new(self, 10)
+    }
+    #[doc = "Bit 11 - int enable of touch scan done"]
+    #[inline(always)]
+    pub fn sar_cocpu_touch_scan_done_int_ena(
+        &mut self,
+    ) -> SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA_W<SAR_COCPU_INT_ENA_SPEC> {
+        SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA_W::new(self, 11)
+    }
+}
+#[doc = "the interrupt enable of ulp\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_cocpu_int_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_cocpu_int_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_COCPU_INT_ENA_SPEC;
+impl crate::RegisterSpec for SAR_COCPU_INT_ENA_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_cocpu_int_ena::R`](R) reader structure"]
+impl crate::Readable for SAR_COCPU_INT_ENA_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sar_cocpu_int_ena::W`](W) writer structure"]
+impl crate::Writable for SAR_COCPU_INT_ENA_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SAR_COCPU_INT_ENA to value 0"]
+impl crate::Resettable for SAR_COCPU_INT_ENA_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sens/sar_cocpu_int_ena_w1tc.rs

@@ -0,0 +1,133 @@
+#[doc = "Register `SAR_COCPU_INT_ENA_W1TC` writer"]
+pub type W = crate::W<SAR_COCPU_INT_ENA_W1TC_SPEC>;
+#[doc = "Field `SAR_COCPU_TOUCH_DONE_INT_ENA_W1TC` writer - Clear int enable of touch done"]
+pub type SAR_COCPU_TOUCH_DONE_INT_ENA_W1TC_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_COCPU_TOUCH_INACTIVE_INT_ENA_W1TC` writer - Clear int enable of from touch inactive"]
+pub type SAR_COCPU_TOUCH_INACTIVE_INT_ENA_W1TC_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_COCPU_TOUCH_ACTIVE_INT_ENA_W1TC` writer - Clear int enable of touch active"]
+pub type SAR_COCPU_TOUCH_ACTIVE_INT_ENA_W1TC_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_COCPU_SARADC1_INT_ENA_W1TC` writer - Clear int enable of from saradc1"]
+pub type SAR_COCPU_SARADC1_INT_ENA_W1TC_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_COCPU_SARADC2_INT_ENA_W1TC` writer - Clear int enable of from saradc2"]
+pub type SAR_COCPU_SARADC2_INT_ENA_W1TC_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_COCPU_TSENS_INT_ENA_W1TC` writer - Clear int enable of tsens"]
+pub type SAR_COCPU_TSENS_INT_ENA_W1TC_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_COCPU_START_INT_ENA_W1TC` writer - Clear int enable of start"]
+pub type SAR_COCPU_START_INT_ENA_W1TC_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_COCPU_SW_INT_ENA_W1TC` writer - Clear int enable of software"]
+pub type SAR_COCPU_SW_INT_ENA_W1TC_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_COCPU_SWD_INT_ENA_W1TC` writer - Clear int enable of super watch dog"]
+pub type SAR_COCPU_SWD_INT_ENA_W1TC_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TC` writer - Clear int enable of timeout done"]
+pub type SAR_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TC_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC` writer - Clear int enable of approach loop done"]
+pub type SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TC` writer - Clear int enable of touch scan done"]
+pub type SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TC_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for crate::generic::Reg<SAR_COCPU_INT_ENA_W1TC_SPEC> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "(not readable)")
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Clear int enable of touch done"]
+    #[inline(always)]
+    pub fn sar_cocpu_touch_done_int_ena_w1tc(
+        &mut self,
+    ) -> SAR_COCPU_TOUCH_DONE_INT_ENA_W1TC_W<SAR_COCPU_INT_ENA_W1TC_SPEC> {
+        SAR_COCPU_TOUCH_DONE_INT_ENA_W1TC_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - Clear int enable of from touch inactive"]
+    #[inline(always)]
+    pub fn sar_cocpu_touch_inactive_int_ena_w1tc(
+        &mut self,
+    ) -> SAR_COCPU_TOUCH_INACTIVE_INT_ENA_W1TC_W<SAR_COCPU_INT_ENA_W1TC_SPEC> {
+        SAR_COCPU_TOUCH_INACTIVE_INT_ENA_W1TC_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - Clear int enable of touch active"]
+    #[inline(always)]
+    pub fn sar_cocpu_touch_active_int_ena_w1tc(
+        &mut self,
+    ) -> SAR_COCPU_TOUCH_ACTIVE_INT_ENA_W1TC_W<SAR_COCPU_INT_ENA_W1TC_SPEC> {
+        SAR_COCPU_TOUCH_ACTIVE_INT_ENA_W1TC_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - Clear int enable of from saradc1"]
+    #[inline(always)]
+    pub fn sar_cocpu_saradc1_int_ena_w1tc(
+        &mut self,
+    ) -> SAR_COCPU_SARADC1_INT_ENA_W1TC_W<SAR_COCPU_INT_ENA_W1TC_SPEC> {
+        SAR_COCPU_SARADC1_INT_ENA_W1TC_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - Clear int enable of from saradc2"]
+    #[inline(always)]
+    pub fn sar_cocpu_saradc2_int_ena_w1tc(
+        &mut self,
+    ) -> SAR_COCPU_SARADC2_INT_ENA_W1TC_W<SAR_COCPU_INT_ENA_W1TC_SPEC> {
+        SAR_COCPU_SARADC2_INT_ENA_W1TC_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - Clear int enable of tsens"]
+    #[inline(always)]
+    pub fn sar_cocpu_tsens_int_ena_w1tc(
+        &mut self,
+    ) -> SAR_COCPU_TSENS_INT_ENA_W1TC_W<SAR_COCPU_INT_ENA_W1TC_SPEC> {
+        SAR_COCPU_TSENS_INT_ENA_W1TC_W::new(self, 5)
+    }
+    #[doc = "Bit 6 - Clear int enable of start"]
+    #[inline(always)]
+    pub fn sar_cocpu_start_int_ena_w1tc(
+        &mut self,
+    ) -> SAR_COCPU_START_INT_ENA_W1TC_W<SAR_COCPU_INT_ENA_W1TC_SPEC> {
+        SAR_COCPU_START_INT_ENA_W1TC_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - Clear int enable of software"]
+    #[inline(always)]
+    pub fn sar_cocpu_sw_int_ena_w1tc(
+        &mut self,
+    ) -> SAR_COCPU_SW_INT_ENA_W1TC_W<SAR_COCPU_INT_ENA_W1TC_SPEC> {
+        SAR_COCPU_SW_INT_ENA_W1TC_W::new(self, 7)
+    }
+    #[doc = "Bit 8 - Clear int enable of super watch dog"]
+    #[inline(always)]
+    pub fn sar_cocpu_swd_int_ena_w1tc(
+        &mut self,
+    ) -> SAR_COCPU_SWD_INT_ENA_W1TC_W<SAR_COCPU_INT_ENA_W1TC_SPEC> {
+        SAR_COCPU_SWD_INT_ENA_W1TC_W::new(self, 8)
+    }
+    #[doc = "Bit 9 - Clear int enable of timeout done"]
+    #[inline(always)]
+    pub fn sar_cocpu_touch_timeout_int_ena_w1tc(
+        &mut self,
+    ) -> SAR_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TC_W<SAR_COCPU_INT_ENA_W1TC_SPEC> {
+        SAR_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TC_W::new(self, 9)
+    }
+    #[doc = "Bit 10 - Clear int enable of approach loop done"]
+    #[inline(always)]
+    pub fn sar_cocpu_touch_approach_loop_done_int_ena_w1tc(
+        &mut self,
+    ) -> SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_W<SAR_COCPU_INT_ENA_W1TC_SPEC> {
+        SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_W::new(self, 10)
+    }
+    #[doc = "Bit 11 - Clear int enable of touch scan done"]
+    #[inline(always)]
+    pub fn sar_cocpu_touch_scan_done_int_ena_w1tc(
+        &mut self,
+    ) -> SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TC_W<SAR_COCPU_INT_ENA_W1TC_SPEC> {
+        SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TC_W::new(self, 11)
+    }
+}
+#[doc = "the interrupt enable clear of ulp\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_cocpu_int_ena_w1tc::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_COCPU_INT_ENA_W1TC_SPEC;
+impl crate::RegisterSpec for SAR_COCPU_INT_ENA_W1TC_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [`sar_cocpu_int_ena_w1tc::W`](W) writer structure"]
+impl crate::Writable for SAR_COCPU_INT_ENA_W1TC_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SAR_COCPU_INT_ENA_W1TC to value 0"]
+impl crate::Resettable for SAR_COCPU_INT_ENA_W1TC_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sens/sar_cocpu_int_ena_w1ts.rs

@@ -0,0 +1,133 @@
+#[doc = "Register `SAR_COCPU_INT_ENA_W1TS` writer"]
+pub type W = crate::W<SAR_COCPU_INT_ENA_W1TS_SPEC>;
+#[doc = "Field `SAR_COCPU_TOUCH_DONE_INT_ENA_W1TS` writer - int enable of touch done"]
+pub type SAR_COCPU_TOUCH_DONE_INT_ENA_W1TS_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_COCPU_TOUCH_INACTIVE_INT_ENA_W1TS` writer - int enable of from touch inactive"]
+pub type SAR_COCPU_TOUCH_INACTIVE_INT_ENA_W1TS_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_COCPU_TOUCH_ACTIVE_INT_ENA_W1TS` writer - int enable of touch active"]
+pub type SAR_COCPU_TOUCH_ACTIVE_INT_ENA_W1TS_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_COCPU_SARADC1_INT_ENA_W1TS` writer - int enable of from saradc1"]
+pub type SAR_COCPU_SARADC1_INT_ENA_W1TS_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_COCPU_SARADC2_INT_ENA_W1TS` writer - int enable of from saradc2"]
+pub type SAR_COCPU_SARADC2_INT_ENA_W1TS_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_COCPU_TSENS_INT_ENA_W1TS` writer - int enable of tsens"]
+pub type SAR_COCPU_TSENS_INT_ENA_W1TS_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_COCPU_START_INT_ENA_W1TS` writer - int enable of start"]
+pub type SAR_COCPU_START_INT_ENA_W1TS_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_COCPU_SW_INT_ENA_W1TS` writer - int enable of software"]
+pub type SAR_COCPU_SW_INT_ENA_W1TS_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_COCPU_SWD_INT_ENA_W1TS` writer - int enable of super watch dog"]
+pub type SAR_COCPU_SWD_INT_ENA_W1TS_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TS` writer - int enable of timeout done"]
+pub type SAR_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TS_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS` writer - int enable of approach loop done"]
+pub type SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TS` writer - int enable of touch scan done"]
+pub type SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TS_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for crate::generic::Reg<SAR_COCPU_INT_ENA_W1TS_SPEC> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "(not readable)")
+    }
+}
+impl W {
+    #[doc = "Bit 0 - int enable of touch done"]
+    #[inline(always)]
+    pub fn sar_cocpu_touch_done_int_ena_w1ts(
+        &mut self,
+    ) -> SAR_COCPU_TOUCH_DONE_INT_ENA_W1TS_W<SAR_COCPU_INT_ENA_W1TS_SPEC> {
+        SAR_COCPU_TOUCH_DONE_INT_ENA_W1TS_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - int enable of from touch inactive"]
+    #[inline(always)]
+    pub fn sar_cocpu_touch_inactive_int_ena_w1ts(
+        &mut self,
+    ) -> SAR_COCPU_TOUCH_INACTIVE_INT_ENA_W1TS_W<SAR_COCPU_INT_ENA_W1TS_SPEC> {
+        SAR_COCPU_TOUCH_INACTIVE_INT_ENA_W1TS_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - int enable of touch active"]
+    #[inline(always)]
+    pub fn sar_cocpu_touch_active_int_ena_w1ts(
+        &mut self,
+    ) -> SAR_COCPU_TOUCH_ACTIVE_INT_ENA_W1TS_W<SAR_COCPU_INT_ENA_W1TS_SPEC> {
+        SAR_COCPU_TOUCH_ACTIVE_INT_ENA_W1TS_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - int enable of from saradc1"]
+    #[inline(always)]
+    pub fn sar_cocpu_saradc1_int_ena_w1ts(
+        &mut self,
+    ) -> SAR_COCPU_SARADC1_INT_ENA_W1TS_W<SAR_COCPU_INT_ENA_W1TS_SPEC> {
+        SAR_COCPU_SARADC1_INT_ENA_W1TS_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - int enable of from saradc2"]
+    #[inline(always)]
+    pub fn sar_cocpu_saradc2_int_ena_w1ts(
+        &mut self,
+    ) -> SAR_COCPU_SARADC2_INT_ENA_W1TS_W<SAR_COCPU_INT_ENA_W1TS_SPEC> {
+        SAR_COCPU_SARADC2_INT_ENA_W1TS_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - int enable of tsens"]
+    #[inline(always)]
+    pub fn sar_cocpu_tsens_int_ena_w1ts(
+        &mut self,
+    ) -> SAR_COCPU_TSENS_INT_ENA_W1TS_W<SAR_COCPU_INT_ENA_W1TS_SPEC> {
+        SAR_COCPU_TSENS_INT_ENA_W1TS_W::new(self, 5)
+    }
+    #[doc = "Bit 6 - int enable of start"]
+    #[inline(always)]
+    pub fn sar_cocpu_start_int_ena_w1ts(
+        &mut self,
+    ) -> SAR_COCPU_START_INT_ENA_W1TS_W<SAR_COCPU_INT_ENA_W1TS_SPEC> {
+        SAR_COCPU_START_INT_ENA_W1TS_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - int enable of software"]
+    #[inline(always)]
+    pub fn sar_cocpu_sw_int_ena_w1ts(
+        &mut self,
+    ) -> SAR_COCPU_SW_INT_ENA_W1TS_W<SAR_COCPU_INT_ENA_W1TS_SPEC> {
+        SAR_COCPU_SW_INT_ENA_W1TS_W::new(self, 7)
+    }
+    #[doc = "Bit 8 - int enable of super watch dog"]
+    #[inline(always)]
+    pub fn sar_cocpu_swd_int_ena_w1ts(
+        &mut self,
+    ) -> SAR_COCPU_SWD_INT_ENA_W1TS_W<SAR_COCPU_INT_ENA_W1TS_SPEC> {
+        SAR_COCPU_SWD_INT_ENA_W1TS_W::new(self, 8)
+    }
+    #[doc = "Bit 9 - int enable of timeout done"]
+    #[inline(always)]
+    pub fn sar_cocpu_touch_timeout_int_ena_w1ts(
+        &mut self,
+    ) -> SAR_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TS_W<SAR_COCPU_INT_ENA_W1TS_SPEC> {
+        SAR_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TS_W::new(self, 9)
+    }
+    #[doc = "Bit 10 - int enable of approach loop done"]
+    #[inline(always)]
+    pub fn sar_cocpu_touch_approach_loop_done_int_ena_w1ts(
+        &mut self,
+    ) -> SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_W<SAR_COCPU_INT_ENA_W1TS_SPEC> {
+        SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_W::new(self, 10)
+    }
+    #[doc = "Bit 11 - int enable of touch scan done"]
+    #[inline(always)]
+    pub fn sar_cocpu_touch_scan_done_int_ena_w1ts(
+        &mut self,
+    ) -> SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TS_W<SAR_COCPU_INT_ENA_W1TS_SPEC> {
+        SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TS_W::new(self, 11)
+    }
+}
+#[doc = "the interrupt enable of ulp\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_cocpu_int_ena_w1ts::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_COCPU_INT_ENA_W1TS_SPEC;
+impl crate::RegisterSpec for SAR_COCPU_INT_ENA_W1TS_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [`sar_cocpu_int_ena_w1ts::W`](W) writer structure"]
+impl crate::Writable for SAR_COCPU_INT_ENA_W1TS_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SAR_COCPU_INT_ENA_W1TS to value 0"]
+impl crate::Resettable for SAR_COCPU_INT_ENA_W1TS_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sens/sar_cocpu_int_raw.rs

@@ -0,0 +1,144 @@
+#[doc = "Register `SAR_COCPU_INT_RAW` reader"]
+pub type R = crate::R<SAR_COCPU_INT_RAW_SPEC>;
+#[doc = "Field `SAR_COCPU_TOUCH_DONE_INT_RAW` reader - int from touch done"]
+pub type SAR_COCPU_TOUCH_DONE_INT_RAW_R = crate::BitReader;
+#[doc = "Field `SAR_COCPU_TOUCH_INACTIVE_INT_RAW` reader - int from touch inactive"]
+pub type SAR_COCPU_TOUCH_INACTIVE_INT_RAW_R = crate::BitReader;
+#[doc = "Field `SAR_COCPU_TOUCH_ACTIVE_INT_RAW` reader - int from touch active"]
+pub type SAR_COCPU_TOUCH_ACTIVE_INT_RAW_R = crate::BitReader;
+#[doc = "Field `SAR_COCPU_SARADC1_INT_RAW` reader - int from saradc1"]
+pub type SAR_COCPU_SARADC1_INT_RAW_R = crate::BitReader;
+#[doc = "Field `SAR_COCPU_SARADC2_INT_RAW` reader - int from saradc2"]
+pub type SAR_COCPU_SARADC2_INT_RAW_R = crate::BitReader;
+#[doc = "Field `SAR_COCPU_TSENS_INT_RAW` reader - int from tsens"]
+pub type SAR_COCPU_TSENS_INT_RAW_R = crate::BitReader;
+#[doc = "Field `SAR_COCPU_START_INT_RAW` reader - int from start"]
+pub type SAR_COCPU_START_INT_RAW_R = crate::BitReader;
+#[doc = "Field `SAR_COCPU_SW_INT_RAW` reader - int from software"]
+pub type SAR_COCPU_SW_INT_RAW_R = crate::BitReader;
+#[doc = "Field `SAR_COCPU_SWD_INT_RAW` reader - int from super watch dog"]
+pub type SAR_COCPU_SWD_INT_RAW_R = crate::BitReader;
+#[doc = "Field `SAR_COCPU_TOUCH_TIMEOUT_INT_RAW` reader - int from timeout done"]
+pub type SAR_COCPU_TOUCH_TIMEOUT_INT_RAW_R = crate::BitReader;
+#[doc = "Field `SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_RAW` reader - int from approach loop done"]
+pub type SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_RAW_R = crate::BitReader;
+#[doc = "Field `SAR_COCPU_TOUCH_SCAN_DONE_INT_RAW` reader - int from touch scan done"]
+pub type SAR_COCPU_TOUCH_SCAN_DONE_INT_RAW_R = crate::BitReader;
+impl R {
+    #[doc = "Bit 0 - int from touch done"]
+    #[inline(always)]
+    pub fn sar_cocpu_touch_done_int_raw(&self) -> SAR_COCPU_TOUCH_DONE_INT_RAW_R {
+        SAR_COCPU_TOUCH_DONE_INT_RAW_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - int from touch inactive"]
+    #[inline(always)]
+    pub fn sar_cocpu_touch_inactive_int_raw(&self) -> SAR_COCPU_TOUCH_INACTIVE_INT_RAW_R {
+        SAR_COCPU_TOUCH_INACTIVE_INT_RAW_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - int from touch active"]
+    #[inline(always)]
+    pub fn sar_cocpu_touch_active_int_raw(&self) -> SAR_COCPU_TOUCH_ACTIVE_INT_RAW_R {
+        SAR_COCPU_TOUCH_ACTIVE_INT_RAW_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - int from saradc1"]
+    #[inline(always)]
+    pub fn sar_cocpu_saradc1_int_raw(&self) -> SAR_COCPU_SARADC1_INT_RAW_R {
+        SAR_COCPU_SARADC1_INT_RAW_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - int from saradc2"]
+    #[inline(always)]
+    pub fn sar_cocpu_saradc2_int_raw(&self) -> SAR_COCPU_SARADC2_INT_RAW_R {
+        SAR_COCPU_SARADC2_INT_RAW_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - int from tsens"]
+    #[inline(always)]
+    pub fn sar_cocpu_tsens_int_raw(&self) -> SAR_COCPU_TSENS_INT_RAW_R {
+        SAR_COCPU_TSENS_INT_RAW_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - int from start"]
+    #[inline(always)]
+    pub fn sar_cocpu_start_int_raw(&self) -> SAR_COCPU_START_INT_RAW_R {
+        SAR_COCPU_START_INT_RAW_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - int from software"]
+    #[inline(always)]
+    pub fn sar_cocpu_sw_int_raw(&self) -> SAR_COCPU_SW_INT_RAW_R {
+        SAR_COCPU_SW_INT_RAW_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - int from super watch dog"]
+    #[inline(always)]
+    pub fn sar_cocpu_swd_int_raw(&self) -> SAR_COCPU_SWD_INT_RAW_R {
+        SAR_COCPU_SWD_INT_RAW_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - int from timeout done"]
+    #[inline(always)]
+    pub fn sar_cocpu_touch_timeout_int_raw(&self) -> SAR_COCPU_TOUCH_TIMEOUT_INT_RAW_R {
+        SAR_COCPU_TOUCH_TIMEOUT_INT_RAW_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 10 - int from approach loop done"]
+    #[inline(always)]
+    pub fn sar_cocpu_touch_approach_loop_done_int_raw(
+        &self,
+    ) -> SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_RAW_R {
+        SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_RAW_R::new(((self.bits >> 10) & 1) != 0)
+    }
+    #[doc = "Bit 11 - int from touch scan done"]
+    #[inline(always)]
+    pub fn sar_cocpu_touch_scan_done_int_raw(&self) -> SAR_COCPU_TOUCH_SCAN_DONE_INT_RAW_R {
+        SAR_COCPU_TOUCH_SCAN_DONE_INT_RAW_R::new(((self.bits >> 11) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_COCPU_INT_RAW")
+            .field(
+                "sar_cocpu_touch_done_int_raw",
+                &self.sar_cocpu_touch_done_int_raw(),
+            )
+            .field(
+                "sar_cocpu_touch_inactive_int_raw",
+                &self.sar_cocpu_touch_inactive_int_raw(),
+            )
+            .field(
+                "sar_cocpu_touch_active_int_raw",
+                &self.sar_cocpu_touch_active_int_raw(),
+            )
+            .field(
+                "sar_cocpu_saradc1_int_raw",
+                &self.sar_cocpu_saradc1_int_raw(),
+            )
+            .field(
+                "sar_cocpu_saradc2_int_raw",
+                &self.sar_cocpu_saradc2_int_raw(),
+            )
+            .field("sar_cocpu_tsens_int_raw", &self.sar_cocpu_tsens_int_raw())
+            .field("sar_cocpu_start_int_raw", &self.sar_cocpu_start_int_raw())
+            .field("sar_cocpu_sw_int_raw", &self.sar_cocpu_sw_int_raw())
+            .field("sar_cocpu_swd_int_raw", &self.sar_cocpu_swd_int_raw())
+            .field(
+                "sar_cocpu_touch_timeout_int_raw",
+                &self.sar_cocpu_touch_timeout_int_raw(),
+            )
+            .field(
+                "sar_cocpu_touch_approach_loop_done_int_raw",
+                &self.sar_cocpu_touch_approach_loop_done_int_raw(),
+            )
+            .field(
+                "sar_cocpu_touch_scan_done_int_raw",
+                &self.sar_cocpu_touch_scan_done_int_raw(),
+            )
+            .finish()
+    }
+}
+#[doc = "the interrupt raw of ulp\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_cocpu_int_raw::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_COCPU_INT_RAW_SPEC;
+impl crate::RegisterSpec for SAR_COCPU_INT_RAW_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_cocpu_int_raw::R`](R) reader structure"]
+impl crate::Readable for SAR_COCPU_INT_RAW_SPEC {}
+#[doc = "`reset()` method sets SAR_COCPU_INT_RAW to value 0"]
+impl crate::Resettable for SAR_COCPU_INT_RAW_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sens/sar_cocpu_int_st.rs

@@ -0,0 +1,138 @@
+#[doc = "Register `SAR_COCPU_INT_ST` reader"]
+pub type R = crate::R<SAR_COCPU_INT_ST_SPEC>;
+#[doc = "Field `SAR_COCPU_TOUCH_DONE_INT_ST` reader - int state of touch done"]
+pub type SAR_COCPU_TOUCH_DONE_INT_ST_R = crate::BitReader;
+#[doc = "Field `SAR_COCPU_TOUCH_INACTIVE_INT_ST` reader - int state of from touch inactive"]
+pub type SAR_COCPU_TOUCH_INACTIVE_INT_ST_R = crate::BitReader;
+#[doc = "Field `SAR_COCPU_TOUCH_ACTIVE_INT_ST` reader - int state of touch active"]
+pub type SAR_COCPU_TOUCH_ACTIVE_INT_ST_R = crate::BitReader;
+#[doc = "Field `SAR_COCPU_SARADC1_INT_ST` reader - int state of from saradc1"]
+pub type SAR_COCPU_SARADC1_INT_ST_R = crate::BitReader;
+#[doc = "Field `SAR_COCPU_SARADC2_INT_ST` reader - int state of from saradc2"]
+pub type SAR_COCPU_SARADC2_INT_ST_R = crate::BitReader;
+#[doc = "Field `SAR_COCPU_TSENS_INT_ST` reader - int state of tsens"]
+pub type SAR_COCPU_TSENS_INT_ST_R = crate::BitReader;
+#[doc = "Field `SAR_COCPU_START_INT_ST` reader - int state of start"]
+pub type SAR_COCPU_START_INT_ST_R = crate::BitReader;
+#[doc = "Field `SAR_COCPU_SW_INT_ST` reader - int state of software"]
+pub type SAR_COCPU_SW_INT_ST_R = crate::BitReader;
+#[doc = "Field `SAR_COCPU_SWD_INT_ST` reader - int state of super watch dog"]
+pub type SAR_COCPU_SWD_INT_ST_R = crate::BitReader;
+#[doc = "Field `SAR_COCPU_TOUCH_TIMEOUT_INT_ST` reader - int state of timeout done"]
+pub type SAR_COCPU_TOUCH_TIMEOUT_INT_ST_R = crate::BitReader;
+#[doc = "Field `SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ST` reader - int state of approach loop done"]
+pub type SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ST_R = crate::BitReader;
+#[doc = "Field `SAR_COCPU_TOUCH_SCAN_DONE_INT_ST` reader - int state of touch scan done"]
+pub type SAR_COCPU_TOUCH_SCAN_DONE_INT_ST_R = crate::BitReader;
+impl R {
+    #[doc = "Bit 0 - int state of touch done"]
+    #[inline(always)]
+    pub fn sar_cocpu_touch_done_int_st(&self) -> SAR_COCPU_TOUCH_DONE_INT_ST_R {
+        SAR_COCPU_TOUCH_DONE_INT_ST_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - int state of from touch inactive"]
+    #[inline(always)]
+    pub fn sar_cocpu_touch_inactive_int_st(&self) -> SAR_COCPU_TOUCH_INACTIVE_INT_ST_R {
+        SAR_COCPU_TOUCH_INACTIVE_INT_ST_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - int state of touch active"]
+    #[inline(always)]
+    pub fn sar_cocpu_touch_active_int_st(&self) -> SAR_COCPU_TOUCH_ACTIVE_INT_ST_R {
+        SAR_COCPU_TOUCH_ACTIVE_INT_ST_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - int state of from saradc1"]
+    #[inline(always)]
+    pub fn sar_cocpu_saradc1_int_st(&self) -> SAR_COCPU_SARADC1_INT_ST_R {
+        SAR_COCPU_SARADC1_INT_ST_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - int state of from saradc2"]
+    #[inline(always)]
+    pub fn sar_cocpu_saradc2_int_st(&self) -> SAR_COCPU_SARADC2_INT_ST_R {
+        SAR_COCPU_SARADC2_INT_ST_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - int state of tsens"]
+    #[inline(always)]
+    pub fn sar_cocpu_tsens_int_st(&self) -> SAR_COCPU_TSENS_INT_ST_R {
+        SAR_COCPU_TSENS_INT_ST_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - int state of start"]
+    #[inline(always)]
+    pub fn sar_cocpu_start_int_st(&self) -> SAR_COCPU_START_INT_ST_R {
+        SAR_COCPU_START_INT_ST_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - int state of software"]
+    #[inline(always)]
+    pub fn sar_cocpu_sw_int_st(&self) -> SAR_COCPU_SW_INT_ST_R {
+        SAR_COCPU_SW_INT_ST_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - int state of super watch dog"]
+    #[inline(always)]
+    pub fn sar_cocpu_swd_int_st(&self) -> SAR_COCPU_SWD_INT_ST_R {
+        SAR_COCPU_SWD_INT_ST_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - int state of timeout done"]
+    #[inline(always)]
+    pub fn sar_cocpu_touch_timeout_int_st(&self) -> SAR_COCPU_TOUCH_TIMEOUT_INT_ST_R {
+        SAR_COCPU_TOUCH_TIMEOUT_INT_ST_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 10 - int state of approach loop done"]
+    #[inline(always)]
+    pub fn sar_cocpu_touch_approach_loop_done_int_st(
+        &self,
+    ) -> SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ST_R {
+        SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ST_R::new(((self.bits >> 10) & 1) != 0)
+    }
+    #[doc = "Bit 11 - int state of touch scan done"]
+    #[inline(always)]
+    pub fn sar_cocpu_touch_scan_done_int_st(&self) -> SAR_COCPU_TOUCH_SCAN_DONE_INT_ST_R {
+        SAR_COCPU_TOUCH_SCAN_DONE_INT_ST_R::new(((self.bits >> 11) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_COCPU_INT_ST")
+            .field(
+                "sar_cocpu_touch_done_int_st",
+                &self.sar_cocpu_touch_done_int_st(),
+            )
+            .field(
+                "sar_cocpu_touch_inactive_int_st",
+                &self.sar_cocpu_touch_inactive_int_st(),
+            )
+            .field(
+                "sar_cocpu_touch_active_int_st",
+                &self.sar_cocpu_touch_active_int_st(),
+            )
+            .field("sar_cocpu_saradc1_int_st", &self.sar_cocpu_saradc1_int_st())
+            .field("sar_cocpu_saradc2_int_st", &self.sar_cocpu_saradc2_int_st())
+            .field("sar_cocpu_tsens_int_st", &self.sar_cocpu_tsens_int_st())
+            .field("sar_cocpu_start_int_st", &self.sar_cocpu_start_int_st())
+            .field("sar_cocpu_sw_int_st", &self.sar_cocpu_sw_int_st())
+            .field("sar_cocpu_swd_int_st", &self.sar_cocpu_swd_int_st())
+            .field(
+                "sar_cocpu_touch_timeout_int_st",
+                &self.sar_cocpu_touch_timeout_int_st(),
+            )
+            .field(
+                "sar_cocpu_touch_approach_loop_done_int_st",
+                &self.sar_cocpu_touch_approach_loop_done_int_st(),
+            )
+            .field(
+                "sar_cocpu_touch_scan_done_int_st",
+                &self.sar_cocpu_touch_scan_done_int_st(),
+            )
+            .finish()
+    }
+}
+#[doc = "the interrupt state of ulp\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_cocpu_int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_COCPU_INT_ST_SPEC;
+impl crate::RegisterSpec for SAR_COCPU_INT_ST_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_cocpu_int_st::R`](R) reader structure"]
+impl crate::Readable for SAR_COCPU_INT_ST_SPEC {}
+#[doc = "`reset()` method sets SAR_COCPU_INT_ST to value 0"]
+impl crate::Resettable for SAR_COCPU_INT_ST_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sens/sar_cocpu_state.rs

@@ -0,0 +1,79 @@
+#[doc = "Register `SAR_COCPU_STATE` reader"]
+pub type R = crate::R<SAR_COCPU_STATE_SPEC>;
+#[doc = "Register `SAR_COCPU_STATE` writer"]
+pub type W = crate::W<SAR_COCPU_STATE_SPEC>;
+#[doc = "Field `SAR_COCPU_DBG_TRIGGER` writer - trigger cocpu debug registers"]
+pub type SAR_COCPU_DBG_TRIGGER_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_COCPU_CLK_EN_ST` reader - check cocpu whether clk on"]
+pub type SAR_COCPU_CLK_EN_ST_R = crate::BitReader;
+#[doc = "Field `SAR_COCPU_RESET_N` reader - check cocpu whether in reset state"]
+pub type SAR_COCPU_RESET_N_R = crate::BitReader;
+#[doc = "Field `SAR_COCPU_EOI` reader - check cocpu whether in interrupt state"]
+pub type SAR_COCPU_EOI_R = crate::BitReader;
+#[doc = "Field `SAR_COCPU_TRAP` reader - check cocpu whether in trap state"]
+pub type SAR_COCPU_TRAP_R = crate::BitReader;
+#[doc = "Field `SAR_COCPU_EBREAK` reader - check cocpu whether in ebreak"]
+pub type SAR_COCPU_EBREAK_R = crate::BitReader;
+impl R {
+    #[doc = "Bit 26 - check cocpu whether clk on"]
+    #[inline(always)]
+    pub fn sar_cocpu_clk_en_st(&self) -> SAR_COCPU_CLK_EN_ST_R {
+        SAR_COCPU_CLK_EN_ST_R::new(((self.bits >> 26) & 1) != 0)
+    }
+    #[doc = "Bit 27 - check cocpu whether in reset state"]
+    #[inline(always)]
+    pub fn sar_cocpu_reset_n(&self) -> SAR_COCPU_RESET_N_R {
+        SAR_COCPU_RESET_N_R::new(((self.bits >> 27) & 1) != 0)
+    }
+    #[doc = "Bit 28 - check cocpu whether in interrupt state"]
+    #[inline(always)]
+    pub fn sar_cocpu_eoi(&self) -> SAR_COCPU_EOI_R {
+        SAR_COCPU_EOI_R::new(((self.bits >> 28) & 1) != 0)
+    }
+    #[doc = "Bit 29 - check cocpu whether in trap state"]
+    #[inline(always)]
+    pub fn sar_cocpu_trap(&self) -> SAR_COCPU_TRAP_R {
+        SAR_COCPU_TRAP_R::new(((self.bits >> 29) & 1) != 0)
+    }
+    #[doc = "Bit 30 - check cocpu whether in ebreak"]
+    #[inline(always)]
+    pub fn sar_cocpu_ebreak(&self) -> SAR_COCPU_EBREAK_R {
+        SAR_COCPU_EBREAK_R::new(((self.bits >> 30) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_COCPU_STATE")
+            .field("sar_cocpu_clk_en_st", &self.sar_cocpu_clk_en_st())
+            .field("sar_cocpu_reset_n", &self.sar_cocpu_reset_n())
+            .field("sar_cocpu_eoi", &self.sar_cocpu_eoi())
+            .field("sar_cocpu_trap", &self.sar_cocpu_trap())
+            .field("sar_cocpu_ebreak", &self.sar_cocpu_ebreak())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 25 - trigger cocpu debug registers"]
+    #[inline(always)]
+    pub fn sar_cocpu_dbg_trigger(&mut self) -> SAR_COCPU_DBG_TRIGGER_W<SAR_COCPU_STATE_SPEC> {
+        SAR_COCPU_DBG_TRIGGER_W::new(self, 25)
+    }
+}
+#[doc = "get cocpu status\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_cocpu_state::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_cocpu_state::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_COCPU_STATE_SPEC;
+impl crate::RegisterSpec for SAR_COCPU_STATE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_cocpu_state::R`](R) reader structure"]
+impl crate::Readable for SAR_COCPU_STATE_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sar_cocpu_state::W`](W) writer structure"]
+impl crate::Writable for SAR_COCPU_STATE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SAR_COCPU_STATE to value 0"]
+impl crate::Resettable for SAR_COCPU_STATE_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sens/sar_debug_conf.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `SAR_DEBUG_CONF` reader"]
+pub type R = crate::R<SAR_DEBUG_CONF_SPEC>;
+#[doc = "Register `SAR_DEBUG_CONF` writer"]
+pub type W = crate::W<SAR_DEBUG_CONF_SPEC>;
+#[doc = "Field `SAR_DEBUG_BIT_SEL` reader - no public"]
+pub type SAR_DEBUG_BIT_SEL_R = crate::FieldReader;
+#[doc = "Field `SAR_DEBUG_BIT_SEL` writer - no public"]
+pub type SAR_DEBUG_BIT_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
+impl R {
+    #[doc = "Bits 0:4 - no public"]
+    #[inline(always)]
+    pub fn sar_debug_bit_sel(&self) -> SAR_DEBUG_BIT_SEL_R {
+        SAR_DEBUG_BIT_SEL_R::new((self.bits & 0x1f) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_DEBUG_CONF")
+            .field("sar_debug_bit_sel", &self.sar_debug_bit_sel())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:4 - no public"]
+    #[inline(always)]
+    pub fn sar_debug_bit_sel(&mut self) -> SAR_DEBUG_BIT_SEL_W<SAR_DEBUG_CONF_SPEC> {
+        SAR_DEBUG_BIT_SEL_W::new(self, 0)
+    }
+}
+#[doc = "rtc peri debug configure\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_debug_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_debug_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_DEBUG_CONF_SPEC;
+impl crate::RegisterSpec for SAR_DEBUG_CONF_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_debug_conf::R`](R) reader structure"]
+impl crate::Readable for SAR_DEBUG_CONF_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sar_debug_conf::W`](W) writer structure"]
+impl crate::Writable for SAR_DEBUG_CONF_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SAR_DEBUG_CONF to value 0"]
+impl crate::Resettable for SAR_DEBUG_CONF_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sens/sar_hall_ctrl.rs

@@ -0,0 +1,92 @@
+#[doc = "Register `SAR_HALL_CTRL` reader"]
+pub type R = crate::R<SAR_HALL_CTRL_SPEC>;
+#[doc = "Register `SAR_HALL_CTRL` writer"]
+pub type W = crate::W<SAR_HALL_CTRL_SPEC>;
+#[doc = "Field `XPD_HALL` reader - Power on hall sensor and connect to VP and VN"]
+pub type XPD_HALL_R = crate::BitReader;
+#[doc = "Field `XPD_HALL` writer - Power on hall sensor and connect to VP and VN"]
+pub type XPD_HALL_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `XPD_HALL_FORCE` reader - 1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by FSM in ULP-coprocessor"]
+pub type XPD_HALL_FORCE_R = crate::BitReader;
+#[doc = "Field `XPD_HALL_FORCE` writer - 1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by FSM in ULP-coprocessor"]
+pub type XPD_HALL_FORCE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `HALL_PHASE` reader - Reverse phase of hall sensor"]
+pub type HALL_PHASE_R = crate::BitReader;
+#[doc = "Field `HALL_PHASE` writer - Reverse phase of hall sensor"]
+pub type HALL_PHASE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `HALL_PHASE_FORCE` reader - 1: HALL PHASE is controlled by SW 0: HALL PHASE is controlled by FSM in ULP-coprocessor"]
+pub type HALL_PHASE_FORCE_R = crate::BitReader;
+#[doc = "Field `HALL_PHASE_FORCE` writer - 1: HALL PHASE is controlled by SW 0: HALL PHASE is controlled by FSM in ULP-coprocessor"]
+pub type HALL_PHASE_FORCE_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 28 - Power on hall sensor and connect to VP and VN"]
+    #[inline(always)]
+    pub fn xpd_hall(&self) -> XPD_HALL_R {
+        XPD_HALL_R::new(((self.bits >> 28) & 1) != 0)
+    }
+    #[doc = "Bit 29 - 1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by FSM in ULP-coprocessor"]
+    #[inline(always)]
+    pub fn xpd_hall_force(&self) -> XPD_HALL_FORCE_R {
+        XPD_HALL_FORCE_R::new(((self.bits >> 29) & 1) != 0)
+    }
+    #[doc = "Bit 30 - Reverse phase of hall sensor"]
+    #[inline(always)]
+    pub fn hall_phase(&self) -> HALL_PHASE_R {
+        HALL_PHASE_R::new(((self.bits >> 30) & 1) != 0)
+    }
+    #[doc = "Bit 31 - 1: HALL PHASE is controlled by SW 0: HALL PHASE is controlled by FSM in ULP-coprocessor"]
+    #[inline(always)]
+    pub fn hall_phase_force(&self) -> HALL_PHASE_FORCE_R {
+        HALL_PHASE_FORCE_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_HALL_CTRL")
+            .field("xpd_hall", &self.xpd_hall())
+            .field("xpd_hall_force", &self.xpd_hall_force())
+            .field("hall_phase", &self.hall_phase())
+            .field("hall_phase_force", &self.hall_phase_force())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 28 - Power on hall sensor and connect to VP and VN"]
+    #[inline(always)]
+    pub fn xpd_hall(&mut self) -> XPD_HALL_W<SAR_HALL_CTRL_SPEC> {
+        XPD_HALL_W::new(self, 28)
+    }
+    #[doc = "Bit 29 - 1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by FSM in ULP-coprocessor"]
+    #[inline(always)]
+    pub fn xpd_hall_force(&mut self) -> XPD_HALL_FORCE_W<SAR_HALL_CTRL_SPEC> {
+        XPD_HALL_FORCE_W::new(self, 29)
+    }
+    #[doc = "Bit 30 - Reverse phase of hall sensor"]
+    #[inline(always)]
+    pub fn hall_phase(&mut self) -> HALL_PHASE_W<SAR_HALL_CTRL_SPEC> {
+        HALL_PHASE_W::new(self, 30)
+    }
+    #[doc = "Bit 31 - 1: HALL PHASE is controlled by SW 0: HALL PHASE is controlled by FSM in ULP-coprocessor"]
+    #[inline(always)]
+    pub fn hall_phase_force(&mut self) -> HALL_PHASE_FORCE_W<SAR_HALL_CTRL_SPEC> {
+        HALL_PHASE_FORCE_W::new(self, 31)
+    }
+}
+#[doc = "no public\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_hall_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_hall_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_HALL_CTRL_SPEC;
+impl crate::RegisterSpec for SAR_HALL_CTRL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_hall_ctrl::R`](R) reader structure"]
+impl crate::Readable for SAR_HALL_CTRL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sar_hall_ctrl::W`](W) writer structure"]
+impl crate::Writable for SAR_HALL_CTRL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SAR_HALL_CTRL to value 0xa000_0000"]
+impl crate::Resettable for SAR_HALL_CTRL_SPEC {
+    const RESET_VALUE: u32 = 0xa000_0000;
+}

vendor/esp32s3/src/sens/sar_i2c_ctrl.rs

@@ -0,0 +1,77 @@
+#[doc = "Register `SAR_I2C_CTRL` reader"]
+pub type R = crate::R<SAR_I2C_CTRL_SPEC>;
+#[doc = "Register `SAR_I2C_CTRL` writer"]
+pub type W = crate::W<SAR_I2C_CTRL_SPEC>;
+#[doc = "Field `SAR_I2C_CTRL` reader - I2C control data only active when reg_sar_i2c_start_force = 1"]
+pub type SAR_I2C_CTRL_R = crate::FieldReader<u32>;
+#[doc = "Field `SAR_I2C_CTRL` writer - I2C control data only active when reg_sar_i2c_start_force = 1"]
+pub type SAR_I2C_CTRL_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>;
+#[doc = "Field `SAR_I2C_START` reader - start I2C only active when reg_sar_i2c_start_force = 1"]
+pub type SAR_I2C_START_R = crate::BitReader;
+#[doc = "Field `SAR_I2C_START` writer - start I2C only active when reg_sar_i2c_start_force = 1"]
+pub type SAR_I2C_START_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_I2C_START_FORCE` reader - 1: I2C started by SW 0: I2C started by FSM"]
+pub type SAR_I2C_START_FORCE_R = crate::BitReader;
+#[doc = "Field `SAR_I2C_START_FORCE` writer - 1: I2C started by SW 0: I2C started by FSM"]
+pub type SAR_I2C_START_FORCE_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 0:27 - I2C control data only active when reg_sar_i2c_start_force = 1"]
+    #[inline(always)]
+    pub fn sar_i2c_ctrl(&self) -> SAR_I2C_CTRL_R {
+        SAR_I2C_CTRL_R::new(self.bits & 0x0fff_ffff)
+    }
+    #[doc = "Bit 28 - start I2C only active when reg_sar_i2c_start_force = 1"]
+    #[inline(always)]
+    pub fn sar_i2c_start(&self) -> SAR_I2C_START_R {
+        SAR_I2C_START_R::new(((self.bits >> 28) & 1) != 0)
+    }
+    #[doc = "Bit 29 - 1: I2C started by SW 0: I2C started by FSM"]
+    #[inline(always)]
+    pub fn sar_i2c_start_force(&self) -> SAR_I2C_START_FORCE_R {
+        SAR_I2C_START_FORCE_R::new(((self.bits >> 29) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_I2C_CTRL")
+            .field("sar_i2c_ctrl", &self.sar_i2c_ctrl())
+            .field("sar_i2c_start", &self.sar_i2c_start())
+            .field("sar_i2c_start_force", &self.sar_i2c_start_force())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:27 - I2C control data only active when reg_sar_i2c_start_force = 1"]
+    #[inline(always)]
+    pub fn sar_i2c_ctrl(&mut self) -> SAR_I2C_CTRL_W<SAR_I2C_CTRL_SPEC> {
+        SAR_I2C_CTRL_W::new(self, 0)
+    }
+    #[doc = "Bit 28 - start I2C only active when reg_sar_i2c_start_force = 1"]
+    #[inline(always)]
+    pub fn sar_i2c_start(&mut self) -> SAR_I2C_START_W<SAR_I2C_CTRL_SPEC> {
+        SAR_I2C_START_W::new(self, 28)
+    }
+    #[doc = "Bit 29 - 1: I2C started by SW 0: I2C started by FSM"]
+    #[inline(always)]
+    pub fn sar_i2c_start_force(&mut self) -> SAR_I2C_START_FORCE_W<SAR_I2C_CTRL_SPEC> {
+        SAR_I2C_START_FORCE_W::new(self, 29)
+    }
+}
+#[doc = "configure rtc i2c controller by sw\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_i2c_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_i2c_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_I2C_CTRL_SPEC;
+impl crate::RegisterSpec for SAR_I2C_CTRL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_i2c_ctrl::R`](R) reader structure"]
+impl crate::Readable for SAR_I2C_CTRL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sar_i2c_ctrl::W`](W) writer structure"]
+impl crate::Writable for SAR_I2C_CTRL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SAR_I2C_CTRL to value 0"]
+impl crate::Resettable for SAR_I2C_CTRL_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sens/sar_meas1_ctrl1.rs

@@ -0,0 +1,92 @@
+#[doc = "Register `SAR_MEAS1_CTRL1` reader"]
+pub type R = crate::R<SAR_MEAS1_CTRL1_SPEC>;
+#[doc = "Register `SAR_MEAS1_CTRL1` writer"]
+pub type W = crate::W<SAR_MEAS1_CTRL1_SPEC>;
+#[doc = "Field `FORCE_XPD_AMP` reader - no public"]
+pub type FORCE_XPD_AMP_R = crate::FieldReader;
+#[doc = "Field `FORCE_XPD_AMP` writer - no public"]
+pub type FORCE_XPD_AMP_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `AMP_RST_FB_FORCE` reader - no public"]
+pub type AMP_RST_FB_FORCE_R = crate::FieldReader;
+#[doc = "Field `AMP_RST_FB_FORCE` writer - no public"]
+pub type AMP_RST_FB_FORCE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `AMP_SHORT_REF_FORCE` reader - no public"]
+pub type AMP_SHORT_REF_FORCE_R = crate::FieldReader;
+#[doc = "Field `AMP_SHORT_REF_FORCE` writer - no public"]
+pub type AMP_SHORT_REF_FORCE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `AMP_SHORT_REF_GND_FORCE` reader - no public"]
+pub type AMP_SHORT_REF_GND_FORCE_R = crate::FieldReader;
+#[doc = "Field `AMP_SHORT_REF_GND_FORCE` writer - no public"]
+pub type AMP_SHORT_REF_GND_FORCE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+impl R {
+    #[doc = "Bits 24:25 - no public"]
+    #[inline(always)]
+    pub fn force_xpd_amp(&self) -> FORCE_XPD_AMP_R {
+        FORCE_XPD_AMP_R::new(((self.bits >> 24) & 3) as u8)
+    }
+    #[doc = "Bits 26:27 - no public"]
+    #[inline(always)]
+    pub fn amp_rst_fb_force(&self) -> AMP_RST_FB_FORCE_R {
+        AMP_RST_FB_FORCE_R::new(((self.bits >> 26) & 3) as u8)
+    }
+    #[doc = "Bits 28:29 - no public"]
+    #[inline(always)]
+    pub fn amp_short_ref_force(&self) -> AMP_SHORT_REF_FORCE_R {
+        AMP_SHORT_REF_FORCE_R::new(((self.bits >> 28) & 3) as u8)
+    }
+    #[doc = "Bits 30:31 - no public"]
+    #[inline(always)]
+    pub fn amp_short_ref_gnd_force(&self) -> AMP_SHORT_REF_GND_FORCE_R {
+        AMP_SHORT_REF_GND_FORCE_R::new(((self.bits >> 30) & 3) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_MEAS1_CTRL1")
+            .field("force_xpd_amp", &self.force_xpd_amp())
+            .field("amp_rst_fb_force", &self.amp_rst_fb_force())
+            .field("amp_short_ref_force", &self.amp_short_ref_force())
+            .field("amp_short_ref_gnd_force", &self.amp_short_ref_gnd_force())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 24:25 - no public"]
+    #[inline(always)]
+    pub fn force_xpd_amp(&mut self) -> FORCE_XPD_AMP_W<SAR_MEAS1_CTRL1_SPEC> {
+        FORCE_XPD_AMP_W::new(self, 24)
+    }
+    #[doc = "Bits 26:27 - no public"]
+    #[inline(always)]
+    pub fn amp_rst_fb_force(&mut self) -> AMP_RST_FB_FORCE_W<SAR_MEAS1_CTRL1_SPEC> {
+        AMP_RST_FB_FORCE_W::new(self, 26)
+    }
+    #[doc = "Bits 28:29 - no public"]
+    #[inline(always)]
+    pub fn amp_short_ref_force(&mut self) -> AMP_SHORT_REF_FORCE_W<SAR_MEAS1_CTRL1_SPEC> {
+        AMP_SHORT_REF_FORCE_W::new(self, 28)
+    }
+    #[doc = "Bits 30:31 - no public"]
+    #[inline(always)]
+    pub fn amp_short_ref_gnd_force(&mut self) -> AMP_SHORT_REF_GND_FORCE_W<SAR_MEAS1_CTRL1_SPEC> {
+        AMP_SHORT_REF_GND_FORCE_W::new(self, 30)
+    }
+}
+#[doc = "no public\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_meas1_ctrl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_meas1_ctrl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_MEAS1_CTRL1_SPEC;
+impl crate::RegisterSpec for SAR_MEAS1_CTRL1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_meas1_ctrl1::R`](R) reader structure"]
+impl crate::Readable for SAR_MEAS1_CTRL1_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sar_meas1_ctrl1::W`](W) writer structure"]
+impl crate::Writable for SAR_MEAS1_CTRL1_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SAR_MEAS1_CTRL1 to value 0"]
+impl crate::Resettable for SAR_MEAS1_CTRL1_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sens/sar_meas1_ctrl2.rs

@@ -0,0 +1,108 @@
+#[doc = "Register `SAR_MEAS1_CTRL2` reader"]
+pub type R = crate::R<SAR_MEAS1_CTRL2_SPEC>;
+#[doc = "Register `SAR_MEAS1_CTRL2` writer"]
+pub type W = crate::W<SAR_MEAS1_CTRL2_SPEC>;
+#[doc = "Field `MEAS1_DATA_SAR` reader - SAR ADC1 data"]
+pub type MEAS1_DATA_SAR_R = crate::FieldReader<u16>;
+#[doc = "Field `MEAS1_DONE_SAR` reader - SAR ADC1 conversion done indication"]
+pub type MEAS1_DONE_SAR_R = crate::BitReader;
+#[doc = "Field `MEAS1_START_SAR` reader - SAR ADC1 controller (in RTC) starts conversion"]
+pub type MEAS1_START_SAR_R = crate::BitReader;
+#[doc = "Field `MEAS1_START_SAR` writer - SAR ADC1 controller (in RTC) starts conversion"]
+pub type MEAS1_START_SAR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `MEAS1_START_FORCE` reader - 1: SAR ADC1 controller (in RTC) is started by SW"]
+pub type MEAS1_START_FORCE_R = crate::BitReader;
+#[doc = "Field `MEAS1_START_FORCE` writer - 1: SAR ADC1 controller (in RTC) is started by SW"]
+pub type MEAS1_START_FORCE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR1_EN_PAD` reader - SAR ADC1 pad enable bitmap"]
+pub type SAR1_EN_PAD_R = crate::FieldReader<u16>;
+#[doc = "Field `SAR1_EN_PAD` writer - SAR ADC1 pad enable bitmap"]
+pub type SAR1_EN_PAD_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
+#[doc = "Field `SAR1_EN_PAD_FORCE` reader - 1: SAR ADC1 pad enable bitmap is controlled by SW"]
+pub type SAR1_EN_PAD_FORCE_R = crate::BitReader;
+#[doc = "Field `SAR1_EN_PAD_FORCE` writer - 1: SAR ADC1 pad enable bitmap is controlled by SW"]
+pub type SAR1_EN_PAD_FORCE_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 0:15 - SAR ADC1 data"]
+    #[inline(always)]
+    pub fn meas1_data_sar(&self) -> MEAS1_DATA_SAR_R {
+        MEAS1_DATA_SAR_R::new((self.bits & 0xffff) as u16)
+    }
+    #[doc = "Bit 16 - SAR ADC1 conversion done indication"]
+    #[inline(always)]
+    pub fn meas1_done_sar(&self) -> MEAS1_DONE_SAR_R {
+        MEAS1_DONE_SAR_R::new(((self.bits >> 16) & 1) != 0)
+    }
+    #[doc = "Bit 17 - SAR ADC1 controller (in RTC) starts conversion"]
+    #[inline(always)]
+    pub fn meas1_start_sar(&self) -> MEAS1_START_SAR_R {
+        MEAS1_START_SAR_R::new(((self.bits >> 17) & 1) != 0)
+    }
+    #[doc = "Bit 18 - 1: SAR ADC1 controller (in RTC) is started by SW"]
+    #[inline(always)]
+    pub fn meas1_start_force(&self) -> MEAS1_START_FORCE_R {
+        MEAS1_START_FORCE_R::new(((self.bits >> 18) & 1) != 0)
+    }
+    #[doc = "Bits 19:30 - SAR ADC1 pad enable bitmap"]
+    #[inline(always)]
+    pub fn sar1_en_pad(&self) -> SAR1_EN_PAD_R {
+        SAR1_EN_PAD_R::new(((self.bits >> 19) & 0x0fff) as u16)
+    }
+    #[doc = "Bit 31 - 1: SAR ADC1 pad enable bitmap is controlled by SW"]
+    #[inline(always)]
+    pub fn sar1_en_pad_force(&self) -> SAR1_EN_PAD_FORCE_R {
+        SAR1_EN_PAD_FORCE_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_MEAS1_CTRL2")
+            .field("meas1_data_sar", &self.meas1_data_sar())
+            .field("meas1_done_sar", &self.meas1_done_sar())
+            .field("meas1_start_sar", &self.meas1_start_sar())
+            .field("meas1_start_force", &self.meas1_start_force())
+            .field("sar1_en_pad", &self.sar1_en_pad())
+            .field("sar1_en_pad_force", &self.sar1_en_pad_force())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 17 - SAR ADC1 controller (in RTC) starts conversion"]
+    #[inline(always)]
+    pub fn meas1_start_sar(&mut self) -> MEAS1_START_SAR_W<SAR_MEAS1_CTRL2_SPEC> {
+        MEAS1_START_SAR_W::new(self, 17)
+    }
+    #[doc = "Bit 18 - 1: SAR ADC1 controller (in RTC) is started by SW"]
+    #[inline(always)]
+    pub fn meas1_start_force(&mut self) -> MEAS1_START_FORCE_W<SAR_MEAS1_CTRL2_SPEC> {
+        MEAS1_START_FORCE_W::new(self, 18)
+    }
+    #[doc = "Bits 19:30 - SAR ADC1 pad enable bitmap"]
+    #[inline(always)]
+    pub fn sar1_en_pad(&mut self) -> SAR1_EN_PAD_W<SAR_MEAS1_CTRL2_SPEC> {
+        SAR1_EN_PAD_W::new(self, 19)
+    }
+    #[doc = "Bit 31 - 1: SAR ADC1 pad enable bitmap is controlled by SW"]
+    #[inline(always)]
+    pub fn sar1_en_pad_force(&mut self) -> SAR1_EN_PAD_FORCE_W<SAR_MEAS1_CTRL2_SPEC> {
+        SAR1_EN_PAD_FORCE_W::new(self, 31)
+    }
+}
+#[doc = "configure saradc1 controller\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_meas1_ctrl2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_meas1_ctrl2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_MEAS1_CTRL2_SPEC;
+impl crate::RegisterSpec for SAR_MEAS1_CTRL2_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_meas1_ctrl2::R`](R) reader structure"]
+impl crate::Readable for SAR_MEAS1_CTRL2_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sar_meas1_ctrl2::W`](W) writer structure"]
+impl crate::Writable for SAR_MEAS1_CTRL2_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SAR_MEAS1_CTRL2 to value 0"]
+impl crate::Resettable for SAR_MEAS1_CTRL2_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sens/sar_meas1_mux.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `SAR_MEAS1_MUX` reader"]
+pub type R = crate::R<SAR_MEAS1_MUX_SPEC>;
+#[doc = "Register `SAR_MEAS1_MUX` writer"]
+pub type W = crate::W<SAR_MEAS1_MUX_SPEC>;
+#[doc = "Field `SAR1_DIG_FORCE` reader - 1: SAR ADC1 controlled by DIG ADC1 CTRL"]
+pub type SAR1_DIG_FORCE_R = crate::BitReader;
+#[doc = "Field `SAR1_DIG_FORCE` writer - 1: SAR ADC1 controlled by DIG ADC1 CTRL"]
+pub type SAR1_DIG_FORCE_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 31 - 1: SAR ADC1 controlled by DIG ADC1 CTRL"]
+    #[inline(always)]
+    pub fn sar1_dig_force(&self) -> SAR1_DIG_FORCE_R {
+        SAR1_DIG_FORCE_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_MEAS1_MUX")
+            .field("sar1_dig_force", &self.sar1_dig_force())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 31 - 1: SAR ADC1 controlled by DIG ADC1 CTRL"]
+    #[inline(always)]
+    pub fn sar1_dig_force(&mut self) -> SAR1_DIG_FORCE_W<SAR_MEAS1_MUX_SPEC> {
+        SAR1_DIG_FORCE_W::new(self, 31)
+    }
+}
+#[doc = "configure saradc1 controller\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_meas1_mux::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_meas1_mux::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_MEAS1_MUX_SPEC;
+impl crate::RegisterSpec for SAR_MEAS1_MUX_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_meas1_mux::R`](R) reader structure"]
+impl crate::Readable for SAR_MEAS1_MUX_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sar_meas1_mux::W`](W) writer structure"]
+impl crate::Writable for SAR_MEAS1_MUX_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SAR_MEAS1_MUX to value 0"]
+impl crate::Resettable for SAR_MEAS1_MUX_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sens/sar_meas2_ctrl1.rs

@@ -0,0 +1,145 @@
+#[doc = "Register `SAR_MEAS2_CTRL1` reader"]
+pub type R = crate::R<SAR_MEAS2_CTRL1_SPEC>;
+#[doc = "Register `SAR_MEAS2_CTRL1` writer"]
+pub type W = crate::W<SAR_MEAS2_CTRL1_SPEC>;
+#[doc = "Field `SAR_SAR2_CNTL_STATE` reader - saradc2_cntl_fsm"]
+pub type SAR_SAR2_CNTL_STATE_R = crate::FieldReader;
+#[doc = "Field `SAR_SAR2_PWDET_CAL_EN` reader - rtc control pwdet enable"]
+pub type SAR_SAR2_PWDET_CAL_EN_R = crate::BitReader;
+#[doc = "Field `SAR_SAR2_PWDET_CAL_EN` writer - rtc control pwdet enable"]
+pub type SAR_SAR2_PWDET_CAL_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_SAR2_PKDET_CAL_EN` reader - rtc control pkdet enable"]
+pub type SAR_SAR2_PKDET_CAL_EN_R = crate::BitReader;
+#[doc = "Field `SAR_SAR2_PKDET_CAL_EN` writer - rtc control pkdet enable"]
+pub type SAR_SAR2_PKDET_CAL_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_SAR2_EN_TEST` reader - SAR2_EN_TEST"]
+pub type SAR_SAR2_EN_TEST_R = crate::BitReader;
+#[doc = "Field `SAR_SAR2_EN_TEST` writer - SAR2_EN_TEST"]
+pub type SAR_SAR2_EN_TEST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_SAR2_RSTB_FORCE` reader - no public"]
+pub type SAR_SAR2_RSTB_FORCE_R = crate::FieldReader;
+#[doc = "Field `SAR_SAR2_RSTB_FORCE` writer - no public"]
+pub type SAR_SAR2_RSTB_FORCE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `SAR_SAR2_STANDBY_WAIT` reader - no public"]
+pub type SAR_SAR2_STANDBY_WAIT_R = crate::FieldReader;
+#[doc = "Field `SAR_SAR2_STANDBY_WAIT` writer - no public"]
+pub type SAR_SAR2_STANDBY_WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+#[doc = "Field `SAR_SAR2_RSTB_WAIT` reader - no public"]
+pub type SAR_SAR2_RSTB_WAIT_R = crate::FieldReader;
+#[doc = "Field `SAR_SAR2_RSTB_WAIT` writer - no public"]
+pub type SAR_SAR2_RSTB_WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+#[doc = "Field `SAR_SAR2_XPD_WAIT` reader - no public"]
+pub type SAR_SAR2_XPD_WAIT_R = crate::FieldReader;
+#[doc = "Field `SAR_SAR2_XPD_WAIT` writer - no public"]
+pub type SAR_SAR2_XPD_WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+impl R {
+    #[doc = "Bits 0:2 - saradc2_cntl_fsm"]
+    #[inline(always)]
+    pub fn sar_sar2_cntl_state(&self) -> SAR_SAR2_CNTL_STATE_R {
+        SAR_SAR2_CNTL_STATE_R::new((self.bits & 7) as u8)
+    }
+    #[doc = "Bit 3 - rtc control pwdet enable"]
+    #[inline(always)]
+    pub fn sar_sar2_pwdet_cal_en(&self) -> SAR_SAR2_PWDET_CAL_EN_R {
+        SAR_SAR2_PWDET_CAL_EN_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - rtc control pkdet enable"]
+    #[inline(always)]
+    pub fn sar_sar2_pkdet_cal_en(&self) -> SAR_SAR2_PKDET_CAL_EN_R {
+        SAR_SAR2_PKDET_CAL_EN_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - SAR2_EN_TEST"]
+    #[inline(always)]
+    pub fn sar_sar2_en_test(&self) -> SAR_SAR2_EN_TEST_R {
+        SAR_SAR2_EN_TEST_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bits 6:7 - no public"]
+    #[inline(always)]
+    pub fn sar_sar2_rstb_force(&self) -> SAR_SAR2_RSTB_FORCE_R {
+        SAR_SAR2_RSTB_FORCE_R::new(((self.bits >> 6) & 3) as u8)
+    }
+    #[doc = "Bits 8:15 - no public"]
+    #[inline(always)]
+    pub fn sar_sar2_standby_wait(&self) -> SAR_SAR2_STANDBY_WAIT_R {
+        SAR_SAR2_STANDBY_WAIT_R::new(((self.bits >> 8) & 0xff) as u8)
+    }
+    #[doc = "Bits 16:23 - no public"]
+    #[inline(always)]
+    pub fn sar_sar2_rstb_wait(&self) -> SAR_SAR2_RSTB_WAIT_R {
+        SAR_SAR2_RSTB_WAIT_R::new(((self.bits >> 16) & 0xff) as u8)
+    }
+    #[doc = "Bits 24:31 - no public"]
+    #[inline(always)]
+    pub fn sar_sar2_xpd_wait(&self) -> SAR_SAR2_XPD_WAIT_R {
+        SAR_SAR2_XPD_WAIT_R::new(((self.bits >> 24) & 0xff) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_MEAS2_CTRL1")
+            .field("sar_sar2_cntl_state", &self.sar_sar2_cntl_state())
+            .field("sar_sar2_pwdet_cal_en", &self.sar_sar2_pwdet_cal_en())
+            .field("sar_sar2_pkdet_cal_en", &self.sar_sar2_pkdet_cal_en())
+            .field("sar_sar2_en_test", &self.sar_sar2_en_test())
+            .field("sar_sar2_rstb_force", &self.sar_sar2_rstb_force())
+            .field("sar_sar2_standby_wait", &self.sar_sar2_standby_wait())
+            .field("sar_sar2_rstb_wait", &self.sar_sar2_rstb_wait())
+            .field("sar_sar2_xpd_wait", &self.sar_sar2_xpd_wait())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 3 - rtc control pwdet enable"]
+    #[inline(always)]
+    pub fn sar_sar2_pwdet_cal_en(&mut self) -> SAR_SAR2_PWDET_CAL_EN_W<SAR_MEAS2_CTRL1_SPEC> {
+        SAR_SAR2_PWDET_CAL_EN_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - rtc control pkdet enable"]
+    #[inline(always)]
+    pub fn sar_sar2_pkdet_cal_en(&mut self) -> SAR_SAR2_PKDET_CAL_EN_W<SAR_MEAS2_CTRL1_SPEC> {
+        SAR_SAR2_PKDET_CAL_EN_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - SAR2_EN_TEST"]
+    #[inline(always)]
+    pub fn sar_sar2_en_test(&mut self) -> SAR_SAR2_EN_TEST_W<SAR_MEAS2_CTRL1_SPEC> {
+        SAR_SAR2_EN_TEST_W::new(self, 5)
+    }
+    #[doc = "Bits 6:7 - no public"]
+    #[inline(always)]
+    pub fn sar_sar2_rstb_force(&mut self) -> SAR_SAR2_RSTB_FORCE_W<SAR_MEAS2_CTRL1_SPEC> {
+        SAR_SAR2_RSTB_FORCE_W::new(self, 6)
+    }
+    #[doc = "Bits 8:15 - no public"]
+    #[inline(always)]
+    pub fn sar_sar2_standby_wait(&mut self) -> SAR_SAR2_STANDBY_WAIT_W<SAR_MEAS2_CTRL1_SPEC> {
+        SAR_SAR2_STANDBY_WAIT_W::new(self, 8)
+    }
+    #[doc = "Bits 16:23 - no public"]
+    #[inline(always)]
+    pub fn sar_sar2_rstb_wait(&mut self) -> SAR_SAR2_RSTB_WAIT_W<SAR_MEAS2_CTRL1_SPEC> {
+        SAR_SAR2_RSTB_WAIT_W::new(self, 16)
+    }
+    #[doc = "Bits 24:31 - no public"]
+    #[inline(always)]
+    pub fn sar_sar2_xpd_wait(&mut self) -> SAR_SAR2_XPD_WAIT_W<SAR_MEAS2_CTRL1_SPEC> {
+        SAR_SAR2_XPD_WAIT_W::new(self, 24)
+    }
+}
+#[doc = "configure saradc2 controller\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_meas2_ctrl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_meas2_ctrl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_MEAS2_CTRL1_SPEC;
+impl crate::RegisterSpec for SAR_MEAS2_CTRL1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_meas2_ctrl1::R`](R) reader structure"]
+impl crate::Readable for SAR_MEAS2_CTRL1_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sar_meas2_ctrl1::W`](W) writer structure"]
+impl crate::Writable for SAR_MEAS2_CTRL1_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SAR_MEAS2_CTRL1 to value 0x0702_0200"]
+impl crate::Resettable for SAR_MEAS2_CTRL1_SPEC {
+    const RESET_VALUE: u32 = 0x0702_0200;
+}

vendor/esp32s3/src/sens/sar_meas2_ctrl2.rs

@@ -0,0 +1,108 @@
+#[doc = "Register `SAR_MEAS2_CTRL2` reader"]
+pub type R = crate::R<SAR_MEAS2_CTRL2_SPEC>;
+#[doc = "Register `SAR_MEAS2_CTRL2` writer"]
+pub type W = crate::W<SAR_MEAS2_CTRL2_SPEC>;
+#[doc = "Field `MEAS2_DATA_SAR` reader - SAR ADC2 data"]
+pub type MEAS2_DATA_SAR_R = crate::FieldReader<u16>;
+#[doc = "Field `MEAS2_DONE_SAR` reader - SAR ADC2 conversion done indication"]
+pub type MEAS2_DONE_SAR_R = crate::BitReader;
+#[doc = "Field `MEAS2_START_SAR` reader - SAR ADC2 controller (in RTC) starts conversion"]
+pub type MEAS2_START_SAR_R = crate::BitReader;
+#[doc = "Field `MEAS2_START_SAR` writer - SAR ADC2 controller (in RTC) starts conversion"]
+pub type MEAS2_START_SAR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `MEAS2_START_FORCE` reader - 1: SAR ADC2 controller (in RTC) is started by SW"]
+pub type MEAS2_START_FORCE_R = crate::BitReader;
+#[doc = "Field `MEAS2_START_FORCE` writer - 1: SAR ADC2 controller (in RTC) is started by SW"]
+pub type MEAS2_START_FORCE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR2_EN_PAD` reader - SAR ADC2 pad enable bitmap"]
+pub type SAR2_EN_PAD_R = crate::FieldReader<u16>;
+#[doc = "Field `SAR2_EN_PAD` writer - SAR ADC2 pad enable bitmap"]
+pub type SAR2_EN_PAD_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
+#[doc = "Field `SAR2_EN_PAD_FORCE` reader - 1: SAR ADC2 pad enable bitmap is controlled by SW"]
+pub type SAR2_EN_PAD_FORCE_R = crate::BitReader;
+#[doc = "Field `SAR2_EN_PAD_FORCE` writer - 1: SAR ADC2 pad enable bitmap is controlled by SW"]
+pub type SAR2_EN_PAD_FORCE_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 0:15 - SAR ADC2 data"]
+    #[inline(always)]
+    pub fn meas2_data_sar(&self) -> MEAS2_DATA_SAR_R {
+        MEAS2_DATA_SAR_R::new((self.bits & 0xffff) as u16)
+    }
+    #[doc = "Bit 16 - SAR ADC2 conversion done indication"]
+    #[inline(always)]
+    pub fn meas2_done_sar(&self) -> MEAS2_DONE_SAR_R {
+        MEAS2_DONE_SAR_R::new(((self.bits >> 16) & 1) != 0)
+    }
+    #[doc = "Bit 17 - SAR ADC2 controller (in RTC) starts conversion"]
+    #[inline(always)]
+    pub fn meas2_start_sar(&self) -> MEAS2_START_SAR_R {
+        MEAS2_START_SAR_R::new(((self.bits >> 17) & 1) != 0)
+    }
+    #[doc = "Bit 18 - 1: SAR ADC2 controller (in RTC) is started by SW"]
+    #[inline(always)]
+    pub fn meas2_start_force(&self) -> MEAS2_START_FORCE_R {
+        MEAS2_START_FORCE_R::new(((self.bits >> 18) & 1) != 0)
+    }
+    #[doc = "Bits 19:30 - SAR ADC2 pad enable bitmap"]
+    #[inline(always)]
+    pub fn sar2_en_pad(&self) -> SAR2_EN_PAD_R {
+        SAR2_EN_PAD_R::new(((self.bits >> 19) & 0x0fff) as u16)
+    }
+    #[doc = "Bit 31 - 1: SAR ADC2 pad enable bitmap is controlled by SW"]
+    #[inline(always)]
+    pub fn sar2_en_pad_force(&self) -> SAR2_EN_PAD_FORCE_R {
+        SAR2_EN_PAD_FORCE_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_MEAS2_CTRL2")
+            .field("meas2_data_sar", &self.meas2_data_sar())
+            .field("meas2_done_sar", &self.meas2_done_sar())
+            .field("meas2_start_sar", &self.meas2_start_sar())
+            .field("meas2_start_force", &self.meas2_start_force())
+            .field("sar2_en_pad", &self.sar2_en_pad())
+            .field("sar2_en_pad_force", &self.sar2_en_pad_force())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 17 - SAR ADC2 controller (in RTC) starts conversion"]
+    #[inline(always)]
+    pub fn meas2_start_sar(&mut self) -> MEAS2_START_SAR_W<SAR_MEAS2_CTRL2_SPEC> {
+        MEAS2_START_SAR_W::new(self, 17)
+    }
+    #[doc = "Bit 18 - 1: SAR ADC2 controller (in RTC) is started by SW"]
+    #[inline(always)]
+    pub fn meas2_start_force(&mut self) -> MEAS2_START_FORCE_W<SAR_MEAS2_CTRL2_SPEC> {
+        MEAS2_START_FORCE_W::new(self, 18)
+    }
+    #[doc = "Bits 19:30 - SAR ADC2 pad enable bitmap"]
+    #[inline(always)]
+    pub fn sar2_en_pad(&mut self) -> SAR2_EN_PAD_W<SAR_MEAS2_CTRL2_SPEC> {
+        SAR2_EN_PAD_W::new(self, 19)
+    }
+    #[doc = "Bit 31 - 1: SAR ADC2 pad enable bitmap is controlled by SW"]
+    #[inline(always)]
+    pub fn sar2_en_pad_force(&mut self) -> SAR2_EN_PAD_FORCE_W<SAR_MEAS2_CTRL2_SPEC> {
+        SAR2_EN_PAD_FORCE_W::new(self, 31)
+    }
+}
+#[doc = "configure saradc2 controller\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_meas2_ctrl2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_meas2_ctrl2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_MEAS2_CTRL2_SPEC;
+impl crate::RegisterSpec for SAR_MEAS2_CTRL2_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_meas2_ctrl2::R`](R) reader structure"]
+impl crate::Readable for SAR_MEAS2_CTRL2_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sar_meas2_ctrl2::W`](W) writer structure"]
+impl crate::Writable for SAR_MEAS2_CTRL2_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SAR_MEAS2_CTRL2 to value 0"]
+impl crate::Resettable for SAR_MEAS2_CTRL2_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sens/sar_meas2_mux.rs

@@ -0,0 +1,62 @@
+#[doc = "Register `SAR_MEAS2_MUX` reader"]
+pub type R = crate::R<SAR_MEAS2_MUX_SPEC>;
+#[doc = "Register `SAR_MEAS2_MUX` writer"]
+pub type W = crate::W<SAR_MEAS2_MUX_SPEC>;
+#[doc = "Field `SAR2_PWDET_CCT` reader - SAR2_PWDET_CCT"]
+pub type SAR2_PWDET_CCT_R = crate::FieldReader;
+#[doc = "Field `SAR2_PWDET_CCT` writer - SAR2_PWDET_CCT"]
+pub type SAR2_PWDET_CCT_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `SAR2_RTC_FORCE` reader - in sleep, force to use rtc to control ADC"]
+pub type SAR2_RTC_FORCE_R = crate::BitReader;
+#[doc = "Field `SAR2_RTC_FORCE` writer - in sleep, force to use rtc to control ADC"]
+pub type SAR2_RTC_FORCE_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 28:30 - SAR2_PWDET_CCT"]
+    #[inline(always)]
+    pub fn sar2_pwdet_cct(&self) -> SAR2_PWDET_CCT_R {
+        SAR2_PWDET_CCT_R::new(((self.bits >> 28) & 7) as u8)
+    }
+    #[doc = "Bit 31 - in sleep, force to use rtc to control ADC"]
+    #[inline(always)]
+    pub fn sar2_rtc_force(&self) -> SAR2_RTC_FORCE_R {
+        SAR2_RTC_FORCE_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_MEAS2_MUX")
+            .field("sar2_pwdet_cct", &self.sar2_pwdet_cct())
+            .field("sar2_rtc_force", &self.sar2_rtc_force())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 28:30 - SAR2_PWDET_CCT"]
+    #[inline(always)]
+    pub fn sar2_pwdet_cct(&mut self) -> SAR2_PWDET_CCT_W<SAR_MEAS2_MUX_SPEC> {
+        SAR2_PWDET_CCT_W::new(self, 28)
+    }
+    #[doc = "Bit 31 - in sleep, force to use rtc to control ADC"]
+    #[inline(always)]
+    pub fn sar2_rtc_force(&mut self) -> SAR2_RTC_FORCE_W<SAR_MEAS2_MUX_SPEC> {
+        SAR2_RTC_FORCE_W::new(self, 31)
+    }
+}
+#[doc = "configure saradc2 controller\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_meas2_mux::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_meas2_mux::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_MEAS2_MUX_SPEC;
+impl crate::RegisterSpec for SAR_MEAS2_MUX_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_meas2_mux::R`](R) reader structure"]
+impl crate::Readable for SAR_MEAS2_MUX_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sar_meas2_mux::W`](W) writer structure"]
+impl crate::Writable for SAR_MEAS2_MUX_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SAR_MEAS2_MUX to value 0"]
+impl crate::Resettable for SAR_MEAS2_MUX_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sens/sar_nouse.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `SAR_NOUSE` reader"]
+pub type R = crate::R<SAR_NOUSE_SPEC>;
+#[doc = "Register `SAR_NOUSE` writer"]
+pub type W = crate::W<SAR_NOUSE_SPEC>;
+#[doc = "Field `SAR_NOUSE` reader - no public"]
+pub type SAR_NOUSE_R = crate::FieldReader<u32>;
+#[doc = "Field `SAR_NOUSE` writer - no public"]
+pub type SAR_NOUSE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - no public"]
+    #[inline(always)]
+    pub fn sar_nouse(&self) -> SAR_NOUSE_R {
+        SAR_NOUSE_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_NOUSE")
+            .field("sar_nouse", &self.sar_nouse())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - no public"]
+    #[inline(always)]
+    pub fn sar_nouse(&mut self) -> SAR_NOUSE_W<SAR_NOUSE_SPEC> {
+        SAR_NOUSE_W::new(self, 0)
+    }
+}
+#[doc = "no public\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_nouse::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_nouse::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_NOUSE_SPEC;
+impl crate::RegisterSpec for SAR_NOUSE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_nouse::R`](R) reader structure"]
+impl crate::Readable for SAR_NOUSE_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sar_nouse::W`](W) writer structure"]
+impl crate::Writable for SAR_NOUSE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SAR_NOUSE to value 0"]
+impl crate::Resettable for SAR_NOUSE_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sens/sar_peri_clk_gate_conf.rs

@@ -0,0 +1,92 @@
+#[doc = "Register `SAR_PERI_CLK_GATE_CONF` reader"]
+pub type R = crate::R<SAR_PERI_CLK_GATE_CONF_SPEC>;
+#[doc = "Register `SAR_PERI_CLK_GATE_CONF` writer"]
+pub type W = crate::W<SAR_PERI_CLK_GATE_CONF_SPEC>;
+#[doc = "Field `RTC_I2C_CLK_EN` reader - enable rtc i2c clock"]
+pub type RTC_I2C_CLK_EN_R = crate::BitReader;
+#[doc = "Field `RTC_I2C_CLK_EN` writer - enable rtc i2c clock"]
+pub type RTC_I2C_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TSENS_CLK_EN` reader - enable tsens clock"]
+pub type TSENS_CLK_EN_R = crate::BitReader;
+#[doc = "Field `TSENS_CLK_EN` writer - enable tsens clock"]
+pub type TSENS_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SARADC_CLK_EN` reader - enbale saradc clock"]
+pub type SARADC_CLK_EN_R = crate::BitReader;
+#[doc = "Field `SARADC_CLK_EN` writer - enbale saradc clock"]
+pub type SARADC_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `IOMUX_CLK_EN` reader - enable io_mux clock"]
+pub type IOMUX_CLK_EN_R = crate::BitReader;
+#[doc = "Field `IOMUX_CLK_EN` writer - enable io_mux clock"]
+pub type IOMUX_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 27 - enable rtc i2c clock"]
+    #[inline(always)]
+    pub fn rtc_i2c_clk_en(&self) -> RTC_I2C_CLK_EN_R {
+        RTC_I2C_CLK_EN_R::new(((self.bits >> 27) & 1) != 0)
+    }
+    #[doc = "Bit 29 - enable tsens clock"]
+    #[inline(always)]
+    pub fn tsens_clk_en(&self) -> TSENS_CLK_EN_R {
+        TSENS_CLK_EN_R::new(((self.bits >> 29) & 1) != 0)
+    }
+    #[doc = "Bit 30 - enbale saradc clock"]
+    #[inline(always)]
+    pub fn saradc_clk_en(&self) -> SARADC_CLK_EN_R {
+        SARADC_CLK_EN_R::new(((self.bits >> 30) & 1) != 0)
+    }
+    #[doc = "Bit 31 - enable io_mux clock"]
+    #[inline(always)]
+    pub fn iomux_clk_en(&self) -> IOMUX_CLK_EN_R {
+        IOMUX_CLK_EN_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_PERI_CLK_GATE_CONF")
+            .field("rtc_i2c_clk_en", &self.rtc_i2c_clk_en())
+            .field("tsens_clk_en", &self.tsens_clk_en())
+            .field("saradc_clk_en", &self.saradc_clk_en())
+            .field("iomux_clk_en", &self.iomux_clk_en())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 27 - enable rtc i2c clock"]
+    #[inline(always)]
+    pub fn rtc_i2c_clk_en(&mut self) -> RTC_I2C_CLK_EN_W<SAR_PERI_CLK_GATE_CONF_SPEC> {
+        RTC_I2C_CLK_EN_W::new(self, 27)
+    }
+    #[doc = "Bit 29 - enable tsens clock"]
+    #[inline(always)]
+    pub fn tsens_clk_en(&mut self) -> TSENS_CLK_EN_W<SAR_PERI_CLK_GATE_CONF_SPEC> {
+        TSENS_CLK_EN_W::new(self, 29)
+    }
+    #[doc = "Bit 30 - enbale saradc clock"]
+    #[inline(always)]
+    pub fn saradc_clk_en(&mut self) -> SARADC_CLK_EN_W<SAR_PERI_CLK_GATE_CONF_SPEC> {
+        SARADC_CLK_EN_W::new(self, 30)
+    }
+    #[doc = "Bit 31 - enable io_mux clock"]
+    #[inline(always)]
+    pub fn iomux_clk_en(&mut self) -> IOMUX_CLK_EN_W<SAR_PERI_CLK_GATE_CONF_SPEC> {
+        IOMUX_CLK_EN_W::new(self, 31)
+    }
+}
+#[doc = "the peri clock gate of rtc peri\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_peri_clk_gate_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_peri_clk_gate_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_PERI_CLK_GATE_CONF_SPEC;
+impl crate::RegisterSpec for SAR_PERI_CLK_GATE_CONF_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_peri_clk_gate_conf::R`](R) reader structure"]
+impl crate::Readable for SAR_PERI_CLK_GATE_CONF_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sar_peri_clk_gate_conf::W`](W) writer structure"]
+impl crate::Writable for SAR_PERI_CLK_GATE_CONF_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SAR_PERI_CLK_GATE_CONF to value 0"]
+impl crate::Resettable for SAR_PERI_CLK_GATE_CONF_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sens/sar_peri_reset_conf.rs

@@ -0,0 +1,92 @@
+#[doc = "Register `SAR_PERI_RESET_CONF` reader"]
+pub type R = crate::R<SAR_PERI_RESET_CONF_SPEC>;
+#[doc = "Register `SAR_PERI_RESET_CONF` writer"]
+pub type W = crate::W<SAR_PERI_RESET_CONF_SPEC>;
+#[doc = "Field `SAR_COCPU_RESET` reader - enable ulp-riscv reset"]
+pub type SAR_COCPU_RESET_R = crate::BitReader;
+#[doc = "Field `SAR_COCPU_RESET` writer - enable ulp-riscv reset"]
+pub type SAR_COCPU_RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_RTC_I2C_RESET` reader - Reserved."]
+pub type SAR_RTC_I2C_RESET_R = crate::BitReader;
+#[doc = "Field `SAR_RTC_I2C_RESET` writer - Reserved."]
+pub type SAR_RTC_I2C_RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_TSENS_RESET` reader - enbale saradc reset"]
+pub type SAR_TSENS_RESET_R = crate::BitReader;
+#[doc = "Field `SAR_TSENS_RESET` writer - enbale saradc reset"]
+pub type SAR_TSENS_RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_SARADC_RESET` reader - enable io_mux reset"]
+pub type SAR_SARADC_RESET_R = crate::BitReader;
+#[doc = "Field `SAR_SARADC_RESET` writer - enable io_mux reset"]
+pub type SAR_SARADC_RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 25 - enable ulp-riscv reset"]
+    #[inline(always)]
+    pub fn sar_cocpu_reset(&self) -> SAR_COCPU_RESET_R {
+        SAR_COCPU_RESET_R::new(((self.bits >> 25) & 1) != 0)
+    }
+    #[doc = "Bit 27 - Reserved."]
+    #[inline(always)]
+    pub fn sar_rtc_i2c_reset(&self) -> SAR_RTC_I2C_RESET_R {
+        SAR_RTC_I2C_RESET_R::new(((self.bits >> 27) & 1) != 0)
+    }
+    #[doc = "Bit 29 - enbale saradc reset"]
+    #[inline(always)]
+    pub fn sar_tsens_reset(&self) -> SAR_TSENS_RESET_R {
+        SAR_TSENS_RESET_R::new(((self.bits >> 29) & 1) != 0)
+    }
+    #[doc = "Bit 30 - enable io_mux reset"]
+    #[inline(always)]
+    pub fn sar_saradc_reset(&self) -> SAR_SARADC_RESET_R {
+        SAR_SARADC_RESET_R::new(((self.bits >> 30) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_PERI_RESET_CONF")
+            .field("sar_cocpu_reset", &self.sar_cocpu_reset())
+            .field("sar_rtc_i2c_reset", &self.sar_rtc_i2c_reset())
+            .field("sar_tsens_reset", &self.sar_tsens_reset())
+            .field("sar_saradc_reset", &self.sar_saradc_reset())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 25 - enable ulp-riscv reset"]
+    #[inline(always)]
+    pub fn sar_cocpu_reset(&mut self) -> SAR_COCPU_RESET_W<SAR_PERI_RESET_CONF_SPEC> {
+        SAR_COCPU_RESET_W::new(self, 25)
+    }
+    #[doc = "Bit 27 - Reserved."]
+    #[inline(always)]
+    pub fn sar_rtc_i2c_reset(&mut self) -> SAR_RTC_I2C_RESET_W<SAR_PERI_RESET_CONF_SPEC> {
+        SAR_RTC_I2C_RESET_W::new(self, 27)
+    }
+    #[doc = "Bit 29 - enbale saradc reset"]
+    #[inline(always)]
+    pub fn sar_tsens_reset(&mut self) -> SAR_TSENS_RESET_W<SAR_PERI_RESET_CONF_SPEC> {
+        SAR_TSENS_RESET_W::new(self, 29)
+    }
+    #[doc = "Bit 30 - enable io_mux reset"]
+    #[inline(always)]
+    pub fn sar_saradc_reset(&mut self) -> SAR_SARADC_RESET_W<SAR_PERI_RESET_CONF_SPEC> {
+        SAR_SARADC_RESET_W::new(self, 30)
+    }
+}
+#[doc = "the peri reset of rtc peri\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_peri_reset_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_peri_reset_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_PERI_RESET_CONF_SPEC;
+impl crate::RegisterSpec for SAR_PERI_RESET_CONF_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_peri_reset_conf::R`](R) reader structure"]
+impl crate::Readable for SAR_PERI_RESET_CONF_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sar_peri_reset_conf::W`](W) writer structure"]
+impl crate::Writable for SAR_PERI_RESET_CONF_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SAR_PERI_RESET_CONF to value 0"]
+impl crate::Resettable for SAR_PERI_RESET_CONF_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sens/sar_power_xpd_sar.rs

@@ -0,0 +1,62 @@
+#[doc = "Register `SAR_POWER_XPD_SAR` reader"]
+pub type R = crate::R<SAR_POWER_XPD_SAR_SPEC>;
+#[doc = "Register `SAR_POWER_XPD_SAR` writer"]
+pub type W = crate::W<SAR_POWER_XPD_SAR_SPEC>;
+#[doc = "Field `FORCE_XPD_SAR` reader - force power on/off saradc"]
+pub type FORCE_XPD_SAR_R = crate::FieldReader;
+#[doc = "Field `FORCE_XPD_SAR` writer - force power on/off saradc"]
+pub type FORCE_XPD_SAR_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `SARCLK_EN` reader - no public"]
+pub type SARCLK_EN_R = crate::BitReader;
+#[doc = "Field `SARCLK_EN` writer - no public"]
+pub type SARCLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 29:30 - force power on/off saradc"]
+    #[inline(always)]
+    pub fn force_xpd_sar(&self) -> FORCE_XPD_SAR_R {
+        FORCE_XPD_SAR_R::new(((self.bits >> 29) & 3) as u8)
+    }
+    #[doc = "Bit 31 - no public"]
+    #[inline(always)]
+    pub fn sarclk_en(&self) -> SARCLK_EN_R {
+        SARCLK_EN_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_POWER_XPD_SAR")
+            .field("force_xpd_sar", &self.force_xpd_sar())
+            .field("sarclk_en", &self.sarclk_en())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 29:30 - force power on/off saradc"]
+    #[inline(always)]
+    pub fn force_xpd_sar(&mut self) -> FORCE_XPD_SAR_W<SAR_POWER_XPD_SAR_SPEC> {
+        FORCE_XPD_SAR_W::new(self, 29)
+    }
+    #[doc = "Bit 31 - no public"]
+    #[inline(always)]
+    pub fn sarclk_en(&mut self) -> SARCLK_EN_W<SAR_POWER_XPD_SAR_SPEC> {
+        SARCLK_EN_W::new(self, 31)
+    }
+}
+#[doc = "configure power of saradc\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_power_xpd_sar::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_power_xpd_sar::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_POWER_XPD_SAR_SPEC;
+impl crate::RegisterSpec for SAR_POWER_XPD_SAR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_power_xpd_sar::R`](R) reader structure"]
+impl crate::Readable for SAR_POWER_XPD_SAR_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sar_power_xpd_sar::W`](W) writer structure"]
+impl crate::Writable for SAR_POWER_XPD_SAR_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SAR_POWER_XPD_SAR to value 0"]
+impl crate::Resettable for SAR_POWER_XPD_SAR_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sens/sar_reader1_ctrl.rs

@@ -0,0 +1,107 @@
+#[doc = "Register `SAR_READER1_CTRL` reader"]
+pub type R = crate::R<SAR_READER1_CTRL_SPEC>;
+#[doc = "Register `SAR_READER1_CTRL` writer"]
+pub type W = crate::W<SAR_READER1_CTRL_SPEC>;
+#[doc = "Field `SAR_SAR1_CLK_DIV` reader - clock divider"]
+pub type SAR_SAR1_CLK_DIV_R = crate::FieldReader;
+#[doc = "Field `SAR_SAR1_CLK_DIV` writer - clock divider"]
+pub type SAR_SAR1_CLK_DIV_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+#[doc = "Field `SAR_SAR1_CLK_GATED` reader - no public"]
+pub type SAR_SAR1_CLK_GATED_R = crate::BitReader;
+#[doc = "Field `SAR_SAR1_CLK_GATED` writer - no public"]
+pub type SAR_SAR1_CLK_GATED_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_SAR1_SAMPLE_NUM` reader - no public"]
+pub type SAR_SAR1_SAMPLE_NUM_R = crate::FieldReader;
+#[doc = "Field `SAR_SAR1_SAMPLE_NUM` writer - no public"]
+pub type SAR_SAR1_SAMPLE_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+#[doc = "Field `SAR_SAR1_DATA_INV` reader - Invert SAR ADC1 data"]
+pub type SAR_SAR1_DATA_INV_R = crate::BitReader;
+#[doc = "Field `SAR_SAR1_DATA_INV` writer - Invert SAR ADC1 data"]
+pub type SAR_SAR1_DATA_INV_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_SAR1_INT_EN` reader - enable saradc1 to send out interrupt"]
+pub type SAR_SAR1_INT_EN_R = crate::BitReader;
+#[doc = "Field `SAR_SAR1_INT_EN` writer - enable saradc1 to send out interrupt"]
+pub type SAR_SAR1_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 0:7 - clock divider"]
+    #[inline(always)]
+    pub fn sar_sar1_clk_div(&self) -> SAR_SAR1_CLK_DIV_R {
+        SAR_SAR1_CLK_DIV_R::new((self.bits & 0xff) as u8)
+    }
+    #[doc = "Bit 18 - no public"]
+    #[inline(always)]
+    pub fn sar_sar1_clk_gated(&self) -> SAR_SAR1_CLK_GATED_R {
+        SAR_SAR1_CLK_GATED_R::new(((self.bits >> 18) & 1) != 0)
+    }
+    #[doc = "Bits 19:26 - no public"]
+    #[inline(always)]
+    pub fn sar_sar1_sample_num(&self) -> SAR_SAR1_SAMPLE_NUM_R {
+        SAR_SAR1_SAMPLE_NUM_R::new(((self.bits >> 19) & 0xff) as u8)
+    }
+    #[doc = "Bit 28 - Invert SAR ADC1 data"]
+    #[inline(always)]
+    pub fn sar_sar1_data_inv(&self) -> SAR_SAR1_DATA_INV_R {
+        SAR_SAR1_DATA_INV_R::new(((self.bits >> 28) & 1) != 0)
+    }
+    #[doc = "Bit 29 - enable saradc1 to send out interrupt"]
+    #[inline(always)]
+    pub fn sar_sar1_int_en(&self) -> SAR_SAR1_INT_EN_R {
+        SAR_SAR1_INT_EN_R::new(((self.bits >> 29) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_READER1_CTRL")
+            .field("sar_sar1_clk_div", &self.sar_sar1_clk_div())
+            .field("sar_sar1_clk_gated", &self.sar_sar1_clk_gated())
+            .field("sar_sar1_sample_num", &self.sar_sar1_sample_num())
+            .field("sar_sar1_data_inv", &self.sar_sar1_data_inv())
+            .field("sar_sar1_int_en", &self.sar_sar1_int_en())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - clock divider"]
+    #[inline(always)]
+    pub fn sar_sar1_clk_div(&mut self) -> SAR_SAR1_CLK_DIV_W<SAR_READER1_CTRL_SPEC> {
+        SAR_SAR1_CLK_DIV_W::new(self, 0)
+    }
+    #[doc = "Bit 18 - no public"]
+    #[inline(always)]
+    pub fn sar_sar1_clk_gated(&mut self) -> SAR_SAR1_CLK_GATED_W<SAR_READER1_CTRL_SPEC> {
+        SAR_SAR1_CLK_GATED_W::new(self, 18)
+    }
+    #[doc = "Bits 19:26 - no public"]
+    #[inline(always)]
+    pub fn sar_sar1_sample_num(&mut self) -> SAR_SAR1_SAMPLE_NUM_W<SAR_READER1_CTRL_SPEC> {
+        SAR_SAR1_SAMPLE_NUM_W::new(self, 19)
+    }
+    #[doc = "Bit 28 - Invert SAR ADC1 data"]
+    #[inline(always)]
+    pub fn sar_sar1_data_inv(&mut self) -> SAR_SAR1_DATA_INV_W<SAR_READER1_CTRL_SPEC> {
+        SAR_SAR1_DATA_INV_W::new(self, 28)
+    }
+    #[doc = "Bit 29 - enable saradc1 to send out interrupt"]
+    #[inline(always)]
+    pub fn sar_sar1_int_en(&mut self) -> SAR_SAR1_INT_EN_W<SAR_READER1_CTRL_SPEC> {
+        SAR_SAR1_INT_EN_W::new(self, 29)
+    }
+}
+#[doc = "configure saradc1 reader\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_reader1_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_reader1_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_READER1_CTRL_SPEC;
+impl crate::RegisterSpec for SAR_READER1_CTRL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_reader1_ctrl::R`](R) reader structure"]
+impl crate::Readable for SAR_READER1_CTRL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sar_reader1_ctrl::W`](W) writer structure"]
+impl crate::Writable for SAR_READER1_CTRL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SAR_READER1_CTRL to value 0x2004_0002"]
+impl crate::Resettable for SAR_READER1_CTRL_SPEC {
+    const RESET_VALUE: u32 = 0x2004_0002;
+}

vendor/esp32s3/src/sens/sar_reader1_status.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `SAR_READER1_STATUS` reader"]
+pub type R = crate::R<SAR_READER1_STATUS_SPEC>;
+#[doc = "Field `SAR_SAR1_READER_STATUS` reader - get saradc1 reader controller status"]
+pub type SAR_SAR1_READER_STATUS_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - get saradc1 reader controller status"]
+    #[inline(always)]
+    pub fn sar_sar1_reader_status(&self) -> SAR_SAR1_READER_STATUS_R {
+        SAR_SAR1_READER_STATUS_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_READER1_STATUS")
+            .field("sar_sar1_reader_status", &self.sar_sar1_reader_status())
+            .finish()
+    }
+}
+#[doc = "get saradc1 reader controller status\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_reader1_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_READER1_STATUS_SPEC;
+impl crate::RegisterSpec for SAR_READER1_STATUS_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_reader1_status::R`](R) reader structure"]
+impl crate::Readable for SAR_READER1_STATUS_SPEC {}
+#[doc = "`reset()` method sets SAR_READER1_STATUS to value 0"]
+impl crate::Resettable for SAR_READER1_STATUS_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sens/sar_reader2_ctrl.rs

@@ -0,0 +1,122 @@
+#[doc = "Register `SAR_READER2_CTRL` reader"]
+pub type R = crate::R<SAR_READER2_CTRL_SPEC>;
+#[doc = "Register `SAR_READER2_CTRL` writer"]
+pub type W = crate::W<SAR_READER2_CTRL_SPEC>;
+#[doc = "Field `SAR_SAR2_CLK_DIV` reader - clock divider"]
+pub type SAR_SAR2_CLK_DIV_R = crate::FieldReader;
+#[doc = "Field `SAR_SAR2_CLK_DIV` writer - clock divider"]
+pub type SAR_SAR2_CLK_DIV_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+#[doc = "Field `SAR_SAR2_WAIT_ARB_CYCLE` reader - wait arbit stable after sar_done"]
+pub type SAR_SAR2_WAIT_ARB_CYCLE_R = crate::FieldReader;
+#[doc = "Field `SAR_SAR2_WAIT_ARB_CYCLE` writer - wait arbit stable after sar_done"]
+pub type SAR_SAR2_WAIT_ARB_CYCLE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `SAR_SAR2_CLK_GATED` reader - ******* Description ***********"]
+pub type SAR_SAR2_CLK_GATED_R = crate::BitReader;
+#[doc = "Field `SAR_SAR2_CLK_GATED` writer - ******* Description ***********"]
+pub type SAR_SAR2_CLK_GATED_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_SAR2_SAMPLE_NUM` reader - ******* Description ***********"]
+pub type SAR_SAR2_SAMPLE_NUM_R = crate::FieldReader;
+#[doc = "Field `SAR_SAR2_SAMPLE_NUM` writer - ******* Description ***********"]
+pub type SAR_SAR2_SAMPLE_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+#[doc = "Field `SAR_SAR2_DATA_INV` reader - Invert SAR ADC2 data"]
+pub type SAR_SAR2_DATA_INV_R = crate::BitReader;
+#[doc = "Field `SAR_SAR2_DATA_INV` writer - Invert SAR ADC2 data"]
+pub type SAR_SAR2_DATA_INV_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_SAR2_INT_EN` reader - enable saradc2 to send out interrupt"]
+pub type SAR_SAR2_INT_EN_R = crate::BitReader;
+#[doc = "Field `SAR_SAR2_INT_EN` writer - enable saradc2 to send out interrupt"]
+pub type SAR_SAR2_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 0:7 - clock divider"]
+    #[inline(always)]
+    pub fn sar_sar2_clk_div(&self) -> SAR_SAR2_CLK_DIV_R {
+        SAR_SAR2_CLK_DIV_R::new((self.bits & 0xff) as u8)
+    }
+    #[doc = "Bits 16:17 - wait arbit stable after sar_done"]
+    #[inline(always)]
+    pub fn sar_sar2_wait_arb_cycle(&self) -> SAR_SAR2_WAIT_ARB_CYCLE_R {
+        SAR_SAR2_WAIT_ARB_CYCLE_R::new(((self.bits >> 16) & 3) as u8)
+    }
+    #[doc = "Bit 18 - ******* Description ***********"]
+    #[inline(always)]
+    pub fn sar_sar2_clk_gated(&self) -> SAR_SAR2_CLK_GATED_R {
+        SAR_SAR2_CLK_GATED_R::new(((self.bits >> 18) & 1) != 0)
+    }
+    #[doc = "Bits 19:26 - ******* Description ***********"]
+    #[inline(always)]
+    pub fn sar_sar2_sample_num(&self) -> SAR_SAR2_SAMPLE_NUM_R {
+        SAR_SAR2_SAMPLE_NUM_R::new(((self.bits >> 19) & 0xff) as u8)
+    }
+    #[doc = "Bit 29 - Invert SAR ADC2 data"]
+    #[inline(always)]
+    pub fn sar_sar2_data_inv(&self) -> SAR_SAR2_DATA_INV_R {
+        SAR_SAR2_DATA_INV_R::new(((self.bits >> 29) & 1) != 0)
+    }
+    #[doc = "Bit 30 - enable saradc2 to send out interrupt"]
+    #[inline(always)]
+    pub fn sar_sar2_int_en(&self) -> SAR_SAR2_INT_EN_R {
+        SAR_SAR2_INT_EN_R::new(((self.bits >> 30) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_READER2_CTRL")
+            .field("sar_sar2_clk_div", &self.sar_sar2_clk_div())
+            .field("sar_sar2_wait_arb_cycle", &self.sar_sar2_wait_arb_cycle())
+            .field("sar_sar2_clk_gated", &self.sar_sar2_clk_gated())
+            .field("sar_sar2_sample_num", &self.sar_sar2_sample_num())
+            .field("sar_sar2_data_inv", &self.sar_sar2_data_inv())
+            .field("sar_sar2_int_en", &self.sar_sar2_int_en())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - clock divider"]
+    #[inline(always)]
+    pub fn sar_sar2_clk_div(&mut self) -> SAR_SAR2_CLK_DIV_W<SAR_READER2_CTRL_SPEC> {
+        SAR_SAR2_CLK_DIV_W::new(self, 0)
+    }
+    #[doc = "Bits 16:17 - wait arbit stable after sar_done"]
+    #[inline(always)]
+    pub fn sar_sar2_wait_arb_cycle(&mut self) -> SAR_SAR2_WAIT_ARB_CYCLE_W<SAR_READER2_CTRL_SPEC> {
+        SAR_SAR2_WAIT_ARB_CYCLE_W::new(self, 16)
+    }
+    #[doc = "Bit 18 - ******* Description ***********"]
+    #[inline(always)]
+    pub fn sar_sar2_clk_gated(&mut self) -> SAR_SAR2_CLK_GATED_W<SAR_READER2_CTRL_SPEC> {
+        SAR_SAR2_CLK_GATED_W::new(self, 18)
+    }
+    #[doc = "Bits 19:26 - ******* Description ***********"]
+    #[inline(always)]
+    pub fn sar_sar2_sample_num(&mut self) -> SAR_SAR2_SAMPLE_NUM_W<SAR_READER2_CTRL_SPEC> {
+        SAR_SAR2_SAMPLE_NUM_W::new(self, 19)
+    }
+    #[doc = "Bit 29 - Invert SAR ADC2 data"]
+    #[inline(always)]
+    pub fn sar_sar2_data_inv(&mut self) -> SAR_SAR2_DATA_INV_W<SAR_READER2_CTRL_SPEC> {
+        SAR_SAR2_DATA_INV_W::new(self, 29)
+    }
+    #[doc = "Bit 30 - enable saradc2 to send out interrupt"]
+    #[inline(always)]
+    pub fn sar_sar2_int_en(&mut self) -> SAR_SAR2_INT_EN_W<SAR_READER2_CTRL_SPEC> {
+        SAR_SAR2_INT_EN_W::new(self, 30)
+    }
+}
+#[doc = "configure saradc2 reader\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_reader2_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_reader2_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_READER2_CTRL_SPEC;
+impl crate::RegisterSpec for SAR_READER2_CTRL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_reader2_ctrl::R`](R) reader structure"]
+impl crate::Readable for SAR_READER2_CTRL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sar_reader2_ctrl::W`](W) writer structure"]
+impl crate::Writable for SAR_READER2_CTRL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SAR_READER2_CTRL to value 0x4005_0002"]
+impl crate::Resettable for SAR_READER2_CTRL_SPEC {
+    const RESET_VALUE: u32 = 0x4005_0002;
+}

vendor/esp32s3/src/sens/sar_reader2_status.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `SAR_READER2_STATUS` reader"]
+pub type R = crate::R<SAR_READER2_STATUS_SPEC>;
+#[doc = "Field `SAR_SAR2_READER_STATUS` reader - get saradc1 reader controller status"]
+pub type SAR_SAR2_READER_STATUS_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - get saradc1 reader controller status"]
+    #[inline(always)]
+    pub fn sar_sar2_reader_status(&self) -> SAR_SAR2_READER_STATUS_R {
+        SAR_SAR2_READER_STATUS_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_READER2_STATUS")
+            .field("sar_sar2_reader_status", &self.sar_sar2_reader_status())
+            .finish()
+    }
+}
+#[doc = "get saradc1 reader controller status\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_reader2_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_READER2_STATUS_SPEC;
+impl crate::RegisterSpec for SAR_READER2_STATUS_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_reader2_status::R`](R) reader structure"]
+impl crate::Readable for SAR_READER2_STATUS_SPEC {}
+#[doc = "`reset()` method sets SAR_READER2_STATUS to value 0"]
+impl crate::Resettable for SAR_READER2_STATUS_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sens/sar_sardate.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `SAR_SARDATE` reader"]
+pub type R = crate::R<SAR_SARDATE_SPEC>;
+#[doc = "Register `SAR_SARDATE` writer"]
+pub type W = crate::W<SAR_SARDATE_SPEC>;
+#[doc = "Field `SAR_DATE` reader - version"]
+pub type SAR_DATE_R = crate::FieldReader<u32>;
+#[doc = "Field `SAR_DATE` writer - version"]
+pub type SAR_DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>;
+impl R {
+    #[doc = "Bits 0:27 - version"]
+    #[inline(always)]
+    pub fn sar_date(&self) -> SAR_DATE_R {
+        SAR_DATE_R::new(self.bits & 0x0fff_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_SARDATE")
+            .field("sar_date", &self.sar_date())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:27 - version"]
+    #[inline(always)]
+    pub fn sar_date(&mut self) -> SAR_DATE_W<SAR_SARDATE_SPEC> {
+        SAR_DATE_W::new(self, 0)
+    }
+}
+#[doc = "version\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_sardate::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_sardate::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_SARDATE_SPEC;
+impl crate::RegisterSpec for SAR_SARDATE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_sardate::R`](R) reader structure"]
+impl crate::Readable for SAR_SARDATE_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sar_sardate::W`](W) writer structure"]
+impl crate::Writable for SAR_SARDATE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SAR_SARDATE to value 0x0210_1180"]
+impl crate::Resettable for SAR_SARDATE_SPEC {
+    const RESET_VALUE: u32 = 0x0210_1180;
+}

vendor/esp32s3/src/sens/sar_slave_addr1.rs

@@ -0,0 +1,70 @@
+#[doc = "Register `SAR_SLAVE_ADDR1` reader"]
+pub type R = crate::R<SAR_SLAVE_ADDR1_SPEC>;
+#[doc = "Register `SAR_SLAVE_ADDR1` writer"]
+pub type W = crate::W<SAR_SLAVE_ADDR1_SPEC>;
+#[doc = "Field `SAR_I2C_SLAVE_ADDR1` reader - configure i2c slave address1"]
+pub type SAR_I2C_SLAVE_ADDR1_R = crate::FieldReader<u16>;
+#[doc = "Field `SAR_I2C_SLAVE_ADDR1` writer - configure i2c slave address1"]
+pub type SAR_I2C_SLAVE_ADDR1_W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>;
+#[doc = "Field `SAR_I2C_SLAVE_ADDR0` reader - configure i2c slave address0"]
+pub type SAR_I2C_SLAVE_ADDR0_R = crate::FieldReader<u16>;
+#[doc = "Field `SAR_I2C_SLAVE_ADDR0` writer - configure i2c slave address0"]
+pub type SAR_I2C_SLAVE_ADDR0_W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>;
+#[doc = "Field `SAR_SARADC_MEAS_STATUS` reader - no public"]
+pub type SAR_SARADC_MEAS_STATUS_R = crate::FieldReader;
+impl R {
+    #[doc = "Bits 0:10 - configure i2c slave address1"]
+    #[inline(always)]
+    pub fn sar_i2c_slave_addr1(&self) -> SAR_I2C_SLAVE_ADDR1_R {
+        SAR_I2C_SLAVE_ADDR1_R::new((self.bits & 0x07ff) as u16)
+    }
+    #[doc = "Bits 11:21 - configure i2c slave address0"]
+    #[inline(always)]
+    pub fn sar_i2c_slave_addr0(&self) -> SAR_I2C_SLAVE_ADDR0_R {
+        SAR_I2C_SLAVE_ADDR0_R::new(((self.bits >> 11) & 0x07ff) as u16)
+    }
+    #[doc = "Bits 22:29 - no public"]
+    #[inline(always)]
+    pub fn sar_saradc_meas_status(&self) -> SAR_SARADC_MEAS_STATUS_R {
+        SAR_SARADC_MEAS_STATUS_R::new(((self.bits >> 22) & 0xff) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_SLAVE_ADDR1")
+            .field("sar_i2c_slave_addr1", &self.sar_i2c_slave_addr1())
+            .field("sar_i2c_slave_addr0", &self.sar_i2c_slave_addr0())
+            .field("sar_saradc_meas_status", &self.sar_saradc_meas_status())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:10 - configure i2c slave address1"]
+    #[inline(always)]
+    pub fn sar_i2c_slave_addr1(&mut self) -> SAR_I2C_SLAVE_ADDR1_W<SAR_SLAVE_ADDR1_SPEC> {
+        SAR_I2C_SLAVE_ADDR1_W::new(self, 0)
+    }
+    #[doc = "Bits 11:21 - configure i2c slave address0"]
+    #[inline(always)]
+    pub fn sar_i2c_slave_addr0(&mut self) -> SAR_I2C_SLAVE_ADDR0_W<SAR_SLAVE_ADDR1_SPEC> {
+        SAR_I2C_SLAVE_ADDR0_W::new(self, 11)
+    }
+}
+#[doc = "configure i2c slave address\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_slave_addr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_slave_addr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_SLAVE_ADDR1_SPEC;
+impl crate::RegisterSpec for SAR_SLAVE_ADDR1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_slave_addr1::R`](R) reader structure"]
+impl crate::Readable for SAR_SLAVE_ADDR1_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sar_slave_addr1::W`](W) writer structure"]
+impl crate::Writable for SAR_SLAVE_ADDR1_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SAR_SLAVE_ADDR1 to value 0"]
+impl crate::Resettable for SAR_SLAVE_ADDR1_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sens/sar_slave_addr2.rs

@@ -0,0 +1,62 @@
+#[doc = "Register `SAR_SLAVE_ADDR2` reader"]
+pub type R = crate::R<SAR_SLAVE_ADDR2_SPEC>;
+#[doc = "Register `SAR_SLAVE_ADDR2` writer"]
+pub type W = crate::W<SAR_SLAVE_ADDR2_SPEC>;
+#[doc = "Field `SAR_I2C_SLAVE_ADDR3` reader - configure i2c slave address3"]
+pub type SAR_I2C_SLAVE_ADDR3_R = crate::FieldReader<u16>;
+#[doc = "Field `SAR_I2C_SLAVE_ADDR3` writer - configure i2c slave address3"]
+pub type SAR_I2C_SLAVE_ADDR3_W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>;
+#[doc = "Field `SAR_I2C_SLAVE_ADDR2` reader - configure i2c slave address2"]
+pub type SAR_I2C_SLAVE_ADDR2_R = crate::FieldReader<u16>;
+#[doc = "Field `SAR_I2C_SLAVE_ADDR2` writer - configure i2c slave address2"]
+pub type SAR_I2C_SLAVE_ADDR2_W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>;
+impl R {
+    #[doc = "Bits 0:10 - configure i2c slave address3"]
+    #[inline(always)]
+    pub fn sar_i2c_slave_addr3(&self) -> SAR_I2C_SLAVE_ADDR3_R {
+        SAR_I2C_SLAVE_ADDR3_R::new((self.bits & 0x07ff) as u16)
+    }
+    #[doc = "Bits 11:21 - configure i2c slave address2"]
+    #[inline(always)]
+    pub fn sar_i2c_slave_addr2(&self) -> SAR_I2C_SLAVE_ADDR2_R {
+        SAR_I2C_SLAVE_ADDR2_R::new(((self.bits >> 11) & 0x07ff) as u16)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_SLAVE_ADDR2")
+            .field("sar_i2c_slave_addr3", &self.sar_i2c_slave_addr3())
+            .field("sar_i2c_slave_addr2", &self.sar_i2c_slave_addr2())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:10 - configure i2c slave address3"]
+    #[inline(always)]
+    pub fn sar_i2c_slave_addr3(&mut self) -> SAR_I2C_SLAVE_ADDR3_W<SAR_SLAVE_ADDR2_SPEC> {
+        SAR_I2C_SLAVE_ADDR3_W::new(self, 0)
+    }
+    #[doc = "Bits 11:21 - configure i2c slave address2"]
+    #[inline(always)]
+    pub fn sar_i2c_slave_addr2(&mut self) -> SAR_I2C_SLAVE_ADDR2_W<SAR_SLAVE_ADDR2_SPEC> {
+        SAR_I2C_SLAVE_ADDR2_W::new(self, 11)
+    }
+}
+#[doc = "configure i2c slave address\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_slave_addr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_slave_addr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_SLAVE_ADDR2_SPEC;
+impl crate::RegisterSpec for SAR_SLAVE_ADDR2_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_slave_addr2::R`](R) reader structure"]
+impl crate::Readable for SAR_SLAVE_ADDR2_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sar_slave_addr2::W`](W) writer structure"]
+impl crate::Writable for SAR_SLAVE_ADDR2_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SAR_SLAVE_ADDR2 to value 0"]
+impl crate::Resettable for SAR_SLAVE_ADDR2_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sens/sar_slave_addr3.rs

@@ -0,0 +1,62 @@
+#[doc = "Register `SAR_SLAVE_ADDR3` reader"]
+pub type R = crate::R<SAR_SLAVE_ADDR3_SPEC>;
+#[doc = "Register `SAR_SLAVE_ADDR3` writer"]
+pub type W = crate::W<SAR_SLAVE_ADDR3_SPEC>;
+#[doc = "Field `SAR_I2C_SLAVE_ADDR5` reader - configure i2c slave address5"]
+pub type SAR_I2C_SLAVE_ADDR5_R = crate::FieldReader<u16>;
+#[doc = "Field `SAR_I2C_SLAVE_ADDR5` writer - configure i2c slave address5"]
+pub type SAR_I2C_SLAVE_ADDR5_W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>;
+#[doc = "Field `SAR_I2C_SLAVE_ADDR4` reader - configure i2c slave address4"]
+pub type SAR_I2C_SLAVE_ADDR4_R = crate::FieldReader<u16>;
+#[doc = "Field `SAR_I2C_SLAVE_ADDR4` writer - configure i2c slave address4"]
+pub type SAR_I2C_SLAVE_ADDR4_W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>;
+impl R {
+    #[doc = "Bits 0:10 - configure i2c slave address5"]
+    #[inline(always)]
+    pub fn sar_i2c_slave_addr5(&self) -> SAR_I2C_SLAVE_ADDR5_R {
+        SAR_I2C_SLAVE_ADDR5_R::new((self.bits & 0x07ff) as u16)
+    }
+    #[doc = "Bits 11:21 - configure i2c slave address4"]
+    #[inline(always)]
+    pub fn sar_i2c_slave_addr4(&self) -> SAR_I2C_SLAVE_ADDR4_R {
+        SAR_I2C_SLAVE_ADDR4_R::new(((self.bits >> 11) & 0x07ff) as u16)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_SLAVE_ADDR3")
+            .field("sar_i2c_slave_addr5", &self.sar_i2c_slave_addr5())
+            .field("sar_i2c_slave_addr4", &self.sar_i2c_slave_addr4())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:10 - configure i2c slave address5"]
+    #[inline(always)]
+    pub fn sar_i2c_slave_addr5(&mut self) -> SAR_I2C_SLAVE_ADDR5_W<SAR_SLAVE_ADDR3_SPEC> {
+        SAR_I2C_SLAVE_ADDR5_W::new(self, 0)
+    }
+    #[doc = "Bits 11:21 - configure i2c slave address4"]
+    #[inline(always)]
+    pub fn sar_i2c_slave_addr4(&mut self) -> SAR_I2C_SLAVE_ADDR4_W<SAR_SLAVE_ADDR3_SPEC> {
+        SAR_I2C_SLAVE_ADDR4_W::new(self, 11)
+    }
+}
+#[doc = "configure i2c slave address\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_slave_addr3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_slave_addr3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_SLAVE_ADDR3_SPEC;
+impl crate::RegisterSpec for SAR_SLAVE_ADDR3_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_slave_addr3::R`](R) reader structure"]
+impl crate::Readable for SAR_SLAVE_ADDR3_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sar_slave_addr3::W`](W) writer structure"]
+impl crate::Writable for SAR_SLAVE_ADDR3_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SAR_SLAVE_ADDR3 to value 0"]
+impl crate::Resettable for SAR_SLAVE_ADDR3_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sens/sar_slave_addr4.rs

@@ -0,0 +1,62 @@
+#[doc = "Register `SAR_SLAVE_ADDR4` reader"]
+pub type R = crate::R<SAR_SLAVE_ADDR4_SPEC>;
+#[doc = "Register `SAR_SLAVE_ADDR4` writer"]
+pub type W = crate::W<SAR_SLAVE_ADDR4_SPEC>;
+#[doc = "Field `SAR_I2C_SLAVE_ADDR7` reader - configure i2c slave address7"]
+pub type SAR_I2C_SLAVE_ADDR7_R = crate::FieldReader<u16>;
+#[doc = "Field `SAR_I2C_SLAVE_ADDR7` writer - configure i2c slave address7"]
+pub type SAR_I2C_SLAVE_ADDR7_W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>;
+#[doc = "Field `SAR_I2C_SLAVE_ADDR6` reader - configure i2c slave address6"]
+pub type SAR_I2C_SLAVE_ADDR6_R = crate::FieldReader<u16>;
+#[doc = "Field `SAR_I2C_SLAVE_ADDR6` writer - configure i2c slave address6"]
+pub type SAR_I2C_SLAVE_ADDR6_W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>;
+impl R {
+    #[doc = "Bits 0:10 - configure i2c slave address7"]
+    #[inline(always)]
+    pub fn sar_i2c_slave_addr7(&self) -> SAR_I2C_SLAVE_ADDR7_R {
+        SAR_I2C_SLAVE_ADDR7_R::new((self.bits & 0x07ff) as u16)
+    }
+    #[doc = "Bits 11:21 - configure i2c slave address6"]
+    #[inline(always)]
+    pub fn sar_i2c_slave_addr6(&self) -> SAR_I2C_SLAVE_ADDR6_R {
+        SAR_I2C_SLAVE_ADDR6_R::new(((self.bits >> 11) & 0x07ff) as u16)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_SLAVE_ADDR4")
+            .field("sar_i2c_slave_addr7", &self.sar_i2c_slave_addr7())
+            .field("sar_i2c_slave_addr6", &self.sar_i2c_slave_addr6())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:10 - configure i2c slave address7"]
+    #[inline(always)]
+    pub fn sar_i2c_slave_addr7(&mut self) -> SAR_I2C_SLAVE_ADDR7_W<SAR_SLAVE_ADDR4_SPEC> {
+        SAR_I2C_SLAVE_ADDR7_W::new(self, 0)
+    }
+    #[doc = "Bits 11:21 - configure i2c slave address6"]
+    #[inline(always)]
+    pub fn sar_i2c_slave_addr6(&mut self) -> SAR_I2C_SLAVE_ADDR6_W<SAR_SLAVE_ADDR4_SPEC> {
+        SAR_I2C_SLAVE_ADDR6_W::new(self, 11)
+    }
+}
+#[doc = "configure i2c slave address\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_slave_addr4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_slave_addr4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_SLAVE_ADDR4_SPEC;
+impl crate::RegisterSpec for SAR_SLAVE_ADDR4_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_slave_addr4::R`](R) reader structure"]
+impl crate::Readable for SAR_SLAVE_ADDR4_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sar_slave_addr4::W`](W) writer structure"]
+impl crate::Writable for SAR_SLAVE_ADDR4_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SAR_SLAVE_ADDR4 to value 0"]
+impl crate::Resettable for SAR_SLAVE_ADDR4_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sens/sar_touch_chn_st.rs

@@ -0,0 +1,55 @@
+#[doc = "Register `SAR_TOUCH_CHN_ST` reader"]
+pub type R = crate::R<SAR_TOUCH_CHN_ST_SPEC>;
+#[doc = "Register `SAR_TOUCH_CHN_ST` writer"]
+pub type W = crate::W<SAR_TOUCH_CHN_ST_SPEC>;
+#[doc = "Field `SAR_TOUCH_PAD_ACTIVE` reader - touch active status"]
+pub type SAR_TOUCH_PAD_ACTIVE_R = crate::FieldReader<u16>;
+#[doc = "Field `SAR_TOUCH_CHANNEL_CLR` writer - Clear touch channel"]
+pub type SAR_TOUCH_CHANNEL_CLR_W<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>;
+#[doc = "Field `SAR_TOUCH_MEAS_DONE` reader - get touch meas done"]
+pub type SAR_TOUCH_MEAS_DONE_R = crate::BitReader;
+impl R {
+    #[doc = "Bits 0:14 - touch active status"]
+    #[inline(always)]
+    pub fn sar_touch_pad_active(&self) -> SAR_TOUCH_PAD_ACTIVE_R {
+        SAR_TOUCH_PAD_ACTIVE_R::new((self.bits & 0x7fff) as u16)
+    }
+    #[doc = "Bit 31 - get touch meas done"]
+    #[inline(always)]
+    pub fn sar_touch_meas_done(&self) -> SAR_TOUCH_MEAS_DONE_R {
+        SAR_TOUCH_MEAS_DONE_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_TOUCH_CHN_ST")
+            .field("sar_touch_pad_active", &self.sar_touch_pad_active())
+            .field("sar_touch_meas_done", &self.sar_touch_meas_done())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 15:29 - Clear touch channel"]
+    #[inline(always)]
+    pub fn sar_touch_channel_clr(&mut self) -> SAR_TOUCH_CHANNEL_CLR_W<SAR_TOUCH_CHN_ST_SPEC> {
+        SAR_TOUCH_CHANNEL_CLR_W::new(self, 15)
+    }
+}
+#[doc = "Get touch channel status\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_touch_chn_st::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_touch_chn_st::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_TOUCH_CHN_ST_SPEC;
+impl crate::RegisterSpec for SAR_TOUCH_CHN_ST_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_touch_chn_st::R`](R) reader structure"]
+impl crate::Readable for SAR_TOUCH_CHN_ST_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sar_touch_chn_st::W`](W) writer structure"]
+impl crate::Writable for SAR_TOUCH_CHN_ST_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SAR_TOUCH_CHN_ST to value 0"]
+impl crate::Resettable for SAR_TOUCH_CHN_ST_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sens/sar_touch_conf.rs

@@ -0,0 +1,130 @@
+#[doc = "Register `SAR_TOUCH_CONF` reader"]
+pub type R = crate::R<SAR_TOUCH_CONF_SPEC>;
+#[doc = "Register `SAR_TOUCH_CONF` writer"]
+pub type W = crate::W<SAR_TOUCH_CONF_SPEC>;
+#[doc = "Field `SAR_TOUCH_OUTEN` reader - touch controller output enable"]
+pub type SAR_TOUCH_OUTEN_R = crate::FieldReader<u16>;
+#[doc = "Field `SAR_TOUCH_OUTEN` writer - touch controller output enable"]
+pub type SAR_TOUCH_OUTEN_W<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>;
+#[doc = "Field `SAR_TOUCH_STATUS_CLR` writer - clear all touch active status"]
+pub type SAR_TOUCH_STATUS_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_TOUCH_DATA_SEL` reader - 3: smooth data 2: baseline 1,0: raw_data"]
+pub type SAR_TOUCH_DATA_SEL_R = crate::FieldReader;
+#[doc = "Field `SAR_TOUCH_DATA_SEL` writer - 3: smooth data 2: baseline 1,0: raw_data"]
+pub type SAR_TOUCH_DATA_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `SAR_TOUCH_DENOISE_END` reader - touch_denoise_done"]
+pub type SAR_TOUCH_DENOISE_END_R = crate::BitReader;
+#[doc = "Field `SAR_TOUCH_UNIT_END` reader - touch_unit_done"]
+pub type SAR_TOUCH_UNIT_END_R = crate::BitReader;
+#[doc = "Field `SAR_TOUCH_APPROACH_PAD2` reader - indicate which pad is approach pad2"]
+pub type SAR_TOUCH_APPROACH_PAD2_R = crate::FieldReader;
+#[doc = "Field `SAR_TOUCH_APPROACH_PAD2` writer - indicate which pad is approach pad2"]
+pub type SAR_TOUCH_APPROACH_PAD2_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `SAR_TOUCH_APPROACH_PAD1` reader - indicate which pad is approach pad1"]
+pub type SAR_TOUCH_APPROACH_PAD1_R = crate::FieldReader;
+#[doc = "Field `SAR_TOUCH_APPROACH_PAD1` writer - indicate which pad is approach pad1"]
+pub type SAR_TOUCH_APPROACH_PAD1_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `SAR_TOUCH_APPROACH_PAD0` reader - indicate which pad is approach pad0"]
+pub type SAR_TOUCH_APPROACH_PAD0_R = crate::FieldReader;
+#[doc = "Field `SAR_TOUCH_APPROACH_PAD0` writer - indicate which pad is approach pad0"]
+pub type SAR_TOUCH_APPROACH_PAD0_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+impl R {
+    #[doc = "Bits 0:14 - touch controller output enable"]
+    #[inline(always)]
+    pub fn sar_touch_outen(&self) -> SAR_TOUCH_OUTEN_R {
+        SAR_TOUCH_OUTEN_R::new((self.bits & 0x7fff) as u16)
+    }
+    #[doc = "Bits 16:17 - 3: smooth data 2: baseline 1,0: raw_data"]
+    #[inline(always)]
+    pub fn sar_touch_data_sel(&self) -> SAR_TOUCH_DATA_SEL_R {
+        SAR_TOUCH_DATA_SEL_R::new(((self.bits >> 16) & 3) as u8)
+    }
+    #[doc = "Bit 18 - touch_denoise_done"]
+    #[inline(always)]
+    pub fn sar_touch_denoise_end(&self) -> SAR_TOUCH_DENOISE_END_R {
+        SAR_TOUCH_DENOISE_END_R::new(((self.bits >> 18) & 1) != 0)
+    }
+    #[doc = "Bit 19 - touch_unit_done"]
+    #[inline(always)]
+    pub fn sar_touch_unit_end(&self) -> SAR_TOUCH_UNIT_END_R {
+        SAR_TOUCH_UNIT_END_R::new(((self.bits >> 19) & 1) != 0)
+    }
+    #[doc = "Bits 20:23 - indicate which pad is approach pad2"]
+    #[inline(always)]
+    pub fn sar_touch_approach_pad2(&self) -> SAR_TOUCH_APPROACH_PAD2_R {
+        SAR_TOUCH_APPROACH_PAD2_R::new(((self.bits >> 20) & 0x0f) as u8)
+    }
+    #[doc = "Bits 24:27 - indicate which pad is approach pad1"]
+    #[inline(always)]
+    pub fn sar_touch_approach_pad1(&self) -> SAR_TOUCH_APPROACH_PAD1_R {
+        SAR_TOUCH_APPROACH_PAD1_R::new(((self.bits >> 24) & 0x0f) as u8)
+    }
+    #[doc = "Bits 28:31 - indicate which pad is approach pad0"]
+    #[inline(always)]
+    pub fn sar_touch_approach_pad0(&self) -> SAR_TOUCH_APPROACH_PAD0_R {
+        SAR_TOUCH_APPROACH_PAD0_R::new(((self.bits >> 28) & 0x0f) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_TOUCH_CONF")
+            .field("sar_touch_outen", &self.sar_touch_outen())
+            .field("sar_touch_data_sel", &self.sar_touch_data_sel())
+            .field("sar_touch_denoise_end", &self.sar_touch_denoise_end())
+            .field("sar_touch_unit_end", &self.sar_touch_unit_end())
+            .field("sar_touch_approach_pad2", &self.sar_touch_approach_pad2())
+            .field("sar_touch_approach_pad1", &self.sar_touch_approach_pad1())
+            .field("sar_touch_approach_pad0", &self.sar_touch_approach_pad0())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:14 - touch controller output enable"]
+    #[inline(always)]
+    pub fn sar_touch_outen(&mut self) -> SAR_TOUCH_OUTEN_W<SAR_TOUCH_CONF_SPEC> {
+        SAR_TOUCH_OUTEN_W::new(self, 0)
+    }
+    #[doc = "Bit 15 - clear all touch active status"]
+    #[inline(always)]
+    pub fn sar_touch_status_clr(&mut self) -> SAR_TOUCH_STATUS_CLR_W<SAR_TOUCH_CONF_SPEC> {
+        SAR_TOUCH_STATUS_CLR_W::new(self, 15)
+    }
+    #[doc = "Bits 16:17 - 3: smooth data 2: baseline 1,0: raw_data"]
+    #[inline(always)]
+    pub fn sar_touch_data_sel(&mut self) -> SAR_TOUCH_DATA_SEL_W<SAR_TOUCH_CONF_SPEC> {
+        SAR_TOUCH_DATA_SEL_W::new(self, 16)
+    }
+    #[doc = "Bits 20:23 - indicate which pad is approach pad2"]
+    #[inline(always)]
+    pub fn sar_touch_approach_pad2(&mut self) -> SAR_TOUCH_APPROACH_PAD2_W<SAR_TOUCH_CONF_SPEC> {
+        SAR_TOUCH_APPROACH_PAD2_W::new(self, 20)
+    }
+    #[doc = "Bits 24:27 - indicate which pad is approach pad1"]
+    #[inline(always)]
+    pub fn sar_touch_approach_pad1(&mut self) -> SAR_TOUCH_APPROACH_PAD1_W<SAR_TOUCH_CONF_SPEC> {
+        SAR_TOUCH_APPROACH_PAD1_W::new(self, 24)
+    }
+    #[doc = "Bits 28:31 - indicate which pad is approach pad0"]
+    #[inline(always)]
+    pub fn sar_touch_approach_pad0(&mut self) -> SAR_TOUCH_APPROACH_PAD0_W<SAR_TOUCH_CONF_SPEC> {
+        SAR_TOUCH_APPROACH_PAD0_W::new(self, 28)
+    }
+}
+#[doc = "configure touch controller\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_touch_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_touch_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_TOUCH_CONF_SPEC;
+impl crate::RegisterSpec for SAR_TOUCH_CONF_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_touch_conf::R`](R) reader structure"]
+impl crate::Readable for SAR_TOUCH_CONF_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sar_touch_conf::W`](W) writer structure"]
+impl crate::Writable for SAR_TOUCH_CONF_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SAR_TOUCH_CONF to value 0xfff0_7fff"]
+impl crate::Resettable for SAR_TOUCH_CONF_SPEC {
+    const RESET_VALUE: u32 = 0xfff0_7fff;
+}

vendor/esp32s3/src/sens/sar_touch_denoise.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `SAR_TOUCH_DENOISE` reader"]
+pub type R = crate::R<SAR_TOUCH_DENOISE_SPEC>;
+#[doc = "Field `DATA` reader - configure touch controller"]
+pub type DATA_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:21 - configure touch controller"]
+    #[inline(always)]
+    pub fn data(&self) -> DATA_R {
+        DATA_R::new(self.bits & 0x003f_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_TOUCH_DENOISE")
+            .field("data", &self.data())
+            .finish()
+    }
+}
+#[doc = "configure touch controller\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_touch_denoise::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_TOUCH_DENOISE_SPEC;
+impl crate::RegisterSpec for SAR_TOUCH_DENOISE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_touch_denoise::R`](R) reader structure"]
+impl crate::Readable for SAR_TOUCH_DENOISE_SPEC {}
+#[doc = "`reset()` method sets SAR_TOUCH_DENOISE to value 0"]
+impl crate::Resettable for SAR_TOUCH_DENOISE_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sens/sar_touch_status0.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `SAR_TOUCH_STATUS0` reader"]
+pub type R = crate::R<SAR_TOUCH_STATUS0_SPEC>;
+#[doc = "Field `SAR_TOUCH_SCAN_CURR` reader - current sample channel"]
+pub type SAR_TOUCH_SCAN_CURR_R = crate::FieldReader;
+impl R {
+    #[doc = "Bits 22:25 - current sample channel"]
+    #[inline(always)]
+    pub fn sar_touch_scan_curr(&self) -> SAR_TOUCH_SCAN_CURR_R {
+        SAR_TOUCH_SCAN_CURR_R::new(((self.bits >> 22) & 0x0f) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_TOUCH_STATUS0")
+            .field("sar_touch_scan_curr", &self.sar_touch_scan_curr())
+            .finish()
+    }
+}
+#[doc = "get touch scan status\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_touch_status0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_TOUCH_STATUS0_SPEC;
+impl crate::RegisterSpec for SAR_TOUCH_STATUS0_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_touch_status0::R`](R) reader structure"]
+impl crate::Readable for SAR_TOUCH_STATUS0_SPEC {}
+#[doc = "`reset()` method sets SAR_TOUCH_STATUS0 to value 0"]
+impl crate::Resettable for SAR_TOUCH_STATUS0_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sens/sar_touch_status1.rs

@@ -0,0 +1,38 @@
+#[doc = "Register `SAR_TOUCH_STATUS1` reader"]
+pub type R = crate::R<SAR_TOUCH_STATUS1_SPEC>;
+#[doc = "Field `SAR_TOUCH_PAD1_DATA` reader - touch data debounce of touch pad 1"]
+pub type SAR_TOUCH_PAD1_DATA_R = crate::FieldReader<u32>;
+#[doc = "Field `SAR_TOUCH_PAD1_DEBOUNCE` reader - touch current debounce of touch pad 1"]
+pub type SAR_TOUCH_PAD1_DEBOUNCE_R = crate::FieldReader;
+impl R {
+    #[doc = "Bits 0:21 - touch data debounce of touch pad 1"]
+    #[inline(always)]
+    pub fn sar_touch_pad1_data(&self) -> SAR_TOUCH_PAD1_DATA_R {
+        SAR_TOUCH_PAD1_DATA_R::new(self.bits & 0x003f_ffff)
+    }
+    #[doc = "Bits 29:31 - touch current debounce of touch pad 1"]
+    #[inline(always)]
+    pub fn sar_touch_pad1_debounce(&self) -> SAR_TOUCH_PAD1_DEBOUNCE_R {
+        SAR_TOUCH_PAD1_DEBOUNCE_R::new(((self.bits >> 29) & 7) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_TOUCH_STATUS1")
+            .field("sar_touch_pad1_data", &self.sar_touch_pad1_data())
+            .field("sar_touch_pad1_debounce", &self.sar_touch_pad1_debounce())
+            .finish()
+    }
+}
+#[doc = "touch channel status of touch pad 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_touch_status1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_TOUCH_STATUS1_SPEC;
+impl crate::RegisterSpec for SAR_TOUCH_STATUS1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_touch_status1::R`](R) reader structure"]
+impl crate::Readable for SAR_TOUCH_STATUS1_SPEC {}
+#[doc = "`reset()` method sets SAR_TOUCH_STATUS1 to value 0"]
+impl crate::Resettable for SAR_TOUCH_STATUS1_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sens/sar_touch_status10.rs

@@ -0,0 +1,38 @@
+#[doc = "Register `SAR_TOUCH_STATUS10` reader"]
+pub type R = crate::R<SAR_TOUCH_STATUS10_SPEC>;
+#[doc = "Field `SAR_TOUCH_PAD10_DATA` reader - touch data debounce of touch pad 10"]
+pub type SAR_TOUCH_PAD10_DATA_R = crate::FieldReader<u32>;
+#[doc = "Field `SAR_TOUCH_PAD10_DEBOUNCE` reader - touch current debounce of touch pad 10"]
+pub type SAR_TOUCH_PAD10_DEBOUNCE_R = crate::FieldReader;
+impl R {
+    #[doc = "Bits 0:21 - touch data debounce of touch pad 10"]
+    #[inline(always)]
+    pub fn sar_touch_pad10_data(&self) -> SAR_TOUCH_PAD10_DATA_R {
+        SAR_TOUCH_PAD10_DATA_R::new(self.bits & 0x003f_ffff)
+    }
+    #[doc = "Bits 29:31 - touch current debounce of touch pad 10"]
+    #[inline(always)]
+    pub fn sar_touch_pad10_debounce(&self) -> SAR_TOUCH_PAD10_DEBOUNCE_R {
+        SAR_TOUCH_PAD10_DEBOUNCE_R::new(((self.bits >> 29) & 7) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_TOUCH_STATUS10")
+            .field("sar_touch_pad10_data", &self.sar_touch_pad10_data())
+            .field("sar_touch_pad10_debounce", &self.sar_touch_pad10_debounce())
+            .finish()
+    }
+}
+#[doc = "touch channel status of touch pad 10\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_touch_status10::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_TOUCH_STATUS10_SPEC;
+impl crate::RegisterSpec for SAR_TOUCH_STATUS10_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_touch_status10::R`](R) reader structure"]
+impl crate::Readable for SAR_TOUCH_STATUS10_SPEC {}
+#[doc = "`reset()` method sets SAR_TOUCH_STATUS10 to value 0"]
+impl crate::Resettable for SAR_TOUCH_STATUS10_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sens/sar_touch_status11.rs

@@ -0,0 +1,38 @@
+#[doc = "Register `SAR_TOUCH_STATUS11` reader"]
+pub type R = crate::R<SAR_TOUCH_STATUS11_SPEC>;
+#[doc = "Field `SAR_TOUCH_PAD11_DATA` reader - touch data debounce of touch pad 11"]
+pub type SAR_TOUCH_PAD11_DATA_R = crate::FieldReader<u32>;
+#[doc = "Field `SAR_TOUCH_PAD11_DEBOUNCE` reader - touch current debounce of touch pad 11"]
+pub type SAR_TOUCH_PAD11_DEBOUNCE_R = crate::FieldReader;
+impl R {
+    #[doc = "Bits 0:21 - touch data debounce of touch pad 11"]
+    #[inline(always)]
+    pub fn sar_touch_pad11_data(&self) -> SAR_TOUCH_PAD11_DATA_R {
+        SAR_TOUCH_PAD11_DATA_R::new(self.bits & 0x003f_ffff)
+    }
+    #[doc = "Bits 29:31 - touch current debounce of touch pad 11"]
+    #[inline(always)]
+    pub fn sar_touch_pad11_debounce(&self) -> SAR_TOUCH_PAD11_DEBOUNCE_R {
+        SAR_TOUCH_PAD11_DEBOUNCE_R::new(((self.bits >> 29) & 7) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_TOUCH_STATUS11")
+            .field("sar_touch_pad11_data", &self.sar_touch_pad11_data())
+            .field("sar_touch_pad11_debounce", &self.sar_touch_pad11_debounce())
+            .finish()
+    }
+}
+#[doc = "touch channel status of touch pad 11\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_touch_status11::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_TOUCH_STATUS11_SPEC;
+impl crate::RegisterSpec for SAR_TOUCH_STATUS11_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_touch_status11::R`](R) reader structure"]
+impl crate::Readable for SAR_TOUCH_STATUS11_SPEC {}
+#[doc = "`reset()` method sets SAR_TOUCH_STATUS11 to value 0"]
+impl crate::Resettable for SAR_TOUCH_STATUS11_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sens/sar_touch_status12.rs

@@ -0,0 +1,38 @@
+#[doc = "Register `SAR_TOUCH_STATUS12` reader"]
+pub type R = crate::R<SAR_TOUCH_STATUS12_SPEC>;
+#[doc = "Field `SAR_TOUCH_PAD12_DATA` reader - touch data debounce of touch pad 12"]
+pub type SAR_TOUCH_PAD12_DATA_R = crate::FieldReader<u32>;
+#[doc = "Field `SAR_TOUCH_PAD12_DEBOUNCE` reader - touch current debounce of touch pad 12"]
+pub type SAR_TOUCH_PAD12_DEBOUNCE_R = crate::FieldReader;
+impl R {
+    #[doc = "Bits 0:21 - touch data debounce of touch pad 12"]
+    #[inline(always)]
+    pub fn sar_touch_pad12_data(&self) -> SAR_TOUCH_PAD12_DATA_R {
+        SAR_TOUCH_PAD12_DATA_R::new(self.bits & 0x003f_ffff)
+    }
+    #[doc = "Bits 29:31 - touch current debounce of touch pad 12"]
+    #[inline(always)]
+    pub fn sar_touch_pad12_debounce(&self) -> SAR_TOUCH_PAD12_DEBOUNCE_R {
+        SAR_TOUCH_PAD12_DEBOUNCE_R::new(((self.bits >> 29) & 7) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_TOUCH_STATUS12")
+            .field("sar_touch_pad12_data", &self.sar_touch_pad12_data())
+            .field("sar_touch_pad12_debounce", &self.sar_touch_pad12_debounce())
+            .finish()
+    }
+}
+#[doc = "touch channel status of touch pad 12\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_touch_status12::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_TOUCH_STATUS12_SPEC;
+impl crate::RegisterSpec for SAR_TOUCH_STATUS12_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_touch_status12::R`](R) reader structure"]
+impl crate::Readable for SAR_TOUCH_STATUS12_SPEC {}
+#[doc = "`reset()` method sets SAR_TOUCH_STATUS12 to value 0"]
+impl crate::Resettable for SAR_TOUCH_STATUS12_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sens/sar_touch_status13.rs

@@ -0,0 +1,38 @@
+#[doc = "Register `SAR_TOUCH_STATUS13` reader"]
+pub type R = crate::R<SAR_TOUCH_STATUS13_SPEC>;
+#[doc = "Field `SAR_TOUCH_PAD13_DATA` reader - touch data debounce of touch pad 13"]
+pub type SAR_TOUCH_PAD13_DATA_R = crate::FieldReader<u32>;
+#[doc = "Field `SAR_TOUCH_PAD13_DEBOUNCE` reader - touch current debounce of touch pad 13"]
+pub type SAR_TOUCH_PAD13_DEBOUNCE_R = crate::FieldReader;
+impl R {
+    #[doc = "Bits 0:21 - touch data debounce of touch pad 13"]
+    #[inline(always)]
+    pub fn sar_touch_pad13_data(&self) -> SAR_TOUCH_PAD13_DATA_R {
+        SAR_TOUCH_PAD13_DATA_R::new(self.bits & 0x003f_ffff)
+    }
+    #[doc = "Bits 29:31 - touch current debounce of touch pad 13"]
+    #[inline(always)]
+    pub fn sar_touch_pad13_debounce(&self) -> SAR_TOUCH_PAD13_DEBOUNCE_R {
+        SAR_TOUCH_PAD13_DEBOUNCE_R::new(((self.bits >> 29) & 7) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_TOUCH_STATUS13")
+            .field("sar_touch_pad13_data", &self.sar_touch_pad13_data())
+            .field("sar_touch_pad13_debounce", &self.sar_touch_pad13_debounce())
+            .finish()
+    }
+}
+#[doc = "touch channel status of touch pad 13\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_touch_status13::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_TOUCH_STATUS13_SPEC;
+impl crate::RegisterSpec for SAR_TOUCH_STATUS13_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_touch_status13::R`](R) reader structure"]
+impl crate::Readable for SAR_TOUCH_STATUS13_SPEC {}
+#[doc = "`reset()` method sets SAR_TOUCH_STATUS13 to value 0"]
+impl crate::Resettable for SAR_TOUCH_STATUS13_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sens/sar_touch_status14.rs

@@ -0,0 +1,38 @@
+#[doc = "Register `SAR_TOUCH_STATUS14` reader"]
+pub type R = crate::R<SAR_TOUCH_STATUS14_SPEC>;
+#[doc = "Field `SAR_TOUCH_PAD14_DATA` reader - touch data debounce of touch pad 14"]
+pub type SAR_TOUCH_PAD14_DATA_R = crate::FieldReader<u32>;
+#[doc = "Field `SAR_TOUCH_PAD14_DEBOUNCE` reader - touch current debounce of touch pad 14"]
+pub type SAR_TOUCH_PAD14_DEBOUNCE_R = crate::FieldReader;
+impl R {
+    #[doc = "Bits 0:21 - touch data debounce of touch pad 14"]
+    #[inline(always)]
+    pub fn sar_touch_pad14_data(&self) -> SAR_TOUCH_PAD14_DATA_R {
+        SAR_TOUCH_PAD14_DATA_R::new(self.bits & 0x003f_ffff)
+    }
+    #[doc = "Bits 29:31 - touch current debounce of touch pad 14"]
+    #[inline(always)]
+    pub fn sar_touch_pad14_debounce(&self) -> SAR_TOUCH_PAD14_DEBOUNCE_R {
+        SAR_TOUCH_PAD14_DEBOUNCE_R::new(((self.bits >> 29) & 7) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_TOUCH_STATUS14")
+            .field("sar_touch_pad14_data", &self.sar_touch_pad14_data())
+            .field("sar_touch_pad14_debounce", &self.sar_touch_pad14_debounce())
+            .finish()
+    }
+}
+#[doc = "touch channel status of touch pad 14\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_touch_status14::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_TOUCH_STATUS14_SPEC;
+impl crate::RegisterSpec for SAR_TOUCH_STATUS14_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_touch_status14::R`](R) reader structure"]
+impl crate::Readable for SAR_TOUCH_STATUS14_SPEC {}
+#[doc = "`reset()` method sets SAR_TOUCH_STATUS14 to value 0"]
+impl crate::Resettable for SAR_TOUCH_STATUS14_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sens/sar_touch_status15.rs

@@ -0,0 +1,38 @@
+#[doc = "Register `SAR_TOUCH_STATUS15` reader"]
+pub type R = crate::R<SAR_TOUCH_STATUS15_SPEC>;
+#[doc = "Field `SAR_TOUCH_SLP_DATA` reader - touch data debounce of sleep pad"]
+pub type SAR_TOUCH_SLP_DATA_R = crate::FieldReader<u32>;
+#[doc = "Field `SAR_TOUCH_SLP_DEBOUNCE` reader - touch current debounce of sleep pad"]
+pub type SAR_TOUCH_SLP_DEBOUNCE_R = crate::FieldReader;
+impl R {
+    #[doc = "Bits 0:21 - touch data debounce of sleep pad"]
+    #[inline(always)]
+    pub fn sar_touch_slp_data(&self) -> SAR_TOUCH_SLP_DATA_R {
+        SAR_TOUCH_SLP_DATA_R::new(self.bits & 0x003f_ffff)
+    }
+    #[doc = "Bits 29:31 - touch current debounce of sleep pad"]
+    #[inline(always)]
+    pub fn sar_touch_slp_debounce(&self) -> SAR_TOUCH_SLP_DEBOUNCE_R {
+        SAR_TOUCH_SLP_DEBOUNCE_R::new(((self.bits >> 29) & 7) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_TOUCH_STATUS15")
+            .field("sar_touch_slp_data", &self.sar_touch_slp_data())
+            .field("sar_touch_slp_debounce", &self.sar_touch_slp_debounce())
+            .finish()
+    }
+}
+#[doc = "touch channel status of sleep pad\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_touch_status15::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_TOUCH_STATUS15_SPEC;
+impl crate::RegisterSpec for SAR_TOUCH_STATUS15_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_touch_status15::R`](R) reader structure"]
+impl crate::Readable for SAR_TOUCH_STATUS15_SPEC {}
+#[doc = "`reset()` method sets SAR_TOUCH_STATUS15 to value 0"]
+impl crate::Resettable for SAR_TOUCH_STATUS15_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sens/sar_touch_status16.rs

@@ -0,0 +1,66 @@
+#[doc = "Register `SAR_TOUCH_STATUS16` reader"]
+pub type R = crate::R<SAR_TOUCH_STATUS16_SPEC>;
+#[doc = "Field `SAR_TOUCH_APPROACH_PAD2_CNT` reader - touch current approach count of approach pad2"]
+pub type SAR_TOUCH_APPROACH_PAD2_CNT_R = crate::FieldReader;
+#[doc = "Field `SAR_TOUCH_APPROACH_PAD1_CNT` reader - touch current approach count of approach pad1"]
+pub type SAR_TOUCH_APPROACH_PAD1_CNT_R = crate::FieldReader;
+#[doc = "Field `SAR_TOUCH_APPROACH_PAD0_CNT` reader - touch current approach count of approach pad0"]
+pub type SAR_TOUCH_APPROACH_PAD0_CNT_R = crate::FieldReader;
+#[doc = "Field `SAR_TOUCH_SLP_APPROACH_CNT` reader - touch current approach count of slp pad"]
+pub type SAR_TOUCH_SLP_APPROACH_CNT_R = crate::FieldReader;
+impl R {
+    #[doc = "Bits 0:7 - touch current approach count of approach pad2"]
+    #[inline(always)]
+    pub fn sar_touch_approach_pad2_cnt(&self) -> SAR_TOUCH_APPROACH_PAD2_CNT_R {
+        SAR_TOUCH_APPROACH_PAD2_CNT_R::new((self.bits & 0xff) as u8)
+    }
+    #[doc = "Bits 8:15 - touch current approach count of approach pad1"]
+    #[inline(always)]
+    pub fn sar_touch_approach_pad1_cnt(&self) -> SAR_TOUCH_APPROACH_PAD1_CNT_R {
+        SAR_TOUCH_APPROACH_PAD1_CNT_R::new(((self.bits >> 8) & 0xff) as u8)
+    }
+    #[doc = "Bits 16:23 - touch current approach count of approach pad0"]
+    #[inline(always)]
+    pub fn sar_touch_approach_pad0_cnt(&self) -> SAR_TOUCH_APPROACH_PAD0_CNT_R {
+        SAR_TOUCH_APPROACH_PAD0_CNT_R::new(((self.bits >> 16) & 0xff) as u8)
+    }
+    #[doc = "Bits 24:31 - touch current approach count of slp pad"]
+    #[inline(always)]
+    pub fn sar_touch_slp_approach_cnt(&self) -> SAR_TOUCH_SLP_APPROACH_CNT_R {
+        SAR_TOUCH_SLP_APPROACH_CNT_R::new(((self.bits >> 24) & 0xff) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_TOUCH_STATUS16")
+            .field(
+                "sar_touch_approach_pad2_cnt",
+                &self.sar_touch_approach_pad2_cnt(),
+            )
+            .field(
+                "sar_touch_approach_pad1_cnt",
+                &self.sar_touch_approach_pad1_cnt(),
+            )
+            .field(
+                "sar_touch_approach_pad0_cnt",
+                &self.sar_touch_approach_pad0_cnt(),
+            )
+            .field(
+                "sar_touch_slp_approach_cnt",
+                &self.sar_touch_slp_approach_cnt(),
+            )
+            .finish()
+    }
+}
+#[doc = "touch channel status of approach mode\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_touch_status16::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_TOUCH_STATUS16_SPEC;
+impl crate::RegisterSpec for SAR_TOUCH_STATUS16_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_touch_status16::R`](R) reader structure"]
+impl crate::Readable for SAR_TOUCH_STATUS16_SPEC {}
+#[doc = "`reset()` method sets SAR_TOUCH_STATUS16 to value 0"]
+impl crate::Resettable for SAR_TOUCH_STATUS16_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sens/sar_touch_status2.rs

@@ -0,0 +1,38 @@
+#[doc = "Register `SAR_TOUCH_STATUS2` reader"]
+pub type R = crate::R<SAR_TOUCH_STATUS2_SPEC>;
+#[doc = "Field `SAR_TOUCH_PAD2_DATA` reader - touch data debounce of touch pad 2"]
+pub type SAR_TOUCH_PAD2_DATA_R = crate::FieldReader<u32>;
+#[doc = "Field `SAR_TOUCH_PAD2_DEBOUNCE` reader - touch current debounce of touch pad 2"]
+pub type SAR_TOUCH_PAD2_DEBOUNCE_R = crate::FieldReader;
+impl R {
+    #[doc = "Bits 0:21 - touch data debounce of touch pad 2"]
+    #[inline(always)]
+    pub fn sar_touch_pad2_data(&self) -> SAR_TOUCH_PAD2_DATA_R {
+        SAR_TOUCH_PAD2_DATA_R::new(self.bits & 0x003f_ffff)
+    }
+    #[doc = "Bits 29:31 - touch current debounce of touch pad 2"]
+    #[inline(always)]
+    pub fn sar_touch_pad2_debounce(&self) -> SAR_TOUCH_PAD2_DEBOUNCE_R {
+        SAR_TOUCH_PAD2_DEBOUNCE_R::new(((self.bits >> 29) & 7) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_TOUCH_STATUS2")
+            .field("sar_touch_pad2_data", &self.sar_touch_pad2_data())
+            .field("sar_touch_pad2_debounce", &self.sar_touch_pad2_debounce())
+            .finish()
+    }
+}
+#[doc = "touch channel status of touch pad 2\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_touch_status2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_TOUCH_STATUS2_SPEC;
+impl crate::RegisterSpec for SAR_TOUCH_STATUS2_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_touch_status2::R`](R) reader structure"]
+impl crate::Readable for SAR_TOUCH_STATUS2_SPEC {}
+#[doc = "`reset()` method sets SAR_TOUCH_STATUS2 to value 0"]
+impl crate::Resettable for SAR_TOUCH_STATUS2_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sens/sar_touch_status3.rs

@@ -0,0 +1,38 @@
+#[doc = "Register `SAR_TOUCH_STATUS3` reader"]
+pub type R = crate::R<SAR_TOUCH_STATUS3_SPEC>;
+#[doc = "Field `SAR_TOUCH_PAD3_DATA` reader - touch data debounce of touch pad 3"]
+pub type SAR_TOUCH_PAD3_DATA_R = crate::FieldReader<u32>;
+#[doc = "Field `SAR_TOUCH_PAD3_DEBOUNCE` reader - touch current debounce of touch pad 3"]
+pub type SAR_TOUCH_PAD3_DEBOUNCE_R = crate::FieldReader;
+impl R {
+    #[doc = "Bits 0:21 - touch data debounce of touch pad 3"]
+    #[inline(always)]
+    pub fn sar_touch_pad3_data(&self) -> SAR_TOUCH_PAD3_DATA_R {
+        SAR_TOUCH_PAD3_DATA_R::new(self.bits & 0x003f_ffff)
+    }
+    #[doc = "Bits 29:31 - touch current debounce of touch pad 3"]
+    #[inline(always)]
+    pub fn sar_touch_pad3_debounce(&self) -> SAR_TOUCH_PAD3_DEBOUNCE_R {
+        SAR_TOUCH_PAD3_DEBOUNCE_R::new(((self.bits >> 29) & 7) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_TOUCH_STATUS3")
+            .field("sar_touch_pad3_data", &self.sar_touch_pad3_data())
+            .field("sar_touch_pad3_debounce", &self.sar_touch_pad3_debounce())
+            .finish()
+    }
+}
+#[doc = "touch channel status of touch pad 3\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_touch_status3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_TOUCH_STATUS3_SPEC;
+impl crate::RegisterSpec for SAR_TOUCH_STATUS3_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_touch_status3::R`](R) reader structure"]
+impl crate::Readable for SAR_TOUCH_STATUS3_SPEC {}
+#[doc = "`reset()` method sets SAR_TOUCH_STATUS3 to value 0"]
+impl crate::Resettable for SAR_TOUCH_STATUS3_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sens/sar_touch_status4.rs

@@ -0,0 +1,38 @@
+#[doc = "Register `SAR_TOUCH_STATUS4` reader"]
+pub type R = crate::R<SAR_TOUCH_STATUS4_SPEC>;
+#[doc = "Field `SAR_TOUCH_PAD4_DATA` reader - touch data debounce of touch pad 4"]
+pub type SAR_TOUCH_PAD4_DATA_R = crate::FieldReader<u32>;
+#[doc = "Field `SAR_TOUCH_PAD4_DEBOUNCE` reader - touch current debounce of touch pad 4"]
+pub type SAR_TOUCH_PAD4_DEBOUNCE_R = crate::FieldReader;
+impl R {
+    #[doc = "Bits 0:21 - touch data debounce of touch pad 4"]
+    #[inline(always)]
+    pub fn sar_touch_pad4_data(&self) -> SAR_TOUCH_PAD4_DATA_R {
+        SAR_TOUCH_PAD4_DATA_R::new(self.bits & 0x003f_ffff)
+    }
+    #[doc = "Bits 29:31 - touch current debounce of touch pad 4"]
+    #[inline(always)]
+    pub fn sar_touch_pad4_debounce(&self) -> SAR_TOUCH_PAD4_DEBOUNCE_R {
+        SAR_TOUCH_PAD4_DEBOUNCE_R::new(((self.bits >> 29) & 7) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_TOUCH_STATUS4")
+            .field("sar_touch_pad4_data", &self.sar_touch_pad4_data())
+            .field("sar_touch_pad4_debounce", &self.sar_touch_pad4_debounce())
+            .finish()
+    }
+}
+#[doc = "touch channel status of touch pad 4\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_touch_status4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_TOUCH_STATUS4_SPEC;
+impl crate::RegisterSpec for SAR_TOUCH_STATUS4_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_touch_status4::R`](R) reader structure"]
+impl crate::Readable for SAR_TOUCH_STATUS4_SPEC {}
+#[doc = "`reset()` method sets SAR_TOUCH_STATUS4 to value 0"]
+impl crate::Resettable for SAR_TOUCH_STATUS4_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sens/sar_touch_status5.rs

@@ -0,0 +1,38 @@
+#[doc = "Register `SAR_TOUCH_STATUS5` reader"]
+pub type R = crate::R<SAR_TOUCH_STATUS5_SPEC>;
+#[doc = "Field `SAR_TOUCH_PAD5_DATA` reader - touch data debounce of touch pad 5"]
+pub type SAR_TOUCH_PAD5_DATA_R = crate::FieldReader<u32>;
+#[doc = "Field `SAR_TOUCH_PAD5_DEBOUNCE` reader - touch current debounce of touch pad 5"]
+pub type SAR_TOUCH_PAD5_DEBOUNCE_R = crate::FieldReader;
+impl R {
+    #[doc = "Bits 0:21 - touch data debounce of touch pad 5"]
+    #[inline(always)]
+    pub fn sar_touch_pad5_data(&self) -> SAR_TOUCH_PAD5_DATA_R {
+        SAR_TOUCH_PAD5_DATA_R::new(self.bits & 0x003f_ffff)
+    }
+    #[doc = "Bits 29:31 - touch current debounce of touch pad 5"]
+    #[inline(always)]
+    pub fn sar_touch_pad5_debounce(&self) -> SAR_TOUCH_PAD5_DEBOUNCE_R {
+        SAR_TOUCH_PAD5_DEBOUNCE_R::new(((self.bits >> 29) & 7) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_TOUCH_STATUS5")
+            .field("sar_touch_pad5_data", &self.sar_touch_pad5_data())
+            .field("sar_touch_pad5_debounce", &self.sar_touch_pad5_debounce())
+            .finish()
+    }
+}
+#[doc = "touch channel status of touch pad 5\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_touch_status5::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_TOUCH_STATUS5_SPEC;
+impl crate::RegisterSpec for SAR_TOUCH_STATUS5_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_touch_status5::R`](R) reader structure"]
+impl crate::Readable for SAR_TOUCH_STATUS5_SPEC {}
+#[doc = "`reset()` method sets SAR_TOUCH_STATUS5 to value 0"]
+impl crate::Resettable for SAR_TOUCH_STATUS5_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sens/sar_touch_status6.rs

@@ -0,0 +1,38 @@
+#[doc = "Register `SAR_TOUCH_STATUS6` reader"]
+pub type R = crate::R<SAR_TOUCH_STATUS6_SPEC>;
+#[doc = "Field `SAR_TOUCH_PAD6_DATA` reader - touch data debounce of touch pad 6"]
+pub type SAR_TOUCH_PAD6_DATA_R = crate::FieldReader<u32>;
+#[doc = "Field `SAR_TOUCH_PAD6_DEBOUNCE` reader - touch current debounce of touch pad 6"]
+pub type SAR_TOUCH_PAD6_DEBOUNCE_R = crate::FieldReader;
+impl R {
+    #[doc = "Bits 0:21 - touch data debounce of touch pad 6"]
+    #[inline(always)]
+    pub fn sar_touch_pad6_data(&self) -> SAR_TOUCH_PAD6_DATA_R {
+        SAR_TOUCH_PAD6_DATA_R::new(self.bits & 0x003f_ffff)
+    }
+    #[doc = "Bits 29:31 - touch current debounce of touch pad 6"]
+    #[inline(always)]
+    pub fn sar_touch_pad6_debounce(&self) -> SAR_TOUCH_PAD6_DEBOUNCE_R {
+        SAR_TOUCH_PAD6_DEBOUNCE_R::new(((self.bits >> 29) & 7) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_TOUCH_STATUS6")
+            .field("sar_touch_pad6_data", &self.sar_touch_pad6_data())
+            .field("sar_touch_pad6_debounce", &self.sar_touch_pad6_debounce())
+            .finish()
+    }
+}
+#[doc = "touch channel status of touch pad 6\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_touch_status6::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_TOUCH_STATUS6_SPEC;
+impl crate::RegisterSpec for SAR_TOUCH_STATUS6_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_touch_status6::R`](R) reader structure"]
+impl crate::Readable for SAR_TOUCH_STATUS6_SPEC {}
+#[doc = "`reset()` method sets SAR_TOUCH_STATUS6 to value 0"]
+impl crate::Resettable for SAR_TOUCH_STATUS6_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sens/sar_touch_status7.rs

@@ -0,0 +1,38 @@
+#[doc = "Register `SAR_TOUCH_STATUS7` reader"]
+pub type R = crate::R<SAR_TOUCH_STATUS7_SPEC>;
+#[doc = "Field `SAR_TOUCH_PAD7_DATA` reader - touch data debounce of touch pad 7"]
+pub type SAR_TOUCH_PAD7_DATA_R = crate::FieldReader<u32>;
+#[doc = "Field `SAR_TOUCH_PAD7_DEBOUNCE` reader - touch current debounce of touch pad 7"]
+pub type SAR_TOUCH_PAD7_DEBOUNCE_R = crate::FieldReader;
+impl R {
+    #[doc = "Bits 0:21 - touch data debounce of touch pad 7"]
+    #[inline(always)]
+    pub fn sar_touch_pad7_data(&self) -> SAR_TOUCH_PAD7_DATA_R {
+        SAR_TOUCH_PAD7_DATA_R::new(self.bits & 0x003f_ffff)
+    }
+    #[doc = "Bits 29:31 - touch current debounce of touch pad 7"]
+    #[inline(always)]
+    pub fn sar_touch_pad7_debounce(&self) -> SAR_TOUCH_PAD7_DEBOUNCE_R {
+        SAR_TOUCH_PAD7_DEBOUNCE_R::new(((self.bits >> 29) & 7) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_TOUCH_STATUS7")
+            .field("sar_touch_pad7_data", &self.sar_touch_pad7_data())
+            .field("sar_touch_pad7_debounce", &self.sar_touch_pad7_debounce())
+            .finish()
+    }
+}
+#[doc = "touch channel status of touch pad 7\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_touch_status7::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_TOUCH_STATUS7_SPEC;
+impl crate::RegisterSpec for SAR_TOUCH_STATUS7_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_touch_status7::R`](R) reader structure"]
+impl crate::Readable for SAR_TOUCH_STATUS7_SPEC {}
+#[doc = "`reset()` method sets SAR_TOUCH_STATUS7 to value 0"]
+impl crate::Resettable for SAR_TOUCH_STATUS7_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sens/sar_touch_status8.rs

@@ -0,0 +1,38 @@
+#[doc = "Register `SAR_TOUCH_STATUS8` reader"]
+pub type R = crate::R<SAR_TOUCH_STATUS8_SPEC>;
+#[doc = "Field `SAR_TOUCH_PAD8_DATA` reader - touch data debounce of touch pad 8"]
+pub type SAR_TOUCH_PAD8_DATA_R = crate::FieldReader<u32>;
+#[doc = "Field `SAR_TOUCH_PAD8_DEBOUNCE` reader - touch current debounce of touch pad 8"]
+pub type SAR_TOUCH_PAD8_DEBOUNCE_R = crate::FieldReader;
+impl R {
+    #[doc = "Bits 0:21 - touch data debounce of touch pad 8"]
+    #[inline(always)]
+    pub fn sar_touch_pad8_data(&self) -> SAR_TOUCH_PAD8_DATA_R {
+        SAR_TOUCH_PAD8_DATA_R::new(self.bits & 0x003f_ffff)
+    }
+    #[doc = "Bits 29:31 - touch current debounce of touch pad 8"]
+    #[inline(always)]
+    pub fn sar_touch_pad8_debounce(&self) -> SAR_TOUCH_PAD8_DEBOUNCE_R {
+        SAR_TOUCH_PAD8_DEBOUNCE_R::new(((self.bits >> 29) & 7) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_TOUCH_STATUS8")
+            .field("sar_touch_pad8_data", &self.sar_touch_pad8_data())
+            .field("sar_touch_pad8_debounce", &self.sar_touch_pad8_debounce())
+            .finish()
+    }
+}
+#[doc = "touch channel status of touch pad 8\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_touch_status8::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_TOUCH_STATUS8_SPEC;
+impl crate::RegisterSpec for SAR_TOUCH_STATUS8_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_touch_status8::R`](R) reader structure"]
+impl crate::Readable for SAR_TOUCH_STATUS8_SPEC {}
+#[doc = "`reset()` method sets SAR_TOUCH_STATUS8 to value 0"]
+impl crate::Resettable for SAR_TOUCH_STATUS8_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sens/sar_touch_status9.rs

@@ -0,0 +1,38 @@
+#[doc = "Register `SAR_TOUCH_STATUS9` reader"]
+pub type R = crate::R<SAR_TOUCH_STATUS9_SPEC>;
+#[doc = "Field `SAR_TOUCH_PAD9_DATA` reader - touch data debounce of touch pad 9"]
+pub type SAR_TOUCH_PAD9_DATA_R = crate::FieldReader<u32>;
+#[doc = "Field `SAR_TOUCH_PAD9_DEBOUNCE` reader - touch current debounce of touch pad 9"]
+pub type SAR_TOUCH_PAD9_DEBOUNCE_R = crate::FieldReader;
+impl R {
+    #[doc = "Bits 0:21 - touch data debounce of touch pad 9"]
+    #[inline(always)]
+    pub fn sar_touch_pad9_data(&self) -> SAR_TOUCH_PAD9_DATA_R {
+        SAR_TOUCH_PAD9_DATA_R::new(self.bits & 0x003f_ffff)
+    }
+    #[doc = "Bits 29:31 - touch current debounce of touch pad 9"]
+    #[inline(always)]
+    pub fn sar_touch_pad9_debounce(&self) -> SAR_TOUCH_PAD9_DEBOUNCE_R {
+        SAR_TOUCH_PAD9_DEBOUNCE_R::new(((self.bits >> 29) & 7) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_TOUCH_STATUS9")
+            .field("sar_touch_pad9_data", &self.sar_touch_pad9_data())
+            .field("sar_touch_pad9_debounce", &self.sar_touch_pad9_debounce())
+            .finish()
+    }
+}
+#[doc = "touch channel status of touch pad 9\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_touch_status9::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_TOUCH_STATUS9_SPEC;
+impl crate::RegisterSpec for SAR_TOUCH_STATUS9_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_touch_status9::R`](R) reader structure"]
+impl crate::Readable for SAR_TOUCH_STATUS9_SPEC {}
+#[doc = "`reset()` method sets SAR_TOUCH_STATUS9 to value 0"]
+impl crate::Resettable for SAR_TOUCH_STATUS9_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sens/sar_touch_thres1.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `SAR_TOUCH_THRES1` reader"]
+pub type R = crate::R<SAR_TOUCH_THRES1_SPEC>;
+#[doc = "Register `SAR_TOUCH_THRES1` writer"]
+pub type W = crate::W<SAR_TOUCH_THRES1_SPEC>;
+#[doc = "Field `SAR_TOUCH_OUT_TH1` reader - Finger threshold for touch pad 1"]
+pub type SAR_TOUCH_OUT_TH1_R = crate::FieldReader<u32>;
+#[doc = "Field `SAR_TOUCH_OUT_TH1` writer - Finger threshold for touch pad 1"]
+pub type SAR_TOUCH_OUT_TH1_W<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>;
+impl R {
+    #[doc = "Bits 0:21 - Finger threshold for touch pad 1"]
+    #[inline(always)]
+    pub fn sar_touch_out_th1(&self) -> SAR_TOUCH_OUT_TH1_R {
+        SAR_TOUCH_OUT_TH1_R::new(self.bits & 0x003f_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_TOUCH_THRES1")
+            .field("sar_touch_out_th1", &self.sar_touch_out_th1())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:21 - Finger threshold for touch pad 1"]
+    #[inline(always)]
+    pub fn sar_touch_out_th1(&mut self) -> SAR_TOUCH_OUT_TH1_W<SAR_TOUCH_THRES1_SPEC> {
+        SAR_TOUCH_OUT_TH1_W::new(self, 0)
+    }
+}
+#[doc = "configure touch thres of touch pad\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_touch_thres1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_touch_thres1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_TOUCH_THRES1_SPEC;
+impl crate::RegisterSpec for SAR_TOUCH_THRES1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_touch_thres1::R`](R) reader structure"]
+impl crate::Readable for SAR_TOUCH_THRES1_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sar_touch_thres1::W`](W) writer structure"]
+impl crate::Writable for SAR_TOUCH_THRES1_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SAR_TOUCH_THRES1 to value 0"]
+impl crate::Resettable for SAR_TOUCH_THRES1_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sens/sar_touch_thres10.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `SAR_TOUCH_THRES10` reader"]
+pub type R = crate::R<SAR_TOUCH_THRES10_SPEC>;
+#[doc = "Register `SAR_TOUCH_THRES10` writer"]
+pub type W = crate::W<SAR_TOUCH_THRES10_SPEC>;
+#[doc = "Field `SAR_TOUCH_OUT_TH10` reader - Finger threshold for touch pad 10"]
+pub type SAR_TOUCH_OUT_TH10_R = crate::FieldReader<u32>;
+#[doc = "Field `SAR_TOUCH_OUT_TH10` writer - Finger threshold for touch pad 10"]
+pub type SAR_TOUCH_OUT_TH10_W<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>;
+impl R {
+    #[doc = "Bits 0:21 - Finger threshold for touch pad 10"]
+    #[inline(always)]
+    pub fn sar_touch_out_th10(&self) -> SAR_TOUCH_OUT_TH10_R {
+        SAR_TOUCH_OUT_TH10_R::new(self.bits & 0x003f_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_TOUCH_THRES10")
+            .field("sar_touch_out_th10", &self.sar_touch_out_th10())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:21 - Finger threshold for touch pad 10"]
+    #[inline(always)]
+    pub fn sar_touch_out_th10(&mut self) -> SAR_TOUCH_OUT_TH10_W<SAR_TOUCH_THRES10_SPEC> {
+        SAR_TOUCH_OUT_TH10_W::new(self, 0)
+    }
+}
+#[doc = "configure touch thres of touch pad\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_touch_thres10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_touch_thres10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_TOUCH_THRES10_SPEC;
+impl crate::RegisterSpec for SAR_TOUCH_THRES10_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_touch_thres10::R`](R) reader structure"]
+impl crate::Readable for SAR_TOUCH_THRES10_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sar_touch_thres10::W`](W) writer structure"]
+impl crate::Writable for SAR_TOUCH_THRES10_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SAR_TOUCH_THRES10 to value 0"]
+impl crate::Resettable for SAR_TOUCH_THRES10_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sens/sar_touch_thres11.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `SAR_TOUCH_THRES11` reader"]
+pub type R = crate::R<SAR_TOUCH_THRES11_SPEC>;
+#[doc = "Register `SAR_TOUCH_THRES11` writer"]
+pub type W = crate::W<SAR_TOUCH_THRES11_SPEC>;
+#[doc = "Field `SAR_TOUCH_OUT_TH11` reader - Finger threshold for touch pad 11"]
+pub type SAR_TOUCH_OUT_TH11_R = crate::FieldReader<u32>;
+#[doc = "Field `SAR_TOUCH_OUT_TH11` writer - Finger threshold for touch pad 11"]
+pub type SAR_TOUCH_OUT_TH11_W<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>;
+impl R {
+    #[doc = "Bits 0:21 - Finger threshold for touch pad 11"]
+    #[inline(always)]
+    pub fn sar_touch_out_th11(&self) -> SAR_TOUCH_OUT_TH11_R {
+        SAR_TOUCH_OUT_TH11_R::new(self.bits & 0x003f_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_TOUCH_THRES11")
+            .field("sar_touch_out_th11", &self.sar_touch_out_th11())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:21 - Finger threshold for touch pad 11"]
+    #[inline(always)]
+    pub fn sar_touch_out_th11(&mut self) -> SAR_TOUCH_OUT_TH11_W<SAR_TOUCH_THRES11_SPEC> {
+        SAR_TOUCH_OUT_TH11_W::new(self, 0)
+    }
+}
+#[doc = "configure touch thres of touch pad\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_touch_thres11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_touch_thres11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_TOUCH_THRES11_SPEC;
+impl crate::RegisterSpec for SAR_TOUCH_THRES11_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_touch_thres11::R`](R) reader structure"]
+impl crate::Readable for SAR_TOUCH_THRES11_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sar_touch_thres11::W`](W) writer structure"]
+impl crate::Writable for SAR_TOUCH_THRES11_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SAR_TOUCH_THRES11 to value 0"]
+impl crate::Resettable for SAR_TOUCH_THRES11_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sens/sar_touch_thres12.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `SAR_TOUCH_THRES12` reader"]
+pub type R = crate::R<SAR_TOUCH_THRES12_SPEC>;
+#[doc = "Register `SAR_TOUCH_THRES12` writer"]
+pub type W = crate::W<SAR_TOUCH_THRES12_SPEC>;
+#[doc = "Field `SAR_TOUCH_OUT_TH12` reader - Finger threshold for touch pad 12"]
+pub type SAR_TOUCH_OUT_TH12_R = crate::FieldReader<u32>;
+#[doc = "Field `SAR_TOUCH_OUT_TH12` writer - Finger threshold for touch pad 12"]
+pub type SAR_TOUCH_OUT_TH12_W<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>;
+impl R {
+    #[doc = "Bits 0:21 - Finger threshold for touch pad 12"]
+    #[inline(always)]
+    pub fn sar_touch_out_th12(&self) -> SAR_TOUCH_OUT_TH12_R {
+        SAR_TOUCH_OUT_TH12_R::new(self.bits & 0x003f_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_TOUCH_THRES12")
+            .field("sar_touch_out_th12", &self.sar_touch_out_th12())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:21 - Finger threshold for touch pad 12"]
+    #[inline(always)]
+    pub fn sar_touch_out_th12(&mut self) -> SAR_TOUCH_OUT_TH12_W<SAR_TOUCH_THRES12_SPEC> {
+        SAR_TOUCH_OUT_TH12_W::new(self, 0)
+    }
+}
+#[doc = "configure touch thres of touch pad\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_touch_thres12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_touch_thres12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_TOUCH_THRES12_SPEC;
+impl crate::RegisterSpec for SAR_TOUCH_THRES12_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_touch_thres12::R`](R) reader structure"]
+impl crate::Readable for SAR_TOUCH_THRES12_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sar_touch_thres12::W`](W) writer structure"]
+impl crate::Writable for SAR_TOUCH_THRES12_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SAR_TOUCH_THRES12 to value 0"]
+impl crate::Resettable for SAR_TOUCH_THRES12_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sens/sar_touch_thres13.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `SAR_TOUCH_THRES13` reader"]
+pub type R = crate::R<SAR_TOUCH_THRES13_SPEC>;
+#[doc = "Register `SAR_TOUCH_THRES13` writer"]
+pub type W = crate::W<SAR_TOUCH_THRES13_SPEC>;
+#[doc = "Field `SAR_TOUCH_OUT_TH13` reader - Finger threshold for touch pad 13"]
+pub type SAR_TOUCH_OUT_TH13_R = crate::FieldReader<u32>;
+#[doc = "Field `SAR_TOUCH_OUT_TH13` writer - Finger threshold for touch pad 13"]
+pub type SAR_TOUCH_OUT_TH13_W<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>;
+impl R {
+    #[doc = "Bits 0:21 - Finger threshold for touch pad 13"]
+    #[inline(always)]
+    pub fn sar_touch_out_th13(&self) -> SAR_TOUCH_OUT_TH13_R {
+        SAR_TOUCH_OUT_TH13_R::new(self.bits & 0x003f_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_TOUCH_THRES13")
+            .field("sar_touch_out_th13", &self.sar_touch_out_th13())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:21 - Finger threshold for touch pad 13"]
+    #[inline(always)]
+    pub fn sar_touch_out_th13(&mut self) -> SAR_TOUCH_OUT_TH13_W<SAR_TOUCH_THRES13_SPEC> {
+        SAR_TOUCH_OUT_TH13_W::new(self, 0)
+    }
+}
+#[doc = "configure touch thres of touch pad\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_touch_thres13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_touch_thres13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_TOUCH_THRES13_SPEC;
+impl crate::RegisterSpec for SAR_TOUCH_THRES13_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_touch_thres13::R`](R) reader structure"]
+impl crate::Readable for SAR_TOUCH_THRES13_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sar_touch_thres13::W`](W) writer structure"]
+impl crate::Writable for SAR_TOUCH_THRES13_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SAR_TOUCH_THRES13 to value 0"]
+impl crate::Resettable for SAR_TOUCH_THRES13_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sens/sar_touch_thres14.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `SAR_TOUCH_THRES14` reader"]
+pub type R = crate::R<SAR_TOUCH_THRES14_SPEC>;
+#[doc = "Register `SAR_TOUCH_THRES14` writer"]
+pub type W = crate::W<SAR_TOUCH_THRES14_SPEC>;
+#[doc = "Field `SAR_TOUCH_OUT_TH14` reader - Finger threshold for touch pad 14"]
+pub type SAR_TOUCH_OUT_TH14_R = crate::FieldReader<u32>;
+#[doc = "Field `SAR_TOUCH_OUT_TH14` writer - Finger threshold for touch pad 14"]
+pub type SAR_TOUCH_OUT_TH14_W<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>;
+impl R {
+    #[doc = "Bits 0:21 - Finger threshold for touch pad 14"]
+    #[inline(always)]
+    pub fn sar_touch_out_th14(&self) -> SAR_TOUCH_OUT_TH14_R {
+        SAR_TOUCH_OUT_TH14_R::new(self.bits & 0x003f_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_TOUCH_THRES14")
+            .field("sar_touch_out_th14", &self.sar_touch_out_th14())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:21 - Finger threshold for touch pad 14"]
+    #[inline(always)]
+    pub fn sar_touch_out_th14(&mut self) -> SAR_TOUCH_OUT_TH14_W<SAR_TOUCH_THRES14_SPEC> {
+        SAR_TOUCH_OUT_TH14_W::new(self, 0)
+    }
+}
+#[doc = "configure touch thres of touch pad\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_touch_thres14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_touch_thres14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_TOUCH_THRES14_SPEC;
+impl crate::RegisterSpec for SAR_TOUCH_THRES14_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_touch_thres14::R`](R) reader structure"]
+impl crate::Readable for SAR_TOUCH_THRES14_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sar_touch_thres14::W`](W) writer structure"]
+impl crate::Writable for SAR_TOUCH_THRES14_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SAR_TOUCH_THRES14 to value 0"]
+impl crate::Resettable for SAR_TOUCH_THRES14_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sens/sar_touch_thres2.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `SAR_TOUCH_THRES2` reader"]
+pub type R = crate::R<SAR_TOUCH_THRES2_SPEC>;
+#[doc = "Register `SAR_TOUCH_THRES2` writer"]
+pub type W = crate::W<SAR_TOUCH_THRES2_SPEC>;
+#[doc = "Field `SAR_TOUCH_OUT_TH2` reader - Finger threshold for touch pad 2"]
+pub type SAR_TOUCH_OUT_TH2_R = crate::FieldReader<u32>;
+#[doc = "Field `SAR_TOUCH_OUT_TH2` writer - Finger threshold for touch pad 2"]
+pub type SAR_TOUCH_OUT_TH2_W<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>;
+impl R {
+    #[doc = "Bits 0:21 - Finger threshold for touch pad 2"]
+    #[inline(always)]
+    pub fn sar_touch_out_th2(&self) -> SAR_TOUCH_OUT_TH2_R {
+        SAR_TOUCH_OUT_TH2_R::new(self.bits & 0x003f_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_TOUCH_THRES2")
+            .field("sar_touch_out_th2", &self.sar_touch_out_th2())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:21 - Finger threshold for touch pad 2"]
+    #[inline(always)]
+    pub fn sar_touch_out_th2(&mut self) -> SAR_TOUCH_OUT_TH2_W<SAR_TOUCH_THRES2_SPEC> {
+        SAR_TOUCH_OUT_TH2_W::new(self, 0)
+    }
+}
+#[doc = "configure touch thres of touch pad\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_touch_thres2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_touch_thres2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_TOUCH_THRES2_SPEC;
+impl crate::RegisterSpec for SAR_TOUCH_THRES2_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_touch_thres2::R`](R) reader structure"]
+impl crate::Readable for SAR_TOUCH_THRES2_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sar_touch_thres2::W`](W) writer structure"]
+impl crate::Writable for SAR_TOUCH_THRES2_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SAR_TOUCH_THRES2 to value 0"]
+impl crate::Resettable for SAR_TOUCH_THRES2_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sens/sar_touch_thres3.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `SAR_TOUCH_THRES3` reader"]
+pub type R = crate::R<SAR_TOUCH_THRES3_SPEC>;
+#[doc = "Register `SAR_TOUCH_THRES3` writer"]
+pub type W = crate::W<SAR_TOUCH_THRES3_SPEC>;
+#[doc = "Field `SAR_TOUCH_OUT_TH3` reader - Finger threshold for touch pad 3"]
+pub type SAR_TOUCH_OUT_TH3_R = crate::FieldReader<u32>;
+#[doc = "Field `SAR_TOUCH_OUT_TH3` writer - Finger threshold for touch pad 3"]
+pub type SAR_TOUCH_OUT_TH3_W<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>;
+impl R {
+    #[doc = "Bits 0:21 - Finger threshold for touch pad 3"]
+    #[inline(always)]
+    pub fn sar_touch_out_th3(&self) -> SAR_TOUCH_OUT_TH3_R {
+        SAR_TOUCH_OUT_TH3_R::new(self.bits & 0x003f_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_TOUCH_THRES3")
+            .field("sar_touch_out_th3", &self.sar_touch_out_th3())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:21 - Finger threshold for touch pad 3"]
+    #[inline(always)]
+    pub fn sar_touch_out_th3(&mut self) -> SAR_TOUCH_OUT_TH3_W<SAR_TOUCH_THRES3_SPEC> {
+        SAR_TOUCH_OUT_TH3_W::new(self, 0)
+    }
+}
+#[doc = "configure touch thres of touch pad\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_touch_thres3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_touch_thres3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_TOUCH_THRES3_SPEC;
+impl crate::RegisterSpec for SAR_TOUCH_THRES3_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_touch_thres3::R`](R) reader structure"]
+impl crate::Readable for SAR_TOUCH_THRES3_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sar_touch_thres3::W`](W) writer structure"]
+impl crate::Writable for SAR_TOUCH_THRES3_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SAR_TOUCH_THRES3 to value 0"]
+impl crate::Resettable for SAR_TOUCH_THRES3_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sens/sar_touch_thres4.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `SAR_TOUCH_THRES4` reader"]
+pub type R = crate::R<SAR_TOUCH_THRES4_SPEC>;
+#[doc = "Register `SAR_TOUCH_THRES4` writer"]
+pub type W = crate::W<SAR_TOUCH_THRES4_SPEC>;
+#[doc = "Field `SAR_TOUCH_OUT_TH4` reader - Finger threshold for touch pad 4"]
+pub type SAR_TOUCH_OUT_TH4_R = crate::FieldReader<u32>;
+#[doc = "Field `SAR_TOUCH_OUT_TH4` writer - Finger threshold for touch pad 4"]
+pub type SAR_TOUCH_OUT_TH4_W<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>;
+impl R {
+    #[doc = "Bits 0:21 - Finger threshold for touch pad 4"]
+    #[inline(always)]
+    pub fn sar_touch_out_th4(&self) -> SAR_TOUCH_OUT_TH4_R {
+        SAR_TOUCH_OUT_TH4_R::new(self.bits & 0x003f_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_TOUCH_THRES4")
+            .field("sar_touch_out_th4", &self.sar_touch_out_th4())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:21 - Finger threshold for touch pad 4"]
+    #[inline(always)]
+    pub fn sar_touch_out_th4(&mut self) -> SAR_TOUCH_OUT_TH4_W<SAR_TOUCH_THRES4_SPEC> {
+        SAR_TOUCH_OUT_TH4_W::new(self, 0)
+    }
+}
+#[doc = "configure touch thres of touch pad\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_touch_thres4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_touch_thres4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_TOUCH_THRES4_SPEC;
+impl crate::RegisterSpec for SAR_TOUCH_THRES4_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_touch_thres4::R`](R) reader structure"]
+impl crate::Readable for SAR_TOUCH_THRES4_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sar_touch_thres4::W`](W) writer structure"]
+impl crate::Writable for SAR_TOUCH_THRES4_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SAR_TOUCH_THRES4 to value 0"]
+impl crate::Resettable for SAR_TOUCH_THRES4_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sens/sar_touch_thres5.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `SAR_TOUCH_THRES5` reader"]
+pub type R = crate::R<SAR_TOUCH_THRES5_SPEC>;
+#[doc = "Register `SAR_TOUCH_THRES5` writer"]
+pub type W = crate::W<SAR_TOUCH_THRES5_SPEC>;
+#[doc = "Field `SAR_TOUCH_OUT_TH5` reader - Finger threshold for touch pad 5"]
+pub type SAR_TOUCH_OUT_TH5_R = crate::FieldReader<u32>;
+#[doc = "Field `SAR_TOUCH_OUT_TH5` writer - Finger threshold for touch pad 5"]
+pub type SAR_TOUCH_OUT_TH5_W<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>;
+impl R {
+    #[doc = "Bits 0:21 - Finger threshold for touch pad 5"]
+    #[inline(always)]
+    pub fn sar_touch_out_th5(&self) -> SAR_TOUCH_OUT_TH5_R {
+        SAR_TOUCH_OUT_TH5_R::new(self.bits & 0x003f_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_TOUCH_THRES5")
+            .field("sar_touch_out_th5", &self.sar_touch_out_th5())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:21 - Finger threshold for touch pad 5"]
+    #[inline(always)]
+    pub fn sar_touch_out_th5(&mut self) -> SAR_TOUCH_OUT_TH5_W<SAR_TOUCH_THRES5_SPEC> {
+        SAR_TOUCH_OUT_TH5_W::new(self, 0)
+    }
+}
+#[doc = "configure touch thres of touch pad\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_touch_thres5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_touch_thres5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_TOUCH_THRES5_SPEC;
+impl crate::RegisterSpec for SAR_TOUCH_THRES5_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_touch_thres5::R`](R) reader structure"]
+impl crate::Readable for SAR_TOUCH_THRES5_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sar_touch_thres5::W`](W) writer structure"]
+impl crate::Writable for SAR_TOUCH_THRES5_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SAR_TOUCH_THRES5 to value 0"]
+impl crate::Resettable for SAR_TOUCH_THRES5_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sens/sar_touch_thres6.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `SAR_TOUCH_THRES6` reader"]
+pub type R = crate::R<SAR_TOUCH_THRES6_SPEC>;
+#[doc = "Register `SAR_TOUCH_THRES6` writer"]
+pub type W = crate::W<SAR_TOUCH_THRES6_SPEC>;
+#[doc = "Field `SAR_TOUCH_OUT_TH6` reader - Finger threshold for touch pad 6"]
+pub type SAR_TOUCH_OUT_TH6_R = crate::FieldReader<u32>;
+#[doc = "Field `SAR_TOUCH_OUT_TH6` writer - Finger threshold for touch pad 6"]
+pub type SAR_TOUCH_OUT_TH6_W<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>;
+impl R {
+    #[doc = "Bits 0:21 - Finger threshold for touch pad 6"]
+    #[inline(always)]
+    pub fn sar_touch_out_th6(&self) -> SAR_TOUCH_OUT_TH6_R {
+        SAR_TOUCH_OUT_TH6_R::new(self.bits & 0x003f_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_TOUCH_THRES6")
+            .field("sar_touch_out_th6", &self.sar_touch_out_th6())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:21 - Finger threshold for touch pad 6"]
+    #[inline(always)]
+    pub fn sar_touch_out_th6(&mut self) -> SAR_TOUCH_OUT_TH6_W<SAR_TOUCH_THRES6_SPEC> {
+        SAR_TOUCH_OUT_TH6_W::new(self, 0)
+    }
+}
+#[doc = "configure touch thres of touch pad\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_touch_thres6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_touch_thres6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_TOUCH_THRES6_SPEC;
+impl crate::RegisterSpec for SAR_TOUCH_THRES6_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_touch_thres6::R`](R) reader structure"]
+impl crate::Readable for SAR_TOUCH_THRES6_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sar_touch_thres6::W`](W) writer structure"]
+impl crate::Writable for SAR_TOUCH_THRES6_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SAR_TOUCH_THRES6 to value 0"]
+impl crate::Resettable for SAR_TOUCH_THRES6_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sens/sar_touch_thres7.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `SAR_TOUCH_THRES7` reader"]
+pub type R = crate::R<SAR_TOUCH_THRES7_SPEC>;
+#[doc = "Register `SAR_TOUCH_THRES7` writer"]
+pub type W = crate::W<SAR_TOUCH_THRES7_SPEC>;
+#[doc = "Field `SAR_TOUCH_OUT_TH7` reader - Finger threshold for touch pad 7"]
+pub type SAR_TOUCH_OUT_TH7_R = crate::FieldReader<u32>;
+#[doc = "Field `SAR_TOUCH_OUT_TH7` writer - Finger threshold for touch pad 7"]
+pub type SAR_TOUCH_OUT_TH7_W<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>;
+impl R {
+    #[doc = "Bits 0:21 - Finger threshold for touch pad 7"]
+    #[inline(always)]
+    pub fn sar_touch_out_th7(&self) -> SAR_TOUCH_OUT_TH7_R {
+        SAR_TOUCH_OUT_TH7_R::new(self.bits & 0x003f_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_TOUCH_THRES7")
+            .field("sar_touch_out_th7", &self.sar_touch_out_th7())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:21 - Finger threshold for touch pad 7"]
+    #[inline(always)]
+    pub fn sar_touch_out_th7(&mut self) -> SAR_TOUCH_OUT_TH7_W<SAR_TOUCH_THRES7_SPEC> {
+        SAR_TOUCH_OUT_TH7_W::new(self, 0)
+    }
+}
+#[doc = "configure touch thres of touch pad\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_touch_thres7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_touch_thres7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_TOUCH_THRES7_SPEC;
+impl crate::RegisterSpec for SAR_TOUCH_THRES7_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_touch_thres7::R`](R) reader structure"]
+impl crate::Readable for SAR_TOUCH_THRES7_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sar_touch_thres7::W`](W) writer structure"]
+impl crate::Writable for SAR_TOUCH_THRES7_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SAR_TOUCH_THRES7 to value 0"]
+impl crate::Resettable for SAR_TOUCH_THRES7_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sens/sar_touch_thres8.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `SAR_TOUCH_THRES8` reader"]
+pub type R = crate::R<SAR_TOUCH_THRES8_SPEC>;
+#[doc = "Register `SAR_TOUCH_THRES8` writer"]
+pub type W = crate::W<SAR_TOUCH_THRES8_SPEC>;
+#[doc = "Field `SAR_TOUCH_OUT_TH8` reader - Finger threshold for touch pad 8"]
+pub type SAR_TOUCH_OUT_TH8_R = crate::FieldReader<u32>;
+#[doc = "Field `SAR_TOUCH_OUT_TH8` writer - Finger threshold for touch pad 8"]
+pub type SAR_TOUCH_OUT_TH8_W<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>;
+impl R {
+    #[doc = "Bits 0:21 - Finger threshold for touch pad 8"]
+    #[inline(always)]
+    pub fn sar_touch_out_th8(&self) -> SAR_TOUCH_OUT_TH8_R {
+        SAR_TOUCH_OUT_TH8_R::new(self.bits & 0x003f_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_TOUCH_THRES8")
+            .field("sar_touch_out_th8", &self.sar_touch_out_th8())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:21 - Finger threshold for touch pad 8"]
+    #[inline(always)]
+    pub fn sar_touch_out_th8(&mut self) -> SAR_TOUCH_OUT_TH8_W<SAR_TOUCH_THRES8_SPEC> {
+        SAR_TOUCH_OUT_TH8_W::new(self, 0)
+    }
+}
+#[doc = "configure touch thres of touch pad\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_touch_thres8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_touch_thres8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_TOUCH_THRES8_SPEC;
+impl crate::RegisterSpec for SAR_TOUCH_THRES8_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_touch_thres8::R`](R) reader structure"]
+impl crate::Readable for SAR_TOUCH_THRES8_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sar_touch_thres8::W`](W) writer structure"]
+impl crate::Writable for SAR_TOUCH_THRES8_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SAR_TOUCH_THRES8 to value 0"]
+impl crate::Resettable for SAR_TOUCH_THRES8_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sens/sar_touch_thres9.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `SAR_TOUCH_THRES9` reader"]
+pub type R = crate::R<SAR_TOUCH_THRES9_SPEC>;
+#[doc = "Register `SAR_TOUCH_THRES9` writer"]
+pub type W = crate::W<SAR_TOUCH_THRES9_SPEC>;
+#[doc = "Field `SAR_TOUCH_OUT_TH9` reader - Finger threshold for touch pad 9"]
+pub type SAR_TOUCH_OUT_TH9_R = crate::FieldReader<u32>;
+#[doc = "Field `SAR_TOUCH_OUT_TH9` writer - Finger threshold for touch pad 9"]
+pub type SAR_TOUCH_OUT_TH9_W<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>;
+impl R {
+    #[doc = "Bits 0:21 - Finger threshold for touch pad 9"]
+    #[inline(always)]
+    pub fn sar_touch_out_th9(&self) -> SAR_TOUCH_OUT_TH9_R {
+        SAR_TOUCH_OUT_TH9_R::new(self.bits & 0x003f_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_TOUCH_THRES9")
+            .field("sar_touch_out_th9", &self.sar_touch_out_th9())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:21 - Finger threshold for touch pad 9"]
+    #[inline(always)]
+    pub fn sar_touch_out_th9(&mut self) -> SAR_TOUCH_OUT_TH9_W<SAR_TOUCH_THRES9_SPEC> {
+        SAR_TOUCH_OUT_TH9_W::new(self, 0)
+    }
+}
+#[doc = "configure touch thres of touch pad\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_touch_thres9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_touch_thres9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_TOUCH_THRES9_SPEC;
+impl crate::RegisterSpec for SAR_TOUCH_THRES9_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_touch_thres9::R`](R) reader structure"]
+impl crate::Readable for SAR_TOUCH_THRES9_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sar_touch_thres9::W`](W) writer structure"]
+impl crate::Writable for SAR_TOUCH_THRES9_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SAR_TOUCH_THRES9 to value 0"]
+impl crate::Resettable for SAR_TOUCH_THRES9_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sens/sar_tsens_ctrl.rs

@@ -0,0 +1,138 @@
+#[doc = "Register `SAR_TSENS_CTRL` reader"]
+pub type R = crate::R<SAR_TSENS_CTRL_SPEC>;
+#[doc = "Register `SAR_TSENS_CTRL` writer"]
+pub type W = crate::W<SAR_TSENS_CTRL_SPEC>;
+#[doc = "Field `SAR_TSENS_OUT` reader - temperature sensor data out"]
+pub type SAR_TSENS_OUT_R = crate::FieldReader;
+#[doc = "Field `SAR_TSENS_READY` reader - indicate temperature sensor out ready"]
+pub type SAR_TSENS_READY_R = crate::BitReader;
+#[doc = "Field `SAR_TSENS_INT_EN` reader - enable temperature sensor to send out interrupt"]
+pub type SAR_TSENS_INT_EN_R = crate::BitReader;
+#[doc = "Field `SAR_TSENS_INT_EN` writer - enable temperature sensor to send out interrupt"]
+pub type SAR_TSENS_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_TSENS_IN_INV` reader - invert temperature sensor data"]
+pub type SAR_TSENS_IN_INV_R = crate::BitReader;
+#[doc = "Field `SAR_TSENS_IN_INV` writer - invert temperature sensor data"]
+pub type SAR_TSENS_IN_INV_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_TSENS_CLK_DIV` reader - temperature sensor clock divider"]
+pub type SAR_TSENS_CLK_DIV_R = crate::FieldReader;
+#[doc = "Field `SAR_TSENS_CLK_DIV` writer - temperature sensor clock divider"]
+pub type SAR_TSENS_CLK_DIV_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+#[doc = "Field `SAR_TSENS_POWER_UP` reader - temperature sensor power up"]
+pub type SAR_TSENS_POWER_UP_R = crate::BitReader;
+#[doc = "Field `SAR_TSENS_POWER_UP` writer - temperature sensor power up"]
+pub type SAR_TSENS_POWER_UP_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_TSENS_POWER_UP_FORCE` reader - 1: dump out & power up controlled by SW 0: by FSM"]
+pub type SAR_TSENS_POWER_UP_FORCE_R = crate::BitReader;
+#[doc = "Field `SAR_TSENS_POWER_UP_FORCE` writer - 1: dump out & power up controlled by SW 0: by FSM"]
+pub type SAR_TSENS_POWER_UP_FORCE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAR_TSENS_DUMP_OUT` reader - temperature sensor dump out only active when reg_tsens_power_up_force = 1"]
+pub type SAR_TSENS_DUMP_OUT_R = crate::BitReader;
+#[doc = "Field `SAR_TSENS_DUMP_OUT` writer - temperature sensor dump out only active when reg_tsens_power_up_force = 1"]
+pub type SAR_TSENS_DUMP_OUT_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 0:7 - temperature sensor data out"]
+    #[inline(always)]
+    pub fn sar_tsens_out(&self) -> SAR_TSENS_OUT_R {
+        SAR_TSENS_OUT_R::new((self.bits & 0xff) as u8)
+    }
+    #[doc = "Bit 8 - indicate temperature sensor out ready"]
+    #[inline(always)]
+    pub fn sar_tsens_ready(&self) -> SAR_TSENS_READY_R {
+        SAR_TSENS_READY_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 12 - enable temperature sensor to send out interrupt"]
+    #[inline(always)]
+    pub fn sar_tsens_int_en(&self) -> SAR_TSENS_INT_EN_R {
+        SAR_TSENS_INT_EN_R::new(((self.bits >> 12) & 1) != 0)
+    }
+    #[doc = "Bit 13 - invert temperature sensor data"]
+    #[inline(always)]
+    pub fn sar_tsens_in_inv(&self) -> SAR_TSENS_IN_INV_R {
+        SAR_TSENS_IN_INV_R::new(((self.bits >> 13) & 1) != 0)
+    }
+    #[doc = "Bits 14:21 - temperature sensor clock divider"]
+    #[inline(always)]
+    pub fn sar_tsens_clk_div(&self) -> SAR_TSENS_CLK_DIV_R {
+        SAR_TSENS_CLK_DIV_R::new(((self.bits >> 14) & 0xff) as u8)
+    }
+    #[doc = "Bit 22 - temperature sensor power up"]
+    #[inline(always)]
+    pub fn sar_tsens_power_up(&self) -> SAR_TSENS_POWER_UP_R {
+        SAR_TSENS_POWER_UP_R::new(((self.bits >> 22) & 1) != 0)
+    }
+    #[doc = "Bit 23 - 1: dump out & power up controlled by SW 0: by FSM"]
+    #[inline(always)]
+    pub fn sar_tsens_power_up_force(&self) -> SAR_TSENS_POWER_UP_FORCE_R {
+        SAR_TSENS_POWER_UP_FORCE_R::new(((self.bits >> 23) & 1) != 0)
+    }
+    #[doc = "Bit 24 - temperature sensor dump out only active when reg_tsens_power_up_force = 1"]
+    #[inline(always)]
+    pub fn sar_tsens_dump_out(&self) -> SAR_TSENS_DUMP_OUT_R {
+        SAR_TSENS_DUMP_OUT_R::new(((self.bits >> 24) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_TSENS_CTRL")
+            .field("sar_tsens_out", &self.sar_tsens_out())
+            .field("sar_tsens_ready", &self.sar_tsens_ready())
+            .field("sar_tsens_int_en", &self.sar_tsens_int_en())
+            .field("sar_tsens_in_inv", &self.sar_tsens_in_inv())
+            .field("sar_tsens_clk_div", &self.sar_tsens_clk_div())
+            .field("sar_tsens_power_up", &self.sar_tsens_power_up())
+            .field("sar_tsens_power_up_force", &self.sar_tsens_power_up_force())
+            .field("sar_tsens_dump_out", &self.sar_tsens_dump_out())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 12 - enable temperature sensor to send out interrupt"]
+    #[inline(always)]
+    pub fn sar_tsens_int_en(&mut self) -> SAR_TSENS_INT_EN_W<SAR_TSENS_CTRL_SPEC> {
+        SAR_TSENS_INT_EN_W::new(self, 12)
+    }
+    #[doc = "Bit 13 - invert temperature sensor data"]
+    #[inline(always)]
+    pub fn sar_tsens_in_inv(&mut self) -> SAR_TSENS_IN_INV_W<SAR_TSENS_CTRL_SPEC> {
+        SAR_TSENS_IN_INV_W::new(self, 13)
+    }
+    #[doc = "Bits 14:21 - temperature sensor clock divider"]
+    #[inline(always)]
+    pub fn sar_tsens_clk_div(&mut self) -> SAR_TSENS_CLK_DIV_W<SAR_TSENS_CTRL_SPEC> {
+        SAR_TSENS_CLK_DIV_W::new(self, 14)
+    }
+    #[doc = "Bit 22 - temperature sensor power up"]
+    #[inline(always)]
+    pub fn sar_tsens_power_up(&mut self) -> SAR_TSENS_POWER_UP_W<SAR_TSENS_CTRL_SPEC> {
+        SAR_TSENS_POWER_UP_W::new(self, 22)
+    }
+    #[doc = "Bit 23 - 1: dump out & power up controlled by SW 0: by FSM"]
+    #[inline(always)]
+    pub fn sar_tsens_power_up_force(&mut self) -> SAR_TSENS_POWER_UP_FORCE_W<SAR_TSENS_CTRL_SPEC> {
+        SAR_TSENS_POWER_UP_FORCE_W::new(self, 23)
+    }
+    #[doc = "Bit 24 - temperature sensor dump out only active when reg_tsens_power_up_force = 1"]
+    #[inline(always)]
+    pub fn sar_tsens_dump_out(&mut self) -> SAR_TSENS_DUMP_OUT_W<SAR_TSENS_CTRL_SPEC> {
+        SAR_TSENS_DUMP_OUT_W::new(self, 24)
+    }
+}
+#[doc = "configure tsens controller\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_tsens_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_tsens_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_TSENS_CTRL_SPEC;
+impl crate::RegisterSpec for SAR_TSENS_CTRL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_tsens_ctrl::R`](R) reader structure"]
+impl crate::Readable for SAR_TSENS_CTRL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sar_tsens_ctrl::W`](W) writer structure"]
+impl crate::Writable for SAR_TSENS_CTRL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SAR_TSENS_CTRL to value 0x0001_9000"]
+impl crate::Resettable for SAR_TSENS_CTRL_SPEC {
+    const RESET_VALUE: u32 = 0x0001_9000;
+}

vendor/esp32s3/src/sens/sar_tsens_ctrl2.rs

@@ -0,0 +1,77 @@
+#[doc = "Register `SAR_TSENS_CTRL2` reader"]
+pub type R = crate::R<SAR_TSENS_CTRL2_SPEC>;
+#[doc = "Register `SAR_TSENS_CTRL2` writer"]
+pub type W = crate::W<SAR_TSENS_CTRL2_SPEC>;
+#[doc = "Field `SAR_TSENS_XPD_WAIT` reader - no public"]
+pub type SAR_TSENS_XPD_WAIT_R = crate::FieldReader<u16>;
+#[doc = "Field `SAR_TSENS_XPD_WAIT` writer - no public"]
+pub type SAR_TSENS_XPD_WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
+#[doc = "Field `SAR_TSENS_XPD_FORCE` reader - no public"]
+pub type SAR_TSENS_XPD_FORCE_R = crate::FieldReader;
+#[doc = "Field `SAR_TSENS_XPD_FORCE` writer - no public"]
+pub type SAR_TSENS_XPD_FORCE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `SAR_TSENS_CLK_INV` reader - no public"]
+pub type SAR_TSENS_CLK_INV_R = crate::BitReader;
+#[doc = "Field `SAR_TSENS_CLK_INV` writer - no public"]
+pub type SAR_TSENS_CLK_INV_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 0:11 - no public"]
+    #[inline(always)]
+    pub fn sar_tsens_xpd_wait(&self) -> SAR_TSENS_XPD_WAIT_R {
+        SAR_TSENS_XPD_WAIT_R::new((self.bits & 0x0fff) as u16)
+    }
+    #[doc = "Bits 12:13 - no public"]
+    #[inline(always)]
+    pub fn sar_tsens_xpd_force(&self) -> SAR_TSENS_XPD_FORCE_R {
+        SAR_TSENS_XPD_FORCE_R::new(((self.bits >> 12) & 3) as u8)
+    }
+    #[doc = "Bit 14 - no public"]
+    #[inline(always)]
+    pub fn sar_tsens_clk_inv(&self) -> SAR_TSENS_CLK_INV_R {
+        SAR_TSENS_CLK_INV_R::new(((self.bits >> 14) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("SAR_TSENS_CTRL2")
+            .field("sar_tsens_xpd_wait", &self.sar_tsens_xpd_wait())
+            .field("sar_tsens_xpd_force", &self.sar_tsens_xpd_force())
+            .field("sar_tsens_clk_inv", &self.sar_tsens_clk_inv())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:11 - no public"]
+    #[inline(always)]
+    pub fn sar_tsens_xpd_wait(&mut self) -> SAR_TSENS_XPD_WAIT_W<SAR_TSENS_CTRL2_SPEC> {
+        SAR_TSENS_XPD_WAIT_W::new(self, 0)
+    }
+    #[doc = "Bits 12:13 - no public"]
+    #[inline(always)]
+    pub fn sar_tsens_xpd_force(&mut self) -> SAR_TSENS_XPD_FORCE_W<SAR_TSENS_CTRL2_SPEC> {
+        SAR_TSENS_XPD_FORCE_W::new(self, 12)
+    }
+    #[doc = "Bit 14 - no public"]
+    #[inline(always)]
+    pub fn sar_tsens_clk_inv(&mut self) -> SAR_TSENS_CLK_INV_W<SAR_TSENS_CTRL2_SPEC> {
+        SAR_TSENS_CLK_INV_W::new(self, 14)
+    }
+}
+#[doc = "configure tsens controller\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_tsens_ctrl2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_tsens_ctrl2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct SAR_TSENS_CTRL2_SPEC;
+impl crate::RegisterSpec for SAR_TSENS_CTRL2_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`sar_tsens_ctrl2::R`](R) reader structure"]
+impl crate::Readable for SAR_TSENS_CTRL2_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`sar_tsens_ctrl2::W`](W) writer structure"]
+impl crate::Writable for SAR_TSENS_CTRL2_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets SAR_TSENS_CTRL2 to value 0x4002"]
+impl crate::Resettable for SAR_TSENS_CTRL2_SPEC {
+    const RESET_VALUE: u32 = 0x4002;
+}