feat: add display UI with splash screen, dashboard, and RSSI sparkline
Implement full SSD1306 OLED display support: - Splash screen on boot (1.5s) with project name, version, board - Dashboard showing radio state, config, counters, RSSI/SNR - RSSI history sparkline (64-sample ring buffer, 2px-wide bars) - DisplayOn/DisplayOff host commands routed via dedicated channel - Pure render functions against generic DrawTarget (no hardware coupling) - Display on/off control bypasses radio task entirely Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
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@@ -0,0 +1,52 @@
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#[doc = "Register `APB_PERIPHERAL_ACCESS_0` reader"]
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pub type R = crate::R<APB_PERIPHERAL_ACCESS_0_SPEC>;
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#[doc = "Register `APB_PERIPHERAL_ACCESS_0` writer"]
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pub type W = crate::W<APB_PERIPHERAL_ACCESS_0_SPEC>;
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#[doc = "Field `APB_PERIPHERAL_ACCESS_LOCK` reader - Set 1 to lock APB peripheral Configuration Register."]
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pub type APB_PERIPHERAL_ACCESS_LOCK_R = crate::BitReader;
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#[doc = "Field `APB_PERIPHERAL_ACCESS_LOCK` writer - Set 1 to lock APB peripheral Configuration Register."]
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pub type APB_PERIPHERAL_ACCESS_LOCK_W<'a, REG> = crate::BitWriter<'a, REG>;
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impl R {
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#[doc = "Bit 0 - Set 1 to lock APB peripheral Configuration Register."]
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#[inline(always)]
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pub fn apb_peripheral_access_lock(&self) -> APB_PERIPHERAL_ACCESS_LOCK_R {
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APB_PERIPHERAL_ACCESS_LOCK_R::new((self.bits & 1) != 0)
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}
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}
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#[cfg(feature = "impl-register-debug")]
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impl core::fmt::Debug for R {
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fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
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f.debug_struct("APB_PERIPHERAL_ACCESS_0")
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.field(
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"apb_peripheral_access_lock",
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&self.apb_peripheral_access_lock(),
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)
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.finish()
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}
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}
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impl W {
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#[doc = "Bit 0 - Set 1 to lock APB peripheral Configuration Register."]
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#[inline(always)]
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pub fn apb_peripheral_access_lock(
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&mut self,
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) -> APB_PERIPHERAL_ACCESS_LOCK_W<APB_PERIPHERAL_ACCESS_0_SPEC> {
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APB_PERIPHERAL_ACCESS_LOCK_W::new(self, 0)
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}
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}
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#[doc = "APB peripheral configuration register 0.\n\nYou can [`read`](crate::Reg::read) this register and get [`apb_peripheral_access_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb_peripheral_access_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
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pub struct APB_PERIPHERAL_ACCESS_0_SPEC;
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impl crate::RegisterSpec for APB_PERIPHERAL_ACCESS_0_SPEC {
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type Ux = u32;
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}
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#[doc = "`read()` method returns [`apb_peripheral_access_0::R`](R) reader structure"]
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impl crate::Readable for APB_PERIPHERAL_ACCESS_0_SPEC {}
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#[doc = "`write(|w| ..)` method takes [`apb_peripheral_access_0::W`](W) writer structure"]
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impl crate::Writable for APB_PERIPHERAL_ACCESS_0_SPEC {
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type Safety = crate::Unsafe;
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const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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}
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#[doc = "`reset()` method sets APB_PERIPHERAL_ACCESS_0 to value 0"]
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impl crate::Resettable for APB_PERIPHERAL_ACCESS_0_SPEC {
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const RESET_VALUE: u32 = 0;
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}
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@@ -0,0 +1,52 @@
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#[doc = "Register `APB_PERIPHERAL_ACCESS_1` reader"]
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pub type R = crate::R<APB_PERIPHERAL_ACCESS_1_SPEC>;
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#[doc = "Register `APB_PERIPHERAL_ACCESS_1` writer"]
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pub type W = crate::W<APB_PERIPHERAL_ACCESS_1_SPEC>;
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#[doc = "Field `APB_PERIPHERAL_ACCESS_SPLIT_BURST` reader - Set 1 to support split function for AHB access to APB peripherals."]
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pub type APB_PERIPHERAL_ACCESS_SPLIT_BURST_R = crate::BitReader;
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#[doc = "Field `APB_PERIPHERAL_ACCESS_SPLIT_BURST` writer - Set 1 to support split function for AHB access to APB peripherals."]
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pub type APB_PERIPHERAL_ACCESS_SPLIT_BURST_W<'a, REG> = crate::BitWriter<'a, REG>;
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impl R {
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#[doc = "Bit 0 - Set 1 to support split function for AHB access to APB peripherals."]
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#[inline(always)]
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pub fn apb_peripheral_access_split_burst(&self) -> APB_PERIPHERAL_ACCESS_SPLIT_BURST_R {
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APB_PERIPHERAL_ACCESS_SPLIT_BURST_R::new((self.bits & 1) != 0)
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}
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}
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#[cfg(feature = "impl-register-debug")]
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impl core::fmt::Debug for R {
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fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
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f.debug_struct("APB_PERIPHERAL_ACCESS_1")
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.field(
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"apb_peripheral_access_split_burst",
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&self.apb_peripheral_access_split_burst(),
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)
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.finish()
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}
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}
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impl W {
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#[doc = "Bit 0 - Set 1 to support split function for AHB access to APB peripherals."]
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#[inline(always)]
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pub fn apb_peripheral_access_split_burst(
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&mut self,
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) -> APB_PERIPHERAL_ACCESS_SPLIT_BURST_W<APB_PERIPHERAL_ACCESS_1_SPEC> {
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APB_PERIPHERAL_ACCESS_SPLIT_BURST_W::new(self, 0)
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}
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}
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#[doc = "APB peripheral configuration register 1.\n\nYou can [`read`](crate::Reg::read) this register and get [`apb_peripheral_access_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb_peripheral_access_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
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pub struct APB_PERIPHERAL_ACCESS_1_SPEC;
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impl crate::RegisterSpec for APB_PERIPHERAL_ACCESS_1_SPEC {
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type Ux = u32;
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}
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#[doc = "`read()` method returns [`apb_peripheral_access_1::R`](R) reader structure"]
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impl crate::Readable for APB_PERIPHERAL_ACCESS_1_SPEC {}
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#[doc = "`write(|w| ..)` method takes [`apb_peripheral_access_1::W`](W) writer structure"]
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impl crate::Writable for APB_PERIPHERAL_ACCESS_1_SPEC {
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type Safety = crate::Unsafe;
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const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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}
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#[doc = "`reset()` method sets APB_PERIPHERAL_ACCESS_1 to value 0x01"]
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impl crate::Resettable for APB_PERIPHERAL_ACCESS_1_SPEC {
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const RESET_VALUE: u32 = 0x01;
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}
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@@ -0,0 +1,52 @@
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#[doc = "Register `BACKUP_BUS_PMS_CONSTRAIN_0` reader"]
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pub type R = crate::R<BACKUP_BUS_PMS_CONSTRAIN_0_SPEC>;
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#[doc = "Register `BACKUP_BUS_PMS_CONSTRAIN_0` writer"]
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pub type W = crate::W<BACKUP_BUS_PMS_CONSTRAIN_0_SPEC>;
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#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_LOCK` reader - Set 1 to lock BackUp permission configuration registers."]
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pub type BACKUP_BUS_PMS_CONSTRAIN_LOCK_R = crate::BitReader;
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#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_LOCK` writer - Set 1 to lock BackUp permission configuration registers."]
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pub type BACKUP_BUS_PMS_CONSTRAIN_LOCK_W<'a, REG> = crate::BitWriter<'a, REG>;
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impl R {
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#[doc = "Bit 0 - Set 1 to lock BackUp permission configuration registers."]
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#[inline(always)]
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pub fn backup_bus_pms_constrain_lock(&self) -> BACKUP_BUS_PMS_CONSTRAIN_LOCK_R {
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BACKUP_BUS_PMS_CONSTRAIN_LOCK_R::new((self.bits & 1) != 0)
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}
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}
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#[cfg(feature = "impl-register-debug")]
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impl core::fmt::Debug for R {
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fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
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f.debug_struct("BACKUP_BUS_PMS_CONSTRAIN_0")
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.field(
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"backup_bus_pms_constrain_lock",
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&self.backup_bus_pms_constrain_lock(),
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)
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.finish()
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}
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}
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impl W {
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#[doc = "Bit 0 - Set 1 to lock BackUp permission configuration registers."]
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#[inline(always)]
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pub fn backup_bus_pms_constrain_lock(
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&mut self,
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) -> BACKUP_BUS_PMS_CONSTRAIN_LOCK_W<BACKUP_BUS_PMS_CONSTRAIN_0_SPEC> {
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BACKUP_BUS_PMS_CONSTRAIN_LOCK_W::new(self, 0)
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}
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}
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#[doc = "BackUp access peripherals permission configuration register 0.\n\nYou can [`read`](crate::Reg::read) this register and get [`backup_bus_pms_constrain_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`backup_bus_pms_constrain_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
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pub struct BACKUP_BUS_PMS_CONSTRAIN_0_SPEC;
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impl crate::RegisterSpec for BACKUP_BUS_PMS_CONSTRAIN_0_SPEC {
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type Ux = u32;
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}
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#[doc = "`read()` method returns [`backup_bus_pms_constrain_0::R`](R) reader structure"]
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impl crate::Readable for BACKUP_BUS_PMS_CONSTRAIN_0_SPEC {}
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#[doc = "`write(|w| ..)` method takes [`backup_bus_pms_constrain_0::W`](W) writer structure"]
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impl crate::Writable for BACKUP_BUS_PMS_CONSTRAIN_0_SPEC {
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type Safety = crate::Unsafe;
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const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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}
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#[doc = "`reset()` method sets BACKUP_BUS_PMS_CONSTRAIN_0 to value 0"]
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impl crate::Resettable for BACKUP_BUS_PMS_CONSTRAIN_0_SPEC {
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const RESET_VALUE: u32 = 0;
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}
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@@ -0,0 +1,292 @@
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#[doc = "Register `BACKUP_BUS_PMS_CONSTRAIN_1` reader"]
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pub type R = crate::R<BACKUP_BUS_PMS_CONSTRAIN_1_SPEC>;
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#[doc = "Register `BACKUP_BUS_PMS_CONSTRAIN_1` writer"]
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pub type W = crate::W<BACKUP_BUS_PMS_CONSTRAIN_1_SPEC>;
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#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_UART` reader - BackUp access uart permission."]
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pub type BACKUP_BUS_PMS_CONSTRAIN_UART_R = crate::FieldReader;
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#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_UART` writer - BackUp access uart permission."]
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pub type BACKUP_BUS_PMS_CONSTRAIN_UART_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
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#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1` reader - BackUp access g0spi_1 permission."]
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pub type BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_R = crate::FieldReader;
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#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1` writer - BackUp access g0spi_1 permission."]
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pub type BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
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#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0` reader - BackUp access g0spi_0 permission."]
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pub type BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_R = crate::FieldReader;
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#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0` writer - BackUp access g0spi_0 permission."]
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pub type BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
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#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_GPIO` reader - BackUp access gpio permission."]
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pub type BACKUP_BUS_PMS_CONSTRAIN_GPIO_R = crate::FieldReader;
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#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_GPIO` writer - BackUp access gpio permission."]
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pub type BACKUP_BUS_PMS_CONSTRAIN_GPIO_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
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#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_FE2` reader - BackUp access fe2 permission."]
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pub type BACKUP_BUS_PMS_CONSTRAIN_FE2_R = crate::FieldReader;
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#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_FE2` writer - BackUp access fe2 permission."]
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pub type BACKUP_BUS_PMS_CONSTRAIN_FE2_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
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#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_FE` reader - BackUp access fe permission."]
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pub type BACKUP_BUS_PMS_CONSTRAIN_FE_R = crate::FieldReader;
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#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_FE` writer - BackUp access fe permission."]
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pub type BACKUP_BUS_PMS_CONSTRAIN_FE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
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#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_RTC` reader - BackUp access rtc permission."]
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pub type BACKUP_BUS_PMS_CONSTRAIN_RTC_R = crate::FieldReader;
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#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_RTC` writer - BackUp access rtc permission."]
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pub type BACKUP_BUS_PMS_CONSTRAIN_RTC_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
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#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_IO_MUX` reader - BackUp access io_mux permission."]
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pub type BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_R = crate::FieldReader;
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#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_IO_MUX` writer - BackUp access io_mux permission."]
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pub type BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
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#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_HINF` reader - BackUp access hinf permission."]
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pub type BACKUP_BUS_PMS_CONSTRAIN_HINF_R = crate::FieldReader;
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#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_HINF` writer - BackUp access hinf permission."]
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pub type BACKUP_BUS_PMS_CONSTRAIN_HINF_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
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#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_MISC` reader - BackUp access misc permission."]
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pub type BACKUP_BUS_PMS_CONSTRAIN_MISC_R = crate::FieldReader;
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#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_MISC` writer - BackUp access misc permission."]
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pub type BACKUP_BUS_PMS_CONSTRAIN_MISC_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
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#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_I2C` reader - BackUp access i2c permission."]
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pub type BACKUP_BUS_PMS_CONSTRAIN_I2C_R = crate::FieldReader;
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#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_I2C` writer - BackUp access i2c permission."]
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pub type BACKUP_BUS_PMS_CONSTRAIN_I2C_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
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#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_I2S0` reader - BackUp access i2s0 permission."]
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pub type BACKUP_BUS_PMS_CONSTRAIN_I2S0_R = crate::FieldReader;
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#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_I2S0` writer - BackUp access i2s0 permission."]
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pub type BACKUP_BUS_PMS_CONSTRAIN_I2S0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
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#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_UART1` reader - BackUp access uart1 permission."]
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pub type BACKUP_BUS_PMS_CONSTRAIN_UART1_R = crate::FieldReader;
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#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_UART1` writer - BackUp access uart1 permission."]
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pub type BACKUP_BUS_PMS_CONSTRAIN_UART1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
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impl R {
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#[doc = "Bits 0:1 - BackUp access uart permission."]
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#[inline(always)]
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pub fn backup_bus_pms_constrain_uart(&self) -> BACKUP_BUS_PMS_CONSTRAIN_UART_R {
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BACKUP_BUS_PMS_CONSTRAIN_UART_R::new((self.bits & 3) as u8)
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}
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#[doc = "Bits 2:3 - BackUp access g0spi_1 permission."]
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#[inline(always)]
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pub fn backup_bus_pms_constrain_g0spi_1(&self) -> BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_R {
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BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_R::new(((self.bits >> 2) & 3) as u8)
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}
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#[doc = "Bits 4:5 - BackUp access g0spi_0 permission."]
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#[inline(always)]
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pub fn backup_bus_pms_constrain_g0spi_0(&self) -> BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_R {
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BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_R::new(((self.bits >> 4) & 3) as u8)
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}
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#[doc = "Bits 6:7 - BackUp access gpio permission."]
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#[inline(always)]
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pub fn backup_bus_pms_constrain_gpio(&self) -> BACKUP_BUS_PMS_CONSTRAIN_GPIO_R {
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BACKUP_BUS_PMS_CONSTRAIN_GPIO_R::new(((self.bits >> 6) & 3) as u8)
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}
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||||
#[doc = "Bits 8:9 - BackUp access fe2 permission."]
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#[inline(always)]
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pub fn backup_bus_pms_constrain_fe2(&self) -> BACKUP_BUS_PMS_CONSTRAIN_FE2_R {
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BACKUP_BUS_PMS_CONSTRAIN_FE2_R::new(((self.bits >> 8) & 3) as u8)
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}
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||||
#[doc = "Bits 10:11 - BackUp access fe permission."]
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#[inline(always)]
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pub fn backup_bus_pms_constrain_fe(&self) -> BACKUP_BUS_PMS_CONSTRAIN_FE_R {
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BACKUP_BUS_PMS_CONSTRAIN_FE_R::new(((self.bits >> 10) & 3) as u8)
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}
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#[doc = "Bits 14:15 - BackUp access rtc permission."]
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#[inline(always)]
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pub fn backup_bus_pms_constrain_rtc(&self) -> BACKUP_BUS_PMS_CONSTRAIN_RTC_R {
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BACKUP_BUS_PMS_CONSTRAIN_RTC_R::new(((self.bits >> 14) & 3) as u8)
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||||
}
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||||
#[doc = "Bits 16:17 - BackUp access io_mux permission."]
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||||
#[inline(always)]
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pub fn backup_bus_pms_constrain_io_mux(&self) -> BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_R {
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||||
BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_R::new(((self.bits >> 16) & 3) as u8)
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||||
}
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||||
#[doc = "Bits 20:21 - BackUp access hinf permission."]
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||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_hinf(&self) -> BACKUP_BUS_PMS_CONSTRAIN_HINF_R {
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||||
BACKUP_BUS_PMS_CONSTRAIN_HINF_R::new(((self.bits >> 20) & 3) as u8)
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||||
}
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||||
#[doc = "Bits 24:25 - BackUp access misc permission."]
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||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_misc(&self) -> BACKUP_BUS_PMS_CONSTRAIN_MISC_R {
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||||
BACKUP_BUS_PMS_CONSTRAIN_MISC_R::new(((self.bits >> 24) & 3) as u8)
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||||
}
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||||
#[doc = "Bits 26:27 - BackUp access i2c permission."]
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||||
#[inline(always)]
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||||
pub fn backup_bus_pms_constrain_i2c(&self) -> BACKUP_BUS_PMS_CONSTRAIN_I2C_R {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_I2C_R::new(((self.bits >> 26) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 28:29 - BackUp access i2s0 permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_i2s0(&self) -> BACKUP_BUS_PMS_CONSTRAIN_I2S0_R {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_I2S0_R::new(((self.bits >> 28) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 30:31 - BackUp access uart1 permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_uart1(&self) -> BACKUP_BUS_PMS_CONSTRAIN_UART1_R {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_UART1_R::new(((self.bits >> 30) & 3) as u8)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("BACKUP_BUS_PMS_CONSTRAIN_1")
|
||||
.field(
|
||||
"backup_bus_pms_constrain_uart",
|
||||
&self.backup_bus_pms_constrain_uart(),
|
||||
)
|
||||
.field(
|
||||
"backup_bus_pms_constrain_g0spi_1",
|
||||
&self.backup_bus_pms_constrain_g0spi_1(),
|
||||
)
|
||||
.field(
|
||||
"backup_bus_pms_constrain_g0spi_0",
|
||||
&self.backup_bus_pms_constrain_g0spi_0(),
|
||||
)
|
||||
.field(
|
||||
"backup_bus_pms_constrain_gpio",
|
||||
&self.backup_bus_pms_constrain_gpio(),
|
||||
)
|
||||
.field(
|
||||
"backup_bus_pms_constrain_fe2",
|
||||
&self.backup_bus_pms_constrain_fe2(),
|
||||
)
|
||||
.field(
|
||||
"backup_bus_pms_constrain_fe",
|
||||
&self.backup_bus_pms_constrain_fe(),
|
||||
)
|
||||
.field(
|
||||
"backup_bus_pms_constrain_rtc",
|
||||
&self.backup_bus_pms_constrain_rtc(),
|
||||
)
|
||||
.field(
|
||||
"backup_bus_pms_constrain_io_mux",
|
||||
&self.backup_bus_pms_constrain_io_mux(),
|
||||
)
|
||||
.field(
|
||||
"backup_bus_pms_constrain_hinf",
|
||||
&self.backup_bus_pms_constrain_hinf(),
|
||||
)
|
||||
.field(
|
||||
"backup_bus_pms_constrain_misc",
|
||||
&self.backup_bus_pms_constrain_misc(),
|
||||
)
|
||||
.field(
|
||||
"backup_bus_pms_constrain_i2c",
|
||||
&self.backup_bus_pms_constrain_i2c(),
|
||||
)
|
||||
.field(
|
||||
"backup_bus_pms_constrain_i2s0",
|
||||
&self.backup_bus_pms_constrain_i2s0(),
|
||||
)
|
||||
.field(
|
||||
"backup_bus_pms_constrain_uart1",
|
||||
&self.backup_bus_pms_constrain_uart1(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:1 - BackUp access uart permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_uart(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_UART_W<BACKUP_BUS_PMS_CONSTRAIN_1_SPEC> {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_UART_W::new(self, 0)
|
||||
}
|
||||
#[doc = "Bits 2:3 - BackUp access g0spi_1 permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_g0spi_1(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_W<BACKUP_BUS_PMS_CONSTRAIN_1_SPEC> {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_W::new(self, 2)
|
||||
}
|
||||
#[doc = "Bits 4:5 - BackUp access g0spi_0 permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_g0spi_0(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_W<BACKUP_BUS_PMS_CONSTRAIN_1_SPEC> {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_W::new(self, 4)
|
||||
}
|
||||
#[doc = "Bits 6:7 - BackUp access gpio permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_gpio(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_GPIO_W<BACKUP_BUS_PMS_CONSTRAIN_1_SPEC> {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_GPIO_W::new(self, 6)
|
||||
}
|
||||
#[doc = "Bits 8:9 - BackUp access fe2 permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_fe2(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_FE2_W<BACKUP_BUS_PMS_CONSTRAIN_1_SPEC> {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_FE2_W::new(self, 8)
|
||||
}
|
||||
#[doc = "Bits 10:11 - BackUp access fe permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_fe(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_FE_W<BACKUP_BUS_PMS_CONSTRAIN_1_SPEC> {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_FE_W::new(self, 10)
|
||||
}
|
||||
#[doc = "Bits 14:15 - BackUp access rtc permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_rtc(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_RTC_W<BACKUP_BUS_PMS_CONSTRAIN_1_SPEC> {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_RTC_W::new(self, 14)
|
||||
}
|
||||
#[doc = "Bits 16:17 - BackUp access io_mux permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_io_mux(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_W<BACKUP_BUS_PMS_CONSTRAIN_1_SPEC> {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_W::new(self, 16)
|
||||
}
|
||||
#[doc = "Bits 20:21 - BackUp access hinf permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_hinf(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_HINF_W<BACKUP_BUS_PMS_CONSTRAIN_1_SPEC> {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_HINF_W::new(self, 20)
|
||||
}
|
||||
#[doc = "Bits 24:25 - BackUp access misc permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_misc(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_MISC_W<BACKUP_BUS_PMS_CONSTRAIN_1_SPEC> {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_MISC_W::new(self, 24)
|
||||
}
|
||||
#[doc = "Bits 26:27 - BackUp access i2c permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_i2c(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_I2C_W<BACKUP_BUS_PMS_CONSTRAIN_1_SPEC> {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_I2C_W::new(self, 26)
|
||||
}
|
||||
#[doc = "Bits 28:29 - BackUp access i2s0 permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_i2s0(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_I2S0_W<BACKUP_BUS_PMS_CONSTRAIN_1_SPEC> {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_I2S0_W::new(self, 28)
|
||||
}
|
||||
#[doc = "Bits 30:31 - BackUp access uart1 permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_uart1(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_UART1_W<BACKUP_BUS_PMS_CONSTRAIN_1_SPEC> {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_UART1_W::new(self, 30)
|
||||
}
|
||||
}
|
||||
#[doc = "BackUp access peripherals permission configuration register 1.\n\nYou can [`read`](crate::Reg::read) this register and get [`backup_bus_pms_constrain_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`backup_bus_pms_constrain_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct BACKUP_BUS_PMS_CONSTRAIN_1_SPEC;
|
||||
impl crate::RegisterSpec for BACKUP_BUS_PMS_CONSTRAIN_1_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`backup_bus_pms_constrain_1::R`](R) reader structure"]
|
||||
impl crate::Readable for BACKUP_BUS_PMS_CONSTRAIN_1_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`backup_bus_pms_constrain_1::W`](W) writer structure"]
|
||||
impl crate::Writable for BACKUP_BUS_PMS_CONSTRAIN_1_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets BACKUP_BUS_PMS_CONSTRAIN_1 to value 0xff33_cfff"]
|
||||
impl crate::Resettable for BACKUP_BUS_PMS_CONSTRAIN_1_SPEC {
|
||||
const RESET_VALUE: u32 = 0xff33_cfff;
|
||||
}
|
||||
@@ -0,0 +1,312 @@
|
||||
#[doc = "Register `BACKUP_BUS_PMS_CONSTRAIN_2` reader"]
|
||||
pub type R = crate::R<BACKUP_BUS_PMS_CONSTRAIN_2_SPEC>;
|
||||
#[doc = "Register `BACKUP_BUS_PMS_CONSTRAIN_2` writer"]
|
||||
pub type W = crate::W<BACKUP_BUS_PMS_CONSTRAIN_2_SPEC>;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_BT` reader - BackUp access bt permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_BT_R = crate::FieldReader;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_BT` writer - BackUp access bt permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_BT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0` reader - BackUp access i2c_ext0 permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_R = crate::FieldReader;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0` writer - BackUp access i2c_ext0 permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_UHCI0` reader - BackUp access uhci0 permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_UHCI0_R = crate::FieldReader;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_UHCI0` writer - BackUp access uhci0 permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_UHCI0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_SLCHOST` reader - BackUp access slchost permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_SLCHOST_R = crate::FieldReader;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_SLCHOST` writer - BackUp access slchost permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_SLCHOST_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_RMT` reader - BackUp access rmt permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_RMT_R = crate::FieldReader;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_RMT` writer - BackUp access rmt permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_RMT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_PCNT` reader - BackUp access pcnt permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_PCNT_R = crate::FieldReader;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_PCNT` writer - BackUp access pcnt permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_PCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_SLC` reader - BackUp access slc permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_SLC_R = crate::FieldReader;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_SLC` writer - BackUp access slc permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_SLC_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_LEDC` reader - BackUp access ledc permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_LEDC_R = crate::FieldReader;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_LEDC` writer - BackUp access ledc permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_LEDC_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_BACKUP` reader - BackUp access backup permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_BACKUP_R = crate::FieldReader;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_BACKUP` writer - BackUp access backup permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_BACKUP_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_BB` reader - BackUp access bb permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_BB_R = crate::FieldReader;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_BB` writer - BackUp access bb permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_BB_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_PWM0` reader - BackUp access pwm0 permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_PWM0_R = crate::FieldReader;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_PWM0` writer - BackUp access pwm0 permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_PWM0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP` reader - BackUp access timergroup permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_R = crate::FieldReader;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP` writer - BackUp access timergroup permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1` reader - BackUp access timergroup1 permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_R = crate::FieldReader;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1` writer - BackUp access timergroup1 permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER` reader - BackUp access systimer permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_R = crate::FieldReader;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER` writer - BackUp access systimer permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:1 - BackUp access bt permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_bt(&self) -> BACKUP_BUS_PMS_CONSTRAIN_BT_R {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_BT_R::new((self.bits & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 4:5 - BackUp access i2c_ext0 permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_i2c_ext0(&self) -> BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_R {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_R::new(((self.bits >> 4) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 6:7 - BackUp access uhci0 permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_uhci0(&self) -> BACKUP_BUS_PMS_CONSTRAIN_UHCI0_R {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_UHCI0_R::new(((self.bits >> 6) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 8:9 - BackUp access slchost permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_slchost(&self) -> BACKUP_BUS_PMS_CONSTRAIN_SLCHOST_R {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_SLCHOST_R::new(((self.bits >> 8) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 10:11 - BackUp access rmt permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_rmt(&self) -> BACKUP_BUS_PMS_CONSTRAIN_RMT_R {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_RMT_R::new(((self.bits >> 10) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 12:13 - BackUp access pcnt permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_pcnt(&self) -> BACKUP_BUS_PMS_CONSTRAIN_PCNT_R {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_PCNT_R::new(((self.bits >> 12) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 14:15 - BackUp access slc permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_slc(&self) -> BACKUP_BUS_PMS_CONSTRAIN_SLC_R {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_SLC_R::new(((self.bits >> 14) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 16:17 - BackUp access ledc permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_ledc(&self) -> BACKUP_BUS_PMS_CONSTRAIN_LEDC_R {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_LEDC_R::new(((self.bits >> 16) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 18:19 - BackUp access backup permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_backup(&self) -> BACKUP_BUS_PMS_CONSTRAIN_BACKUP_R {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_BACKUP_R::new(((self.bits >> 18) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 22:23 - BackUp access bb permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_bb(&self) -> BACKUP_BUS_PMS_CONSTRAIN_BB_R {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_BB_R::new(((self.bits >> 22) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 24:25 - BackUp access pwm0 permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_pwm0(&self) -> BACKUP_BUS_PMS_CONSTRAIN_PWM0_R {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_PWM0_R::new(((self.bits >> 24) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 26:27 - BackUp access timergroup permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_timergroup(&self) -> BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_R {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_R::new(((self.bits >> 26) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 28:29 - BackUp access timergroup1 permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_timergroup1(&self) -> BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_R {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_R::new(((self.bits >> 28) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 30:31 - BackUp access systimer permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_systimer(&self) -> BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_R {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_R::new(((self.bits >> 30) & 3) as u8)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("BACKUP_BUS_PMS_CONSTRAIN_2")
|
||||
.field(
|
||||
"backup_bus_pms_constrain_bt",
|
||||
&self.backup_bus_pms_constrain_bt(),
|
||||
)
|
||||
.field(
|
||||
"backup_bus_pms_constrain_i2c_ext0",
|
||||
&self.backup_bus_pms_constrain_i2c_ext0(),
|
||||
)
|
||||
.field(
|
||||
"backup_bus_pms_constrain_uhci0",
|
||||
&self.backup_bus_pms_constrain_uhci0(),
|
||||
)
|
||||
.field(
|
||||
"backup_bus_pms_constrain_slchost",
|
||||
&self.backup_bus_pms_constrain_slchost(),
|
||||
)
|
||||
.field(
|
||||
"backup_bus_pms_constrain_rmt",
|
||||
&self.backup_bus_pms_constrain_rmt(),
|
||||
)
|
||||
.field(
|
||||
"backup_bus_pms_constrain_pcnt",
|
||||
&self.backup_bus_pms_constrain_pcnt(),
|
||||
)
|
||||
.field(
|
||||
"backup_bus_pms_constrain_slc",
|
||||
&self.backup_bus_pms_constrain_slc(),
|
||||
)
|
||||
.field(
|
||||
"backup_bus_pms_constrain_ledc",
|
||||
&self.backup_bus_pms_constrain_ledc(),
|
||||
)
|
||||
.field(
|
||||
"backup_bus_pms_constrain_backup",
|
||||
&self.backup_bus_pms_constrain_backup(),
|
||||
)
|
||||
.field(
|
||||
"backup_bus_pms_constrain_bb",
|
||||
&self.backup_bus_pms_constrain_bb(),
|
||||
)
|
||||
.field(
|
||||
"backup_bus_pms_constrain_pwm0",
|
||||
&self.backup_bus_pms_constrain_pwm0(),
|
||||
)
|
||||
.field(
|
||||
"backup_bus_pms_constrain_timergroup",
|
||||
&self.backup_bus_pms_constrain_timergroup(),
|
||||
)
|
||||
.field(
|
||||
"backup_bus_pms_constrain_timergroup1",
|
||||
&self.backup_bus_pms_constrain_timergroup1(),
|
||||
)
|
||||
.field(
|
||||
"backup_bus_pms_constrain_systimer",
|
||||
&self.backup_bus_pms_constrain_systimer(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:1 - BackUp access bt permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_bt(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_BT_W<BACKUP_BUS_PMS_CONSTRAIN_2_SPEC> {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_BT_W::new(self, 0)
|
||||
}
|
||||
#[doc = "Bits 4:5 - BackUp access i2c_ext0 permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_i2c_ext0(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_W<BACKUP_BUS_PMS_CONSTRAIN_2_SPEC> {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_W::new(self, 4)
|
||||
}
|
||||
#[doc = "Bits 6:7 - BackUp access uhci0 permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_uhci0(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_UHCI0_W<BACKUP_BUS_PMS_CONSTRAIN_2_SPEC> {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_UHCI0_W::new(self, 6)
|
||||
}
|
||||
#[doc = "Bits 8:9 - BackUp access slchost permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_slchost(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_SLCHOST_W<BACKUP_BUS_PMS_CONSTRAIN_2_SPEC> {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_SLCHOST_W::new(self, 8)
|
||||
}
|
||||
#[doc = "Bits 10:11 - BackUp access rmt permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_rmt(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_RMT_W<BACKUP_BUS_PMS_CONSTRAIN_2_SPEC> {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_RMT_W::new(self, 10)
|
||||
}
|
||||
#[doc = "Bits 12:13 - BackUp access pcnt permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_pcnt(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_PCNT_W<BACKUP_BUS_PMS_CONSTRAIN_2_SPEC> {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_PCNT_W::new(self, 12)
|
||||
}
|
||||
#[doc = "Bits 14:15 - BackUp access slc permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_slc(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_SLC_W<BACKUP_BUS_PMS_CONSTRAIN_2_SPEC> {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_SLC_W::new(self, 14)
|
||||
}
|
||||
#[doc = "Bits 16:17 - BackUp access ledc permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_ledc(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_LEDC_W<BACKUP_BUS_PMS_CONSTRAIN_2_SPEC> {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_LEDC_W::new(self, 16)
|
||||
}
|
||||
#[doc = "Bits 18:19 - BackUp access backup permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_backup(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_BACKUP_W<BACKUP_BUS_PMS_CONSTRAIN_2_SPEC> {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_BACKUP_W::new(self, 18)
|
||||
}
|
||||
#[doc = "Bits 22:23 - BackUp access bb permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_bb(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_BB_W<BACKUP_BUS_PMS_CONSTRAIN_2_SPEC> {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_BB_W::new(self, 22)
|
||||
}
|
||||
#[doc = "Bits 24:25 - BackUp access pwm0 permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_pwm0(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_PWM0_W<BACKUP_BUS_PMS_CONSTRAIN_2_SPEC> {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_PWM0_W::new(self, 24)
|
||||
}
|
||||
#[doc = "Bits 26:27 - BackUp access timergroup permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_timergroup(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_W<BACKUP_BUS_PMS_CONSTRAIN_2_SPEC> {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_W::new(self, 26)
|
||||
}
|
||||
#[doc = "Bits 28:29 - BackUp access timergroup1 permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_timergroup1(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_W<BACKUP_BUS_PMS_CONSTRAIN_2_SPEC> {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_W::new(self, 28)
|
||||
}
|
||||
#[doc = "Bits 30:31 - BackUp access systimer permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_systimer(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_W<BACKUP_BUS_PMS_CONSTRAIN_2_SPEC> {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_W::new(self, 30)
|
||||
}
|
||||
}
|
||||
#[doc = "BackUp access peripherals permission configuration register 2.\n\nYou can [`read`](crate::Reg::read) this register and get [`backup_bus_pms_constrain_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`backup_bus_pms_constrain_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct BACKUP_BUS_PMS_CONSTRAIN_2_SPEC;
|
||||
impl crate::RegisterSpec for BACKUP_BUS_PMS_CONSTRAIN_2_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`backup_bus_pms_constrain_2::R`](R) reader structure"]
|
||||
impl crate::Readable for BACKUP_BUS_PMS_CONSTRAIN_2_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`backup_bus_pms_constrain_2::W`](W) writer structure"]
|
||||
impl crate::Writable for BACKUP_BUS_PMS_CONSTRAIN_2_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets BACKUP_BUS_PMS_CONSTRAIN_2 to value 0xffcf_fff3"]
|
||||
impl crate::Resettable for BACKUP_BUS_PMS_CONSTRAIN_2_SPEC {
|
||||
const RESET_VALUE: u32 = 0xffcf_fff3;
|
||||
}
|
||||
@@ -0,0 +1,272 @@
|
||||
#[doc = "Register `BACKUP_BUS_PMS_CONSTRAIN_3` reader"]
|
||||
pub type R = crate::R<BACKUP_BUS_PMS_CONSTRAIN_3_SPEC>;
|
||||
#[doc = "Register `BACKUP_BUS_PMS_CONSTRAIN_3` writer"]
|
||||
pub type W = crate::W<BACKUP_BUS_PMS_CONSTRAIN_3_SPEC>;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_SPI_2` reader - BackUp access spi_2 permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_SPI_2_R = crate::FieldReader;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_SPI_2` writer - BackUp access spi_2 permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_SPI_2_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_SPI_3` reader - BackUp access spi_3 permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_SPI_3_R = crate::FieldReader;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_SPI_3` writer - BackUp access spi_3 permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_SPI_3_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL` reader - BackUp access apb_ctrl permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_R = crate::FieldReader;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL` writer - BackUp access apb_ctrl permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1` reader - BackUp access i2c_ext1 permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1_R = crate::FieldReader;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1` writer - BackUp access i2c_ext1 permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST` reader - BackUp access sdio_host permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST_R = crate::FieldReader;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST` writer - BackUp access sdio_host permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_CAN` reader - BackUp access can permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_CAN_R = crate::FieldReader;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_CAN` writer - BackUp access can permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_CAN_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_PWM1` reader - BackUp access pwm1 permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_PWM1_R = crate::FieldReader;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_PWM1` writer - BackUp access pwm1 permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_PWM1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_I2S1` reader - BackUp access i2s1 permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_I2S1_R = crate::FieldReader;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_I2S1` writer - BackUp access i2s1 permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_I2S1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_UART2` reader - BackUp access uart2 permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_UART2_R = crate::FieldReader;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_UART2` writer - BackUp access uart2 permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_UART2_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_RWBT` reader - BackUp access rwbt permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_RWBT_R = crate::FieldReader;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_RWBT` writer - BackUp access rwbt permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_RWBT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC` reader - BackUp access wifimac permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_R = crate::FieldReader;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC` writer - BackUp access wifimac permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_PWR` reader - BackUp access pwr permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_PWR_R = crate::FieldReader;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_PWR` writer - BackUp access pwr permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_PWR_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:1 - BackUp access spi_2 permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_spi_2(&self) -> BACKUP_BUS_PMS_CONSTRAIN_SPI_2_R {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_SPI_2_R::new((self.bits & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 2:3 - BackUp access spi_3 permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_spi_3(&self) -> BACKUP_BUS_PMS_CONSTRAIN_SPI_3_R {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_SPI_3_R::new(((self.bits >> 2) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 4:5 - BackUp access apb_ctrl permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_apb_ctrl(&self) -> BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_R {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_R::new(((self.bits >> 4) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 6:7 - BackUp access i2c_ext1 permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_i2c_ext1(&self) -> BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1_R {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1_R::new(((self.bits >> 6) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 8:9 - BackUp access sdio_host permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_sdio_host(&self) -> BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST_R {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST_R::new(((self.bits >> 8) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 10:11 - BackUp access can permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_can(&self) -> BACKUP_BUS_PMS_CONSTRAIN_CAN_R {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_CAN_R::new(((self.bits >> 10) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 12:13 - BackUp access pwm1 permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_pwm1(&self) -> BACKUP_BUS_PMS_CONSTRAIN_PWM1_R {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_PWM1_R::new(((self.bits >> 12) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 14:15 - BackUp access i2s1 permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_i2s1(&self) -> BACKUP_BUS_PMS_CONSTRAIN_I2S1_R {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_I2S1_R::new(((self.bits >> 14) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 16:17 - BackUp access uart2 permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_uart2(&self) -> BACKUP_BUS_PMS_CONSTRAIN_UART2_R {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_UART2_R::new(((self.bits >> 16) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 22:23 - BackUp access rwbt permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_rwbt(&self) -> BACKUP_BUS_PMS_CONSTRAIN_RWBT_R {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_RWBT_R::new(((self.bits >> 22) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 26:27 - BackUp access wifimac permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_wifimac(&self) -> BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_R {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_R::new(((self.bits >> 26) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 28:29 - BackUp access pwr permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_pwr(&self) -> BACKUP_BUS_PMS_CONSTRAIN_PWR_R {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_PWR_R::new(((self.bits >> 28) & 3) as u8)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("BACKUP_BUS_PMS_CONSTRAIN_3")
|
||||
.field(
|
||||
"backup_bus_pms_constrain_spi_2",
|
||||
&self.backup_bus_pms_constrain_spi_2(),
|
||||
)
|
||||
.field(
|
||||
"backup_bus_pms_constrain_spi_3",
|
||||
&self.backup_bus_pms_constrain_spi_3(),
|
||||
)
|
||||
.field(
|
||||
"backup_bus_pms_constrain_apb_ctrl",
|
||||
&self.backup_bus_pms_constrain_apb_ctrl(),
|
||||
)
|
||||
.field(
|
||||
"backup_bus_pms_constrain_i2c_ext1",
|
||||
&self.backup_bus_pms_constrain_i2c_ext1(),
|
||||
)
|
||||
.field(
|
||||
"backup_bus_pms_constrain_sdio_host",
|
||||
&self.backup_bus_pms_constrain_sdio_host(),
|
||||
)
|
||||
.field(
|
||||
"backup_bus_pms_constrain_can",
|
||||
&self.backup_bus_pms_constrain_can(),
|
||||
)
|
||||
.field(
|
||||
"backup_bus_pms_constrain_pwm1",
|
||||
&self.backup_bus_pms_constrain_pwm1(),
|
||||
)
|
||||
.field(
|
||||
"backup_bus_pms_constrain_i2s1",
|
||||
&self.backup_bus_pms_constrain_i2s1(),
|
||||
)
|
||||
.field(
|
||||
"backup_bus_pms_constrain_uart2",
|
||||
&self.backup_bus_pms_constrain_uart2(),
|
||||
)
|
||||
.field(
|
||||
"backup_bus_pms_constrain_rwbt",
|
||||
&self.backup_bus_pms_constrain_rwbt(),
|
||||
)
|
||||
.field(
|
||||
"backup_bus_pms_constrain_wifimac",
|
||||
&self.backup_bus_pms_constrain_wifimac(),
|
||||
)
|
||||
.field(
|
||||
"backup_bus_pms_constrain_pwr",
|
||||
&self.backup_bus_pms_constrain_pwr(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:1 - BackUp access spi_2 permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_spi_2(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_SPI_2_W<BACKUP_BUS_PMS_CONSTRAIN_3_SPEC> {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_SPI_2_W::new(self, 0)
|
||||
}
|
||||
#[doc = "Bits 2:3 - BackUp access spi_3 permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_spi_3(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_SPI_3_W<BACKUP_BUS_PMS_CONSTRAIN_3_SPEC> {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_SPI_3_W::new(self, 2)
|
||||
}
|
||||
#[doc = "Bits 4:5 - BackUp access apb_ctrl permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_apb_ctrl(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_W<BACKUP_BUS_PMS_CONSTRAIN_3_SPEC> {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_W::new(self, 4)
|
||||
}
|
||||
#[doc = "Bits 6:7 - BackUp access i2c_ext1 permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_i2c_ext1(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1_W<BACKUP_BUS_PMS_CONSTRAIN_3_SPEC> {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1_W::new(self, 6)
|
||||
}
|
||||
#[doc = "Bits 8:9 - BackUp access sdio_host permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_sdio_host(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST_W<BACKUP_BUS_PMS_CONSTRAIN_3_SPEC> {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST_W::new(self, 8)
|
||||
}
|
||||
#[doc = "Bits 10:11 - BackUp access can permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_can(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_CAN_W<BACKUP_BUS_PMS_CONSTRAIN_3_SPEC> {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_CAN_W::new(self, 10)
|
||||
}
|
||||
#[doc = "Bits 12:13 - BackUp access pwm1 permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_pwm1(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_PWM1_W<BACKUP_BUS_PMS_CONSTRAIN_3_SPEC> {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_PWM1_W::new(self, 12)
|
||||
}
|
||||
#[doc = "Bits 14:15 - BackUp access i2s1 permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_i2s1(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_I2S1_W<BACKUP_BUS_PMS_CONSTRAIN_3_SPEC> {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_I2S1_W::new(self, 14)
|
||||
}
|
||||
#[doc = "Bits 16:17 - BackUp access uart2 permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_uart2(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_UART2_W<BACKUP_BUS_PMS_CONSTRAIN_3_SPEC> {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_UART2_W::new(self, 16)
|
||||
}
|
||||
#[doc = "Bits 22:23 - BackUp access rwbt permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_rwbt(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_RWBT_W<BACKUP_BUS_PMS_CONSTRAIN_3_SPEC> {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_RWBT_W::new(self, 22)
|
||||
}
|
||||
#[doc = "Bits 26:27 - BackUp access wifimac permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_wifimac(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_W<BACKUP_BUS_PMS_CONSTRAIN_3_SPEC> {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_W::new(self, 26)
|
||||
}
|
||||
#[doc = "Bits 28:29 - BackUp access pwr permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_pwr(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_PWR_W<BACKUP_BUS_PMS_CONSTRAIN_3_SPEC> {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_PWR_W::new(self, 28)
|
||||
}
|
||||
}
|
||||
#[doc = "BackUp access peripherals permission configuration register 3.\n\nYou can [`read`](crate::Reg::read) this register and get [`backup_bus_pms_constrain_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`backup_bus_pms_constrain_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct BACKUP_BUS_PMS_CONSTRAIN_3_SPEC;
|
||||
impl crate::RegisterSpec for BACKUP_BUS_PMS_CONSTRAIN_3_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`backup_bus_pms_constrain_3::R`](R) reader structure"]
|
||||
impl crate::Readable for BACKUP_BUS_PMS_CONSTRAIN_3_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`backup_bus_pms_constrain_3::W`](W) writer structure"]
|
||||
impl crate::Writable for BACKUP_BUS_PMS_CONSTRAIN_3_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets BACKUP_BUS_PMS_CONSTRAIN_3 to value 0x3cc3_ffff"]
|
||||
impl crate::Resettable for BACKUP_BUS_PMS_CONSTRAIN_3_SPEC {
|
||||
const RESET_VALUE: u32 = 0x3cc3_ffff;
|
||||
}
|
||||
@@ -0,0 +1,354 @@
|
||||
#[doc = "Register `BACKUP_BUS_PMS_CONSTRAIN_4` reader"]
|
||||
pub type R = crate::R<BACKUP_BUS_PMS_CONSTRAIN_4_SPEC>;
|
||||
#[doc = "Register `BACKUP_BUS_PMS_CONSTRAIN_4` writer"]
|
||||
pub type W = crate::W<BACKUP_BUS_PMS_CONSTRAIN_4_SPEC>;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE` reader - BackUp access usb_device permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_R = crate::FieldReader;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE` writer - BackUp access usb_device permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP` reader - BackUp access usb_wrap permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_R = crate::FieldReader;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP` writer - BackUp access usb_wrap permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI` reader - BackUp access crypto_peri permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_R = crate::FieldReader;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI` writer - BackUp access crypto_peri permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA` reader - BackUp access crypto_dma permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_R = crate::FieldReader;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA` writer - BackUp access crypto_dma permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_APB_ADC` reader - BackUp access apb_adc permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_R = crate::FieldReader;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_APB_ADC` writer - BackUp access apb_adc permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM` reader - BackUp access lcd_cam permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM_R = crate::FieldReader;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM` writer - BackUp access lcd_cam permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_BT_PWR` reader - BackUp access bt_pwr permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_R = crate::FieldReader;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_BT_PWR` writer - BackUp access bt_pwr permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_USB` reader - BackUp access usb permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_USB_R = crate::FieldReader;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_USB` writer - BackUp access usb permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_USB_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_SYSTEM` reader - BackUp access system permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_SYSTEM_R = crate::FieldReader;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_SYSTEM` writer - BackUp access system permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_SYSTEM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE` reader - BackUp access sensitive permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE_R = crate::FieldReader;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE` writer - BackUp access sensitive permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT` reader - BackUp access interrupt permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT_R = crate::FieldReader;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT` writer - BackUp access interrupt permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY` reader - BackUp access dma_copy permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY_R = crate::FieldReader;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY` writer - BackUp access dma_copy permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG` reader - BackUp access cache_config permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG_R = crate::FieldReader;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG` writer - BackUp access cache_config permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_AD` reader - BackUp access ad permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_AD_R = crate::FieldReader;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_AD` writer - BackUp access ad permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_AD_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_DIO` reader - BackUp access dio permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_DIO_R = crate::FieldReader;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_DIO` writer - BackUp access dio permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_DIO_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER` reader - BackUp access world_controller permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER_R = crate::FieldReader;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER` writer - BackUp access world_controller permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:1 - BackUp access usb_device permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_usb_device(&self) -> BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_R {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_R::new((self.bits & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 2:3 - BackUp access usb_wrap permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_usb_wrap(&self) -> BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_R {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_R::new(((self.bits >> 2) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 4:5 - BackUp access crypto_peri permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_crypto_peri(&self) -> BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_R {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_R::new(((self.bits >> 4) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 6:7 - BackUp access crypto_dma permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_crypto_dma(&self) -> BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_R {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_R::new(((self.bits >> 6) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 8:9 - BackUp access apb_adc permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_apb_adc(&self) -> BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_R {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_R::new(((self.bits >> 8) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 10:11 - BackUp access lcd_cam permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_lcd_cam(&self) -> BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM_R {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM_R::new(((self.bits >> 10) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 12:13 - BackUp access bt_pwr permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_bt_pwr(&self) -> BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_R {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_R::new(((self.bits >> 12) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 14:15 - BackUp access usb permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_usb(&self) -> BACKUP_BUS_PMS_CONSTRAIN_USB_R {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_USB_R::new(((self.bits >> 14) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 16:17 - BackUp access system permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_system(&self) -> BACKUP_BUS_PMS_CONSTRAIN_SYSTEM_R {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_SYSTEM_R::new(((self.bits >> 16) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 18:19 - BackUp access sensitive permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_sensitive(&self) -> BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE_R {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE_R::new(((self.bits >> 18) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 20:21 - BackUp access interrupt permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_interrupt(&self) -> BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT_R {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT_R::new(((self.bits >> 20) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 22:23 - BackUp access dma_copy permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_dma_copy(&self) -> BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY_R {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY_R::new(((self.bits >> 22) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 24:25 - BackUp access cache_config permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_cache_config(&self) -> BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG_R {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG_R::new(((self.bits >> 24) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 26:27 - BackUp access ad permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_ad(&self) -> BACKUP_BUS_PMS_CONSTRAIN_AD_R {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_AD_R::new(((self.bits >> 26) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 28:29 - BackUp access dio permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_dio(&self) -> BACKUP_BUS_PMS_CONSTRAIN_DIO_R {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_DIO_R::new(((self.bits >> 28) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 30:31 - BackUp access world_controller permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_world_controller(
|
||||
&self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER_R {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER_R::new(((self.bits >> 30) & 3) as u8)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("BACKUP_BUS_PMS_CONSTRAIN_4")
|
||||
.field(
|
||||
"backup_bus_pms_constrain_usb_device",
|
||||
&self.backup_bus_pms_constrain_usb_device(),
|
||||
)
|
||||
.field(
|
||||
"backup_bus_pms_constrain_usb_wrap",
|
||||
&self.backup_bus_pms_constrain_usb_wrap(),
|
||||
)
|
||||
.field(
|
||||
"backup_bus_pms_constrain_crypto_peri",
|
||||
&self.backup_bus_pms_constrain_crypto_peri(),
|
||||
)
|
||||
.field(
|
||||
"backup_bus_pms_constrain_crypto_dma",
|
||||
&self.backup_bus_pms_constrain_crypto_dma(),
|
||||
)
|
||||
.field(
|
||||
"backup_bus_pms_constrain_apb_adc",
|
||||
&self.backup_bus_pms_constrain_apb_adc(),
|
||||
)
|
||||
.field(
|
||||
"backup_bus_pms_constrain_lcd_cam",
|
||||
&self.backup_bus_pms_constrain_lcd_cam(),
|
||||
)
|
||||
.field(
|
||||
"backup_bus_pms_constrain_bt_pwr",
|
||||
&self.backup_bus_pms_constrain_bt_pwr(),
|
||||
)
|
||||
.field(
|
||||
"backup_bus_pms_constrain_usb",
|
||||
&self.backup_bus_pms_constrain_usb(),
|
||||
)
|
||||
.field(
|
||||
"backup_bus_pms_constrain_system",
|
||||
&self.backup_bus_pms_constrain_system(),
|
||||
)
|
||||
.field(
|
||||
"backup_bus_pms_constrain_sensitive",
|
||||
&self.backup_bus_pms_constrain_sensitive(),
|
||||
)
|
||||
.field(
|
||||
"backup_bus_pms_constrain_interrupt",
|
||||
&self.backup_bus_pms_constrain_interrupt(),
|
||||
)
|
||||
.field(
|
||||
"backup_bus_pms_constrain_dma_copy",
|
||||
&self.backup_bus_pms_constrain_dma_copy(),
|
||||
)
|
||||
.field(
|
||||
"backup_bus_pms_constrain_cache_config",
|
||||
&self.backup_bus_pms_constrain_cache_config(),
|
||||
)
|
||||
.field(
|
||||
"backup_bus_pms_constrain_ad",
|
||||
&self.backup_bus_pms_constrain_ad(),
|
||||
)
|
||||
.field(
|
||||
"backup_bus_pms_constrain_dio",
|
||||
&self.backup_bus_pms_constrain_dio(),
|
||||
)
|
||||
.field(
|
||||
"backup_bus_pms_constrain_world_controller",
|
||||
&self.backup_bus_pms_constrain_world_controller(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:1 - BackUp access usb_device permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_usb_device(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_W<BACKUP_BUS_PMS_CONSTRAIN_4_SPEC> {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_W::new(self, 0)
|
||||
}
|
||||
#[doc = "Bits 2:3 - BackUp access usb_wrap permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_usb_wrap(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_W<BACKUP_BUS_PMS_CONSTRAIN_4_SPEC> {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_W::new(self, 2)
|
||||
}
|
||||
#[doc = "Bits 4:5 - BackUp access crypto_peri permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_crypto_peri(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_W<BACKUP_BUS_PMS_CONSTRAIN_4_SPEC> {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_W::new(self, 4)
|
||||
}
|
||||
#[doc = "Bits 6:7 - BackUp access crypto_dma permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_crypto_dma(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_W<BACKUP_BUS_PMS_CONSTRAIN_4_SPEC> {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_W::new(self, 6)
|
||||
}
|
||||
#[doc = "Bits 8:9 - BackUp access apb_adc permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_apb_adc(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_W<BACKUP_BUS_PMS_CONSTRAIN_4_SPEC> {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_W::new(self, 8)
|
||||
}
|
||||
#[doc = "Bits 10:11 - BackUp access lcd_cam permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_lcd_cam(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM_W<BACKUP_BUS_PMS_CONSTRAIN_4_SPEC> {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM_W::new(self, 10)
|
||||
}
|
||||
#[doc = "Bits 12:13 - BackUp access bt_pwr permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_bt_pwr(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_W<BACKUP_BUS_PMS_CONSTRAIN_4_SPEC> {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_W::new(self, 12)
|
||||
}
|
||||
#[doc = "Bits 14:15 - BackUp access usb permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_usb(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_USB_W<BACKUP_BUS_PMS_CONSTRAIN_4_SPEC> {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_USB_W::new(self, 14)
|
||||
}
|
||||
#[doc = "Bits 16:17 - BackUp access system permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_system(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_SYSTEM_W<BACKUP_BUS_PMS_CONSTRAIN_4_SPEC> {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_SYSTEM_W::new(self, 16)
|
||||
}
|
||||
#[doc = "Bits 18:19 - BackUp access sensitive permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_sensitive(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE_W<BACKUP_BUS_PMS_CONSTRAIN_4_SPEC> {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE_W::new(self, 18)
|
||||
}
|
||||
#[doc = "Bits 20:21 - BackUp access interrupt permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_interrupt(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT_W<BACKUP_BUS_PMS_CONSTRAIN_4_SPEC> {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT_W::new(self, 20)
|
||||
}
|
||||
#[doc = "Bits 22:23 - BackUp access dma_copy permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_dma_copy(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY_W<BACKUP_BUS_PMS_CONSTRAIN_4_SPEC> {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY_W::new(self, 22)
|
||||
}
|
||||
#[doc = "Bits 24:25 - BackUp access cache_config permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_cache_config(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG_W<BACKUP_BUS_PMS_CONSTRAIN_4_SPEC> {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG_W::new(self, 24)
|
||||
}
|
||||
#[doc = "Bits 26:27 - BackUp access ad permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_ad(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_AD_W<BACKUP_BUS_PMS_CONSTRAIN_4_SPEC> {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_AD_W::new(self, 26)
|
||||
}
|
||||
#[doc = "Bits 28:29 - BackUp access dio permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_dio(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_DIO_W<BACKUP_BUS_PMS_CONSTRAIN_4_SPEC> {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_DIO_W::new(self, 28)
|
||||
}
|
||||
#[doc = "Bits 30:31 - BackUp access world_controller permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_world_controller(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER_W<BACKUP_BUS_PMS_CONSTRAIN_4_SPEC> {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER_W::new(self, 30)
|
||||
}
|
||||
}
|
||||
#[doc = "BackUp access peripherals permission configuration register 4.\n\nYou can [`read`](crate::Reg::read) this register and get [`backup_bus_pms_constrain_4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`backup_bus_pms_constrain_4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct BACKUP_BUS_PMS_CONSTRAIN_4_SPEC;
|
||||
impl crate::RegisterSpec for BACKUP_BUS_PMS_CONSTRAIN_4_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`backup_bus_pms_constrain_4::R`](R) reader structure"]
|
||||
impl crate::Readable for BACKUP_BUS_PMS_CONSTRAIN_4_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`backup_bus_pms_constrain_4::W`](W) writer structure"]
|
||||
impl crate::Writable for BACKUP_BUS_PMS_CONSTRAIN_4_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets BACKUP_BUS_PMS_CONSTRAIN_4 to value 0xffff_ffff"]
|
||||
impl crate::Resettable for BACKUP_BUS_PMS_CONSTRAIN_4_SPEC {
|
||||
const RESET_VALUE: u32 = 0xffff_ffff;
|
||||
}
|
||||
@@ -0,0 +1,55 @@
|
||||
#[doc = "Register `BACKUP_BUS_PMS_CONSTRAIN_5` reader"]
|
||||
pub type R = crate::R<BACKUP_BUS_PMS_CONSTRAIN_5_SPEC>;
|
||||
#[doc = "Register `BACKUP_BUS_PMS_CONSTRAIN_5` writer"]
|
||||
pub type W = crate::W<BACKUP_BUS_PMS_CONSTRAIN_5_SPEC>;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR` reader - BackUp access rtcfast_spltaddr permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR_R = crate::FieldReader<u16>;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR` writer - BackUp access rtcfast_spltaddr permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR_W<'a, REG> =
|
||||
crate::FieldWriter<'a, REG, 11, u16>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:10 - BackUp access rtcfast_spltaddr permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_rtcfast_spltaddr(
|
||||
&self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR_R {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR_R::new((self.bits & 0x07ff) as u16)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("BACKUP_BUS_PMS_CONSTRAIN_5")
|
||||
.field(
|
||||
"backup_bus_pms_constrain_rtcfast_spltaddr",
|
||||
&self.backup_bus_pms_constrain_rtcfast_spltaddr(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:10 - BackUp access rtcfast_spltaddr permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_rtcfast_spltaddr(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR_W<BACKUP_BUS_PMS_CONSTRAIN_5_SPEC> {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR_W::new(self, 0)
|
||||
}
|
||||
}
|
||||
#[doc = "BackUp access peripherals permission configuration register 5.\n\nYou can [`read`](crate::Reg::read) this register and get [`backup_bus_pms_constrain_5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`backup_bus_pms_constrain_5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct BACKUP_BUS_PMS_CONSTRAIN_5_SPEC;
|
||||
impl crate::RegisterSpec for BACKUP_BUS_PMS_CONSTRAIN_5_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`backup_bus_pms_constrain_5::R`](R) reader structure"]
|
||||
impl crate::Readable for BACKUP_BUS_PMS_CONSTRAIN_5_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`backup_bus_pms_constrain_5::W`](W) writer structure"]
|
||||
impl crate::Writable for BACKUP_BUS_PMS_CONSTRAIN_5_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets BACKUP_BUS_PMS_CONSTRAIN_5 to value 0x07ff"]
|
||||
impl crate::Resettable for BACKUP_BUS_PMS_CONSTRAIN_5_SPEC {
|
||||
const RESET_VALUE: u32 = 0x07ff;
|
||||
}
|
||||
@@ -0,0 +1,72 @@
|
||||
#[doc = "Register `BACKUP_BUS_PMS_CONSTRAIN_6` reader"]
|
||||
pub type R = crate::R<BACKUP_BUS_PMS_CONSTRAIN_6_SPEC>;
|
||||
#[doc = "Register `BACKUP_BUS_PMS_CONSTRAIN_6` writer"]
|
||||
pub type W = crate::W<BACKUP_BUS_PMS_CONSTRAIN_6_SPEC>;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L` reader - BackUp access rtcfast_l permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L_R = crate::FieldReader;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L` writer - BackUp access rtcfast_l permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H` reader - BackUp access rtcfast_h permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H_R = crate::FieldReader;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H` writer - BackUp access rtcfast_h permission."]
|
||||
pub type BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:2 - BackUp access rtcfast_l permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_rtcfast_l(&self) -> BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L_R {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L_R::new((self.bits & 7) as u8)
|
||||
}
|
||||
#[doc = "Bits 3:5 - BackUp access rtcfast_h permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_rtcfast_h(&self) -> BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H_R {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H_R::new(((self.bits >> 3) & 7) as u8)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("BACKUP_BUS_PMS_CONSTRAIN_6")
|
||||
.field(
|
||||
"backup_bus_pms_constrain_rtcfast_l",
|
||||
&self.backup_bus_pms_constrain_rtcfast_l(),
|
||||
)
|
||||
.field(
|
||||
"backup_bus_pms_constrain_rtcfast_h",
|
||||
&self.backup_bus_pms_constrain_rtcfast_h(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:2 - BackUp access rtcfast_l permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_rtcfast_l(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L_W<BACKUP_BUS_PMS_CONSTRAIN_6_SPEC> {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L_W::new(self, 0)
|
||||
}
|
||||
#[doc = "Bits 3:5 - BackUp access rtcfast_h permission."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_constrain_rtcfast_h(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H_W<BACKUP_BUS_PMS_CONSTRAIN_6_SPEC> {
|
||||
BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H_W::new(self, 3)
|
||||
}
|
||||
}
|
||||
#[doc = "BackUp access peripherals permission configuration register 6.\n\nYou can [`read`](crate::Reg::read) this register and get [`backup_bus_pms_constrain_6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`backup_bus_pms_constrain_6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct BACKUP_BUS_PMS_CONSTRAIN_6_SPEC;
|
||||
impl crate::RegisterSpec for BACKUP_BUS_PMS_CONSTRAIN_6_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`backup_bus_pms_constrain_6::R`](R) reader structure"]
|
||||
impl crate::Readable for BACKUP_BUS_PMS_CONSTRAIN_6_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`backup_bus_pms_constrain_6::W`](W) writer structure"]
|
||||
impl crate::Writable for BACKUP_BUS_PMS_CONSTRAIN_6_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets BACKUP_BUS_PMS_CONSTRAIN_6 to value 0x3f"]
|
||||
impl crate::Resettable for BACKUP_BUS_PMS_CONSTRAIN_6_SPEC {
|
||||
const RESET_VALUE: u32 = 0x3f;
|
||||
}
|
||||
@@ -0,0 +1,52 @@
|
||||
#[doc = "Register `BACKUP_BUS_PMS_MONITOR_0` reader"]
|
||||
pub type R = crate::R<BACKUP_BUS_PMS_MONITOR_0_SPEC>;
|
||||
#[doc = "Register `BACKUP_BUS_PMS_MONITOR_0` writer"]
|
||||
pub type W = crate::W<BACKUP_BUS_PMS_MONITOR_0_SPEC>;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_MONITOR_LOCK` reader - Set 1 to lock BackUp permission report registers."]
|
||||
pub type BACKUP_BUS_PMS_MONITOR_LOCK_R = crate::BitReader;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_MONITOR_LOCK` writer - Set 1 to lock BackUp permission report registers."]
|
||||
pub type BACKUP_BUS_PMS_MONITOR_LOCK_W<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
impl R {
|
||||
#[doc = "Bit 0 - Set 1 to lock BackUp permission report registers."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_monitor_lock(&self) -> BACKUP_BUS_PMS_MONITOR_LOCK_R {
|
||||
BACKUP_BUS_PMS_MONITOR_LOCK_R::new((self.bits & 1) != 0)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("BACKUP_BUS_PMS_MONITOR_0")
|
||||
.field(
|
||||
"backup_bus_pms_monitor_lock",
|
||||
&self.backup_bus_pms_monitor_lock(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bit 0 - Set 1 to lock BackUp permission report registers."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_monitor_lock(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_MONITOR_LOCK_W<BACKUP_BUS_PMS_MONITOR_0_SPEC> {
|
||||
BACKUP_BUS_PMS_MONITOR_LOCK_W::new(self, 0)
|
||||
}
|
||||
}
|
||||
#[doc = "BackUp permission report register 0.\n\nYou can [`read`](crate::Reg::read) this register and get [`backup_bus_pms_monitor_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`backup_bus_pms_monitor_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct BACKUP_BUS_PMS_MONITOR_0_SPEC;
|
||||
impl crate::RegisterSpec for BACKUP_BUS_PMS_MONITOR_0_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`backup_bus_pms_monitor_0::R`](R) reader structure"]
|
||||
impl crate::Readable for BACKUP_BUS_PMS_MONITOR_0_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`backup_bus_pms_monitor_0::W`](W) writer structure"]
|
||||
impl crate::Writable for BACKUP_BUS_PMS_MONITOR_0_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets BACKUP_BUS_PMS_MONITOR_0 to value 0"]
|
||||
impl crate::Resettable for BACKUP_BUS_PMS_MONITOR_0_SPEC {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
@@ -0,0 +1,72 @@
|
||||
#[doc = "Register `BACKUP_BUS_PMS_MONITOR_1` reader"]
|
||||
pub type R = crate::R<BACKUP_BUS_PMS_MONITOR_1_SPEC>;
|
||||
#[doc = "Register `BACKUP_BUS_PMS_MONITOR_1` writer"]
|
||||
pub type W = crate::W<BACKUP_BUS_PMS_MONITOR_1_SPEC>;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR` reader - Set 1 to clear interrupt that BackUp initiate illegal access."]
|
||||
pub type BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_R = crate::BitReader;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR` writer - Set 1 to clear interrupt that BackUp initiate illegal access."]
|
||||
pub type BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_MONITOR_VIOLATE_EN` reader - Set 1 to enable interrupt that BackUp initiate illegal access."]
|
||||
pub type BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_R = crate::BitReader;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_MONITOR_VIOLATE_EN` writer - Set 1 to enable interrupt that BackUp initiate illegal access."]
|
||||
pub type BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
impl R {
|
||||
#[doc = "Bit 0 - Set 1 to clear interrupt that BackUp initiate illegal access."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_monitor_violate_clr(&self) -> BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_R {
|
||||
BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_R::new((self.bits & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 1 - Set 1 to enable interrupt that BackUp initiate illegal access."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_monitor_violate_en(&self) -> BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_R {
|
||||
BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_R::new(((self.bits >> 1) & 1) != 0)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("BACKUP_BUS_PMS_MONITOR_1")
|
||||
.field(
|
||||
"backup_bus_pms_monitor_violate_clr",
|
||||
&self.backup_bus_pms_monitor_violate_clr(),
|
||||
)
|
||||
.field(
|
||||
"backup_bus_pms_monitor_violate_en",
|
||||
&self.backup_bus_pms_monitor_violate_en(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bit 0 - Set 1 to clear interrupt that BackUp initiate illegal access."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_monitor_violate_clr(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_W<BACKUP_BUS_PMS_MONITOR_1_SPEC> {
|
||||
BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_W::new(self, 0)
|
||||
}
|
||||
#[doc = "Bit 1 - Set 1 to enable interrupt that BackUp initiate illegal access."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_monitor_violate_en(
|
||||
&mut self,
|
||||
) -> BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_W<BACKUP_BUS_PMS_MONITOR_1_SPEC> {
|
||||
BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_W::new(self, 1)
|
||||
}
|
||||
}
|
||||
#[doc = "BackUp permission report register 1.\n\nYou can [`read`](crate::Reg::read) this register and get [`backup_bus_pms_monitor_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`backup_bus_pms_monitor_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct BACKUP_BUS_PMS_MONITOR_1_SPEC;
|
||||
impl crate::RegisterSpec for BACKUP_BUS_PMS_MONITOR_1_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`backup_bus_pms_monitor_1::R`](R) reader structure"]
|
||||
impl crate::Readable for BACKUP_BUS_PMS_MONITOR_1_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`backup_bus_pms_monitor_1::W`](W) writer structure"]
|
||||
impl crate::Writable for BACKUP_BUS_PMS_MONITOR_1_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets BACKUP_BUS_PMS_MONITOR_1 to value 0x03"]
|
||||
impl crate::Resettable for BACKUP_BUS_PMS_MONITOR_1_SPEC {
|
||||
const RESET_VALUE: u32 = 0x03;
|
||||
}
|
||||
@@ -0,0 +1,72 @@
|
||||
#[doc = "Register `BACKUP_BUS_PMS_MONITOR_2` reader"]
|
||||
pub type R = crate::R<BACKUP_BUS_PMS_MONITOR_2_SPEC>;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR` reader - Record BackUp illegal access interrupt state."]
|
||||
pub type BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR_R = crate::BitReader;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS` reader - Record htrans when BackUp initate illegal access."]
|
||||
pub type BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_R = crate::FieldReader;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE` reader - Record access type when BackUp initate illegal access."]
|
||||
pub type BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_R = crate::FieldReader;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE` reader - Record access direction when BackUp initiate illegal access."]
|
||||
pub type BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE_R = crate::BitReader;
|
||||
impl R {
|
||||
#[doc = "Bit 0 - Record BackUp illegal access interrupt state."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_monitor_violate_intr(&self) -> BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR_R {
|
||||
BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR_R::new((self.bits & 1) != 0)
|
||||
}
|
||||
#[doc = "Bits 1:2 - Record htrans when BackUp initate illegal access."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_monitor_violate_status_htrans(
|
||||
&self,
|
||||
) -> BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_R {
|
||||
BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_R::new(((self.bits >> 1) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 3:5 - Record access type when BackUp initate illegal access."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_monitor_violate_status_hsize(
|
||||
&self,
|
||||
) -> BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_R {
|
||||
BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_R::new(((self.bits >> 3) & 7) as u8)
|
||||
}
|
||||
#[doc = "Bit 6 - Record access direction when BackUp initiate illegal access."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_monitor_violate_status_hwrite(
|
||||
&self,
|
||||
) -> BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE_R {
|
||||
BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE_R::new(((self.bits >> 6) & 1) != 0)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("BACKUP_BUS_PMS_MONITOR_2")
|
||||
.field(
|
||||
"backup_bus_pms_monitor_violate_intr",
|
||||
&self.backup_bus_pms_monitor_violate_intr(),
|
||||
)
|
||||
.field(
|
||||
"backup_bus_pms_monitor_violate_status_htrans",
|
||||
&self.backup_bus_pms_monitor_violate_status_htrans(),
|
||||
)
|
||||
.field(
|
||||
"backup_bus_pms_monitor_violate_status_hsize",
|
||||
&self.backup_bus_pms_monitor_violate_status_hsize(),
|
||||
)
|
||||
.field(
|
||||
"backup_bus_pms_monitor_violate_status_hwrite",
|
||||
&self.backup_bus_pms_monitor_violate_status_hwrite(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
#[doc = "BackUp permission report register 2.\n\nYou can [`read`](crate::Reg::read) this register and get [`backup_bus_pms_monitor_2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct BACKUP_BUS_PMS_MONITOR_2_SPEC;
|
||||
impl crate::RegisterSpec for BACKUP_BUS_PMS_MONITOR_2_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`backup_bus_pms_monitor_2::R`](R) reader structure"]
|
||||
impl crate::Readable for BACKUP_BUS_PMS_MONITOR_2_SPEC {}
|
||||
#[doc = "`reset()` method sets BACKUP_BUS_PMS_MONITOR_2 to value 0"]
|
||||
impl crate::Resettable for BACKUP_BUS_PMS_MONITOR_2_SPEC {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
@@ -0,0 +1,33 @@
|
||||
#[doc = "Register `BACKUP_BUS_PMS_MONITOR_3` reader"]
|
||||
pub type R = crate::R<BACKUP_BUS_PMS_MONITOR_3_SPEC>;
|
||||
#[doc = "Field `BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR` reader - Record address information when BackUp initiate illegal access."]
|
||||
pub type BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_R = crate::FieldReader<u32>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:31 - Record address information when BackUp initiate illegal access."]
|
||||
#[inline(always)]
|
||||
pub fn backup_bus_pms_monitor_violate_haddr(&self) -> BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_R {
|
||||
BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_R::new(self.bits)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("BACKUP_BUS_PMS_MONITOR_3")
|
||||
.field(
|
||||
"backup_bus_pms_monitor_violate_haddr",
|
||||
&self.backup_bus_pms_monitor_violate_haddr(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
#[doc = "BackUp permission report register 3.\n\nYou can [`read`](crate::Reg::read) this register and get [`backup_bus_pms_monitor_3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct BACKUP_BUS_PMS_MONITOR_3_SPEC;
|
||||
impl crate::RegisterSpec for BACKUP_BUS_PMS_MONITOR_3_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`backup_bus_pms_monitor_3::R`](R) reader structure"]
|
||||
impl crate::Readable for BACKUP_BUS_PMS_MONITOR_3_SPEC {}
|
||||
#[doc = "`reset()` method sets BACKUP_BUS_PMS_MONITOR_3 to value 0"]
|
||||
impl crate::Resettable for BACKUP_BUS_PMS_MONITOR_3_SPEC {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
@@ -0,0 +1,52 @@
|
||||
#[doc = "Register `CACHE_DATAARRAY_CONNECT_0` reader"]
|
||||
pub type R = crate::R<CACHE_DATAARRAY_CONNECT_0_SPEC>;
|
||||
#[doc = "Register `CACHE_DATAARRAY_CONNECT_0` writer"]
|
||||
pub type W = crate::W<CACHE_DATAARRAY_CONNECT_0_SPEC>;
|
||||
#[doc = "Field `CACHE_DATAARRAY_CONNECT_LOCK` reader - Set 1 to lock cache data array registers."]
|
||||
pub type CACHE_DATAARRAY_CONNECT_LOCK_R = crate::BitReader;
|
||||
#[doc = "Field `CACHE_DATAARRAY_CONNECT_LOCK` writer - Set 1 to lock cache data array registers."]
|
||||
pub type CACHE_DATAARRAY_CONNECT_LOCK_W<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
impl R {
|
||||
#[doc = "Bit 0 - Set 1 to lock cache data array registers."]
|
||||
#[inline(always)]
|
||||
pub fn cache_dataarray_connect_lock(&self) -> CACHE_DATAARRAY_CONNECT_LOCK_R {
|
||||
CACHE_DATAARRAY_CONNECT_LOCK_R::new((self.bits & 1) != 0)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CACHE_DATAARRAY_CONNECT_0")
|
||||
.field(
|
||||
"cache_dataarray_connect_lock",
|
||||
&self.cache_dataarray_connect_lock(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bit 0 - Set 1 to lock cache data array registers."]
|
||||
#[inline(always)]
|
||||
pub fn cache_dataarray_connect_lock(
|
||||
&mut self,
|
||||
) -> CACHE_DATAARRAY_CONNECT_LOCK_W<CACHE_DATAARRAY_CONNECT_0_SPEC> {
|
||||
CACHE_DATAARRAY_CONNECT_LOCK_W::new(self, 0)
|
||||
}
|
||||
}
|
||||
#[doc = "Cache data array configuration register 0.\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_dataarray_connect_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_dataarray_connect_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CACHE_DATAARRAY_CONNECT_0_SPEC;
|
||||
impl crate::RegisterSpec for CACHE_DATAARRAY_CONNECT_0_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`cache_dataarray_connect_0::R`](R) reader structure"]
|
||||
impl crate::Readable for CACHE_DATAARRAY_CONNECT_0_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`cache_dataarray_connect_0::W`](W) writer structure"]
|
||||
impl crate::Writable for CACHE_DATAARRAY_CONNECT_0_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CACHE_DATAARRAY_CONNECT_0 to value 0"]
|
||||
impl crate::Resettable for CACHE_DATAARRAY_CONNECT_0_SPEC {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
@@ -0,0 +1,52 @@
|
||||
#[doc = "Register `CACHE_DATAARRAY_CONNECT_1` reader"]
|
||||
pub type R = crate::R<CACHE_DATAARRAY_CONNECT_1_SPEC>;
|
||||
#[doc = "Register `CACHE_DATAARRAY_CONNECT_1` writer"]
|
||||
pub type W = crate::W<CACHE_DATAARRAY_CONNECT_1_SPEC>;
|
||||
#[doc = "Field `CACHE_DATAARRAY_CONNECT_FLATTEN` reader - Cache data array connection configuration."]
|
||||
pub type CACHE_DATAARRAY_CONNECT_FLATTEN_R = crate::FieldReader;
|
||||
#[doc = "Field `CACHE_DATAARRAY_CONNECT_FLATTEN` writer - Cache data array connection configuration."]
|
||||
pub type CACHE_DATAARRAY_CONNECT_FLATTEN_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:7 - Cache data array connection configuration."]
|
||||
#[inline(always)]
|
||||
pub fn cache_dataarray_connect_flatten(&self) -> CACHE_DATAARRAY_CONNECT_FLATTEN_R {
|
||||
CACHE_DATAARRAY_CONNECT_FLATTEN_R::new((self.bits & 0xff) as u8)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CACHE_DATAARRAY_CONNECT_1")
|
||||
.field(
|
||||
"cache_dataarray_connect_flatten",
|
||||
&self.cache_dataarray_connect_flatten(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:7 - Cache data array connection configuration."]
|
||||
#[inline(always)]
|
||||
pub fn cache_dataarray_connect_flatten(
|
||||
&mut self,
|
||||
) -> CACHE_DATAARRAY_CONNECT_FLATTEN_W<CACHE_DATAARRAY_CONNECT_1_SPEC> {
|
||||
CACHE_DATAARRAY_CONNECT_FLATTEN_W::new(self, 0)
|
||||
}
|
||||
}
|
||||
#[doc = "Cache data array configuration register 1.\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_dataarray_connect_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_dataarray_connect_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CACHE_DATAARRAY_CONNECT_1_SPEC;
|
||||
impl crate::RegisterSpec for CACHE_DATAARRAY_CONNECT_1_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`cache_dataarray_connect_1::R`](R) reader structure"]
|
||||
impl crate::Readable for CACHE_DATAARRAY_CONNECT_1_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`cache_dataarray_connect_1::W`](W) writer structure"]
|
||||
impl crate::Writable for CACHE_DATAARRAY_CONNECT_1_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CACHE_DATAARRAY_CONNECT_1 to value 0xff"]
|
||||
impl crate::Resettable for CACHE_DATAARRAY_CONNECT_1_SPEC {
|
||||
const RESET_VALUE: u32 = 0xff;
|
||||
}
|
||||
@@ -0,0 +1,47 @@
|
||||
#[doc = "Register `CACHE_MMU_ACCESS_0` reader"]
|
||||
pub type R = crate::R<CACHE_MMU_ACCESS_0_SPEC>;
|
||||
#[doc = "Register `CACHE_MMU_ACCESS_0` writer"]
|
||||
pub type W = crate::W<CACHE_MMU_ACCESS_0_SPEC>;
|
||||
#[doc = "Field `CACHE_MMU_ACCESS_LOCK` reader - Set 1 to lock cache MMU registers."]
|
||||
pub type CACHE_MMU_ACCESS_LOCK_R = crate::BitReader;
|
||||
#[doc = "Field `CACHE_MMU_ACCESS_LOCK` writer - Set 1 to lock cache MMU registers."]
|
||||
pub type CACHE_MMU_ACCESS_LOCK_W<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
impl R {
|
||||
#[doc = "Bit 0 - Set 1 to lock cache MMU registers."]
|
||||
#[inline(always)]
|
||||
pub fn cache_mmu_access_lock(&self) -> CACHE_MMU_ACCESS_LOCK_R {
|
||||
CACHE_MMU_ACCESS_LOCK_R::new((self.bits & 1) != 0)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CACHE_MMU_ACCESS_0")
|
||||
.field("cache_mmu_access_lock", &self.cache_mmu_access_lock())
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bit 0 - Set 1 to lock cache MMU registers."]
|
||||
#[inline(always)]
|
||||
pub fn cache_mmu_access_lock(&mut self) -> CACHE_MMU_ACCESS_LOCK_W<CACHE_MMU_ACCESS_0_SPEC> {
|
||||
CACHE_MMU_ACCESS_LOCK_W::new(self, 0)
|
||||
}
|
||||
}
|
||||
#[doc = "Cache MMU configuration register 0.\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_mmu_access_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_mmu_access_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CACHE_MMU_ACCESS_0_SPEC;
|
||||
impl crate::RegisterSpec for CACHE_MMU_ACCESS_0_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`cache_mmu_access_0::R`](R) reader structure"]
|
||||
impl crate::Readable for CACHE_MMU_ACCESS_0_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`cache_mmu_access_0::W`](W) writer structure"]
|
||||
impl crate::Writable for CACHE_MMU_ACCESS_0_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CACHE_MMU_ACCESS_0 to value 0"]
|
||||
impl crate::Resettable for CACHE_MMU_ACCESS_0_SPEC {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
@@ -0,0 +1,62 @@
|
||||
#[doc = "Register `CACHE_MMU_ACCESS_1` reader"]
|
||||
pub type R = crate::R<CACHE_MMU_ACCESS_1_SPEC>;
|
||||
#[doc = "Register `CACHE_MMU_ACCESS_1` writer"]
|
||||
pub type W = crate::W<CACHE_MMU_ACCESS_1_SPEC>;
|
||||
#[doc = "Field `PRO_MMU_RD_ACS` reader - Set 1 to enable read access MMU memory."]
|
||||
pub type PRO_MMU_RD_ACS_R = crate::BitReader;
|
||||
#[doc = "Field `PRO_MMU_RD_ACS` writer - Set 1 to enable read access MMU memory."]
|
||||
pub type PRO_MMU_RD_ACS_W<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `PRO_MMU_WR_ACS` reader - Set 1 to enable write access MMU memory."]
|
||||
pub type PRO_MMU_WR_ACS_R = crate::BitReader;
|
||||
#[doc = "Field `PRO_MMU_WR_ACS` writer - Set 1 to enable write access MMU memory."]
|
||||
pub type PRO_MMU_WR_ACS_W<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
impl R {
|
||||
#[doc = "Bit 0 - Set 1 to enable read access MMU memory."]
|
||||
#[inline(always)]
|
||||
pub fn pro_mmu_rd_acs(&self) -> PRO_MMU_RD_ACS_R {
|
||||
PRO_MMU_RD_ACS_R::new((self.bits & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 1 - Set 1 to enable write access MMU memory."]
|
||||
#[inline(always)]
|
||||
pub fn pro_mmu_wr_acs(&self) -> PRO_MMU_WR_ACS_R {
|
||||
PRO_MMU_WR_ACS_R::new(((self.bits >> 1) & 1) != 0)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CACHE_MMU_ACCESS_1")
|
||||
.field("pro_mmu_rd_acs", &self.pro_mmu_rd_acs())
|
||||
.field("pro_mmu_wr_acs", &self.pro_mmu_wr_acs())
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bit 0 - Set 1 to enable read access MMU memory."]
|
||||
#[inline(always)]
|
||||
pub fn pro_mmu_rd_acs(&mut self) -> PRO_MMU_RD_ACS_W<CACHE_MMU_ACCESS_1_SPEC> {
|
||||
PRO_MMU_RD_ACS_W::new(self, 0)
|
||||
}
|
||||
#[doc = "Bit 1 - Set 1 to enable write access MMU memory."]
|
||||
#[inline(always)]
|
||||
pub fn pro_mmu_wr_acs(&mut self) -> PRO_MMU_WR_ACS_W<CACHE_MMU_ACCESS_1_SPEC> {
|
||||
PRO_MMU_WR_ACS_W::new(self, 1)
|
||||
}
|
||||
}
|
||||
#[doc = "Cache MMU configuration register 1.\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_mmu_access_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_mmu_access_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CACHE_MMU_ACCESS_1_SPEC;
|
||||
impl crate::RegisterSpec for CACHE_MMU_ACCESS_1_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`cache_mmu_access_1::R`](R) reader structure"]
|
||||
impl crate::Readable for CACHE_MMU_ACCESS_1_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`cache_mmu_access_1::W`](W) writer structure"]
|
||||
impl crate::Writable for CACHE_MMU_ACCESS_1_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CACHE_MMU_ACCESS_1 to value 0x03"]
|
||||
impl crate::Resettable for CACHE_MMU_ACCESS_1_SPEC {
|
||||
const RESET_VALUE: u32 = 0x03;
|
||||
}
|
||||
@@ -0,0 +1,47 @@
|
||||
#[doc = "Register `CACHE_TAG_ACCESS_0` reader"]
|
||||
pub type R = crate::R<CACHE_TAG_ACCESS_0_SPEC>;
|
||||
#[doc = "Register `CACHE_TAG_ACCESS_0` writer"]
|
||||
pub type W = crate::W<CACHE_TAG_ACCESS_0_SPEC>;
|
||||
#[doc = "Field `CACHE_TAG_ACCESS_LOCK` reader - Set 1 to lock cache tag Configuration Register."]
|
||||
pub type CACHE_TAG_ACCESS_LOCK_R = crate::BitReader;
|
||||
#[doc = "Field `CACHE_TAG_ACCESS_LOCK` writer - Set 1 to lock cache tag Configuration Register."]
|
||||
pub type CACHE_TAG_ACCESS_LOCK_W<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
impl R {
|
||||
#[doc = "Bit 0 - Set 1 to lock cache tag Configuration Register."]
|
||||
#[inline(always)]
|
||||
pub fn cache_tag_access_lock(&self) -> CACHE_TAG_ACCESS_LOCK_R {
|
||||
CACHE_TAG_ACCESS_LOCK_R::new((self.bits & 1) != 0)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CACHE_TAG_ACCESS_0")
|
||||
.field("cache_tag_access_lock", &self.cache_tag_access_lock())
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bit 0 - Set 1 to lock cache tag Configuration Register."]
|
||||
#[inline(always)]
|
||||
pub fn cache_tag_access_lock(&mut self) -> CACHE_TAG_ACCESS_LOCK_W<CACHE_TAG_ACCESS_0_SPEC> {
|
||||
CACHE_TAG_ACCESS_LOCK_W::new(self, 0)
|
||||
}
|
||||
}
|
||||
#[doc = "Cache tag configuration register 0.\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_tag_access_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_tag_access_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CACHE_TAG_ACCESS_0_SPEC;
|
||||
impl crate::RegisterSpec for CACHE_TAG_ACCESS_0_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`cache_tag_access_0::R`](R) reader structure"]
|
||||
impl crate::Readable for CACHE_TAG_ACCESS_0_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`cache_tag_access_0::W`](W) writer structure"]
|
||||
impl crate::Writable for CACHE_TAG_ACCESS_0_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CACHE_TAG_ACCESS_0 to value 0"]
|
||||
impl crate::Resettable for CACHE_TAG_ACCESS_0_SPEC {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
@@ -0,0 +1,92 @@
|
||||
#[doc = "Register `CACHE_TAG_ACCESS_1` reader"]
|
||||
pub type R = crate::R<CACHE_TAG_ACCESS_1_SPEC>;
|
||||
#[doc = "Register `CACHE_TAG_ACCESS_1` writer"]
|
||||
pub type W = crate::W<CACHE_TAG_ACCESS_1_SPEC>;
|
||||
#[doc = "Field `PRO_I_TAG_RD_ACS` reader - Set 1 to enable Icache read access tag memory."]
|
||||
pub type PRO_I_TAG_RD_ACS_R = crate::BitReader;
|
||||
#[doc = "Field `PRO_I_TAG_RD_ACS` writer - Set 1 to enable Icache read access tag memory."]
|
||||
pub type PRO_I_TAG_RD_ACS_W<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `PRO_I_TAG_WR_ACS` reader - Set 1 to enable Icache wrtie access tag memory."]
|
||||
pub type PRO_I_TAG_WR_ACS_R = crate::BitReader;
|
||||
#[doc = "Field `PRO_I_TAG_WR_ACS` writer - Set 1 to enable Icache wrtie access tag memory."]
|
||||
pub type PRO_I_TAG_WR_ACS_W<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `PRO_D_TAG_RD_ACS` reader - Set 1 to enable Dcache read access tag memory."]
|
||||
pub type PRO_D_TAG_RD_ACS_R = crate::BitReader;
|
||||
#[doc = "Field `PRO_D_TAG_RD_ACS` writer - Set 1 to enable Dcache read access tag memory."]
|
||||
pub type PRO_D_TAG_RD_ACS_W<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `PRO_D_TAG_WR_ACS` reader - Set 1 to enable Dcache wrtie access tag memory."]
|
||||
pub type PRO_D_TAG_WR_ACS_R = crate::BitReader;
|
||||
#[doc = "Field `PRO_D_TAG_WR_ACS` writer - Set 1 to enable Dcache wrtie access tag memory."]
|
||||
pub type PRO_D_TAG_WR_ACS_W<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
impl R {
|
||||
#[doc = "Bit 0 - Set 1 to enable Icache read access tag memory."]
|
||||
#[inline(always)]
|
||||
pub fn pro_i_tag_rd_acs(&self) -> PRO_I_TAG_RD_ACS_R {
|
||||
PRO_I_TAG_RD_ACS_R::new((self.bits & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 1 - Set 1 to enable Icache wrtie access tag memory."]
|
||||
#[inline(always)]
|
||||
pub fn pro_i_tag_wr_acs(&self) -> PRO_I_TAG_WR_ACS_R {
|
||||
PRO_I_TAG_WR_ACS_R::new(((self.bits >> 1) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 2 - Set 1 to enable Dcache read access tag memory."]
|
||||
#[inline(always)]
|
||||
pub fn pro_d_tag_rd_acs(&self) -> PRO_D_TAG_RD_ACS_R {
|
||||
PRO_D_TAG_RD_ACS_R::new(((self.bits >> 2) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 3 - Set 1 to enable Dcache wrtie access tag memory."]
|
||||
#[inline(always)]
|
||||
pub fn pro_d_tag_wr_acs(&self) -> PRO_D_TAG_WR_ACS_R {
|
||||
PRO_D_TAG_WR_ACS_R::new(((self.bits >> 3) & 1) != 0)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CACHE_TAG_ACCESS_1")
|
||||
.field("pro_i_tag_rd_acs", &self.pro_i_tag_rd_acs())
|
||||
.field("pro_i_tag_wr_acs", &self.pro_i_tag_wr_acs())
|
||||
.field("pro_d_tag_rd_acs", &self.pro_d_tag_rd_acs())
|
||||
.field("pro_d_tag_wr_acs", &self.pro_d_tag_wr_acs())
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bit 0 - Set 1 to enable Icache read access tag memory."]
|
||||
#[inline(always)]
|
||||
pub fn pro_i_tag_rd_acs(&mut self) -> PRO_I_TAG_RD_ACS_W<CACHE_TAG_ACCESS_1_SPEC> {
|
||||
PRO_I_TAG_RD_ACS_W::new(self, 0)
|
||||
}
|
||||
#[doc = "Bit 1 - Set 1 to enable Icache wrtie access tag memory."]
|
||||
#[inline(always)]
|
||||
pub fn pro_i_tag_wr_acs(&mut self) -> PRO_I_TAG_WR_ACS_W<CACHE_TAG_ACCESS_1_SPEC> {
|
||||
PRO_I_TAG_WR_ACS_W::new(self, 1)
|
||||
}
|
||||
#[doc = "Bit 2 - Set 1 to enable Dcache read access tag memory."]
|
||||
#[inline(always)]
|
||||
pub fn pro_d_tag_rd_acs(&mut self) -> PRO_D_TAG_RD_ACS_W<CACHE_TAG_ACCESS_1_SPEC> {
|
||||
PRO_D_TAG_RD_ACS_W::new(self, 2)
|
||||
}
|
||||
#[doc = "Bit 3 - Set 1 to enable Dcache wrtie access tag memory."]
|
||||
#[inline(always)]
|
||||
pub fn pro_d_tag_wr_acs(&mut self) -> PRO_D_TAG_WR_ACS_W<CACHE_TAG_ACCESS_1_SPEC> {
|
||||
PRO_D_TAG_WR_ACS_W::new(self, 3)
|
||||
}
|
||||
}
|
||||
#[doc = "Cache tag configuration register 1.\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_tag_access_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_tag_access_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CACHE_TAG_ACCESS_1_SPEC;
|
||||
impl crate::RegisterSpec for CACHE_TAG_ACCESS_1_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`cache_tag_access_1::R`](R) reader structure"]
|
||||
impl crate::Readable for CACHE_TAG_ACCESS_1_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`cache_tag_access_1::W`](W) writer structure"]
|
||||
impl crate::Writable for CACHE_TAG_ACCESS_1_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CACHE_TAG_ACCESS_1 to value 0x0f"]
|
||||
impl crate::Resettable for CACHE_TAG_ACCESS_1_SPEC {
|
||||
const RESET_VALUE: u32 = 0x0f;
|
||||
}
|
||||
+47
@@ -0,0 +1,47 @@
|
||||
#[doc = "Register `CLOCK_GATE` reader"]
|
||||
pub type R = crate::R<CLOCK_GATE_SPEC>;
|
||||
#[doc = "Register `CLOCK_GATE` writer"]
|
||||
pub type W = crate::W<CLOCK_GATE_SPEC>;
|
||||
#[doc = "Field `REG_CLK_EN` reader - Set 1 to enable clock gate function."]
|
||||
pub type REG_CLK_EN_R = crate::BitReader;
|
||||
#[doc = "Field `REG_CLK_EN` writer - Set 1 to enable clock gate function."]
|
||||
pub type REG_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
impl R {
|
||||
#[doc = "Bit 0 - Set 1 to enable clock gate function."]
|
||||
#[inline(always)]
|
||||
pub fn reg_clk_en(&self) -> REG_CLK_EN_R {
|
||||
REG_CLK_EN_R::new((self.bits & 1) != 0)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CLOCK_GATE")
|
||||
.field("reg_clk_en", &self.reg_clk_en())
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bit 0 - Set 1 to enable clock gate function."]
|
||||
#[inline(always)]
|
||||
pub fn reg_clk_en(&mut self) -> REG_CLK_EN_W<CLOCK_GATE_SPEC> {
|
||||
REG_CLK_EN_W::new(self, 0)
|
||||
}
|
||||
}
|
||||
#[doc = "Sensitive module clock gate configuration register.\n\nYou can [`read`](crate::Reg::read) this register and get [`clock_gate::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clock_gate::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CLOCK_GATE_SPEC;
|
||||
impl crate::RegisterSpec for CLOCK_GATE_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`clock_gate::R`](R) reader structure"]
|
||||
impl crate::Readable for CLOCK_GATE_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`clock_gate::W`](W) writer structure"]
|
||||
impl crate::Writable for CLOCK_GATE_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CLOCK_GATE to value 0x01"]
|
||||
impl crate::Resettable for CLOCK_GATE_SPEC {
|
||||
const RESET_VALUE: u32 = 0x01;
|
||||
}
|
||||
@@ -0,0 +1,52 @@
|
||||
#[doc = "Register `CORE_0_DRAM0_PMS_MONITOR_0` reader"]
|
||||
pub type R = crate::R<CORE_0_DRAM0_PMS_MONITOR_0_SPEC>;
|
||||
#[doc = "Register `CORE_0_DRAM0_PMS_MONITOR_0` writer"]
|
||||
pub type W = crate::W<CORE_0_DRAM0_PMS_MONITOR_0_SPEC>;
|
||||
#[doc = "Field `CORE_0_DRAM0_PMS_MONITOR_LOCK` reader - Set 1 to lock core0 dram0 permission monitor configuration register."]
|
||||
pub type CORE_0_DRAM0_PMS_MONITOR_LOCK_R = crate::BitReader;
|
||||
#[doc = "Field `CORE_0_DRAM0_PMS_MONITOR_LOCK` writer - Set 1 to lock core0 dram0 permission monitor configuration register."]
|
||||
pub type CORE_0_DRAM0_PMS_MONITOR_LOCK_W<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
impl R {
|
||||
#[doc = "Bit 0 - Set 1 to lock core0 dram0 permission monitor configuration register."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_dram0_pms_monitor_lock(&self) -> CORE_0_DRAM0_PMS_MONITOR_LOCK_R {
|
||||
CORE_0_DRAM0_PMS_MONITOR_LOCK_R::new((self.bits & 1) != 0)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_0_DRAM0_PMS_MONITOR_0")
|
||||
.field(
|
||||
"core_0_dram0_pms_monitor_lock",
|
||||
&self.core_0_dram0_pms_monitor_lock(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bit 0 - Set 1 to lock core0 dram0 permission monitor configuration register."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_dram0_pms_monitor_lock(
|
||||
&mut self,
|
||||
) -> CORE_0_DRAM0_PMS_MONITOR_LOCK_W<CORE_0_DRAM0_PMS_MONITOR_0_SPEC> {
|
||||
CORE_0_DRAM0_PMS_MONITOR_LOCK_W::new(self, 0)
|
||||
}
|
||||
}
|
||||
#[doc = "core0 dram0 permission monitor configuration register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_dram0_pms_monitor_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_dram0_pms_monitor_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_0_DRAM0_PMS_MONITOR_0_SPEC;
|
||||
impl crate::RegisterSpec for CORE_0_DRAM0_PMS_MONITOR_0_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_0_dram0_pms_monitor_0::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_0_DRAM0_PMS_MONITOR_0_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_0_dram0_pms_monitor_0::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_0_DRAM0_PMS_MONITOR_0_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_0_DRAM0_PMS_MONITOR_0 to value 0"]
|
||||
impl crate::Resettable for CORE_0_DRAM0_PMS_MONITOR_0_SPEC {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
@@ -0,0 +1,72 @@
|
||||
#[doc = "Register `CORE_0_DRAM0_PMS_MONITOR_1` reader"]
|
||||
pub type R = crate::R<CORE_0_DRAM0_PMS_MONITOR_1_SPEC>;
|
||||
#[doc = "Register `CORE_0_DRAM0_PMS_MONITOR_1` writer"]
|
||||
pub type W = crate::W<CORE_0_DRAM0_PMS_MONITOR_1_SPEC>;
|
||||
#[doc = "Field `CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR` reader - Set 1 to clear core0 dram0 permission monior interrupt."]
|
||||
pub type CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_R = crate::BitReader;
|
||||
#[doc = "Field `CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR` writer - Set 1 to clear core0 dram0 permission monior interrupt."]
|
||||
pub type CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN` reader - Set 1 to enable core0 dram0 permission monitor interrupt."]
|
||||
pub type CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_R = crate::BitReader;
|
||||
#[doc = "Field `CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN` writer - Set 1 to enable core0 dram0 permission monitor interrupt."]
|
||||
pub type CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
impl R {
|
||||
#[doc = "Bit 0 - Set 1 to clear core0 dram0 permission monior interrupt."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_dram0_pms_monitor_violate_clr(&self) -> CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_R {
|
||||
CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_R::new((self.bits & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 1 - Set 1 to enable core0 dram0 permission monitor interrupt."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_dram0_pms_monitor_violate_en(&self) -> CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_R {
|
||||
CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_R::new(((self.bits >> 1) & 1) != 0)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_0_DRAM0_PMS_MONITOR_1")
|
||||
.field(
|
||||
"core_0_dram0_pms_monitor_violate_clr",
|
||||
&self.core_0_dram0_pms_monitor_violate_clr(),
|
||||
)
|
||||
.field(
|
||||
"core_0_dram0_pms_monitor_violate_en",
|
||||
&self.core_0_dram0_pms_monitor_violate_en(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bit 0 - Set 1 to clear core0 dram0 permission monior interrupt."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_dram0_pms_monitor_violate_clr(
|
||||
&mut self,
|
||||
) -> CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_W<CORE_0_DRAM0_PMS_MONITOR_1_SPEC> {
|
||||
CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_W::new(self, 0)
|
||||
}
|
||||
#[doc = "Bit 1 - Set 1 to enable core0 dram0 permission monitor interrupt."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_dram0_pms_monitor_violate_en(
|
||||
&mut self,
|
||||
) -> CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_W<CORE_0_DRAM0_PMS_MONITOR_1_SPEC> {
|
||||
CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_W::new(self, 1)
|
||||
}
|
||||
}
|
||||
#[doc = "core0 dram0 permission monitor configuration register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_dram0_pms_monitor_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_dram0_pms_monitor_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_0_DRAM0_PMS_MONITOR_1_SPEC;
|
||||
impl crate::RegisterSpec for CORE_0_DRAM0_PMS_MONITOR_1_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_0_dram0_pms_monitor_1::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_0_DRAM0_PMS_MONITOR_1_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_0_dram0_pms_monitor_1::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_0_DRAM0_PMS_MONITOR_1_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_0_DRAM0_PMS_MONITOR_1 to value 0x03"]
|
||||
impl crate::Resettable for CORE_0_DRAM0_PMS_MONITOR_1_SPEC {
|
||||
const RESET_VALUE: u32 = 0x03;
|
||||
}
|
||||
@@ -0,0 +1,72 @@
|
||||
#[doc = "Register `CORE_0_DRAM0_PMS_MONITOR_2` reader"]
|
||||
pub type R = crate::R<CORE_0_DRAM0_PMS_MONITOR_2_SPEC>;
|
||||
#[doc = "Field `CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR` reader - recorded core0 dram0 permission monitor interrupt status."]
|
||||
pub type CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_R = crate::BitReader;
|
||||
#[doc = "Field `CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK` reader - recorded core0 dram0 lock status, 1 means s32c1i access."]
|
||||
pub type CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_R = crate::BitReader;
|
||||
#[doc = "Field `CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD` reader - recorded core0 dram0 world status, 0x1 means world0, 0x2 means world1."]
|
||||
pub type CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR` reader - recorded core0 dram0 address\\[25:4\\] status when core0 dram0 violated permission,the real address is 0x3c000000+addr*16"]
|
||||
pub type CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_R = crate::FieldReader<u32>;
|
||||
impl R {
|
||||
#[doc = "Bit 0 - recorded core0 dram0 permission monitor interrupt status."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_dram0_pms_monitor_violate_intr(&self) -> CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_R {
|
||||
CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_R::new((self.bits & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 1 - recorded core0 dram0 lock status, 1 means s32c1i access."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_dram0_pms_monitor_violate_status_lock(
|
||||
&self,
|
||||
) -> CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_R {
|
||||
CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_R::new(((self.bits >> 1) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bits 2:3 - recorded core0 dram0 world status, 0x1 means world0, 0x2 means world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_dram0_pms_monitor_violate_status_world(
|
||||
&self,
|
||||
) -> CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_R {
|
||||
CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_R::new(((self.bits >> 2) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 4:25 - recorded core0 dram0 address\\[25:4\\] status when core0 dram0 violated permission,the real address is 0x3c000000+addr*16"]
|
||||
#[inline(always)]
|
||||
pub fn core_0_dram0_pms_monitor_violate_status_addr(
|
||||
&self,
|
||||
) -> CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_R {
|
||||
CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_R::new((self.bits >> 4) & 0x003f_ffff)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_0_DRAM0_PMS_MONITOR_2")
|
||||
.field(
|
||||
"core_0_dram0_pms_monitor_violate_intr",
|
||||
&self.core_0_dram0_pms_monitor_violate_intr(),
|
||||
)
|
||||
.field(
|
||||
"core_0_dram0_pms_monitor_violate_status_lock",
|
||||
&self.core_0_dram0_pms_monitor_violate_status_lock(),
|
||||
)
|
||||
.field(
|
||||
"core_0_dram0_pms_monitor_violate_status_world",
|
||||
&self.core_0_dram0_pms_monitor_violate_status_world(),
|
||||
)
|
||||
.field(
|
||||
"core_0_dram0_pms_monitor_violate_status_addr",
|
||||
&self.core_0_dram0_pms_monitor_violate_status_addr(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
#[doc = "core0 dram0 permission monitor configuration register 2.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_dram0_pms_monitor_2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_0_DRAM0_PMS_MONITOR_2_SPEC;
|
||||
impl crate::RegisterSpec for CORE_0_DRAM0_PMS_MONITOR_2_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_0_dram0_pms_monitor_2::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_0_DRAM0_PMS_MONITOR_2_SPEC {}
|
||||
#[doc = "`reset()` method sets CORE_0_DRAM0_PMS_MONITOR_2 to value 0"]
|
||||
impl crate::Resettable for CORE_0_DRAM0_PMS_MONITOR_2_SPEC {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
@@ -0,0 +1,48 @@
|
||||
#[doc = "Register `CORE_0_DRAM0_PMS_MONITOR_3` reader"]
|
||||
pub type R = crate::R<CORE_0_DRAM0_PMS_MONITOR_3_SPEC>;
|
||||
#[doc = "Field `CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR` reader - recorded core0 dram0 wr status, 1 means store, 0 means load."]
|
||||
pub type CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_R = crate::BitReader;
|
||||
#[doc = "Field `CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN` reader - recorded core0 dram0 byteen status."]
|
||||
pub type CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_R = crate::FieldReader<u16>;
|
||||
impl R {
|
||||
#[doc = "Bit 0 - recorded core0 dram0 wr status, 1 means store, 0 means load."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_dram0_pms_monitor_violate_status_wr(
|
||||
&self,
|
||||
) -> CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_R {
|
||||
CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_R::new((self.bits & 1) != 0)
|
||||
}
|
||||
#[doc = "Bits 1:16 - recorded core0 dram0 byteen status."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_dram0_pms_monitor_violate_status_byteen(
|
||||
&self,
|
||||
) -> CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_R {
|
||||
CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_R::new(((self.bits >> 1) & 0xffff) as u16)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_0_DRAM0_PMS_MONITOR_3")
|
||||
.field(
|
||||
"core_0_dram0_pms_monitor_violate_status_wr",
|
||||
&self.core_0_dram0_pms_monitor_violate_status_wr(),
|
||||
)
|
||||
.field(
|
||||
"core_0_dram0_pms_monitor_violate_status_byteen",
|
||||
&self.core_0_dram0_pms_monitor_violate_status_byteen(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
#[doc = "core0 dram0 permission monitor configuration register 3.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_dram0_pms_monitor_3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_0_DRAM0_PMS_MONITOR_3_SPEC;
|
||||
impl crate::RegisterSpec for CORE_0_DRAM0_PMS_MONITOR_3_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_0_dram0_pms_monitor_3::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_0_DRAM0_PMS_MONITOR_3_SPEC {}
|
||||
#[doc = "`reset()` method sets CORE_0_DRAM0_PMS_MONITOR_3 to value 0"]
|
||||
impl crate::Resettable for CORE_0_DRAM0_PMS_MONITOR_3_SPEC {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
@@ -0,0 +1,52 @@
|
||||
#[doc = "Register `CORE_0_IRAM0_PMS_MONITOR_0` reader"]
|
||||
pub type R = crate::R<CORE_0_IRAM0_PMS_MONITOR_0_SPEC>;
|
||||
#[doc = "Register `CORE_0_IRAM0_PMS_MONITOR_0` writer"]
|
||||
pub type W = crate::W<CORE_0_IRAM0_PMS_MONITOR_0_SPEC>;
|
||||
#[doc = "Field `CORE_0_IRAM0_PMS_MONITOR_LOCK` reader - Set 1 to lock core0 iram0 permission monitor register"]
|
||||
pub type CORE_0_IRAM0_PMS_MONITOR_LOCK_R = crate::BitReader;
|
||||
#[doc = "Field `CORE_0_IRAM0_PMS_MONITOR_LOCK` writer - Set 1 to lock core0 iram0 permission monitor register"]
|
||||
pub type CORE_0_IRAM0_PMS_MONITOR_LOCK_W<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
impl R {
|
||||
#[doc = "Bit 0 - Set 1 to lock core0 iram0 permission monitor register"]
|
||||
#[inline(always)]
|
||||
pub fn core_0_iram0_pms_monitor_lock(&self) -> CORE_0_IRAM0_PMS_MONITOR_LOCK_R {
|
||||
CORE_0_IRAM0_PMS_MONITOR_LOCK_R::new((self.bits & 1) != 0)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_0_IRAM0_PMS_MONITOR_0")
|
||||
.field(
|
||||
"core_0_iram0_pms_monitor_lock",
|
||||
&self.core_0_iram0_pms_monitor_lock(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bit 0 - Set 1 to lock core0 iram0 permission monitor register"]
|
||||
#[inline(always)]
|
||||
pub fn core_0_iram0_pms_monitor_lock(
|
||||
&mut self,
|
||||
) -> CORE_0_IRAM0_PMS_MONITOR_LOCK_W<CORE_0_IRAM0_PMS_MONITOR_0_SPEC> {
|
||||
CORE_0_IRAM0_PMS_MONITOR_LOCK_W::new(self, 0)
|
||||
}
|
||||
}
|
||||
#[doc = "core0 iram0 permission monitor configuration register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_iram0_pms_monitor_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_iram0_pms_monitor_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_0_IRAM0_PMS_MONITOR_0_SPEC;
|
||||
impl crate::RegisterSpec for CORE_0_IRAM0_PMS_MONITOR_0_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_0_iram0_pms_monitor_0::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_0_IRAM0_PMS_MONITOR_0_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_0_iram0_pms_monitor_0::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_0_IRAM0_PMS_MONITOR_0_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_0_IRAM0_PMS_MONITOR_0 to value 0"]
|
||||
impl crate::Resettable for CORE_0_IRAM0_PMS_MONITOR_0_SPEC {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
@@ -0,0 +1,72 @@
|
||||
#[doc = "Register `CORE_0_IRAM0_PMS_MONITOR_1` reader"]
|
||||
pub type R = crate::R<CORE_0_IRAM0_PMS_MONITOR_1_SPEC>;
|
||||
#[doc = "Register `CORE_0_IRAM0_PMS_MONITOR_1` writer"]
|
||||
pub type W = crate::W<CORE_0_IRAM0_PMS_MONITOR_1_SPEC>;
|
||||
#[doc = "Field `CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR` reader - Set 1 to clear core0 iram0 permission violated interrupt"]
|
||||
pub type CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_R = crate::BitReader;
|
||||
#[doc = "Field `CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR` writer - Set 1 to clear core0 iram0 permission violated interrupt"]
|
||||
pub type CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN` reader - Set 1 to enable core0 iram0 permission monitor, when core0_iram violated permission, will trigger interrupt"]
|
||||
pub type CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_R = crate::BitReader;
|
||||
#[doc = "Field `CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN` writer - Set 1 to enable core0 iram0 permission monitor, when core0_iram violated permission, will trigger interrupt"]
|
||||
pub type CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
impl R {
|
||||
#[doc = "Bit 0 - Set 1 to clear core0 iram0 permission violated interrupt"]
|
||||
#[inline(always)]
|
||||
pub fn core_0_iram0_pms_monitor_violate_clr(&self) -> CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_R {
|
||||
CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_R::new((self.bits & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 1 - Set 1 to enable core0 iram0 permission monitor, when core0_iram violated permission, will trigger interrupt"]
|
||||
#[inline(always)]
|
||||
pub fn core_0_iram0_pms_monitor_violate_en(&self) -> CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_R {
|
||||
CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_R::new(((self.bits >> 1) & 1) != 0)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_0_IRAM0_PMS_MONITOR_1")
|
||||
.field(
|
||||
"core_0_iram0_pms_monitor_violate_clr",
|
||||
&self.core_0_iram0_pms_monitor_violate_clr(),
|
||||
)
|
||||
.field(
|
||||
"core_0_iram0_pms_monitor_violate_en",
|
||||
&self.core_0_iram0_pms_monitor_violate_en(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bit 0 - Set 1 to clear core0 iram0 permission violated interrupt"]
|
||||
#[inline(always)]
|
||||
pub fn core_0_iram0_pms_monitor_violate_clr(
|
||||
&mut self,
|
||||
) -> CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_W<CORE_0_IRAM0_PMS_MONITOR_1_SPEC> {
|
||||
CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_W::new(self, 0)
|
||||
}
|
||||
#[doc = "Bit 1 - Set 1 to enable core0 iram0 permission monitor, when core0_iram violated permission, will trigger interrupt"]
|
||||
#[inline(always)]
|
||||
pub fn core_0_iram0_pms_monitor_violate_en(
|
||||
&mut self,
|
||||
) -> CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_W<CORE_0_IRAM0_PMS_MONITOR_1_SPEC> {
|
||||
CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_W::new(self, 1)
|
||||
}
|
||||
}
|
||||
#[doc = "core0 iram0 permission monitor configuration register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_iram0_pms_monitor_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_iram0_pms_monitor_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_0_IRAM0_PMS_MONITOR_1_SPEC;
|
||||
impl crate::RegisterSpec for CORE_0_IRAM0_PMS_MONITOR_1_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_0_iram0_pms_monitor_1::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_0_IRAM0_PMS_MONITOR_1_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_0_iram0_pms_monitor_1::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_0_IRAM0_PMS_MONITOR_1_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_0_IRAM0_PMS_MONITOR_1 to value 0x03"]
|
||||
impl crate::Resettable for CORE_0_IRAM0_PMS_MONITOR_1_SPEC {
|
||||
const RESET_VALUE: u32 = 0x03;
|
||||
}
|
||||
@@ -0,0 +1,85 @@
|
||||
#[doc = "Register `CORE_0_IRAM0_PMS_MONITOR_2` reader"]
|
||||
pub type R = crate::R<CORE_0_IRAM0_PMS_MONITOR_2_SPEC>;
|
||||
#[doc = "Field `CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR` reader - recorded core0 iram0 pms monitor interrupt status."]
|
||||
pub type CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_R = crate::BitReader;
|
||||
#[doc = "Field `CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR` reader - recorded core0 iram0 wr status, only if loadstore is 1 have meaning, 1(store), 0(load)."]
|
||||
pub type CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_R = crate::BitReader;
|
||||
#[doc = "Field `CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE` reader - recorded core0 iram0 loadstore status, indicated the type of operation, 0(fetch), 1(load/store)."]
|
||||
pub type CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_R = crate::BitReader;
|
||||
#[doc = "Field `CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD` reader - recorded core0 iram0 world status, 0x01 means world0, 0x10 means world1."]
|
||||
pub type CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR` reader - recorded core0 iram0 address \\[25:2\\] status when core0 iram0 violated permission, the real address is 0x40000000+addr*4"]
|
||||
pub type CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_R = crate::FieldReader<u32>;
|
||||
impl R {
|
||||
#[doc = "Bit 0 - recorded core0 iram0 pms monitor interrupt status."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_iram0_pms_monitor_violate_intr(&self) -> CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_R {
|
||||
CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_R::new((self.bits & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 1 - recorded core0 iram0 wr status, only if loadstore is 1 have meaning, 1(store), 0(load)."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_iram0_pms_monitor_violate_status_wr(
|
||||
&self,
|
||||
) -> CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_R {
|
||||
CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_R::new(((self.bits >> 1) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 2 - recorded core0 iram0 loadstore status, indicated the type of operation, 0(fetch), 1(load/store)."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_iram0_pms_monitor_violate_status_loadstore(
|
||||
&self,
|
||||
) -> CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_R {
|
||||
CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_R::new(((self.bits >> 2) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bits 3:4 - recorded core0 iram0 world status, 0x01 means world0, 0x10 means world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_iram0_pms_monitor_violate_status_world(
|
||||
&self,
|
||||
) -> CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_R {
|
||||
CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_R::new(((self.bits >> 3) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 5:28 - recorded core0 iram0 address \\[25:2\\] status when core0 iram0 violated permission, the real address is 0x40000000+addr*4"]
|
||||
#[inline(always)]
|
||||
pub fn core_0_iram0_pms_monitor_violate_status_addr(
|
||||
&self,
|
||||
) -> CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_R {
|
||||
CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_R::new((self.bits >> 5) & 0x00ff_ffff)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_0_IRAM0_PMS_MONITOR_2")
|
||||
.field(
|
||||
"core_0_iram0_pms_monitor_violate_intr",
|
||||
&self.core_0_iram0_pms_monitor_violate_intr(),
|
||||
)
|
||||
.field(
|
||||
"core_0_iram0_pms_monitor_violate_status_wr",
|
||||
&self.core_0_iram0_pms_monitor_violate_status_wr(),
|
||||
)
|
||||
.field(
|
||||
"core_0_iram0_pms_monitor_violate_status_loadstore",
|
||||
&self.core_0_iram0_pms_monitor_violate_status_loadstore(),
|
||||
)
|
||||
.field(
|
||||
"core_0_iram0_pms_monitor_violate_status_world",
|
||||
&self.core_0_iram0_pms_monitor_violate_status_world(),
|
||||
)
|
||||
.field(
|
||||
"core_0_iram0_pms_monitor_violate_status_addr",
|
||||
&self.core_0_iram0_pms_monitor_violate_status_addr(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
#[doc = "core0 iram0 permission monitor configuration register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_iram0_pms_monitor_2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_0_IRAM0_PMS_MONITOR_2_SPEC;
|
||||
impl crate::RegisterSpec for CORE_0_IRAM0_PMS_MONITOR_2_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_0_iram0_pms_monitor_2::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_0_IRAM0_PMS_MONITOR_2_SPEC {}
|
||||
#[doc = "`reset()` method sets CORE_0_IRAM0_PMS_MONITOR_2 to value 0"]
|
||||
impl crate::Resettable for CORE_0_IRAM0_PMS_MONITOR_2_SPEC {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
@@ -0,0 +1,52 @@
|
||||
#[doc = "Register `CORE_0_PIF_PMS_CONSTRAIN_0` reader"]
|
||||
pub type R = crate::R<CORE_0_PIF_PMS_CONSTRAIN_0_SPEC>;
|
||||
#[doc = "Register `CORE_0_PIF_PMS_CONSTRAIN_0` writer"]
|
||||
pub type W = crate::W<CORE_0_PIF_PMS_CONSTRAIN_0_SPEC>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_LOCK` reader - Set 1 to lock core0 access peripherals permission Configuration Register."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_LOCK_R = crate::BitReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_LOCK` writer - Set 1 to lock core0 access peripherals permission Configuration Register."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_LOCK_W<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
impl R {
|
||||
#[doc = "Bit 0 - Set 1 to lock core0 access peripherals permission Configuration Register."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_lock(&self) -> CORE_0_PIF_PMS_CONSTRAIN_LOCK_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_LOCK_R::new((self.bits & 1) != 0)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_0_PIF_PMS_CONSTRAIN_0")
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_lock",
|
||||
&self.core_0_pif_pms_constrain_lock(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bit 0 - Set 1 to lock core0 access peripherals permission Configuration Register."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_lock(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_LOCK_W<CORE_0_PIF_PMS_CONSTRAIN_0_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_LOCK_W::new(self, 0)
|
||||
}
|
||||
}
|
||||
#[doc = "Core0 access peripherals permission configuration register 0.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_pif_pms_constrain_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_pif_pms_constrain_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_0_PIF_PMS_CONSTRAIN_0_SPEC;
|
||||
impl crate::RegisterSpec for CORE_0_PIF_PMS_CONSTRAIN_0_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_0_pif_pms_constrain_0::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_0_PIF_PMS_CONSTRAIN_0_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_0_pif_pms_constrain_0::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_0_PIF_PMS_CONSTRAIN_0_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_0_PIF_PMS_CONSTRAIN_0 to value 0"]
|
||||
impl crate::Resettable for CORE_0_PIF_PMS_CONSTRAIN_0_SPEC {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
@@ -0,0 +1,300 @@
|
||||
#[doc = "Register `CORE_0_PIF_PMS_CONSTRAIN_1` reader"]
|
||||
pub type R = crate::R<CORE_0_PIF_PMS_CONSTRAIN_1_SPEC>;
|
||||
#[doc = "Register `CORE_0_PIF_PMS_CONSTRAIN_1` writer"]
|
||||
pub type W = crate::W<CORE_0_PIF_PMS_CONSTRAIN_1_SPEC>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART` reader - Core0 access uart permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART` writer - Core0 access uart permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1` reader - Core0 access g0spi_1 permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1` writer - Core0 access g0spi_1 permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0` reader - Core0 access g0spi_0 permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0` writer - Core0 access g0spi_0 permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO` reader - Core0 access gpio permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO` writer - Core0 access gpio permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2` reader - Core0 access fe2 permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2` writer - Core0 access fe2 permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE` reader - Core0 access fe permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE` writer - Core0 access fe permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC` reader - Core0 access rtc permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC` writer - Core0 access rtc permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX` reader - Core0 access io_mux permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX` writer - Core0 access io_mux permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF` reader - Core0 access hinf permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF` writer - Core0 access hinf permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC` reader - Core0 access misc permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC` writer - Core0 access misc permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C` reader - Core0 access i2c permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C` writer - Core0 access i2c permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0` reader - Core0 access i2s0 permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0` writer - Core0 access i2s0 permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1` reader - Core0 access uart1 permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1` writer - Core0 access uart1 permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:1 - Core0 access uart permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_uart(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_R::new((self.bits & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 2:3 - Core0 access g0spi_1 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_g0spi_1(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_R::new(((self.bits >> 2) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 4:5 - Core0 access g0spi_0 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_g0spi_0(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_R::new(((self.bits >> 4) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 6:7 - Core0 access gpio permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_gpio(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_R::new(((self.bits >> 6) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 8:9 - Core0 access fe2 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_fe2(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_R::new(((self.bits >> 8) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 10:11 - Core0 access fe permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_fe(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_R::new(((self.bits >> 10) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 14:15 - Core0 access rtc permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_rtc(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_R::new(((self.bits >> 14) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 16:17 - Core0 access io_mux permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_io_mux(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_R::new(((self.bits >> 16) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 20:21 - Core0 access hinf permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_hinf(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF_R::new(((self.bits >> 20) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 24:25 - Core0 access misc permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_misc(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_R::new(((self.bits >> 24) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 26:27 - Core0 access i2c permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_i2c(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_R::new(((self.bits >> 26) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 28:29 - Core0 access i2s0 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_i2s0(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_R::new(((self.bits >> 28) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 30:31 - Core0 access uart1 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_uart1(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_R::new(((self.bits >> 30) & 3) as u8)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_0_PIF_PMS_CONSTRAIN_1")
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_0_uart",
|
||||
&self.core_0_pif_pms_constrain_world_0_uart(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_0_g0spi_1",
|
||||
&self.core_0_pif_pms_constrain_world_0_g0spi_1(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_0_g0spi_0",
|
||||
&self.core_0_pif_pms_constrain_world_0_g0spi_0(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_0_gpio",
|
||||
&self.core_0_pif_pms_constrain_world_0_gpio(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_0_fe2",
|
||||
&self.core_0_pif_pms_constrain_world_0_fe2(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_0_fe",
|
||||
&self.core_0_pif_pms_constrain_world_0_fe(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_0_rtc",
|
||||
&self.core_0_pif_pms_constrain_world_0_rtc(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_0_io_mux",
|
||||
&self.core_0_pif_pms_constrain_world_0_io_mux(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_0_hinf",
|
||||
&self.core_0_pif_pms_constrain_world_0_hinf(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_0_misc",
|
||||
&self.core_0_pif_pms_constrain_world_0_misc(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_0_i2c",
|
||||
&self.core_0_pif_pms_constrain_world_0_i2c(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_0_i2s0",
|
||||
&self.core_0_pif_pms_constrain_world_0_i2s0(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_0_uart1",
|
||||
&self.core_0_pif_pms_constrain_world_0_uart1(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:1 - Core0 access uart permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_uart(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_W<CORE_0_PIF_PMS_CONSTRAIN_1_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_W::new(self, 0)
|
||||
}
|
||||
#[doc = "Bits 2:3 - Core0 access g0spi_1 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_g0spi_1(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_W<CORE_0_PIF_PMS_CONSTRAIN_1_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_W::new(self, 2)
|
||||
}
|
||||
#[doc = "Bits 4:5 - Core0 access g0spi_0 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_g0spi_0(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_W<CORE_0_PIF_PMS_CONSTRAIN_1_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_W::new(self, 4)
|
||||
}
|
||||
#[doc = "Bits 6:7 - Core0 access gpio permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_gpio(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_W<CORE_0_PIF_PMS_CONSTRAIN_1_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_W::new(self, 6)
|
||||
}
|
||||
#[doc = "Bits 8:9 - Core0 access fe2 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_fe2(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_W<CORE_0_PIF_PMS_CONSTRAIN_1_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_W::new(self, 8)
|
||||
}
|
||||
#[doc = "Bits 10:11 - Core0 access fe permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_fe(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_W<CORE_0_PIF_PMS_CONSTRAIN_1_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_W::new(self, 10)
|
||||
}
|
||||
#[doc = "Bits 14:15 - Core0 access rtc permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_rtc(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_W<CORE_0_PIF_PMS_CONSTRAIN_1_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_W::new(self, 14)
|
||||
}
|
||||
#[doc = "Bits 16:17 - Core0 access io_mux permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_io_mux(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_W<CORE_0_PIF_PMS_CONSTRAIN_1_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_W::new(self, 16)
|
||||
}
|
||||
#[doc = "Bits 20:21 - Core0 access hinf permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_hinf(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF_W<CORE_0_PIF_PMS_CONSTRAIN_1_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF_W::new(self, 20)
|
||||
}
|
||||
#[doc = "Bits 24:25 - Core0 access misc permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_misc(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_W<CORE_0_PIF_PMS_CONSTRAIN_1_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_W::new(self, 24)
|
||||
}
|
||||
#[doc = "Bits 26:27 - Core0 access i2c permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_i2c(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_W<CORE_0_PIF_PMS_CONSTRAIN_1_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_W::new(self, 26)
|
||||
}
|
||||
#[doc = "Bits 28:29 - Core0 access i2s0 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_i2s0(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_W<CORE_0_PIF_PMS_CONSTRAIN_1_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_W::new(self, 28)
|
||||
}
|
||||
#[doc = "Bits 30:31 - Core0 access uart1 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_uart1(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_W<CORE_0_PIF_PMS_CONSTRAIN_1_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_W::new(self, 30)
|
||||
}
|
||||
}
|
||||
#[doc = "Core0 access peripherals permission configuration register 1.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_pif_pms_constrain_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_pif_pms_constrain_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_0_PIF_PMS_CONSTRAIN_1_SPEC;
|
||||
impl crate::RegisterSpec for CORE_0_PIF_PMS_CONSTRAIN_1_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_0_pif_pms_constrain_1::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_0_PIF_PMS_CONSTRAIN_1_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_0_pif_pms_constrain_1::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_0_PIF_PMS_CONSTRAIN_1_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_0_PIF_PMS_CONSTRAIN_1 to value 0xff33_cfff"]
|
||||
impl crate::Resettable for CORE_0_PIF_PMS_CONSTRAIN_1_SPEC {
|
||||
const RESET_VALUE: u32 = 0xff33_cfff;
|
||||
}
|
||||
@@ -0,0 +1,120 @@
|
||||
#[doc = "Register `CORE_0_PIF_PMS_CONSTRAIN_10` reader"]
|
||||
pub type R = crate::R<CORE_0_PIF_PMS_CONSTRAIN_10_SPEC>;
|
||||
#[doc = "Register `CORE_0_PIF_PMS_CONSTRAIN_10` writer"]
|
||||
pub type W = crate::W<CORE_0_PIF_PMS_CONSTRAIN_10_SPEC>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L` reader - RTCFast memory low region permission in world 0 for core0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L` writer - RTCFast memory low region permission in world 0 for core0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H` reader - RTCFast memory high region permission in world 0 for core0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H` writer - RTCFast memory high region permission in world 0 for core0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L` reader - RTCFast memory low region permission in world 1 for core0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L` writer - RTCFast memory low region permission in world 1 for core0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H` reader - RTCFast memory high region permission in world 1 for core0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H` writer - RTCFast memory high region permission in world 1 for core0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:2 - RTCFast memory low region permission in world 0 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_rtcfast_world_0_l(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_R::new((self.bits & 7) as u8)
|
||||
}
|
||||
#[doc = "Bits 3:5 - RTCFast memory high region permission in world 0 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_rtcfast_world_0_h(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_R::new(((self.bits >> 3) & 7) as u8)
|
||||
}
|
||||
#[doc = "Bits 6:8 - RTCFast memory low region permission in world 1 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_rtcfast_world_1_l(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_R::new(((self.bits >> 6) & 7) as u8)
|
||||
}
|
||||
#[doc = "Bits 9:11 - RTCFast memory high region permission in world 1 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_rtcfast_world_1_h(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_R::new(((self.bits >> 9) & 7) as u8)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_0_PIF_PMS_CONSTRAIN_10")
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_rtcfast_world_0_l",
|
||||
&self.core_0_pif_pms_constrain_rtcfast_world_0_l(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_rtcfast_world_0_h",
|
||||
&self.core_0_pif_pms_constrain_rtcfast_world_0_h(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_rtcfast_world_1_l",
|
||||
&self.core_0_pif_pms_constrain_rtcfast_world_1_l(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_rtcfast_world_1_h",
|
||||
&self.core_0_pif_pms_constrain_rtcfast_world_1_h(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:2 - RTCFast memory low region permission in world 0 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_rtcfast_world_0_l(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_W<CORE_0_PIF_PMS_CONSTRAIN_10_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_W::new(self, 0)
|
||||
}
|
||||
#[doc = "Bits 3:5 - RTCFast memory high region permission in world 0 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_rtcfast_world_0_h(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_W<CORE_0_PIF_PMS_CONSTRAIN_10_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_W::new(self, 3)
|
||||
}
|
||||
#[doc = "Bits 6:8 - RTCFast memory low region permission in world 1 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_rtcfast_world_1_l(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_W<CORE_0_PIF_PMS_CONSTRAIN_10_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_W::new(self, 6)
|
||||
}
|
||||
#[doc = "Bits 9:11 - RTCFast memory high region permission in world 1 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_rtcfast_world_1_h(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_W<CORE_0_PIF_PMS_CONSTRAIN_10_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_W::new(self, 9)
|
||||
}
|
||||
}
|
||||
#[doc = "Core0 access peripherals permission configuration register 10.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_pif_pms_constrain_10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_pif_pms_constrain_10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_0_PIF_PMS_CONSTRAIN_10_SPEC;
|
||||
impl crate::RegisterSpec for CORE_0_PIF_PMS_CONSTRAIN_10_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_0_pif_pms_constrain_10::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_0_PIF_PMS_CONSTRAIN_10_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_0_pif_pms_constrain_10::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_0_PIF_PMS_CONSTRAIN_10_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_0_PIF_PMS_CONSTRAIN_10 to value 0x0fff"]
|
||||
impl crate::Resettable for CORE_0_PIF_PMS_CONSTRAIN_10_SPEC {
|
||||
const RESET_VALUE: u32 = 0x0fff;
|
||||
}
|
||||
@@ -0,0 +1,82 @@
|
||||
#[doc = "Register `CORE_0_PIF_PMS_CONSTRAIN_11` reader"]
|
||||
pub type R = crate::R<CORE_0_PIF_PMS_CONSTRAIN_11_SPEC>;
|
||||
#[doc = "Register `CORE_0_PIF_PMS_CONSTRAIN_11` writer"]
|
||||
pub type W = crate::W<CORE_0_PIF_PMS_CONSTRAIN_11_SPEC>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0` reader - RTCSlow_0 memory split address in world 0 for core0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_R = crate::FieldReader<u16>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0` writer - RTCSlow_0 memory split address in world 0 for core0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_W<'a, REG> =
|
||||
crate::FieldWriter<'a, REG, 11, u16>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1` reader - RTCSlow_0 memory split address in world 1 for core0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_R = crate::FieldReader<u16>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1` writer - RTCSlow_0 memory split address in world 1 for core0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_W<'a, REG> =
|
||||
crate::FieldWriter<'a, REG, 11, u16>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:10 - RTCSlow_0 memory split address in world 0 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_rtcslow_0_spltaddr_world_0(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_R::new((self.bits & 0x07ff) as u16)
|
||||
}
|
||||
#[doc = "Bits 11:21 - RTCSlow_0 memory split address in world 1 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_rtcslow_0_spltaddr_world_1(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_R::new(
|
||||
((self.bits >> 11) & 0x07ff) as u16,
|
||||
)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_0_PIF_PMS_CONSTRAIN_11")
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_rtcslow_0_spltaddr_world_0",
|
||||
&self.core_0_pif_pms_constrain_rtcslow_0_spltaddr_world_0(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_rtcslow_0_spltaddr_world_1",
|
||||
&self.core_0_pif_pms_constrain_rtcslow_0_spltaddr_world_1(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:10 - RTCSlow_0 memory split address in world 0 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_rtcslow_0_spltaddr_world_0(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_W<CORE_0_PIF_PMS_CONSTRAIN_11_SPEC>
|
||||
{
|
||||
CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_W::new(self, 0)
|
||||
}
|
||||
#[doc = "Bits 11:21 - RTCSlow_0 memory split address in world 1 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_rtcslow_0_spltaddr_world_1(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_W<CORE_0_PIF_PMS_CONSTRAIN_11_SPEC>
|
||||
{
|
||||
CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_W::new(self, 11)
|
||||
}
|
||||
}
|
||||
#[doc = "Core0 access peripherals permission configuration register 11.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_pif_pms_constrain_11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_pif_pms_constrain_11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_0_PIF_PMS_CONSTRAIN_11_SPEC;
|
||||
impl crate::RegisterSpec for CORE_0_PIF_PMS_CONSTRAIN_11_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_0_pif_pms_constrain_11::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_0_PIF_PMS_CONSTRAIN_11_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_0_pif_pms_constrain_11::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_0_PIF_PMS_CONSTRAIN_11_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_0_PIF_PMS_CONSTRAIN_11 to value 0x003f_ffff"]
|
||||
impl crate::Resettable for CORE_0_PIF_PMS_CONSTRAIN_11_SPEC {
|
||||
const RESET_VALUE: u32 = 0x003f_ffff;
|
||||
}
|
||||
@@ -0,0 +1,120 @@
|
||||
#[doc = "Register `CORE_0_PIF_PMS_CONSTRAIN_12` reader"]
|
||||
pub type R = crate::R<CORE_0_PIF_PMS_CONSTRAIN_12_SPEC>;
|
||||
#[doc = "Register `CORE_0_PIF_PMS_CONSTRAIN_12` writer"]
|
||||
pub type W = crate::W<CORE_0_PIF_PMS_CONSTRAIN_12_SPEC>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L` reader - RTCSlow_0 memory low region permission in world 0 for core0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L` writer - RTCSlow_0 memory low region permission in world 0 for core0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H` reader - RTCSlow_0 memory high region permission in world 0 for core0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H` writer - RTCSlow_0 memory high region permission in world 0 for core0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L` reader - RTCSlow_0 memory low region permission in world 1 for core0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L` writer - RTCSlow_0 memory low region permission in world 1 for core0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H` reader - RTCSlow_0 memory high region permission in world 1 for core0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H` writer - RTCSlow_0 memory high region permission in world 1 for core0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:2 - RTCSlow_0 memory low region permission in world 0 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_rtcslow_0_world_0_l(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_R::new((self.bits & 7) as u8)
|
||||
}
|
||||
#[doc = "Bits 3:5 - RTCSlow_0 memory high region permission in world 0 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_rtcslow_0_world_0_h(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_R::new(((self.bits >> 3) & 7) as u8)
|
||||
}
|
||||
#[doc = "Bits 6:8 - RTCSlow_0 memory low region permission in world 1 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_rtcslow_0_world_1_l(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_R::new(((self.bits >> 6) & 7) as u8)
|
||||
}
|
||||
#[doc = "Bits 9:11 - RTCSlow_0 memory high region permission in world 1 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_rtcslow_0_world_1_h(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_R::new(((self.bits >> 9) & 7) as u8)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_0_PIF_PMS_CONSTRAIN_12")
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_rtcslow_0_world_0_l",
|
||||
&self.core_0_pif_pms_constrain_rtcslow_0_world_0_l(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_rtcslow_0_world_0_h",
|
||||
&self.core_0_pif_pms_constrain_rtcslow_0_world_0_h(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_rtcslow_0_world_1_l",
|
||||
&self.core_0_pif_pms_constrain_rtcslow_0_world_1_l(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_rtcslow_0_world_1_h",
|
||||
&self.core_0_pif_pms_constrain_rtcslow_0_world_1_h(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:2 - RTCSlow_0 memory low region permission in world 0 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_rtcslow_0_world_0_l(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_W<CORE_0_PIF_PMS_CONSTRAIN_12_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_W::new(self, 0)
|
||||
}
|
||||
#[doc = "Bits 3:5 - RTCSlow_0 memory high region permission in world 0 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_rtcslow_0_world_0_h(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_W<CORE_0_PIF_PMS_CONSTRAIN_12_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_W::new(self, 3)
|
||||
}
|
||||
#[doc = "Bits 6:8 - RTCSlow_0 memory low region permission in world 1 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_rtcslow_0_world_1_l(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_W<CORE_0_PIF_PMS_CONSTRAIN_12_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_W::new(self, 6)
|
||||
}
|
||||
#[doc = "Bits 9:11 - RTCSlow_0 memory high region permission in world 1 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_rtcslow_0_world_1_h(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_W<CORE_0_PIF_PMS_CONSTRAIN_12_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_W::new(self, 9)
|
||||
}
|
||||
}
|
||||
#[doc = "Core0 access peripherals permission configuration register 12.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_pif_pms_constrain_12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_pif_pms_constrain_12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_0_PIF_PMS_CONSTRAIN_12_SPEC;
|
||||
impl crate::RegisterSpec for CORE_0_PIF_PMS_CONSTRAIN_12_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_0_pif_pms_constrain_12::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_0_PIF_PMS_CONSTRAIN_12_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_0_pif_pms_constrain_12::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_0_PIF_PMS_CONSTRAIN_12_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_0_PIF_PMS_CONSTRAIN_12 to value 0x0fff"]
|
||||
impl crate::Resettable for CORE_0_PIF_PMS_CONSTRAIN_12_SPEC {
|
||||
const RESET_VALUE: u32 = 0x0fff;
|
||||
}
|
||||
@@ -0,0 +1,82 @@
|
||||
#[doc = "Register `CORE_0_PIF_PMS_CONSTRAIN_13` reader"]
|
||||
pub type R = crate::R<CORE_0_PIF_PMS_CONSTRAIN_13_SPEC>;
|
||||
#[doc = "Register `CORE_0_PIF_PMS_CONSTRAIN_13` writer"]
|
||||
pub type W = crate::W<CORE_0_PIF_PMS_CONSTRAIN_13_SPEC>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0` reader - RTCSlow_1 memory split address in world 0 for core0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_R = crate::FieldReader<u16>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0` writer - RTCSlow_1 memory split address in world 0 for core0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_W<'a, REG> =
|
||||
crate::FieldWriter<'a, REG, 11, u16>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1` reader - RTCSlow_1 memory split address in world 1 for core0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_R = crate::FieldReader<u16>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1` writer - RTCSlow_1 memory split address in world 1 for core0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_W<'a, REG> =
|
||||
crate::FieldWriter<'a, REG, 11, u16>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:10 - RTCSlow_1 memory split address in world 0 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_rtcslow_1_spltaddr_world_0(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_R::new((self.bits & 0x07ff) as u16)
|
||||
}
|
||||
#[doc = "Bits 11:21 - RTCSlow_1 memory split address in world 1 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_rtcslow_1_spltaddr_world_1(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_R::new(
|
||||
((self.bits >> 11) & 0x07ff) as u16,
|
||||
)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_0_PIF_PMS_CONSTRAIN_13")
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_rtcslow_1_spltaddr_world_0",
|
||||
&self.core_0_pif_pms_constrain_rtcslow_1_spltaddr_world_0(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_rtcslow_1_spltaddr_world_1",
|
||||
&self.core_0_pif_pms_constrain_rtcslow_1_spltaddr_world_1(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:10 - RTCSlow_1 memory split address in world 0 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_rtcslow_1_spltaddr_world_0(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_W<CORE_0_PIF_PMS_CONSTRAIN_13_SPEC>
|
||||
{
|
||||
CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_W::new(self, 0)
|
||||
}
|
||||
#[doc = "Bits 11:21 - RTCSlow_1 memory split address in world 1 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_rtcslow_1_spltaddr_world_1(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_W<CORE_0_PIF_PMS_CONSTRAIN_13_SPEC>
|
||||
{
|
||||
CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_W::new(self, 11)
|
||||
}
|
||||
}
|
||||
#[doc = "Core0 access peripherals permission configuration register 13.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_pif_pms_constrain_13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_pif_pms_constrain_13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_0_PIF_PMS_CONSTRAIN_13_SPEC;
|
||||
impl crate::RegisterSpec for CORE_0_PIF_PMS_CONSTRAIN_13_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_0_pif_pms_constrain_13::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_0_PIF_PMS_CONSTRAIN_13_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_0_pif_pms_constrain_13::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_0_PIF_PMS_CONSTRAIN_13_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_0_PIF_PMS_CONSTRAIN_13 to value 0x003f_ffff"]
|
||||
impl crate::Resettable for CORE_0_PIF_PMS_CONSTRAIN_13_SPEC {
|
||||
const RESET_VALUE: u32 = 0x003f_ffff;
|
||||
}
|
||||
@@ -0,0 +1,120 @@
|
||||
#[doc = "Register `CORE_0_PIF_PMS_CONSTRAIN_14` reader"]
|
||||
pub type R = crate::R<CORE_0_PIF_PMS_CONSTRAIN_14_SPEC>;
|
||||
#[doc = "Register `CORE_0_PIF_PMS_CONSTRAIN_14` writer"]
|
||||
pub type W = crate::W<CORE_0_PIF_PMS_CONSTRAIN_14_SPEC>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L` reader - RTCSlow_1 memory low region permission in world 0 for core0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L` writer - RTCSlow_1 memory low region permission in world 0 for core0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H` reader - RTCSlow_1 memory high region permission in world 0 for core0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H` writer - RTCSlow_1 memory high region permission in world 0 for core0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L` reader - RTCSlow_1 memory low region permission in world 1 for core0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L` writer - RTCSlow_1 memory low region permission in world 1 for core0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H` reader - RTCSlow_1 memory high region permission in world 1 for core0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H` writer - RTCSlow_1 memory high region permission in world 1 for core0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:2 - RTCSlow_1 memory low region permission in world 0 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_rtcslow_1_world_0_l(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_R::new((self.bits & 7) as u8)
|
||||
}
|
||||
#[doc = "Bits 3:5 - RTCSlow_1 memory high region permission in world 0 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_rtcslow_1_world_0_h(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_R::new(((self.bits >> 3) & 7) as u8)
|
||||
}
|
||||
#[doc = "Bits 6:8 - RTCSlow_1 memory low region permission in world 1 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_rtcslow_1_world_1_l(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_R::new(((self.bits >> 6) & 7) as u8)
|
||||
}
|
||||
#[doc = "Bits 9:11 - RTCSlow_1 memory high region permission in world 1 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_rtcslow_1_world_1_h(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_R::new(((self.bits >> 9) & 7) as u8)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_0_PIF_PMS_CONSTRAIN_14")
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_rtcslow_1_world_0_l",
|
||||
&self.core_0_pif_pms_constrain_rtcslow_1_world_0_l(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_rtcslow_1_world_0_h",
|
||||
&self.core_0_pif_pms_constrain_rtcslow_1_world_0_h(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_rtcslow_1_world_1_l",
|
||||
&self.core_0_pif_pms_constrain_rtcslow_1_world_1_l(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_rtcslow_1_world_1_h",
|
||||
&self.core_0_pif_pms_constrain_rtcslow_1_world_1_h(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:2 - RTCSlow_1 memory low region permission in world 0 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_rtcslow_1_world_0_l(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_W<CORE_0_PIF_PMS_CONSTRAIN_14_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_W::new(self, 0)
|
||||
}
|
||||
#[doc = "Bits 3:5 - RTCSlow_1 memory high region permission in world 0 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_rtcslow_1_world_0_h(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_W<CORE_0_PIF_PMS_CONSTRAIN_14_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_W::new(self, 3)
|
||||
}
|
||||
#[doc = "Bits 6:8 - RTCSlow_1 memory low region permission in world 1 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_rtcslow_1_world_1_l(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_W<CORE_0_PIF_PMS_CONSTRAIN_14_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_W::new(self, 6)
|
||||
}
|
||||
#[doc = "Bits 9:11 - RTCSlow_1 memory high region permission in world 1 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_rtcslow_1_world_1_h(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_W<CORE_0_PIF_PMS_CONSTRAIN_14_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_W::new(self, 9)
|
||||
}
|
||||
}
|
||||
#[doc = "Core0 access peripherals permission configuration register 14.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_pif_pms_constrain_14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_pif_pms_constrain_14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_0_PIF_PMS_CONSTRAIN_14_SPEC;
|
||||
impl crate::RegisterSpec for CORE_0_PIF_PMS_CONSTRAIN_14_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_0_pif_pms_constrain_14::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_0_PIF_PMS_CONSTRAIN_14_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_0_pif_pms_constrain_14::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_0_PIF_PMS_CONSTRAIN_14_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_0_PIF_PMS_CONSTRAIN_14 to value 0x0fff"]
|
||||
impl crate::Resettable for CORE_0_PIF_PMS_CONSTRAIN_14_SPEC {
|
||||
const RESET_VALUE: u32 = 0x0fff;
|
||||
}
|
||||
@@ -0,0 +1,326 @@
|
||||
#[doc = "Register `CORE_0_PIF_PMS_CONSTRAIN_2` reader"]
|
||||
pub type R = crate::R<CORE_0_PIF_PMS_CONSTRAIN_2_SPEC>;
|
||||
#[doc = "Register `CORE_0_PIF_PMS_CONSTRAIN_2` writer"]
|
||||
pub type W = crate::W<CORE_0_PIF_PMS_CONSTRAIN_2_SPEC>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT` reader - Core0 access bt permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT` writer - Core0 access bt permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0` reader - Core0 access i2c_ext0 permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0` writer - Core0 access i2c_ext0 permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0` reader - Core0 access uhci0 permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0` writer - Core0 access uhci0 permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST` reader - Core0 access slchost permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST` writer - Core0 access slchost permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT` reader - Core0 access rmt permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT` writer - Core0 access rmt permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT` reader - Core0 access pcnt permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT` writer - Core0 access pcnt permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC` reader - Core0 access slc permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC` writer - Core0 access slc permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC` reader - Core0 access ledc permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC` writer - Core0 access ledc permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP` reader - Core0 access backup permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP` writer - Core0 access backup permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB` reader - Core0 access bb permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB` writer - Core0 access bb permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0` reader - Core0 access pwm0 permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0` writer - Core0 access pwm0 permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP` reader - Core0 access timergroup permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP` writer - Core0 access timergroup permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1` reader - Core0 access timergroup1 permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1` writer - Core0 access timergroup1 permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER` reader - Core0 access systimer permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER` writer - Core0 access systimer permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:1 - Core0 access bt permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_bt(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_R::new((self.bits & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 4:5 - Core0 access i2c_ext0 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_i2c_ext0(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_R::new(((self.bits >> 4) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 6:7 - Core0 access uhci0 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_uhci0(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_R::new(((self.bits >> 6) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 8:9 - Core0 access slchost permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_slchost(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_R::new(((self.bits >> 8) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 10:11 - Core0 access rmt permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_rmt(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_R::new(((self.bits >> 10) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 12:13 - Core0 access pcnt permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_pcnt(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_R::new(((self.bits >> 12) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 14:15 - Core0 access slc permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_slc(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC_R::new(((self.bits >> 14) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 16:17 - Core0 access ledc permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_ledc(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_R::new(((self.bits >> 16) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 18:19 - Core0 access backup permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_backup(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_R::new(((self.bits >> 18) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 22:23 - Core0 access bb permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_bb(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_R::new(((self.bits >> 22) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 24:25 - Core0 access pwm0 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_pwm0(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_R::new(((self.bits >> 24) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 26:27 - Core0 access timergroup permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_timergroup(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_R::new(((self.bits >> 26) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 28:29 - Core0 access timergroup1 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_timergroup1(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_R::new(((self.bits >> 28) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 30:31 - Core0 access systimer permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_systimer(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_R::new(((self.bits >> 30) & 3) as u8)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_0_PIF_PMS_CONSTRAIN_2")
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_0_bt",
|
||||
&self.core_0_pif_pms_constrain_world_0_bt(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_0_i2c_ext0",
|
||||
&self.core_0_pif_pms_constrain_world_0_i2c_ext0(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_0_uhci0",
|
||||
&self.core_0_pif_pms_constrain_world_0_uhci0(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_0_slchost",
|
||||
&self.core_0_pif_pms_constrain_world_0_slchost(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_0_rmt",
|
||||
&self.core_0_pif_pms_constrain_world_0_rmt(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_0_pcnt",
|
||||
&self.core_0_pif_pms_constrain_world_0_pcnt(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_0_slc",
|
||||
&self.core_0_pif_pms_constrain_world_0_slc(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_0_ledc",
|
||||
&self.core_0_pif_pms_constrain_world_0_ledc(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_0_backup",
|
||||
&self.core_0_pif_pms_constrain_world_0_backup(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_0_bb",
|
||||
&self.core_0_pif_pms_constrain_world_0_bb(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_0_pwm0",
|
||||
&self.core_0_pif_pms_constrain_world_0_pwm0(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_0_timergroup",
|
||||
&self.core_0_pif_pms_constrain_world_0_timergroup(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_0_timergroup1",
|
||||
&self.core_0_pif_pms_constrain_world_0_timergroup1(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_0_systimer",
|
||||
&self.core_0_pif_pms_constrain_world_0_systimer(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:1 - Core0 access bt permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_bt(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_W<CORE_0_PIF_PMS_CONSTRAIN_2_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_W::new(self, 0)
|
||||
}
|
||||
#[doc = "Bits 4:5 - Core0 access i2c_ext0 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_i2c_ext0(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_W<CORE_0_PIF_PMS_CONSTRAIN_2_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_W::new(self, 4)
|
||||
}
|
||||
#[doc = "Bits 6:7 - Core0 access uhci0 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_uhci0(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_W<CORE_0_PIF_PMS_CONSTRAIN_2_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_W::new(self, 6)
|
||||
}
|
||||
#[doc = "Bits 8:9 - Core0 access slchost permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_slchost(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_W<CORE_0_PIF_PMS_CONSTRAIN_2_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_W::new(self, 8)
|
||||
}
|
||||
#[doc = "Bits 10:11 - Core0 access rmt permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_rmt(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_W<CORE_0_PIF_PMS_CONSTRAIN_2_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_W::new(self, 10)
|
||||
}
|
||||
#[doc = "Bits 12:13 - Core0 access pcnt permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_pcnt(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_W<CORE_0_PIF_PMS_CONSTRAIN_2_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_W::new(self, 12)
|
||||
}
|
||||
#[doc = "Bits 14:15 - Core0 access slc permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_slc(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC_W<CORE_0_PIF_PMS_CONSTRAIN_2_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC_W::new(self, 14)
|
||||
}
|
||||
#[doc = "Bits 16:17 - Core0 access ledc permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_ledc(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_W<CORE_0_PIF_PMS_CONSTRAIN_2_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_W::new(self, 16)
|
||||
}
|
||||
#[doc = "Bits 18:19 - Core0 access backup permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_backup(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_W<CORE_0_PIF_PMS_CONSTRAIN_2_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_W::new(self, 18)
|
||||
}
|
||||
#[doc = "Bits 22:23 - Core0 access bb permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_bb(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_W<CORE_0_PIF_PMS_CONSTRAIN_2_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_W::new(self, 22)
|
||||
}
|
||||
#[doc = "Bits 24:25 - Core0 access pwm0 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_pwm0(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_W<CORE_0_PIF_PMS_CONSTRAIN_2_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_W::new(self, 24)
|
||||
}
|
||||
#[doc = "Bits 26:27 - Core0 access timergroup permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_timergroup(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_W<CORE_0_PIF_PMS_CONSTRAIN_2_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_W::new(self, 26)
|
||||
}
|
||||
#[doc = "Bits 28:29 - Core0 access timergroup1 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_timergroup1(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_W<CORE_0_PIF_PMS_CONSTRAIN_2_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_W::new(self, 28)
|
||||
}
|
||||
#[doc = "Bits 30:31 - Core0 access systimer permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_systimer(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_W<CORE_0_PIF_PMS_CONSTRAIN_2_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_W::new(self, 30)
|
||||
}
|
||||
}
|
||||
#[doc = "Core0 access peripherals permission configuration register 2.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_pif_pms_constrain_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_pif_pms_constrain_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_0_PIF_PMS_CONSTRAIN_2_SPEC;
|
||||
impl crate::RegisterSpec for CORE_0_PIF_PMS_CONSTRAIN_2_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_0_pif_pms_constrain_2::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_0_PIF_PMS_CONSTRAIN_2_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_0_pif_pms_constrain_2::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_0_PIF_PMS_CONSTRAIN_2_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_0_PIF_PMS_CONSTRAIN_2 to value 0xffcf_fff3"]
|
||||
impl crate::Resettable for CORE_0_PIF_PMS_CONSTRAIN_2_SPEC {
|
||||
const RESET_VALUE: u32 = 0xffcf_fff3;
|
||||
}
|
||||
@@ -0,0 +1,286 @@
|
||||
#[doc = "Register `CORE_0_PIF_PMS_CONSTRAIN_3` reader"]
|
||||
pub type R = crate::R<CORE_0_PIF_PMS_CONSTRAIN_3_SPEC>;
|
||||
#[doc = "Register `CORE_0_PIF_PMS_CONSTRAIN_3` writer"]
|
||||
pub type W = crate::W<CORE_0_PIF_PMS_CONSTRAIN_3_SPEC>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2` reader - Core0 access spi_2 permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2` writer - Core0 access spi_2 permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3` reader - Core0 access spi_3 permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3` writer - Core0 access spi_3 permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL` reader - Core0 access apb_ctrl permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL` writer - Core0 access apb_ctrl permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1` reader - Core0 access i2c_ext1 permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1` writer - Core0 access i2c_ext1 permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST` reader - Core0 access sdio_host permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST` writer - Core0 access sdio_host permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN` reader - Core0 access can permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN` writer - Core0 access can permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1` reader - Core0 access pwm1 permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1` writer - Core0 access pwm1 permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1` reader - Core0 access i2s1 permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1` writer - Core0 access i2s1 permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2` reader - Core0 access uart2 permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2` writer - Core0 access uart2 permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT` reader - Core0 access rwbt permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT` writer - Core0 access rwbt permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC` reader - Core0 access wifimac permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC` writer - Core0 access wifimac permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR` reader - Core0 access pwr permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR` writer - Core0 access pwr permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:1 - Core0 access spi_2 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_spi_2(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_R::new((self.bits & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 2:3 - Core0 access spi_3 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_spi_3(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_R::new(((self.bits >> 2) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 4:5 - Core0 access apb_ctrl permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_apb_ctrl(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_R::new(((self.bits >> 4) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 6:7 - Core0 access i2c_ext1 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_i2c_ext1(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_R::new(((self.bits >> 6) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 8:9 - Core0 access sdio_host permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_sdio_host(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_R::new(((self.bits >> 8) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 10:11 - Core0 access can permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_can(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_R::new(((self.bits >> 10) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 12:13 - Core0 access pwm1 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_pwm1(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_R::new(((self.bits >> 12) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 14:15 - Core0 access i2s1 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_i2s1(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_R::new(((self.bits >> 14) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 16:17 - Core0 access uart2 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_uart2(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2_R::new(((self.bits >> 16) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 22:23 - Core0 access rwbt permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_rwbt(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_R::new(((self.bits >> 22) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 26:27 - Core0 access wifimac permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_wifimac(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_R::new(((self.bits >> 26) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 28:29 - Core0 access pwr permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_pwr(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_R::new(((self.bits >> 28) & 3) as u8)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_0_PIF_PMS_CONSTRAIN_3")
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_0_spi_2",
|
||||
&self.core_0_pif_pms_constrain_world_0_spi_2(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_0_spi_3",
|
||||
&self.core_0_pif_pms_constrain_world_0_spi_3(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_0_apb_ctrl",
|
||||
&self.core_0_pif_pms_constrain_world_0_apb_ctrl(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_0_i2c_ext1",
|
||||
&self.core_0_pif_pms_constrain_world_0_i2c_ext1(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_0_sdio_host",
|
||||
&self.core_0_pif_pms_constrain_world_0_sdio_host(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_0_can",
|
||||
&self.core_0_pif_pms_constrain_world_0_can(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_0_pwm1",
|
||||
&self.core_0_pif_pms_constrain_world_0_pwm1(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_0_i2s1",
|
||||
&self.core_0_pif_pms_constrain_world_0_i2s1(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_0_uart2",
|
||||
&self.core_0_pif_pms_constrain_world_0_uart2(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_0_rwbt",
|
||||
&self.core_0_pif_pms_constrain_world_0_rwbt(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_0_wifimac",
|
||||
&self.core_0_pif_pms_constrain_world_0_wifimac(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_0_pwr",
|
||||
&self.core_0_pif_pms_constrain_world_0_pwr(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:1 - Core0 access spi_2 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_spi_2(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_W<CORE_0_PIF_PMS_CONSTRAIN_3_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_W::new(self, 0)
|
||||
}
|
||||
#[doc = "Bits 2:3 - Core0 access spi_3 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_spi_3(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_W<CORE_0_PIF_PMS_CONSTRAIN_3_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_W::new(self, 2)
|
||||
}
|
||||
#[doc = "Bits 4:5 - Core0 access apb_ctrl permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_apb_ctrl(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_W<CORE_0_PIF_PMS_CONSTRAIN_3_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_W::new(self, 4)
|
||||
}
|
||||
#[doc = "Bits 6:7 - Core0 access i2c_ext1 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_i2c_ext1(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_W<CORE_0_PIF_PMS_CONSTRAIN_3_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_W::new(self, 6)
|
||||
}
|
||||
#[doc = "Bits 8:9 - Core0 access sdio_host permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_sdio_host(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_W<CORE_0_PIF_PMS_CONSTRAIN_3_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_W::new(self, 8)
|
||||
}
|
||||
#[doc = "Bits 10:11 - Core0 access can permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_can(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_W<CORE_0_PIF_PMS_CONSTRAIN_3_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_W::new(self, 10)
|
||||
}
|
||||
#[doc = "Bits 12:13 - Core0 access pwm1 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_pwm1(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_W<CORE_0_PIF_PMS_CONSTRAIN_3_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_W::new(self, 12)
|
||||
}
|
||||
#[doc = "Bits 14:15 - Core0 access i2s1 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_i2s1(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_W<CORE_0_PIF_PMS_CONSTRAIN_3_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_W::new(self, 14)
|
||||
}
|
||||
#[doc = "Bits 16:17 - Core0 access uart2 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_uart2(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2_W<CORE_0_PIF_PMS_CONSTRAIN_3_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2_W::new(self, 16)
|
||||
}
|
||||
#[doc = "Bits 22:23 - Core0 access rwbt permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_rwbt(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_W<CORE_0_PIF_PMS_CONSTRAIN_3_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_W::new(self, 22)
|
||||
}
|
||||
#[doc = "Bits 26:27 - Core0 access wifimac permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_wifimac(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_W<CORE_0_PIF_PMS_CONSTRAIN_3_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_W::new(self, 26)
|
||||
}
|
||||
#[doc = "Bits 28:29 - Core0 access pwr permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_pwr(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_W<CORE_0_PIF_PMS_CONSTRAIN_3_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_W::new(self, 28)
|
||||
}
|
||||
}
|
||||
#[doc = "Core0 access peripherals permission configuration register 3.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_pif_pms_constrain_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_pif_pms_constrain_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_0_PIF_PMS_CONSTRAIN_3_SPEC;
|
||||
impl crate::RegisterSpec for CORE_0_PIF_PMS_CONSTRAIN_3_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_0_pif_pms_constrain_3::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_0_PIF_PMS_CONSTRAIN_3_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_0_pif_pms_constrain_3::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_0_PIF_PMS_CONSTRAIN_3_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_0_PIF_PMS_CONSTRAIN_3 to value 0x3cc3_ffff"]
|
||||
impl crate::Resettable for CORE_0_PIF_PMS_CONSTRAIN_3_SPEC {
|
||||
const RESET_VALUE: u32 = 0x3cc3_ffff;
|
||||
}
|
||||
@@ -0,0 +1,379 @@
|
||||
#[doc = "Register `CORE_0_PIF_PMS_CONSTRAIN_4` reader"]
|
||||
pub type R = crate::R<CORE_0_PIF_PMS_CONSTRAIN_4_SPEC>;
|
||||
#[doc = "Register `CORE_0_PIF_PMS_CONSTRAIN_4` writer"]
|
||||
pub type W = crate::W<CORE_0_PIF_PMS_CONSTRAIN_4_SPEC>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE` reader - Core0 access usb_device permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE` writer - Core0 access usb_device permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP` reader - Core0 access usb_wrap permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP` writer - Core0 access usb_wrap permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI` reader - Core0 access crypto_peri permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI` writer - Core0 access crypto_peri permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA` reader - Core0 access crypto_dma permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA` writer - Core0 access crypto_dma permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC` reader - Core0 access apb_adc permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC` writer - Core0 access apb_adc permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM` reader - Core0 access lcd_cam permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM` writer - Core0 access lcd_cam permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR` reader - Core0 access bt_pwr permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR` writer - Core0 access bt_pwr permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB` reader - Core0 access usb permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB` writer - Core0 access usb permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM` reader - Core0 access system permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM` writer - Core0 access system permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE` reader - Core0 access sensitive permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE` writer - Core0 access sensitive permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT` reader - Core0 access interrupt permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT` writer - Core0 access interrupt permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY` reader - Core0 access dma_copy permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY` writer - Core0 access dma_copy permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG` reader - Core0 access cache_config permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG` writer - Core0 access cache_config permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD` reader - Core0 access ad permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD` writer - Core0 access ad permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO` reader - Core0 access dio permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO` writer - Core0 access dio permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER` reader - Core0 access world_controller permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER` writer - Core0 access world_controller permission in world0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_W<'a, REG> =
|
||||
crate::FieldWriter<'a, REG, 2>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:1 - Core0 access usb_device permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_usb_device(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_R::new((self.bits & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 2:3 - Core0 access usb_wrap permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_usb_wrap(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_R::new(((self.bits >> 2) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 4:5 - Core0 access crypto_peri permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_crypto_peri(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_R::new(((self.bits >> 4) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 6:7 - Core0 access crypto_dma permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_crypto_dma(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_R::new(((self.bits >> 6) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 8:9 - Core0 access apb_adc permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_apb_adc(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_R::new(((self.bits >> 8) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 10:11 - Core0 access lcd_cam permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_lcd_cam(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_R::new(((self.bits >> 10) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 12:13 - Core0 access bt_pwr permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_bt_pwr(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_R::new(((self.bits >> 12) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 14:15 - Core0 access usb permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_usb(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_R::new(((self.bits >> 14) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 16:17 - Core0 access system permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_system(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_R::new(((self.bits >> 16) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 18:19 - Core0 access sensitive permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_sensitive(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_R::new(((self.bits >> 18) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 20:21 - Core0 access interrupt permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_interrupt(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_R::new(((self.bits >> 20) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 22:23 - Core0 access dma_copy permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_dma_copy(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_R::new(((self.bits >> 22) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 24:25 - Core0 access cache_config permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_cache_config(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_R::new(((self.bits >> 24) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 26:27 - Core0 access ad permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_ad(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_R::new(((self.bits >> 26) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 28:29 - Core0 access dio permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_dio(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_R::new(((self.bits >> 28) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 30:31 - Core0 access world_controller permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_world_controller(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_R::new(((self.bits >> 30) & 3) as u8)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_0_PIF_PMS_CONSTRAIN_4")
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_0_usb_device",
|
||||
&self.core_0_pif_pms_constrain_world_0_usb_device(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_0_usb_wrap",
|
||||
&self.core_0_pif_pms_constrain_world_0_usb_wrap(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_0_crypto_peri",
|
||||
&self.core_0_pif_pms_constrain_world_0_crypto_peri(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_0_crypto_dma",
|
||||
&self.core_0_pif_pms_constrain_world_0_crypto_dma(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_0_apb_adc",
|
||||
&self.core_0_pif_pms_constrain_world_0_apb_adc(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_0_lcd_cam",
|
||||
&self.core_0_pif_pms_constrain_world_0_lcd_cam(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_0_bt_pwr",
|
||||
&self.core_0_pif_pms_constrain_world_0_bt_pwr(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_0_usb",
|
||||
&self.core_0_pif_pms_constrain_world_0_usb(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_0_system",
|
||||
&self.core_0_pif_pms_constrain_world_0_system(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_0_sensitive",
|
||||
&self.core_0_pif_pms_constrain_world_0_sensitive(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_0_interrupt",
|
||||
&self.core_0_pif_pms_constrain_world_0_interrupt(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_0_dma_copy",
|
||||
&self.core_0_pif_pms_constrain_world_0_dma_copy(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_0_cache_config",
|
||||
&self.core_0_pif_pms_constrain_world_0_cache_config(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_0_ad",
|
||||
&self.core_0_pif_pms_constrain_world_0_ad(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_0_dio",
|
||||
&self.core_0_pif_pms_constrain_world_0_dio(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_0_world_controller",
|
||||
&self.core_0_pif_pms_constrain_world_0_world_controller(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:1 - Core0 access usb_device permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_usb_device(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_W<CORE_0_PIF_PMS_CONSTRAIN_4_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_W::new(self, 0)
|
||||
}
|
||||
#[doc = "Bits 2:3 - Core0 access usb_wrap permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_usb_wrap(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_W<CORE_0_PIF_PMS_CONSTRAIN_4_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_W::new(self, 2)
|
||||
}
|
||||
#[doc = "Bits 4:5 - Core0 access crypto_peri permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_crypto_peri(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_W<CORE_0_PIF_PMS_CONSTRAIN_4_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_W::new(self, 4)
|
||||
}
|
||||
#[doc = "Bits 6:7 - Core0 access crypto_dma permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_crypto_dma(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_W<CORE_0_PIF_PMS_CONSTRAIN_4_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_W::new(self, 6)
|
||||
}
|
||||
#[doc = "Bits 8:9 - Core0 access apb_adc permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_apb_adc(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_W<CORE_0_PIF_PMS_CONSTRAIN_4_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_W::new(self, 8)
|
||||
}
|
||||
#[doc = "Bits 10:11 - Core0 access lcd_cam permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_lcd_cam(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_W<CORE_0_PIF_PMS_CONSTRAIN_4_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_W::new(self, 10)
|
||||
}
|
||||
#[doc = "Bits 12:13 - Core0 access bt_pwr permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_bt_pwr(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_W<CORE_0_PIF_PMS_CONSTRAIN_4_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_W::new(self, 12)
|
||||
}
|
||||
#[doc = "Bits 14:15 - Core0 access usb permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_usb(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_W<CORE_0_PIF_PMS_CONSTRAIN_4_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_W::new(self, 14)
|
||||
}
|
||||
#[doc = "Bits 16:17 - Core0 access system permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_system(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_W<CORE_0_PIF_PMS_CONSTRAIN_4_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_W::new(self, 16)
|
||||
}
|
||||
#[doc = "Bits 18:19 - Core0 access sensitive permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_sensitive(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_W<CORE_0_PIF_PMS_CONSTRAIN_4_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_W::new(self, 18)
|
||||
}
|
||||
#[doc = "Bits 20:21 - Core0 access interrupt permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_interrupt(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_W<CORE_0_PIF_PMS_CONSTRAIN_4_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_W::new(self, 20)
|
||||
}
|
||||
#[doc = "Bits 22:23 - Core0 access dma_copy permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_dma_copy(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_W<CORE_0_PIF_PMS_CONSTRAIN_4_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_W::new(self, 22)
|
||||
}
|
||||
#[doc = "Bits 24:25 - Core0 access cache_config permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_cache_config(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_W<CORE_0_PIF_PMS_CONSTRAIN_4_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_W::new(self, 24)
|
||||
}
|
||||
#[doc = "Bits 26:27 - Core0 access ad permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_ad(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_W<CORE_0_PIF_PMS_CONSTRAIN_4_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_W::new(self, 26)
|
||||
}
|
||||
#[doc = "Bits 28:29 - Core0 access dio permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_dio(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_W<CORE_0_PIF_PMS_CONSTRAIN_4_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_W::new(self, 28)
|
||||
}
|
||||
#[doc = "Bits 30:31 - Core0 access world_controller permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_0_world_controller(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_W<CORE_0_PIF_PMS_CONSTRAIN_4_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_W::new(self, 30)
|
||||
}
|
||||
}
|
||||
#[doc = "Core0 access peripherals permission configuration register 4.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_pif_pms_constrain_4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_pif_pms_constrain_4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_0_PIF_PMS_CONSTRAIN_4_SPEC;
|
||||
impl crate::RegisterSpec for CORE_0_PIF_PMS_CONSTRAIN_4_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_0_pif_pms_constrain_4::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_0_PIF_PMS_CONSTRAIN_4_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_0_pif_pms_constrain_4::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_0_PIF_PMS_CONSTRAIN_4_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_0_PIF_PMS_CONSTRAIN_4 to value 0xffff_ffff"]
|
||||
impl crate::Resettable for CORE_0_PIF_PMS_CONSTRAIN_4_SPEC {
|
||||
const RESET_VALUE: u32 = 0xffff_ffff;
|
||||
}
|
||||
@@ -0,0 +1,300 @@
|
||||
#[doc = "Register `CORE_0_PIF_PMS_CONSTRAIN_5` reader"]
|
||||
pub type R = crate::R<CORE_0_PIF_PMS_CONSTRAIN_5_SPEC>;
|
||||
#[doc = "Register `CORE_0_PIF_PMS_CONSTRAIN_5` writer"]
|
||||
pub type W = crate::W<CORE_0_PIF_PMS_CONSTRAIN_5_SPEC>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART` reader - Core0 access uart permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART` writer - Core0 access uart permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1` reader - Core0 access g0spi_1 permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1` writer - Core0 access g0spi_1 permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0` reader - Core0 access g0spi_0 permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0` writer - Core0 access g0spi_0 permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO` reader - Core0 access gpio permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO` writer - Core0 access gpio permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2` reader - Core0 access fe2 permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2` writer - Core0 access fe2 permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE` reader - Core0 access fe permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE` writer - Core0 access fe permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC` reader - Core0 access rtc permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC` writer - Core0 access rtc permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX` reader - Core0 access io_mux permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX` writer - Core0 access io_mux permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF` reader - Core0 access hinf permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF` writer - Core0 access hinf permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC` reader - Core0 access misc permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC` writer - Core0 access misc permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C` reader - Core0 access i2c permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C` writer - Core0 access i2c permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0` reader - Core0 access i2s0 permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0` writer - Core0 access i2s0 permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1` reader - Core0 access uart1 permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1` writer - Core0 access uart1 permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:1 - Core0 access uart permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_uart(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_R::new((self.bits & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 2:3 - Core0 access g0spi_1 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_g0spi_1(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_R::new(((self.bits >> 2) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 4:5 - Core0 access g0spi_0 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_g0spi_0(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_R::new(((self.bits >> 4) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 6:7 - Core0 access gpio permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_gpio(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_R::new(((self.bits >> 6) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 8:9 - Core0 access fe2 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_fe2(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_R::new(((self.bits >> 8) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 10:11 - Core0 access fe permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_fe(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_R::new(((self.bits >> 10) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 14:15 - Core0 access rtc permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_rtc(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_R::new(((self.bits >> 14) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 16:17 - Core0 access io_mux permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_io_mux(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_R::new(((self.bits >> 16) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 20:21 - Core0 access hinf permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_hinf(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF_R::new(((self.bits >> 20) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 24:25 - Core0 access misc permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_misc(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_R::new(((self.bits >> 24) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 26:27 - Core0 access i2c permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_i2c(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_R::new(((self.bits >> 26) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 28:29 - Core0 access i2s0 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_i2s0(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_R::new(((self.bits >> 28) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 30:31 - Core0 access uart1 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_uart1(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_R::new(((self.bits >> 30) & 3) as u8)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_0_PIF_PMS_CONSTRAIN_5")
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_1_uart",
|
||||
&self.core_0_pif_pms_constrain_world_1_uart(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_1_g0spi_1",
|
||||
&self.core_0_pif_pms_constrain_world_1_g0spi_1(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_1_g0spi_0",
|
||||
&self.core_0_pif_pms_constrain_world_1_g0spi_0(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_1_gpio",
|
||||
&self.core_0_pif_pms_constrain_world_1_gpio(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_1_fe2",
|
||||
&self.core_0_pif_pms_constrain_world_1_fe2(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_1_fe",
|
||||
&self.core_0_pif_pms_constrain_world_1_fe(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_1_rtc",
|
||||
&self.core_0_pif_pms_constrain_world_1_rtc(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_1_io_mux",
|
||||
&self.core_0_pif_pms_constrain_world_1_io_mux(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_1_hinf",
|
||||
&self.core_0_pif_pms_constrain_world_1_hinf(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_1_misc",
|
||||
&self.core_0_pif_pms_constrain_world_1_misc(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_1_i2c",
|
||||
&self.core_0_pif_pms_constrain_world_1_i2c(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_1_i2s0",
|
||||
&self.core_0_pif_pms_constrain_world_1_i2s0(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_1_uart1",
|
||||
&self.core_0_pif_pms_constrain_world_1_uart1(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:1 - Core0 access uart permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_uart(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_W<CORE_0_PIF_PMS_CONSTRAIN_5_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_W::new(self, 0)
|
||||
}
|
||||
#[doc = "Bits 2:3 - Core0 access g0spi_1 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_g0spi_1(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_W<CORE_0_PIF_PMS_CONSTRAIN_5_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_W::new(self, 2)
|
||||
}
|
||||
#[doc = "Bits 4:5 - Core0 access g0spi_0 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_g0spi_0(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_W<CORE_0_PIF_PMS_CONSTRAIN_5_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_W::new(self, 4)
|
||||
}
|
||||
#[doc = "Bits 6:7 - Core0 access gpio permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_gpio(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_W<CORE_0_PIF_PMS_CONSTRAIN_5_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_W::new(self, 6)
|
||||
}
|
||||
#[doc = "Bits 8:9 - Core0 access fe2 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_fe2(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_W<CORE_0_PIF_PMS_CONSTRAIN_5_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_W::new(self, 8)
|
||||
}
|
||||
#[doc = "Bits 10:11 - Core0 access fe permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_fe(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_W<CORE_0_PIF_PMS_CONSTRAIN_5_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_W::new(self, 10)
|
||||
}
|
||||
#[doc = "Bits 14:15 - Core0 access rtc permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_rtc(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_W<CORE_0_PIF_PMS_CONSTRAIN_5_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_W::new(self, 14)
|
||||
}
|
||||
#[doc = "Bits 16:17 - Core0 access io_mux permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_io_mux(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_W<CORE_0_PIF_PMS_CONSTRAIN_5_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_W::new(self, 16)
|
||||
}
|
||||
#[doc = "Bits 20:21 - Core0 access hinf permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_hinf(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF_W<CORE_0_PIF_PMS_CONSTRAIN_5_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF_W::new(self, 20)
|
||||
}
|
||||
#[doc = "Bits 24:25 - Core0 access misc permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_misc(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_W<CORE_0_PIF_PMS_CONSTRAIN_5_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_W::new(self, 24)
|
||||
}
|
||||
#[doc = "Bits 26:27 - Core0 access i2c permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_i2c(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_W<CORE_0_PIF_PMS_CONSTRAIN_5_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_W::new(self, 26)
|
||||
}
|
||||
#[doc = "Bits 28:29 - Core0 access i2s0 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_i2s0(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_W<CORE_0_PIF_PMS_CONSTRAIN_5_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_W::new(self, 28)
|
||||
}
|
||||
#[doc = "Bits 30:31 - Core0 access uart1 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_uart1(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_W<CORE_0_PIF_PMS_CONSTRAIN_5_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_W::new(self, 30)
|
||||
}
|
||||
}
|
||||
#[doc = "Core0 access peripherals permission configuration register 5.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_pif_pms_constrain_5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_pif_pms_constrain_5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_0_PIF_PMS_CONSTRAIN_5_SPEC;
|
||||
impl crate::RegisterSpec for CORE_0_PIF_PMS_CONSTRAIN_5_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_0_pif_pms_constrain_5::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_0_PIF_PMS_CONSTRAIN_5_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_0_pif_pms_constrain_5::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_0_PIF_PMS_CONSTRAIN_5_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_0_PIF_PMS_CONSTRAIN_5 to value 0xff33_cfff"]
|
||||
impl crate::Resettable for CORE_0_PIF_PMS_CONSTRAIN_5_SPEC {
|
||||
const RESET_VALUE: u32 = 0xff33_cfff;
|
||||
}
|
||||
@@ -0,0 +1,326 @@
|
||||
#[doc = "Register `CORE_0_PIF_PMS_CONSTRAIN_6` reader"]
|
||||
pub type R = crate::R<CORE_0_PIF_PMS_CONSTRAIN_6_SPEC>;
|
||||
#[doc = "Register `CORE_0_PIF_PMS_CONSTRAIN_6` writer"]
|
||||
pub type W = crate::W<CORE_0_PIF_PMS_CONSTRAIN_6_SPEC>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT` reader - Core0 access bt permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT` writer - Core0 access bt permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0` reader - Core0 access i2c_ext0 permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0` writer - Core0 access i2c_ext0 permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0` reader - Core0 access uhci0 permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0` writer - Core0 access uhci0 permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST` reader - Core0 access slchost permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST` writer - Core0 access slchost permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT` reader - Core0 access rmt permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT` writer - Core0 access rmt permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT` reader - Core0 access pcnt permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT` writer - Core0 access pcnt permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC` reader - Core0 access slc permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC` writer - Core0 access slc permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC` reader - Core0 access ledc permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC` writer - Core0 access ledc permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP` reader - Core0 access backup permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP` writer - Core0 access backup permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB` reader - Core0 access bb permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB` writer - Core0 access bb permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0` reader - Core0 access pwm0 permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0` writer - Core0 access pwm0 permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP` reader - Core0 access timergroup permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP` writer - Core0 access timergroup permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1` reader - Core0 access timergroup1 permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1` writer - Core0 access timergroup1 permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER` reader - Core0 access systimer permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER` writer - Core0 access systimer permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:1 - Core0 access bt permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_bt(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_R::new((self.bits & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 4:5 - Core0 access i2c_ext0 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_i2c_ext0(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_R::new(((self.bits >> 4) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 6:7 - Core0 access uhci0 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_uhci0(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_R::new(((self.bits >> 6) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 8:9 - Core0 access slchost permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_slchost(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_R::new(((self.bits >> 8) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 10:11 - Core0 access rmt permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_rmt(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_R::new(((self.bits >> 10) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 12:13 - Core0 access pcnt permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_pcnt(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_R::new(((self.bits >> 12) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 14:15 - Core0 access slc permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_slc(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC_R::new(((self.bits >> 14) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 16:17 - Core0 access ledc permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_ledc(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_R::new(((self.bits >> 16) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 18:19 - Core0 access backup permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_backup(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_R::new(((self.bits >> 18) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 22:23 - Core0 access bb permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_bb(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_R::new(((self.bits >> 22) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 24:25 - Core0 access pwm0 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_pwm0(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_R::new(((self.bits >> 24) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 26:27 - Core0 access timergroup permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_timergroup(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_R::new(((self.bits >> 26) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 28:29 - Core0 access timergroup1 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_timergroup1(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_R::new(((self.bits >> 28) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 30:31 - Core0 access systimer permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_systimer(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_R::new(((self.bits >> 30) & 3) as u8)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_0_PIF_PMS_CONSTRAIN_6")
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_1_bt",
|
||||
&self.core_0_pif_pms_constrain_world_1_bt(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_1_i2c_ext0",
|
||||
&self.core_0_pif_pms_constrain_world_1_i2c_ext0(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_1_uhci0",
|
||||
&self.core_0_pif_pms_constrain_world_1_uhci0(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_1_slchost",
|
||||
&self.core_0_pif_pms_constrain_world_1_slchost(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_1_rmt",
|
||||
&self.core_0_pif_pms_constrain_world_1_rmt(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_1_pcnt",
|
||||
&self.core_0_pif_pms_constrain_world_1_pcnt(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_1_slc",
|
||||
&self.core_0_pif_pms_constrain_world_1_slc(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_1_ledc",
|
||||
&self.core_0_pif_pms_constrain_world_1_ledc(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_1_backup",
|
||||
&self.core_0_pif_pms_constrain_world_1_backup(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_1_bb",
|
||||
&self.core_0_pif_pms_constrain_world_1_bb(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_1_pwm0",
|
||||
&self.core_0_pif_pms_constrain_world_1_pwm0(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_1_timergroup",
|
||||
&self.core_0_pif_pms_constrain_world_1_timergroup(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_1_timergroup1",
|
||||
&self.core_0_pif_pms_constrain_world_1_timergroup1(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_1_systimer",
|
||||
&self.core_0_pif_pms_constrain_world_1_systimer(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:1 - Core0 access bt permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_bt(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_W<CORE_0_PIF_PMS_CONSTRAIN_6_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_W::new(self, 0)
|
||||
}
|
||||
#[doc = "Bits 4:5 - Core0 access i2c_ext0 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_i2c_ext0(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_W<CORE_0_PIF_PMS_CONSTRAIN_6_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_W::new(self, 4)
|
||||
}
|
||||
#[doc = "Bits 6:7 - Core0 access uhci0 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_uhci0(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_W<CORE_0_PIF_PMS_CONSTRAIN_6_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_W::new(self, 6)
|
||||
}
|
||||
#[doc = "Bits 8:9 - Core0 access slchost permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_slchost(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_W<CORE_0_PIF_PMS_CONSTRAIN_6_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_W::new(self, 8)
|
||||
}
|
||||
#[doc = "Bits 10:11 - Core0 access rmt permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_rmt(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_W<CORE_0_PIF_PMS_CONSTRAIN_6_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_W::new(self, 10)
|
||||
}
|
||||
#[doc = "Bits 12:13 - Core0 access pcnt permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_pcnt(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_W<CORE_0_PIF_PMS_CONSTRAIN_6_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_W::new(self, 12)
|
||||
}
|
||||
#[doc = "Bits 14:15 - Core0 access slc permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_slc(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC_W<CORE_0_PIF_PMS_CONSTRAIN_6_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC_W::new(self, 14)
|
||||
}
|
||||
#[doc = "Bits 16:17 - Core0 access ledc permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_ledc(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_W<CORE_0_PIF_PMS_CONSTRAIN_6_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_W::new(self, 16)
|
||||
}
|
||||
#[doc = "Bits 18:19 - Core0 access backup permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_backup(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_W<CORE_0_PIF_PMS_CONSTRAIN_6_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_W::new(self, 18)
|
||||
}
|
||||
#[doc = "Bits 22:23 - Core0 access bb permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_bb(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_W<CORE_0_PIF_PMS_CONSTRAIN_6_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_W::new(self, 22)
|
||||
}
|
||||
#[doc = "Bits 24:25 - Core0 access pwm0 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_pwm0(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_W<CORE_0_PIF_PMS_CONSTRAIN_6_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_W::new(self, 24)
|
||||
}
|
||||
#[doc = "Bits 26:27 - Core0 access timergroup permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_timergroup(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_W<CORE_0_PIF_PMS_CONSTRAIN_6_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_W::new(self, 26)
|
||||
}
|
||||
#[doc = "Bits 28:29 - Core0 access timergroup1 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_timergroup1(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_W<CORE_0_PIF_PMS_CONSTRAIN_6_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_W::new(self, 28)
|
||||
}
|
||||
#[doc = "Bits 30:31 - Core0 access systimer permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_systimer(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_W<CORE_0_PIF_PMS_CONSTRAIN_6_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_W::new(self, 30)
|
||||
}
|
||||
}
|
||||
#[doc = "Core0 access peripherals permission configuration register 6.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_pif_pms_constrain_6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_pif_pms_constrain_6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_0_PIF_PMS_CONSTRAIN_6_SPEC;
|
||||
impl crate::RegisterSpec for CORE_0_PIF_PMS_CONSTRAIN_6_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_0_pif_pms_constrain_6::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_0_PIF_PMS_CONSTRAIN_6_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_0_pif_pms_constrain_6::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_0_PIF_PMS_CONSTRAIN_6_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_0_PIF_PMS_CONSTRAIN_6 to value 0xffcf_fff3"]
|
||||
impl crate::Resettable for CORE_0_PIF_PMS_CONSTRAIN_6_SPEC {
|
||||
const RESET_VALUE: u32 = 0xffcf_fff3;
|
||||
}
|
||||
@@ -0,0 +1,286 @@
|
||||
#[doc = "Register `CORE_0_PIF_PMS_CONSTRAIN_7` reader"]
|
||||
pub type R = crate::R<CORE_0_PIF_PMS_CONSTRAIN_7_SPEC>;
|
||||
#[doc = "Register `CORE_0_PIF_PMS_CONSTRAIN_7` writer"]
|
||||
pub type W = crate::W<CORE_0_PIF_PMS_CONSTRAIN_7_SPEC>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2` reader - Core0 access spi_2 permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2` writer - Core0 access spi_2 permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3` reader - Core0 access spi_3 permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3` writer - Core0 access spi_3 permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL` reader - Core0 access apb_ctrl permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL` writer - Core0 access apb_ctrl permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1` reader - Core0 access i2c_ext1 permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1` writer - Core0 access i2c_ext1 permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST` reader - Core0 access sdio_host permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST` writer - Core0 access sdio_host permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN` reader - Core0 access can permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN` writer - Core0 access can permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1` reader - Core0 access pwm1 permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1` writer - Core0 access pwm1 permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1` reader - Core0 access i2s1 permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1` writer - Core0 access i2s1 permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2` reader - Core0 access uart2 permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2` writer - Core0 access uart2 permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT` reader - Core0 access rwbt permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT` writer - Core0 access rwbt permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC` reader - Core0 access wifimac permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC` writer - Core0 access wifimac permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR` reader - Core0 access pwr permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR` writer - Core0 access pwr permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:1 - Core0 access spi_2 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_spi_2(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_R::new((self.bits & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 2:3 - Core0 access spi_3 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_spi_3(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_R::new(((self.bits >> 2) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 4:5 - Core0 access apb_ctrl permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_apb_ctrl(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_R::new(((self.bits >> 4) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 6:7 - Core0 access i2c_ext1 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_i2c_ext1(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_R::new(((self.bits >> 6) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 8:9 - Core0 access sdio_host permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_sdio_host(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_R::new(((self.bits >> 8) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 10:11 - Core0 access can permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_can(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_R::new(((self.bits >> 10) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 12:13 - Core0 access pwm1 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_pwm1(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_R::new(((self.bits >> 12) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 14:15 - Core0 access i2s1 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_i2s1(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_R::new(((self.bits >> 14) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 16:17 - Core0 access uart2 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_uart2(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2_R::new(((self.bits >> 16) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 22:23 - Core0 access rwbt permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_rwbt(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_R::new(((self.bits >> 22) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 26:27 - Core0 access wifimac permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_wifimac(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_R::new(((self.bits >> 26) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 28:29 - Core0 access pwr permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_pwr(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_R::new(((self.bits >> 28) & 3) as u8)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_0_PIF_PMS_CONSTRAIN_7")
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_1_spi_2",
|
||||
&self.core_0_pif_pms_constrain_world_1_spi_2(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_1_spi_3",
|
||||
&self.core_0_pif_pms_constrain_world_1_spi_3(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_1_apb_ctrl",
|
||||
&self.core_0_pif_pms_constrain_world_1_apb_ctrl(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_1_i2c_ext1",
|
||||
&self.core_0_pif_pms_constrain_world_1_i2c_ext1(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_1_sdio_host",
|
||||
&self.core_0_pif_pms_constrain_world_1_sdio_host(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_1_can",
|
||||
&self.core_0_pif_pms_constrain_world_1_can(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_1_pwm1",
|
||||
&self.core_0_pif_pms_constrain_world_1_pwm1(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_1_i2s1",
|
||||
&self.core_0_pif_pms_constrain_world_1_i2s1(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_1_uart2",
|
||||
&self.core_0_pif_pms_constrain_world_1_uart2(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_1_rwbt",
|
||||
&self.core_0_pif_pms_constrain_world_1_rwbt(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_1_wifimac",
|
||||
&self.core_0_pif_pms_constrain_world_1_wifimac(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_1_pwr",
|
||||
&self.core_0_pif_pms_constrain_world_1_pwr(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:1 - Core0 access spi_2 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_spi_2(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_W<CORE_0_PIF_PMS_CONSTRAIN_7_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_W::new(self, 0)
|
||||
}
|
||||
#[doc = "Bits 2:3 - Core0 access spi_3 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_spi_3(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_W<CORE_0_PIF_PMS_CONSTRAIN_7_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_W::new(self, 2)
|
||||
}
|
||||
#[doc = "Bits 4:5 - Core0 access apb_ctrl permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_apb_ctrl(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_W<CORE_0_PIF_PMS_CONSTRAIN_7_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_W::new(self, 4)
|
||||
}
|
||||
#[doc = "Bits 6:7 - Core0 access i2c_ext1 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_i2c_ext1(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_W<CORE_0_PIF_PMS_CONSTRAIN_7_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_W::new(self, 6)
|
||||
}
|
||||
#[doc = "Bits 8:9 - Core0 access sdio_host permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_sdio_host(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_W<CORE_0_PIF_PMS_CONSTRAIN_7_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_W::new(self, 8)
|
||||
}
|
||||
#[doc = "Bits 10:11 - Core0 access can permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_can(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_W<CORE_0_PIF_PMS_CONSTRAIN_7_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_W::new(self, 10)
|
||||
}
|
||||
#[doc = "Bits 12:13 - Core0 access pwm1 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_pwm1(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_W<CORE_0_PIF_PMS_CONSTRAIN_7_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_W::new(self, 12)
|
||||
}
|
||||
#[doc = "Bits 14:15 - Core0 access i2s1 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_i2s1(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_W<CORE_0_PIF_PMS_CONSTRAIN_7_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_W::new(self, 14)
|
||||
}
|
||||
#[doc = "Bits 16:17 - Core0 access uart2 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_uart2(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2_W<CORE_0_PIF_PMS_CONSTRAIN_7_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2_W::new(self, 16)
|
||||
}
|
||||
#[doc = "Bits 22:23 - Core0 access rwbt permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_rwbt(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_W<CORE_0_PIF_PMS_CONSTRAIN_7_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_W::new(self, 22)
|
||||
}
|
||||
#[doc = "Bits 26:27 - Core0 access wifimac permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_wifimac(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_W<CORE_0_PIF_PMS_CONSTRAIN_7_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_W::new(self, 26)
|
||||
}
|
||||
#[doc = "Bits 28:29 - Core0 access pwr permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_pwr(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_W<CORE_0_PIF_PMS_CONSTRAIN_7_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_W::new(self, 28)
|
||||
}
|
||||
}
|
||||
#[doc = "Core0 access peripherals permission configuration register 7.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_pif_pms_constrain_7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_pif_pms_constrain_7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_0_PIF_PMS_CONSTRAIN_7_SPEC;
|
||||
impl crate::RegisterSpec for CORE_0_PIF_PMS_CONSTRAIN_7_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_0_pif_pms_constrain_7::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_0_PIF_PMS_CONSTRAIN_7_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_0_pif_pms_constrain_7::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_0_PIF_PMS_CONSTRAIN_7_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_0_PIF_PMS_CONSTRAIN_7 to value 0x3cc3_ffff"]
|
||||
impl crate::Resettable for CORE_0_PIF_PMS_CONSTRAIN_7_SPEC {
|
||||
const RESET_VALUE: u32 = 0x3cc3_ffff;
|
||||
}
|
||||
@@ -0,0 +1,379 @@
|
||||
#[doc = "Register `CORE_0_PIF_PMS_CONSTRAIN_8` reader"]
|
||||
pub type R = crate::R<CORE_0_PIF_PMS_CONSTRAIN_8_SPEC>;
|
||||
#[doc = "Register `CORE_0_PIF_PMS_CONSTRAIN_8` writer"]
|
||||
pub type W = crate::W<CORE_0_PIF_PMS_CONSTRAIN_8_SPEC>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE` reader - Core0 access usb_device permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE` writer - Core0 access usb_device permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP` reader - Core0 access usb_wrap permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP` writer - Core0 access usb_wrap permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI` reader - Core0 access crypto_peri permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI` writer - Core0 access crypto_peri permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA` reader - Core0 access crypto_dma permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA` writer - Core0 access crypto_dma permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC` reader - Core0 access apb_adc permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC` writer - Core0 access apb_adc permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM` reader - Core0 access lcd_cam permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM` writer - Core0 access lcd_cam permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR` reader - Core0 access bt_pwr permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR` writer - Core0 access bt_pwr permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB` reader - Core0 access usb permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB` writer - Core0 access usb permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM` reader - Core0 access system permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM` writer - Core0 access system permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE` reader - Core0 access sensitive permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE` writer - Core0 access sensitive permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT` reader - Core0 access interrupt permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT` writer - Core0 access interrupt permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY` reader - Core0 access dma_copy permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY` writer - Core0 access dma_copy permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG` reader - Core0 access cache_config permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG` writer - Core0 access cache_config permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD` reader - Core0 access ad permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD` writer - Core0 access ad permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO` reader - Core0 access dio permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO` writer - Core0 access dio permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER` reader - Core0 access world_controller permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER` writer - Core0 access world_controller permission in world1."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_W<'a, REG> =
|
||||
crate::FieldWriter<'a, REG, 2>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:1 - Core0 access usb_device permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_usb_device(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_R::new((self.bits & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 2:3 - Core0 access usb_wrap permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_usb_wrap(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_R::new(((self.bits >> 2) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 4:5 - Core0 access crypto_peri permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_crypto_peri(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_R::new(((self.bits >> 4) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 6:7 - Core0 access crypto_dma permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_crypto_dma(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_R::new(((self.bits >> 6) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 8:9 - Core0 access apb_adc permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_apb_adc(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_R::new(((self.bits >> 8) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 10:11 - Core0 access lcd_cam permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_lcd_cam(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_R::new(((self.bits >> 10) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 12:13 - Core0 access bt_pwr permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_bt_pwr(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_R::new(((self.bits >> 12) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 14:15 - Core0 access usb permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_usb(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_R::new(((self.bits >> 14) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 16:17 - Core0 access system permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_system(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_R::new(((self.bits >> 16) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 18:19 - Core0 access sensitive permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_sensitive(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_R::new(((self.bits >> 18) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 20:21 - Core0 access interrupt permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_interrupt(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_R::new(((self.bits >> 20) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 22:23 - Core0 access dma_copy permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_dma_copy(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_R::new(((self.bits >> 22) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 24:25 - Core0 access cache_config permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_cache_config(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_R::new(((self.bits >> 24) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 26:27 - Core0 access ad permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_ad(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_R::new(((self.bits >> 26) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 28:29 - Core0 access dio permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_dio(&self) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_R::new(((self.bits >> 28) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 30:31 - Core0 access world_controller permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_world_controller(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_R::new(((self.bits >> 30) & 3) as u8)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_0_PIF_PMS_CONSTRAIN_8")
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_1_usb_device",
|
||||
&self.core_0_pif_pms_constrain_world_1_usb_device(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_1_usb_wrap",
|
||||
&self.core_0_pif_pms_constrain_world_1_usb_wrap(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_1_crypto_peri",
|
||||
&self.core_0_pif_pms_constrain_world_1_crypto_peri(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_1_crypto_dma",
|
||||
&self.core_0_pif_pms_constrain_world_1_crypto_dma(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_1_apb_adc",
|
||||
&self.core_0_pif_pms_constrain_world_1_apb_adc(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_1_lcd_cam",
|
||||
&self.core_0_pif_pms_constrain_world_1_lcd_cam(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_1_bt_pwr",
|
||||
&self.core_0_pif_pms_constrain_world_1_bt_pwr(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_1_usb",
|
||||
&self.core_0_pif_pms_constrain_world_1_usb(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_1_system",
|
||||
&self.core_0_pif_pms_constrain_world_1_system(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_1_sensitive",
|
||||
&self.core_0_pif_pms_constrain_world_1_sensitive(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_1_interrupt",
|
||||
&self.core_0_pif_pms_constrain_world_1_interrupt(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_1_dma_copy",
|
||||
&self.core_0_pif_pms_constrain_world_1_dma_copy(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_1_cache_config",
|
||||
&self.core_0_pif_pms_constrain_world_1_cache_config(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_1_ad",
|
||||
&self.core_0_pif_pms_constrain_world_1_ad(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_1_dio",
|
||||
&self.core_0_pif_pms_constrain_world_1_dio(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_world_1_world_controller",
|
||||
&self.core_0_pif_pms_constrain_world_1_world_controller(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:1 - Core0 access usb_device permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_usb_device(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_W<CORE_0_PIF_PMS_CONSTRAIN_8_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_W::new(self, 0)
|
||||
}
|
||||
#[doc = "Bits 2:3 - Core0 access usb_wrap permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_usb_wrap(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_W<CORE_0_PIF_PMS_CONSTRAIN_8_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_W::new(self, 2)
|
||||
}
|
||||
#[doc = "Bits 4:5 - Core0 access crypto_peri permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_crypto_peri(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_W<CORE_0_PIF_PMS_CONSTRAIN_8_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_W::new(self, 4)
|
||||
}
|
||||
#[doc = "Bits 6:7 - Core0 access crypto_dma permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_crypto_dma(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_W<CORE_0_PIF_PMS_CONSTRAIN_8_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_W::new(self, 6)
|
||||
}
|
||||
#[doc = "Bits 8:9 - Core0 access apb_adc permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_apb_adc(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_W<CORE_0_PIF_PMS_CONSTRAIN_8_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_W::new(self, 8)
|
||||
}
|
||||
#[doc = "Bits 10:11 - Core0 access lcd_cam permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_lcd_cam(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_W<CORE_0_PIF_PMS_CONSTRAIN_8_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_W::new(self, 10)
|
||||
}
|
||||
#[doc = "Bits 12:13 - Core0 access bt_pwr permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_bt_pwr(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_W<CORE_0_PIF_PMS_CONSTRAIN_8_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_W::new(self, 12)
|
||||
}
|
||||
#[doc = "Bits 14:15 - Core0 access usb permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_usb(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_W<CORE_0_PIF_PMS_CONSTRAIN_8_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_W::new(self, 14)
|
||||
}
|
||||
#[doc = "Bits 16:17 - Core0 access system permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_system(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_W<CORE_0_PIF_PMS_CONSTRAIN_8_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_W::new(self, 16)
|
||||
}
|
||||
#[doc = "Bits 18:19 - Core0 access sensitive permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_sensitive(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_W<CORE_0_PIF_PMS_CONSTRAIN_8_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_W::new(self, 18)
|
||||
}
|
||||
#[doc = "Bits 20:21 - Core0 access interrupt permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_interrupt(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_W<CORE_0_PIF_PMS_CONSTRAIN_8_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_W::new(self, 20)
|
||||
}
|
||||
#[doc = "Bits 22:23 - Core0 access dma_copy permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_dma_copy(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_W<CORE_0_PIF_PMS_CONSTRAIN_8_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_W::new(self, 22)
|
||||
}
|
||||
#[doc = "Bits 24:25 - Core0 access cache_config permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_cache_config(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_W<CORE_0_PIF_PMS_CONSTRAIN_8_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_W::new(self, 24)
|
||||
}
|
||||
#[doc = "Bits 26:27 - Core0 access ad permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_ad(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_W<CORE_0_PIF_PMS_CONSTRAIN_8_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_W::new(self, 26)
|
||||
}
|
||||
#[doc = "Bits 28:29 - Core0 access dio permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_dio(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_W<CORE_0_PIF_PMS_CONSTRAIN_8_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_W::new(self, 28)
|
||||
}
|
||||
#[doc = "Bits 30:31 - Core0 access world_controller permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_world_1_world_controller(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_W<CORE_0_PIF_PMS_CONSTRAIN_8_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_W::new(self, 30)
|
||||
}
|
||||
}
|
||||
#[doc = "Core0 access peripherals permission configuration register 8.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_pif_pms_constrain_8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_pif_pms_constrain_8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_0_PIF_PMS_CONSTRAIN_8_SPEC;
|
||||
impl crate::RegisterSpec for CORE_0_PIF_PMS_CONSTRAIN_8_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_0_pif_pms_constrain_8::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_0_PIF_PMS_CONSTRAIN_8_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_0_pif_pms_constrain_8::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_0_PIF_PMS_CONSTRAIN_8_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_0_PIF_PMS_CONSTRAIN_8 to value 0xffff_ffff"]
|
||||
impl crate::Resettable for CORE_0_PIF_PMS_CONSTRAIN_8_SPEC {
|
||||
const RESET_VALUE: u32 = 0xffff_ffff;
|
||||
}
|
||||
@@ -0,0 +1,80 @@
|
||||
#[doc = "Register `CORE_0_PIF_PMS_CONSTRAIN_9` reader"]
|
||||
pub type R = crate::R<CORE_0_PIF_PMS_CONSTRAIN_9_SPEC>;
|
||||
#[doc = "Register `CORE_0_PIF_PMS_CONSTRAIN_9` writer"]
|
||||
pub type W = crate::W<CORE_0_PIF_PMS_CONSTRAIN_9_SPEC>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0` reader - RTCFast memory split address in world 0 for core0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_R = crate::FieldReader<u16>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0` writer - RTCFast memory split address in world 0 for core0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_W<'a, REG> =
|
||||
crate::FieldWriter<'a, REG, 11, u16>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1` reader - RTCFast memory split address in world 1 for core0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_R = crate::FieldReader<u16>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1` writer - RTCFast memory split address in world 1 for core0."]
|
||||
pub type CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_W<'a, REG> =
|
||||
crate::FieldWriter<'a, REG, 11, u16>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:10 - RTCFast memory split address in world 0 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_rtcfast_spltaddr_world_0(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_R::new((self.bits & 0x07ff) as u16)
|
||||
}
|
||||
#[doc = "Bits 11:21 - RTCFast memory split address in world 1 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_rtcfast_spltaddr_world_1(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_R {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_R::new(
|
||||
((self.bits >> 11) & 0x07ff) as u16,
|
||||
)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_0_PIF_PMS_CONSTRAIN_9")
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_rtcfast_spltaddr_world_0",
|
||||
&self.core_0_pif_pms_constrain_rtcfast_spltaddr_world_0(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_constrain_rtcfast_spltaddr_world_1",
|
||||
&self.core_0_pif_pms_constrain_rtcfast_spltaddr_world_1(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:10 - RTCFast memory split address in world 0 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_rtcfast_spltaddr_world_0(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_W<CORE_0_PIF_PMS_CONSTRAIN_9_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_W::new(self, 0)
|
||||
}
|
||||
#[doc = "Bits 11:21 - RTCFast memory split address in world 1 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_constrain_rtcfast_spltaddr_world_1(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_W<CORE_0_PIF_PMS_CONSTRAIN_9_SPEC> {
|
||||
CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_W::new(self, 11)
|
||||
}
|
||||
}
|
||||
#[doc = "Core0 access peripherals permission configuration register 9.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_pif_pms_constrain_9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_pif_pms_constrain_9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_0_PIF_PMS_CONSTRAIN_9_SPEC;
|
||||
impl crate::RegisterSpec for CORE_0_PIF_PMS_CONSTRAIN_9_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_0_pif_pms_constrain_9::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_0_PIF_PMS_CONSTRAIN_9_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_0_pif_pms_constrain_9::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_0_PIF_PMS_CONSTRAIN_9_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_0_PIF_PMS_CONSTRAIN_9 to value 0x003f_ffff"]
|
||||
impl crate::Resettable for CORE_0_PIF_PMS_CONSTRAIN_9_SPEC {
|
||||
const RESET_VALUE: u32 = 0x003f_ffff;
|
||||
}
|
||||
@@ -0,0 +1,52 @@
|
||||
#[doc = "Register `CORE_0_PIF_PMS_MONITOR_0` reader"]
|
||||
pub type R = crate::R<CORE_0_PIF_PMS_MONITOR_0_SPEC>;
|
||||
#[doc = "Register `CORE_0_PIF_PMS_MONITOR_0` writer"]
|
||||
pub type W = crate::W<CORE_0_PIF_PMS_MONITOR_0_SPEC>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_MONITOR_LOCK` reader - Set 1 to lock core0 permission report registers."]
|
||||
pub type CORE_0_PIF_PMS_MONITOR_LOCK_R = crate::BitReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_MONITOR_LOCK` writer - Set 1 to lock core0 permission report registers."]
|
||||
pub type CORE_0_PIF_PMS_MONITOR_LOCK_W<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
impl R {
|
||||
#[doc = "Bit 0 - Set 1 to lock core0 permission report registers."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_monitor_lock(&self) -> CORE_0_PIF_PMS_MONITOR_LOCK_R {
|
||||
CORE_0_PIF_PMS_MONITOR_LOCK_R::new((self.bits & 1) != 0)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_0_PIF_PMS_MONITOR_0")
|
||||
.field(
|
||||
"core_0_pif_pms_monitor_lock",
|
||||
&self.core_0_pif_pms_monitor_lock(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bit 0 - Set 1 to lock core0 permission report registers."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_monitor_lock(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_MONITOR_LOCK_W<CORE_0_PIF_PMS_MONITOR_0_SPEC> {
|
||||
CORE_0_PIF_PMS_MONITOR_LOCK_W::new(self, 0)
|
||||
}
|
||||
}
|
||||
#[doc = "Core0 permission report register 0.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_pif_pms_monitor_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_pif_pms_monitor_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_0_PIF_PMS_MONITOR_0_SPEC;
|
||||
impl crate::RegisterSpec for CORE_0_PIF_PMS_MONITOR_0_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_0_pif_pms_monitor_0::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_0_PIF_PMS_MONITOR_0_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_0_pif_pms_monitor_0::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_0_PIF_PMS_MONITOR_0_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_0_PIF_PMS_MONITOR_0 to value 0"]
|
||||
impl crate::Resettable for CORE_0_PIF_PMS_MONITOR_0_SPEC {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
@@ -0,0 +1,72 @@
|
||||
#[doc = "Register `CORE_0_PIF_PMS_MONITOR_1` reader"]
|
||||
pub type R = crate::R<CORE_0_PIF_PMS_MONITOR_1_SPEC>;
|
||||
#[doc = "Register `CORE_0_PIF_PMS_MONITOR_1` writer"]
|
||||
pub type W = crate::W<CORE_0_PIF_PMS_MONITOR_1_SPEC>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR` reader - Set 1 to clear interrupt that core0 initiate illegal PIF bus access."]
|
||||
pub type CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_R = crate::BitReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR` writer - Set 1 to clear interrupt that core0 initiate illegal PIF bus access."]
|
||||
pub type CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_MONITOR_VIOLATE_EN` reader - Set 1 to enable interrupt that core0 initiate illegal PIF bus access."]
|
||||
pub type CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_R = crate::BitReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_MONITOR_VIOLATE_EN` writer - Set 1 to enable interrupt that core0 initiate illegal PIF bus access."]
|
||||
pub type CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
impl R {
|
||||
#[doc = "Bit 0 - Set 1 to clear interrupt that core0 initiate illegal PIF bus access."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_monitor_violate_clr(&self) -> CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_R {
|
||||
CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_R::new((self.bits & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 1 - Set 1 to enable interrupt that core0 initiate illegal PIF bus access."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_monitor_violate_en(&self) -> CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_R {
|
||||
CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_R::new(((self.bits >> 1) & 1) != 0)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_0_PIF_PMS_MONITOR_1")
|
||||
.field(
|
||||
"core_0_pif_pms_monitor_violate_clr",
|
||||
&self.core_0_pif_pms_monitor_violate_clr(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_monitor_violate_en",
|
||||
&self.core_0_pif_pms_monitor_violate_en(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bit 0 - Set 1 to clear interrupt that core0 initiate illegal PIF bus access."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_monitor_violate_clr(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_W<CORE_0_PIF_PMS_MONITOR_1_SPEC> {
|
||||
CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_W::new(self, 0)
|
||||
}
|
||||
#[doc = "Bit 1 - Set 1 to enable interrupt that core0 initiate illegal PIF bus access."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_monitor_violate_en(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_W<CORE_0_PIF_PMS_MONITOR_1_SPEC> {
|
||||
CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_W::new(self, 1)
|
||||
}
|
||||
}
|
||||
#[doc = "Core0 permission report register 1.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_pif_pms_monitor_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_pif_pms_monitor_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_0_PIF_PMS_MONITOR_1_SPEC;
|
||||
impl crate::RegisterSpec for CORE_0_PIF_PMS_MONITOR_1_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_0_pif_pms_monitor_1::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_0_PIF_PMS_MONITOR_1_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_0_pif_pms_monitor_1::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_0_PIF_PMS_MONITOR_1_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_0_PIF_PMS_MONITOR_1 to value 0x03"]
|
||||
impl crate::Resettable for CORE_0_PIF_PMS_MONITOR_1_SPEC {
|
||||
const RESET_VALUE: u32 = 0x03;
|
||||
}
|
||||
@@ -0,0 +1,85 @@
|
||||
#[doc = "Register `CORE_0_PIF_PMS_MONITOR_2` reader"]
|
||||
pub type R = crate::R<CORE_0_PIF_PMS_MONITOR_2_SPEC>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR` reader - Record core0 illegal access interrupt state."]
|
||||
pub type CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_R = crate::BitReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0` reader - Record hport information when core0 initiate illegal access."]
|
||||
pub type CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_R = crate::BitReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE` reader - Record access type when core0 initate illegal access."]
|
||||
pub type CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE` reader - Record access direction when core0 initiate illegal access."]
|
||||
pub type CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_R = crate::BitReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD` reader - Record world information when core0 initiate illegal access."]
|
||||
pub type CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_R = crate::FieldReader;
|
||||
impl R {
|
||||
#[doc = "Bit 0 - Record core0 illegal access interrupt state."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_monitor_violate_intr(&self) -> CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_R {
|
||||
CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_R::new((self.bits & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 1 - Record hport information when core0 initiate illegal access."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_monitor_violate_status_hport_0(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_R {
|
||||
CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_R::new(((self.bits >> 1) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bits 2:4 - Record access type when core0 initate illegal access."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_monitor_violate_status_hsize(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_R {
|
||||
CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_R::new(((self.bits >> 2) & 7) as u8)
|
||||
}
|
||||
#[doc = "Bit 5 - Record access direction when core0 initiate illegal access."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_monitor_violate_status_hwrite(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_R {
|
||||
CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_R::new(((self.bits >> 5) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bits 6:7 - Record world information when core0 initiate illegal access."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_monitor_violate_status_hworld(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_R {
|
||||
CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_R::new(((self.bits >> 6) & 3) as u8)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_0_PIF_PMS_MONITOR_2")
|
||||
.field(
|
||||
"core_0_pif_pms_monitor_violate_intr",
|
||||
&self.core_0_pif_pms_monitor_violate_intr(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_monitor_violate_status_hport_0",
|
||||
&self.core_0_pif_pms_monitor_violate_status_hport_0(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_monitor_violate_status_hsize",
|
||||
&self.core_0_pif_pms_monitor_violate_status_hsize(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_monitor_violate_status_hwrite",
|
||||
&self.core_0_pif_pms_monitor_violate_status_hwrite(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_monitor_violate_status_hworld",
|
||||
&self.core_0_pif_pms_monitor_violate_status_hworld(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
#[doc = "Core0 permission report register 2.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_pif_pms_monitor_2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_0_PIF_PMS_MONITOR_2_SPEC;
|
||||
impl crate::RegisterSpec for CORE_0_PIF_PMS_MONITOR_2_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_0_pif_pms_monitor_2::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_0_PIF_PMS_MONITOR_2_SPEC {}
|
||||
#[doc = "`reset()` method sets CORE_0_PIF_PMS_MONITOR_2 to value 0"]
|
||||
impl crate::Resettable for CORE_0_PIF_PMS_MONITOR_2_SPEC {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
@@ -0,0 +1,35 @@
|
||||
#[doc = "Register `CORE_0_PIF_PMS_MONITOR_3` reader"]
|
||||
pub type R = crate::R<CORE_0_PIF_PMS_MONITOR_3_SPEC>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR` reader - Record address information when core0 initiate illegal access."]
|
||||
pub type CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_R = crate::FieldReader<u32>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:31 - Record address information when core0 initiate illegal access."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_monitor_violate_status_haddr(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_R {
|
||||
CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_R::new(self.bits)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_0_PIF_PMS_MONITOR_3")
|
||||
.field(
|
||||
"core_0_pif_pms_monitor_violate_status_haddr",
|
||||
&self.core_0_pif_pms_monitor_violate_status_haddr(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
#[doc = "Core0 permission report register 3.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_pif_pms_monitor_3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_0_PIF_PMS_MONITOR_3_SPEC;
|
||||
impl crate::RegisterSpec for CORE_0_PIF_PMS_MONITOR_3_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_0_pif_pms_monitor_3::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_0_PIF_PMS_MONITOR_3_SPEC {}
|
||||
#[doc = "`reset()` method sets CORE_0_PIF_PMS_MONITOR_3 to value 0"]
|
||||
impl crate::Resettable for CORE_0_PIF_PMS_MONITOR_3_SPEC {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
@@ -0,0 +1,76 @@
|
||||
#[doc = "Register `CORE_0_PIF_PMS_MONITOR_4` reader"]
|
||||
pub type R = crate::R<CORE_0_PIF_PMS_MONITOR_4_SPEC>;
|
||||
#[doc = "Register `CORE_0_PIF_PMS_MONITOR_4` writer"]
|
||||
pub type W = crate::W<CORE_0_PIF_PMS_MONITOR_4_SPEC>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR` reader - Set 1 to clear interrupt that core0 initiate unsupported access type."]
|
||||
pub type CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_R = crate::BitReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR` writer - Set 1 to clear interrupt that core0 initiate unsupported access type."]
|
||||
pub type CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN` reader - Set 1 to enable interrupt that core0 initiate unsupported access type."]
|
||||
pub type CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_R = crate::BitReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN` writer - Set 1 to enable interrupt that core0 initiate unsupported access type."]
|
||||
pub type CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
impl R {
|
||||
#[doc = "Bit 0 - Set 1 to clear interrupt that core0 initiate unsupported access type."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_monitor_nonword_violate_clr(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_R {
|
||||
CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_R::new((self.bits & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 1 - Set 1 to enable interrupt that core0 initiate unsupported access type."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_monitor_nonword_violate_en(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_R {
|
||||
CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_R::new(((self.bits >> 1) & 1) != 0)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_0_PIF_PMS_MONITOR_4")
|
||||
.field(
|
||||
"core_0_pif_pms_monitor_nonword_violate_clr",
|
||||
&self.core_0_pif_pms_monitor_nonword_violate_clr(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_monitor_nonword_violate_en",
|
||||
&self.core_0_pif_pms_monitor_nonword_violate_en(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bit 0 - Set 1 to clear interrupt that core0 initiate unsupported access type."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_monitor_nonword_violate_clr(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_W<CORE_0_PIF_PMS_MONITOR_4_SPEC> {
|
||||
CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_W::new(self, 0)
|
||||
}
|
||||
#[doc = "Bit 1 - Set 1 to enable interrupt that core0 initiate unsupported access type."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_monitor_nonword_violate_en(
|
||||
&mut self,
|
||||
) -> CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_W<CORE_0_PIF_PMS_MONITOR_4_SPEC> {
|
||||
CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_W::new(self, 1)
|
||||
}
|
||||
}
|
||||
#[doc = "Core0 permission report register 4.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_pif_pms_monitor_4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_pif_pms_monitor_4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_0_PIF_PMS_MONITOR_4_SPEC;
|
||||
impl crate::RegisterSpec for CORE_0_PIF_PMS_MONITOR_4_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_0_pif_pms_monitor_4::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_0_PIF_PMS_MONITOR_4_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_0_pif_pms_monitor_4::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_0_PIF_PMS_MONITOR_4_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_0_PIF_PMS_MONITOR_4 to value 0x03"]
|
||||
impl crate::Resettable for CORE_0_PIF_PMS_MONITOR_4_SPEC {
|
||||
const RESET_VALUE: u32 = 0x03;
|
||||
}
|
||||
@@ -0,0 +1,61 @@
|
||||
#[doc = "Register `CORE_0_PIF_PMS_MONITOR_5` reader"]
|
||||
pub type R = crate::R<CORE_0_PIF_PMS_MONITOR_5_SPEC>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR` reader - Record core0 unsupported access type interrupt state."]
|
||||
pub type CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_R = crate::BitReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE` reader - Record access type when core0 initiate unsupported access type."]
|
||||
pub type CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD` reader - Record world information when core0 initiate unsupported access type."]
|
||||
pub type CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_R = crate::FieldReader;
|
||||
impl R {
|
||||
#[doc = "Bit 0 - Record core0 unsupported access type interrupt state."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_monitor_nonword_violate_intr(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_R {
|
||||
CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_R::new((self.bits & 1) != 0)
|
||||
}
|
||||
#[doc = "Bits 1:2 - Record access type when core0 initiate unsupported access type."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_monitor_nonword_violate_status_hsize(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_R {
|
||||
CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_R::new(((self.bits >> 1) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 3:4 - Record world information when core0 initiate unsupported access type."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_monitor_nonword_violate_status_hworld(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_R {
|
||||
CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_R::new(((self.bits >> 3) & 3) as u8)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_0_PIF_PMS_MONITOR_5")
|
||||
.field(
|
||||
"core_0_pif_pms_monitor_nonword_violate_intr",
|
||||
&self.core_0_pif_pms_monitor_nonword_violate_intr(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_monitor_nonword_violate_status_hsize",
|
||||
&self.core_0_pif_pms_monitor_nonword_violate_status_hsize(),
|
||||
)
|
||||
.field(
|
||||
"core_0_pif_pms_monitor_nonword_violate_status_hworld",
|
||||
&self.core_0_pif_pms_monitor_nonword_violate_status_hworld(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
#[doc = "Core0 permission report register 5.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_pif_pms_monitor_5::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_0_PIF_PMS_MONITOR_5_SPEC;
|
||||
impl crate::RegisterSpec for CORE_0_PIF_PMS_MONITOR_5_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_0_pif_pms_monitor_5::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_0_PIF_PMS_MONITOR_5_SPEC {}
|
||||
#[doc = "`reset()` method sets CORE_0_PIF_PMS_MONITOR_5 to value 0"]
|
||||
impl crate::Resettable for CORE_0_PIF_PMS_MONITOR_5_SPEC {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
@@ -0,0 +1,35 @@
|
||||
#[doc = "Register `CORE_0_PIF_PMS_MONITOR_6` reader"]
|
||||
pub type R = crate::R<CORE_0_PIF_PMS_MONITOR_6_SPEC>;
|
||||
#[doc = "Field `CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR` reader - Record address information when core0 initiate unsupported access type."]
|
||||
pub type CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_R = crate::FieldReader<u32>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:31 - Record address information when core0 initiate unsupported access type."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_pif_pms_monitor_nonword_violate_status_haddr(
|
||||
&self,
|
||||
) -> CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_R {
|
||||
CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_R::new(self.bits)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_0_PIF_PMS_MONITOR_6")
|
||||
.field(
|
||||
"core_0_pif_pms_monitor_nonword_violate_status_haddr",
|
||||
&self.core_0_pif_pms_monitor_nonword_violate_status_haddr(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
#[doc = "Core0 permission report register 6.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_pif_pms_monitor_6::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_0_PIF_PMS_MONITOR_6_SPEC;
|
||||
impl crate::RegisterSpec for CORE_0_PIF_PMS_MONITOR_6_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_0_pif_pms_monitor_6::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_0_PIF_PMS_MONITOR_6_SPEC {}
|
||||
#[doc = "`reset()` method sets CORE_0_PIF_PMS_MONITOR_6 to value 0"]
|
||||
impl crate::Resettable for CORE_0_PIF_PMS_MONITOR_6_SPEC {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
@@ -0,0 +1,52 @@
|
||||
#[doc = "Register `CORE_0_REGION_PMS_CONSTRAIN_0` reader"]
|
||||
pub type R = crate::R<CORE_0_REGION_PMS_CONSTRAIN_0_SPEC>;
|
||||
#[doc = "Register `CORE_0_REGION_PMS_CONSTRAIN_0` writer"]
|
||||
pub type W = crate::W<CORE_0_REGION_PMS_CONSTRAIN_0_SPEC>;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_LOCK` reader - Set 1 to lock core0 region permission registers."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_LOCK_R = crate::BitReader;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_LOCK` writer - Set 1 to lock core0 region permission registers."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_LOCK_W<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
impl R {
|
||||
#[doc = "Bit 0 - Set 1 to lock core0 region permission registers."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_lock(&self) -> CORE_0_REGION_PMS_CONSTRAIN_LOCK_R {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_LOCK_R::new((self.bits & 1) != 0)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_0_REGION_PMS_CONSTRAIN_0")
|
||||
.field(
|
||||
"core_0_region_pms_constrain_lock",
|
||||
&self.core_0_region_pms_constrain_lock(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bit 0 - Set 1 to lock core0 region permission registers."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_lock(
|
||||
&mut self,
|
||||
) -> CORE_0_REGION_PMS_CONSTRAIN_LOCK_W<CORE_0_REGION_PMS_CONSTRAIN_0_SPEC> {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_LOCK_W::new(self, 0)
|
||||
}
|
||||
}
|
||||
#[doc = "Core0 region permission register 0.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_region_pms_constrain_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_region_pms_constrain_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_0_REGION_PMS_CONSTRAIN_0_SPEC;
|
||||
impl crate::RegisterSpec for CORE_0_REGION_PMS_CONSTRAIN_0_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_0_region_pms_constrain_0::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_0_REGION_PMS_CONSTRAIN_0_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_0_region_pms_constrain_0::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_0_REGION_PMS_CONSTRAIN_0_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_0_REGION_PMS_CONSTRAIN_0 to value 0"]
|
||||
impl crate::Resettable for CORE_0_REGION_PMS_CONSTRAIN_0_SPEC {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
@@ -0,0 +1,274 @@
|
||||
#[doc = "Register `CORE_0_REGION_PMS_CONSTRAIN_1` reader"]
|
||||
pub type R = crate::R<CORE_0_REGION_PMS_CONSTRAIN_1_SPEC>;
|
||||
#[doc = "Register `CORE_0_REGION_PMS_CONSTRAIN_1` writer"]
|
||||
pub type W = crate::W<CORE_0_REGION_PMS_CONSTRAIN_1_SPEC>;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0` reader - Region 0 permission in world 0 for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0` writer - Region 0 permission in world 0 for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1` reader - Region 1 permission in world 0 for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1` writer - Region 1 permission in world 0 for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2` reader - Region 2 permission in world 0 for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2` writer - Region 2 permission in world 0 for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3` reader - Region 3 permission in world 0 for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3` writer - Region 3 permission in world 0 for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4` reader - Region 4 permission in world 0 for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4` writer - Region 4 permission in world 0 for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5` reader - Region 5 permission in world 0 for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5` writer - Region 5 permission in world 0 for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6` reader - Region 6 permission in world 0 for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6` writer - Region 6 permission in world 0 for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7` reader - Region 7 permission in world 0 for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7` writer - Region 7 permission in world 0 for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8` reader - Region 8 permission in world 0 for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8` writer - Region 8 permission in world 0 for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9` reader - Region 9 permission in world 0 for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9` writer - Region 9 permission in world 0 for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10` reader - Region 10 permission in world 0 for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10` writer - Region 10 permission in world 0 for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:1 - Region 0 permission in world 0 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_world_0_area_0(
|
||||
&self,
|
||||
) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_R {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_R::new((self.bits & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 2:3 - Region 1 permission in world 0 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_world_0_area_1(
|
||||
&self,
|
||||
) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_R {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_R::new(((self.bits >> 2) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 4:5 - Region 2 permission in world 0 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_world_0_area_2(
|
||||
&self,
|
||||
) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_R {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_R::new(((self.bits >> 4) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 6:7 - Region 3 permission in world 0 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_world_0_area_3(
|
||||
&self,
|
||||
) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_R {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_R::new(((self.bits >> 6) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 8:9 - Region 4 permission in world 0 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_world_0_area_4(
|
||||
&self,
|
||||
) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_R {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_R::new(((self.bits >> 8) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 10:11 - Region 5 permission in world 0 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_world_0_area_5(
|
||||
&self,
|
||||
) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_R {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_R::new(((self.bits >> 10) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 12:13 - Region 6 permission in world 0 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_world_0_area_6(
|
||||
&self,
|
||||
) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_R {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_R::new(((self.bits >> 12) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 14:15 - Region 7 permission in world 0 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_world_0_area_7(
|
||||
&self,
|
||||
) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_R {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_R::new(((self.bits >> 14) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 16:17 - Region 8 permission in world 0 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_world_0_area_8(
|
||||
&self,
|
||||
) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_R {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_R::new(((self.bits >> 16) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 18:19 - Region 9 permission in world 0 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_world_0_area_9(
|
||||
&self,
|
||||
) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_R {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_R::new(((self.bits >> 18) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 20:21 - Region 10 permission in world 0 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_world_0_area_10(
|
||||
&self,
|
||||
) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_R {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_R::new(((self.bits >> 20) & 3) as u8)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_0_REGION_PMS_CONSTRAIN_1")
|
||||
.field(
|
||||
"core_0_region_pms_constrain_world_0_area_0",
|
||||
&self.core_0_region_pms_constrain_world_0_area_0(),
|
||||
)
|
||||
.field(
|
||||
"core_0_region_pms_constrain_world_0_area_1",
|
||||
&self.core_0_region_pms_constrain_world_0_area_1(),
|
||||
)
|
||||
.field(
|
||||
"core_0_region_pms_constrain_world_0_area_2",
|
||||
&self.core_0_region_pms_constrain_world_0_area_2(),
|
||||
)
|
||||
.field(
|
||||
"core_0_region_pms_constrain_world_0_area_3",
|
||||
&self.core_0_region_pms_constrain_world_0_area_3(),
|
||||
)
|
||||
.field(
|
||||
"core_0_region_pms_constrain_world_0_area_4",
|
||||
&self.core_0_region_pms_constrain_world_0_area_4(),
|
||||
)
|
||||
.field(
|
||||
"core_0_region_pms_constrain_world_0_area_5",
|
||||
&self.core_0_region_pms_constrain_world_0_area_5(),
|
||||
)
|
||||
.field(
|
||||
"core_0_region_pms_constrain_world_0_area_6",
|
||||
&self.core_0_region_pms_constrain_world_0_area_6(),
|
||||
)
|
||||
.field(
|
||||
"core_0_region_pms_constrain_world_0_area_7",
|
||||
&self.core_0_region_pms_constrain_world_0_area_7(),
|
||||
)
|
||||
.field(
|
||||
"core_0_region_pms_constrain_world_0_area_8",
|
||||
&self.core_0_region_pms_constrain_world_0_area_8(),
|
||||
)
|
||||
.field(
|
||||
"core_0_region_pms_constrain_world_0_area_9",
|
||||
&self.core_0_region_pms_constrain_world_0_area_9(),
|
||||
)
|
||||
.field(
|
||||
"core_0_region_pms_constrain_world_0_area_10",
|
||||
&self.core_0_region_pms_constrain_world_0_area_10(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:1 - Region 0 permission in world 0 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_world_0_area_0(
|
||||
&mut self,
|
||||
) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_W<CORE_0_REGION_PMS_CONSTRAIN_1_SPEC> {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_W::new(self, 0)
|
||||
}
|
||||
#[doc = "Bits 2:3 - Region 1 permission in world 0 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_world_0_area_1(
|
||||
&mut self,
|
||||
) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_W<CORE_0_REGION_PMS_CONSTRAIN_1_SPEC> {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_W::new(self, 2)
|
||||
}
|
||||
#[doc = "Bits 4:5 - Region 2 permission in world 0 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_world_0_area_2(
|
||||
&mut self,
|
||||
) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_W<CORE_0_REGION_PMS_CONSTRAIN_1_SPEC> {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_W::new(self, 4)
|
||||
}
|
||||
#[doc = "Bits 6:7 - Region 3 permission in world 0 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_world_0_area_3(
|
||||
&mut self,
|
||||
) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_W<CORE_0_REGION_PMS_CONSTRAIN_1_SPEC> {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_W::new(self, 6)
|
||||
}
|
||||
#[doc = "Bits 8:9 - Region 4 permission in world 0 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_world_0_area_4(
|
||||
&mut self,
|
||||
) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_W<CORE_0_REGION_PMS_CONSTRAIN_1_SPEC> {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_W::new(self, 8)
|
||||
}
|
||||
#[doc = "Bits 10:11 - Region 5 permission in world 0 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_world_0_area_5(
|
||||
&mut self,
|
||||
) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_W<CORE_0_REGION_PMS_CONSTRAIN_1_SPEC> {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_W::new(self, 10)
|
||||
}
|
||||
#[doc = "Bits 12:13 - Region 6 permission in world 0 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_world_0_area_6(
|
||||
&mut self,
|
||||
) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_W<CORE_0_REGION_PMS_CONSTRAIN_1_SPEC> {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_W::new(self, 12)
|
||||
}
|
||||
#[doc = "Bits 14:15 - Region 7 permission in world 0 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_world_0_area_7(
|
||||
&mut self,
|
||||
) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_W<CORE_0_REGION_PMS_CONSTRAIN_1_SPEC> {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_W::new(self, 14)
|
||||
}
|
||||
#[doc = "Bits 16:17 - Region 8 permission in world 0 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_world_0_area_8(
|
||||
&mut self,
|
||||
) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_W<CORE_0_REGION_PMS_CONSTRAIN_1_SPEC> {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_W::new(self, 16)
|
||||
}
|
||||
#[doc = "Bits 18:19 - Region 9 permission in world 0 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_world_0_area_9(
|
||||
&mut self,
|
||||
) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_W<CORE_0_REGION_PMS_CONSTRAIN_1_SPEC> {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_W::new(self, 18)
|
||||
}
|
||||
#[doc = "Bits 20:21 - Region 10 permission in world 0 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_world_0_area_10(
|
||||
&mut self,
|
||||
) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_W<CORE_0_REGION_PMS_CONSTRAIN_1_SPEC> {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_W::new(self, 20)
|
||||
}
|
||||
}
|
||||
#[doc = "Core0 region permission register 1.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_region_pms_constrain_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_region_pms_constrain_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_0_REGION_PMS_CONSTRAIN_1_SPEC;
|
||||
impl crate::RegisterSpec for CORE_0_REGION_PMS_CONSTRAIN_1_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_0_region_pms_constrain_1::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_0_REGION_PMS_CONSTRAIN_1_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_0_region_pms_constrain_1::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_0_REGION_PMS_CONSTRAIN_1_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_0_REGION_PMS_CONSTRAIN_1 to value 0x003f_ffff"]
|
||||
impl crate::Resettable for CORE_0_REGION_PMS_CONSTRAIN_1_SPEC {
|
||||
const RESET_VALUE: u32 = 0x003f_ffff;
|
||||
}
|
||||
@@ -0,0 +1,52 @@
|
||||
#[doc = "Register `CORE_0_REGION_PMS_CONSTRAIN_10` reader"]
|
||||
pub type R = crate::R<CORE_0_REGION_PMS_CONSTRAIN_10_SPEC>;
|
||||
#[doc = "Register `CORE_0_REGION_PMS_CONSTRAIN_10` writer"]
|
||||
pub type W = crate::W<CORE_0_REGION_PMS_CONSTRAIN_10_SPEC>;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_ADDR_7` reader - Region 6 end address and Region 7 start address for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_ADDR_7_R = crate::FieldReader<u32>;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_ADDR_7` writer - Region 6 end address and Region 7 start address for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_ADDR_7_W<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:29 - Region 6 end address and Region 7 start address for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_addr_7(&self) -> CORE_0_REGION_PMS_CONSTRAIN_ADDR_7_R {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_ADDR_7_R::new(self.bits & 0x3fff_ffff)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_0_REGION_PMS_CONSTRAIN_10")
|
||||
.field(
|
||||
"core_0_region_pms_constrain_addr_7",
|
||||
&self.core_0_region_pms_constrain_addr_7(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:29 - Region 6 end address and Region 7 start address for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_addr_7(
|
||||
&mut self,
|
||||
) -> CORE_0_REGION_PMS_CONSTRAIN_ADDR_7_W<CORE_0_REGION_PMS_CONSTRAIN_10_SPEC> {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_ADDR_7_W::new(self, 0)
|
||||
}
|
||||
}
|
||||
#[doc = "Core0 region permission register 10.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_region_pms_constrain_10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_region_pms_constrain_10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_0_REGION_PMS_CONSTRAIN_10_SPEC;
|
||||
impl crate::RegisterSpec for CORE_0_REGION_PMS_CONSTRAIN_10_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_0_region_pms_constrain_10::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_0_REGION_PMS_CONSTRAIN_10_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_0_region_pms_constrain_10::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_0_REGION_PMS_CONSTRAIN_10_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_0_REGION_PMS_CONSTRAIN_10 to value 0"]
|
||||
impl crate::Resettable for CORE_0_REGION_PMS_CONSTRAIN_10_SPEC {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
@@ -0,0 +1,52 @@
|
||||
#[doc = "Register `CORE_0_REGION_PMS_CONSTRAIN_11` reader"]
|
||||
pub type R = crate::R<CORE_0_REGION_PMS_CONSTRAIN_11_SPEC>;
|
||||
#[doc = "Register `CORE_0_REGION_PMS_CONSTRAIN_11` writer"]
|
||||
pub type W = crate::W<CORE_0_REGION_PMS_CONSTRAIN_11_SPEC>;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_ADDR_8` reader - Region 7 end address and Region 8 start address for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_ADDR_8_R = crate::FieldReader<u32>;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_ADDR_8` writer - Region 7 end address and Region 8 start address for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_ADDR_8_W<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:29 - Region 7 end address and Region 8 start address for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_addr_8(&self) -> CORE_0_REGION_PMS_CONSTRAIN_ADDR_8_R {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_ADDR_8_R::new(self.bits & 0x3fff_ffff)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_0_REGION_PMS_CONSTRAIN_11")
|
||||
.field(
|
||||
"core_0_region_pms_constrain_addr_8",
|
||||
&self.core_0_region_pms_constrain_addr_8(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:29 - Region 7 end address and Region 8 start address for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_addr_8(
|
||||
&mut self,
|
||||
) -> CORE_0_REGION_PMS_CONSTRAIN_ADDR_8_W<CORE_0_REGION_PMS_CONSTRAIN_11_SPEC> {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_ADDR_8_W::new(self, 0)
|
||||
}
|
||||
}
|
||||
#[doc = "Core0 region permission register 11.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_region_pms_constrain_11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_region_pms_constrain_11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_0_REGION_PMS_CONSTRAIN_11_SPEC;
|
||||
impl crate::RegisterSpec for CORE_0_REGION_PMS_CONSTRAIN_11_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_0_region_pms_constrain_11::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_0_REGION_PMS_CONSTRAIN_11_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_0_region_pms_constrain_11::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_0_REGION_PMS_CONSTRAIN_11_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_0_REGION_PMS_CONSTRAIN_11 to value 0"]
|
||||
impl crate::Resettable for CORE_0_REGION_PMS_CONSTRAIN_11_SPEC {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
@@ -0,0 +1,52 @@
|
||||
#[doc = "Register `CORE_0_REGION_PMS_CONSTRAIN_12` reader"]
|
||||
pub type R = crate::R<CORE_0_REGION_PMS_CONSTRAIN_12_SPEC>;
|
||||
#[doc = "Register `CORE_0_REGION_PMS_CONSTRAIN_12` writer"]
|
||||
pub type W = crate::W<CORE_0_REGION_PMS_CONSTRAIN_12_SPEC>;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_ADDR_9` reader - Region 8 end address and Region 9 start address for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_ADDR_9_R = crate::FieldReader<u32>;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_ADDR_9` writer - Region 8 end address and Region 9 start address for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_ADDR_9_W<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:29 - Region 8 end address and Region 9 start address for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_addr_9(&self) -> CORE_0_REGION_PMS_CONSTRAIN_ADDR_9_R {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_ADDR_9_R::new(self.bits & 0x3fff_ffff)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_0_REGION_PMS_CONSTRAIN_12")
|
||||
.field(
|
||||
"core_0_region_pms_constrain_addr_9",
|
||||
&self.core_0_region_pms_constrain_addr_9(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:29 - Region 8 end address and Region 9 start address for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_addr_9(
|
||||
&mut self,
|
||||
) -> CORE_0_REGION_PMS_CONSTRAIN_ADDR_9_W<CORE_0_REGION_PMS_CONSTRAIN_12_SPEC> {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_ADDR_9_W::new(self, 0)
|
||||
}
|
||||
}
|
||||
#[doc = "Core0 region permission register 12.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_region_pms_constrain_12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_region_pms_constrain_12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_0_REGION_PMS_CONSTRAIN_12_SPEC;
|
||||
impl crate::RegisterSpec for CORE_0_REGION_PMS_CONSTRAIN_12_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_0_region_pms_constrain_12::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_0_REGION_PMS_CONSTRAIN_12_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_0_region_pms_constrain_12::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_0_REGION_PMS_CONSTRAIN_12_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_0_REGION_PMS_CONSTRAIN_12 to value 0"]
|
||||
impl crate::Resettable for CORE_0_REGION_PMS_CONSTRAIN_12_SPEC {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
@@ -0,0 +1,52 @@
|
||||
#[doc = "Register `CORE_0_REGION_PMS_CONSTRAIN_13` reader"]
|
||||
pub type R = crate::R<CORE_0_REGION_PMS_CONSTRAIN_13_SPEC>;
|
||||
#[doc = "Register `CORE_0_REGION_PMS_CONSTRAIN_13` writer"]
|
||||
pub type W = crate::W<CORE_0_REGION_PMS_CONSTRAIN_13_SPEC>;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_ADDR_10` reader - Region 9 end address and Region 10 start address for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_ADDR_10_R = crate::FieldReader<u32>;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_ADDR_10` writer - Region 9 end address and Region 10 start address for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_ADDR_10_W<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:29 - Region 9 end address and Region 10 start address for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_addr_10(&self) -> CORE_0_REGION_PMS_CONSTRAIN_ADDR_10_R {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_ADDR_10_R::new(self.bits & 0x3fff_ffff)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_0_REGION_PMS_CONSTRAIN_13")
|
||||
.field(
|
||||
"core_0_region_pms_constrain_addr_10",
|
||||
&self.core_0_region_pms_constrain_addr_10(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:29 - Region 9 end address and Region 10 start address for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_addr_10(
|
||||
&mut self,
|
||||
) -> CORE_0_REGION_PMS_CONSTRAIN_ADDR_10_W<CORE_0_REGION_PMS_CONSTRAIN_13_SPEC> {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_ADDR_10_W::new(self, 0)
|
||||
}
|
||||
}
|
||||
#[doc = "Core0 region permission register 13.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_region_pms_constrain_13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_region_pms_constrain_13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_0_REGION_PMS_CONSTRAIN_13_SPEC;
|
||||
impl crate::RegisterSpec for CORE_0_REGION_PMS_CONSTRAIN_13_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_0_region_pms_constrain_13::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_0_REGION_PMS_CONSTRAIN_13_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_0_region_pms_constrain_13::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_0_REGION_PMS_CONSTRAIN_13_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_0_REGION_PMS_CONSTRAIN_13 to value 0"]
|
||||
impl crate::Resettable for CORE_0_REGION_PMS_CONSTRAIN_13_SPEC {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
@@ -0,0 +1,52 @@
|
||||
#[doc = "Register `CORE_0_REGION_PMS_CONSTRAIN_14` reader"]
|
||||
pub type R = crate::R<CORE_0_REGION_PMS_CONSTRAIN_14_SPEC>;
|
||||
#[doc = "Register `CORE_0_REGION_PMS_CONSTRAIN_14` writer"]
|
||||
pub type W = crate::W<CORE_0_REGION_PMS_CONSTRAIN_14_SPEC>;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_ADDR_11` reader - Region 10 end address for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_ADDR_11_R = crate::FieldReader<u32>;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_ADDR_11` writer - Region 10 end address for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_ADDR_11_W<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:29 - Region 10 end address for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_addr_11(&self) -> CORE_0_REGION_PMS_CONSTRAIN_ADDR_11_R {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_ADDR_11_R::new(self.bits & 0x3fff_ffff)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_0_REGION_PMS_CONSTRAIN_14")
|
||||
.field(
|
||||
"core_0_region_pms_constrain_addr_11",
|
||||
&self.core_0_region_pms_constrain_addr_11(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:29 - Region 10 end address for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_addr_11(
|
||||
&mut self,
|
||||
) -> CORE_0_REGION_PMS_CONSTRAIN_ADDR_11_W<CORE_0_REGION_PMS_CONSTRAIN_14_SPEC> {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_ADDR_11_W::new(self, 0)
|
||||
}
|
||||
}
|
||||
#[doc = "Core0 region permission register 14.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_region_pms_constrain_14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_region_pms_constrain_14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_0_REGION_PMS_CONSTRAIN_14_SPEC;
|
||||
impl crate::RegisterSpec for CORE_0_REGION_PMS_CONSTRAIN_14_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_0_region_pms_constrain_14::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_0_REGION_PMS_CONSTRAIN_14_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_0_region_pms_constrain_14::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_0_REGION_PMS_CONSTRAIN_14_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_0_REGION_PMS_CONSTRAIN_14 to value 0"]
|
||||
impl crate::Resettable for CORE_0_REGION_PMS_CONSTRAIN_14_SPEC {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
@@ -0,0 +1,274 @@
|
||||
#[doc = "Register `CORE_0_REGION_PMS_CONSTRAIN_2` reader"]
|
||||
pub type R = crate::R<CORE_0_REGION_PMS_CONSTRAIN_2_SPEC>;
|
||||
#[doc = "Register `CORE_0_REGION_PMS_CONSTRAIN_2` writer"]
|
||||
pub type W = crate::W<CORE_0_REGION_PMS_CONSTRAIN_2_SPEC>;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0` reader - Region 0 permission in world 1 for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0` writer - Region 0 permission in world 1 for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1` reader - Region 1 permission in world 1 for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1` writer - Region 1 permission in world 1 for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2` reader - Region 2 permission in world 1 for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2` writer - Region 2 permission in world 1 for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3` reader - Region 3 permission in world 1 for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3` writer - Region 3 permission in world 1 for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4` reader - Region 4 permission in world 1 for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4` writer - Region 4 permission in world 1 for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5` reader - Region 5 permission in world 1 for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5` writer - Region 5 permission in world 1 for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6` reader - Region 6 permission in world 1 for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6` writer - Region 6 permission in world 1 for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7` reader - Region 7 permission in world 1 for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7` writer - Region 7 permission in world 1 for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8` reader - Region 8 permission in world 1 for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8` writer - Region 8 permission in world 1 for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9` reader - Region 9 permission in world 1 for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9` writer - Region 9 permission in world 1 for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10` reader - Region 10 permission in world 1 for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10` writer - Region 10 permission in world 1 for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:1 - Region 0 permission in world 1 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_world_1_area_0(
|
||||
&self,
|
||||
) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_R {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_R::new((self.bits & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 2:3 - Region 1 permission in world 1 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_world_1_area_1(
|
||||
&self,
|
||||
) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_R {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_R::new(((self.bits >> 2) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 4:5 - Region 2 permission in world 1 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_world_1_area_2(
|
||||
&self,
|
||||
) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_R {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_R::new(((self.bits >> 4) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 6:7 - Region 3 permission in world 1 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_world_1_area_3(
|
||||
&self,
|
||||
) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_R {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_R::new(((self.bits >> 6) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 8:9 - Region 4 permission in world 1 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_world_1_area_4(
|
||||
&self,
|
||||
) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_R {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_R::new(((self.bits >> 8) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 10:11 - Region 5 permission in world 1 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_world_1_area_5(
|
||||
&self,
|
||||
) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_R {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_R::new(((self.bits >> 10) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 12:13 - Region 6 permission in world 1 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_world_1_area_6(
|
||||
&self,
|
||||
) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_R {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_R::new(((self.bits >> 12) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 14:15 - Region 7 permission in world 1 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_world_1_area_7(
|
||||
&self,
|
||||
) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_R {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_R::new(((self.bits >> 14) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 16:17 - Region 8 permission in world 1 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_world_1_area_8(
|
||||
&self,
|
||||
) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_R {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_R::new(((self.bits >> 16) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 18:19 - Region 9 permission in world 1 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_world_1_area_9(
|
||||
&self,
|
||||
) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_R {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_R::new(((self.bits >> 18) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 20:21 - Region 10 permission in world 1 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_world_1_area_10(
|
||||
&self,
|
||||
) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_R {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_R::new(((self.bits >> 20) & 3) as u8)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_0_REGION_PMS_CONSTRAIN_2")
|
||||
.field(
|
||||
"core_0_region_pms_constrain_world_1_area_0",
|
||||
&self.core_0_region_pms_constrain_world_1_area_0(),
|
||||
)
|
||||
.field(
|
||||
"core_0_region_pms_constrain_world_1_area_1",
|
||||
&self.core_0_region_pms_constrain_world_1_area_1(),
|
||||
)
|
||||
.field(
|
||||
"core_0_region_pms_constrain_world_1_area_2",
|
||||
&self.core_0_region_pms_constrain_world_1_area_2(),
|
||||
)
|
||||
.field(
|
||||
"core_0_region_pms_constrain_world_1_area_3",
|
||||
&self.core_0_region_pms_constrain_world_1_area_3(),
|
||||
)
|
||||
.field(
|
||||
"core_0_region_pms_constrain_world_1_area_4",
|
||||
&self.core_0_region_pms_constrain_world_1_area_4(),
|
||||
)
|
||||
.field(
|
||||
"core_0_region_pms_constrain_world_1_area_5",
|
||||
&self.core_0_region_pms_constrain_world_1_area_5(),
|
||||
)
|
||||
.field(
|
||||
"core_0_region_pms_constrain_world_1_area_6",
|
||||
&self.core_0_region_pms_constrain_world_1_area_6(),
|
||||
)
|
||||
.field(
|
||||
"core_0_region_pms_constrain_world_1_area_7",
|
||||
&self.core_0_region_pms_constrain_world_1_area_7(),
|
||||
)
|
||||
.field(
|
||||
"core_0_region_pms_constrain_world_1_area_8",
|
||||
&self.core_0_region_pms_constrain_world_1_area_8(),
|
||||
)
|
||||
.field(
|
||||
"core_0_region_pms_constrain_world_1_area_9",
|
||||
&self.core_0_region_pms_constrain_world_1_area_9(),
|
||||
)
|
||||
.field(
|
||||
"core_0_region_pms_constrain_world_1_area_10",
|
||||
&self.core_0_region_pms_constrain_world_1_area_10(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:1 - Region 0 permission in world 1 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_world_1_area_0(
|
||||
&mut self,
|
||||
) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_W<CORE_0_REGION_PMS_CONSTRAIN_2_SPEC> {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_W::new(self, 0)
|
||||
}
|
||||
#[doc = "Bits 2:3 - Region 1 permission in world 1 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_world_1_area_1(
|
||||
&mut self,
|
||||
) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_W<CORE_0_REGION_PMS_CONSTRAIN_2_SPEC> {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_W::new(self, 2)
|
||||
}
|
||||
#[doc = "Bits 4:5 - Region 2 permission in world 1 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_world_1_area_2(
|
||||
&mut self,
|
||||
) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_W<CORE_0_REGION_PMS_CONSTRAIN_2_SPEC> {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_W::new(self, 4)
|
||||
}
|
||||
#[doc = "Bits 6:7 - Region 3 permission in world 1 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_world_1_area_3(
|
||||
&mut self,
|
||||
) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_W<CORE_0_REGION_PMS_CONSTRAIN_2_SPEC> {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_W::new(self, 6)
|
||||
}
|
||||
#[doc = "Bits 8:9 - Region 4 permission in world 1 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_world_1_area_4(
|
||||
&mut self,
|
||||
) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_W<CORE_0_REGION_PMS_CONSTRAIN_2_SPEC> {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_W::new(self, 8)
|
||||
}
|
||||
#[doc = "Bits 10:11 - Region 5 permission in world 1 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_world_1_area_5(
|
||||
&mut self,
|
||||
) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_W<CORE_0_REGION_PMS_CONSTRAIN_2_SPEC> {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_W::new(self, 10)
|
||||
}
|
||||
#[doc = "Bits 12:13 - Region 6 permission in world 1 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_world_1_area_6(
|
||||
&mut self,
|
||||
) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_W<CORE_0_REGION_PMS_CONSTRAIN_2_SPEC> {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_W::new(self, 12)
|
||||
}
|
||||
#[doc = "Bits 14:15 - Region 7 permission in world 1 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_world_1_area_7(
|
||||
&mut self,
|
||||
) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_W<CORE_0_REGION_PMS_CONSTRAIN_2_SPEC> {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_W::new(self, 14)
|
||||
}
|
||||
#[doc = "Bits 16:17 - Region 8 permission in world 1 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_world_1_area_8(
|
||||
&mut self,
|
||||
) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_W<CORE_0_REGION_PMS_CONSTRAIN_2_SPEC> {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_W::new(self, 16)
|
||||
}
|
||||
#[doc = "Bits 18:19 - Region 9 permission in world 1 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_world_1_area_9(
|
||||
&mut self,
|
||||
) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_W<CORE_0_REGION_PMS_CONSTRAIN_2_SPEC> {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_W::new(self, 18)
|
||||
}
|
||||
#[doc = "Bits 20:21 - Region 10 permission in world 1 for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_world_1_area_10(
|
||||
&mut self,
|
||||
) -> CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_W<CORE_0_REGION_PMS_CONSTRAIN_2_SPEC> {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_W::new(self, 20)
|
||||
}
|
||||
}
|
||||
#[doc = "Core0 region permission register 2.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_region_pms_constrain_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_region_pms_constrain_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_0_REGION_PMS_CONSTRAIN_2_SPEC;
|
||||
impl crate::RegisterSpec for CORE_0_REGION_PMS_CONSTRAIN_2_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_0_region_pms_constrain_2::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_0_REGION_PMS_CONSTRAIN_2_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_0_region_pms_constrain_2::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_0_REGION_PMS_CONSTRAIN_2_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_0_REGION_PMS_CONSTRAIN_2 to value 0x003f_ffff"]
|
||||
impl crate::Resettable for CORE_0_REGION_PMS_CONSTRAIN_2_SPEC {
|
||||
const RESET_VALUE: u32 = 0x003f_ffff;
|
||||
}
|
||||
@@ -0,0 +1,52 @@
|
||||
#[doc = "Register `CORE_0_REGION_PMS_CONSTRAIN_3` reader"]
|
||||
pub type R = crate::R<CORE_0_REGION_PMS_CONSTRAIN_3_SPEC>;
|
||||
#[doc = "Register `CORE_0_REGION_PMS_CONSTRAIN_3` writer"]
|
||||
pub type W = crate::W<CORE_0_REGION_PMS_CONSTRAIN_3_SPEC>;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_ADDR_0` reader - Region 0 start address for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_ADDR_0_R = crate::FieldReader<u32>;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_ADDR_0` writer - Region 0 start address for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_ADDR_0_W<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:29 - Region 0 start address for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_addr_0(&self) -> CORE_0_REGION_PMS_CONSTRAIN_ADDR_0_R {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_ADDR_0_R::new(self.bits & 0x3fff_ffff)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_0_REGION_PMS_CONSTRAIN_3")
|
||||
.field(
|
||||
"core_0_region_pms_constrain_addr_0",
|
||||
&self.core_0_region_pms_constrain_addr_0(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:29 - Region 0 start address for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_addr_0(
|
||||
&mut self,
|
||||
) -> CORE_0_REGION_PMS_CONSTRAIN_ADDR_0_W<CORE_0_REGION_PMS_CONSTRAIN_3_SPEC> {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_ADDR_0_W::new(self, 0)
|
||||
}
|
||||
}
|
||||
#[doc = "Core0 region permission register 3.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_region_pms_constrain_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_region_pms_constrain_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_0_REGION_PMS_CONSTRAIN_3_SPEC;
|
||||
impl crate::RegisterSpec for CORE_0_REGION_PMS_CONSTRAIN_3_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_0_region_pms_constrain_3::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_0_REGION_PMS_CONSTRAIN_3_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_0_region_pms_constrain_3::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_0_REGION_PMS_CONSTRAIN_3_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_0_REGION_PMS_CONSTRAIN_3 to value 0"]
|
||||
impl crate::Resettable for CORE_0_REGION_PMS_CONSTRAIN_3_SPEC {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
@@ -0,0 +1,52 @@
|
||||
#[doc = "Register `CORE_0_REGION_PMS_CONSTRAIN_4` reader"]
|
||||
pub type R = crate::R<CORE_0_REGION_PMS_CONSTRAIN_4_SPEC>;
|
||||
#[doc = "Register `CORE_0_REGION_PMS_CONSTRAIN_4` writer"]
|
||||
pub type W = crate::W<CORE_0_REGION_PMS_CONSTRAIN_4_SPEC>;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_ADDR_1` reader - Region 0 end address and Region 1 start address for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_ADDR_1_R = crate::FieldReader<u32>;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_ADDR_1` writer - Region 0 end address and Region 1 start address for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_ADDR_1_W<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:29 - Region 0 end address and Region 1 start address for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_addr_1(&self) -> CORE_0_REGION_PMS_CONSTRAIN_ADDR_1_R {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_ADDR_1_R::new(self.bits & 0x3fff_ffff)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_0_REGION_PMS_CONSTRAIN_4")
|
||||
.field(
|
||||
"core_0_region_pms_constrain_addr_1",
|
||||
&self.core_0_region_pms_constrain_addr_1(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:29 - Region 0 end address and Region 1 start address for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_addr_1(
|
||||
&mut self,
|
||||
) -> CORE_0_REGION_PMS_CONSTRAIN_ADDR_1_W<CORE_0_REGION_PMS_CONSTRAIN_4_SPEC> {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_ADDR_1_W::new(self, 0)
|
||||
}
|
||||
}
|
||||
#[doc = "Core0 region permission register 4.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_region_pms_constrain_4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_region_pms_constrain_4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_0_REGION_PMS_CONSTRAIN_4_SPEC;
|
||||
impl crate::RegisterSpec for CORE_0_REGION_PMS_CONSTRAIN_4_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_0_region_pms_constrain_4::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_0_REGION_PMS_CONSTRAIN_4_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_0_region_pms_constrain_4::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_0_REGION_PMS_CONSTRAIN_4_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_0_REGION_PMS_CONSTRAIN_4 to value 0"]
|
||||
impl crate::Resettable for CORE_0_REGION_PMS_CONSTRAIN_4_SPEC {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
@@ -0,0 +1,52 @@
|
||||
#[doc = "Register `CORE_0_REGION_PMS_CONSTRAIN_5` reader"]
|
||||
pub type R = crate::R<CORE_0_REGION_PMS_CONSTRAIN_5_SPEC>;
|
||||
#[doc = "Register `CORE_0_REGION_PMS_CONSTRAIN_5` writer"]
|
||||
pub type W = crate::W<CORE_0_REGION_PMS_CONSTRAIN_5_SPEC>;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_ADDR_2` reader - Region 1 end address and Region 2 start address for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_ADDR_2_R = crate::FieldReader<u32>;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_ADDR_2` writer - Region 1 end address and Region 2 start address for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_ADDR_2_W<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:29 - Region 1 end address and Region 2 start address for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_addr_2(&self) -> CORE_0_REGION_PMS_CONSTRAIN_ADDR_2_R {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_ADDR_2_R::new(self.bits & 0x3fff_ffff)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_0_REGION_PMS_CONSTRAIN_5")
|
||||
.field(
|
||||
"core_0_region_pms_constrain_addr_2",
|
||||
&self.core_0_region_pms_constrain_addr_2(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:29 - Region 1 end address and Region 2 start address for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_addr_2(
|
||||
&mut self,
|
||||
) -> CORE_0_REGION_PMS_CONSTRAIN_ADDR_2_W<CORE_0_REGION_PMS_CONSTRAIN_5_SPEC> {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_ADDR_2_W::new(self, 0)
|
||||
}
|
||||
}
|
||||
#[doc = "Core0 region permission register 5.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_region_pms_constrain_5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_region_pms_constrain_5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_0_REGION_PMS_CONSTRAIN_5_SPEC;
|
||||
impl crate::RegisterSpec for CORE_0_REGION_PMS_CONSTRAIN_5_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_0_region_pms_constrain_5::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_0_REGION_PMS_CONSTRAIN_5_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_0_region_pms_constrain_5::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_0_REGION_PMS_CONSTRAIN_5_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_0_REGION_PMS_CONSTRAIN_5 to value 0"]
|
||||
impl crate::Resettable for CORE_0_REGION_PMS_CONSTRAIN_5_SPEC {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
@@ -0,0 +1,52 @@
|
||||
#[doc = "Register `CORE_0_REGION_PMS_CONSTRAIN_6` reader"]
|
||||
pub type R = crate::R<CORE_0_REGION_PMS_CONSTRAIN_6_SPEC>;
|
||||
#[doc = "Register `CORE_0_REGION_PMS_CONSTRAIN_6` writer"]
|
||||
pub type W = crate::W<CORE_0_REGION_PMS_CONSTRAIN_6_SPEC>;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_ADDR_3` reader - Region 2 end address and Region 3 start address for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_ADDR_3_R = crate::FieldReader<u32>;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_ADDR_3` writer - Region 2 end address and Region 3 start address for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_ADDR_3_W<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:29 - Region 2 end address and Region 3 start address for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_addr_3(&self) -> CORE_0_REGION_PMS_CONSTRAIN_ADDR_3_R {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_ADDR_3_R::new(self.bits & 0x3fff_ffff)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_0_REGION_PMS_CONSTRAIN_6")
|
||||
.field(
|
||||
"core_0_region_pms_constrain_addr_3",
|
||||
&self.core_0_region_pms_constrain_addr_3(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:29 - Region 2 end address and Region 3 start address for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_addr_3(
|
||||
&mut self,
|
||||
) -> CORE_0_REGION_PMS_CONSTRAIN_ADDR_3_W<CORE_0_REGION_PMS_CONSTRAIN_6_SPEC> {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_ADDR_3_W::new(self, 0)
|
||||
}
|
||||
}
|
||||
#[doc = "Core0 region permission register 6.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_region_pms_constrain_6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_region_pms_constrain_6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_0_REGION_PMS_CONSTRAIN_6_SPEC;
|
||||
impl crate::RegisterSpec for CORE_0_REGION_PMS_CONSTRAIN_6_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_0_region_pms_constrain_6::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_0_REGION_PMS_CONSTRAIN_6_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_0_region_pms_constrain_6::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_0_REGION_PMS_CONSTRAIN_6_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_0_REGION_PMS_CONSTRAIN_6 to value 0"]
|
||||
impl crate::Resettable for CORE_0_REGION_PMS_CONSTRAIN_6_SPEC {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
@@ -0,0 +1,52 @@
|
||||
#[doc = "Register `CORE_0_REGION_PMS_CONSTRAIN_7` reader"]
|
||||
pub type R = crate::R<CORE_0_REGION_PMS_CONSTRAIN_7_SPEC>;
|
||||
#[doc = "Register `CORE_0_REGION_PMS_CONSTRAIN_7` writer"]
|
||||
pub type W = crate::W<CORE_0_REGION_PMS_CONSTRAIN_7_SPEC>;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_ADDR_4` reader - Region 3 end address and Region 4 start address for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_ADDR_4_R = crate::FieldReader<u32>;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_ADDR_4` writer - Region 3 end address and Region 4 start address for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_ADDR_4_W<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:29 - Region 3 end address and Region 4 start address for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_addr_4(&self) -> CORE_0_REGION_PMS_CONSTRAIN_ADDR_4_R {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_ADDR_4_R::new(self.bits & 0x3fff_ffff)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_0_REGION_PMS_CONSTRAIN_7")
|
||||
.field(
|
||||
"core_0_region_pms_constrain_addr_4",
|
||||
&self.core_0_region_pms_constrain_addr_4(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:29 - Region 3 end address and Region 4 start address for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_addr_4(
|
||||
&mut self,
|
||||
) -> CORE_0_REGION_PMS_CONSTRAIN_ADDR_4_W<CORE_0_REGION_PMS_CONSTRAIN_7_SPEC> {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_ADDR_4_W::new(self, 0)
|
||||
}
|
||||
}
|
||||
#[doc = "Core0 region permission register 7.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_region_pms_constrain_7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_region_pms_constrain_7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_0_REGION_PMS_CONSTRAIN_7_SPEC;
|
||||
impl crate::RegisterSpec for CORE_0_REGION_PMS_CONSTRAIN_7_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_0_region_pms_constrain_7::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_0_REGION_PMS_CONSTRAIN_7_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_0_region_pms_constrain_7::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_0_REGION_PMS_CONSTRAIN_7_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_0_REGION_PMS_CONSTRAIN_7 to value 0"]
|
||||
impl crate::Resettable for CORE_0_REGION_PMS_CONSTRAIN_7_SPEC {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
@@ -0,0 +1,52 @@
|
||||
#[doc = "Register `CORE_0_REGION_PMS_CONSTRAIN_8` reader"]
|
||||
pub type R = crate::R<CORE_0_REGION_PMS_CONSTRAIN_8_SPEC>;
|
||||
#[doc = "Register `CORE_0_REGION_PMS_CONSTRAIN_8` writer"]
|
||||
pub type W = crate::W<CORE_0_REGION_PMS_CONSTRAIN_8_SPEC>;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_ADDR_5` reader - Region 4 end address and Region 5 start address for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_ADDR_5_R = crate::FieldReader<u32>;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_ADDR_5` writer - Region 4 end address and Region 5 start address for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_ADDR_5_W<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:29 - Region 4 end address and Region 5 start address for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_addr_5(&self) -> CORE_0_REGION_PMS_CONSTRAIN_ADDR_5_R {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_ADDR_5_R::new(self.bits & 0x3fff_ffff)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_0_REGION_PMS_CONSTRAIN_8")
|
||||
.field(
|
||||
"core_0_region_pms_constrain_addr_5",
|
||||
&self.core_0_region_pms_constrain_addr_5(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:29 - Region 4 end address and Region 5 start address for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_addr_5(
|
||||
&mut self,
|
||||
) -> CORE_0_REGION_PMS_CONSTRAIN_ADDR_5_W<CORE_0_REGION_PMS_CONSTRAIN_8_SPEC> {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_ADDR_5_W::new(self, 0)
|
||||
}
|
||||
}
|
||||
#[doc = "Core0 region permission register 8.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_region_pms_constrain_8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_region_pms_constrain_8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_0_REGION_PMS_CONSTRAIN_8_SPEC;
|
||||
impl crate::RegisterSpec for CORE_0_REGION_PMS_CONSTRAIN_8_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_0_region_pms_constrain_8::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_0_REGION_PMS_CONSTRAIN_8_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_0_region_pms_constrain_8::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_0_REGION_PMS_CONSTRAIN_8_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_0_REGION_PMS_CONSTRAIN_8 to value 0"]
|
||||
impl crate::Resettable for CORE_0_REGION_PMS_CONSTRAIN_8_SPEC {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
@@ -0,0 +1,52 @@
|
||||
#[doc = "Register `CORE_0_REGION_PMS_CONSTRAIN_9` reader"]
|
||||
pub type R = crate::R<CORE_0_REGION_PMS_CONSTRAIN_9_SPEC>;
|
||||
#[doc = "Register `CORE_0_REGION_PMS_CONSTRAIN_9` writer"]
|
||||
pub type W = crate::W<CORE_0_REGION_PMS_CONSTRAIN_9_SPEC>;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_ADDR_6` reader - Region 5 end address and Region 6 start address for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_ADDR_6_R = crate::FieldReader<u32>;
|
||||
#[doc = "Field `CORE_0_REGION_PMS_CONSTRAIN_ADDR_6` writer - Region 5 end address and Region 6 start address for core0."]
|
||||
pub type CORE_0_REGION_PMS_CONSTRAIN_ADDR_6_W<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:29 - Region 5 end address and Region 6 start address for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_addr_6(&self) -> CORE_0_REGION_PMS_CONSTRAIN_ADDR_6_R {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_ADDR_6_R::new(self.bits & 0x3fff_ffff)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_0_REGION_PMS_CONSTRAIN_9")
|
||||
.field(
|
||||
"core_0_region_pms_constrain_addr_6",
|
||||
&self.core_0_region_pms_constrain_addr_6(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:29 - Region 5 end address and Region 6 start address for core0."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_region_pms_constrain_addr_6(
|
||||
&mut self,
|
||||
) -> CORE_0_REGION_PMS_CONSTRAIN_ADDR_6_W<CORE_0_REGION_PMS_CONSTRAIN_9_SPEC> {
|
||||
CORE_0_REGION_PMS_CONSTRAIN_ADDR_6_W::new(self, 0)
|
||||
}
|
||||
}
|
||||
#[doc = "Core0 region permission register 9.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_region_pms_constrain_9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_region_pms_constrain_9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_0_REGION_PMS_CONSTRAIN_9_SPEC;
|
||||
impl crate::RegisterSpec for CORE_0_REGION_PMS_CONSTRAIN_9_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_0_region_pms_constrain_9::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_0_REGION_PMS_CONSTRAIN_9_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_0_region_pms_constrain_9::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_0_REGION_PMS_CONSTRAIN_9_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_0_REGION_PMS_CONSTRAIN_9 to value 0"]
|
||||
impl crate::Resettable for CORE_0_REGION_PMS_CONSTRAIN_9_SPEC {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
@@ -0,0 +1,55 @@
|
||||
#[doc = "Register `CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_0` reader"]
|
||||
pub type R = crate::R<CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_0_SPEC>;
|
||||
#[doc = "Register `CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_0` writer"]
|
||||
pub type W = crate::W<CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_0_SPEC>;
|
||||
#[doc = "Field `CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK` reader - Set 1 to lock core0 toomanyexception override configuration register"]
|
||||
pub type CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_R = crate::BitReader;
|
||||
#[doc = "Field `CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK` writer - Set 1 to lock core0 toomanyexception override configuration register"]
|
||||
pub type CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_W<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
impl R {
|
||||
#[doc = "Bit 0 - Set 1 to lock core0 toomanyexception override configuration register"]
|
||||
#[inline(always)]
|
||||
pub fn core_0_toomanyexceptions_m_override_lock(
|
||||
&self,
|
||||
) -> CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_R {
|
||||
CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_R::new((self.bits & 1) != 0)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_0")
|
||||
.field(
|
||||
"core_0_toomanyexceptions_m_override_lock",
|
||||
&self.core_0_toomanyexceptions_m_override_lock(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bit 0 - Set 1 to lock core0 toomanyexception override configuration register"]
|
||||
#[inline(always)]
|
||||
pub fn core_0_toomanyexceptions_m_override_lock(
|
||||
&mut self,
|
||||
) -> CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_W<CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_0_SPEC>
|
||||
{
|
||||
CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_W::new(self, 0)
|
||||
}
|
||||
}
|
||||
#[doc = "core0 toomanyexception override configuration register 0.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_toomanyexceptions_m_override_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_toomanyexceptions_m_override_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_0_SPEC;
|
||||
impl crate::RegisterSpec for CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_0_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_0_toomanyexceptions_m_override_0::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_0_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_0_toomanyexceptions_m_override_0::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_0_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_0 to value 0"]
|
||||
impl crate::Resettable for CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_0_SPEC {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
@@ -0,0 +1,52 @@
|
||||
#[doc = "Register `CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_1` reader"]
|
||||
pub type R = crate::R<CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_1_SPEC>;
|
||||
#[doc = "Register `CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_1` writer"]
|
||||
pub type W = crate::W<CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_1_SPEC>;
|
||||
#[doc = "Field `CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE` reader - Set 1 to mask toomanyexception."]
|
||||
pub type CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_R = crate::BitReader;
|
||||
#[doc = "Field `CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE` writer - Set 1 to mask toomanyexception."]
|
||||
pub type CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_W<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
impl R {
|
||||
#[doc = "Bit 0 - Set 1 to mask toomanyexception."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_toomanyexceptions_m_override(&self) -> CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_R {
|
||||
CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_R::new((self.bits & 1) != 0)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_1")
|
||||
.field(
|
||||
"core_0_toomanyexceptions_m_override",
|
||||
&self.core_0_toomanyexceptions_m_override(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bit 0 - Set 1 to mask toomanyexception."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_toomanyexceptions_m_override(
|
||||
&mut self,
|
||||
) -> CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_W<CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_1_SPEC> {
|
||||
CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_W::new(self, 0)
|
||||
}
|
||||
}
|
||||
#[doc = "core0 toomanyexception override configuration register 1.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_toomanyexceptions_m_override_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_toomanyexceptions_m_override_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_1_SPEC;
|
||||
impl crate::RegisterSpec for CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_1_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_0_toomanyexceptions_m_override_1::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_1_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_0_toomanyexceptions_m_override_1::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_1_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_1 to value 0x01"]
|
||||
impl crate::Resettable for CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_1_SPEC {
|
||||
const RESET_VALUE: u32 = 0x01;
|
||||
}
|
||||
@@ -0,0 +1,52 @@
|
||||
#[doc = "Register `CORE_0_VECBASE_OVERRIDE_0` reader"]
|
||||
pub type R = crate::R<CORE_0_VECBASE_OVERRIDE_0_SPEC>;
|
||||
#[doc = "Register `CORE_0_VECBASE_OVERRIDE_0` writer"]
|
||||
pub type W = crate::W<CORE_0_VECBASE_OVERRIDE_0_SPEC>;
|
||||
#[doc = "Field `CORE_0_VECBASE_WORLD_MASK` reader - Set 1 to mask world, then only world0_value will work."]
|
||||
pub type CORE_0_VECBASE_WORLD_MASK_R = crate::BitReader;
|
||||
#[doc = "Field `CORE_0_VECBASE_WORLD_MASK` writer - Set 1 to mask world, then only world0_value will work."]
|
||||
pub type CORE_0_VECBASE_WORLD_MASK_W<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
impl R {
|
||||
#[doc = "Bit 0 - Set 1 to mask world, then only world0_value will work."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_vecbase_world_mask(&self) -> CORE_0_VECBASE_WORLD_MASK_R {
|
||||
CORE_0_VECBASE_WORLD_MASK_R::new((self.bits & 1) != 0)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_0_VECBASE_OVERRIDE_0")
|
||||
.field(
|
||||
"core_0_vecbase_world_mask",
|
||||
&self.core_0_vecbase_world_mask(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bit 0 - Set 1 to mask world, then only world0_value will work."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_vecbase_world_mask(
|
||||
&mut self,
|
||||
) -> CORE_0_VECBASE_WORLD_MASK_W<CORE_0_VECBASE_OVERRIDE_0_SPEC> {
|
||||
CORE_0_VECBASE_WORLD_MASK_W::new(self, 0)
|
||||
}
|
||||
}
|
||||
#[doc = "core0 vecbase override configuration register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_vecbase_override_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_vecbase_override_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_0_VECBASE_OVERRIDE_0_SPEC;
|
||||
impl crate::RegisterSpec for CORE_0_VECBASE_OVERRIDE_0_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_0_vecbase_override_0::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_0_VECBASE_OVERRIDE_0_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_0_vecbase_override_0::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_0_VECBASE_OVERRIDE_0_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_0_VECBASE_OVERRIDE_0 to value 0x01"]
|
||||
impl crate::Resettable for CORE_0_VECBASE_OVERRIDE_0_SPEC {
|
||||
const RESET_VALUE: u32 = 0x01;
|
||||
}
|
||||
@@ -0,0 +1,72 @@
|
||||
#[doc = "Register `CORE_0_VECBASE_OVERRIDE_1` reader"]
|
||||
pub type R = crate::R<CORE_0_VECBASE_OVERRIDE_1_SPEC>;
|
||||
#[doc = "Register `CORE_0_VECBASE_OVERRIDE_1` writer"]
|
||||
pub type W = crate::W<CORE_0_VECBASE_OVERRIDE_1_SPEC>;
|
||||
#[doc = "Field `CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE` reader - world0 vecbase_override register, when core0 in world0 use this register to override vecbase register."]
|
||||
pub type CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE_R = crate::FieldReader<u32>;
|
||||
#[doc = "Field `CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE` writer - world0 vecbase_override register, when core0 in world0 use this register to override vecbase register."]
|
||||
pub type CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>;
|
||||
#[doc = "Field `CORE_0_VECBASE_OVERRIDE_SEL` reader - Set 0x3 to sel vecbase_override to override vecbase register."]
|
||||
pub type CORE_0_VECBASE_OVERRIDE_SEL_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_0_VECBASE_OVERRIDE_SEL` writer - Set 0x3 to sel vecbase_override to override vecbase register."]
|
||||
pub type CORE_0_VECBASE_OVERRIDE_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:21 - world0 vecbase_override register, when core0 in world0 use this register to override vecbase register."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_vecbase_override_world0_value(&self) -> CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE_R {
|
||||
CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE_R::new(self.bits & 0x003f_ffff)
|
||||
}
|
||||
#[doc = "Bits 22:23 - Set 0x3 to sel vecbase_override to override vecbase register."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_vecbase_override_sel(&self) -> CORE_0_VECBASE_OVERRIDE_SEL_R {
|
||||
CORE_0_VECBASE_OVERRIDE_SEL_R::new(((self.bits >> 22) & 3) as u8)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_0_VECBASE_OVERRIDE_1")
|
||||
.field(
|
||||
"core_0_vecbase_override_world0_value",
|
||||
&self.core_0_vecbase_override_world0_value(),
|
||||
)
|
||||
.field(
|
||||
"core_0_vecbase_override_sel",
|
||||
&self.core_0_vecbase_override_sel(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:21 - world0 vecbase_override register, when core0 in world0 use this register to override vecbase register."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_vecbase_override_world0_value(
|
||||
&mut self,
|
||||
) -> CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE_W<CORE_0_VECBASE_OVERRIDE_1_SPEC> {
|
||||
CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE_W::new(self, 0)
|
||||
}
|
||||
#[doc = "Bits 22:23 - Set 0x3 to sel vecbase_override to override vecbase register."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_vecbase_override_sel(
|
||||
&mut self,
|
||||
) -> CORE_0_VECBASE_OVERRIDE_SEL_W<CORE_0_VECBASE_OVERRIDE_1_SPEC> {
|
||||
CORE_0_VECBASE_OVERRIDE_SEL_W::new(self, 22)
|
||||
}
|
||||
}
|
||||
#[doc = "core0 vecbase override configuration register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_vecbase_override_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_vecbase_override_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_0_VECBASE_OVERRIDE_1_SPEC;
|
||||
impl crate::RegisterSpec for CORE_0_VECBASE_OVERRIDE_1_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_0_vecbase_override_1::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_0_VECBASE_OVERRIDE_1_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_0_vecbase_override_1::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_0_VECBASE_OVERRIDE_1_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_0_VECBASE_OVERRIDE_1 to value 0"]
|
||||
impl crate::Resettable for CORE_0_VECBASE_OVERRIDE_1_SPEC {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
@@ -0,0 +1,52 @@
|
||||
#[doc = "Register `CORE_0_VECBASE_OVERRIDE_2` reader"]
|
||||
pub type R = crate::R<CORE_0_VECBASE_OVERRIDE_2_SPEC>;
|
||||
#[doc = "Register `CORE_0_VECBASE_OVERRIDE_2` writer"]
|
||||
pub type W = crate::W<CORE_0_VECBASE_OVERRIDE_2_SPEC>;
|
||||
#[doc = "Field `CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE` reader - world1 vecbase_override register, when core0 in world1 use this register to override vecbase register."]
|
||||
pub type CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE_R = crate::FieldReader<u32>;
|
||||
#[doc = "Field `CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE` writer - world1 vecbase_override register, when core0 in world1 use this register to override vecbase register."]
|
||||
pub type CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:21 - world1 vecbase_override register, when core0 in world1 use this register to override vecbase register."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_vecbase_override_world1_value(&self) -> CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE_R {
|
||||
CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE_R::new(self.bits & 0x003f_ffff)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_0_VECBASE_OVERRIDE_2")
|
||||
.field(
|
||||
"core_0_vecbase_override_world1_value",
|
||||
&self.core_0_vecbase_override_world1_value(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:21 - world1 vecbase_override register, when core0 in world1 use this register to override vecbase register."]
|
||||
#[inline(always)]
|
||||
pub fn core_0_vecbase_override_world1_value(
|
||||
&mut self,
|
||||
) -> CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE_W<CORE_0_VECBASE_OVERRIDE_2_SPEC> {
|
||||
CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE_W::new(self, 0)
|
||||
}
|
||||
}
|
||||
#[doc = "core0 vecbase override configuration register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_vecbase_override_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_vecbase_override_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_0_VECBASE_OVERRIDE_2_SPEC;
|
||||
impl crate::RegisterSpec for CORE_0_VECBASE_OVERRIDE_2_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_0_vecbase_override_2::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_0_VECBASE_OVERRIDE_2_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_0_vecbase_override_2::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_0_VECBASE_OVERRIDE_2_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_0_VECBASE_OVERRIDE_2 to value 0"]
|
||||
impl crate::Resettable for CORE_0_VECBASE_OVERRIDE_2_SPEC {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
@@ -0,0 +1,52 @@
|
||||
#[doc = "Register `CORE_0_VECBASE_OVERRIDE_LOCK` reader"]
|
||||
pub type R = crate::R<CORE_0_VECBASE_OVERRIDE_LOCK_SPEC>;
|
||||
#[doc = "Register `CORE_0_VECBASE_OVERRIDE_LOCK` writer"]
|
||||
pub type W = crate::W<CORE_0_VECBASE_OVERRIDE_LOCK_SPEC>;
|
||||
#[doc = "Field `CORE_0_VECBASE_OVERRIDE_LOCK` reader - Set 1 to lock core0 vecbase configuration register"]
|
||||
pub type CORE_0_VECBASE_OVERRIDE_LOCK_R = crate::BitReader;
|
||||
#[doc = "Field `CORE_0_VECBASE_OVERRIDE_LOCK` writer - Set 1 to lock core0 vecbase configuration register"]
|
||||
pub type CORE_0_VECBASE_OVERRIDE_LOCK_W<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
impl R {
|
||||
#[doc = "Bit 0 - Set 1 to lock core0 vecbase configuration register"]
|
||||
#[inline(always)]
|
||||
pub fn core_0_vecbase_override_lock(&self) -> CORE_0_VECBASE_OVERRIDE_LOCK_R {
|
||||
CORE_0_VECBASE_OVERRIDE_LOCK_R::new((self.bits & 1) != 0)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_0_VECBASE_OVERRIDE_LOCK")
|
||||
.field(
|
||||
"core_0_vecbase_override_lock",
|
||||
&self.core_0_vecbase_override_lock(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bit 0 - Set 1 to lock core0 vecbase configuration register"]
|
||||
#[inline(always)]
|
||||
pub fn core_0_vecbase_override_lock(
|
||||
&mut self,
|
||||
) -> CORE_0_VECBASE_OVERRIDE_LOCK_W<CORE_0_VECBASE_OVERRIDE_LOCK_SPEC> {
|
||||
CORE_0_VECBASE_OVERRIDE_LOCK_W::new(self, 0)
|
||||
}
|
||||
}
|
||||
#[doc = "core0 vecbase override configuration register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_vecbase_override_lock::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_vecbase_override_lock::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_0_VECBASE_OVERRIDE_LOCK_SPEC;
|
||||
impl crate::RegisterSpec for CORE_0_VECBASE_OVERRIDE_LOCK_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_0_vecbase_override_lock::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_0_VECBASE_OVERRIDE_LOCK_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_0_vecbase_override_lock::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_0_VECBASE_OVERRIDE_LOCK_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_0_VECBASE_OVERRIDE_LOCK to value 0"]
|
||||
impl crate::Resettable for CORE_0_VECBASE_OVERRIDE_LOCK_SPEC {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
@@ -0,0 +1,52 @@
|
||||
#[doc = "Register `CORE_1_DRAM0_PMS_MONITOR_0` reader"]
|
||||
pub type R = crate::R<CORE_1_DRAM0_PMS_MONITOR_0_SPEC>;
|
||||
#[doc = "Register `CORE_1_DRAM0_PMS_MONITOR_0` writer"]
|
||||
pub type W = crate::W<CORE_1_DRAM0_PMS_MONITOR_0_SPEC>;
|
||||
#[doc = "Field `CORE_1_DRAM0_PMS_MONITOR_LOCK` reader - Set 1 to lock core1 dram0 permission monitor configuration register."]
|
||||
pub type CORE_1_DRAM0_PMS_MONITOR_LOCK_R = crate::BitReader;
|
||||
#[doc = "Field `CORE_1_DRAM0_PMS_MONITOR_LOCK` writer - Set 1 to lock core1 dram0 permission monitor configuration register."]
|
||||
pub type CORE_1_DRAM0_PMS_MONITOR_LOCK_W<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
impl R {
|
||||
#[doc = "Bit 0 - Set 1 to lock core1 dram0 permission monitor configuration register."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_dram0_pms_monitor_lock(&self) -> CORE_1_DRAM0_PMS_MONITOR_LOCK_R {
|
||||
CORE_1_DRAM0_PMS_MONITOR_LOCK_R::new((self.bits & 1) != 0)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_1_DRAM0_PMS_MONITOR_0")
|
||||
.field(
|
||||
"core_1_dram0_pms_monitor_lock",
|
||||
&self.core_1_dram0_pms_monitor_lock(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bit 0 - Set 1 to lock core1 dram0 permission monitor configuration register."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_dram0_pms_monitor_lock(
|
||||
&mut self,
|
||||
) -> CORE_1_DRAM0_PMS_MONITOR_LOCK_W<CORE_1_DRAM0_PMS_MONITOR_0_SPEC> {
|
||||
CORE_1_DRAM0_PMS_MONITOR_LOCK_W::new(self, 0)
|
||||
}
|
||||
}
|
||||
#[doc = "core1 dram0 permission monitor configuration register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_dram0_pms_monitor_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_1_dram0_pms_monitor_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_1_DRAM0_PMS_MONITOR_0_SPEC;
|
||||
impl crate::RegisterSpec for CORE_1_DRAM0_PMS_MONITOR_0_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_1_dram0_pms_monitor_0::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_1_DRAM0_PMS_MONITOR_0_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_1_dram0_pms_monitor_0::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_1_DRAM0_PMS_MONITOR_0_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_1_DRAM0_PMS_MONITOR_0 to value 0"]
|
||||
impl crate::Resettable for CORE_1_DRAM0_PMS_MONITOR_0_SPEC {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
@@ -0,0 +1,72 @@
|
||||
#[doc = "Register `CORE_1_DRAM0_PMS_MONITOR_1` reader"]
|
||||
pub type R = crate::R<CORE_1_DRAM0_PMS_MONITOR_1_SPEC>;
|
||||
#[doc = "Register `CORE_1_DRAM0_PMS_MONITOR_1` writer"]
|
||||
pub type W = crate::W<CORE_1_DRAM0_PMS_MONITOR_1_SPEC>;
|
||||
#[doc = "Field `CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR` reader - Set 1 to clear core1 dram0 permission monior interrupt."]
|
||||
pub type CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR_R = crate::BitReader;
|
||||
#[doc = "Field `CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR` writer - Set 1 to clear core1 dram0 permission monior interrupt."]
|
||||
pub type CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN` reader - Set 1 to enable core1 dram0 permission monitor interrupt."]
|
||||
pub type CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN_R = crate::BitReader;
|
||||
#[doc = "Field `CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN` writer - Set 1 to enable core1 dram0 permission monitor interrupt."]
|
||||
pub type CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
impl R {
|
||||
#[doc = "Bit 0 - Set 1 to clear core1 dram0 permission monior interrupt."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_dram0_pms_monitor_violate_clr(&self) -> CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR_R {
|
||||
CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR_R::new((self.bits & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 1 - Set 1 to enable core1 dram0 permission monitor interrupt."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_dram0_pms_monitor_violate_en(&self) -> CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN_R {
|
||||
CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN_R::new(((self.bits >> 1) & 1) != 0)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_1_DRAM0_PMS_MONITOR_1")
|
||||
.field(
|
||||
"core_1_dram0_pms_monitor_violate_clr",
|
||||
&self.core_1_dram0_pms_monitor_violate_clr(),
|
||||
)
|
||||
.field(
|
||||
"core_1_dram0_pms_monitor_violate_en",
|
||||
&self.core_1_dram0_pms_monitor_violate_en(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bit 0 - Set 1 to clear core1 dram0 permission monior interrupt."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_dram0_pms_monitor_violate_clr(
|
||||
&mut self,
|
||||
) -> CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR_W<CORE_1_DRAM0_PMS_MONITOR_1_SPEC> {
|
||||
CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR_W::new(self, 0)
|
||||
}
|
||||
#[doc = "Bit 1 - Set 1 to enable core1 dram0 permission monitor interrupt."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_dram0_pms_monitor_violate_en(
|
||||
&mut self,
|
||||
) -> CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN_W<CORE_1_DRAM0_PMS_MONITOR_1_SPEC> {
|
||||
CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN_W::new(self, 1)
|
||||
}
|
||||
}
|
||||
#[doc = "core1 dram0 permission monitor configuration register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_dram0_pms_monitor_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_1_dram0_pms_monitor_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_1_DRAM0_PMS_MONITOR_1_SPEC;
|
||||
impl crate::RegisterSpec for CORE_1_DRAM0_PMS_MONITOR_1_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_1_dram0_pms_monitor_1::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_1_DRAM0_PMS_MONITOR_1_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_1_dram0_pms_monitor_1::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_1_DRAM0_PMS_MONITOR_1_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_1_DRAM0_PMS_MONITOR_1 to value 0x03"]
|
||||
impl crate::Resettable for CORE_1_DRAM0_PMS_MONITOR_1_SPEC {
|
||||
const RESET_VALUE: u32 = 0x03;
|
||||
}
|
||||
@@ -0,0 +1,72 @@
|
||||
#[doc = "Register `CORE_1_DRAM0_PMS_MONITOR_2` reader"]
|
||||
pub type R = crate::R<CORE_1_DRAM0_PMS_MONITOR_2_SPEC>;
|
||||
#[doc = "Field `CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR` reader - recorded core1 dram0 permission monitor interrupt status."]
|
||||
pub type CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_R = crate::BitReader;
|
||||
#[doc = "Field `CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK` reader - recorded core1 dram0 lock status, 1 means s32c1i access."]
|
||||
pub type CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_R = crate::BitReader;
|
||||
#[doc = "Field `CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD` reader - recorded core1 dram0 world status, 0x1 means world0, 0x2 means world1."]
|
||||
pub type CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR` reader - recorded core1 dram0 address\\[25:4\\] status when core1 dram0 violated permission,the real address is 0x3c000000+addr*16"]
|
||||
pub type CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_R = crate::FieldReader<u32>;
|
||||
impl R {
|
||||
#[doc = "Bit 0 - recorded core1 dram0 permission monitor interrupt status."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_dram0_pms_monitor_violate_intr(&self) -> CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_R {
|
||||
CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_R::new((self.bits & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 1 - recorded core1 dram0 lock status, 1 means s32c1i access."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_dram0_pms_monitor_violate_status_lock(
|
||||
&self,
|
||||
) -> CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_R {
|
||||
CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_R::new(((self.bits >> 1) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bits 2:3 - recorded core1 dram0 world status, 0x1 means world0, 0x2 means world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_dram0_pms_monitor_violate_status_world(
|
||||
&self,
|
||||
) -> CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_R {
|
||||
CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_R::new(((self.bits >> 2) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 4:25 - recorded core1 dram0 address\\[25:4\\] status when core1 dram0 violated permission,the real address is 0x3c000000+addr*16"]
|
||||
#[inline(always)]
|
||||
pub fn core_1_dram0_pms_monitor_violate_status_addr(
|
||||
&self,
|
||||
) -> CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_R {
|
||||
CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_R::new((self.bits >> 4) & 0x003f_ffff)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_1_DRAM0_PMS_MONITOR_2")
|
||||
.field(
|
||||
"core_1_dram0_pms_monitor_violate_intr",
|
||||
&self.core_1_dram0_pms_monitor_violate_intr(),
|
||||
)
|
||||
.field(
|
||||
"core_1_dram0_pms_monitor_violate_status_lock",
|
||||
&self.core_1_dram0_pms_monitor_violate_status_lock(),
|
||||
)
|
||||
.field(
|
||||
"core_1_dram0_pms_monitor_violate_status_world",
|
||||
&self.core_1_dram0_pms_monitor_violate_status_world(),
|
||||
)
|
||||
.field(
|
||||
"core_1_dram0_pms_monitor_violate_status_addr",
|
||||
&self.core_1_dram0_pms_monitor_violate_status_addr(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
#[doc = "core1 dram0 permission monitor configuration register 2.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_dram0_pms_monitor_2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_1_DRAM0_PMS_MONITOR_2_SPEC;
|
||||
impl crate::RegisterSpec for CORE_1_DRAM0_PMS_MONITOR_2_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_1_dram0_pms_monitor_2::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_1_DRAM0_PMS_MONITOR_2_SPEC {}
|
||||
#[doc = "`reset()` method sets CORE_1_DRAM0_PMS_MONITOR_2 to value 0"]
|
||||
impl crate::Resettable for CORE_1_DRAM0_PMS_MONITOR_2_SPEC {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
@@ -0,0 +1,48 @@
|
||||
#[doc = "Register `CORE_1_DRAM0_PMS_MONITOR_3` reader"]
|
||||
pub type R = crate::R<CORE_1_DRAM0_PMS_MONITOR_3_SPEC>;
|
||||
#[doc = "Field `CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR` reader - recorded core1 dram0 wr status, 1 means store, 0 means load."]
|
||||
pub type CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_R = crate::BitReader;
|
||||
#[doc = "Field `CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN` reader - recorded core1 dram0 byteen status."]
|
||||
pub type CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_R = crate::FieldReader<u16>;
|
||||
impl R {
|
||||
#[doc = "Bit 0 - recorded core1 dram0 wr status, 1 means store, 0 means load."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_dram0_pms_monitor_violate_status_wr(
|
||||
&self,
|
||||
) -> CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_R {
|
||||
CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_R::new((self.bits & 1) != 0)
|
||||
}
|
||||
#[doc = "Bits 1:16 - recorded core1 dram0 byteen status."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_dram0_pms_monitor_violate_status_byteen(
|
||||
&self,
|
||||
) -> CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_R {
|
||||
CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_R::new(((self.bits >> 1) & 0xffff) as u16)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_1_DRAM0_PMS_MONITOR_3")
|
||||
.field(
|
||||
"core_1_dram0_pms_monitor_violate_status_wr",
|
||||
&self.core_1_dram0_pms_monitor_violate_status_wr(),
|
||||
)
|
||||
.field(
|
||||
"core_1_dram0_pms_monitor_violate_status_byteen",
|
||||
&self.core_1_dram0_pms_monitor_violate_status_byteen(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
#[doc = "core1 dram0 permission monitor configuration register 3.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_dram0_pms_monitor_3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_1_DRAM0_PMS_MONITOR_3_SPEC;
|
||||
impl crate::RegisterSpec for CORE_1_DRAM0_PMS_MONITOR_3_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_1_dram0_pms_monitor_3::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_1_DRAM0_PMS_MONITOR_3_SPEC {}
|
||||
#[doc = "`reset()` method sets CORE_1_DRAM0_PMS_MONITOR_3 to value 0"]
|
||||
impl crate::Resettable for CORE_1_DRAM0_PMS_MONITOR_3_SPEC {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
@@ -0,0 +1,52 @@
|
||||
#[doc = "Register `CORE_1_IRAM0_PMS_MONITOR_0` reader"]
|
||||
pub type R = crate::R<CORE_1_IRAM0_PMS_MONITOR_0_SPEC>;
|
||||
#[doc = "Register `CORE_1_IRAM0_PMS_MONITOR_0` writer"]
|
||||
pub type W = crate::W<CORE_1_IRAM0_PMS_MONITOR_0_SPEC>;
|
||||
#[doc = "Field `CORE_1_IRAM0_PMS_MONITOR_LOCK` reader - Set 1 to lock core1 iram0 permission monitor register"]
|
||||
pub type CORE_1_IRAM0_PMS_MONITOR_LOCK_R = crate::BitReader;
|
||||
#[doc = "Field `CORE_1_IRAM0_PMS_MONITOR_LOCK` writer - Set 1 to lock core1 iram0 permission monitor register"]
|
||||
pub type CORE_1_IRAM0_PMS_MONITOR_LOCK_W<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
impl R {
|
||||
#[doc = "Bit 0 - Set 1 to lock core1 iram0 permission monitor register"]
|
||||
#[inline(always)]
|
||||
pub fn core_1_iram0_pms_monitor_lock(&self) -> CORE_1_IRAM0_PMS_MONITOR_LOCK_R {
|
||||
CORE_1_IRAM0_PMS_MONITOR_LOCK_R::new((self.bits & 1) != 0)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_1_IRAM0_PMS_MONITOR_0")
|
||||
.field(
|
||||
"core_1_iram0_pms_monitor_lock",
|
||||
&self.core_1_iram0_pms_monitor_lock(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bit 0 - Set 1 to lock core1 iram0 permission monitor register"]
|
||||
#[inline(always)]
|
||||
pub fn core_1_iram0_pms_monitor_lock(
|
||||
&mut self,
|
||||
) -> CORE_1_IRAM0_PMS_MONITOR_LOCK_W<CORE_1_IRAM0_PMS_MONITOR_0_SPEC> {
|
||||
CORE_1_IRAM0_PMS_MONITOR_LOCK_W::new(self, 0)
|
||||
}
|
||||
}
|
||||
#[doc = "core1 iram0 permission monitor configuration register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_iram0_pms_monitor_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_1_iram0_pms_monitor_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_1_IRAM0_PMS_MONITOR_0_SPEC;
|
||||
impl crate::RegisterSpec for CORE_1_IRAM0_PMS_MONITOR_0_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_1_iram0_pms_monitor_0::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_1_IRAM0_PMS_MONITOR_0_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_1_iram0_pms_monitor_0::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_1_IRAM0_PMS_MONITOR_0_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_1_IRAM0_PMS_MONITOR_0 to value 0"]
|
||||
impl crate::Resettable for CORE_1_IRAM0_PMS_MONITOR_0_SPEC {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
@@ -0,0 +1,72 @@
|
||||
#[doc = "Register `CORE_1_IRAM0_PMS_MONITOR_1` reader"]
|
||||
pub type R = crate::R<CORE_1_IRAM0_PMS_MONITOR_1_SPEC>;
|
||||
#[doc = "Register `CORE_1_IRAM0_PMS_MONITOR_1` writer"]
|
||||
pub type W = crate::W<CORE_1_IRAM0_PMS_MONITOR_1_SPEC>;
|
||||
#[doc = "Field `CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR` reader - Set 1 to clear core1 iram0 permission violated interrupt"]
|
||||
pub type CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR_R = crate::BitReader;
|
||||
#[doc = "Field `CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR` writer - Set 1 to clear core1 iram0 permission violated interrupt"]
|
||||
pub type CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN` reader - Set 1 to enable core1 iram0 permission monitor, when core1_iram violated permission, will trigger interrupt"]
|
||||
pub type CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN_R = crate::BitReader;
|
||||
#[doc = "Field `CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN` writer - Set 1 to enable core1 iram0 permission monitor, when core1_iram violated permission, will trigger interrupt"]
|
||||
pub type CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
impl R {
|
||||
#[doc = "Bit 0 - Set 1 to clear core1 iram0 permission violated interrupt"]
|
||||
#[inline(always)]
|
||||
pub fn core_1_iram0_pms_monitor_violate_clr(&self) -> CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR_R {
|
||||
CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR_R::new((self.bits & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 1 - Set 1 to enable core1 iram0 permission monitor, when core1_iram violated permission, will trigger interrupt"]
|
||||
#[inline(always)]
|
||||
pub fn core_1_iram0_pms_monitor_violate_en(&self) -> CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN_R {
|
||||
CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN_R::new(((self.bits >> 1) & 1) != 0)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_1_IRAM0_PMS_MONITOR_1")
|
||||
.field(
|
||||
"core_1_iram0_pms_monitor_violate_clr",
|
||||
&self.core_1_iram0_pms_monitor_violate_clr(),
|
||||
)
|
||||
.field(
|
||||
"core_1_iram0_pms_monitor_violate_en",
|
||||
&self.core_1_iram0_pms_monitor_violate_en(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bit 0 - Set 1 to clear core1 iram0 permission violated interrupt"]
|
||||
#[inline(always)]
|
||||
pub fn core_1_iram0_pms_monitor_violate_clr(
|
||||
&mut self,
|
||||
) -> CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR_W<CORE_1_IRAM0_PMS_MONITOR_1_SPEC> {
|
||||
CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR_W::new(self, 0)
|
||||
}
|
||||
#[doc = "Bit 1 - Set 1 to enable core1 iram0 permission monitor, when core1_iram violated permission, will trigger interrupt"]
|
||||
#[inline(always)]
|
||||
pub fn core_1_iram0_pms_monitor_violate_en(
|
||||
&mut self,
|
||||
) -> CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN_W<CORE_1_IRAM0_PMS_MONITOR_1_SPEC> {
|
||||
CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN_W::new(self, 1)
|
||||
}
|
||||
}
|
||||
#[doc = "core1 iram0 permission monitor configuration register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_iram0_pms_monitor_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_1_iram0_pms_monitor_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_1_IRAM0_PMS_MONITOR_1_SPEC;
|
||||
impl crate::RegisterSpec for CORE_1_IRAM0_PMS_MONITOR_1_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_1_iram0_pms_monitor_1::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_1_IRAM0_PMS_MONITOR_1_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_1_iram0_pms_monitor_1::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_1_IRAM0_PMS_MONITOR_1_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_1_IRAM0_PMS_MONITOR_1 to value 0x03"]
|
||||
impl crate::Resettable for CORE_1_IRAM0_PMS_MONITOR_1_SPEC {
|
||||
const RESET_VALUE: u32 = 0x03;
|
||||
}
|
||||
@@ -0,0 +1,85 @@
|
||||
#[doc = "Register `CORE_1_IRAM0_PMS_MONITOR_2` reader"]
|
||||
pub type R = crate::R<CORE_1_IRAM0_PMS_MONITOR_2_SPEC>;
|
||||
#[doc = "Field `CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR` reader - recorded core1 iram0 pms monitor interrupt status."]
|
||||
pub type CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_R = crate::BitReader;
|
||||
#[doc = "Field `CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR` reader - recorded core1 iram0 wr status, only if loadstore is 1 have meaning, 1(store), 0(load)."]
|
||||
pub type CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_R = crate::BitReader;
|
||||
#[doc = "Field `CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE` reader - recorded core1 iram0 loadstore status, indicated the type of operation, 0(fetch), 1(load/store)."]
|
||||
pub type CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_R = crate::BitReader;
|
||||
#[doc = "Field `CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD` reader - recorded core1 iram0 world status, 0x01 means world0, 0x10 means world1."]
|
||||
pub type CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR` reader - recorded core1 iram0 address \\[25:2\\] status when core1 iram0 violated permission, the real address is 0x40000000+addr*4"]
|
||||
pub type CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_R = crate::FieldReader<u32>;
|
||||
impl R {
|
||||
#[doc = "Bit 0 - recorded core1 iram0 pms monitor interrupt status."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_iram0_pms_monitor_violate_intr(&self) -> CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_R {
|
||||
CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_R::new((self.bits & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 1 - recorded core1 iram0 wr status, only if loadstore is 1 have meaning, 1(store), 0(load)."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_iram0_pms_monitor_violate_status_wr(
|
||||
&self,
|
||||
) -> CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_R {
|
||||
CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_R::new(((self.bits >> 1) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 2 - recorded core1 iram0 loadstore status, indicated the type of operation, 0(fetch), 1(load/store)."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_iram0_pms_monitor_violate_status_loadstore(
|
||||
&self,
|
||||
) -> CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_R {
|
||||
CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_R::new(((self.bits >> 2) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bits 3:4 - recorded core1 iram0 world status, 0x01 means world0, 0x10 means world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_iram0_pms_monitor_violate_status_world(
|
||||
&self,
|
||||
) -> CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_R {
|
||||
CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_R::new(((self.bits >> 3) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 5:28 - recorded core1 iram0 address \\[25:2\\] status when core1 iram0 violated permission, the real address is 0x40000000+addr*4"]
|
||||
#[inline(always)]
|
||||
pub fn core_1_iram0_pms_monitor_violate_status_addr(
|
||||
&self,
|
||||
) -> CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_R {
|
||||
CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_R::new((self.bits >> 5) & 0x00ff_ffff)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_1_IRAM0_PMS_MONITOR_2")
|
||||
.field(
|
||||
"core_1_iram0_pms_monitor_violate_intr",
|
||||
&self.core_1_iram0_pms_monitor_violate_intr(),
|
||||
)
|
||||
.field(
|
||||
"core_1_iram0_pms_monitor_violate_status_wr",
|
||||
&self.core_1_iram0_pms_monitor_violate_status_wr(),
|
||||
)
|
||||
.field(
|
||||
"core_1_iram0_pms_monitor_violate_status_loadstore",
|
||||
&self.core_1_iram0_pms_monitor_violate_status_loadstore(),
|
||||
)
|
||||
.field(
|
||||
"core_1_iram0_pms_monitor_violate_status_world",
|
||||
&self.core_1_iram0_pms_monitor_violate_status_world(),
|
||||
)
|
||||
.field(
|
||||
"core_1_iram0_pms_monitor_violate_status_addr",
|
||||
&self.core_1_iram0_pms_monitor_violate_status_addr(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
#[doc = "core1 iram0 permission monitor configuration register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_iram0_pms_monitor_2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_1_IRAM0_PMS_MONITOR_2_SPEC;
|
||||
impl crate::RegisterSpec for CORE_1_IRAM0_PMS_MONITOR_2_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_1_iram0_pms_monitor_2::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_1_IRAM0_PMS_MONITOR_2_SPEC {}
|
||||
#[doc = "`reset()` method sets CORE_1_IRAM0_PMS_MONITOR_2 to value 0"]
|
||||
impl crate::Resettable for CORE_1_IRAM0_PMS_MONITOR_2_SPEC {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
@@ -0,0 +1,52 @@
|
||||
#[doc = "Register `CORE_1_PIF_PMS_CONSTRAIN_0` reader"]
|
||||
pub type R = crate::R<CORE_1_PIF_PMS_CONSTRAIN_0_SPEC>;
|
||||
#[doc = "Register `CORE_1_PIF_PMS_CONSTRAIN_0` writer"]
|
||||
pub type W = crate::W<CORE_1_PIF_PMS_CONSTRAIN_0_SPEC>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_LOCK` reader - Set 1 to lock core1 pif permission configuration register."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_LOCK_R = crate::BitReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_LOCK` writer - Set 1 to lock core1 pif permission configuration register."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_LOCK_W<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
impl R {
|
||||
#[doc = "Bit 0 - Set 1 to lock core1 pif permission configuration register."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_lock(&self) -> CORE_1_PIF_PMS_CONSTRAIN_LOCK_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_LOCK_R::new((self.bits & 1) != 0)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_1_PIF_PMS_CONSTRAIN_0")
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_lock",
|
||||
&self.core_1_pif_pms_constrain_lock(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bit 0 - Set 1 to lock core1 pif permission configuration register."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_lock(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_LOCK_W<CORE_1_PIF_PMS_CONSTRAIN_0_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_LOCK_W::new(self, 0)
|
||||
}
|
||||
}
|
||||
#[doc = "Core1 access peripherals permission configuration register 0.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_pif_pms_constrain_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_1_pif_pms_constrain_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_1_PIF_PMS_CONSTRAIN_0_SPEC;
|
||||
impl crate::RegisterSpec for CORE_1_PIF_PMS_CONSTRAIN_0_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_1_pif_pms_constrain_0::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_1_PIF_PMS_CONSTRAIN_0_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_1_pif_pms_constrain_0::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_1_PIF_PMS_CONSTRAIN_0_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_1_PIF_PMS_CONSTRAIN_0 to value 0"]
|
||||
impl crate::Resettable for CORE_1_PIF_PMS_CONSTRAIN_0_SPEC {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
@@ -0,0 +1,300 @@
|
||||
#[doc = "Register `CORE_1_PIF_PMS_CONSTRAIN_1` reader"]
|
||||
pub type R = crate::R<CORE_1_PIF_PMS_CONSTRAIN_1_SPEC>;
|
||||
#[doc = "Register `CORE_1_PIF_PMS_CONSTRAIN_1` writer"]
|
||||
pub type W = crate::W<CORE_1_PIF_PMS_CONSTRAIN_1_SPEC>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART` reader - Core1 access uart permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART` writer - Core1 access uart permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1` reader - Core1 access g0spi_1 permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1` writer - Core1 access g0spi_1 permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0` reader - Core1 access g0spi_0 permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0` writer - Core1 access g0spi_0 permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO` reader - Core1 access gpio permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO` writer - Core1 access gpio permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2` reader - Core1 access fe2 permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2` writer - Core1 access fe2 permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE` reader - Core1 access fe permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE` writer - Core1 access fe permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC` reader - Core1 access rtc permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC` writer - Core1 access rtc permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX` reader - Core1 access io_mux permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX` writer - Core1 access io_mux permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF` reader - Core1 access hinf permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF` writer - Core1 access hinf permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC` reader - Core1 access misc permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC` writer - Core1 access misc permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C` reader - Core1 access i2c permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C` writer - Core1 access i2c permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0` reader - Core1 access i2s0 permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0` writer - Core1 access i2s0 permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1` reader - Core1 access uart1 permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1` writer - Core1 access uart1 permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:1 - Core1 access uart permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_uart(&self) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART_R::new((self.bits & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 2:3 - Core1 access g0spi_1 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_g0spi_1(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_R::new(((self.bits >> 2) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 4:5 - Core1 access g0spi_0 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_g0spi_0(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_R::new(((self.bits >> 4) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 6:7 - Core1 access gpio permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_gpio(&self) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_R::new(((self.bits >> 6) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 8:9 - Core1 access fe2 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_fe2(&self) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2_R::new(((self.bits >> 8) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 10:11 - Core1 access fe permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_fe(&self) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE_R::new(((self.bits >> 10) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 14:15 - Core1 access rtc permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_rtc(&self) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_R::new(((self.bits >> 14) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 16:17 - Core1 access io_mux permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_io_mux(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_R::new(((self.bits >> 16) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 20:21 - Core1 access hinf permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_hinf(&self) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF_R::new(((self.bits >> 20) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 24:25 - Core1 access misc permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_misc(&self) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC_R::new(((self.bits >> 24) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 26:27 - Core1 access i2c permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_i2c(&self) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_R::new(((self.bits >> 26) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 28:29 - Core1 access i2s0 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_i2s0(&self) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_R::new(((self.bits >> 28) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 30:31 - Core1 access uart1 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_uart1(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1_R::new(((self.bits >> 30) & 3) as u8)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_1_PIF_PMS_CONSTRAIN_1")
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_0_uart",
|
||||
&self.core_1_pif_pms_constrain_world_0_uart(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_0_g0spi_1",
|
||||
&self.core_1_pif_pms_constrain_world_0_g0spi_1(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_0_g0spi_0",
|
||||
&self.core_1_pif_pms_constrain_world_0_g0spi_0(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_0_gpio",
|
||||
&self.core_1_pif_pms_constrain_world_0_gpio(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_0_fe2",
|
||||
&self.core_1_pif_pms_constrain_world_0_fe2(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_0_fe",
|
||||
&self.core_1_pif_pms_constrain_world_0_fe(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_0_rtc",
|
||||
&self.core_1_pif_pms_constrain_world_0_rtc(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_0_io_mux",
|
||||
&self.core_1_pif_pms_constrain_world_0_io_mux(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_0_hinf",
|
||||
&self.core_1_pif_pms_constrain_world_0_hinf(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_0_misc",
|
||||
&self.core_1_pif_pms_constrain_world_0_misc(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_0_i2c",
|
||||
&self.core_1_pif_pms_constrain_world_0_i2c(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_0_i2s0",
|
||||
&self.core_1_pif_pms_constrain_world_0_i2s0(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_0_uart1",
|
||||
&self.core_1_pif_pms_constrain_world_0_uart1(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:1 - Core1 access uart permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_uart(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART_W<CORE_1_PIF_PMS_CONSTRAIN_1_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART_W::new(self, 0)
|
||||
}
|
||||
#[doc = "Bits 2:3 - Core1 access g0spi_1 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_g0spi_1(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_W<CORE_1_PIF_PMS_CONSTRAIN_1_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_W::new(self, 2)
|
||||
}
|
||||
#[doc = "Bits 4:5 - Core1 access g0spi_0 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_g0spi_0(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_W<CORE_1_PIF_PMS_CONSTRAIN_1_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_W::new(self, 4)
|
||||
}
|
||||
#[doc = "Bits 6:7 - Core1 access gpio permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_gpio(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_W<CORE_1_PIF_PMS_CONSTRAIN_1_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_W::new(self, 6)
|
||||
}
|
||||
#[doc = "Bits 8:9 - Core1 access fe2 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_fe2(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2_W<CORE_1_PIF_PMS_CONSTRAIN_1_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2_W::new(self, 8)
|
||||
}
|
||||
#[doc = "Bits 10:11 - Core1 access fe permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_fe(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE_W<CORE_1_PIF_PMS_CONSTRAIN_1_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE_W::new(self, 10)
|
||||
}
|
||||
#[doc = "Bits 14:15 - Core1 access rtc permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_rtc(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_W<CORE_1_PIF_PMS_CONSTRAIN_1_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_W::new(self, 14)
|
||||
}
|
||||
#[doc = "Bits 16:17 - Core1 access io_mux permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_io_mux(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_W<CORE_1_PIF_PMS_CONSTRAIN_1_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_W::new(self, 16)
|
||||
}
|
||||
#[doc = "Bits 20:21 - Core1 access hinf permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_hinf(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF_W<CORE_1_PIF_PMS_CONSTRAIN_1_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF_W::new(self, 20)
|
||||
}
|
||||
#[doc = "Bits 24:25 - Core1 access misc permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_misc(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC_W<CORE_1_PIF_PMS_CONSTRAIN_1_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC_W::new(self, 24)
|
||||
}
|
||||
#[doc = "Bits 26:27 - Core1 access i2c permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_i2c(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_W<CORE_1_PIF_PMS_CONSTRAIN_1_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_W::new(self, 26)
|
||||
}
|
||||
#[doc = "Bits 28:29 - Core1 access i2s0 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_i2s0(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_W<CORE_1_PIF_PMS_CONSTRAIN_1_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_W::new(self, 28)
|
||||
}
|
||||
#[doc = "Bits 30:31 - Core1 access uart1 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_uart1(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1_W<CORE_1_PIF_PMS_CONSTRAIN_1_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1_W::new(self, 30)
|
||||
}
|
||||
}
|
||||
#[doc = "Core1 access peripherals permission configuration register 1.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_pif_pms_constrain_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_1_pif_pms_constrain_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_1_PIF_PMS_CONSTRAIN_1_SPEC;
|
||||
impl crate::RegisterSpec for CORE_1_PIF_PMS_CONSTRAIN_1_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_1_pif_pms_constrain_1::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_1_PIF_PMS_CONSTRAIN_1_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_1_pif_pms_constrain_1::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_1_PIF_PMS_CONSTRAIN_1_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_1_PIF_PMS_CONSTRAIN_1 to value 0xff33_cfff"]
|
||||
impl crate::Resettable for CORE_1_PIF_PMS_CONSTRAIN_1_SPEC {
|
||||
const RESET_VALUE: u32 = 0xff33_cfff;
|
||||
}
|
||||
@@ -0,0 +1,120 @@
|
||||
#[doc = "Register `CORE_1_PIF_PMS_CONSTRAIN_10` reader"]
|
||||
pub type R = crate::R<CORE_1_PIF_PMS_CONSTRAIN_10_SPEC>;
|
||||
#[doc = "Register `CORE_1_PIF_PMS_CONSTRAIN_10` writer"]
|
||||
pub type W = crate::W<CORE_1_PIF_PMS_CONSTRAIN_10_SPEC>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L` reader - RTCFast memory low region permission in world 0 for core1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L` writer - RTCFast memory low region permission in world 0 for core1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H` reader - RTCFast memory high region permission in world 0 for core1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H` writer - RTCFast memory high region permission in world 0 for core1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L` reader - RTCFast memory low region permission in world 1 for core1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L` writer - RTCFast memory low region permission in world 1 for core1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H` reader - RTCFast memory high region permission in world 1 for core1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H` writer - RTCFast memory high region permission in world 1 for core1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:2 - RTCFast memory low region permission in world 0 for core1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_rtcfast_world_0_l(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_R::new((self.bits & 7) as u8)
|
||||
}
|
||||
#[doc = "Bits 3:5 - RTCFast memory high region permission in world 0 for core1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_rtcfast_world_0_h(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_R::new(((self.bits >> 3) & 7) as u8)
|
||||
}
|
||||
#[doc = "Bits 6:8 - RTCFast memory low region permission in world 1 for core1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_rtcfast_world_1_l(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_R::new(((self.bits >> 6) & 7) as u8)
|
||||
}
|
||||
#[doc = "Bits 9:11 - RTCFast memory high region permission in world 1 for core1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_rtcfast_world_1_h(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_R::new(((self.bits >> 9) & 7) as u8)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_1_PIF_PMS_CONSTRAIN_10")
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_rtcfast_world_0_l",
|
||||
&self.core_1_pif_pms_constrain_rtcfast_world_0_l(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_rtcfast_world_0_h",
|
||||
&self.core_1_pif_pms_constrain_rtcfast_world_0_h(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_rtcfast_world_1_l",
|
||||
&self.core_1_pif_pms_constrain_rtcfast_world_1_l(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_rtcfast_world_1_h",
|
||||
&self.core_1_pif_pms_constrain_rtcfast_world_1_h(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:2 - RTCFast memory low region permission in world 0 for core1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_rtcfast_world_0_l(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_W<CORE_1_PIF_PMS_CONSTRAIN_10_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_W::new(self, 0)
|
||||
}
|
||||
#[doc = "Bits 3:5 - RTCFast memory high region permission in world 0 for core1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_rtcfast_world_0_h(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_W<CORE_1_PIF_PMS_CONSTRAIN_10_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_W::new(self, 3)
|
||||
}
|
||||
#[doc = "Bits 6:8 - RTCFast memory low region permission in world 1 for core1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_rtcfast_world_1_l(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_W<CORE_1_PIF_PMS_CONSTRAIN_10_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_W::new(self, 6)
|
||||
}
|
||||
#[doc = "Bits 9:11 - RTCFast memory high region permission in world 1 for core1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_rtcfast_world_1_h(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_W<CORE_1_PIF_PMS_CONSTRAIN_10_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_W::new(self, 9)
|
||||
}
|
||||
}
|
||||
#[doc = "core1 access peripherals permission configuration register 10.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_pif_pms_constrain_10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_1_pif_pms_constrain_10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_1_PIF_PMS_CONSTRAIN_10_SPEC;
|
||||
impl crate::RegisterSpec for CORE_1_PIF_PMS_CONSTRAIN_10_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_1_pif_pms_constrain_10::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_1_PIF_PMS_CONSTRAIN_10_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_1_pif_pms_constrain_10::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_1_PIF_PMS_CONSTRAIN_10_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_1_PIF_PMS_CONSTRAIN_10 to value 0x0fff"]
|
||||
impl crate::Resettable for CORE_1_PIF_PMS_CONSTRAIN_10_SPEC {
|
||||
const RESET_VALUE: u32 = 0x0fff;
|
||||
}
|
||||
@@ -0,0 +1,82 @@
|
||||
#[doc = "Register `CORE_1_PIF_PMS_CONSTRAIN_11` reader"]
|
||||
pub type R = crate::R<CORE_1_PIF_PMS_CONSTRAIN_11_SPEC>;
|
||||
#[doc = "Register `CORE_1_PIF_PMS_CONSTRAIN_11` writer"]
|
||||
pub type W = crate::W<CORE_1_PIF_PMS_CONSTRAIN_11_SPEC>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0` reader - RTCSlow_0 memory split address in world 0 for core1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_R = crate::FieldReader<u16>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0` writer - RTCSlow_0 memory split address in world 0 for core1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_W<'a, REG> =
|
||||
crate::FieldWriter<'a, REG, 11, u16>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1` reader - RTCSlow_0 memory split address in world 1 for core1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_R = crate::FieldReader<u16>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1` writer - RTCSlow_0 memory split address in world 1 for core1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_W<'a, REG> =
|
||||
crate::FieldWriter<'a, REG, 11, u16>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:10 - RTCSlow_0 memory split address in world 0 for core1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_rtcslow_0_spltaddr_world_0(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_R::new((self.bits & 0x07ff) as u16)
|
||||
}
|
||||
#[doc = "Bits 11:21 - RTCSlow_0 memory split address in world 1 for core1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_rtcslow_0_spltaddr_world_1(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_R::new(
|
||||
((self.bits >> 11) & 0x07ff) as u16,
|
||||
)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_1_PIF_PMS_CONSTRAIN_11")
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_rtcslow_0_spltaddr_world_0",
|
||||
&self.core_1_pif_pms_constrain_rtcslow_0_spltaddr_world_0(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_rtcslow_0_spltaddr_world_1",
|
||||
&self.core_1_pif_pms_constrain_rtcslow_0_spltaddr_world_1(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:10 - RTCSlow_0 memory split address in world 0 for core1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_rtcslow_0_spltaddr_world_0(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_W<CORE_1_PIF_PMS_CONSTRAIN_11_SPEC>
|
||||
{
|
||||
CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_W::new(self, 0)
|
||||
}
|
||||
#[doc = "Bits 11:21 - RTCSlow_0 memory split address in world 1 for core1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_rtcslow_0_spltaddr_world_1(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_W<CORE_1_PIF_PMS_CONSTRAIN_11_SPEC>
|
||||
{
|
||||
CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_W::new(self, 11)
|
||||
}
|
||||
}
|
||||
#[doc = "core1 access peripherals permission configuration register 11.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_pif_pms_constrain_11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_1_pif_pms_constrain_11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_1_PIF_PMS_CONSTRAIN_11_SPEC;
|
||||
impl crate::RegisterSpec for CORE_1_PIF_PMS_CONSTRAIN_11_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_1_pif_pms_constrain_11::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_1_PIF_PMS_CONSTRAIN_11_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_1_pif_pms_constrain_11::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_1_PIF_PMS_CONSTRAIN_11_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_1_PIF_PMS_CONSTRAIN_11 to value 0x003f_ffff"]
|
||||
impl crate::Resettable for CORE_1_PIF_PMS_CONSTRAIN_11_SPEC {
|
||||
const RESET_VALUE: u32 = 0x003f_ffff;
|
||||
}
|
||||
@@ -0,0 +1,120 @@
|
||||
#[doc = "Register `CORE_1_PIF_PMS_CONSTRAIN_12` reader"]
|
||||
pub type R = crate::R<CORE_1_PIF_PMS_CONSTRAIN_12_SPEC>;
|
||||
#[doc = "Register `CORE_1_PIF_PMS_CONSTRAIN_12` writer"]
|
||||
pub type W = crate::W<CORE_1_PIF_PMS_CONSTRAIN_12_SPEC>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L` reader - RTCSlow_0 memory low region permission in world 0 for core1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L` writer - RTCSlow_0 memory low region permission in world 0 for core1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H` reader - RTCSlow_0 memory high region permission in world 0 for core1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H` writer - RTCSlow_0 memory high region permission in world 0 for core1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L` reader - RTCSlow_0 memory low region permission in world 1 for core1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L` writer - RTCSlow_0 memory low region permission in world 1 for core1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H` reader - RTCSlow_0 memory high region permission in world 1 for core1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H` writer - RTCSlow_0 memory high region permission in world 1 for core1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:2 - RTCSlow_0 memory low region permission in world 0 for core1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_rtcslow_0_world_0_l(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_R::new((self.bits & 7) as u8)
|
||||
}
|
||||
#[doc = "Bits 3:5 - RTCSlow_0 memory high region permission in world 0 for core1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_rtcslow_0_world_0_h(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_R::new(((self.bits >> 3) & 7) as u8)
|
||||
}
|
||||
#[doc = "Bits 6:8 - RTCSlow_0 memory low region permission in world 1 for core1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_rtcslow_0_world_1_l(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_R::new(((self.bits >> 6) & 7) as u8)
|
||||
}
|
||||
#[doc = "Bits 9:11 - RTCSlow_0 memory high region permission in world 1 for core1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_rtcslow_0_world_1_h(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_R::new(((self.bits >> 9) & 7) as u8)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_1_PIF_PMS_CONSTRAIN_12")
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_rtcslow_0_world_0_l",
|
||||
&self.core_1_pif_pms_constrain_rtcslow_0_world_0_l(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_rtcslow_0_world_0_h",
|
||||
&self.core_1_pif_pms_constrain_rtcslow_0_world_0_h(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_rtcslow_0_world_1_l",
|
||||
&self.core_1_pif_pms_constrain_rtcslow_0_world_1_l(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_rtcslow_0_world_1_h",
|
||||
&self.core_1_pif_pms_constrain_rtcslow_0_world_1_h(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:2 - RTCSlow_0 memory low region permission in world 0 for core1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_rtcslow_0_world_0_l(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_W<CORE_1_PIF_PMS_CONSTRAIN_12_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_W::new(self, 0)
|
||||
}
|
||||
#[doc = "Bits 3:5 - RTCSlow_0 memory high region permission in world 0 for core1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_rtcslow_0_world_0_h(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_W<CORE_1_PIF_PMS_CONSTRAIN_12_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_W::new(self, 3)
|
||||
}
|
||||
#[doc = "Bits 6:8 - RTCSlow_0 memory low region permission in world 1 for core1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_rtcslow_0_world_1_l(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_W<CORE_1_PIF_PMS_CONSTRAIN_12_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_W::new(self, 6)
|
||||
}
|
||||
#[doc = "Bits 9:11 - RTCSlow_0 memory high region permission in world 1 for core1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_rtcslow_0_world_1_h(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_W<CORE_1_PIF_PMS_CONSTRAIN_12_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_W::new(self, 9)
|
||||
}
|
||||
}
|
||||
#[doc = "core1 access peripherals permission configuration register 12.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_pif_pms_constrain_12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_1_pif_pms_constrain_12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_1_PIF_PMS_CONSTRAIN_12_SPEC;
|
||||
impl crate::RegisterSpec for CORE_1_PIF_PMS_CONSTRAIN_12_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_1_pif_pms_constrain_12::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_1_PIF_PMS_CONSTRAIN_12_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_1_pif_pms_constrain_12::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_1_PIF_PMS_CONSTRAIN_12_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_1_PIF_PMS_CONSTRAIN_12 to value 0x0fff"]
|
||||
impl crate::Resettable for CORE_1_PIF_PMS_CONSTRAIN_12_SPEC {
|
||||
const RESET_VALUE: u32 = 0x0fff;
|
||||
}
|
||||
@@ -0,0 +1,82 @@
|
||||
#[doc = "Register `CORE_1_PIF_PMS_CONSTRAIN_13` reader"]
|
||||
pub type R = crate::R<CORE_1_PIF_PMS_CONSTRAIN_13_SPEC>;
|
||||
#[doc = "Register `CORE_1_PIF_PMS_CONSTRAIN_13` writer"]
|
||||
pub type W = crate::W<CORE_1_PIF_PMS_CONSTRAIN_13_SPEC>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0` reader - RTCSlow_1 memory split address in world 0 for core1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_R = crate::FieldReader<u16>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0` writer - RTCSlow_1 memory split address in world 0 for core1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_W<'a, REG> =
|
||||
crate::FieldWriter<'a, REG, 11, u16>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1` reader - RTCSlow_1 memory split address in world 1 for core1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_R = crate::FieldReader<u16>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1` writer - RTCSlow_1 memory split address in world 1 for core1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_W<'a, REG> =
|
||||
crate::FieldWriter<'a, REG, 11, u16>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:10 - RTCSlow_1 memory split address in world 0 for core1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_rtcslow_1_spltaddr_world_0(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_R::new((self.bits & 0x07ff) as u16)
|
||||
}
|
||||
#[doc = "Bits 11:21 - RTCSlow_1 memory split address in world 1 for core1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_rtcslow_1_spltaddr_world_1(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_R::new(
|
||||
((self.bits >> 11) & 0x07ff) as u16,
|
||||
)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_1_PIF_PMS_CONSTRAIN_13")
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_rtcslow_1_spltaddr_world_0",
|
||||
&self.core_1_pif_pms_constrain_rtcslow_1_spltaddr_world_0(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_rtcslow_1_spltaddr_world_1",
|
||||
&self.core_1_pif_pms_constrain_rtcslow_1_spltaddr_world_1(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:10 - RTCSlow_1 memory split address in world 0 for core1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_rtcslow_1_spltaddr_world_0(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_W<CORE_1_PIF_PMS_CONSTRAIN_13_SPEC>
|
||||
{
|
||||
CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_W::new(self, 0)
|
||||
}
|
||||
#[doc = "Bits 11:21 - RTCSlow_1 memory split address in world 1 for core1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_rtcslow_1_spltaddr_world_1(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_W<CORE_1_PIF_PMS_CONSTRAIN_13_SPEC>
|
||||
{
|
||||
CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_W::new(self, 11)
|
||||
}
|
||||
}
|
||||
#[doc = "core1 access peripherals permission configuration register 13.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_pif_pms_constrain_13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_1_pif_pms_constrain_13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_1_PIF_PMS_CONSTRAIN_13_SPEC;
|
||||
impl crate::RegisterSpec for CORE_1_PIF_PMS_CONSTRAIN_13_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_1_pif_pms_constrain_13::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_1_PIF_PMS_CONSTRAIN_13_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_1_pif_pms_constrain_13::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_1_PIF_PMS_CONSTRAIN_13_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_1_PIF_PMS_CONSTRAIN_13 to value 0x003f_ffff"]
|
||||
impl crate::Resettable for CORE_1_PIF_PMS_CONSTRAIN_13_SPEC {
|
||||
const RESET_VALUE: u32 = 0x003f_ffff;
|
||||
}
|
||||
@@ -0,0 +1,120 @@
|
||||
#[doc = "Register `CORE_1_PIF_PMS_CONSTRAIN_14` reader"]
|
||||
pub type R = crate::R<CORE_1_PIF_PMS_CONSTRAIN_14_SPEC>;
|
||||
#[doc = "Register `CORE_1_PIF_PMS_CONSTRAIN_14` writer"]
|
||||
pub type W = crate::W<CORE_1_PIF_PMS_CONSTRAIN_14_SPEC>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L` reader - RTCSlow_1 memory low region permission in world 0 for core1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L` writer - RTCSlow_1 memory low region permission in world 0 for core1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H` reader - RTCSlow_1 memory high region permission in world 0 for core1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H` writer - RTCSlow_1 memory high region permission in world 0 for core1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L` reader - RTCSlow_1 memory low region permission in world 1 for core1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L` writer - RTCSlow_1 memory low region permission in world 1 for core1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H` reader - RTCSlow_1 memory high region permission in world 1 for core1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H` writer - RTCSlow_1 memory high region permission in world 1 for core1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:2 - RTCSlow_1 memory low region permission in world 0 for core1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_rtcslow_1_world_0_l(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_R::new((self.bits & 7) as u8)
|
||||
}
|
||||
#[doc = "Bits 3:5 - RTCSlow_1 memory high region permission in world 0 for core1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_rtcslow_1_world_0_h(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_R::new(((self.bits >> 3) & 7) as u8)
|
||||
}
|
||||
#[doc = "Bits 6:8 - RTCSlow_1 memory low region permission in world 1 for core1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_rtcslow_1_world_1_l(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_R::new(((self.bits >> 6) & 7) as u8)
|
||||
}
|
||||
#[doc = "Bits 9:11 - RTCSlow_1 memory high region permission in world 1 for core1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_rtcslow_1_world_1_h(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_R::new(((self.bits >> 9) & 7) as u8)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_1_PIF_PMS_CONSTRAIN_14")
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_rtcslow_1_world_0_l",
|
||||
&self.core_1_pif_pms_constrain_rtcslow_1_world_0_l(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_rtcslow_1_world_0_h",
|
||||
&self.core_1_pif_pms_constrain_rtcslow_1_world_0_h(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_rtcslow_1_world_1_l",
|
||||
&self.core_1_pif_pms_constrain_rtcslow_1_world_1_l(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_rtcslow_1_world_1_h",
|
||||
&self.core_1_pif_pms_constrain_rtcslow_1_world_1_h(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:2 - RTCSlow_1 memory low region permission in world 0 for core1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_rtcslow_1_world_0_l(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_W<CORE_1_PIF_PMS_CONSTRAIN_14_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_W::new(self, 0)
|
||||
}
|
||||
#[doc = "Bits 3:5 - RTCSlow_1 memory high region permission in world 0 for core1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_rtcslow_1_world_0_h(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_W<CORE_1_PIF_PMS_CONSTRAIN_14_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_W::new(self, 3)
|
||||
}
|
||||
#[doc = "Bits 6:8 - RTCSlow_1 memory low region permission in world 1 for core1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_rtcslow_1_world_1_l(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_W<CORE_1_PIF_PMS_CONSTRAIN_14_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_W::new(self, 6)
|
||||
}
|
||||
#[doc = "Bits 9:11 - RTCSlow_1 memory high region permission in world 1 for core1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_rtcslow_1_world_1_h(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_W<CORE_1_PIF_PMS_CONSTRAIN_14_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_W::new(self, 9)
|
||||
}
|
||||
}
|
||||
#[doc = "core1 access peripherals permission configuration register 14.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_pif_pms_constrain_14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_1_pif_pms_constrain_14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_1_PIF_PMS_CONSTRAIN_14_SPEC;
|
||||
impl crate::RegisterSpec for CORE_1_PIF_PMS_CONSTRAIN_14_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_1_pif_pms_constrain_14::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_1_PIF_PMS_CONSTRAIN_14_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_1_pif_pms_constrain_14::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_1_PIF_PMS_CONSTRAIN_14_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_1_PIF_PMS_CONSTRAIN_14 to value 0x0fff"]
|
||||
impl crate::Resettable for CORE_1_PIF_PMS_CONSTRAIN_14_SPEC {
|
||||
const RESET_VALUE: u32 = 0x0fff;
|
||||
}
|
||||
@@ -0,0 +1,326 @@
|
||||
#[doc = "Register `CORE_1_PIF_PMS_CONSTRAIN_2` reader"]
|
||||
pub type R = crate::R<CORE_1_PIF_PMS_CONSTRAIN_2_SPEC>;
|
||||
#[doc = "Register `CORE_1_PIF_PMS_CONSTRAIN_2` writer"]
|
||||
pub type W = crate::W<CORE_1_PIF_PMS_CONSTRAIN_2_SPEC>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT` reader - Core1 access bt permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT` writer - Core1 access bt permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0` reader - Core1 access i2c_ext0 permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0` writer - Core1 access i2c_ext0 permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0` reader - Core1 access uhci0 permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0` writer - Core1 access uhci0 permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST` reader - Core1 access slchost permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST` writer - Core1 access slchost permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT` reader - Core1 access rmt permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT` writer - Core1 access rmt permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT` reader - Core1 access pcnt permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT` writer - Core1 access pcnt permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC` reader - Core1 access slc permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC` writer - Core1 access slc permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC` reader - Core1 access ledc permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC` writer - Core1 access ledc permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP` reader - Core1 access backup permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP` writer - Core1 access backup permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB` reader - Core1 access bb permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB` writer - Core1 access bb permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0` reader - Core1 access pwm0 permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0` writer - Core1 access pwm0 permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP` reader - Core1 access timergroup permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP` writer - Core1 access timergroup permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1` reader - Core1 access timergroup1 permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1` writer - Core1 access timergroup1 permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER` reader - Core1 access systimer permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER` writer - Core1 access systimer permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:1 - Core1 access bt permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_bt(&self) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_R::new((self.bits & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 4:5 - Core1 access i2c_ext0 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_i2c_ext0(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_R::new(((self.bits >> 4) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 6:7 - Core1 access uhci0 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_uhci0(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_R::new(((self.bits >> 6) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 8:9 - Core1 access slchost permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_slchost(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_R::new(((self.bits >> 8) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 10:11 - Core1 access rmt permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_rmt(&self) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT_R::new(((self.bits >> 10) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 12:13 - Core1 access pcnt permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_pcnt(&self) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_R::new(((self.bits >> 12) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 14:15 - Core1 access slc permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_slc(&self) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC_R::new(((self.bits >> 14) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 16:17 - Core1 access ledc permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_ledc(&self) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_R::new(((self.bits >> 16) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 18:19 - Core1 access backup permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_backup(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_R::new(((self.bits >> 18) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 22:23 - Core1 access bb permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_bb(&self) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB_R::new(((self.bits >> 22) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 24:25 - Core1 access pwm0 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_pwm0(&self) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_R::new(((self.bits >> 24) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 26:27 - Core1 access timergroup permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_timergroup(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_R::new(((self.bits >> 26) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 28:29 - Core1 access timergroup1 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_timergroup1(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_R::new(((self.bits >> 28) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 30:31 - Core1 access systimer permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_systimer(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_R::new(((self.bits >> 30) & 3) as u8)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_1_PIF_PMS_CONSTRAIN_2")
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_0_bt",
|
||||
&self.core_1_pif_pms_constrain_world_0_bt(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_0_i2c_ext0",
|
||||
&self.core_1_pif_pms_constrain_world_0_i2c_ext0(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_0_uhci0",
|
||||
&self.core_1_pif_pms_constrain_world_0_uhci0(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_0_slchost",
|
||||
&self.core_1_pif_pms_constrain_world_0_slchost(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_0_rmt",
|
||||
&self.core_1_pif_pms_constrain_world_0_rmt(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_0_pcnt",
|
||||
&self.core_1_pif_pms_constrain_world_0_pcnt(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_0_slc",
|
||||
&self.core_1_pif_pms_constrain_world_0_slc(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_0_ledc",
|
||||
&self.core_1_pif_pms_constrain_world_0_ledc(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_0_backup",
|
||||
&self.core_1_pif_pms_constrain_world_0_backup(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_0_bb",
|
||||
&self.core_1_pif_pms_constrain_world_0_bb(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_0_pwm0",
|
||||
&self.core_1_pif_pms_constrain_world_0_pwm0(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_0_timergroup",
|
||||
&self.core_1_pif_pms_constrain_world_0_timergroup(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_0_timergroup1",
|
||||
&self.core_1_pif_pms_constrain_world_0_timergroup1(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_0_systimer",
|
||||
&self.core_1_pif_pms_constrain_world_0_systimer(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:1 - Core1 access bt permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_bt(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_W<CORE_1_PIF_PMS_CONSTRAIN_2_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_W::new(self, 0)
|
||||
}
|
||||
#[doc = "Bits 4:5 - Core1 access i2c_ext0 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_i2c_ext0(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_W<CORE_1_PIF_PMS_CONSTRAIN_2_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_W::new(self, 4)
|
||||
}
|
||||
#[doc = "Bits 6:7 - Core1 access uhci0 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_uhci0(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_W<CORE_1_PIF_PMS_CONSTRAIN_2_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_W::new(self, 6)
|
||||
}
|
||||
#[doc = "Bits 8:9 - Core1 access slchost permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_slchost(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_W<CORE_1_PIF_PMS_CONSTRAIN_2_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_W::new(self, 8)
|
||||
}
|
||||
#[doc = "Bits 10:11 - Core1 access rmt permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_rmt(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT_W<CORE_1_PIF_PMS_CONSTRAIN_2_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT_W::new(self, 10)
|
||||
}
|
||||
#[doc = "Bits 12:13 - Core1 access pcnt permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_pcnt(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_W<CORE_1_PIF_PMS_CONSTRAIN_2_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_W::new(self, 12)
|
||||
}
|
||||
#[doc = "Bits 14:15 - Core1 access slc permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_slc(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC_W<CORE_1_PIF_PMS_CONSTRAIN_2_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC_W::new(self, 14)
|
||||
}
|
||||
#[doc = "Bits 16:17 - Core1 access ledc permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_ledc(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_W<CORE_1_PIF_PMS_CONSTRAIN_2_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_W::new(self, 16)
|
||||
}
|
||||
#[doc = "Bits 18:19 - Core1 access backup permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_backup(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_W<CORE_1_PIF_PMS_CONSTRAIN_2_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_W::new(self, 18)
|
||||
}
|
||||
#[doc = "Bits 22:23 - Core1 access bb permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_bb(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB_W<CORE_1_PIF_PMS_CONSTRAIN_2_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB_W::new(self, 22)
|
||||
}
|
||||
#[doc = "Bits 24:25 - Core1 access pwm0 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_pwm0(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_W<CORE_1_PIF_PMS_CONSTRAIN_2_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_W::new(self, 24)
|
||||
}
|
||||
#[doc = "Bits 26:27 - Core1 access timergroup permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_timergroup(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_W<CORE_1_PIF_PMS_CONSTRAIN_2_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_W::new(self, 26)
|
||||
}
|
||||
#[doc = "Bits 28:29 - Core1 access timergroup1 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_timergroup1(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_W<CORE_1_PIF_PMS_CONSTRAIN_2_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_W::new(self, 28)
|
||||
}
|
||||
#[doc = "Bits 30:31 - Core1 access systimer permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_systimer(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_W<CORE_1_PIF_PMS_CONSTRAIN_2_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_W::new(self, 30)
|
||||
}
|
||||
}
|
||||
#[doc = "Core1 access peripherals permission configuration register 2.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_pif_pms_constrain_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_1_pif_pms_constrain_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_1_PIF_PMS_CONSTRAIN_2_SPEC;
|
||||
impl crate::RegisterSpec for CORE_1_PIF_PMS_CONSTRAIN_2_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_1_pif_pms_constrain_2::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_1_PIF_PMS_CONSTRAIN_2_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_1_pif_pms_constrain_2::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_1_PIF_PMS_CONSTRAIN_2_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_1_PIF_PMS_CONSTRAIN_2 to value 0xffcf_fff3"]
|
||||
impl crate::Resettable for CORE_1_PIF_PMS_CONSTRAIN_2_SPEC {
|
||||
const RESET_VALUE: u32 = 0xffcf_fff3;
|
||||
}
|
||||
@@ -0,0 +1,286 @@
|
||||
#[doc = "Register `CORE_1_PIF_PMS_CONSTRAIN_3` reader"]
|
||||
pub type R = crate::R<CORE_1_PIF_PMS_CONSTRAIN_3_SPEC>;
|
||||
#[doc = "Register `CORE_1_PIF_PMS_CONSTRAIN_3` writer"]
|
||||
pub type W = crate::W<CORE_1_PIF_PMS_CONSTRAIN_3_SPEC>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2` reader - Core1 access spi_2 permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2` writer - Core1 access spi_2 permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3` reader - Core1 access spi_3 permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3` writer - Core1 access spi_3 permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL` reader - Core1 access apb_ctrl permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL` writer - Core1 access apb_ctrl permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1` reader - Core1 access i2c_ext1 permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1` writer - Core1 access i2c_ext1 permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST` reader - Core1 access sdio_host permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST` writer - Core1 access sdio_host permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN` reader - Core1 access can permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN` writer - Core1 access can permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1` reader - Core1 access pwm1 permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1` writer - Core1 access pwm1 permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1` reader - Core1 access i2s1 permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1` writer - Core1 access i2s1 permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2` reader - Core1 access uart2 permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2` writer - Core1 access uart2 permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT` reader - Core1 access rwbt permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT` writer - Core1 access rwbt permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC` reader - Core1 access wifimac permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC` writer - Core1 access wifimac permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR` reader - Core1 access pwr permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR` writer - Core1 access pwr permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:1 - Core1 access spi_2 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_spi_2(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_R::new((self.bits & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 2:3 - Core1 access spi_3 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_spi_3(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_R::new(((self.bits >> 2) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 4:5 - Core1 access apb_ctrl permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_apb_ctrl(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_R::new(((self.bits >> 4) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 6:7 - Core1 access i2c_ext1 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_i2c_ext1(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_R::new(((self.bits >> 6) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 8:9 - Core1 access sdio_host permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_sdio_host(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_R::new(((self.bits >> 8) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 10:11 - Core1 access can permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_can(&self) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN_R::new(((self.bits >> 10) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 12:13 - Core1 access pwm1 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_pwm1(&self) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_R::new(((self.bits >> 12) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 14:15 - Core1 access i2s1 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_i2s1(&self) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_R::new(((self.bits >> 14) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 16:17 - Core1 access uart2 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_uart2(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2_R::new(((self.bits >> 16) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 22:23 - Core1 access rwbt permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_rwbt(&self) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_R::new(((self.bits >> 22) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 26:27 - Core1 access wifimac permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_wifimac(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_R::new(((self.bits >> 26) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 28:29 - Core1 access pwr permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_pwr(&self) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR_R::new(((self.bits >> 28) & 3) as u8)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_1_PIF_PMS_CONSTRAIN_3")
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_0_spi_2",
|
||||
&self.core_1_pif_pms_constrain_world_0_spi_2(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_0_spi_3",
|
||||
&self.core_1_pif_pms_constrain_world_0_spi_3(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_0_apb_ctrl",
|
||||
&self.core_1_pif_pms_constrain_world_0_apb_ctrl(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_0_i2c_ext1",
|
||||
&self.core_1_pif_pms_constrain_world_0_i2c_ext1(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_0_sdio_host",
|
||||
&self.core_1_pif_pms_constrain_world_0_sdio_host(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_0_can",
|
||||
&self.core_1_pif_pms_constrain_world_0_can(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_0_pwm1",
|
||||
&self.core_1_pif_pms_constrain_world_0_pwm1(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_0_i2s1",
|
||||
&self.core_1_pif_pms_constrain_world_0_i2s1(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_0_uart2",
|
||||
&self.core_1_pif_pms_constrain_world_0_uart2(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_0_rwbt",
|
||||
&self.core_1_pif_pms_constrain_world_0_rwbt(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_0_wifimac",
|
||||
&self.core_1_pif_pms_constrain_world_0_wifimac(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_0_pwr",
|
||||
&self.core_1_pif_pms_constrain_world_0_pwr(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:1 - Core1 access spi_2 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_spi_2(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_W<CORE_1_PIF_PMS_CONSTRAIN_3_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_W::new(self, 0)
|
||||
}
|
||||
#[doc = "Bits 2:3 - Core1 access spi_3 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_spi_3(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_W<CORE_1_PIF_PMS_CONSTRAIN_3_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_W::new(self, 2)
|
||||
}
|
||||
#[doc = "Bits 4:5 - Core1 access apb_ctrl permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_apb_ctrl(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_W<CORE_1_PIF_PMS_CONSTRAIN_3_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_W::new(self, 4)
|
||||
}
|
||||
#[doc = "Bits 6:7 - Core1 access i2c_ext1 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_i2c_ext1(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_W<CORE_1_PIF_PMS_CONSTRAIN_3_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_W::new(self, 6)
|
||||
}
|
||||
#[doc = "Bits 8:9 - Core1 access sdio_host permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_sdio_host(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_W<CORE_1_PIF_PMS_CONSTRAIN_3_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_W::new(self, 8)
|
||||
}
|
||||
#[doc = "Bits 10:11 - Core1 access can permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_can(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN_W<CORE_1_PIF_PMS_CONSTRAIN_3_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN_W::new(self, 10)
|
||||
}
|
||||
#[doc = "Bits 12:13 - Core1 access pwm1 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_pwm1(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_W<CORE_1_PIF_PMS_CONSTRAIN_3_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_W::new(self, 12)
|
||||
}
|
||||
#[doc = "Bits 14:15 - Core1 access i2s1 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_i2s1(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_W<CORE_1_PIF_PMS_CONSTRAIN_3_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_W::new(self, 14)
|
||||
}
|
||||
#[doc = "Bits 16:17 - Core1 access uart2 permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_uart2(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2_W<CORE_1_PIF_PMS_CONSTRAIN_3_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2_W::new(self, 16)
|
||||
}
|
||||
#[doc = "Bits 22:23 - Core1 access rwbt permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_rwbt(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_W<CORE_1_PIF_PMS_CONSTRAIN_3_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_W::new(self, 22)
|
||||
}
|
||||
#[doc = "Bits 26:27 - Core1 access wifimac permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_wifimac(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_W<CORE_1_PIF_PMS_CONSTRAIN_3_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_W::new(self, 26)
|
||||
}
|
||||
#[doc = "Bits 28:29 - Core1 access pwr permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_pwr(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR_W<CORE_1_PIF_PMS_CONSTRAIN_3_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR_W::new(self, 28)
|
||||
}
|
||||
}
|
||||
#[doc = "Core1 access peripherals permission configuration register 3.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_pif_pms_constrain_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_1_pif_pms_constrain_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_1_PIF_PMS_CONSTRAIN_3_SPEC;
|
||||
impl crate::RegisterSpec for CORE_1_PIF_PMS_CONSTRAIN_3_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_1_pif_pms_constrain_3::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_1_PIF_PMS_CONSTRAIN_3_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_1_pif_pms_constrain_3::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_1_PIF_PMS_CONSTRAIN_3_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_1_PIF_PMS_CONSTRAIN_3 to value 0x3cc3_ffff"]
|
||||
impl crate::Resettable for CORE_1_PIF_PMS_CONSTRAIN_3_SPEC {
|
||||
const RESET_VALUE: u32 = 0x3cc3_ffff;
|
||||
}
|
||||
@@ -0,0 +1,379 @@
|
||||
#[doc = "Register `CORE_1_PIF_PMS_CONSTRAIN_4` reader"]
|
||||
pub type R = crate::R<CORE_1_PIF_PMS_CONSTRAIN_4_SPEC>;
|
||||
#[doc = "Register `CORE_1_PIF_PMS_CONSTRAIN_4` writer"]
|
||||
pub type W = crate::W<CORE_1_PIF_PMS_CONSTRAIN_4_SPEC>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE` reader - Core1 access usb_device permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE` writer - Core1 access usb_device permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP` reader - Core1 access usb_wrap permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP` writer - Core1 access usb_wrap permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI` reader - Core1 access crypto_peri permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI` writer - Core1 access crypto_peri permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA` reader - Core1 access crypto_dma permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA` writer - Core1 access crypto_dma permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC` reader - Core1 access apb_adc permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC` writer - Core1 access apb_adc permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM` reader - Core1 access lcd_cam permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM` writer - Core1 access lcd_cam permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR` reader - Core1 access bt_pwr permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR` writer - Core1 access bt_pwr permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB` reader - Core1 access usb permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB` writer - Core1 access usb permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM` reader - Core1 access system permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM` writer - Core1 access system permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE` reader - Core1 access sensitive permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE` writer - Core1 access sensitive permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT` reader - Core1 access interrupt permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT` writer - Core1 access interrupt permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY` reader - Core1 access dma_copy permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY` writer - Core1 access dma_copy permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG` reader - Core1 access cache_config permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG` writer - Core1 access cache_config permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD` reader - Core1 access ad permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD` writer - Core1 access ad permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO` reader - Core1 access dio permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO` writer - Core1 access dio permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER` reader - Core1 access world_controller permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER` writer - Core1 access world_controller permission in world0."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_W<'a, REG> =
|
||||
crate::FieldWriter<'a, REG, 2>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:1 - Core1 access usb_device permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_usb_device(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_R::new((self.bits & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 2:3 - Core1 access usb_wrap permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_usb_wrap(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_R::new(((self.bits >> 2) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 4:5 - Core1 access crypto_peri permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_crypto_peri(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_R::new(((self.bits >> 4) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 6:7 - Core1 access crypto_dma permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_crypto_dma(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_R::new(((self.bits >> 6) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 8:9 - Core1 access apb_adc permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_apb_adc(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_R::new(((self.bits >> 8) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 10:11 - Core1 access lcd_cam permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_lcd_cam(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_R::new(((self.bits >> 10) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 12:13 - Core1 access bt_pwr permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_bt_pwr(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_R::new(((self.bits >> 12) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 14:15 - Core1 access usb permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_usb(&self) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_R::new(((self.bits >> 14) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 16:17 - Core1 access system permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_system(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_R::new(((self.bits >> 16) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 18:19 - Core1 access sensitive permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_sensitive(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_R::new(((self.bits >> 18) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 20:21 - Core1 access interrupt permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_interrupt(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_R::new(((self.bits >> 20) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 22:23 - Core1 access dma_copy permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_dma_copy(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_R::new(((self.bits >> 22) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 24:25 - Core1 access cache_config permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_cache_config(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_R::new(((self.bits >> 24) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 26:27 - Core1 access ad permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_ad(&self) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD_R::new(((self.bits >> 26) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 28:29 - Core1 access dio permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_dio(&self) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO_R::new(((self.bits >> 28) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 30:31 - Core1 access world_controller permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_world_controller(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_R::new(((self.bits >> 30) & 3) as u8)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_1_PIF_PMS_CONSTRAIN_4")
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_0_usb_device",
|
||||
&self.core_1_pif_pms_constrain_world_0_usb_device(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_0_usb_wrap",
|
||||
&self.core_1_pif_pms_constrain_world_0_usb_wrap(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_0_crypto_peri",
|
||||
&self.core_1_pif_pms_constrain_world_0_crypto_peri(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_0_crypto_dma",
|
||||
&self.core_1_pif_pms_constrain_world_0_crypto_dma(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_0_apb_adc",
|
||||
&self.core_1_pif_pms_constrain_world_0_apb_adc(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_0_lcd_cam",
|
||||
&self.core_1_pif_pms_constrain_world_0_lcd_cam(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_0_bt_pwr",
|
||||
&self.core_1_pif_pms_constrain_world_0_bt_pwr(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_0_usb",
|
||||
&self.core_1_pif_pms_constrain_world_0_usb(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_0_system",
|
||||
&self.core_1_pif_pms_constrain_world_0_system(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_0_sensitive",
|
||||
&self.core_1_pif_pms_constrain_world_0_sensitive(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_0_interrupt",
|
||||
&self.core_1_pif_pms_constrain_world_0_interrupt(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_0_dma_copy",
|
||||
&self.core_1_pif_pms_constrain_world_0_dma_copy(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_0_cache_config",
|
||||
&self.core_1_pif_pms_constrain_world_0_cache_config(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_0_ad",
|
||||
&self.core_1_pif_pms_constrain_world_0_ad(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_0_dio",
|
||||
&self.core_1_pif_pms_constrain_world_0_dio(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_0_world_controller",
|
||||
&self.core_1_pif_pms_constrain_world_0_world_controller(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:1 - Core1 access usb_device permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_usb_device(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_W<CORE_1_PIF_PMS_CONSTRAIN_4_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_W::new(self, 0)
|
||||
}
|
||||
#[doc = "Bits 2:3 - Core1 access usb_wrap permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_usb_wrap(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_W<CORE_1_PIF_PMS_CONSTRAIN_4_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_W::new(self, 2)
|
||||
}
|
||||
#[doc = "Bits 4:5 - Core1 access crypto_peri permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_crypto_peri(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_W<CORE_1_PIF_PMS_CONSTRAIN_4_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_W::new(self, 4)
|
||||
}
|
||||
#[doc = "Bits 6:7 - Core1 access crypto_dma permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_crypto_dma(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_W<CORE_1_PIF_PMS_CONSTRAIN_4_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_W::new(self, 6)
|
||||
}
|
||||
#[doc = "Bits 8:9 - Core1 access apb_adc permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_apb_adc(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_W<CORE_1_PIF_PMS_CONSTRAIN_4_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_W::new(self, 8)
|
||||
}
|
||||
#[doc = "Bits 10:11 - Core1 access lcd_cam permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_lcd_cam(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_W<CORE_1_PIF_PMS_CONSTRAIN_4_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_W::new(self, 10)
|
||||
}
|
||||
#[doc = "Bits 12:13 - Core1 access bt_pwr permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_bt_pwr(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_W<CORE_1_PIF_PMS_CONSTRAIN_4_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_W::new(self, 12)
|
||||
}
|
||||
#[doc = "Bits 14:15 - Core1 access usb permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_usb(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_W<CORE_1_PIF_PMS_CONSTRAIN_4_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_W::new(self, 14)
|
||||
}
|
||||
#[doc = "Bits 16:17 - Core1 access system permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_system(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_W<CORE_1_PIF_PMS_CONSTRAIN_4_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_W::new(self, 16)
|
||||
}
|
||||
#[doc = "Bits 18:19 - Core1 access sensitive permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_sensitive(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_W<CORE_1_PIF_PMS_CONSTRAIN_4_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_W::new(self, 18)
|
||||
}
|
||||
#[doc = "Bits 20:21 - Core1 access interrupt permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_interrupt(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_W<CORE_1_PIF_PMS_CONSTRAIN_4_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_W::new(self, 20)
|
||||
}
|
||||
#[doc = "Bits 22:23 - Core1 access dma_copy permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_dma_copy(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_W<CORE_1_PIF_PMS_CONSTRAIN_4_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_W::new(self, 22)
|
||||
}
|
||||
#[doc = "Bits 24:25 - Core1 access cache_config permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_cache_config(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_W<CORE_1_PIF_PMS_CONSTRAIN_4_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_W::new(self, 24)
|
||||
}
|
||||
#[doc = "Bits 26:27 - Core1 access ad permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_ad(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD_W<CORE_1_PIF_PMS_CONSTRAIN_4_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD_W::new(self, 26)
|
||||
}
|
||||
#[doc = "Bits 28:29 - Core1 access dio permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_dio(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO_W<CORE_1_PIF_PMS_CONSTRAIN_4_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO_W::new(self, 28)
|
||||
}
|
||||
#[doc = "Bits 30:31 - Core1 access world_controller permission in world0."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_0_world_controller(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_W<CORE_1_PIF_PMS_CONSTRAIN_4_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_W::new(self, 30)
|
||||
}
|
||||
}
|
||||
#[doc = "Core1 access peripherals permission configuration register 4.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_pif_pms_constrain_4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_1_pif_pms_constrain_4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_1_PIF_PMS_CONSTRAIN_4_SPEC;
|
||||
impl crate::RegisterSpec for CORE_1_PIF_PMS_CONSTRAIN_4_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_1_pif_pms_constrain_4::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_1_PIF_PMS_CONSTRAIN_4_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_1_pif_pms_constrain_4::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_1_PIF_PMS_CONSTRAIN_4_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_1_PIF_PMS_CONSTRAIN_4 to value 0xffff_ffff"]
|
||||
impl crate::Resettable for CORE_1_PIF_PMS_CONSTRAIN_4_SPEC {
|
||||
const RESET_VALUE: u32 = 0xffff_ffff;
|
||||
}
|
||||
@@ -0,0 +1,300 @@
|
||||
#[doc = "Register `CORE_1_PIF_PMS_CONSTRAIN_5` reader"]
|
||||
pub type R = crate::R<CORE_1_PIF_PMS_CONSTRAIN_5_SPEC>;
|
||||
#[doc = "Register `CORE_1_PIF_PMS_CONSTRAIN_5` writer"]
|
||||
pub type W = crate::W<CORE_1_PIF_PMS_CONSTRAIN_5_SPEC>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART` reader - Core1 access uart permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART` writer - Core1 access uart permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1` reader - Core1 access g0spi_1 permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1` writer - Core1 access g0spi_1 permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0` reader - Core1 access g0spi_0 permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0` writer - Core1 access g0spi_0 permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO` reader - Core1 access gpio permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO` writer - Core1 access gpio permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2` reader - Core1 access fe2 permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2` writer - Core1 access fe2 permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE` reader - Core1 access fe permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE` writer - Core1 access fe permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC` reader - Core1 access rtc permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC` writer - Core1 access rtc permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX` reader - Core1 access io_mux permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX` writer - Core1 access io_mux permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF` reader - Core1 access hinf permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF` writer - Core1 access hinf permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC` reader - Core1 access misc permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC` writer - Core1 access misc permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C` reader - Core1 access i2c permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C` writer - Core1 access i2c permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0` reader - Core1 access i2s0 permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0` writer - Core1 access i2s0 permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1` reader - Core1 access uart1 permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1` writer - Core1 access uart1 permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:1 - Core1 access uart permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_uart(&self) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART_R::new((self.bits & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 2:3 - Core1 access g0spi_1 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_g0spi_1(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_R::new(((self.bits >> 2) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 4:5 - Core1 access g0spi_0 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_g0spi_0(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_R::new(((self.bits >> 4) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 6:7 - Core1 access gpio permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_gpio(&self) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_R::new(((self.bits >> 6) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 8:9 - Core1 access fe2 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_fe2(&self) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2_R::new(((self.bits >> 8) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 10:11 - Core1 access fe permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_fe(&self) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE_R::new(((self.bits >> 10) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 14:15 - Core1 access rtc permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_rtc(&self) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_R::new(((self.bits >> 14) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 16:17 - Core1 access io_mux permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_io_mux(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_R::new(((self.bits >> 16) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 20:21 - Core1 access hinf permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_hinf(&self) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF_R::new(((self.bits >> 20) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 24:25 - Core1 access misc permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_misc(&self) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC_R::new(((self.bits >> 24) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 26:27 - Core1 access i2c permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_i2c(&self) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_R::new(((self.bits >> 26) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 28:29 - Core1 access i2s0 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_i2s0(&self) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_R::new(((self.bits >> 28) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 30:31 - Core1 access uart1 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_uart1(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1_R::new(((self.bits >> 30) & 3) as u8)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_1_PIF_PMS_CONSTRAIN_5")
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_1_uart",
|
||||
&self.core_1_pif_pms_constrain_world_1_uart(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_1_g0spi_1",
|
||||
&self.core_1_pif_pms_constrain_world_1_g0spi_1(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_1_g0spi_0",
|
||||
&self.core_1_pif_pms_constrain_world_1_g0spi_0(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_1_gpio",
|
||||
&self.core_1_pif_pms_constrain_world_1_gpio(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_1_fe2",
|
||||
&self.core_1_pif_pms_constrain_world_1_fe2(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_1_fe",
|
||||
&self.core_1_pif_pms_constrain_world_1_fe(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_1_rtc",
|
||||
&self.core_1_pif_pms_constrain_world_1_rtc(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_1_io_mux",
|
||||
&self.core_1_pif_pms_constrain_world_1_io_mux(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_1_hinf",
|
||||
&self.core_1_pif_pms_constrain_world_1_hinf(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_1_misc",
|
||||
&self.core_1_pif_pms_constrain_world_1_misc(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_1_i2c",
|
||||
&self.core_1_pif_pms_constrain_world_1_i2c(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_1_i2s0",
|
||||
&self.core_1_pif_pms_constrain_world_1_i2s0(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_1_uart1",
|
||||
&self.core_1_pif_pms_constrain_world_1_uart1(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:1 - Core1 access uart permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_uart(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART_W<CORE_1_PIF_PMS_CONSTRAIN_5_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART_W::new(self, 0)
|
||||
}
|
||||
#[doc = "Bits 2:3 - Core1 access g0spi_1 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_g0spi_1(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_W<CORE_1_PIF_PMS_CONSTRAIN_5_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_W::new(self, 2)
|
||||
}
|
||||
#[doc = "Bits 4:5 - Core1 access g0spi_0 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_g0spi_0(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_W<CORE_1_PIF_PMS_CONSTRAIN_5_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_W::new(self, 4)
|
||||
}
|
||||
#[doc = "Bits 6:7 - Core1 access gpio permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_gpio(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_W<CORE_1_PIF_PMS_CONSTRAIN_5_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_W::new(self, 6)
|
||||
}
|
||||
#[doc = "Bits 8:9 - Core1 access fe2 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_fe2(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2_W<CORE_1_PIF_PMS_CONSTRAIN_5_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2_W::new(self, 8)
|
||||
}
|
||||
#[doc = "Bits 10:11 - Core1 access fe permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_fe(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE_W<CORE_1_PIF_PMS_CONSTRAIN_5_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE_W::new(self, 10)
|
||||
}
|
||||
#[doc = "Bits 14:15 - Core1 access rtc permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_rtc(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_W<CORE_1_PIF_PMS_CONSTRAIN_5_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_W::new(self, 14)
|
||||
}
|
||||
#[doc = "Bits 16:17 - Core1 access io_mux permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_io_mux(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_W<CORE_1_PIF_PMS_CONSTRAIN_5_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_W::new(self, 16)
|
||||
}
|
||||
#[doc = "Bits 20:21 - Core1 access hinf permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_hinf(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF_W<CORE_1_PIF_PMS_CONSTRAIN_5_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF_W::new(self, 20)
|
||||
}
|
||||
#[doc = "Bits 24:25 - Core1 access misc permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_misc(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC_W<CORE_1_PIF_PMS_CONSTRAIN_5_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC_W::new(self, 24)
|
||||
}
|
||||
#[doc = "Bits 26:27 - Core1 access i2c permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_i2c(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_W<CORE_1_PIF_PMS_CONSTRAIN_5_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_W::new(self, 26)
|
||||
}
|
||||
#[doc = "Bits 28:29 - Core1 access i2s0 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_i2s0(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_W<CORE_1_PIF_PMS_CONSTRAIN_5_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_W::new(self, 28)
|
||||
}
|
||||
#[doc = "Bits 30:31 - Core1 access uart1 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_uart1(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1_W<CORE_1_PIF_PMS_CONSTRAIN_5_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1_W::new(self, 30)
|
||||
}
|
||||
}
|
||||
#[doc = "Core1 access peripherals permission configuration register 5.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_pif_pms_constrain_5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_1_pif_pms_constrain_5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_1_PIF_PMS_CONSTRAIN_5_SPEC;
|
||||
impl crate::RegisterSpec for CORE_1_PIF_PMS_CONSTRAIN_5_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_1_pif_pms_constrain_5::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_1_PIF_PMS_CONSTRAIN_5_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_1_pif_pms_constrain_5::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_1_PIF_PMS_CONSTRAIN_5_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_1_PIF_PMS_CONSTRAIN_5 to value 0xff33_cfff"]
|
||||
impl crate::Resettable for CORE_1_PIF_PMS_CONSTRAIN_5_SPEC {
|
||||
const RESET_VALUE: u32 = 0xff33_cfff;
|
||||
}
|
||||
@@ -0,0 +1,326 @@
|
||||
#[doc = "Register `CORE_1_PIF_PMS_CONSTRAIN_6` reader"]
|
||||
pub type R = crate::R<CORE_1_PIF_PMS_CONSTRAIN_6_SPEC>;
|
||||
#[doc = "Register `CORE_1_PIF_PMS_CONSTRAIN_6` writer"]
|
||||
pub type W = crate::W<CORE_1_PIF_PMS_CONSTRAIN_6_SPEC>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT` reader - Core1 access bt permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT` writer - Core1 access bt permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0` reader - Core1 access i2c_ext0 permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0` writer - Core1 access i2c_ext0 permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0` reader - Core1 access uhci0 permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0` writer - Core1 access uhci0 permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST` reader - Core1 access slchost permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST` writer - Core1 access slchost permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT` reader - Core1 access rmt permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT` writer - Core1 access rmt permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT` reader - Core1 access pcnt permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT` writer - Core1 access pcnt permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC` reader - Core1 access slc permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC` writer - Core1 access slc permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC` reader - Core1 access ledc permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC` writer - Core1 access ledc permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP` reader - Core1 access backup permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP` writer - Core1 access backup permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB` reader - Core1 access bb permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB` writer - Core1 access bb permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0` reader - Core1 access pwm0 permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0` writer - Core1 access pwm0 permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP` reader - Core1 access timergroup permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP` writer - Core1 access timergroup permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1` reader - Core1 access timergroup1 permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1` writer - Core1 access timergroup1 permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER` reader - Core1 access systimer permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER` writer - Core1 access systimer permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:1 - Core1 access bt permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_bt(&self) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_R::new((self.bits & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 4:5 - Core1 access i2c_ext0 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_i2c_ext0(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_R::new(((self.bits >> 4) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 6:7 - Core1 access uhci0 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_uhci0(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_R::new(((self.bits >> 6) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 8:9 - Core1 access slchost permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_slchost(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_R::new(((self.bits >> 8) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 10:11 - Core1 access rmt permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_rmt(&self) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT_R::new(((self.bits >> 10) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 12:13 - Core1 access pcnt permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_pcnt(&self) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_R::new(((self.bits >> 12) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 14:15 - Core1 access slc permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_slc(&self) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC_R::new(((self.bits >> 14) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 16:17 - Core1 access ledc permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_ledc(&self) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_R::new(((self.bits >> 16) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 18:19 - Core1 access backup permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_backup(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_R::new(((self.bits >> 18) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 22:23 - Core1 access bb permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_bb(&self) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB_R::new(((self.bits >> 22) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 24:25 - Core1 access pwm0 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_pwm0(&self) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_R::new(((self.bits >> 24) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 26:27 - Core1 access timergroup permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_timergroup(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_R::new(((self.bits >> 26) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 28:29 - Core1 access timergroup1 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_timergroup1(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_R::new(((self.bits >> 28) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 30:31 - Core1 access systimer permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_systimer(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_R::new(((self.bits >> 30) & 3) as u8)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_1_PIF_PMS_CONSTRAIN_6")
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_1_bt",
|
||||
&self.core_1_pif_pms_constrain_world_1_bt(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_1_i2c_ext0",
|
||||
&self.core_1_pif_pms_constrain_world_1_i2c_ext0(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_1_uhci0",
|
||||
&self.core_1_pif_pms_constrain_world_1_uhci0(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_1_slchost",
|
||||
&self.core_1_pif_pms_constrain_world_1_slchost(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_1_rmt",
|
||||
&self.core_1_pif_pms_constrain_world_1_rmt(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_1_pcnt",
|
||||
&self.core_1_pif_pms_constrain_world_1_pcnt(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_1_slc",
|
||||
&self.core_1_pif_pms_constrain_world_1_slc(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_1_ledc",
|
||||
&self.core_1_pif_pms_constrain_world_1_ledc(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_1_backup",
|
||||
&self.core_1_pif_pms_constrain_world_1_backup(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_1_bb",
|
||||
&self.core_1_pif_pms_constrain_world_1_bb(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_1_pwm0",
|
||||
&self.core_1_pif_pms_constrain_world_1_pwm0(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_1_timergroup",
|
||||
&self.core_1_pif_pms_constrain_world_1_timergroup(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_1_timergroup1",
|
||||
&self.core_1_pif_pms_constrain_world_1_timergroup1(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_1_systimer",
|
||||
&self.core_1_pif_pms_constrain_world_1_systimer(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:1 - Core1 access bt permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_bt(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_W<CORE_1_PIF_PMS_CONSTRAIN_6_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_W::new(self, 0)
|
||||
}
|
||||
#[doc = "Bits 4:5 - Core1 access i2c_ext0 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_i2c_ext0(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_W<CORE_1_PIF_PMS_CONSTRAIN_6_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_W::new(self, 4)
|
||||
}
|
||||
#[doc = "Bits 6:7 - Core1 access uhci0 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_uhci0(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_W<CORE_1_PIF_PMS_CONSTRAIN_6_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_W::new(self, 6)
|
||||
}
|
||||
#[doc = "Bits 8:9 - Core1 access slchost permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_slchost(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_W<CORE_1_PIF_PMS_CONSTRAIN_6_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_W::new(self, 8)
|
||||
}
|
||||
#[doc = "Bits 10:11 - Core1 access rmt permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_rmt(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT_W<CORE_1_PIF_PMS_CONSTRAIN_6_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT_W::new(self, 10)
|
||||
}
|
||||
#[doc = "Bits 12:13 - Core1 access pcnt permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_pcnt(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_W<CORE_1_PIF_PMS_CONSTRAIN_6_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_W::new(self, 12)
|
||||
}
|
||||
#[doc = "Bits 14:15 - Core1 access slc permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_slc(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC_W<CORE_1_PIF_PMS_CONSTRAIN_6_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC_W::new(self, 14)
|
||||
}
|
||||
#[doc = "Bits 16:17 - Core1 access ledc permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_ledc(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_W<CORE_1_PIF_PMS_CONSTRAIN_6_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_W::new(self, 16)
|
||||
}
|
||||
#[doc = "Bits 18:19 - Core1 access backup permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_backup(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_W<CORE_1_PIF_PMS_CONSTRAIN_6_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_W::new(self, 18)
|
||||
}
|
||||
#[doc = "Bits 22:23 - Core1 access bb permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_bb(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB_W<CORE_1_PIF_PMS_CONSTRAIN_6_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB_W::new(self, 22)
|
||||
}
|
||||
#[doc = "Bits 24:25 - Core1 access pwm0 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_pwm0(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_W<CORE_1_PIF_PMS_CONSTRAIN_6_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_W::new(self, 24)
|
||||
}
|
||||
#[doc = "Bits 26:27 - Core1 access timergroup permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_timergroup(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_W<CORE_1_PIF_PMS_CONSTRAIN_6_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_W::new(self, 26)
|
||||
}
|
||||
#[doc = "Bits 28:29 - Core1 access timergroup1 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_timergroup1(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_W<CORE_1_PIF_PMS_CONSTRAIN_6_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_W::new(self, 28)
|
||||
}
|
||||
#[doc = "Bits 30:31 - Core1 access systimer permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_systimer(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_W<CORE_1_PIF_PMS_CONSTRAIN_6_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_W::new(self, 30)
|
||||
}
|
||||
}
|
||||
#[doc = "Core1 access peripherals permission configuration register 6.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_pif_pms_constrain_6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_1_pif_pms_constrain_6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_1_PIF_PMS_CONSTRAIN_6_SPEC;
|
||||
impl crate::RegisterSpec for CORE_1_PIF_PMS_CONSTRAIN_6_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_1_pif_pms_constrain_6::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_1_PIF_PMS_CONSTRAIN_6_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_1_pif_pms_constrain_6::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_1_PIF_PMS_CONSTRAIN_6_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_1_PIF_PMS_CONSTRAIN_6 to value 0xffcf_fff3"]
|
||||
impl crate::Resettable for CORE_1_PIF_PMS_CONSTRAIN_6_SPEC {
|
||||
const RESET_VALUE: u32 = 0xffcf_fff3;
|
||||
}
|
||||
@@ -0,0 +1,286 @@
|
||||
#[doc = "Register `CORE_1_PIF_PMS_CONSTRAIN_7` reader"]
|
||||
pub type R = crate::R<CORE_1_PIF_PMS_CONSTRAIN_7_SPEC>;
|
||||
#[doc = "Register `CORE_1_PIF_PMS_CONSTRAIN_7` writer"]
|
||||
pub type W = crate::W<CORE_1_PIF_PMS_CONSTRAIN_7_SPEC>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2` reader - Core1 access spi_2 permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2` writer - Core1 access spi_2 permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3` reader - Core1 access spi_3 permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3` writer - Core1 access spi_3 permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL` reader - Core1 access apb_ctrl permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL` writer - Core1 access apb_ctrl permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1` reader - Core1 access i2c_ext1 permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1` writer - Core1 access i2c_ext1 permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST` reader - Core1 access sdio_host permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST` writer - Core1 access sdio_host permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN` reader - Core1 access can permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN` writer - Core1 access can permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1` reader - Core1 access pwm1 permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1` writer - Core1 access pwm1 permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1` reader - Core1 access i2s1 permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1` writer - Core1 access i2s1 permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2` reader - Core1 access uart2 permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2` writer - Core1 access uart2 permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT` reader - Core1 access rwbt permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT` writer - Core1 access rwbt permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC` reader - Core1 access wifimac permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC` writer - Core1 access wifimac permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR` reader - Core1 access pwr permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR` writer - Core1 access pwr permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:1 - Core1 access spi_2 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_spi_2(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_R::new((self.bits & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 2:3 - Core1 access spi_3 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_spi_3(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_R::new(((self.bits >> 2) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 4:5 - Core1 access apb_ctrl permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_apb_ctrl(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_R::new(((self.bits >> 4) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 6:7 - Core1 access i2c_ext1 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_i2c_ext1(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_R::new(((self.bits >> 6) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 8:9 - Core1 access sdio_host permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_sdio_host(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_R::new(((self.bits >> 8) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 10:11 - Core1 access can permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_can(&self) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN_R::new(((self.bits >> 10) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 12:13 - Core1 access pwm1 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_pwm1(&self) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_R::new(((self.bits >> 12) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 14:15 - Core1 access i2s1 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_i2s1(&self) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_R::new(((self.bits >> 14) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 16:17 - Core1 access uart2 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_uart2(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2_R::new(((self.bits >> 16) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 22:23 - Core1 access rwbt permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_rwbt(&self) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_R::new(((self.bits >> 22) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 26:27 - Core1 access wifimac permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_wifimac(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_R::new(((self.bits >> 26) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 28:29 - Core1 access pwr permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_pwr(&self) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR_R::new(((self.bits >> 28) & 3) as u8)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_1_PIF_PMS_CONSTRAIN_7")
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_1_spi_2",
|
||||
&self.core_1_pif_pms_constrain_world_1_spi_2(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_1_spi_3",
|
||||
&self.core_1_pif_pms_constrain_world_1_spi_3(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_1_apb_ctrl",
|
||||
&self.core_1_pif_pms_constrain_world_1_apb_ctrl(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_1_i2c_ext1",
|
||||
&self.core_1_pif_pms_constrain_world_1_i2c_ext1(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_1_sdio_host",
|
||||
&self.core_1_pif_pms_constrain_world_1_sdio_host(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_1_can",
|
||||
&self.core_1_pif_pms_constrain_world_1_can(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_1_pwm1",
|
||||
&self.core_1_pif_pms_constrain_world_1_pwm1(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_1_i2s1",
|
||||
&self.core_1_pif_pms_constrain_world_1_i2s1(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_1_uart2",
|
||||
&self.core_1_pif_pms_constrain_world_1_uart2(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_1_rwbt",
|
||||
&self.core_1_pif_pms_constrain_world_1_rwbt(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_1_wifimac",
|
||||
&self.core_1_pif_pms_constrain_world_1_wifimac(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_1_pwr",
|
||||
&self.core_1_pif_pms_constrain_world_1_pwr(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:1 - Core1 access spi_2 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_spi_2(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_W<CORE_1_PIF_PMS_CONSTRAIN_7_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_W::new(self, 0)
|
||||
}
|
||||
#[doc = "Bits 2:3 - Core1 access spi_3 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_spi_3(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_W<CORE_1_PIF_PMS_CONSTRAIN_7_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_W::new(self, 2)
|
||||
}
|
||||
#[doc = "Bits 4:5 - Core1 access apb_ctrl permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_apb_ctrl(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_W<CORE_1_PIF_PMS_CONSTRAIN_7_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_W::new(self, 4)
|
||||
}
|
||||
#[doc = "Bits 6:7 - Core1 access i2c_ext1 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_i2c_ext1(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_W<CORE_1_PIF_PMS_CONSTRAIN_7_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_W::new(self, 6)
|
||||
}
|
||||
#[doc = "Bits 8:9 - Core1 access sdio_host permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_sdio_host(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_W<CORE_1_PIF_PMS_CONSTRAIN_7_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_W::new(self, 8)
|
||||
}
|
||||
#[doc = "Bits 10:11 - Core1 access can permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_can(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN_W<CORE_1_PIF_PMS_CONSTRAIN_7_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN_W::new(self, 10)
|
||||
}
|
||||
#[doc = "Bits 12:13 - Core1 access pwm1 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_pwm1(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_W<CORE_1_PIF_PMS_CONSTRAIN_7_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_W::new(self, 12)
|
||||
}
|
||||
#[doc = "Bits 14:15 - Core1 access i2s1 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_i2s1(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_W<CORE_1_PIF_PMS_CONSTRAIN_7_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_W::new(self, 14)
|
||||
}
|
||||
#[doc = "Bits 16:17 - Core1 access uart2 permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_uart2(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2_W<CORE_1_PIF_PMS_CONSTRAIN_7_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2_W::new(self, 16)
|
||||
}
|
||||
#[doc = "Bits 22:23 - Core1 access rwbt permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_rwbt(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_W<CORE_1_PIF_PMS_CONSTRAIN_7_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_W::new(self, 22)
|
||||
}
|
||||
#[doc = "Bits 26:27 - Core1 access wifimac permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_wifimac(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_W<CORE_1_PIF_PMS_CONSTRAIN_7_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_W::new(self, 26)
|
||||
}
|
||||
#[doc = "Bits 28:29 - Core1 access pwr permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_pwr(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR_W<CORE_1_PIF_PMS_CONSTRAIN_7_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR_W::new(self, 28)
|
||||
}
|
||||
}
|
||||
#[doc = "Core1 access peripherals permission configuration register 7.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_pif_pms_constrain_7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_1_pif_pms_constrain_7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_1_PIF_PMS_CONSTRAIN_7_SPEC;
|
||||
impl crate::RegisterSpec for CORE_1_PIF_PMS_CONSTRAIN_7_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_1_pif_pms_constrain_7::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_1_PIF_PMS_CONSTRAIN_7_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_1_pif_pms_constrain_7::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_1_PIF_PMS_CONSTRAIN_7_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_1_PIF_PMS_CONSTRAIN_7 to value 0x3cc3_ffff"]
|
||||
impl crate::Resettable for CORE_1_PIF_PMS_CONSTRAIN_7_SPEC {
|
||||
const RESET_VALUE: u32 = 0x3cc3_ffff;
|
||||
}
|
||||
@@ -0,0 +1,379 @@
|
||||
#[doc = "Register `CORE_1_PIF_PMS_CONSTRAIN_8` reader"]
|
||||
pub type R = crate::R<CORE_1_PIF_PMS_CONSTRAIN_8_SPEC>;
|
||||
#[doc = "Register `CORE_1_PIF_PMS_CONSTRAIN_8` writer"]
|
||||
pub type W = crate::W<CORE_1_PIF_PMS_CONSTRAIN_8_SPEC>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE` reader - Core1 access usb_device permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE` writer - Core1 access usb_device permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP` reader - Core1 access usb_wrap permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP` writer - Core1 access usb_wrap permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI` reader - Core1 access crypto_peri permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI` writer - Core1 access crypto_peri permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA` reader - Core1 access crypto_dma permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA` writer - Core1 access crypto_dma permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC` reader - Core1 access apb_adc permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC` writer - Core1 access apb_adc permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM` reader - Core1 access lcd_cam permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM` writer - Core1 access lcd_cam permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR` reader - Core1 access bt_pwr permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR` writer - Core1 access bt_pwr permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB` reader - Core1 access usb permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB` writer - Core1 access usb permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM` reader - Core1 access system permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM` writer - Core1 access system permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE` reader - Core1 access sensitive permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE` writer - Core1 access sensitive permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT` reader - Core1 access interrupt permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT` writer - Core1 access interrupt permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY` reader - Core1 access dma_copy permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY` writer - Core1 access dma_copy permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG` reader - Core1 access cache_config permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG` writer - Core1 access cache_config permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD` reader - Core1 access ad permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD` writer - Core1 access ad permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO` reader - Core1 access dio permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO` writer - Core1 access dio permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER` reader - Core1 access world_controller permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER` writer - Core1 access world_controller permission in world1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_W<'a, REG> =
|
||||
crate::FieldWriter<'a, REG, 2>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:1 - Core1 access usb_device permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_usb_device(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_R::new((self.bits & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 2:3 - Core1 access usb_wrap permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_usb_wrap(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_R::new(((self.bits >> 2) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 4:5 - Core1 access crypto_peri permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_crypto_peri(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_R::new(((self.bits >> 4) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 6:7 - Core1 access crypto_dma permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_crypto_dma(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_R::new(((self.bits >> 6) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 8:9 - Core1 access apb_adc permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_apb_adc(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_R::new(((self.bits >> 8) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 10:11 - Core1 access lcd_cam permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_lcd_cam(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_R::new(((self.bits >> 10) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 12:13 - Core1 access bt_pwr permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_bt_pwr(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_R::new(((self.bits >> 12) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 14:15 - Core1 access usb permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_usb(&self) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_R::new(((self.bits >> 14) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 16:17 - Core1 access system permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_system(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_R::new(((self.bits >> 16) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 18:19 - Core1 access sensitive permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_sensitive(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_R::new(((self.bits >> 18) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 20:21 - Core1 access interrupt permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_interrupt(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_R::new(((self.bits >> 20) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 22:23 - Core1 access dma_copy permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_dma_copy(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_R::new(((self.bits >> 22) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 24:25 - Core1 access cache_config permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_cache_config(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_R::new(((self.bits >> 24) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 26:27 - Core1 access ad permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_ad(&self) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD_R::new(((self.bits >> 26) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 28:29 - Core1 access dio permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_dio(&self) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO_R::new(((self.bits >> 28) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 30:31 - Core1 access world_controller permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_world_controller(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_R::new(((self.bits >> 30) & 3) as u8)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_1_PIF_PMS_CONSTRAIN_8")
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_1_usb_device",
|
||||
&self.core_1_pif_pms_constrain_world_1_usb_device(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_1_usb_wrap",
|
||||
&self.core_1_pif_pms_constrain_world_1_usb_wrap(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_1_crypto_peri",
|
||||
&self.core_1_pif_pms_constrain_world_1_crypto_peri(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_1_crypto_dma",
|
||||
&self.core_1_pif_pms_constrain_world_1_crypto_dma(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_1_apb_adc",
|
||||
&self.core_1_pif_pms_constrain_world_1_apb_adc(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_1_lcd_cam",
|
||||
&self.core_1_pif_pms_constrain_world_1_lcd_cam(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_1_bt_pwr",
|
||||
&self.core_1_pif_pms_constrain_world_1_bt_pwr(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_1_usb",
|
||||
&self.core_1_pif_pms_constrain_world_1_usb(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_1_system",
|
||||
&self.core_1_pif_pms_constrain_world_1_system(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_1_sensitive",
|
||||
&self.core_1_pif_pms_constrain_world_1_sensitive(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_1_interrupt",
|
||||
&self.core_1_pif_pms_constrain_world_1_interrupt(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_1_dma_copy",
|
||||
&self.core_1_pif_pms_constrain_world_1_dma_copy(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_1_cache_config",
|
||||
&self.core_1_pif_pms_constrain_world_1_cache_config(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_1_ad",
|
||||
&self.core_1_pif_pms_constrain_world_1_ad(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_1_dio",
|
||||
&self.core_1_pif_pms_constrain_world_1_dio(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_world_1_world_controller",
|
||||
&self.core_1_pif_pms_constrain_world_1_world_controller(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:1 - Core1 access usb_device permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_usb_device(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_W<CORE_1_PIF_PMS_CONSTRAIN_8_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_W::new(self, 0)
|
||||
}
|
||||
#[doc = "Bits 2:3 - Core1 access usb_wrap permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_usb_wrap(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_W<CORE_1_PIF_PMS_CONSTRAIN_8_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_W::new(self, 2)
|
||||
}
|
||||
#[doc = "Bits 4:5 - Core1 access crypto_peri permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_crypto_peri(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_W<CORE_1_PIF_PMS_CONSTRAIN_8_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_W::new(self, 4)
|
||||
}
|
||||
#[doc = "Bits 6:7 - Core1 access crypto_dma permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_crypto_dma(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_W<CORE_1_PIF_PMS_CONSTRAIN_8_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_W::new(self, 6)
|
||||
}
|
||||
#[doc = "Bits 8:9 - Core1 access apb_adc permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_apb_adc(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_W<CORE_1_PIF_PMS_CONSTRAIN_8_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_W::new(self, 8)
|
||||
}
|
||||
#[doc = "Bits 10:11 - Core1 access lcd_cam permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_lcd_cam(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_W<CORE_1_PIF_PMS_CONSTRAIN_8_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_W::new(self, 10)
|
||||
}
|
||||
#[doc = "Bits 12:13 - Core1 access bt_pwr permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_bt_pwr(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_W<CORE_1_PIF_PMS_CONSTRAIN_8_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_W::new(self, 12)
|
||||
}
|
||||
#[doc = "Bits 14:15 - Core1 access usb permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_usb(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_W<CORE_1_PIF_PMS_CONSTRAIN_8_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_W::new(self, 14)
|
||||
}
|
||||
#[doc = "Bits 16:17 - Core1 access system permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_system(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_W<CORE_1_PIF_PMS_CONSTRAIN_8_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_W::new(self, 16)
|
||||
}
|
||||
#[doc = "Bits 18:19 - Core1 access sensitive permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_sensitive(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_W<CORE_1_PIF_PMS_CONSTRAIN_8_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_W::new(self, 18)
|
||||
}
|
||||
#[doc = "Bits 20:21 - Core1 access interrupt permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_interrupt(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_W<CORE_1_PIF_PMS_CONSTRAIN_8_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_W::new(self, 20)
|
||||
}
|
||||
#[doc = "Bits 22:23 - Core1 access dma_copy permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_dma_copy(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_W<CORE_1_PIF_PMS_CONSTRAIN_8_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_W::new(self, 22)
|
||||
}
|
||||
#[doc = "Bits 24:25 - Core1 access cache_config permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_cache_config(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_W<CORE_1_PIF_PMS_CONSTRAIN_8_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_W::new(self, 24)
|
||||
}
|
||||
#[doc = "Bits 26:27 - Core1 access ad permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_ad(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD_W<CORE_1_PIF_PMS_CONSTRAIN_8_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD_W::new(self, 26)
|
||||
}
|
||||
#[doc = "Bits 28:29 - Core1 access dio permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_dio(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO_W<CORE_1_PIF_PMS_CONSTRAIN_8_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO_W::new(self, 28)
|
||||
}
|
||||
#[doc = "Bits 30:31 - Core1 access world_controller permission in world1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_world_1_world_controller(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_W<CORE_1_PIF_PMS_CONSTRAIN_8_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_W::new(self, 30)
|
||||
}
|
||||
}
|
||||
#[doc = "Core1 access peripherals permission configuration register 8.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_pif_pms_constrain_8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_1_pif_pms_constrain_8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_1_PIF_PMS_CONSTRAIN_8_SPEC;
|
||||
impl crate::RegisterSpec for CORE_1_PIF_PMS_CONSTRAIN_8_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_1_pif_pms_constrain_8::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_1_PIF_PMS_CONSTRAIN_8_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_1_pif_pms_constrain_8::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_1_PIF_PMS_CONSTRAIN_8_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_1_PIF_PMS_CONSTRAIN_8 to value 0xffff_ffff"]
|
||||
impl crate::Resettable for CORE_1_PIF_PMS_CONSTRAIN_8_SPEC {
|
||||
const RESET_VALUE: u32 = 0xffff_ffff;
|
||||
}
|
||||
@@ -0,0 +1,80 @@
|
||||
#[doc = "Register `CORE_1_PIF_PMS_CONSTRAIN_9` reader"]
|
||||
pub type R = crate::R<CORE_1_PIF_PMS_CONSTRAIN_9_SPEC>;
|
||||
#[doc = "Register `CORE_1_PIF_PMS_CONSTRAIN_9` writer"]
|
||||
pub type W = crate::W<CORE_1_PIF_PMS_CONSTRAIN_9_SPEC>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0` reader - RTCFast memory split address in world 0 for core1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_R = crate::FieldReader<u16>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0` writer - RTCFast memory split address in world 0 for core1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_W<'a, REG> =
|
||||
crate::FieldWriter<'a, REG, 11, u16>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1` reader - RTCFast memory split address in world 1 for core1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_R = crate::FieldReader<u16>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1` writer - RTCFast memory split address in world 1 for core1."]
|
||||
pub type CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_W<'a, REG> =
|
||||
crate::FieldWriter<'a, REG, 11, u16>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:10 - RTCFast memory split address in world 0 for core1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_rtcfast_spltaddr_world_0(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_R::new((self.bits & 0x07ff) as u16)
|
||||
}
|
||||
#[doc = "Bits 11:21 - RTCFast memory split address in world 1 for core1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_rtcfast_spltaddr_world_1(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_R {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_R::new(
|
||||
((self.bits >> 11) & 0x07ff) as u16,
|
||||
)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_1_PIF_PMS_CONSTRAIN_9")
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_rtcfast_spltaddr_world_0",
|
||||
&self.core_1_pif_pms_constrain_rtcfast_spltaddr_world_0(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_constrain_rtcfast_spltaddr_world_1",
|
||||
&self.core_1_pif_pms_constrain_rtcfast_spltaddr_world_1(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:10 - RTCFast memory split address in world 0 for core1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_rtcfast_spltaddr_world_0(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_W<CORE_1_PIF_PMS_CONSTRAIN_9_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_W::new(self, 0)
|
||||
}
|
||||
#[doc = "Bits 11:21 - RTCFast memory split address in world 1 for core1."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_constrain_rtcfast_spltaddr_world_1(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_W<CORE_1_PIF_PMS_CONSTRAIN_9_SPEC> {
|
||||
CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_W::new(self, 11)
|
||||
}
|
||||
}
|
||||
#[doc = "Core1 access peripherals permission configuration register 9.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_pif_pms_constrain_9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_1_pif_pms_constrain_9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_1_PIF_PMS_CONSTRAIN_9_SPEC;
|
||||
impl crate::RegisterSpec for CORE_1_PIF_PMS_CONSTRAIN_9_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_1_pif_pms_constrain_9::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_1_PIF_PMS_CONSTRAIN_9_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_1_pif_pms_constrain_9::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_1_PIF_PMS_CONSTRAIN_9_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_1_PIF_PMS_CONSTRAIN_9 to value 0x003f_ffff"]
|
||||
impl crate::Resettable for CORE_1_PIF_PMS_CONSTRAIN_9_SPEC {
|
||||
const RESET_VALUE: u32 = 0x003f_ffff;
|
||||
}
|
||||
@@ -0,0 +1,52 @@
|
||||
#[doc = "Register `CORE_1_PIF_PMS_MONITOR_0` reader"]
|
||||
pub type R = crate::R<CORE_1_PIF_PMS_MONITOR_0_SPEC>;
|
||||
#[doc = "Register `CORE_1_PIF_PMS_MONITOR_0` writer"]
|
||||
pub type W = crate::W<CORE_1_PIF_PMS_MONITOR_0_SPEC>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_MONITOR_LOCK` reader - Set 1 to lock core1 permission report registers."]
|
||||
pub type CORE_1_PIF_PMS_MONITOR_LOCK_R = crate::BitReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_MONITOR_LOCK` writer - Set 1 to lock core1 permission report registers."]
|
||||
pub type CORE_1_PIF_PMS_MONITOR_LOCK_W<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
impl R {
|
||||
#[doc = "Bit 0 - Set 1 to lock core1 permission report registers."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_monitor_lock(&self) -> CORE_1_PIF_PMS_MONITOR_LOCK_R {
|
||||
CORE_1_PIF_PMS_MONITOR_LOCK_R::new((self.bits & 1) != 0)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_1_PIF_PMS_MONITOR_0")
|
||||
.field(
|
||||
"core_1_pif_pms_monitor_lock",
|
||||
&self.core_1_pif_pms_monitor_lock(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bit 0 - Set 1 to lock core1 permission report registers."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_monitor_lock(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_MONITOR_LOCK_W<CORE_1_PIF_PMS_MONITOR_0_SPEC> {
|
||||
CORE_1_PIF_PMS_MONITOR_LOCK_W::new(self, 0)
|
||||
}
|
||||
}
|
||||
#[doc = "core1 permission report register 0.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_pif_pms_monitor_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_1_pif_pms_monitor_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_1_PIF_PMS_MONITOR_0_SPEC;
|
||||
impl crate::RegisterSpec for CORE_1_PIF_PMS_MONITOR_0_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_1_pif_pms_monitor_0::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_1_PIF_PMS_MONITOR_0_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_1_pif_pms_monitor_0::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_1_PIF_PMS_MONITOR_0_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_1_PIF_PMS_MONITOR_0 to value 0"]
|
||||
impl crate::Resettable for CORE_1_PIF_PMS_MONITOR_0_SPEC {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
@@ -0,0 +1,72 @@
|
||||
#[doc = "Register `CORE_1_PIF_PMS_MONITOR_1` reader"]
|
||||
pub type R = crate::R<CORE_1_PIF_PMS_MONITOR_1_SPEC>;
|
||||
#[doc = "Register `CORE_1_PIF_PMS_MONITOR_1` writer"]
|
||||
pub type W = crate::W<CORE_1_PIF_PMS_MONITOR_1_SPEC>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR` reader - Set 1 to clear interrupt that core1 initiate illegal PIF bus access."]
|
||||
pub type CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR_R = crate::BitReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR` writer - Set 1 to clear interrupt that core1 initiate illegal PIF bus access."]
|
||||
pub type CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_MONITOR_VIOLATE_EN` reader - Set 1 to enable interrupt that core1 initiate illegal PIF bus access."]
|
||||
pub type CORE_1_PIF_PMS_MONITOR_VIOLATE_EN_R = crate::BitReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_MONITOR_VIOLATE_EN` writer - Set 1 to enable interrupt that core1 initiate illegal PIF bus access."]
|
||||
pub type CORE_1_PIF_PMS_MONITOR_VIOLATE_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
impl R {
|
||||
#[doc = "Bit 0 - Set 1 to clear interrupt that core1 initiate illegal PIF bus access."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_monitor_violate_clr(&self) -> CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR_R {
|
||||
CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR_R::new((self.bits & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 1 - Set 1 to enable interrupt that core1 initiate illegal PIF bus access."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_monitor_violate_en(&self) -> CORE_1_PIF_PMS_MONITOR_VIOLATE_EN_R {
|
||||
CORE_1_PIF_PMS_MONITOR_VIOLATE_EN_R::new(((self.bits >> 1) & 1) != 0)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_1_PIF_PMS_MONITOR_1")
|
||||
.field(
|
||||
"core_1_pif_pms_monitor_violate_clr",
|
||||
&self.core_1_pif_pms_monitor_violate_clr(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_monitor_violate_en",
|
||||
&self.core_1_pif_pms_monitor_violate_en(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bit 0 - Set 1 to clear interrupt that core1 initiate illegal PIF bus access."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_monitor_violate_clr(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR_W<CORE_1_PIF_PMS_MONITOR_1_SPEC> {
|
||||
CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR_W::new(self, 0)
|
||||
}
|
||||
#[doc = "Bit 1 - Set 1 to enable interrupt that core1 initiate illegal PIF bus access."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_monitor_violate_en(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_MONITOR_VIOLATE_EN_W<CORE_1_PIF_PMS_MONITOR_1_SPEC> {
|
||||
CORE_1_PIF_PMS_MONITOR_VIOLATE_EN_W::new(self, 1)
|
||||
}
|
||||
}
|
||||
#[doc = "core1 permission report register 1.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_pif_pms_monitor_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_1_pif_pms_monitor_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_1_PIF_PMS_MONITOR_1_SPEC;
|
||||
impl crate::RegisterSpec for CORE_1_PIF_PMS_MONITOR_1_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_1_pif_pms_monitor_1::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_1_PIF_PMS_MONITOR_1_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_1_pif_pms_monitor_1::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_1_PIF_PMS_MONITOR_1_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_1_PIF_PMS_MONITOR_1 to value 0x03"]
|
||||
impl crate::Resettable for CORE_1_PIF_PMS_MONITOR_1_SPEC {
|
||||
const RESET_VALUE: u32 = 0x03;
|
||||
}
|
||||
@@ -0,0 +1,85 @@
|
||||
#[doc = "Register `CORE_1_PIF_PMS_MONITOR_2` reader"]
|
||||
pub type R = crate::R<CORE_1_PIF_PMS_MONITOR_2_SPEC>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR` reader - Record core1 illegal access interrupt state."]
|
||||
pub type CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_R = crate::BitReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0` reader - Record hport information when core1 initiate illegal access."]
|
||||
pub type CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_R = crate::BitReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE` reader - Record access type when core1 initate illegal access."]
|
||||
pub type CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE` reader - Record access direction when core1 initiate illegal access."]
|
||||
pub type CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_R = crate::BitReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD` reader - Record world information when core1 initiate illegal access."]
|
||||
pub type CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_R = crate::FieldReader;
|
||||
impl R {
|
||||
#[doc = "Bit 0 - Record core1 illegal access interrupt state."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_monitor_violate_intr(&self) -> CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_R {
|
||||
CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_R::new((self.bits & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 1 - Record hport information when core1 initiate illegal access."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_monitor_violate_status_hport_0(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_R {
|
||||
CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_R::new(((self.bits >> 1) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bits 2:4 - Record access type when core1 initate illegal access."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_monitor_violate_status_hsize(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_R {
|
||||
CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_R::new(((self.bits >> 2) & 7) as u8)
|
||||
}
|
||||
#[doc = "Bit 5 - Record access direction when core1 initiate illegal access."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_monitor_violate_status_hwrite(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_R {
|
||||
CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_R::new(((self.bits >> 5) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bits 6:7 - Record world information when core1 initiate illegal access."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_monitor_violate_status_hworld(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_R {
|
||||
CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_R::new(((self.bits >> 6) & 3) as u8)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_1_PIF_PMS_MONITOR_2")
|
||||
.field(
|
||||
"core_1_pif_pms_monitor_violate_intr",
|
||||
&self.core_1_pif_pms_monitor_violate_intr(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_monitor_violate_status_hport_0",
|
||||
&self.core_1_pif_pms_monitor_violate_status_hport_0(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_monitor_violate_status_hsize",
|
||||
&self.core_1_pif_pms_monitor_violate_status_hsize(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_monitor_violate_status_hwrite",
|
||||
&self.core_1_pif_pms_monitor_violate_status_hwrite(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_monitor_violate_status_hworld",
|
||||
&self.core_1_pif_pms_monitor_violate_status_hworld(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
#[doc = "core1 permission report register 2.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_pif_pms_monitor_2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_1_PIF_PMS_MONITOR_2_SPEC;
|
||||
impl crate::RegisterSpec for CORE_1_PIF_PMS_MONITOR_2_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_1_pif_pms_monitor_2::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_1_PIF_PMS_MONITOR_2_SPEC {}
|
||||
#[doc = "`reset()` method sets CORE_1_PIF_PMS_MONITOR_2 to value 0"]
|
||||
impl crate::Resettable for CORE_1_PIF_PMS_MONITOR_2_SPEC {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
@@ -0,0 +1,35 @@
|
||||
#[doc = "Register `CORE_1_PIF_PMS_MONITOR_3` reader"]
|
||||
pub type R = crate::R<CORE_1_PIF_PMS_MONITOR_3_SPEC>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR` reader - Record address information when core1 initiate illegal access."]
|
||||
pub type CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_R = crate::FieldReader<u32>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:31 - Record address information when core1 initiate illegal access."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_monitor_violate_status_haddr(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_R {
|
||||
CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_R::new(self.bits)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_1_PIF_PMS_MONITOR_3")
|
||||
.field(
|
||||
"core_1_pif_pms_monitor_violate_status_haddr",
|
||||
&self.core_1_pif_pms_monitor_violate_status_haddr(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
#[doc = "core1 permission report register 3.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_pif_pms_monitor_3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_1_PIF_PMS_MONITOR_3_SPEC;
|
||||
impl crate::RegisterSpec for CORE_1_PIF_PMS_MONITOR_3_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_1_pif_pms_monitor_3::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_1_PIF_PMS_MONITOR_3_SPEC {}
|
||||
#[doc = "`reset()` method sets CORE_1_PIF_PMS_MONITOR_3 to value 0"]
|
||||
impl crate::Resettable for CORE_1_PIF_PMS_MONITOR_3_SPEC {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
@@ -0,0 +1,76 @@
|
||||
#[doc = "Register `CORE_1_PIF_PMS_MONITOR_4` reader"]
|
||||
pub type R = crate::R<CORE_1_PIF_PMS_MONITOR_4_SPEC>;
|
||||
#[doc = "Register `CORE_1_PIF_PMS_MONITOR_4` writer"]
|
||||
pub type W = crate::W<CORE_1_PIF_PMS_MONITOR_4_SPEC>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR` reader - Set 1 to clear interrupt that core1 initiate unsupported access type."]
|
||||
pub type CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_R = crate::BitReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR` writer - Set 1 to clear interrupt that core1 initiate unsupported access type."]
|
||||
pub type CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN` reader - Set 1 to enable interrupt that core1 initiate unsupported access type."]
|
||||
pub type CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_R = crate::BitReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN` writer - Set 1 to enable interrupt that core1 initiate unsupported access type."]
|
||||
pub type CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
impl R {
|
||||
#[doc = "Bit 0 - Set 1 to clear interrupt that core1 initiate unsupported access type."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_monitor_nonword_violate_clr(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_R {
|
||||
CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_R::new((self.bits & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 1 - Set 1 to enable interrupt that core1 initiate unsupported access type."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_monitor_nonword_violate_en(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_R {
|
||||
CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_R::new(((self.bits >> 1) & 1) != 0)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_1_PIF_PMS_MONITOR_4")
|
||||
.field(
|
||||
"core_1_pif_pms_monitor_nonword_violate_clr",
|
||||
&self.core_1_pif_pms_monitor_nonword_violate_clr(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_monitor_nonword_violate_en",
|
||||
&self.core_1_pif_pms_monitor_nonword_violate_en(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bit 0 - Set 1 to clear interrupt that core1 initiate unsupported access type."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_monitor_nonword_violate_clr(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_W<CORE_1_PIF_PMS_MONITOR_4_SPEC> {
|
||||
CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_W::new(self, 0)
|
||||
}
|
||||
#[doc = "Bit 1 - Set 1 to enable interrupt that core1 initiate unsupported access type."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_monitor_nonword_violate_en(
|
||||
&mut self,
|
||||
) -> CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_W<CORE_1_PIF_PMS_MONITOR_4_SPEC> {
|
||||
CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_W::new(self, 1)
|
||||
}
|
||||
}
|
||||
#[doc = "core1 permission report register 4.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_pif_pms_monitor_4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_1_pif_pms_monitor_4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_1_PIF_PMS_MONITOR_4_SPEC;
|
||||
impl crate::RegisterSpec for CORE_1_PIF_PMS_MONITOR_4_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_1_pif_pms_monitor_4::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_1_PIF_PMS_MONITOR_4_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_1_pif_pms_monitor_4::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_1_PIF_PMS_MONITOR_4_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_1_PIF_PMS_MONITOR_4 to value 0x03"]
|
||||
impl crate::Resettable for CORE_1_PIF_PMS_MONITOR_4_SPEC {
|
||||
const RESET_VALUE: u32 = 0x03;
|
||||
}
|
||||
@@ -0,0 +1,61 @@
|
||||
#[doc = "Register `CORE_1_PIF_PMS_MONITOR_5` reader"]
|
||||
pub type R = crate::R<CORE_1_PIF_PMS_MONITOR_5_SPEC>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR` reader - Record core1 unsupported access type interrupt state."]
|
||||
pub type CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_R = crate::BitReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE` reader - Record access type when core1 initiate unsupported access type."]
|
||||
pub type CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_R = crate::FieldReader;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD` reader - Record world information when core1 initiate unsupported access type."]
|
||||
pub type CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_R = crate::FieldReader;
|
||||
impl R {
|
||||
#[doc = "Bit 0 - Record core1 unsupported access type interrupt state."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_monitor_nonword_violate_intr(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_R {
|
||||
CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_R::new((self.bits & 1) != 0)
|
||||
}
|
||||
#[doc = "Bits 1:2 - Record access type when core1 initiate unsupported access type."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_monitor_nonword_violate_status_hsize(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_R {
|
||||
CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_R::new(((self.bits >> 1) & 3) as u8)
|
||||
}
|
||||
#[doc = "Bits 3:4 - Record world information when core1 initiate unsupported access type."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_monitor_nonword_violate_status_hworld(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_R {
|
||||
CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_R::new(((self.bits >> 3) & 3) as u8)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_1_PIF_PMS_MONITOR_5")
|
||||
.field(
|
||||
"core_1_pif_pms_monitor_nonword_violate_intr",
|
||||
&self.core_1_pif_pms_monitor_nonword_violate_intr(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_monitor_nonword_violate_status_hsize",
|
||||
&self.core_1_pif_pms_monitor_nonword_violate_status_hsize(),
|
||||
)
|
||||
.field(
|
||||
"core_1_pif_pms_monitor_nonword_violate_status_hworld",
|
||||
&self.core_1_pif_pms_monitor_nonword_violate_status_hworld(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
#[doc = "core1 permission report register 5.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_pif_pms_monitor_5::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_1_PIF_PMS_MONITOR_5_SPEC;
|
||||
impl crate::RegisterSpec for CORE_1_PIF_PMS_MONITOR_5_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_1_pif_pms_monitor_5::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_1_PIF_PMS_MONITOR_5_SPEC {}
|
||||
#[doc = "`reset()` method sets CORE_1_PIF_PMS_MONITOR_5 to value 0"]
|
||||
impl crate::Resettable for CORE_1_PIF_PMS_MONITOR_5_SPEC {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
@@ -0,0 +1,35 @@
|
||||
#[doc = "Register `CORE_1_PIF_PMS_MONITOR_6` reader"]
|
||||
pub type R = crate::R<CORE_1_PIF_PMS_MONITOR_6_SPEC>;
|
||||
#[doc = "Field `CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR` reader - Record address information when core1 initiate unsupported access type."]
|
||||
pub type CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_R = crate::FieldReader<u32>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:31 - Record address information when core1 initiate unsupported access type."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_pif_pms_monitor_nonword_violate_status_haddr(
|
||||
&self,
|
||||
) -> CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_R {
|
||||
CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_R::new(self.bits)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_1_PIF_PMS_MONITOR_6")
|
||||
.field(
|
||||
"core_1_pif_pms_monitor_nonword_violate_status_haddr",
|
||||
&self.core_1_pif_pms_monitor_nonword_violate_status_haddr(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
#[doc = "core1 permission report register 6.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_pif_pms_monitor_6::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_1_PIF_PMS_MONITOR_6_SPEC;
|
||||
impl crate::RegisterSpec for CORE_1_PIF_PMS_MONITOR_6_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_1_pif_pms_monitor_6::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_1_PIF_PMS_MONITOR_6_SPEC {}
|
||||
#[doc = "`reset()` method sets CORE_1_PIF_PMS_MONITOR_6 to value 0"]
|
||||
impl crate::Resettable for CORE_1_PIF_PMS_MONITOR_6_SPEC {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
@@ -0,0 +1,52 @@
|
||||
#[doc = "Register `CORE_1_REGION_PMS_CONSTRAIN_0` reader"]
|
||||
pub type R = crate::R<CORE_1_REGION_PMS_CONSTRAIN_0_SPEC>;
|
||||
#[doc = "Register `CORE_1_REGION_PMS_CONSTRAIN_0` writer"]
|
||||
pub type W = crate::W<CORE_1_REGION_PMS_CONSTRAIN_0_SPEC>;
|
||||
#[doc = "Field `CORE_1_REGION_PMS_CONSTRAIN_LOCK` reader - Set 1 to lock core1 region permission registers."]
|
||||
pub type CORE_1_REGION_PMS_CONSTRAIN_LOCK_R = crate::BitReader;
|
||||
#[doc = "Field `CORE_1_REGION_PMS_CONSTRAIN_LOCK` writer - Set 1 to lock core1 region permission registers."]
|
||||
pub type CORE_1_REGION_PMS_CONSTRAIN_LOCK_W<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
impl R {
|
||||
#[doc = "Bit 0 - Set 1 to lock core1 region permission registers."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_region_pms_constrain_lock(&self) -> CORE_1_REGION_PMS_CONSTRAIN_LOCK_R {
|
||||
CORE_1_REGION_PMS_CONSTRAIN_LOCK_R::new((self.bits & 1) != 0)
|
||||
}
|
||||
}
|
||||
#[cfg(feature = "impl-register-debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("CORE_1_REGION_PMS_CONSTRAIN_0")
|
||||
.field(
|
||||
"core_1_region_pms_constrain_lock",
|
||||
&self.core_1_region_pms_constrain_lock(),
|
||||
)
|
||||
.finish()
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bit 0 - Set 1 to lock core1 region permission registers."]
|
||||
#[inline(always)]
|
||||
pub fn core_1_region_pms_constrain_lock(
|
||||
&mut self,
|
||||
) -> CORE_1_REGION_PMS_CONSTRAIN_LOCK_W<CORE_1_REGION_PMS_CONSTRAIN_0_SPEC> {
|
||||
CORE_1_REGION_PMS_CONSTRAIN_LOCK_W::new(self, 0)
|
||||
}
|
||||
}
|
||||
#[doc = "core1 region permission register 0.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_1_region_pms_constrain_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_1_region_pms_constrain_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CORE_1_REGION_PMS_CONSTRAIN_0_SPEC;
|
||||
impl crate::RegisterSpec for CORE_1_REGION_PMS_CONSTRAIN_0_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`core_1_region_pms_constrain_0::R`](R) reader structure"]
|
||||
impl crate::Readable for CORE_1_REGION_PMS_CONSTRAIN_0_SPEC {}
|
||||
#[doc = "`write(|w| ..)` method takes [`core_1_region_pms_constrain_0::W`](W) writer structure"]
|
||||
impl crate::Writable for CORE_1_REGION_PMS_CONSTRAIN_0_SPEC {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets CORE_1_REGION_PMS_CONSTRAIN_0 to value 0"]
|
||||
impl crate::Resettable for CORE_1_REGION_PMS_CONSTRAIN_0_SPEC {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
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