feat: add display UI with splash screen, dashboard, and RSSI sparkline

Implement full SSD1306 OLED display support:
- Splash screen on boot (1.5s) with project name, version, board
- Dashboard showing radio state, config, counters, RSSI/SNR
- RSSI history sparkline (64-sample ring buffer, 2px-wide bars)
- DisplayOn/DisplayOff host commands routed via dedicated channel
- Pure render functions against generic DrawTarget (no hardware coupling)
- Display on/off control bypasses radio task entirely

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>

vendor/esp32s3/src/sha/busy.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `BUSY` reader"]
+pub type R = crate::R<BUSY_SPEC>;
+#[doc = "Field `STATE` reader - sha busy state. 1'b0: idle 1'b1: busy"]
+pub type STATE_R = crate::BitReader;
+impl R {
+    #[doc = "Bit 0 - sha busy state. 1'b0: idle 1'b1: busy"]
+    #[inline(always)]
+    pub fn state(&self) -> STATE_R {
+        STATE_R::new((self.bits & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("BUSY")
+            .field("state", &self.state())
+            .finish()
+    }
+}
+#[doc = "Busy register.\n\nYou can [`read`](crate::Reg::read) this register and get [`busy::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct BUSY_SPEC;
+impl crate::RegisterSpec for BUSY_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`busy::R`](R) reader structure"]
+impl crate::Readable for BUSY_SPEC {}
+#[doc = "`reset()` method sets BUSY to value 0"]
+impl crate::Resettable for BUSY_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sha/clear_irq.rs

@@ -0,0 +1,32 @@
+#[doc = "Register `CLEAR_IRQ` writer"]
+pub type W = crate::W<CLEAR_IRQ_SPEC>;
+#[doc = "Field `CLEAR_INTERRUPT` writer - clear sha interrupt"]
+pub type CLEAR_INTERRUPT_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for crate::generic::Reg<CLEAR_IRQ_SPEC> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "(not readable)")
+    }
+}
+impl W {
+    #[doc = "Bit 0 - clear sha interrupt"]
+    #[inline(always)]
+    pub fn clear_interrupt(&mut self) -> CLEAR_INTERRUPT_W<CLEAR_IRQ_SPEC> {
+        CLEAR_INTERRUPT_W::new(self, 0)
+    }
+}
+#[doc = "Interrupt clear register.\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clear_irq::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CLEAR_IRQ_SPEC;
+impl crate::RegisterSpec for CLEAR_IRQ_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [`clear_irq::W`](W) writer structure"]
+impl crate::Writable for CLEAR_IRQ_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CLEAR_IRQ to value 0"]
+impl crate::Resettable for CLEAR_IRQ_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sha/continue_.rs

@@ -0,0 +1,32 @@
+#[doc = "Register `CONTINUE` writer"]
+pub type W = crate::W<CONTINUE_SPEC>;
+#[doc = "Field `CONTINUE` writer - reserved."]
+pub type CONTINUE_W<'a, REG> = crate::FieldWriter<'a, REG, 31, u32>;
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for crate::generic::Reg<CONTINUE_SPEC> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "(not readable)")
+    }
+}
+impl W {
+    #[doc = "Bits 1:31 - reserved."]
+    #[inline(always)]
+    pub fn continue_(&mut self) -> CONTINUE_W<CONTINUE_SPEC> {
+        CONTINUE_W::new(self, 1)
+    }
+}
+#[doc = "Typical SHA configuration register 1.\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`continue_::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CONTINUE_SPEC;
+impl crate::RegisterSpec for CONTINUE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [`continue_::W`](W) writer structure"]
+impl crate::Writable for CONTINUE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CONTINUE to value 0"]
+impl crate::Resettable for CONTINUE_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sha/date.rs

@@ -0,0 +1,45 @@
+#[doc = "Register `DATE` reader"]
+pub type R = crate::R<DATE_SPEC>;
+#[doc = "Register `DATE` writer"]
+pub type W = crate::W<DATE_SPEC>;
+#[doc = "Field `DATE` reader - sha date information/ sha version information"]
+pub type DATE_R = crate::FieldReader<u32>;
+#[doc = "Field `DATE` writer - sha date information/ sha version information"]
+pub type DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>;
+impl R {
+    #[doc = "Bits 0:29 - sha date information/ sha version information"]
+    #[inline(always)]
+    pub fn date(&self) -> DATE_R {
+        DATE_R::new(self.bits & 0x3fff_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DATE").field("date", &self.date()).finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:29 - sha date information/ sha version information"]
+    #[inline(always)]
+    pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
+        DATE_W::new(self, 0)
+    }
+}
+#[doc = "Date register.\n\nYou can [`read`](crate::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DATE_SPEC;
+impl crate::RegisterSpec for DATE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`date::R`](R) reader structure"]
+impl crate::Readable for DATE_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"]
+impl crate::Writable for DATE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DATE to value 0x2019_0402"]
+impl crate::Resettable for DATE_SPEC {
+    const RESET_VALUE: u32 = 0x2019_0402;
+}

vendor/esp32s3/src/sha/dma_block_num.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `DMA_BLOCK_NUM` reader"]
+pub type R = crate::R<DMA_BLOCK_NUM_SPEC>;
+#[doc = "Register `DMA_BLOCK_NUM` writer"]
+pub type W = crate::W<DMA_BLOCK_NUM_SPEC>;
+#[doc = "Field `DMA_BLOCK_NUM` reader - dma-sha block number"]
+pub type DMA_BLOCK_NUM_R = crate::FieldReader;
+#[doc = "Field `DMA_BLOCK_NUM` writer - dma-sha block number"]
+pub type DMA_BLOCK_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
+impl R {
+    #[doc = "Bits 0:5 - dma-sha block number"]
+    #[inline(always)]
+    pub fn dma_block_num(&self) -> DMA_BLOCK_NUM_R {
+        DMA_BLOCK_NUM_R::new((self.bits & 0x3f) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DMA_BLOCK_NUM")
+            .field("dma_block_num", &self.dma_block_num())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:5 - dma-sha block number"]
+    #[inline(always)]
+    pub fn dma_block_num(&mut self) -> DMA_BLOCK_NUM_W<DMA_BLOCK_NUM_SPEC> {
+        DMA_BLOCK_NUM_W::new(self, 0)
+    }
+}
+#[doc = "DMA configuration register 0.\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_block_num::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_block_num::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DMA_BLOCK_NUM_SPEC;
+impl crate::RegisterSpec for DMA_BLOCK_NUM_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`dma_block_num::R`](R) reader structure"]
+impl crate::Readable for DMA_BLOCK_NUM_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`dma_block_num::W`](W) writer structure"]
+impl crate::Writable for DMA_BLOCK_NUM_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DMA_BLOCK_NUM to value 0"]
+impl crate::Resettable for DMA_BLOCK_NUM_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sha/dma_continue.rs

@@ -0,0 +1,32 @@
+#[doc = "Register `DMA_CONTINUE` writer"]
+pub type W = crate::W<DMA_CONTINUE_SPEC>;
+#[doc = "Field `DMA_CONTINUE` writer - continue dma-sha"]
+pub type DMA_CONTINUE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for crate::generic::Reg<DMA_CONTINUE_SPEC> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "(not readable)")
+    }
+}
+impl W {
+    #[doc = "Bit 0 - continue dma-sha"]
+    #[inline(always)]
+    pub fn dma_continue(&mut self) -> DMA_CONTINUE_W<DMA_CONTINUE_SPEC> {
+        DMA_CONTINUE_W::new(self, 0)
+    }
+}
+#[doc = "DMA configuration register 2.\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_continue::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DMA_CONTINUE_SPEC;
+impl crate::RegisterSpec for DMA_CONTINUE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [`dma_continue::W`](W) writer structure"]
+impl crate::Writable for DMA_CONTINUE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DMA_CONTINUE to value 0"]
+impl crate::Resettable for DMA_CONTINUE_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sha/dma_start.rs

@@ -0,0 +1,32 @@
+#[doc = "Register `DMA_START` writer"]
+pub type W = crate::W<DMA_START_SPEC>;
+#[doc = "Field `DMA_START` writer - start dma-sha"]
+pub type DMA_START_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for crate::generic::Reg<DMA_START_SPEC> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "(not readable)")
+    }
+}
+impl W {
+    #[doc = "Bit 0 - start dma-sha"]
+    #[inline(always)]
+    pub fn dma_start(&mut self) -> DMA_START_W<DMA_START_SPEC> {
+        DMA_START_W::new(self, 0)
+    }
+}
+#[doc = "DMA configuration register 1.\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_start::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DMA_START_SPEC;
+impl crate::RegisterSpec for DMA_START_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [`dma_start::W`](W) writer structure"]
+impl crate::Writable for DMA_START_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DMA_START to value 0"]
+impl crate::Resettable for DMA_START_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sha/h_mem.rs

@@ -0,0 +1,28 @@
+#[doc = "Register `H_MEM[%s]` reader"]
+pub type R = crate::R<H_MEM_SPEC>;
+#[doc = "Register `H_MEM[%s]` writer"]
+pub type W = crate::W<H_MEM_SPEC>;
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+impl W {}
+#[doc = "Sha H memory which contains intermediate hash or finial hash.\n\nYou can [`read`](crate::Reg::read) this register and get [`h_mem::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`h_mem::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct H_MEM_SPEC;
+impl crate::RegisterSpec for H_MEM_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`h_mem::R`](R) reader structure"]
+impl crate::Readable for H_MEM_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`h_mem::W`](W) writer structure"]
+impl crate::Writable for H_MEM_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets H_MEM[%s] to value 0"]
+impl crate::Resettable for H_MEM_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sha/irq_ena.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `IRQ_ENA` reader"]
+pub type R = crate::R<IRQ_ENA_SPEC>;
+#[doc = "Register `IRQ_ENA` writer"]
+pub type W = crate::W<IRQ_ENA_SPEC>;
+#[doc = "Field `INTERRUPT_ENA` reader - sha interrupt enable register. 1'b0: disable(default) 1'b1: enable"]
+pub type INTERRUPT_ENA_R = crate::BitReader;
+#[doc = "Field `INTERRUPT_ENA` writer - sha interrupt enable register. 1'b0: disable(default) 1'b1: enable"]
+pub type INTERRUPT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - sha interrupt enable register. 1'b0: disable(default) 1'b1: enable"]
+    #[inline(always)]
+    pub fn interrupt_ena(&self) -> INTERRUPT_ENA_R {
+        INTERRUPT_ENA_R::new((self.bits & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("IRQ_ENA")
+            .field("interrupt_ena", &self.interrupt_ena())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - sha interrupt enable register. 1'b0: disable(default) 1'b1: enable"]
+    #[inline(always)]
+    pub fn interrupt_ena(&mut self) -> INTERRUPT_ENA_W<IRQ_ENA_SPEC> {
+        INTERRUPT_ENA_W::new(self, 0)
+    }
+}
+#[doc = "Interrupt enable register.\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct IRQ_ENA_SPEC;
+impl crate::RegisterSpec for IRQ_ENA_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`irq_ena::R`](R) reader structure"]
+impl crate::Readable for IRQ_ENA_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`irq_ena::W`](W) writer structure"]
+impl crate::Writable for IRQ_ENA_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets IRQ_ENA to value 0"]
+impl crate::Resettable for IRQ_ENA_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sha/m_mem.rs

@@ -0,0 +1,28 @@
+#[doc = "Register `M_MEM[%s]` reader"]
+pub type R = crate::R<M_MEM_SPEC>;
+#[doc = "Register `M_MEM[%s]` writer"]
+pub type W = crate::W<M_MEM_SPEC>;
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+impl W {}
+#[doc = "Sha M memory which contains message.\n\nYou can [`read`](crate::Reg::read) this register and get [`m_mem::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`m_mem::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct M_MEM_SPEC;
+impl crate::RegisterSpec for M_MEM_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`m_mem::R`](R) reader structure"]
+impl crate::Readable for M_MEM_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`m_mem::W`](W) writer structure"]
+impl crate::Writable for M_MEM_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets M_MEM[%s] to value 0"]
+impl crate::Resettable for M_MEM_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sha/mode.rs

@@ -0,0 +1,45 @@
+#[doc = "Register `MODE` reader"]
+pub type R = crate::R<MODE_SPEC>;
+#[doc = "Register `MODE` writer"]
+pub type W = crate::W<MODE_SPEC>;
+#[doc = "Field `MODE` reader - sha mode"]
+pub type MODE_R = crate::FieldReader;
+#[doc = "Field `MODE` writer - sha mode"]
+pub type MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+impl R {
+    #[doc = "Bits 0:2 - sha mode"]
+    #[inline(always)]
+    pub fn mode(&self) -> MODE_R {
+        MODE_R::new((self.bits & 7) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("MODE").field("mode", &self.mode()).finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:2 - sha mode"]
+    #[inline(always)]
+    pub fn mode(&mut self) -> MODE_W<MODE_SPEC> {
+        MODE_W::new(self, 0)
+    }
+}
+#[doc = "Initial configuration register.\n\nYou can [`read`](crate::Reg::read) this register and get [`mode::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mode::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct MODE_SPEC;
+impl crate::RegisterSpec for MODE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`mode::R`](R) reader structure"]
+impl crate::Readable for MODE_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`mode::W`](W) writer structure"]
+impl crate::Writable for MODE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets MODE to value 0"]
+impl crate::Resettable for MODE_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sha/start.rs

@@ -0,0 +1,32 @@
+#[doc = "Register `START` writer"]
+pub type W = crate::W<START_SPEC>;
+#[doc = "Field `START` writer - reserved."]
+pub type START_W<'a, REG> = crate::FieldWriter<'a, REG, 31, u32>;
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for crate::generic::Reg<START_SPEC> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "(not readable)")
+    }
+}
+impl W {
+    #[doc = "Bits 1:31 - reserved."]
+    #[inline(always)]
+    pub fn start(&mut self) -> START_W<START_SPEC> {
+        START_W::new(self, 1)
+    }
+}
+#[doc = "Typical SHA configuration register 0.\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`start::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct START_SPEC;
+impl crate::RegisterSpec for START_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [`start::W`](W) writer structure"]
+impl crate::Writable for START_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets START to value 0"]
+impl crate::Resettable for START_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sha/t_length.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `T_LENGTH` reader"]
+pub type R = crate::R<T_LENGTH_SPEC>;
+#[doc = "Register `T_LENGTH` writer"]
+pub type W = crate::W<T_LENGTH_SPEC>;
+#[doc = "Field `T_LENGTH` reader - sha t_length(used if and only if mode == sha_256/t)"]
+pub type T_LENGTH_R = crate::FieldReader;
+#[doc = "Field `T_LENGTH` writer - sha t_length(used if and only if mode == sha_256/t)"]
+pub type T_LENGTH_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
+impl R {
+    #[doc = "Bits 0:5 - sha t_length(used if and only if mode == sha_256/t)"]
+    #[inline(always)]
+    pub fn t_length(&self) -> T_LENGTH_R {
+        T_LENGTH_R::new((self.bits & 0x3f) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("T_LENGTH")
+            .field("t_length", &self.t_length())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:5 - sha t_length(used if and only if mode == sha_256/t)"]
+    #[inline(always)]
+    pub fn t_length(&mut self) -> T_LENGTH_W<T_LENGTH_SPEC> {
+        T_LENGTH_W::new(self, 0)
+    }
+}
+#[doc = "SHA 512/t configuration register 1.\n\nYou can [`read`](crate::Reg::read) this register and get [`t_length::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`t_length::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct T_LENGTH_SPEC;
+impl crate::RegisterSpec for T_LENGTH_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`t_length::R`](R) reader structure"]
+impl crate::Readable for T_LENGTH_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`t_length::W`](W) writer structure"]
+impl crate::Writable for T_LENGTH_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets T_LENGTH to value 0"]
+impl crate::Resettable for T_LENGTH_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/sha/t_string.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `T_STRING` reader"]
+pub type R = crate::R<T_STRING_SPEC>;
+#[doc = "Register `T_STRING` writer"]
+pub type W = crate::W<T_STRING_SPEC>;
+#[doc = "Field `T_STRING` reader - sha t_string(used if and only if mode == sha_256/t)"]
+pub type T_STRING_R = crate::FieldReader<u32>;
+#[doc = "Field `T_STRING` writer - sha t_string(used if and only if mode == sha_256/t)"]
+pub type T_STRING_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - sha t_string(used if and only if mode == sha_256/t)"]
+    #[inline(always)]
+    pub fn t_string(&self) -> T_STRING_R {
+        T_STRING_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("T_STRING")
+            .field("t_string", &self.t_string())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - sha t_string(used if and only if mode == sha_256/t)"]
+    #[inline(always)]
+    pub fn t_string(&mut self) -> T_STRING_W<T_STRING_SPEC> {
+        T_STRING_W::new(self, 0)
+    }
+}
+#[doc = "SHA 512/t configuration register 0.\n\nYou can [`read`](crate::Reg::read) this register and get [`t_string::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`t_string::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct T_STRING_SPEC;
+impl crate::RegisterSpec for T_STRING_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`t_string::R`](R) reader structure"]
+impl crate::Readable for T_STRING_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`t_string::W`](W) writer structure"]
+impl crate::Writable for T_STRING_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets T_STRING to value 0"]
+impl crate::Resettable for T_STRING_SPEC {
+    const RESET_VALUE: u32 = 0;
+}