feat: add display UI with splash screen, dashboard, and RSSI sparkline

Implement full SSD1306 OLED display support:
- Splash screen on boot (1.5s) with project name, version, board
- Dashboard showing radio state, config, counters, RSSI/SNR
- RSSI history sparkline (64-sample ring buffer, 2px-wide bars)
- DisplayOn/DisplayOff host commands routed via dedicated channel
- Pure render functions against generic DrawTarget (no hardware coupling)
- Display on/off control bypasses radio task entirely

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>

vendor/esp32s3/src/systimer/comp_load.rs

@@ -0,0 +1,32 @@
+#[doc = "Register `COMP%s_LOAD` writer"]
+pub type W = crate::W<COMP_LOAD_SPEC>;
+#[doc = "Field `LOAD` writer - timer comp0 sync enable signal"]
+pub type LOAD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for crate::generic::Reg<COMP_LOAD_SPEC> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "(not readable)")
+    }
+}
+impl W {
+    #[doc = "Bit 0 - timer comp0 sync enable signal"]
+    #[inline(always)]
+    pub fn load(&mut self) -> LOAD_W<COMP_LOAD_SPEC> {
+        LOAD_W::new(self, 0)
+    }
+}
+#[doc = "system timer comp%s conf sync register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`comp_load::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct COMP_LOAD_SPEC;
+impl crate::RegisterSpec for COMP_LOAD_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [`comp_load::W`](W) writer structure"]
+impl crate::Writable for COMP_LOAD_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets COMP%s_LOAD to value 0"]
+impl crate::Resettable for COMP_LOAD_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/systimer/conf.rs

@@ -0,0 +1,209 @@
+#[doc = "Register `CONF` reader"]
+pub type R = crate::R<CONF_SPEC>;
+#[doc = "Register `CONF` writer"]
+pub type W = crate::W<CONF_SPEC>;
+#[doc = "Field `SYSTIMER_CLK_FO` reader - systimer clock force on"]
+pub type SYSTIMER_CLK_FO_R = crate::BitReader;
+#[doc = "Field `SYSTIMER_CLK_FO` writer - systimer clock force on"]
+pub type SYSTIMER_CLK_FO_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TARGET2_WORK_EN` reader - target2 work enable"]
+pub type TARGET2_WORK_EN_R = crate::BitReader;
+#[doc = "Field `TARGET2_WORK_EN` writer - target2 work enable"]
+pub type TARGET2_WORK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TARGET1_WORK_EN` reader - target1 work enable"]
+pub type TARGET1_WORK_EN_R = crate::BitReader;
+#[doc = "Field `TARGET1_WORK_EN` writer - target1 work enable"]
+pub type TARGET1_WORK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TARGET0_WORK_EN` reader - target0 work enable"]
+pub type TARGET0_WORK_EN_R = crate::BitReader;
+#[doc = "Field `TARGET0_WORK_EN` writer - target0 work enable"]
+pub type TARGET0_WORK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER_UNIT1_CORE1_STALL_EN` reader - If timer unit1 is stalled when core1 stalled"]
+pub type TIMER_UNIT1_CORE1_STALL_EN_R = crate::BitReader;
+#[doc = "Field `TIMER_UNIT1_CORE1_STALL_EN` writer - If timer unit1 is stalled when core1 stalled"]
+pub type TIMER_UNIT1_CORE1_STALL_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER_UNIT1_CORE0_STALL_EN` reader - If timer unit1 is stalled when core0 stalled"]
+pub type TIMER_UNIT1_CORE0_STALL_EN_R = crate::BitReader;
+#[doc = "Field `TIMER_UNIT1_CORE0_STALL_EN` writer - If timer unit1 is stalled when core0 stalled"]
+pub type TIMER_UNIT1_CORE0_STALL_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER_UNIT0_CORE1_STALL_EN` reader - If timer unit0 is stalled when core1 stalled"]
+pub type TIMER_UNIT0_CORE1_STALL_EN_R = crate::BitReader;
+#[doc = "Field `TIMER_UNIT0_CORE1_STALL_EN` writer - If timer unit0 is stalled when core1 stalled"]
+pub type TIMER_UNIT0_CORE1_STALL_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER_UNIT0_CORE0_STALL_EN` reader - If timer unit0 is stalled when core0 stalled"]
+pub type TIMER_UNIT0_CORE0_STALL_EN_R = crate::BitReader;
+#[doc = "Field `TIMER_UNIT0_CORE0_STALL_EN` writer - If timer unit0 is stalled when core0 stalled"]
+pub type TIMER_UNIT0_CORE0_STALL_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER_UNIT1_WORK_EN` reader - timer unit1 work enable"]
+pub type TIMER_UNIT1_WORK_EN_R = crate::BitReader;
+#[doc = "Field `TIMER_UNIT1_WORK_EN` writer - timer unit1 work enable"]
+pub type TIMER_UNIT1_WORK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER_UNIT0_WORK_EN` reader - timer unit0 work enable"]
+pub type TIMER_UNIT0_WORK_EN_R = crate::BitReader;
+#[doc = "Field `TIMER_UNIT0_WORK_EN` writer - timer unit0 work enable"]
+pub type TIMER_UNIT0_WORK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CLK_EN` reader - register file clk gating"]
+pub type CLK_EN_R = crate::BitReader;
+#[doc = "Field `CLK_EN` writer - register file clk gating"]
+pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - systimer clock force on"]
+    #[inline(always)]
+    pub fn systimer_clk_fo(&self) -> SYSTIMER_CLK_FO_R {
+        SYSTIMER_CLK_FO_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 22 - target2 work enable"]
+    #[inline(always)]
+    pub fn target2_work_en(&self) -> TARGET2_WORK_EN_R {
+        TARGET2_WORK_EN_R::new(((self.bits >> 22) & 1) != 0)
+    }
+    #[doc = "Bit 23 - target1 work enable"]
+    #[inline(always)]
+    pub fn target1_work_en(&self) -> TARGET1_WORK_EN_R {
+        TARGET1_WORK_EN_R::new(((self.bits >> 23) & 1) != 0)
+    }
+    #[doc = "Bit 24 - target0 work enable"]
+    #[inline(always)]
+    pub fn target0_work_en(&self) -> TARGET0_WORK_EN_R {
+        TARGET0_WORK_EN_R::new(((self.bits >> 24) & 1) != 0)
+    }
+    #[doc = "Bit 25 - If timer unit1 is stalled when core1 stalled"]
+    #[inline(always)]
+    pub fn timer_unit1_core1_stall_en(&self) -> TIMER_UNIT1_CORE1_STALL_EN_R {
+        TIMER_UNIT1_CORE1_STALL_EN_R::new(((self.bits >> 25) & 1) != 0)
+    }
+    #[doc = "Bit 26 - If timer unit1 is stalled when core0 stalled"]
+    #[inline(always)]
+    pub fn timer_unit1_core0_stall_en(&self) -> TIMER_UNIT1_CORE0_STALL_EN_R {
+        TIMER_UNIT1_CORE0_STALL_EN_R::new(((self.bits >> 26) & 1) != 0)
+    }
+    #[doc = "Bit 27 - If timer unit0 is stalled when core1 stalled"]
+    #[inline(always)]
+    pub fn timer_unit0_core1_stall_en(&self) -> TIMER_UNIT0_CORE1_STALL_EN_R {
+        TIMER_UNIT0_CORE1_STALL_EN_R::new(((self.bits >> 27) & 1) != 0)
+    }
+    #[doc = "Bit 28 - If timer unit0 is stalled when core0 stalled"]
+    #[inline(always)]
+    pub fn timer_unit0_core0_stall_en(&self) -> TIMER_UNIT0_CORE0_STALL_EN_R {
+        TIMER_UNIT0_CORE0_STALL_EN_R::new(((self.bits >> 28) & 1) != 0)
+    }
+    #[doc = "Bit 29 - timer unit1 work enable"]
+    #[inline(always)]
+    pub fn timer_unit1_work_en(&self) -> TIMER_UNIT1_WORK_EN_R {
+        TIMER_UNIT1_WORK_EN_R::new(((self.bits >> 29) & 1) != 0)
+    }
+    #[doc = "Bit 30 - timer unit0 work enable"]
+    #[inline(always)]
+    pub fn timer_unit0_work_en(&self) -> TIMER_UNIT0_WORK_EN_R {
+        TIMER_UNIT0_WORK_EN_R::new(((self.bits >> 30) & 1) != 0)
+    }
+    #[doc = "Bit 31 - register file clk gating"]
+    #[inline(always)]
+    pub fn clk_en(&self) -> CLK_EN_R {
+        CLK_EN_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CONF")
+            .field("systimer_clk_fo", &self.systimer_clk_fo())
+            .field("target2_work_en", &self.target2_work_en())
+            .field("target1_work_en", &self.target1_work_en())
+            .field("target0_work_en", &self.target0_work_en())
+            .field(
+                "timer_unit1_core1_stall_en",
+                &self.timer_unit1_core1_stall_en(),
+            )
+            .field(
+                "timer_unit1_core0_stall_en",
+                &self.timer_unit1_core0_stall_en(),
+            )
+            .field(
+                "timer_unit0_core1_stall_en",
+                &self.timer_unit0_core1_stall_en(),
+            )
+            .field(
+                "timer_unit0_core0_stall_en",
+                &self.timer_unit0_core0_stall_en(),
+            )
+            .field("timer_unit1_work_en", &self.timer_unit1_work_en())
+            .field("timer_unit0_work_en", &self.timer_unit0_work_en())
+            .field("clk_en", &self.clk_en())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - systimer clock force on"]
+    #[inline(always)]
+    pub fn systimer_clk_fo(&mut self) -> SYSTIMER_CLK_FO_W<CONF_SPEC> {
+        SYSTIMER_CLK_FO_W::new(self, 0)
+    }
+    #[doc = "Bit 22 - target2 work enable"]
+    #[inline(always)]
+    pub fn target2_work_en(&mut self) -> TARGET2_WORK_EN_W<CONF_SPEC> {
+        TARGET2_WORK_EN_W::new(self, 22)
+    }
+    #[doc = "Bit 23 - target1 work enable"]
+    #[inline(always)]
+    pub fn target1_work_en(&mut self) -> TARGET1_WORK_EN_W<CONF_SPEC> {
+        TARGET1_WORK_EN_W::new(self, 23)
+    }
+    #[doc = "Bit 24 - target0 work enable"]
+    #[inline(always)]
+    pub fn target0_work_en(&mut self) -> TARGET0_WORK_EN_W<CONF_SPEC> {
+        TARGET0_WORK_EN_W::new(self, 24)
+    }
+    #[doc = "Bit 25 - If timer unit1 is stalled when core1 stalled"]
+    #[inline(always)]
+    pub fn timer_unit1_core1_stall_en(&mut self) -> TIMER_UNIT1_CORE1_STALL_EN_W<CONF_SPEC> {
+        TIMER_UNIT1_CORE1_STALL_EN_W::new(self, 25)
+    }
+    #[doc = "Bit 26 - If timer unit1 is stalled when core0 stalled"]
+    #[inline(always)]
+    pub fn timer_unit1_core0_stall_en(&mut self) -> TIMER_UNIT1_CORE0_STALL_EN_W<CONF_SPEC> {
+        TIMER_UNIT1_CORE0_STALL_EN_W::new(self, 26)
+    }
+    #[doc = "Bit 27 - If timer unit0 is stalled when core1 stalled"]
+    #[inline(always)]
+    pub fn timer_unit0_core1_stall_en(&mut self) -> TIMER_UNIT0_CORE1_STALL_EN_W<CONF_SPEC> {
+        TIMER_UNIT0_CORE1_STALL_EN_W::new(self, 27)
+    }
+    #[doc = "Bit 28 - If timer unit0 is stalled when core0 stalled"]
+    #[inline(always)]
+    pub fn timer_unit0_core0_stall_en(&mut self) -> TIMER_UNIT0_CORE0_STALL_EN_W<CONF_SPEC> {
+        TIMER_UNIT0_CORE0_STALL_EN_W::new(self, 28)
+    }
+    #[doc = "Bit 29 - timer unit1 work enable"]
+    #[inline(always)]
+    pub fn timer_unit1_work_en(&mut self) -> TIMER_UNIT1_WORK_EN_W<CONF_SPEC> {
+        TIMER_UNIT1_WORK_EN_W::new(self, 29)
+    }
+    #[doc = "Bit 30 - timer unit0 work enable"]
+    #[inline(always)]
+    pub fn timer_unit0_work_en(&mut self) -> TIMER_UNIT0_WORK_EN_W<CONF_SPEC> {
+        TIMER_UNIT0_WORK_EN_W::new(self, 30)
+    }
+    #[doc = "Bit 31 - register file clk gating"]
+    #[inline(always)]
+    pub fn clk_en(&mut self) -> CLK_EN_W<CONF_SPEC> {
+        CLK_EN_W::new(self, 31)
+    }
+}
+#[doc = "Configure system timer clock\n\nYou can [`read`](crate::Reg::read) this register and get [`conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CONF_SPEC;
+impl crate::RegisterSpec for CONF_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`conf::R`](R) reader structure"]
+impl crate::Readable for CONF_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`conf::W`](W) writer structure"]
+impl crate::Writable for CONF_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CONF to value 0x4600_0000"]
+impl crate::Resettable for CONF_SPEC {
+    const RESET_VALUE: u32 = 0x4600_0000;
+}

vendor/esp32s3/src/systimer/date.rs

@@ -0,0 +1,45 @@
+#[doc = "Register `DATE` reader"]
+pub type R = crate::R<DATE_SPEC>;
+#[doc = "Register `DATE` writer"]
+pub type W = crate::W<DATE_SPEC>;
+#[doc = "Field `DATE` reader - systimer register version"]
+pub type DATE_R = crate::FieldReader<u32>;
+#[doc = "Field `DATE` writer - systimer register version"]
+pub type DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - systimer register version"]
+    #[inline(always)]
+    pub fn date(&self) -> DATE_R {
+        DATE_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DATE").field("date", &self.date()).finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - systimer register version"]
+    #[inline(always)]
+    pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
+        DATE_W::new(self, 0)
+    }
+}
+#[doc = "system timer version control register\n\nYou can [`read`](crate::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DATE_SPEC;
+impl crate::RegisterSpec for DATE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`date::R`](R) reader structure"]
+impl crate::Readable for DATE_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"]
+impl crate::Writable for DATE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DATE to value 0x0201_2251"]
+impl crate::Resettable for DATE_SPEC {
+    const RESET_VALUE: u32 = 0x0201_2251;
+}

vendor/esp32s3/src/systimer/int_clr.rs

@@ -0,0 +1,51 @@
+#[doc = "Register `INT_CLR` writer"]
+pub type W = crate::W<INT_CLR_SPEC>;
+#[doc = "Field `TARGET(0-2)` writer - interupt%s clear"]
+pub type TARGET_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "(not readable)")
+    }
+}
+impl W {
+    #[doc = "interupt(0-2) clear"]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TARGET0` field.</div>"]
+    #[inline(always)]
+    pub fn target(&mut self, n: u8) -> TARGET_W<INT_CLR_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TARGET_W::new(self, n)
+    }
+    #[doc = "Bit 0 - interupt0 clear"]
+    #[inline(always)]
+    pub fn target0(&mut self) -> TARGET_W<INT_CLR_SPEC> {
+        TARGET_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - interupt1 clear"]
+    #[inline(always)]
+    pub fn target1(&mut self) -> TARGET_W<INT_CLR_SPEC> {
+        TARGET_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - interupt2 clear"]
+    #[inline(always)]
+    pub fn target2(&mut self) -> TARGET_W<INT_CLR_SPEC> {
+        TARGET_W::new(self, 2)
+    }
+}
+#[doc = "systimer interrupt clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct INT_CLR_SPEC;
+impl crate::RegisterSpec for INT_CLR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
+impl crate::Writable for INT_CLR_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x07;
+}
+#[doc = "`reset()` method sets INT_CLR to value 0"]
+impl crate::Resettable for INT_CLR_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/systimer/int_ena.rs

@@ -0,0 +1,93 @@
+#[doc = "Register `INT_ENA` reader"]
+pub type R = crate::R<INT_ENA_SPEC>;
+#[doc = "Register `INT_ENA` writer"]
+pub type W = crate::W<INT_ENA_SPEC>;
+#[doc = "Field `TARGET(0-2)` reader - interupt%s enable"]
+pub type TARGET_R = crate::BitReader;
+#[doc = "Field `TARGET(0-2)` writer - interupt%s enable"]
+pub type TARGET_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "interupt(0-2) enable"]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TARGET0` field.</div>"]
+    #[inline(always)]
+    pub fn target(&self, n: u8) -> TARGET_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TARGET_R::new(((self.bits >> n) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "interupt(0-2) enable"]
+    #[inline(always)]
+    pub fn target_iter(&self) -> impl Iterator<Item = TARGET_R> + '_ {
+        (0..3).map(move |n| TARGET_R::new(((self.bits >> n) & 1) != 0))
+    }
+    #[doc = "Bit 0 - interupt0 enable"]
+    #[inline(always)]
+    pub fn target0(&self) -> TARGET_R {
+        TARGET_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - interupt1 enable"]
+    #[inline(always)]
+    pub fn target1(&self) -> TARGET_R {
+        TARGET_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - interupt2 enable"]
+    #[inline(always)]
+    pub fn target2(&self) -> TARGET_R {
+        TARGET_R::new(((self.bits >> 2) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("INT_ENA")
+            .field("target0", &self.target0())
+            .field("target1", &self.target1())
+            .field("target2", &self.target2())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "interupt(0-2) enable"]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TARGET0` field.</div>"]
+    #[inline(always)]
+    pub fn target(&mut self, n: u8) -> TARGET_W<INT_ENA_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TARGET_W::new(self, n)
+    }
+    #[doc = "Bit 0 - interupt0 enable"]
+    #[inline(always)]
+    pub fn target0(&mut self) -> TARGET_W<INT_ENA_SPEC> {
+        TARGET_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - interupt1 enable"]
+    #[inline(always)]
+    pub fn target1(&mut self) -> TARGET_W<INT_ENA_SPEC> {
+        TARGET_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - interupt2 enable"]
+    #[inline(always)]
+    pub fn target2(&mut self) -> TARGET_W<INT_ENA_SPEC> {
+        TARGET_W::new(self, 2)
+    }
+}
+#[doc = "systimer interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct INT_ENA_SPEC;
+impl crate::RegisterSpec for INT_ENA_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"]
+impl crate::Readable for INT_ENA_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"]
+impl crate::Writable for INT_ENA_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets INT_ENA to value 0"]
+impl crate::Resettable for INT_ENA_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/systimer/int_raw.rs

@@ -0,0 +1,93 @@
+#[doc = "Register `INT_RAW` reader"]
+pub type R = crate::R<INT_RAW_SPEC>;
+#[doc = "Register `INT_RAW` writer"]
+pub type W = crate::W<INT_RAW_SPEC>;
+#[doc = "Field `TARGET(0-2)` reader - interupt%s raw"]
+pub type TARGET_R = crate::BitReader;
+#[doc = "Field `TARGET(0-2)` writer - interupt%s raw"]
+pub type TARGET_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "interupt(0-2) raw"]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TARGET0` field.</div>"]
+    #[inline(always)]
+    pub fn target(&self, n: u8) -> TARGET_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TARGET_R::new(((self.bits >> n) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "interupt(0-2) raw"]
+    #[inline(always)]
+    pub fn target_iter(&self) -> impl Iterator<Item = TARGET_R> + '_ {
+        (0..3).map(move |n| TARGET_R::new(((self.bits >> n) & 1) != 0))
+    }
+    #[doc = "Bit 0 - interupt0 raw"]
+    #[inline(always)]
+    pub fn target0(&self) -> TARGET_R {
+        TARGET_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - interupt1 raw"]
+    #[inline(always)]
+    pub fn target1(&self) -> TARGET_R {
+        TARGET_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - interupt2 raw"]
+    #[inline(always)]
+    pub fn target2(&self) -> TARGET_R {
+        TARGET_R::new(((self.bits >> 2) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("INT_RAW")
+            .field("target0", &self.target0())
+            .field("target1", &self.target1())
+            .field("target2", &self.target2())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "interupt(0-2) raw"]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TARGET0` field.</div>"]
+    #[inline(always)]
+    pub fn target(&mut self, n: u8) -> TARGET_W<INT_RAW_SPEC> {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TARGET_W::new(self, n)
+    }
+    #[doc = "Bit 0 - interupt0 raw"]
+    #[inline(always)]
+    pub fn target0(&mut self) -> TARGET_W<INT_RAW_SPEC> {
+        TARGET_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - interupt1 raw"]
+    #[inline(always)]
+    pub fn target1(&mut self) -> TARGET_W<INT_RAW_SPEC> {
+        TARGET_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - interupt2 raw"]
+    #[inline(always)]
+    pub fn target2(&mut self) -> TARGET_W<INT_RAW_SPEC> {
+        TARGET_W::new(self, 2)
+    }
+}
+#[doc = "systimer interrupt raw register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_raw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_raw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct INT_RAW_SPEC;
+impl crate::RegisterSpec for INT_RAW_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"]
+impl crate::Readable for INT_RAW_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`int_raw::W`](W) writer structure"]
+impl crate::Writable for INT_RAW_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets INT_RAW to value 0"]
+impl crate::Resettable for INT_RAW_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/systimer/int_st.rs

@@ -0,0 +1,57 @@
+#[doc = "Register `INT_ST` reader"]
+pub type R = crate::R<INT_ST_SPEC>;
+#[doc = "Field `TARGET(0-2)` reader - interupt%s status"]
+pub type TARGET_R = crate::BitReader;
+impl R {
+    #[doc = "interupt(0-2) status"]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `TARGET0` field.</div>"]
+    #[inline(always)]
+    pub fn target(&self, n: u8) -> TARGET_R {
+        #[allow(clippy::no_effect)]
+        [(); 3][n as usize];
+        TARGET_R::new(((self.bits >> n) & 1) != 0)
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "interupt(0-2) status"]
+    #[inline(always)]
+    pub fn target_iter(&self) -> impl Iterator<Item = TARGET_R> + '_ {
+        (0..3).map(move |n| TARGET_R::new(((self.bits >> n) & 1) != 0))
+    }
+    #[doc = "Bit 0 - interupt0 status"]
+    #[inline(always)]
+    pub fn target0(&self) -> TARGET_R {
+        TARGET_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - interupt1 status"]
+    #[inline(always)]
+    pub fn target1(&self) -> TARGET_R {
+        TARGET_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - interupt2 status"]
+    #[inline(always)]
+    pub fn target2(&self) -> TARGET_R {
+        TARGET_R::new(((self.bits >> 2) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("INT_ST")
+            .field("target0", &self.target0())
+            .field("target1", &self.target1())
+            .field("target2", &self.target2())
+            .finish()
+    }
+}
+#[doc = "systimer interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct INT_ST_SPEC;
+impl crate::RegisterSpec for INT_ST_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`int_st::R`](R) reader structure"]
+impl crate::Readable for INT_ST_SPEC {}
+#[doc = "`reset()` method sets INT_ST to value 0"]
+impl crate::Resettable for INT_ST_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/systimer/real_target.rs

@@ -0,0 +1,27 @@
+#[repr(C)]
+#[cfg_attr(feature = "impl-register-debug", derive(Debug))]
+#[doc = "Cluster REAL_TARGET%s, containing REAL_TARGET?_LO, REAL_TARGET?_HI"]
+pub struct REAL_TARGET {
+    lo: LO,
+    hi: HI,
+}
+impl REAL_TARGET {
+    #[doc = "0x00 - system timer comp0 actual target value low register"]
+    #[inline(always)]
+    pub const fn lo(&self) -> &LO {
+        &self.lo
+    }
+    #[doc = "0x04 - system timer comp0 actual target value high register"]
+    #[inline(always)]
+    pub const fn hi(&self) -> &HI {
+        &self.hi
+    }
+}
+#[doc = "LO (r) register accessor: system timer comp0 actual target value low register\n\nYou can [`read`](crate::Reg::read) this register and get [`lo::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lo`] module"]
+pub type LO = crate::Reg<lo::LO_SPEC>;
+#[doc = "system timer comp0 actual target value low register"]
+pub mod lo;
+#[doc = "HI (r) register accessor: system timer comp0 actual target value high register\n\nYou can [`read`](crate::Reg::read) this register and get [`hi::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hi`] module"]
+pub type HI = crate::Reg<hi::HI_SPEC>;
+#[doc = "system timer comp0 actual target value high register"]
+pub mod hi;

vendor/esp32s3/src/systimer/real_target/hi.rs

@@ -0,0 +1,28 @@
+#[doc = "Register `HI` reader"]
+pub type R = crate::R<HI_SPEC>;
+#[doc = "Field `HI_RO` reader - actual target value value high 20bits"]
+pub type HI_RO_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:19 - actual target value value high 20bits"]
+    #[inline(always)]
+    pub fn hi_ro(&self) -> HI_RO_R {
+        HI_RO_R::new(self.bits & 0x000f_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("HI").field("hi_ro", &self.hi_ro()).finish()
+    }
+}
+#[doc = "system timer comp0 actual target value high register\n\nYou can [`read`](crate::Reg::read) this register and get [`hi::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct HI_SPEC;
+impl crate::RegisterSpec for HI_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`hi::R`](R) reader structure"]
+impl crate::Readable for HI_SPEC {}
+#[doc = "`reset()` method sets HI to value 0"]
+impl crate::Resettable for HI_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/systimer/real_target/lo.rs

@@ -0,0 +1,28 @@
+#[doc = "Register `LO` reader"]
+pub type R = crate::R<LO_SPEC>;
+#[doc = "Field `LO_RO` reader - actual target value value low 32bits"]
+pub type LO_RO_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - actual target value value low 32bits"]
+    #[inline(always)]
+    pub fn lo_ro(&self) -> LO_RO_R {
+        LO_RO_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("LO").field("lo_ro", &self.lo_ro()).finish()
+    }
+}
+#[doc = "system timer comp0 actual target value low register\n\nYou can [`read`](crate::Reg::read) this register and get [`lo::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct LO_SPEC;
+impl crate::RegisterSpec for LO_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`lo::R`](R) reader structure"]
+impl crate::Readable for LO_SPEC {}
+#[doc = "`reset()` method sets LO to value 0"]
+impl crate::Resettable for LO_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/systimer/target_conf.rs

@@ -0,0 +1,77 @@
+#[doc = "Register `TARGET%s_CONF` reader"]
+pub type R = crate::R<TARGET_CONF_SPEC>;
+#[doc = "Register `TARGET%s_CONF` writer"]
+pub type W = crate::W<TARGET_CONF_SPEC>;
+#[doc = "Field `PERIOD` reader - target0 period"]
+pub type PERIOD_R = crate::FieldReader<u32>;
+#[doc = "Field `PERIOD` writer - target0 period"]
+pub type PERIOD_W<'a, REG> = crate::FieldWriter<'a, REG, 26, u32>;
+#[doc = "Field `PERIOD_MODE` reader - Set target0 to period mode"]
+pub type PERIOD_MODE_R = crate::BitReader;
+#[doc = "Field `PERIOD_MODE` writer - Set target0 to period mode"]
+pub type PERIOD_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TIMER_UNIT_SEL` reader - select which unit to compare"]
+pub type TIMER_UNIT_SEL_R = crate::BitReader;
+#[doc = "Field `TIMER_UNIT_SEL` writer - select which unit to compare"]
+pub type TIMER_UNIT_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 0:25 - target0 period"]
+    #[inline(always)]
+    pub fn period(&self) -> PERIOD_R {
+        PERIOD_R::new(self.bits & 0x03ff_ffff)
+    }
+    #[doc = "Bit 30 - Set target0 to period mode"]
+    #[inline(always)]
+    pub fn period_mode(&self) -> PERIOD_MODE_R {
+        PERIOD_MODE_R::new(((self.bits >> 30) & 1) != 0)
+    }
+    #[doc = "Bit 31 - select which unit to compare"]
+    #[inline(always)]
+    pub fn timer_unit_sel(&self) -> TIMER_UNIT_SEL_R {
+        TIMER_UNIT_SEL_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("TARGET_CONF")
+            .field("period", &self.period())
+            .field("period_mode", &self.period_mode())
+            .field("timer_unit_sel", &self.timer_unit_sel())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:25 - target0 period"]
+    #[inline(always)]
+    pub fn period(&mut self) -> PERIOD_W<TARGET_CONF_SPEC> {
+        PERIOD_W::new(self, 0)
+    }
+    #[doc = "Bit 30 - Set target0 to period mode"]
+    #[inline(always)]
+    pub fn period_mode(&mut self) -> PERIOD_MODE_W<TARGET_CONF_SPEC> {
+        PERIOD_MODE_W::new(self, 30)
+    }
+    #[doc = "Bit 31 - select which unit to compare"]
+    #[inline(always)]
+    pub fn timer_unit_sel(&mut self) -> TIMER_UNIT_SEL_W<TARGET_CONF_SPEC> {
+        TIMER_UNIT_SEL_W::new(self, 31)
+    }
+}
+#[doc = "system timer comp%s target mode register\n\nYou can [`read`](crate::Reg::read) this register and get [`target_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`target_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct TARGET_CONF_SPEC;
+impl crate::RegisterSpec for TARGET_CONF_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`target_conf::R`](R) reader structure"]
+impl crate::Readable for TARGET_CONF_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`target_conf::W`](W) writer structure"]
+impl crate::Writable for TARGET_CONF_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets TARGET%s_CONF to value 0"]
+impl crate::Resettable for TARGET_CONF_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/systimer/trgt.rs

@@ -0,0 +1,27 @@
+#[repr(C)]
+#[cfg_attr(feature = "impl-register-debug", derive(Debug))]
+#[doc = "Cluster TRGT%s, containing TARGET?_HI, TARGET?_LO"]
+pub struct TRGT {
+    hi: HI,
+    lo: LO,
+}
+impl TRGT {
+    #[doc = "0x00 - system timer comp0 value high register"]
+    #[inline(always)]
+    pub const fn hi(&self) -> &HI {
+        &self.hi
+    }
+    #[doc = "0x04 - system timer comp0 value low register"]
+    #[inline(always)]
+    pub const fn lo(&self) -> &LO {
+        &self.lo
+    }
+}
+#[doc = "HI (rw) register accessor: system timer comp0 value high register\n\nYou can [`read`](crate::Reg::read) this register and get [`hi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hi`] module"]
+pub type HI = crate::Reg<hi::HI_SPEC>;
+#[doc = "system timer comp0 value high register"]
+pub mod hi;
+#[doc = "LO (rw) register accessor: system timer comp0 value low register\n\nYou can [`read`](crate::Reg::read) this register and get [`lo::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lo::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lo`] module"]
+pub type LO = crate::Reg<lo::LO_SPEC>;
+#[doc = "system timer comp0 value low register"]
+pub mod lo;

vendor/esp32s3/src/systimer/trgt/hi.rs

@@ -0,0 +1,45 @@
+#[doc = "Register `HI` reader"]
+pub type R = crate::R<HI_SPEC>;
+#[doc = "Register `HI` writer"]
+pub type W = crate::W<HI_SPEC>;
+#[doc = "Field `HI` reader - timer taget0 high 20 bits"]
+pub type HI_R = crate::FieldReader<u32>;
+#[doc = "Field `HI` writer - timer taget0 high 20 bits"]
+pub type HI_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32, crate::Safe>;
+impl R {
+    #[doc = "Bits 0:19 - timer taget0 high 20 bits"]
+    #[inline(always)]
+    pub fn hi(&self) -> HI_R {
+        HI_R::new(self.bits & 0x000f_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("HI").field("hi", &self.hi()).finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:19 - timer taget0 high 20 bits"]
+    #[inline(always)]
+    pub fn hi(&mut self) -> HI_W<HI_SPEC> {
+        HI_W::new(self, 0)
+    }
+}
+#[doc = "system timer comp0 value high register\n\nYou can [`read`](crate::Reg::read) this register and get [`hi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct HI_SPEC;
+impl crate::RegisterSpec for HI_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`hi::R`](R) reader structure"]
+impl crate::Readable for HI_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`hi::W`](W) writer structure"]
+impl crate::Writable for HI_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets HI to value 0"]
+impl crate::Resettable for HI_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/systimer/trgt/lo.rs

@@ -0,0 +1,45 @@
+#[doc = "Register `LO` reader"]
+pub type R = crate::R<LO_SPEC>;
+#[doc = "Register `LO` writer"]
+pub type W = crate::W<LO_SPEC>;
+#[doc = "Field `LO` reader - timer taget0 low 32 bits"]
+pub type LO_R = crate::FieldReader<u32>;
+#[doc = "Field `LO` writer - timer taget0 low 32 bits"]
+pub type LO_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32, crate::Safe>;
+impl R {
+    #[doc = "Bits 0:31 - timer taget0 low 32 bits"]
+    #[inline(always)]
+    pub fn lo(&self) -> LO_R {
+        LO_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("LO").field("lo", &self.lo()).finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - timer taget0 low 32 bits"]
+    #[inline(always)]
+    pub fn lo(&mut self) -> LO_W<LO_SPEC> {
+        LO_W::new(self, 0)
+    }
+}
+#[doc = "system timer comp0 value low register\n\nYou can [`read`](crate::Reg::read) this register and get [`lo::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lo::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct LO_SPEC;
+impl crate::RegisterSpec for LO_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`lo::R`](R) reader structure"]
+impl crate::Readable for LO_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`lo::W`](W) writer structure"]
+impl crate::Writable for LO_SPEC {
+    type Safety = crate::Safe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets LO to value 0"]
+impl crate::Resettable for LO_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/systimer/unit_load.rs

@@ -0,0 +1,32 @@
+#[doc = "Register `UNIT%s_LOAD` writer"]
+pub type W = crate::W<UNIT_LOAD_SPEC>;
+#[doc = "Field `LOAD` writer - timer unit0 sync enable signal"]
+pub type LOAD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for crate::generic::Reg<UNIT_LOAD_SPEC> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "(not readable)")
+    }
+}
+impl W {
+    #[doc = "Bit 0 - timer unit0 sync enable signal"]
+    #[inline(always)]
+    pub fn load(&mut self) -> LOAD_W<UNIT_LOAD_SPEC> {
+        LOAD_W::new(self, 0)
+    }
+}
+#[doc = "system timer unit%s conf sync register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`unit_load::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct UNIT_LOAD_SPEC;
+impl crate::RegisterSpec for UNIT_LOAD_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [`unit_load::W`](W) writer structure"]
+impl crate::Writable for UNIT_LOAD_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets UNIT%s_LOAD to value 0"]
+impl crate::Resettable for UNIT_LOAD_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/systimer/unit_op.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `UNIT%s_OP` reader"]
+pub type R = crate::R<UNIT_OP_SPEC>;
+#[doc = "Register `UNIT%s_OP` writer"]
+pub type W = crate::W<UNIT_OP_SPEC>;
+#[doc = "Field `VALUE_VALID` reader - timer value is sync and valid"]
+pub type VALUE_VALID_R = crate::BitReader;
+#[doc = "Field `UPDATE` writer - update timer_unit0"]
+pub type UPDATE_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 29 - timer value is sync and valid"]
+    #[inline(always)]
+    pub fn value_valid(&self) -> VALUE_VALID_R {
+        VALUE_VALID_R::new(((self.bits >> 29) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("UNIT_OP")
+            .field("value_valid", &self.value_valid())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 30 - update timer_unit0"]
+    #[inline(always)]
+    pub fn update(&mut self) -> UPDATE_W<UNIT_OP_SPEC> {
+        UPDATE_W::new(self, 30)
+    }
+}
+#[doc = "system timer unit%s value update register\n\nYou can [`read`](crate::Reg::read) this register and get [`unit_op::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`unit_op::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct UNIT_OP_SPEC;
+impl crate::RegisterSpec for UNIT_OP_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`unit_op::R`](R) reader structure"]
+impl crate::Readable for UNIT_OP_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`unit_op::W`](W) writer structure"]
+impl crate::Writable for UNIT_OP_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets UNIT%s_OP to value 0"]
+impl crate::Resettable for UNIT_OP_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/systimer/unit_value.rs

@@ -0,0 +1,27 @@
+#[repr(C)]
+#[cfg_attr(feature = "impl-register-debug", derive(Debug))]
+#[doc = "Cluster UNIT%s_VALUE, containing UNIT?_VALUE_HI, UNIT?_VALUE_LO"]
+pub struct UNIT_VALUE {
+    hi: HI,
+    lo: LO,
+}
+impl UNIT_VALUE {
+    #[doc = "0x00 - system timer unit0 value high register"]
+    #[inline(always)]
+    pub const fn hi(&self) -> &HI {
+        &self.hi
+    }
+    #[doc = "0x04 - system timer unit0 value low register"]
+    #[inline(always)]
+    pub const fn lo(&self) -> &LO {
+        &self.lo
+    }
+}
+#[doc = "HI (r) register accessor: system timer unit0 value high register\n\nYou can [`read`](crate::Reg::read) this register and get [`hi::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hi`] module"]
+pub type HI = crate::Reg<hi::HI_SPEC>;
+#[doc = "system timer unit0 value high register"]
+pub mod hi;
+#[doc = "LO (r) register accessor: system timer unit0 value low register\n\nYou can [`read`](crate::Reg::read) this register and get [`lo::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lo`] module"]
+pub type LO = crate::Reg<lo::LO_SPEC>;
+#[doc = "system timer unit0 value low register"]
+pub mod lo;

vendor/esp32s3/src/systimer/unit_value/hi.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `HI` reader"]
+pub type R = crate::R<HI_SPEC>;
+#[doc = "Field `VALUE_HI` reader - timer read value high 20bits"]
+pub type VALUE_HI_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:19 - timer read value high 20bits"]
+    #[inline(always)]
+    pub fn value_hi(&self) -> VALUE_HI_R {
+        VALUE_HI_R::new(self.bits & 0x000f_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("HI")
+            .field("value_hi", &self.value_hi())
+            .finish()
+    }
+}
+#[doc = "system timer unit0 value high register\n\nYou can [`read`](crate::Reg::read) this register and get [`hi::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct HI_SPEC;
+impl crate::RegisterSpec for HI_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`hi::R`](R) reader structure"]
+impl crate::Readable for HI_SPEC {}
+#[doc = "`reset()` method sets HI to value 0"]
+impl crate::Resettable for HI_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/systimer/unit_value/lo.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `LO` reader"]
+pub type R = crate::R<LO_SPEC>;
+#[doc = "Field `VALUE_LO` reader - timer read value low 32bits"]
+pub type VALUE_LO_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - timer read value low 32bits"]
+    #[inline(always)]
+    pub fn value_lo(&self) -> VALUE_LO_R {
+        VALUE_LO_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("LO")
+            .field("value_lo", &self.value_lo())
+            .finish()
+    }
+}
+#[doc = "system timer unit0 value low register\n\nYou can [`read`](crate::Reg::read) this register and get [`lo::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct LO_SPEC;
+impl crate::RegisterSpec for LO_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`lo::R`](R) reader structure"]
+impl crate::Readable for LO_SPEC {}
+#[doc = "`reset()` method sets LO to value 0"]
+impl crate::Resettable for LO_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/systimer/unitload.rs

@@ -0,0 +1,27 @@
+#[repr(C)]
+#[cfg_attr(feature = "impl-register-debug", derive(Debug))]
+#[doc = "Cluster UNIT%sLOAD, containing UNIT?_LOAD_HI, UNIT?_LOAD_LO"]
+pub struct UNITLOAD {
+    hi: HI,
+    lo: LO,
+}
+impl UNITLOAD {
+    #[doc = "0x00 - system timer unit0 value high load register"]
+    #[inline(always)]
+    pub const fn hi(&self) -> &HI {
+        &self.hi
+    }
+    #[doc = "0x04 - system timer unit0 value low load register"]
+    #[inline(always)]
+    pub const fn lo(&self) -> &LO {
+        &self.lo
+    }
+}
+#[doc = "HI (rw) register accessor: system timer unit0 value high load register\n\nYou can [`read`](crate::Reg::read) this register and get [`hi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hi`] module"]
+pub type HI = crate::Reg<hi::HI_SPEC>;
+#[doc = "system timer unit0 value high load register"]
+pub mod hi;
+#[doc = "LO (rw) register accessor: system timer unit0 value low load register\n\nYou can [`read`](crate::Reg::read) this register and get [`lo::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lo::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lo`] module"]
+pub type LO = crate::Reg<lo::LO_SPEC>;
+#[doc = "system timer unit0 value low load register"]
+pub mod lo;

vendor/esp32s3/src/systimer/unitload/hi.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `HI` reader"]
+pub type R = crate::R<HI_SPEC>;
+#[doc = "Register `HI` writer"]
+pub type W = crate::W<HI_SPEC>;
+#[doc = "Field `LOAD_HI` reader - timer unit0 load high 20 bits"]
+pub type LOAD_HI_R = crate::FieldReader<u32>;
+#[doc = "Field `LOAD_HI` writer - timer unit0 load high 20 bits"]
+pub type LOAD_HI_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32, crate::Safe>;
+impl R {
+    #[doc = "Bits 0:19 - timer unit0 load high 20 bits"]
+    #[inline(always)]
+    pub fn load_hi(&self) -> LOAD_HI_R {
+        LOAD_HI_R::new(self.bits & 0x000f_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("HI")
+            .field("load_hi", &self.load_hi())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:19 - timer unit0 load high 20 bits"]
+    #[inline(always)]
+    pub fn load_hi(&mut self) -> LOAD_HI_W<HI_SPEC> {
+        LOAD_HI_W::new(self, 0)
+    }
+}
+#[doc = "system timer unit0 value high load register\n\nYou can [`read`](crate::Reg::read) this register and get [`hi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct HI_SPEC;
+impl crate::RegisterSpec for HI_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`hi::R`](R) reader structure"]
+impl crate::Readable for HI_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`hi::W`](W) writer structure"]
+impl crate::Writable for HI_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets HI to value 0"]
+impl crate::Resettable for HI_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/systimer/unitload/lo.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `LO` reader"]
+pub type R = crate::R<LO_SPEC>;
+#[doc = "Register `LO` writer"]
+pub type W = crate::W<LO_SPEC>;
+#[doc = "Field `LOAD_LO` reader - timer unit0 load low 32 bits"]
+pub type LOAD_LO_R = crate::FieldReader<u32>;
+#[doc = "Field `LOAD_LO` writer - timer unit0 load low 32 bits"]
+pub type LOAD_LO_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32, crate::Safe>;
+impl R {
+    #[doc = "Bits 0:31 - timer unit0 load low 32 bits"]
+    #[inline(always)]
+    pub fn load_lo(&self) -> LOAD_LO_R {
+        LOAD_LO_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("LO")
+            .field("load_lo", &self.load_lo())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - timer unit0 load low 32 bits"]
+    #[inline(always)]
+    pub fn load_lo(&mut self) -> LOAD_LO_W<LO_SPEC> {
+        LOAD_LO_W::new(self, 0)
+    }
+}
+#[doc = "system timer unit0 value low load register\n\nYou can [`read`](crate::Reg::read) this register and get [`lo::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lo::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct LO_SPEC;
+impl crate::RegisterSpec for LO_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`lo::R`](R) reader structure"]
+impl crate::Readable for LO_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`lo::W`](W) writer structure"]
+impl crate::Writable for LO_SPEC {
+    type Safety = crate::Safe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets LO to value 0"]
+impl crate::Resettable for LO_SPEC {
+    const RESET_VALUE: u32 = 0;
+}