feat: add display UI with splash screen, dashboard, and RSSI sparkline

Implement full SSD1306 OLED display support:
- Splash screen on boot (1.5s) with project name, version, board
- Dashboard showing radio state, config, counters, RSSI/SNR
- RSSI history sparkline (64-sample ring buffer, 2px-wide bars)
- DisplayOn/DisplayOff host commands routed via dedicated channel
- Pure render functions against generic DrawTarget (no hardware coupling)
- Display on/off control bypasses radio task entirely

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>

vendor/esp32s3/src/uhci0/ack_num.rs

@@ -0,0 +1,54 @@
+#[doc = "Register `ACK_NUM` reader"]
+pub type R = crate::R<ACK_NUM_SPEC>;
+#[doc = "Register `ACK_NUM` writer"]
+pub type W = crate::W<ACK_NUM_SPEC>;
+#[doc = "Field `ACK_NUM` reader - This ACK number used in software flow control."]
+pub type ACK_NUM_R = crate::FieldReader;
+#[doc = "Field `ACK_NUM` writer - This ACK number used in software flow control."]
+pub type ACK_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `LOAD` writer - Set this bit to 1, the value configured by UHCI_ACK_NUM would be loaded."]
+pub type LOAD_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 0:2 - This ACK number used in software flow control."]
+    #[inline(always)]
+    pub fn ack_num(&self) -> ACK_NUM_R {
+        ACK_NUM_R::new((self.bits & 7) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("ACK_NUM")
+            .field("ack_num", &self.ack_num())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:2 - This ACK number used in software flow control."]
+    #[inline(always)]
+    pub fn ack_num(&mut self) -> ACK_NUM_W<ACK_NUM_SPEC> {
+        ACK_NUM_W::new(self, 0)
+    }
+    #[doc = "Bit 3 - Set this bit to 1, the value configured by UHCI_ACK_NUM would be loaded."]
+    #[inline(always)]
+    pub fn load(&mut self) -> LOAD_W<ACK_NUM_SPEC> {
+        LOAD_W::new(self, 3)
+    }
+}
+#[doc = "UHCI ACK number configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`ack_num::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ack_num::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ACK_NUM_SPEC;
+impl crate::RegisterSpec for ACK_NUM_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`ack_num::R`](R) reader structure"]
+impl crate::Readable for ACK_NUM_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`ack_num::W`](W) writer structure"]
+impl crate::Writable for ACK_NUM_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets ACK_NUM to value 0x08"]
+impl crate::Resettable for ACK_NUM_SPEC {
+    const RESET_VALUE: u32 = 0x08;
+}

vendor/esp32s3/src/uhci0/app_int_set.rs

@@ -0,0 +1,39 @@
+#[doc = "Register `APP_INT_SET` writer"]
+pub type W = crate::W<APP_INT_SET_SPEC>;
+#[doc = "Field `APP_CTRL0_INT_SET` writer - This bit is software interrupt trigger source of UHCI_APP_CTRL0_INT."]
+pub type APP_CTRL0_INT_SET_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `APP_CTRL1_INT_SET` writer - This bit is software interrupt trigger source of UHCI_APP_CTRL1_INT."]
+pub type APP_CTRL1_INT_SET_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for crate::generic::Reg<APP_INT_SET_SPEC> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "(not readable)")
+    }
+}
+impl W {
+    #[doc = "Bit 0 - This bit is software interrupt trigger source of UHCI_APP_CTRL0_INT."]
+    #[inline(always)]
+    pub fn app_ctrl0_int_set(&mut self) -> APP_CTRL0_INT_SET_W<APP_INT_SET_SPEC> {
+        APP_CTRL0_INT_SET_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - This bit is software interrupt trigger source of UHCI_APP_CTRL1_INT."]
+    #[inline(always)]
+    pub fn app_ctrl1_int_set(&mut self) -> APP_CTRL1_INT_SET_W<APP_INT_SET_SPEC> {
+        APP_CTRL1_INT_SET_W::new(self, 1)
+    }
+}
+#[doc = "Software interrupt trigger source\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_int_set::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct APP_INT_SET_SPEC;
+impl crate::RegisterSpec for APP_INT_SET_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [`app_int_set::W`](W) writer structure"]
+impl crate::Writable for APP_INT_SET_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets APP_INT_SET to value 0"]
+impl crate::Resettable for APP_INT_SET_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/uhci0/conf0.rs

@@ -0,0 +1,227 @@
+#[doc = "Register `CONF0` reader"]
+pub type R = crate::R<CONF0_SPEC>;
+#[doc = "Register `CONF0` writer"]
+pub type W = crate::W<CONF0_SPEC>;
+#[doc = "Field `TX_RST` reader - Write 1, then write 0 to this bit to reset decode state machine."]
+pub type TX_RST_R = crate::BitReader;
+#[doc = "Field `TX_RST` writer - Write 1, then write 0 to this bit to reset decode state machine."]
+pub type TX_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RX_RST` reader - Write 1, then write 0 to this bit to reset encode state machine."]
+pub type RX_RST_R = crate::BitReader;
+#[doc = "Field `RX_RST` writer - Write 1, then write 0 to this bit to reset encode state machine."]
+pub type RX_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `UART0_CE` reader - Set this bit to link up HCI and UART0."]
+pub type UART0_CE_R = crate::BitReader;
+#[doc = "Field `UART0_CE` writer - Set this bit to link up HCI and UART0."]
+pub type UART0_CE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `UART1_CE` reader - Set this bit to link up HCI and UART1."]
+pub type UART1_CE_R = crate::BitReader;
+#[doc = "Field `UART1_CE` writer - Set this bit to link up HCI and UART1."]
+pub type UART1_CE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `UART2_CE` reader - Set this bit to link up HCI and UART2."]
+pub type UART2_CE_R = crate::BitReader;
+#[doc = "Field `UART2_CE` writer - Set this bit to link up HCI and UART2."]
+pub type UART2_CE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SEPER_EN` reader - Set this bit to separate the data frame using a special char."]
+pub type SEPER_EN_R = crate::BitReader;
+#[doc = "Field `SEPER_EN` writer - Set this bit to separate the data frame using a special char."]
+pub type SEPER_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `HEAD_EN` reader - Set this bit to encode the data packet with a formatting header."]
+pub type HEAD_EN_R = crate::BitReader;
+#[doc = "Field `HEAD_EN` writer - Set this bit to encode the data packet with a formatting header."]
+pub type HEAD_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CRC_REC_EN` reader - Set this bit to enable UHCI to receive the 16 bit CRC."]
+pub type CRC_REC_EN_R = crate::BitReader;
+#[doc = "Field `CRC_REC_EN` writer - Set this bit to enable UHCI to receive the 16 bit CRC."]
+pub type CRC_REC_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `UART_IDLE_EOF_EN` reader - If this bit is set to 1, UHCI will end the payload receiving process when UART has been in idle state."]
+pub type UART_IDLE_EOF_EN_R = crate::BitReader;
+#[doc = "Field `UART_IDLE_EOF_EN` writer - If this bit is set to 1, UHCI will end the payload receiving process when UART has been in idle state."]
+pub type UART_IDLE_EOF_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `LEN_EOF_EN` reader - If this bit is set to 1, UHCI decoder receiving payload data is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0, UHCI decoder receiving payload data is end when 0xc0 is received."]
+pub type LEN_EOF_EN_R = crate::BitReader;
+#[doc = "Field `LEN_EOF_EN` writer - If this bit is set to 1, UHCI decoder receiving payload data is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0, UHCI decoder receiving payload data is end when 0xc0 is received."]
+pub type LEN_EOF_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ENCODE_CRC_EN` reader - Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to end of the payload."]
+pub type ENCODE_CRC_EN_R = crate::BitReader;
+#[doc = "Field `ENCODE_CRC_EN` writer - Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to end of the payload."]
+pub type ENCODE_CRC_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CLK_EN` reader - 1'b1: Force clock on for register. 1'b0: Support clock only when application writes registers."]
+pub type CLK_EN_R = crate::BitReader;
+#[doc = "Field `CLK_EN` writer - 1'b1: Force clock on for register. 1'b0: Support clock only when application writes registers."]
+pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `UART_RX_BRK_EOF_EN` reader - If this bit is set to 1, UHCI will end payload receive process when NULL frame is received by UART."]
+pub type UART_RX_BRK_EOF_EN_R = crate::BitReader;
+#[doc = "Field `UART_RX_BRK_EOF_EN` writer - If this bit is set to 1, UHCI will end payload receive process when NULL frame is received by UART."]
+pub type UART_RX_BRK_EOF_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Write 1, then write 0 to this bit to reset decode state machine."]
+    #[inline(always)]
+    pub fn tx_rst(&self) -> TX_RST_R {
+        TX_RST_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Write 1, then write 0 to this bit to reset encode state machine."]
+    #[inline(always)]
+    pub fn rx_rst(&self) -> RX_RST_R {
+        RX_RST_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Set this bit to link up HCI and UART0."]
+    #[inline(always)]
+    pub fn uart0_ce(&self) -> UART0_CE_R {
+        UART0_CE_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Set this bit to link up HCI and UART1."]
+    #[inline(always)]
+    pub fn uart1_ce(&self) -> UART1_CE_R {
+        UART1_CE_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Set this bit to link up HCI and UART2."]
+    #[inline(always)]
+    pub fn uart2_ce(&self) -> UART2_CE_R {
+        UART2_CE_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - Set this bit to separate the data frame using a special char."]
+    #[inline(always)]
+    pub fn seper_en(&self) -> SEPER_EN_R {
+        SEPER_EN_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - Set this bit to encode the data packet with a formatting header."]
+    #[inline(always)]
+    pub fn head_en(&self) -> HEAD_EN_R {
+        HEAD_EN_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - Set this bit to enable UHCI to receive the 16 bit CRC."]
+    #[inline(always)]
+    pub fn crc_rec_en(&self) -> CRC_REC_EN_R {
+        CRC_REC_EN_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - If this bit is set to 1, UHCI will end the payload receiving process when UART has been in idle state."]
+    #[inline(always)]
+    pub fn uart_idle_eof_en(&self) -> UART_IDLE_EOF_EN_R {
+        UART_IDLE_EOF_EN_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - If this bit is set to 1, UHCI decoder receiving payload data is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0, UHCI decoder receiving payload data is end when 0xc0 is received."]
+    #[inline(always)]
+    pub fn len_eof_en(&self) -> LEN_EOF_EN_R {
+        LEN_EOF_EN_R::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 10 - Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to end of the payload."]
+    #[inline(always)]
+    pub fn encode_crc_en(&self) -> ENCODE_CRC_EN_R {
+        ENCODE_CRC_EN_R::new(((self.bits >> 10) & 1) != 0)
+    }
+    #[doc = "Bit 11 - 1'b1: Force clock on for register. 1'b0: Support clock only when application writes registers."]
+    #[inline(always)]
+    pub fn clk_en(&self) -> CLK_EN_R {
+        CLK_EN_R::new(((self.bits >> 11) & 1) != 0)
+    }
+    #[doc = "Bit 12 - If this bit is set to 1, UHCI will end payload receive process when NULL frame is received by UART."]
+    #[inline(always)]
+    pub fn uart_rx_brk_eof_en(&self) -> UART_RX_BRK_EOF_EN_R {
+        UART_RX_BRK_EOF_EN_R::new(((self.bits >> 12) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CONF0")
+            .field("tx_rst", &self.tx_rst())
+            .field("rx_rst", &self.rx_rst())
+            .field("uart0_ce", &self.uart0_ce())
+            .field("uart1_ce", &self.uart1_ce())
+            .field("uart2_ce", &self.uart2_ce())
+            .field("seper_en", &self.seper_en())
+            .field("head_en", &self.head_en())
+            .field("crc_rec_en", &self.crc_rec_en())
+            .field("uart_idle_eof_en", &self.uart_idle_eof_en())
+            .field("len_eof_en", &self.len_eof_en())
+            .field("encode_crc_en", &self.encode_crc_en())
+            .field("clk_en", &self.clk_en())
+            .field("uart_rx_brk_eof_en", &self.uart_rx_brk_eof_en())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Write 1, then write 0 to this bit to reset decode state machine."]
+    #[inline(always)]
+    pub fn tx_rst(&mut self) -> TX_RST_W<CONF0_SPEC> {
+        TX_RST_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - Write 1, then write 0 to this bit to reset encode state machine."]
+    #[inline(always)]
+    pub fn rx_rst(&mut self) -> RX_RST_W<CONF0_SPEC> {
+        RX_RST_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - Set this bit to link up HCI and UART0."]
+    #[inline(always)]
+    pub fn uart0_ce(&mut self) -> UART0_CE_W<CONF0_SPEC> {
+        UART0_CE_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - Set this bit to link up HCI and UART1."]
+    #[inline(always)]
+    pub fn uart1_ce(&mut self) -> UART1_CE_W<CONF0_SPEC> {
+        UART1_CE_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - Set this bit to link up HCI and UART2."]
+    #[inline(always)]
+    pub fn uart2_ce(&mut self) -> UART2_CE_W<CONF0_SPEC> {
+        UART2_CE_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - Set this bit to separate the data frame using a special char."]
+    #[inline(always)]
+    pub fn seper_en(&mut self) -> SEPER_EN_W<CONF0_SPEC> {
+        SEPER_EN_W::new(self, 5)
+    }
+    #[doc = "Bit 6 - Set this bit to encode the data packet with a formatting header."]
+    #[inline(always)]
+    pub fn head_en(&mut self) -> HEAD_EN_W<CONF0_SPEC> {
+        HEAD_EN_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - Set this bit to enable UHCI to receive the 16 bit CRC."]
+    #[inline(always)]
+    pub fn crc_rec_en(&mut self) -> CRC_REC_EN_W<CONF0_SPEC> {
+        CRC_REC_EN_W::new(self, 7)
+    }
+    #[doc = "Bit 8 - If this bit is set to 1, UHCI will end the payload receiving process when UART has been in idle state."]
+    #[inline(always)]
+    pub fn uart_idle_eof_en(&mut self) -> UART_IDLE_EOF_EN_W<CONF0_SPEC> {
+        UART_IDLE_EOF_EN_W::new(self, 8)
+    }
+    #[doc = "Bit 9 - If this bit is set to 1, UHCI decoder receiving payload data is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0, UHCI decoder receiving payload data is end when 0xc0 is received."]
+    #[inline(always)]
+    pub fn len_eof_en(&mut self) -> LEN_EOF_EN_W<CONF0_SPEC> {
+        LEN_EOF_EN_W::new(self, 9)
+    }
+    #[doc = "Bit 10 - Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to end of the payload."]
+    #[inline(always)]
+    pub fn encode_crc_en(&mut self) -> ENCODE_CRC_EN_W<CONF0_SPEC> {
+        ENCODE_CRC_EN_W::new(self, 10)
+    }
+    #[doc = "Bit 11 - 1'b1: Force clock on for register. 1'b0: Support clock only when application writes registers."]
+    #[inline(always)]
+    pub fn clk_en(&mut self) -> CLK_EN_W<CONF0_SPEC> {
+        CLK_EN_W::new(self, 11)
+    }
+    #[doc = "Bit 12 - If this bit is set to 1, UHCI will end payload receive process when NULL frame is received by UART."]
+    #[inline(always)]
+    pub fn uart_rx_brk_eof_en(&mut self) -> UART_RX_BRK_EOF_EN_W<CONF0_SPEC> {
+        UART_RX_BRK_EOF_EN_W::new(self, 12)
+    }
+}
+#[doc = "UHCI configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`conf0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`conf0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CONF0_SPEC;
+impl crate::RegisterSpec for CONF0_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`conf0::R`](R) reader structure"]
+impl crate::Readable for CONF0_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`conf0::W`](W) writer structure"]
+impl crate::Writable for CONF0_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CONF0 to value 0x06e0"]
+impl crate::Resettable for CONF0_SPEC {
+    const RESET_VALUE: u32 = 0x06e0;
+}

vendor/esp32s3/src/uhci0/conf1.rs

@@ -0,0 +1,152 @@
+#[doc = "Register `CONF1` reader"]
+pub type R = crate::R<CONF1_SPEC>;
+#[doc = "Register `CONF1` writer"]
+pub type W = crate::W<CONF1_SPEC>;
+#[doc = "Field `CHECK_SUM_EN` reader - This is the enable bit to check header checksum when UHCI receives a data packet."]
+pub type CHECK_SUM_EN_R = crate::BitReader;
+#[doc = "Field `CHECK_SUM_EN` writer - This is the enable bit to check header checksum when UHCI receives a data packet."]
+pub type CHECK_SUM_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CHECK_SEQ_EN` reader - This is the enable bit to check sequence number when UHCI receives a data packet."]
+pub type CHECK_SEQ_EN_R = crate::BitReader;
+#[doc = "Field `CHECK_SEQ_EN` writer - This is the enable bit to check sequence number when UHCI receives a data packet."]
+pub type CHECK_SEQ_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CRC_DISABLE` reader - Set this bit to support CRC calculation. Data Integrity Check Present bit in UHCI packet frame should be 1."]
+pub type CRC_DISABLE_R = crate::BitReader;
+#[doc = "Field `CRC_DISABLE` writer - Set this bit to support CRC calculation. Data Integrity Check Present bit in UHCI packet frame should be 1."]
+pub type CRC_DISABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SAVE_HEAD` reader - Set this bit to save the packet header when HCI receives a data packet."]
+pub type SAVE_HEAD_R = crate::BitReader;
+#[doc = "Field `SAVE_HEAD` writer - Set this bit to save the packet header when HCI receives a data packet."]
+pub type SAVE_HEAD_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TX_CHECK_SUM_RE` reader - Set this bit to encode the data packet with a checksum."]
+pub type TX_CHECK_SUM_RE_R = crate::BitReader;
+#[doc = "Field `TX_CHECK_SUM_RE` writer - Set this bit to encode the data packet with a checksum."]
+pub type TX_CHECK_SUM_RE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TX_ACK_NUM_RE` reader - Set this bit to encode the data packet with an acknowledgment when a reliable packet is to be transmit."]
+pub type TX_ACK_NUM_RE_R = crate::BitReader;
+#[doc = "Field `TX_ACK_NUM_RE` writer - Set this bit to encode the data packet with an acknowledgment when a reliable packet is to be transmit."]
+pub type TX_ACK_NUM_RE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `WAIT_SW_START` reader - The uhci-encoder will jump to ST_SW_WAIT status if this register is set to 1."]
+pub type WAIT_SW_START_R = crate::BitReader;
+#[doc = "Field `WAIT_SW_START` writer - The uhci-encoder will jump to ST_SW_WAIT status if this register is set to 1."]
+pub type WAIT_SW_START_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SW_START` reader - If current UHCI_ENCODE_STATE is ST_SW_WAIT, the UHCI will start to send data packet out when this bit is set to 1."]
+pub type SW_START_R = crate::BitReader;
+#[doc = "Field `SW_START` writer - If current UHCI_ENCODE_STATE is ST_SW_WAIT, the UHCI will start to send data packet out when this bit is set to 1."]
+pub type SW_START_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - This is the enable bit to check header checksum when UHCI receives a data packet."]
+    #[inline(always)]
+    pub fn check_sum_en(&self) -> CHECK_SUM_EN_R {
+        CHECK_SUM_EN_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - This is the enable bit to check sequence number when UHCI receives a data packet."]
+    #[inline(always)]
+    pub fn check_seq_en(&self) -> CHECK_SEQ_EN_R {
+        CHECK_SEQ_EN_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Set this bit to support CRC calculation. Data Integrity Check Present bit in UHCI packet frame should be 1."]
+    #[inline(always)]
+    pub fn crc_disable(&self) -> CRC_DISABLE_R {
+        CRC_DISABLE_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Set this bit to save the packet header when HCI receives a data packet."]
+    #[inline(always)]
+    pub fn save_head(&self) -> SAVE_HEAD_R {
+        SAVE_HEAD_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Set this bit to encode the data packet with a checksum."]
+    #[inline(always)]
+    pub fn tx_check_sum_re(&self) -> TX_CHECK_SUM_RE_R {
+        TX_CHECK_SUM_RE_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - Set this bit to encode the data packet with an acknowledgment when a reliable packet is to be transmit."]
+    #[inline(always)]
+    pub fn tx_ack_num_re(&self) -> TX_ACK_NUM_RE_R {
+        TX_ACK_NUM_RE_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 7 - The uhci-encoder will jump to ST_SW_WAIT status if this register is set to 1."]
+    #[inline(always)]
+    pub fn wait_sw_start(&self) -> WAIT_SW_START_R {
+        WAIT_SW_START_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - If current UHCI_ENCODE_STATE is ST_SW_WAIT, the UHCI will start to send data packet out when this bit is set to 1."]
+    #[inline(always)]
+    pub fn sw_start(&self) -> SW_START_R {
+        SW_START_R::new(((self.bits >> 8) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CONF1")
+            .field("check_sum_en", &self.check_sum_en())
+            .field("check_seq_en", &self.check_seq_en())
+            .field("crc_disable", &self.crc_disable())
+            .field("save_head", &self.save_head())
+            .field("tx_check_sum_re", &self.tx_check_sum_re())
+            .field("tx_ack_num_re", &self.tx_ack_num_re())
+            .field("wait_sw_start", &self.wait_sw_start())
+            .field("sw_start", &self.sw_start())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - This is the enable bit to check header checksum when UHCI receives a data packet."]
+    #[inline(always)]
+    pub fn check_sum_en(&mut self) -> CHECK_SUM_EN_W<CONF1_SPEC> {
+        CHECK_SUM_EN_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - This is the enable bit to check sequence number when UHCI receives a data packet."]
+    #[inline(always)]
+    pub fn check_seq_en(&mut self) -> CHECK_SEQ_EN_W<CONF1_SPEC> {
+        CHECK_SEQ_EN_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - Set this bit to support CRC calculation. Data Integrity Check Present bit in UHCI packet frame should be 1."]
+    #[inline(always)]
+    pub fn crc_disable(&mut self) -> CRC_DISABLE_W<CONF1_SPEC> {
+        CRC_DISABLE_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - Set this bit to save the packet header when HCI receives a data packet."]
+    #[inline(always)]
+    pub fn save_head(&mut self) -> SAVE_HEAD_W<CONF1_SPEC> {
+        SAVE_HEAD_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - Set this bit to encode the data packet with a checksum."]
+    #[inline(always)]
+    pub fn tx_check_sum_re(&mut self) -> TX_CHECK_SUM_RE_W<CONF1_SPEC> {
+        TX_CHECK_SUM_RE_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - Set this bit to encode the data packet with an acknowledgment when a reliable packet is to be transmit."]
+    #[inline(always)]
+    pub fn tx_ack_num_re(&mut self) -> TX_ACK_NUM_RE_W<CONF1_SPEC> {
+        TX_ACK_NUM_RE_W::new(self, 5)
+    }
+    #[doc = "Bit 7 - The uhci-encoder will jump to ST_SW_WAIT status if this register is set to 1."]
+    #[inline(always)]
+    pub fn wait_sw_start(&mut self) -> WAIT_SW_START_W<CONF1_SPEC> {
+        WAIT_SW_START_W::new(self, 7)
+    }
+    #[doc = "Bit 8 - If current UHCI_ENCODE_STATE is ST_SW_WAIT, the UHCI will start to send data packet out when this bit is set to 1."]
+    #[inline(always)]
+    pub fn sw_start(&mut self) -> SW_START_W<CONF1_SPEC> {
+        SW_START_W::new(self, 8)
+    }
+}
+#[doc = "UHCI configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`conf1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`conf1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CONF1_SPEC;
+impl crate::RegisterSpec for CONF1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`conf1::R`](R) reader structure"]
+impl crate::Readable for CONF1_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`conf1::W`](W) writer structure"]
+impl crate::Writable for CONF1_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CONF1 to value 0x33"]
+impl crate::Resettable for CONF1_SPEC {
+    const RESET_VALUE: u32 = 0x33;
+}

vendor/esp32s3/src/uhci0/date.rs

@@ -0,0 +1,45 @@
+#[doc = "Register `DATE` reader"]
+pub type R = crate::R<DATE_SPEC>;
+#[doc = "Register `DATE` writer"]
+pub type W = crate::W<DATE_SPEC>;
+#[doc = "Field `DATE` reader - This is the version control register."]
+pub type DATE_R = crate::FieldReader<u32>;
+#[doc = "Field `DATE` writer - This is the version control register."]
+pub type DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - This is the version control register."]
+    #[inline(always)]
+    pub fn date(&self) -> DATE_R {
+        DATE_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DATE").field("date", &self.date()).finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - This is the version control register."]
+    #[inline(always)]
+    pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
+        DATE_W::new(self, 0)
+    }
+}
+#[doc = "UHCI version control register\n\nYou can [`read`](crate::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DATE_SPEC;
+impl crate::RegisterSpec for DATE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`date::R`](R) reader structure"]
+impl crate::Readable for DATE_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"]
+impl crate::Writable for DATE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DATE to value 0x0201_0090"]
+impl crate::Resettable for DATE_SPEC {
+    const RESET_VALUE: u32 = 0x0201_0090;
+}

vendor/esp32s3/src/uhci0/esc_conf.rs

@@ -0,0 +1,77 @@
+#[doc = "Register `ESC_CONF%s` reader"]
+pub type R = crate::R<ESC_CONF_SPEC>;
+#[doc = "Register `ESC_CONF%s` writer"]
+pub type W = crate::W<ESC_CONF_SPEC>;
+#[doc = "Field `SEPER_CHAR` reader - This register is used to define the separate char that need to be encoded, default is 0xc0."]
+pub type SEPER_CHAR_R = crate::FieldReader;
+#[doc = "Field `SEPER_CHAR` writer - This register is used to define the separate char that need to be encoded, default is 0xc0."]
+pub type SEPER_CHAR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+#[doc = "Field `SEPER_ESC_CHAR0` reader - This register is used to define the first char of slip escape sequence when encoding the separate char, default is 0xdb."]
+pub type SEPER_ESC_CHAR0_R = crate::FieldReader;
+#[doc = "Field `SEPER_ESC_CHAR0` writer - This register is used to define the first char of slip escape sequence when encoding the separate char, default is 0xdb."]
+pub type SEPER_ESC_CHAR0_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+#[doc = "Field `SEPER_ESC_CHAR1` reader - This register is used to define the second char of slip escape sequence when encoding the separate char, default is 0xdc."]
+pub type SEPER_ESC_CHAR1_R = crate::FieldReader;
+#[doc = "Field `SEPER_ESC_CHAR1` writer - This register is used to define the second char of slip escape sequence when encoding the separate char, default is 0xdc."]
+pub type SEPER_ESC_CHAR1_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+impl R {
+    #[doc = "Bits 0:7 - This register is used to define the separate char that need to be encoded, default is 0xc0."]
+    #[inline(always)]
+    pub fn seper_char(&self) -> SEPER_CHAR_R {
+        SEPER_CHAR_R::new((self.bits & 0xff) as u8)
+    }
+    #[doc = "Bits 8:15 - This register is used to define the first char of slip escape sequence when encoding the separate char, default is 0xdb."]
+    #[inline(always)]
+    pub fn seper_esc_char0(&self) -> SEPER_ESC_CHAR0_R {
+        SEPER_ESC_CHAR0_R::new(((self.bits >> 8) & 0xff) as u8)
+    }
+    #[doc = "Bits 16:23 - This register is used to define the second char of slip escape sequence when encoding the separate char, default is 0xdc."]
+    #[inline(always)]
+    pub fn seper_esc_char1(&self) -> SEPER_ESC_CHAR1_R {
+        SEPER_ESC_CHAR1_R::new(((self.bits >> 16) & 0xff) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("ESC_CONF")
+            .field("seper_char", &self.seper_char())
+            .field("seper_esc_char0", &self.seper_esc_char0())
+            .field("seper_esc_char1", &self.seper_esc_char1())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - This register is used to define the separate char that need to be encoded, default is 0xc0."]
+    #[inline(always)]
+    pub fn seper_char(&mut self) -> SEPER_CHAR_W<ESC_CONF_SPEC> {
+        SEPER_CHAR_W::new(self, 0)
+    }
+    #[doc = "Bits 8:15 - This register is used to define the first char of slip escape sequence when encoding the separate char, default is 0xdb."]
+    #[inline(always)]
+    pub fn seper_esc_char0(&mut self) -> SEPER_ESC_CHAR0_W<ESC_CONF_SPEC> {
+        SEPER_ESC_CHAR0_W::new(self, 8)
+    }
+    #[doc = "Bits 16:23 - This register is used to define the second char of slip escape sequence when encoding the separate char, default is 0xdc."]
+    #[inline(always)]
+    pub fn seper_esc_char1(&mut self) -> SEPER_ESC_CHAR1_W<ESC_CONF_SPEC> {
+        SEPER_ESC_CHAR1_W::new(self, 16)
+    }
+}
+#[doc = "Escape sequence configuration register %s\n\nYou can [`read`](crate::Reg::read) this register and get [`esc_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esc_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ESC_CONF_SPEC;
+impl crate::RegisterSpec for ESC_CONF_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`esc_conf::R`](R) reader structure"]
+impl crate::Readable for ESC_CONF_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`esc_conf::W`](W) writer structure"]
+impl crate::Writable for ESC_CONF_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets ESC_CONF%s to value 0x00dc_dbc0"]
+impl crate::Resettable for ESC_CONF_SPEC {
+    const RESET_VALUE: u32 = 0x00dc_dbc0;
+}

vendor/esp32s3/src/uhci0/escape_conf.rs

@@ -0,0 +1,152 @@
+#[doc = "Register `ESCAPE_CONF` reader"]
+pub type R = crate::R<ESCAPE_CONF_SPEC>;
+#[doc = "Register `ESCAPE_CONF` writer"]
+pub type W = crate::W<ESCAPE_CONF_SPEC>;
+#[doc = "Field `TX_C0_ESC_EN` reader - Set this bit to enable decoding char 0xc0 when DMA receives data."]
+pub type TX_C0_ESC_EN_R = crate::BitReader;
+#[doc = "Field `TX_C0_ESC_EN` writer - Set this bit to enable decoding char 0xc0 when DMA receives data."]
+pub type TX_C0_ESC_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TX_DB_ESC_EN` reader - Set this bit to enable decoding char 0xdb when DMA receives data."]
+pub type TX_DB_ESC_EN_R = crate::BitReader;
+#[doc = "Field `TX_DB_ESC_EN` writer - Set this bit to enable decoding char 0xdb when DMA receives data."]
+pub type TX_DB_ESC_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TX_11_ESC_EN` reader - Set this bit to enable decoding flow control char 0x11 when DMA receives data."]
+pub type TX_11_ESC_EN_R = crate::BitReader;
+#[doc = "Field `TX_11_ESC_EN` writer - Set this bit to enable decoding flow control char 0x11 when DMA receives data."]
+pub type TX_11_ESC_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TX_13_ESC_EN` reader - Set this bit to enable decoding flow control char 0x13 when DMA receives data."]
+pub type TX_13_ESC_EN_R = crate::BitReader;
+#[doc = "Field `TX_13_ESC_EN` writer - Set this bit to enable decoding flow control char 0x13 when DMA receives data."]
+pub type TX_13_ESC_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RX_C0_ESC_EN` reader - Set this bit to enable replacing 0xc0 by special char when DMA sends data."]
+pub type RX_C0_ESC_EN_R = crate::BitReader;
+#[doc = "Field `RX_C0_ESC_EN` writer - Set this bit to enable replacing 0xc0 by special char when DMA sends data."]
+pub type RX_C0_ESC_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RX_DB_ESC_EN` reader - Set this bit to enable replacing 0xdb by special char when DMA sends data."]
+pub type RX_DB_ESC_EN_R = crate::BitReader;
+#[doc = "Field `RX_DB_ESC_EN` writer - Set this bit to enable replacing 0xdb by special char when DMA sends data."]
+pub type RX_DB_ESC_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RX_11_ESC_EN` reader - Set this bit to enable replacing flow control char 0x11 by special char when DMA sends data."]
+pub type RX_11_ESC_EN_R = crate::BitReader;
+#[doc = "Field `RX_11_ESC_EN` writer - Set this bit to enable replacing flow control char 0x11 by special char when DMA sends data."]
+pub type RX_11_ESC_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RX_13_ESC_EN` reader - Set this bit to enable replacing flow control char 0x13 by special char when DMA sends data."]
+pub type RX_13_ESC_EN_R = crate::BitReader;
+#[doc = "Field `RX_13_ESC_EN` writer - Set this bit to enable replacing flow control char 0x13 by special char when DMA sends data."]
+pub type RX_13_ESC_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Set this bit to enable decoding char 0xc0 when DMA receives data."]
+    #[inline(always)]
+    pub fn tx_c0_esc_en(&self) -> TX_C0_ESC_EN_R {
+        TX_C0_ESC_EN_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Set this bit to enable decoding char 0xdb when DMA receives data."]
+    #[inline(always)]
+    pub fn tx_db_esc_en(&self) -> TX_DB_ESC_EN_R {
+        TX_DB_ESC_EN_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Set this bit to enable decoding flow control char 0x11 when DMA receives data."]
+    #[inline(always)]
+    pub fn tx_11_esc_en(&self) -> TX_11_ESC_EN_R {
+        TX_11_ESC_EN_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Set this bit to enable decoding flow control char 0x13 when DMA receives data."]
+    #[inline(always)]
+    pub fn tx_13_esc_en(&self) -> TX_13_ESC_EN_R {
+        TX_13_ESC_EN_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Set this bit to enable replacing 0xc0 by special char when DMA sends data."]
+    #[inline(always)]
+    pub fn rx_c0_esc_en(&self) -> RX_C0_ESC_EN_R {
+        RX_C0_ESC_EN_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - Set this bit to enable replacing 0xdb by special char when DMA sends data."]
+    #[inline(always)]
+    pub fn rx_db_esc_en(&self) -> RX_DB_ESC_EN_R {
+        RX_DB_ESC_EN_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - Set this bit to enable replacing flow control char 0x11 by special char when DMA sends data."]
+    #[inline(always)]
+    pub fn rx_11_esc_en(&self) -> RX_11_ESC_EN_R {
+        RX_11_ESC_EN_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - Set this bit to enable replacing flow control char 0x13 by special char when DMA sends data."]
+    #[inline(always)]
+    pub fn rx_13_esc_en(&self) -> RX_13_ESC_EN_R {
+        RX_13_ESC_EN_R::new(((self.bits >> 7) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("ESCAPE_CONF")
+            .field("tx_c0_esc_en", &self.tx_c0_esc_en())
+            .field("tx_db_esc_en", &self.tx_db_esc_en())
+            .field("tx_11_esc_en", &self.tx_11_esc_en())
+            .field("tx_13_esc_en", &self.tx_13_esc_en())
+            .field("rx_c0_esc_en", &self.rx_c0_esc_en())
+            .field("rx_db_esc_en", &self.rx_db_esc_en())
+            .field("rx_11_esc_en", &self.rx_11_esc_en())
+            .field("rx_13_esc_en", &self.rx_13_esc_en())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Set this bit to enable decoding char 0xc0 when DMA receives data."]
+    #[inline(always)]
+    pub fn tx_c0_esc_en(&mut self) -> TX_C0_ESC_EN_W<ESCAPE_CONF_SPEC> {
+        TX_C0_ESC_EN_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - Set this bit to enable decoding char 0xdb when DMA receives data."]
+    #[inline(always)]
+    pub fn tx_db_esc_en(&mut self) -> TX_DB_ESC_EN_W<ESCAPE_CONF_SPEC> {
+        TX_DB_ESC_EN_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - Set this bit to enable decoding flow control char 0x11 when DMA receives data."]
+    #[inline(always)]
+    pub fn tx_11_esc_en(&mut self) -> TX_11_ESC_EN_W<ESCAPE_CONF_SPEC> {
+        TX_11_ESC_EN_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - Set this bit to enable decoding flow control char 0x13 when DMA receives data."]
+    #[inline(always)]
+    pub fn tx_13_esc_en(&mut self) -> TX_13_ESC_EN_W<ESCAPE_CONF_SPEC> {
+        TX_13_ESC_EN_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - Set this bit to enable replacing 0xc0 by special char when DMA sends data."]
+    #[inline(always)]
+    pub fn rx_c0_esc_en(&mut self) -> RX_C0_ESC_EN_W<ESCAPE_CONF_SPEC> {
+        RX_C0_ESC_EN_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - Set this bit to enable replacing 0xdb by special char when DMA sends data."]
+    #[inline(always)]
+    pub fn rx_db_esc_en(&mut self) -> RX_DB_ESC_EN_W<ESCAPE_CONF_SPEC> {
+        RX_DB_ESC_EN_W::new(self, 5)
+    }
+    #[doc = "Bit 6 - Set this bit to enable replacing flow control char 0x11 by special char when DMA sends data."]
+    #[inline(always)]
+    pub fn rx_11_esc_en(&mut self) -> RX_11_ESC_EN_W<ESCAPE_CONF_SPEC> {
+        RX_11_ESC_EN_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - Set this bit to enable replacing flow control char 0x13 by special char when DMA sends data."]
+    #[inline(always)]
+    pub fn rx_13_esc_en(&mut self) -> RX_13_ESC_EN_W<ESCAPE_CONF_SPEC> {
+        RX_13_ESC_EN_W::new(self, 7)
+    }
+}
+#[doc = "Escape character configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`escape_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`escape_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ESCAPE_CONF_SPEC;
+impl crate::RegisterSpec for ESCAPE_CONF_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`escape_conf::R`](R) reader structure"]
+impl crate::Readable for ESCAPE_CONF_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`escape_conf::W`](W) writer structure"]
+impl crate::Writable for ESCAPE_CONF_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets ESCAPE_CONF to value 0x33"]
+impl crate::Resettable for ESCAPE_CONF_SPEC {
+    const RESET_VALUE: u32 = 0x33;
+}

vendor/esp32s3/src/uhci0/hung_conf.rs

@@ -0,0 +1,122 @@
+#[doc = "Register `HUNG_CONF` reader"]
+pub type R = crate::R<HUNG_CONF_SPEC>;
+#[doc = "Register `HUNG_CONF` writer"]
+pub type W = crate::W<HUNG_CONF_SPEC>;
+#[doc = "Field `TXFIFO_TIMEOUT` reader - This register stores the timeout value. It will produce the UHCI_TX_HUNG_INT interrupt when DMA takes more time to receive data."]
+pub type TXFIFO_TIMEOUT_R = crate::FieldReader;
+#[doc = "Field `TXFIFO_TIMEOUT` writer - This register stores the timeout value. It will produce the UHCI_TX_HUNG_INT interrupt when DMA takes more time to receive data."]
+pub type TXFIFO_TIMEOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+#[doc = "Field `TXFIFO_TIMEOUT_SHIFT` reader - This register is used to configure the tick count maximum value."]
+pub type TXFIFO_TIMEOUT_SHIFT_R = crate::FieldReader;
+#[doc = "Field `TXFIFO_TIMEOUT_SHIFT` writer - This register is used to configure the tick count maximum value."]
+pub type TXFIFO_TIMEOUT_SHIFT_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `TXFIFO_TIMEOUT_ENA` reader - This is the enable bit for Tx-FIFO receive-data timeout."]
+pub type TXFIFO_TIMEOUT_ENA_R = crate::BitReader;
+#[doc = "Field `TXFIFO_TIMEOUT_ENA` writer - This is the enable bit for Tx-FIFO receive-data timeout."]
+pub type TXFIFO_TIMEOUT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RXFIFO_TIMEOUT` reader - This register stores the timeout value. It will produce the UHCI_RX_HUNG_INT interrupt when DMA takes more time to read data from RAM."]
+pub type RXFIFO_TIMEOUT_R = crate::FieldReader;
+#[doc = "Field `RXFIFO_TIMEOUT` writer - This register stores the timeout value. It will produce the UHCI_RX_HUNG_INT interrupt when DMA takes more time to read data from RAM."]
+pub type RXFIFO_TIMEOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+#[doc = "Field `RXFIFO_TIMEOUT_SHIFT` reader - This register is used to configure the tick count maximum value."]
+pub type RXFIFO_TIMEOUT_SHIFT_R = crate::FieldReader;
+#[doc = "Field `RXFIFO_TIMEOUT_SHIFT` writer - This register is used to configure the tick count maximum value."]
+pub type RXFIFO_TIMEOUT_SHIFT_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `RXFIFO_TIMEOUT_ENA` reader - This is the enable bit for DMA send-data timeout."]
+pub type RXFIFO_TIMEOUT_ENA_R = crate::BitReader;
+#[doc = "Field `RXFIFO_TIMEOUT_ENA` writer - This is the enable bit for DMA send-data timeout."]
+pub type RXFIFO_TIMEOUT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 0:7 - This register stores the timeout value. It will produce the UHCI_TX_HUNG_INT interrupt when DMA takes more time to receive data."]
+    #[inline(always)]
+    pub fn txfifo_timeout(&self) -> TXFIFO_TIMEOUT_R {
+        TXFIFO_TIMEOUT_R::new((self.bits & 0xff) as u8)
+    }
+    #[doc = "Bits 8:10 - This register is used to configure the tick count maximum value."]
+    #[inline(always)]
+    pub fn txfifo_timeout_shift(&self) -> TXFIFO_TIMEOUT_SHIFT_R {
+        TXFIFO_TIMEOUT_SHIFT_R::new(((self.bits >> 8) & 7) as u8)
+    }
+    #[doc = "Bit 11 - This is the enable bit for Tx-FIFO receive-data timeout."]
+    #[inline(always)]
+    pub fn txfifo_timeout_ena(&self) -> TXFIFO_TIMEOUT_ENA_R {
+        TXFIFO_TIMEOUT_ENA_R::new(((self.bits >> 11) & 1) != 0)
+    }
+    #[doc = "Bits 12:19 - This register stores the timeout value. It will produce the UHCI_RX_HUNG_INT interrupt when DMA takes more time to read data from RAM."]
+    #[inline(always)]
+    pub fn rxfifo_timeout(&self) -> RXFIFO_TIMEOUT_R {
+        RXFIFO_TIMEOUT_R::new(((self.bits >> 12) & 0xff) as u8)
+    }
+    #[doc = "Bits 20:22 - This register is used to configure the tick count maximum value."]
+    #[inline(always)]
+    pub fn rxfifo_timeout_shift(&self) -> RXFIFO_TIMEOUT_SHIFT_R {
+        RXFIFO_TIMEOUT_SHIFT_R::new(((self.bits >> 20) & 7) as u8)
+    }
+    #[doc = "Bit 23 - This is the enable bit for DMA send-data timeout."]
+    #[inline(always)]
+    pub fn rxfifo_timeout_ena(&self) -> RXFIFO_TIMEOUT_ENA_R {
+        RXFIFO_TIMEOUT_ENA_R::new(((self.bits >> 23) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("HUNG_CONF")
+            .field("txfifo_timeout", &self.txfifo_timeout())
+            .field("txfifo_timeout_shift", &self.txfifo_timeout_shift())
+            .field("txfifo_timeout_ena", &self.txfifo_timeout_ena())
+            .field("rxfifo_timeout", &self.rxfifo_timeout())
+            .field("rxfifo_timeout_shift", &self.rxfifo_timeout_shift())
+            .field("rxfifo_timeout_ena", &self.rxfifo_timeout_ena())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - This register stores the timeout value. It will produce the UHCI_TX_HUNG_INT interrupt when DMA takes more time to receive data."]
+    #[inline(always)]
+    pub fn txfifo_timeout(&mut self) -> TXFIFO_TIMEOUT_W<HUNG_CONF_SPEC> {
+        TXFIFO_TIMEOUT_W::new(self, 0)
+    }
+    #[doc = "Bits 8:10 - This register is used to configure the tick count maximum value."]
+    #[inline(always)]
+    pub fn txfifo_timeout_shift(&mut self) -> TXFIFO_TIMEOUT_SHIFT_W<HUNG_CONF_SPEC> {
+        TXFIFO_TIMEOUT_SHIFT_W::new(self, 8)
+    }
+    #[doc = "Bit 11 - This is the enable bit for Tx-FIFO receive-data timeout."]
+    #[inline(always)]
+    pub fn txfifo_timeout_ena(&mut self) -> TXFIFO_TIMEOUT_ENA_W<HUNG_CONF_SPEC> {
+        TXFIFO_TIMEOUT_ENA_W::new(self, 11)
+    }
+    #[doc = "Bits 12:19 - This register stores the timeout value. It will produce the UHCI_RX_HUNG_INT interrupt when DMA takes more time to read data from RAM."]
+    #[inline(always)]
+    pub fn rxfifo_timeout(&mut self) -> RXFIFO_TIMEOUT_W<HUNG_CONF_SPEC> {
+        RXFIFO_TIMEOUT_W::new(self, 12)
+    }
+    #[doc = "Bits 20:22 - This register is used to configure the tick count maximum value."]
+    #[inline(always)]
+    pub fn rxfifo_timeout_shift(&mut self) -> RXFIFO_TIMEOUT_SHIFT_W<HUNG_CONF_SPEC> {
+        RXFIFO_TIMEOUT_SHIFT_W::new(self, 20)
+    }
+    #[doc = "Bit 23 - This is the enable bit for DMA send-data timeout."]
+    #[inline(always)]
+    pub fn rxfifo_timeout_ena(&mut self) -> RXFIFO_TIMEOUT_ENA_W<HUNG_CONF_SPEC> {
+        RXFIFO_TIMEOUT_ENA_W::new(self, 23)
+    }
+}
+#[doc = "Timeout configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`hung_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hung_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct HUNG_CONF_SPEC;
+impl crate::RegisterSpec for HUNG_CONF_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`hung_conf::R`](R) reader structure"]
+impl crate::Readable for HUNG_CONF_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`hung_conf::W`](W) writer structure"]
+impl crate::Writable for HUNG_CONF_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets HUNG_CONF to value 0x0081_0810"]
+impl crate::Resettable for HUNG_CONF_SPEC {
+    const RESET_VALUE: u32 = 0x0081_0810;
+}

vendor/esp32s3/src/uhci0/int_clr.rs

@@ -0,0 +1,88 @@
+#[doc = "Register `INT_CLR` writer"]
+pub type W = crate::W<INT_CLR_SPEC>;
+#[doc = "Field `RX_START` writer - Set this bit to clear UHCI_RX_START_INT interrupt."]
+pub type RX_START_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TX_START` writer - Set this bit to clear UHCI_TX_START_INT interrupt."]
+pub type TX_START_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `RX_HUNG` writer - Set this bit to clear UHCI_RX_HUNG_INT interrupt."]
+pub type RX_HUNG_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `TX_HUNG` writer - Set this bit to clear UHCI_TX_HUNG_INT interrupt."]
+pub type TX_HUNG_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `SEND_S_REG_Q` writer - Set this bit to clear UHCI_SEND_S_REQ_Q_INT interrupt."]
+pub type SEND_S_REG_Q_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `SEND_A_REG_Q` writer - Set this bit to clear UHCI_SEND_A_REQ_Q_INT interrupt."]
+pub type SEND_A_REG_Q_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `OUTLINK_EOF_ERR` writer - Set this bit to clear UHCI_OUTLINK_EOF_ERR_INT interrupt."]
+pub type OUTLINK_EOF_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `APP_CTRL0` writer - Set this bit to clear UHCI_APP_CTRL0_INT interrupt."]
+pub type APP_CTRL0_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[doc = "Field `APP_CTRL1` writer - Set this bit to clear UHCI_APP_CTRL1_INT interrupt."]
+pub type APP_CTRL1_W<'a, REG> = crate::BitWriter1C<'a, REG>;
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "(not readable)")
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Set this bit to clear UHCI_RX_START_INT interrupt."]
+    #[inline(always)]
+    pub fn rx_start(&mut self) -> RX_START_W<INT_CLR_SPEC> {
+        RX_START_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - Set this bit to clear UHCI_TX_START_INT interrupt."]
+    #[inline(always)]
+    pub fn tx_start(&mut self) -> TX_START_W<INT_CLR_SPEC> {
+        TX_START_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - Set this bit to clear UHCI_RX_HUNG_INT interrupt."]
+    #[inline(always)]
+    pub fn rx_hung(&mut self) -> RX_HUNG_W<INT_CLR_SPEC> {
+        RX_HUNG_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - Set this bit to clear UHCI_TX_HUNG_INT interrupt."]
+    #[inline(always)]
+    pub fn tx_hung(&mut self) -> TX_HUNG_W<INT_CLR_SPEC> {
+        TX_HUNG_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - Set this bit to clear UHCI_SEND_S_REQ_Q_INT interrupt."]
+    #[inline(always)]
+    pub fn send_s_reg_q(&mut self) -> SEND_S_REG_Q_W<INT_CLR_SPEC> {
+        SEND_S_REG_Q_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - Set this bit to clear UHCI_SEND_A_REQ_Q_INT interrupt."]
+    #[inline(always)]
+    pub fn send_a_reg_q(&mut self) -> SEND_A_REG_Q_W<INT_CLR_SPEC> {
+        SEND_A_REG_Q_W::new(self, 5)
+    }
+    #[doc = "Bit 6 - Set this bit to clear UHCI_OUTLINK_EOF_ERR_INT interrupt."]
+    #[inline(always)]
+    pub fn outlink_eof_err(&mut self) -> OUTLINK_EOF_ERR_W<INT_CLR_SPEC> {
+        OUTLINK_EOF_ERR_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - Set this bit to clear UHCI_APP_CTRL0_INT interrupt."]
+    #[inline(always)]
+    pub fn app_ctrl0(&mut self) -> APP_CTRL0_W<INT_CLR_SPEC> {
+        APP_CTRL0_W::new(self, 7)
+    }
+    #[doc = "Bit 8 - Set this bit to clear UHCI_APP_CTRL1_INT interrupt."]
+    #[inline(always)]
+    pub fn app_ctrl1(&mut self) -> APP_CTRL1_W<INT_CLR_SPEC> {
+        APP_CTRL1_W::new(self, 8)
+    }
+}
+#[doc = "Interrupt clear bits\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct INT_CLR_SPEC;
+impl crate::RegisterSpec for INT_CLR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
+impl crate::Writable for INT_CLR_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x01ff;
+}
+#[doc = "`reset()` method sets INT_CLR to value 0"]
+impl crate::Resettable for INT_CLR_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/uhci0/int_ena.rs

@@ -0,0 +1,167 @@
+#[doc = "Register `INT_ENA` reader"]
+pub type R = crate::R<INT_ENA_SPEC>;
+#[doc = "Register `INT_ENA` writer"]
+pub type W = crate::W<INT_ENA_SPEC>;
+#[doc = "Field `RX_START` reader - This is the interrupt enable bit for UHCI_RX_START_INT interrupt."]
+pub type RX_START_R = crate::BitReader;
+#[doc = "Field `RX_START` writer - This is the interrupt enable bit for UHCI_RX_START_INT interrupt."]
+pub type RX_START_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TX_START` reader - This is the interrupt enable bit for UHCI_TX_START_INT interrupt."]
+pub type TX_START_R = crate::BitReader;
+#[doc = "Field `TX_START` writer - This is the interrupt enable bit for UHCI_TX_START_INT interrupt."]
+pub type TX_START_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RX_HUNG` reader - This is the interrupt enable bit for UHCI_RX_HUNG_INT interrupt."]
+pub type RX_HUNG_R = crate::BitReader;
+#[doc = "Field `RX_HUNG` writer - This is the interrupt enable bit for UHCI_RX_HUNG_INT interrupt."]
+pub type RX_HUNG_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TX_HUNG` reader - This is the interrupt enable bit for UHCI_TX_HUNG_INT interrupt."]
+pub type TX_HUNG_R = crate::BitReader;
+#[doc = "Field `TX_HUNG` writer - This is the interrupt enable bit for UHCI_TX_HUNG_INT interrupt."]
+pub type TX_HUNG_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SEND_S_REG_Q` reader - This is the interrupt enable bit for UHCI_SEND_S_REQ_Q_INT interrupt."]
+pub type SEND_S_REG_Q_R = crate::BitReader;
+#[doc = "Field `SEND_S_REG_Q` writer - This is the interrupt enable bit for UHCI_SEND_S_REQ_Q_INT interrupt."]
+pub type SEND_S_REG_Q_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SEND_A_REG_Q` reader - This is the interrupt enable bit for UHCI_SEND_A_REQ_Q_INT interrupt."]
+pub type SEND_A_REG_Q_R = crate::BitReader;
+#[doc = "Field `SEND_A_REG_Q` writer - This is the interrupt enable bit for UHCI_SEND_A_REQ_Q_INT interrupt."]
+pub type SEND_A_REG_Q_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `OUTLINK_EOF_ERR` reader - This is the interrupt enable bit for UHCI_OUTLINK_EOF_ERR_INT interrupt."]
+pub type OUTLINK_EOF_ERR_R = crate::BitReader;
+#[doc = "Field `OUTLINK_EOF_ERR` writer - This is the interrupt enable bit for UHCI_OUTLINK_EOF_ERR_INT interrupt."]
+pub type OUTLINK_EOF_ERR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `APP_CTRL0` reader - This is the interrupt enable bit for UHCI_APP_CTRL0_INT interrupt."]
+pub type APP_CTRL0_R = crate::BitReader;
+#[doc = "Field `APP_CTRL0` writer - This is the interrupt enable bit for UHCI_APP_CTRL0_INT interrupt."]
+pub type APP_CTRL0_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `APP_CTRL1` reader - This is the interrupt enable bit for UHCI_APP_CTRL1_INT interrupt."]
+pub type APP_CTRL1_R = crate::BitReader;
+#[doc = "Field `APP_CTRL1` writer - This is the interrupt enable bit for UHCI_APP_CTRL1_INT interrupt."]
+pub type APP_CTRL1_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - This is the interrupt enable bit for UHCI_RX_START_INT interrupt."]
+    #[inline(always)]
+    pub fn rx_start(&self) -> RX_START_R {
+        RX_START_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - This is the interrupt enable bit for UHCI_TX_START_INT interrupt."]
+    #[inline(always)]
+    pub fn tx_start(&self) -> TX_START_R {
+        TX_START_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - This is the interrupt enable bit for UHCI_RX_HUNG_INT interrupt."]
+    #[inline(always)]
+    pub fn rx_hung(&self) -> RX_HUNG_R {
+        RX_HUNG_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - This is the interrupt enable bit for UHCI_TX_HUNG_INT interrupt."]
+    #[inline(always)]
+    pub fn tx_hung(&self) -> TX_HUNG_R {
+        TX_HUNG_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - This is the interrupt enable bit for UHCI_SEND_S_REQ_Q_INT interrupt."]
+    #[inline(always)]
+    pub fn send_s_reg_q(&self) -> SEND_S_REG_Q_R {
+        SEND_S_REG_Q_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - This is the interrupt enable bit for UHCI_SEND_A_REQ_Q_INT interrupt."]
+    #[inline(always)]
+    pub fn send_a_reg_q(&self) -> SEND_A_REG_Q_R {
+        SEND_A_REG_Q_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - This is the interrupt enable bit for UHCI_OUTLINK_EOF_ERR_INT interrupt."]
+    #[inline(always)]
+    pub fn outlink_eof_err(&self) -> OUTLINK_EOF_ERR_R {
+        OUTLINK_EOF_ERR_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - This is the interrupt enable bit for UHCI_APP_CTRL0_INT interrupt."]
+    #[inline(always)]
+    pub fn app_ctrl0(&self) -> APP_CTRL0_R {
+        APP_CTRL0_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - This is the interrupt enable bit for UHCI_APP_CTRL1_INT interrupt."]
+    #[inline(always)]
+    pub fn app_ctrl1(&self) -> APP_CTRL1_R {
+        APP_CTRL1_R::new(((self.bits >> 8) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("INT_ENA")
+            .field("rx_start", &self.rx_start())
+            .field("tx_start", &self.tx_start())
+            .field("rx_hung", &self.rx_hung())
+            .field("tx_hung", &self.tx_hung())
+            .field("send_s_reg_q", &self.send_s_reg_q())
+            .field("send_a_reg_q", &self.send_a_reg_q())
+            .field("outlink_eof_err", &self.outlink_eof_err())
+            .field("app_ctrl0", &self.app_ctrl0())
+            .field("app_ctrl1", &self.app_ctrl1())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - This is the interrupt enable bit for UHCI_RX_START_INT interrupt."]
+    #[inline(always)]
+    pub fn rx_start(&mut self) -> RX_START_W<INT_ENA_SPEC> {
+        RX_START_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - This is the interrupt enable bit for UHCI_TX_START_INT interrupt."]
+    #[inline(always)]
+    pub fn tx_start(&mut self) -> TX_START_W<INT_ENA_SPEC> {
+        TX_START_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - This is the interrupt enable bit for UHCI_RX_HUNG_INT interrupt."]
+    #[inline(always)]
+    pub fn rx_hung(&mut self) -> RX_HUNG_W<INT_ENA_SPEC> {
+        RX_HUNG_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - This is the interrupt enable bit for UHCI_TX_HUNG_INT interrupt."]
+    #[inline(always)]
+    pub fn tx_hung(&mut self) -> TX_HUNG_W<INT_ENA_SPEC> {
+        TX_HUNG_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - This is the interrupt enable bit for UHCI_SEND_S_REQ_Q_INT interrupt."]
+    #[inline(always)]
+    pub fn send_s_reg_q(&mut self) -> SEND_S_REG_Q_W<INT_ENA_SPEC> {
+        SEND_S_REG_Q_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - This is the interrupt enable bit for UHCI_SEND_A_REQ_Q_INT interrupt."]
+    #[inline(always)]
+    pub fn send_a_reg_q(&mut self) -> SEND_A_REG_Q_W<INT_ENA_SPEC> {
+        SEND_A_REG_Q_W::new(self, 5)
+    }
+    #[doc = "Bit 6 - This is the interrupt enable bit for UHCI_OUTLINK_EOF_ERR_INT interrupt."]
+    #[inline(always)]
+    pub fn outlink_eof_err(&mut self) -> OUTLINK_EOF_ERR_W<INT_ENA_SPEC> {
+        OUTLINK_EOF_ERR_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - This is the interrupt enable bit for UHCI_APP_CTRL0_INT interrupt."]
+    #[inline(always)]
+    pub fn app_ctrl0(&mut self) -> APP_CTRL0_W<INT_ENA_SPEC> {
+        APP_CTRL0_W::new(self, 7)
+    }
+    #[doc = "Bit 8 - This is the interrupt enable bit for UHCI_APP_CTRL1_INT interrupt."]
+    #[inline(always)]
+    pub fn app_ctrl1(&mut self) -> APP_CTRL1_W<INT_ENA_SPEC> {
+        APP_CTRL1_W::new(self, 8)
+    }
+}
+#[doc = "Interrupt enable bits\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct INT_ENA_SPEC;
+impl crate::RegisterSpec for INT_ENA_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"]
+impl crate::Readable for INT_ENA_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"]
+impl crate::Writable for INT_ENA_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets INT_ENA to value 0"]
+impl crate::Resettable for INT_ENA_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/uhci0/int_raw.rs

@@ -0,0 +1,167 @@
+#[doc = "Register `INT_RAW` reader"]
+pub type R = crate::R<INT_RAW_SPEC>;
+#[doc = "Register `INT_RAW` writer"]
+pub type W = crate::W<INT_RAW_SPEC>;
+#[doc = "Field `RX_START` reader - This is the interrupt raw bit. Triggered when a separator char has been sent."]
+pub type RX_START_R = crate::BitReader;
+#[doc = "Field `RX_START` writer - This is the interrupt raw bit. Triggered when a separator char has been sent."]
+pub type RX_START_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TX_START` reader - This is the interrupt raw bit. Triggered when UHCI detects a separator char."]
+pub type TX_START_R = crate::BitReader;
+#[doc = "Field `TX_START` writer - This is the interrupt raw bit. Triggered when UHCI detects a separator char."]
+pub type TX_START_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `RX_HUNG` reader - This is the interrupt raw bit. Triggered when UHCI takes more time to receive data than configure value."]
+pub type RX_HUNG_R = crate::BitReader;
+#[doc = "Field `RX_HUNG` writer - This is the interrupt raw bit. Triggered when UHCI takes more time to receive data than configure value."]
+pub type RX_HUNG_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TX_HUNG` reader - This is the interrupt raw bit. Triggered when UHCI takes more time to read data from RAM than the configured value."]
+pub type TX_HUNG_R = crate::BitReader;
+#[doc = "Field `TX_HUNG` writer - This is the interrupt raw bit. Triggered when UHCI takes more time to read data from RAM than the configured value."]
+pub type TX_HUNG_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SEND_S_REG_Q` reader - This is the interrupt raw bit. Triggered when UHCI has sent out a short packet using single_send registers."]
+pub type SEND_S_REG_Q_R = crate::BitReader;
+#[doc = "Field `SEND_S_REG_Q` writer - This is the interrupt raw bit. Triggered when UHCI has sent out a short packet using single_send registers."]
+pub type SEND_S_REG_Q_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SEND_A_REG_Q` reader - This is the interrupt raw bit. Triggered when UHCI has sent out a short packet using always_send registers."]
+pub type SEND_A_REG_Q_R = crate::BitReader;
+#[doc = "Field `SEND_A_REG_Q` writer - This is the interrupt raw bit. Triggered when UHCI has sent out a short packet using always_send registers."]
+pub type SEND_A_REG_Q_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `OUT_EOF` reader - This is the interrupt raw bit. Triggered when there are some errors in EOF in the transmit data."]
+pub type OUT_EOF_R = crate::BitReader;
+#[doc = "Field `OUT_EOF` writer - This is the interrupt raw bit. Triggered when there are some errors in EOF in the transmit data."]
+pub type OUT_EOF_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `APP_CTRL0` reader - This is the interrupt raw bit. Triggered when set UHCI_APP_CTRL0_IN_SET."]
+pub type APP_CTRL0_R = crate::BitReader;
+#[doc = "Field `APP_CTRL0` writer - This is the interrupt raw bit. Triggered when set UHCI_APP_CTRL0_IN_SET."]
+pub type APP_CTRL0_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `APP_CTRL1` reader - This is the interrupt raw bit. Triggered when set UHCI_APP_CTRL1_IN_SET."]
+pub type APP_CTRL1_R = crate::BitReader;
+#[doc = "Field `APP_CTRL1` writer - This is the interrupt raw bit. Triggered when set UHCI_APP_CTRL1_IN_SET."]
+pub type APP_CTRL1_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - This is the interrupt raw bit. Triggered when a separator char has been sent."]
+    #[inline(always)]
+    pub fn rx_start(&self) -> RX_START_R {
+        RX_START_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - This is the interrupt raw bit. Triggered when UHCI detects a separator char."]
+    #[inline(always)]
+    pub fn tx_start(&self) -> TX_START_R {
+        TX_START_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - This is the interrupt raw bit. Triggered when UHCI takes more time to receive data than configure value."]
+    #[inline(always)]
+    pub fn rx_hung(&self) -> RX_HUNG_R {
+        RX_HUNG_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - This is the interrupt raw bit. Triggered when UHCI takes more time to read data from RAM than the configured value."]
+    #[inline(always)]
+    pub fn tx_hung(&self) -> TX_HUNG_R {
+        TX_HUNG_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - This is the interrupt raw bit. Triggered when UHCI has sent out a short packet using single_send registers."]
+    #[inline(always)]
+    pub fn send_s_reg_q(&self) -> SEND_S_REG_Q_R {
+        SEND_S_REG_Q_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - This is the interrupt raw bit. Triggered when UHCI has sent out a short packet using always_send registers."]
+    #[inline(always)]
+    pub fn send_a_reg_q(&self) -> SEND_A_REG_Q_R {
+        SEND_A_REG_Q_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - This is the interrupt raw bit. Triggered when there are some errors in EOF in the transmit data."]
+    #[inline(always)]
+    pub fn out_eof(&self) -> OUT_EOF_R {
+        OUT_EOF_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - This is the interrupt raw bit. Triggered when set UHCI_APP_CTRL0_IN_SET."]
+    #[inline(always)]
+    pub fn app_ctrl0(&self) -> APP_CTRL0_R {
+        APP_CTRL0_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - This is the interrupt raw bit. Triggered when set UHCI_APP_CTRL1_IN_SET."]
+    #[inline(always)]
+    pub fn app_ctrl1(&self) -> APP_CTRL1_R {
+        APP_CTRL1_R::new(((self.bits >> 8) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("INT_RAW")
+            .field("rx_start", &self.rx_start())
+            .field("tx_start", &self.tx_start())
+            .field("rx_hung", &self.rx_hung())
+            .field("tx_hung", &self.tx_hung())
+            .field("send_s_reg_q", &self.send_s_reg_q())
+            .field("send_a_reg_q", &self.send_a_reg_q())
+            .field("out_eof", &self.out_eof())
+            .field("app_ctrl0", &self.app_ctrl0())
+            .field("app_ctrl1", &self.app_ctrl1())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - This is the interrupt raw bit. Triggered when a separator char has been sent."]
+    #[inline(always)]
+    pub fn rx_start(&mut self) -> RX_START_W<INT_RAW_SPEC> {
+        RX_START_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - This is the interrupt raw bit. Triggered when UHCI detects a separator char."]
+    #[inline(always)]
+    pub fn tx_start(&mut self) -> TX_START_W<INT_RAW_SPEC> {
+        TX_START_W::new(self, 1)
+    }
+    #[doc = "Bit 2 - This is the interrupt raw bit. Triggered when UHCI takes more time to receive data than configure value."]
+    #[inline(always)]
+    pub fn rx_hung(&mut self) -> RX_HUNG_W<INT_RAW_SPEC> {
+        RX_HUNG_W::new(self, 2)
+    }
+    #[doc = "Bit 3 - This is the interrupt raw bit. Triggered when UHCI takes more time to read data from RAM than the configured value."]
+    #[inline(always)]
+    pub fn tx_hung(&mut self) -> TX_HUNG_W<INT_RAW_SPEC> {
+        TX_HUNG_W::new(self, 3)
+    }
+    #[doc = "Bit 4 - This is the interrupt raw bit. Triggered when UHCI has sent out a short packet using single_send registers."]
+    #[inline(always)]
+    pub fn send_s_reg_q(&mut self) -> SEND_S_REG_Q_W<INT_RAW_SPEC> {
+        SEND_S_REG_Q_W::new(self, 4)
+    }
+    #[doc = "Bit 5 - This is the interrupt raw bit. Triggered when UHCI has sent out a short packet using always_send registers."]
+    #[inline(always)]
+    pub fn send_a_reg_q(&mut self) -> SEND_A_REG_Q_W<INT_RAW_SPEC> {
+        SEND_A_REG_Q_W::new(self, 5)
+    }
+    #[doc = "Bit 6 - This is the interrupt raw bit. Triggered when there are some errors in EOF in the transmit data."]
+    #[inline(always)]
+    pub fn out_eof(&mut self) -> OUT_EOF_W<INT_RAW_SPEC> {
+        OUT_EOF_W::new(self, 6)
+    }
+    #[doc = "Bit 7 - This is the interrupt raw bit. Triggered when set UHCI_APP_CTRL0_IN_SET."]
+    #[inline(always)]
+    pub fn app_ctrl0(&mut self) -> APP_CTRL0_W<INT_RAW_SPEC> {
+        APP_CTRL0_W::new(self, 7)
+    }
+    #[doc = "Bit 8 - This is the interrupt raw bit. Triggered when set UHCI_APP_CTRL1_IN_SET."]
+    #[inline(always)]
+    pub fn app_ctrl1(&mut self) -> APP_CTRL1_W<INT_RAW_SPEC> {
+        APP_CTRL1_W::new(self, 8)
+    }
+}
+#[doc = "Raw interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`int_raw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_raw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct INT_RAW_SPEC;
+impl crate::RegisterSpec for INT_RAW_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"]
+impl crate::Readable for INT_RAW_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`int_raw::W`](W) writer structure"]
+impl crate::Writable for INT_RAW_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets INT_RAW to value 0"]
+impl crate::Resettable for INT_RAW_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/uhci0/int_st.rs

@@ -0,0 +1,94 @@
+#[doc = "Register `INT_ST` reader"]
+pub type R = crate::R<INT_ST_SPEC>;
+#[doc = "Field `RX_START` reader - This is the masked interrupt bit for UHCI_RX_START_INT interrupt when UHCI_RX_START_INT_ENA is set to 1."]
+pub type RX_START_R = crate::BitReader;
+#[doc = "Field `TX_START` reader - This is the masked interrupt bit for UHCI_TX_START_INT interrupt when UHCI_TX_START_INT_ENA is set to 1."]
+pub type TX_START_R = crate::BitReader;
+#[doc = "Field `RX_HUNG` reader - This is the masked interrupt bit for UHCI_RX_HUNG_INT interrupt when UHCI_RX_HUNG_INT_ENA is set to 1."]
+pub type RX_HUNG_R = crate::BitReader;
+#[doc = "Field `TX_HUNG` reader - This is the masked interrupt bit for UHCI_TX_HUNG_INT interrupt when UHCI_TX_HUNG_INT_ENA is set to 1."]
+pub type TX_HUNG_R = crate::BitReader;
+#[doc = "Field `SEND_S_REG_Q` reader - This is the masked interrupt bit for UHCI_SEND_S_REQ_Q_INT interrupt when UHCI_SEND_S_REQ_Q_INT_ENA is set to 1."]
+pub type SEND_S_REG_Q_R = crate::BitReader;
+#[doc = "Field `SEND_A_REG_Q` reader - This is the masked interrupt bit for UHCI_SEND_A_REQ_Q_INT interrupt when UHCI_SEND_A_REQ_Q_INT_ENA is set to 1."]
+pub type SEND_A_REG_Q_R = crate::BitReader;
+#[doc = "Field `OUTLINK_EOF_ERR` reader - This is the masked interrupt bit for UHCI_OUTLINK_EOF_ERR_INT interrupt when UHCI_OUTLINK_EOF_ERR_INT_ENA is set to 1."]
+pub type OUTLINK_EOF_ERR_R = crate::BitReader;
+#[doc = "Field `APP_CTRL0` reader - This is the masked interrupt bit for UHCI_APP_CTRL0_INT interrupt when UHCI_APP_CTRL0_INT_ENA is set to 1."]
+pub type APP_CTRL0_R = crate::BitReader;
+#[doc = "Field `APP_CTRL1` reader - This is the masked interrupt bit for UHCI_APP_CTRL1_INT interrupt when UHCI_APP_CTRL1_INT_ENA is set to 1."]
+pub type APP_CTRL1_R = crate::BitReader;
+impl R {
+    #[doc = "Bit 0 - This is the masked interrupt bit for UHCI_RX_START_INT interrupt when UHCI_RX_START_INT_ENA is set to 1."]
+    #[inline(always)]
+    pub fn rx_start(&self) -> RX_START_R {
+        RX_START_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - This is the masked interrupt bit for UHCI_TX_START_INT interrupt when UHCI_TX_START_INT_ENA is set to 1."]
+    #[inline(always)]
+    pub fn tx_start(&self) -> TX_START_R {
+        TX_START_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - This is the masked interrupt bit for UHCI_RX_HUNG_INT interrupt when UHCI_RX_HUNG_INT_ENA is set to 1."]
+    #[inline(always)]
+    pub fn rx_hung(&self) -> RX_HUNG_R {
+        RX_HUNG_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - This is the masked interrupt bit for UHCI_TX_HUNG_INT interrupt when UHCI_TX_HUNG_INT_ENA is set to 1."]
+    #[inline(always)]
+    pub fn tx_hung(&self) -> TX_HUNG_R {
+        TX_HUNG_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - This is the masked interrupt bit for UHCI_SEND_S_REQ_Q_INT interrupt when UHCI_SEND_S_REQ_Q_INT_ENA is set to 1."]
+    #[inline(always)]
+    pub fn send_s_reg_q(&self) -> SEND_S_REG_Q_R {
+        SEND_S_REG_Q_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - This is the masked interrupt bit for UHCI_SEND_A_REQ_Q_INT interrupt when UHCI_SEND_A_REQ_Q_INT_ENA is set to 1."]
+    #[inline(always)]
+    pub fn send_a_reg_q(&self) -> SEND_A_REG_Q_R {
+        SEND_A_REG_Q_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - This is the masked interrupt bit for UHCI_OUTLINK_EOF_ERR_INT interrupt when UHCI_OUTLINK_EOF_ERR_INT_ENA is set to 1."]
+    #[inline(always)]
+    pub fn outlink_eof_err(&self) -> OUTLINK_EOF_ERR_R {
+        OUTLINK_EOF_ERR_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - This is the masked interrupt bit for UHCI_APP_CTRL0_INT interrupt when UHCI_APP_CTRL0_INT_ENA is set to 1."]
+    #[inline(always)]
+    pub fn app_ctrl0(&self) -> APP_CTRL0_R {
+        APP_CTRL0_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - This is the masked interrupt bit for UHCI_APP_CTRL1_INT interrupt when UHCI_APP_CTRL1_INT_ENA is set to 1."]
+    #[inline(always)]
+    pub fn app_ctrl1(&self) -> APP_CTRL1_R {
+        APP_CTRL1_R::new(((self.bits >> 8) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("INT_ST")
+            .field("rx_start", &self.rx_start())
+            .field("tx_start", &self.tx_start())
+            .field("rx_hung", &self.rx_hung())
+            .field("tx_hung", &self.tx_hung())
+            .field("send_s_reg_q", &self.send_s_reg_q())
+            .field("send_a_reg_q", &self.send_a_reg_q())
+            .field("outlink_eof_err", &self.outlink_eof_err())
+            .field("app_ctrl0", &self.app_ctrl0())
+            .field("app_ctrl1", &self.app_ctrl1())
+            .finish()
+    }
+}
+#[doc = "Masked interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct INT_ST_SPEC;
+impl crate::RegisterSpec for INT_ST_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`int_st::R`](R) reader structure"]
+impl crate::Readable for INT_ST_SPEC {}
+#[doc = "`reset()` method sets INT_ST to value 0"]
+impl crate::Resettable for INT_ST_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/uhci0/pkt_thres.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `PKT_THRES` reader"]
+pub type R = crate::R<PKT_THRES_SPEC>;
+#[doc = "Register `PKT_THRES` writer"]
+pub type W = crate::W<PKT_THRES_SPEC>;
+#[doc = "Field `PKT_THRS` reader - This register is used to configure the maximum value of the packet length when UHCI_HEAD_EN is 0."]
+pub type PKT_THRS_R = crate::FieldReader<u16>;
+#[doc = "Field `PKT_THRS` writer - This register is used to configure the maximum value of the packet length when UHCI_HEAD_EN is 0."]
+pub type PKT_THRS_W<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>;
+impl R {
+    #[doc = "Bits 0:12 - This register is used to configure the maximum value of the packet length when UHCI_HEAD_EN is 0."]
+    #[inline(always)]
+    pub fn pkt_thrs(&self) -> PKT_THRS_R {
+        PKT_THRS_R::new((self.bits & 0x1fff) as u16)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("PKT_THRES")
+            .field("pkt_thrs", &self.pkt_thrs())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:12 - This register is used to configure the maximum value of the packet length when UHCI_HEAD_EN is 0."]
+    #[inline(always)]
+    pub fn pkt_thrs(&mut self) -> PKT_THRS_W<PKT_THRES_SPEC> {
+        PKT_THRS_W::new(self, 0)
+    }
+}
+#[doc = "Configure register for packet length\n\nYou can [`read`](crate::Reg::read) this register and get [`pkt_thres::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkt_thres::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct PKT_THRES_SPEC;
+impl crate::RegisterSpec for PKT_THRES_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`pkt_thres::R`](R) reader structure"]
+impl crate::Readable for PKT_THRES_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`pkt_thres::W`](W) writer structure"]
+impl crate::Writable for PKT_THRES_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets PKT_THRES to value 0x80"]
+impl crate::Resettable for PKT_THRES_SPEC {
+    const RESET_VALUE: u32 = 0x80;
+}

vendor/esp32s3/src/uhci0/quick_sent.rs

@@ -0,0 +1,92 @@
+#[doc = "Register `QUICK_SENT` reader"]
+pub type R = crate::R<QUICK_SENT_SPEC>;
+#[doc = "Register `QUICK_SENT` writer"]
+pub type W = crate::W<QUICK_SENT_SPEC>;
+#[doc = "Field `SINGLE_SEND_NUM` reader - This register is used to specify the single_send register."]
+pub type SINGLE_SEND_NUM_R = crate::FieldReader;
+#[doc = "Field `SINGLE_SEND_NUM` writer - This register is used to specify the single_send register."]
+pub type SINGLE_SEND_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `SINGLE_SEND_EN` reader - Set this bit to enable single_send mode to send short packet."]
+pub type SINGLE_SEND_EN_R = crate::BitReader;
+#[doc = "Field `SINGLE_SEND_EN` writer - Set this bit to enable single_send mode to send short packet."]
+pub type SINGLE_SEND_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ALWAYS_SEND_NUM` reader - This register is used to specify the always_send register."]
+pub type ALWAYS_SEND_NUM_R = crate::FieldReader;
+#[doc = "Field `ALWAYS_SEND_NUM` writer - This register is used to specify the always_send register."]
+pub type ALWAYS_SEND_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `ALWAYS_SEND_EN` reader - Set this bit to enable always_send mode to send short packet."]
+pub type ALWAYS_SEND_EN_R = crate::BitReader;
+#[doc = "Field `ALWAYS_SEND_EN` writer - Set this bit to enable always_send mode to send short packet."]
+pub type ALWAYS_SEND_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 0:2 - This register is used to specify the single_send register."]
+    #[inline(always)]
+    pub fn single_send_num(&self) -> SINGLE_SEND_NUM_R {
+        SINGLE_SEND_NUM_R::new((self.bits & 7) as u8)
+    }
+    #[doc = "Bit 3 - Set this bit to enable single_send mode to send short packet."]
+    #[inline(always)]
+    pub fn single_send_en(&self) -> SINGLE_SEND_EN_R {
+        SINGLE_SEND_EN_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bits 4:6 - This register is used to specify the always_send register."]
+    #[inline(always)]
+    pub fn always_send_num(&self) -> ALWAYS_SEND_NUM_R {
+        ALWAYS_SEND_NUM_R::new(((self.bits >> 4) & 7) as u8)
+    }
+    #[doc = "Bit 7 - Set this bit to enable always_send mode to send short packet."]
+    #[inline(always)]
+    pub fn always_send_en(&self) -> ALWAYS_SEND_EN_R {
+        ALWAYS_SEND_EN_R::new(((self.bits >> 7) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("QUICK_SENT")
+            .field("single_send_num", &self.single_send_num())
+            .field("single_send_en", &self.single_send_en())
+            .field("always_send_num", &self.always_send_num())
+            .field("always_send_en", &self.always_send_en())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:2 - This register is used to specify the single_send register."]
+    #[inline(always)]
+    pub fn single_send_num(&mut self) -> SINGLE_SEND_NUM_W<QUICK_SENT_SPEC> {
+        SINGLE_SEND_NUM_W::new(self, 0)
+    }
+    #[doc = "Bit 3 - Set this bit to enable single_send mode to send short packet."]
+    #[inline(always)]
+    pub fn single_send_en(&mut self) -> SINGLE_SEND_EN_W<QUICK_SENT_SPEC> {
+        SINGLE_SEND_EN_W::new(self, 3)
+    }
+    #[doc = "Bits 4:6 - This register is used to specify the always_send register."]
+    #[inline(always)]
+    pub fn always_send_num(&mut self) -> ALWAYS_SEND_NUM_W<QUICK_SENT_SPEC> {
+        ALWAYS_SEND_NUM_W::new(self, 4)
+    }
+    #[doc = "Bit 7 - Set this bit to enable always_send mode to send short packet."]
+    #[inline(always)]
+    pub fn always_send_en(&mut self) -> ALWAYS_SEND_EN_W<QUICK_SENT_SPEC> {
+        ALWAYS_SEND_EN_W::new(self, 7)
+    }
+}
+#[doc = "UHCI quick send configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`quick_sent::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`quick_sent::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct QUICK_SENT_SPEC;
+impl crate::RegisterSpec for QUICK_SENT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`quick_sent::R`](R) reader structure"]
+impl crate::Readable for QUICK_SENT_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`quick_sent::W`](W) writer structure"]
+impl crate::Writable for QUICK_SENT_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets QUICK_SENT to value 0"]
+impl crate::Resettable for QUICK_SENT_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/uhci0/reg_q.rs

@@ -0,0 +1,27 @@
+#[repr(C)]
+#[cfg_attr(feature = "impl-register-debug", derive(Debug))]
+#[doc = "Cluster REG_Q%s, containing REG_Q?_WORD0, REG_Q?_WORD1"]
+pub struct REG_Q {
+    word0: WORD0,
+    word1: WORD1,
+}
+impl REG_Q {
+    #[doc = "0x00 - Q0_WORD0 quick_sent register"]
+    #[inline(always)]
+    pub const fn word0(&self) -> &WORD0 {
+        &self.word0
+    }
+    #[doc = "0x04 - Q0_WORD1 quick_sent register"]
+    #[inline(always)]
+    pub const fn word1(&self) -> &WORD1 {
+        &self.word1
+    }
+}
+#[doc = "WORD0 (rw) register accessor: Q0_WORD0 quick_sent register\n\nYou can [`read`](crate::Reg::read) this register and get [`word0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`word0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@word0`] module"]
+pub type WORD0 = crate::Reg<word0::WORD0_SPEC>;
+#[doc = "Q0_WORD0 quick_sent register"]
+pub mod word0;
+#[doc = "WORD1 (rw) register accessor: Q0_WORD1 quick_sent register\n\nYou can [`read`](crate::Reg::read) this register and get [`word1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`word1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@word1`] module"]
+pub type WORD1 = crate::Reg<word1::WORD1_SPEC>;
+#[doc = "Q0_WORD1 quick_sent register"]
+pub mod word1;

vendor/esp32s3/src/uhci0/reg_q/word0.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `WORD0` reader"]
+pub type R = crate::R<WORD0_SPEC>;
+#[doc = "Register `WORD0` writer"]
+pub type W = crate::W<WORD0_SPEC>;
+#[doc = "Field `SEND_WORD` reader - This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."]
+pub type SEND_WORD_R = crate::FieldReader<u32>;
+#[doc = "Field `SEND_WORD` writer - This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."]
+pub type SEND_WORD_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."]
+    #[inline(always)]
+    pub fn send_word(&self) -> SEND_WORD_R {
+        SEND_WORD_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("WORD0")
+            .field("send_word", &self.send_word())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."]
+    #[inline(always)]
+    pub fn send_word(&mut self) -> SEND_WORD_W<WORD0_SPEC> {
+        SEND_WORD_W::new(self, 0)
+    }
+}
+#[doc = "Q0_WORD0 quick_sent register\n\nYou can [`read`](crate::Reg::read) this register and get [`word0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`word0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct WORD0_SPEC;
+impl crate::RegisterSpec for WORD0_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`word0::R`](R) reader structure"]
+impl crate::Readable for WORD0_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`word0::W`](W) writer structure"]
+impl crate::Writable for WORD0_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets WORD0 to value 0"]
+impl crate::Resettable for WORD0_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/uhci0/reg_q/word1.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `WORD1` reader"]
+pub type R = crate::R<WORD1_SPEC>;
+#[doc = "Register `WORD1` writer"]
+pub type W = crate::W<WORD1_SPEC>;
+#[doc = "Field `SEND_WORD` reader - This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."]
+pub type SEND_WORD_R = crate::FieldReader<u32>;
+#[doc = "Field `SEND_WORD` writer - This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."]
+pub type SEND_WORD_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."]
+    #[inline(always)]
+    pub fn send_word(&self) -> SEND_WORD_R {
+        SEND_WORD_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("WORD1")
+            .field("send_word", &self.send_word())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."]
+    #[inline(always)]
+    pub fn send_word(&mut self) -> SEND_WORD_W<WORD1_SPEC> {
+        SEND_WORD_W::new(self, 0)
+    }
+}
+#[doc = "Q0_WORD1 quick_sent register\n\nYou can [`read`](crate::Reg::read) this register and get [`word1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`word1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct WORD1_SPEC;
+impl crate::RegisterSpec for WORD1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`word1::R`](R) reader structure"]
+impl crate::Readable for WORD1_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`word1::W`](W) writer structure"]
+impl crate::Writable for WORD1_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets WORD1 to value 0"]
+impl crate::Resettable for WORD1_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/uhci0/rx_head.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `RX_HEAD` reader"]
+pub type R = crate::R<RX_HEAD_SPEC>;
+#[doc = "Field `RX_HEAD` reader - This register stores the header of the current received packet."]
+pub type RX_HEAD_R = crate::FieldReader<u32>;
+impl R {
+    #[doc = "Bits 0:31 - This register stores the header of the current received packet."]
+    #[inline(always)]
+    pub fn rx_head(&self) -> RX_HEAD_R {
+        RX_HEAD_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("RX_HEAD")
+            .field("rx_head", &self.rx_head())
+            .finish()
+    }
+}
+#[doc = "UHCI packet header register\n\nYou can [`read`](crate::Reg::read) this register and get [`rx_head::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct RX_HEAD_SPEC;
+impl crate::RegisterSpec for RX_HEAD_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`rx_head::R`](R) reader structure"]
+impl crate::Readable for RX_HEAD_SPEC {}
+#[doc = "`reset()` method sets RX_HEAD to value 0"]
+impl crate::Resettable for RX_HEAD_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/uhci0/state0.rs

@@ -0,0 +1,38 @@
+#[doc = "Register `STATE0` reader"]
+pub type R = crate::R<STATE0_SPEC>;
+#[doc = "Field `RX_ERR_CAUSE` reader - This register indicates the error type when DMA has received a packet with error. 3'b001: Checksum error in HCI packet. 3'b010: Sequence number error in HCI packet. 3'b011: CRC bit error in HCI packet. 3'b100: 0xc0 is found but received HCI packet is not end. 3'b101: 0xc0 is not found when receiving HCI packet is end. 3'b110: CRC check error."]
+pub type RX_ERR_CAUSE_R = crate::FieldReader;
+#[doc = "Field `DECODE_STATE` reader - UHCI decoder status."]
+pub type DECODE_STATE_R = crate::FieldReader;
+impl R {
+    #[doc = "Bits 0:2 - This register indicates the error type when DMA has received a packet with error. 3'b001: Checksum error in HCI packet. 3'b010: Sequence number error in HCI packet. 3'b011: CRC bit error in HCI packet. 3'b100: 0xc0 is found but received HCI packet is not end. 3'b101: 0xc0 is not found when receiving HCI packet is end. 3'b110: CRC check error."]
+    #[inline(always)]
+    pub fn rx_err_cause(&self) -> RX_ERR_CAUSE_R {
+        RX_ERR_CAUSE_R::new((self.bits & 7) as u8)
+    }
+    #[doc = "Bits 3:5 - UHCI decoder status."]
+    #[inline(always)]
+    pub fn decode_state(&self) -> DECODE_STATE_R {
+        DECODE_STATE_R::new(((self.bits >> 3) & 7) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("STATE0")
+            .field("rx_err_cause", &self.rx_err_cause())
+            .field("decode_state", &self.decode_state())
+            .finish()
+    }
+}
+#[doc = "UHCI receive status\n\nYou can [`read`](crate::Reg::read) this register and get [`state0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct STATE0_SPEC;
+impl crate::RegisterSpec for STATE0_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`state0::R`](R) reader structure"]
+impl crate::Readable for STATE0_SPEC {}
+#[doc = "`reset()` method sets STATE0 to value 0"]
+impl crate::Resettable for STATE0_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/uhci0/state1.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `STATE1` reader"]
+pub type R = crate::R<STATE1_SPEC>;
+#[doc = "Field `ENCODE_STATE` reader - UHCI encoder status."]
+pub type ENCODE_STATE_R = crate::FieldReader;
+impl R {
+    #[doc = "Bits 0:2 - UHCI encoder status."]
+    #[inline(always)]
+    pub fn encode_state(&self) -> ENCODE_STATE_R {
+        ENCODE_STATE_R::new((self.bits & 7) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("STATE1")
+            .field("encode_state", &self.encode_state())
+            .finish()
+    }
+}
+#[doc = "UHCI transmit status\n\nYou can [`read`](crate::Reg::read) this register and get [`state1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct STATE1_SPEC;
+impl crate::RegisterSpec for STATE1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`state1::R`](R) reader structure"]
+impl crate::Readable for STATE1_SPEC {}
+#[doc = "`reset()` method sets STATE1 to value 0"]
+impl crate::Resettable for STATE1_SPEC {
+    const RESET_VALUE: u32 = 0;
+}