feat: add display UI with splash screen, dashboard, and RSSI sparkline

Implement full SSD1306 OLED display support:
- Splash screen on boot (1.5s) with project name, version, board
- Dashboard showing radio state, config, counters, RSSI/SNR
- RSSI history sparkline (64-sample ring buffer, 2px-wide bars)
- DisplayOn/DisplayOff host commands routed via dedicated channel
- Pure render functions against generic DrawTarget (no hardware coupling)
- Display on/off control bypasses radio task entirely

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>

vendor/esp32s3/src/xts_aes/date.rs

@@ -0,0 +1,45 @@
+#[doc = "Register `DATE` reader"]
+pub type R = crate::R<DATE_SPEC>;
+#[doc = "Register `DATE` writer"]
+pub type W = crate::W<DATE_SPEC>;
+#[doc = "Field `DATE` reader - Manual Encryption block version information."]
+pub type DATE_R = crate::FieldReader<u32>;
+#[doc = "Field `DATE` writer - Manual Encryption block version information."]
+pub type DATE_W<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>;
+impl R {
+    #[doc = "Bits 0:29 - Manual Encryption block version information."]
+    #[inline(always)]
+    pub fn date(&self) -> DATE_R {
+        DATE_R::new(self.bits & 0x3fff_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DATE").field("date", &self.date()).finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:29 - Manual Encryption block version information."]
+    #[inline(always)]
+    pub fn date(&mut self) -> DATE_W<DATE_SPEC> {
+        DATE_W::new(self, 0)
+    }
+}
+#[doc = "XTS-AES version control register\n\nYou can [`read`](crate::Reg::read) this register and get [`date::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`date::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DATE_SPEC;
+impl crate::RegisterSpec for DATE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`date::R`](R) reader structure"]
+impl crate::Readable for DATE_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`date::W`](W) writer structure"]
+impl crate::Writable for DATE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DATE to value 0x2020_0111"]
+impl crate::Resettable for DATE_SPEC {
+    const RESET_VALUE: u32 = 0x2020_0111;
+}

vendor/esp32s3/src/xts_aes/destination.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `DESTINATION` reader"]
+pub type R = crate::R<DESTINATION_SPEC>;
+#[doc = "Register `DESTINATION` writer"]
+pub type W = crate::W<DESTINATION_SPEC>;
+#[doc = "Field `DESTINATION` reader - Configures the type of the external memory. Currently, it must be set to 0, as the Manual Encryption block only supports flash encryption. Errors may occurs if users write 1. 0:flash. 1: external RAM."]
+pub type DESTINATION_R = crate::BitReader;
+#[doc = "Field `DESTINATION` writer - Configures the type of the external memory. Currently, it must be set to 0, as the Manual Encryption block only supports flash encryption. Errors may occurs if users write 1. 0:flash. 1: external RAM."]
+pub type DESTINATION_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Configures the type of the external memory. Currently, it must be set to 0, as the Manual Encryption block only supports flash encryption. Errors may occurs if users write 1. 0:flash. 1: external RAM."]
+    #[inline(always)]
+    pub fn destination(&self) -> DESTINATION_R {
+        DESTINATION_R::new((self.bits & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("DESTINATION")
+            .field("destination", &self.destination())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Configures the type of the external memory. Currently, it must be set to 0, as the Manual Encryption block only supports flash encryption. Errors may occurs if users write 1. 0:flash. 1: external RAM."]
+    #[inline(always)]
+    pub fn destination(&mut self) -> DESTINATION_W<DESTINATION_SPEC> {
+        DESTINATION_W::new(self, 0)
+    }
+}
+#[doc = "XTS-AES destination register\n\nYou can [`read`](crate::Reg::read) this register and get [`destination::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`destination::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DESTINATION_SPEC;
+impl crate::RegisterSpec for DESTINATION_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`destination::R`](R) reader structure"]
+impl crate::Readable for DESTINATION_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`destination::W`](W) writer structure"]
+impl crate::Writable for DESTINATION_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DESTINATION to value 0"]
+impl crate::Resettable for DESTINATION_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/xts_aes/destroy.rs

@@ -0,0 +1,32 @@
+#[doc = "Register `DESTROY` writer"]
+pub type W = crate::W<DESTROY_SPEC>;
+#[doc = "Field `DESTROY` writer - Write 1 to destroy encrypted result."]
+pub type DESTROY_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for crate::generic::Reg<DESTROY_SPEC> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "(not readable)")
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Write 1 to destroy encrypted result."]
+    #[inline(always)]
+    pub fn destroy(&mut self) -> DESTROY_W<DESTROY_SPEC> {
+        DESTROY_W::new(self, 0)
+    }
+}
+#[doc = "XTS-AES destroy control register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`destroy::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DESTROY_SPEC;
+impl crate::RegisterSpec for DESTROY_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [`destroy::W`](W) writer structure"]
+impl crate::Writable for DESTROY_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DESTROY to value 0"]
+impl crate::Resettable for DESTROY_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/xts_aes/linesize.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `LINESIZE` reader"]
+pub type R = crate::R<LINESIZE_SPEC>;
+#[doc = "Register `LINESIZE` writer"]
+pub type W = crate::W<LINESIZE_SPEC>;
+#[doc = "Field `LINESIZE` reader - Configures the data size of one encryption."]
+pub type LINESIZE_R = crate::BitReader;
+#[doc = "Field `LINESIZE` writer - Configures the data size of one encryption."]
+pub type LINESIZE_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Configures the data size of one encryption."]
+    #[inline(always)]
+    pub fn linesize(&self) -> LINESIZE_R {
+        LINESIZE_R::new((self.bits & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("LINESIZE")
+            .field("linesize", &self.linesize())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Configures the data size of one encryption."]
+    #[inline(always)]
+    pub fn linesize(&mut self) -> LINESIZE_W<LINESIZE_SPEC> {
+        LINESIZE_W::new(self, 0)
+    }
+}
+#[doc = "XTS-AES line-size register\n\nYou can [`read`](crate::Reg::read) this register and get [`linesize::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`linesize::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct LINESIZE_SPEC;
+impl crate::RegisterSpec for LINESIZE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`linesize::R`](R) reader structure"]
+impl crate::Readable for LINESIZE_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`linesize::W`](W) writer structure"]
+impl crate::Writable for LINESIZE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets LINESIZE to value 0"]
+impl crate::Resettable for LINESIZE_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/xts_aes/physical_address.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `PHYSICAL_ADDRESS` reader"]
+pub type R = crate::R<PHYSICAL_ADDRESS_SPEC>;
+#[doc = "Register `PHYSICAL_ADDRESS` writer"]
+pub type W = crate::W<PHYSICAL_ADDRESS_SPEC>;
+#[doc = "Field `PHYSICAL_ADDRESS` reader - Those bits stores the physical address. If linesize is 16-byte, the physical address should be aligned of 16 bytes. If linesize is 32-byte, the physical address should be aligned of 32 bytes. If linesize is 64-byte, the physical address should be aligned of 64 bytes."]
+pub type PHYSICAL_ADDRESS_R = crate::FieldReader<u32>;
+#[doc = "Field `PHYSICAL_ADDRESS` writer - Those bits stores the physical address. If linesize is 16-byte, the physical address should be aligned of 16 bytes. If linesize is 32-byte, the physical address should be aligned of 32 bytes. If linesize is 64-byte, the physical address should be aligned of 64 bytes."]
+pub type PHYSICAL_ADDRESS_W<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>;
+impl R {
+    #[doc = "Bits 0:29 - Those bits stores the physical address. If linesize is 16-byte, the physical address should be aligned of 16 bytes. If linesize is 32-byte, the physical address should be aligned of 32 bytes. If linesize is 64-byte, the physical address should be aligned of 64 bytes."]
+    #[inline(always)]
+    pub fn physical_address(&self) -> PHYSICAL_ADDRESS_R {
+        PHYSICAL_ADDRESS_R::new(self.bits & 0x3fff_ffff)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("PHYSICAL_ADDRESS")
+            .field("physical_address", &self.physical_address())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:29 - Those bits stores the physical address. If linesize is 16-byte, the physical address should be aligned of 16 bytes. If linesize is 32-byte, the physical address should be aligned of 32 bytes. If linesize is 64-byte, the physical address should be aligned of 64 bytes."]
+    #[inline(always)]
+    pub fn physical_address(&mut self) -> PHYSICAL_ADDRESS_W<PHYSICAL_ADDRESS_SPEC> {
+        PHYSICAL_ADDRESS_W::new(self, 0)
+    }
+}
+#[doc = "physical address\n\nYou can [`read`](crate::Reg::read) this register and get [`physical_address::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`physical_address::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct PHYSICAL_ADDRESS_SPEC;
+impl crate::RegisterSpec for PHYSICAL_ADDRESS_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`physical_address::R`](R) reader structure"]
+impl crate::Readable for PHYSICAL_ADDRESS_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`physical_address::W`](W) writer structure"]
+impl crate::Writable for PHYSICAL_ADDRESS_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets PHYSICAL_ADDRESS to value 0"]
+impl crate::Resettable for PHYSICAL_ADDRESS_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/xts_aes/plain_.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `PLAIN_%s` reader"]
+pub type R = crate::R<PLAIN__SPEC>;
+#[doc = "Register `PLAIN_%s` writer"]
+pub type W = crate::W<PLAIN__SPEC>;
+#[doc = "Field `PLAIN` reader - Stores the nth 32-bit piece of plaintext."]
+pub type PLAIN_R = crate::FieldReader<u32>;
+#[doc = "Field `PLAIN` writer - Stores the nth 32-bit piece of plaintext."]
+pub type PLAIN_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - Stores the nth 32-bit piece of plaintext."]
+    #[inline(always)]
+    pub fn plain(&self) -> PLAIN_R {
+        PLAIN_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("PLAIN_")
+            .field("plain", &self.plain())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Stores the nth 32-bit piece of plaintext."]
+    #[inline(always)]
+    pub fn plain(&mut self) -> PLAIN_W<PLAIN__SPEC> {
+        PLAIN_W::new(self, 0)
+    }
+}
+#[doc = "Plaintext register %s\n\nYou can [`read`](crate::Reg::read) this register and get [`plain_::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`plain_::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct PLAIN__SPEC;
+impl crate::RegisterSpec for PLAIN__SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`plain_::R`](R) reader structure"]
+impl crate::Readable for PLAIN__SPEC {}
+#[doc = "`write(|w| ..)` method takes [`plain_::W`](W) writer structure"]
+impl crate::Writable for PLAIN__SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets PLAIN_%s to value 0"]
+impl crate::Resettable for PLAIN__SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/xts_aes/release.rs

@@ -0,0 +1,32 @@
+#[doc = "Register `RELEASE` writer"]
+pub type W = crate::W<RELEASE_SPEC>;
+#[doc = "Field `RELEASE` writer - Write 1 to grant SPI1 access to encrypted result."]
+pub type RELEASE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for crate::generic::Reg<RELEASE_SPEC> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "(not readable)")
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Write 1 to grant SPI1 access to encrypted result."]
+    #[inline(always)]
+    pub fn release(&mut self) -> RELEASE_W<RELEASE_SPEC> {
+        RELEASE_W::new(self, 0)
+    }
+}
+#[doc = "XTS-AES release control register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`release::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct RELEASE_SPEC;
+impl crate::RegisterSpec for RELEASE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [`release::W`](W) writer structure"]
+impl crate::Writable for RELEASE_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets RELEASE to value 0"]
+impl crate::Resettable for RELEASE_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/xts_aes/state.rs

@@ -0,0 +1,30 @@
+#[doc = "Register `STATE` reader"]
+pub type R = crate::R<STATE_SPEC>;
+#[doc = "Field `STATE` reader - Those bits indicates the status of the Manual Encryption block. 0X0 (XTS_AES_IDLE): idle. 0X1 (XTS_AES_BUSY): busy with encryption. 0X2 (XTS_AES_DONE): encryption is completed, but the encrypted result is not accessible to SPI. 0X3 (XTS_AES_AVAILABLE) encrypted result is accessible and available to SPI."]
+pub type STATE_R = crate::FieldReader;
+impl R {
+    #[doc = "Bits 0:1 - Those bits indicates the status of the Manual Encryption block. 0X0 (XTS_AES_IDLE): idle. 0X1 (XTS_AES_BUSY): busy with encryption. 0X2 (XTS_AES_DONE): encryption is completed, but the encrypted result is not accessible to SPI. 0X3 (XTS_AES_AVAILABLE) encrypted result is accessible and available to SPI."]
+    #[inline(always)]
+    pub fn state(&self) -> STATE_R {
+        STATE_R::new((self.bits & 3) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("STATE")
+            .field("state", &self.state())
+            .finish()
+    }
+}
+#[doc = "XTS-AES status register\n\nYou can [`read`](crate::Reg::read) this register and get [`state::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct STATE_SPEC;
+impl crate::RegisterSpec for STATE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`state::R`](R) reader structure"]
+impl crate::Readable for STATE_SPEC {}
+#[doc = "`reset()` method sets STATE to value 0"]
+impl crate::Resettable for STATE_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

vendor/esp32s3/src/xts_aes/trigger.rs

@@ -0,0 +1,32 @@
+#[doc = "Register `TRIGGER` writer"]
+pub type W = crate::W<TRIGGER_SPEC>;
+#[doc = "Field `TRIGGER` writer - Write 1 to activate manual encryption."]
+pub type TRIGGER_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for crate::generic::Reg<TRIGGER_SPEC> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "(not readable)")
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Write 1 to activate manual encryption."]
+    #[inline(always)]
+    pub fn trigger(&mut self) -> TRIGGER_W<TRIGGER_SPEC> {
+        TRIGGER_W::new(self, 0)
+    }
+}
+#[doc = "XTS-AES trigger register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trigger::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct TRIGGER_SPEC;
+impl crate::RegisterSpec for TRIGGER_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [`trigger::W`](W) writer structure"]
+impl crate::Writable for TRIGGER_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets TRIGGER to value 0"]
+impl crate::Resettable for TRIGGER_SPEC {
+    const RESET_VALUE: u32 = 0;
+}