feat: add display UI with splash screen, dashboard, and RSSI sparkline

Implement full SSD1306 OLED display support:
- Splash screen on boot (1.5s) with project name, version, board
- Dashboard showing radio state, config, counters, RSSI/SNR
- RSSI history sparkline (64-sample ring buffer, 2px-wide bars)
- DisplayOn/DisplayOff host commands routed via dedicated channel
- Pure render functions against generic DrawTarget (no hardware coupling)
- Display on/off control bypasses radio task entirely

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>

vendor/nrf51-pac/src/aar.rs

@@ -0,0 +1,95 @@
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00 - Start resolving addresses based on IRKs specified in the IRK data structure."]
+    pub tasks_start: TASKS_START,
+    _reserved1: [u8; 0x04],
+    #[doc = "0x08 - Stop resolving addresses."]
+    pub tasks_stop: TASKS_STOP,
+    _reserved2: [u8; 0xf4],
+    #[doc = "0x100 - Address resolution procedure completed."]
+    pub events_end: EVENTS_END,
+    #[doc = "0x104 - Address resolved."]
+    pub events_resolved: EVENTS_RESOLVED,
+    #[doc = "0x108 - Address not resolved."]
+    pub events_notresolved: EVENTS_NOTRESOLVED,
+    _reserved5: [u8; 0x01f8],
+    #[doc = "0x304 - Interrupt enable set register."]
+    pub intenset: INTENSET,
+    #[doc = "0x308 - Interrupt enable clear register."]
+    pub intenclr: INTENCLR,
+    _reserved7: [u8; 0xf4],
+    #[doc = "0x400 - Resolution status."]
+    pub status: STATUS,
+    _reserved8: [u8; 0xfc],
+    #[doc = "0x500 - Enable AAR."]
+    pub enable: ENABLE,
+    #[doc = "0x504 - Number of Identity root Keys in the IRK data structure."]
+    pub nirk: NIRK,
+    #[doc = "0x508 - Pointer to the IRK data structure."]
+    pub irkptr: IRKPTR,
+    _reserved11: [u8; 0x04],
+    #[doc = "0x510 - Pointer to the resolvable address (6 bytes)."]
+    pub addrptr: ADDRPTR,
+    #[doc = "0x514 - Pointer to a scratch data area used for temporary storage during resolution. A minimum of 3 bytes must be reserved."]
+    pub scratchptr: SCRATCHPTR,
+    _reserved13: [u8; 0x0ae4],
+    #[doc = "0xffc - Peripheral power control."]
+    pub power: POWER,
+}
+#[doc = "TASKS_START (w) register accessor: an alias for `Reg<TASKS_START_SPEC>`"]
+pub type TASKS_START = crate::Reg<tasks_start::TASKS_START_SPEC>;
+#[doc = "Start resolving addresses based on IRKs specified in the IRK data structure."]
+pub mod tasks_start;
+#[doc = "TASKS_STOP (w) register accessor: an alias for `Reg<TASKS_STOP_SPEC>`"]
+pub type TASKS_STOP = crate::Reg<tasks_stop::TASKS_STOP_SPEC>;
+#[doc = "Stop resolving addresses."]
+pub mod tasks_stop;
+#[doc = "EVENTS_END (rw) register accessor: an alias for `Reg<EVENTS_END_SPEC>`"]
+pub type EVENTS_END = crate::Reg<events_end::EVENTS_END_SPEC>;
+#[doc = "Address resolution procedure completed."]
+pub mod events_end;
+#[doc = "EVENTS_RESOLVED (rw) register accessor: an alias for `Reg<EVENTS_RESOLVED_SPEC>`"]
+pub type EVENTS_RESOLVED = crate::Reg<events_resolved::EVENTS_RESOLVED_SPEC>;
+#[doc = "Address resolved."]
+pub mod events_resolved;
+#[doc = "EVENTS_NOTRESOLVED (rw) register accessor: an alias for `Reg<EVENTS_NOTRESOLVED_SPEC>`"]
+pub type EVENTS_NOTRESOLVED = crate::Reg<events_notresolved::EVENTS_NOTRESOLVED_SPEC>;
+#[doc = "Address not resolved."]
+pub mod events_notresolved;
+#[doc = "INTENSET (rw) register accessor: an alias for `Reg<INTENSET_SPEC>`"]
+pub type INTENSET = crate::Reg<intenset::INTENSET_SPEC>;
+#[doc = "Interrupt enable set register."]
+pub mod intenset;
+#[doc = "INTENCLR (rw) register accessor: an alias for `Reg<INTENCLR_SPEC>`"]
+pub type INTENCLR = crate::Reg<intenclr::INTENCLR_SPEC>;
+#[doc = "Interrupt enable clear register."]
+pub mod intenclr;
+#[doc = "STATUS (r) register accessor: an alias for `Reg<STATUS_SPEC>`"]
+pub type STATUS = crate::Reg<status::STATUS_SPEC>;
+#[doc = "Resolution status."]
+pub mod status;
+#[doc = "ENABLE (rw) register accessor: an alias for `Reg<ENABLE_SPEC>`"]
+pub type ENABLE = crate::Reg<enable::ENABLE_SPEC>;
+#[doc = "Enable AAR."]
+pub mod enable;
+#[doc = "NIRK (rw) register accessor: an alias for `Reg<NIRK_SPEC>`"]
+pub type NIRK = crate::Reg<nirk::NIRK_SPEC>;
+#[doc = "Number of Identity root Keys in the IRK data structure."]
+pub mod nirk;
+#[doc = "IRKPTR (rw) register accessor: an alias for `Reg<IRKPTR_SPEC>`"]
+pub type IRKPTR = crate::Reg<irkptr::IRKPTR_SPEC>;
+#[doc = "Pointer to the IRK data structure."]
+pub mod irkptr;
+#[doc = "ADDRPTR (rw) register accessor: an alias for `Reg<ADDRPTR_SPEC>`"]
+pub type ADDRPTR = crate::Reg<addrptr::ADDRPTR_SPEC>;
+#[doc = "Pointer to the resolvable address (6 bytes)."]
+pub mod addrptr;
+#[doc = "SCRATCHPTR (rw) register accessor: an alias for `Reg<SCRATCHPTR_SPEC>`"]
+pub type SCRATCHPTR = crate::Reg<scratchptr::SCRATCHPTR_SPEC>;
+#[doc = "Pointer to a scratch data area used for temporary storage during resolution. A minimum of 3 bytes must be reserved."]
+pub mod scratchptr;
+#[doc = "POWER (rw) register accessor: an alias for `Reg<POWER_SPEC>`"]
+pub type POWER = crate::Reg<power::POWER_SPEC>;
+#[doc = "Peripheral power control."]
+pub mod power;

vendor/nrf51-pac/src/aar/addrptr.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `ADDRPTR` reader"]
+pub struct R(crate::R<ADDRPTR_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<ADDRPTR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<ADDRPTR_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<ADDRPTR_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `ADDRPTR` writer"]
+pub struct W(crate::W<ADDRPTR_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<ADDRPTR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<ADDRPTR_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<ADDRPTR_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Pointer to the resolvable address (6 bytes).\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addrptr](index.html) module"]
+pub struct ADDRPTR_SPEC;
+impl crate::RegisterSpec for ADDRPTR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [addrptr::R](R) reader structure"]
+impl crate::Readable for ADDRPTR_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [addrptr::W](W) writer structure"]
+impl crate::Writable for ADDRPTR_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets ADDRPTR to value 0"]
+impl crate::Resettable for ADDRPTR_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/aar/enable.rs

@@ -0,0 +1,128 @@
+#[doc = "Register `ENABLE` reader"]
+pub struct R(crate::R<ENABLE_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<ENABLE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<ENABLE_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<ENABLE_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `ENABLE` writer"]
+pub struct W(crate::W<ENABLE_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<ENABLE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<ENABLE_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<ENABLE_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `ENABLE` reader - Enable AAR."]
+pub type ENABLE_R = crate::FieldReader<u8, ENABLE_A>;
+#[doc = "Enable AAR.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum ENABLE_A {
+    #[doc = "0: Disabled AAR."]
+    DISABLED = 0,
+    #[doc = "3: Enable AAR."]
+    ENABLED = 3,
+}
+impl From<ENABLE_A> for u8 {
+    #[inline(always)]
+    fn from(variant: ENABLE_A) -> Self {
+        variant as _
+    }
+}
+impl ENABLE_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<ENABLE_A> {
+        match self.bits {
+            0 => Some(ENABLE_A::DISABLED),
+            3 => Some(ENABLE_A::ENABLED),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == ENABLE_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == ENABLE_A::ENABLED
+    }
+}
+#[doc = "Field `ENABLE` writer - Enable AAR."]
+pub type ENABLE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ENABLE_SPEC, u8, ENABLE_A, 2, O>;
+impl<'a, const O: u8> ENABLE_W<'a, O> {
+    #[doc = "Disabled AAR."]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(ENABLE_A::DISABLED)
+    }
+    #[doc = "Enable AAR."]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(ENABLE_A::ENABLED)
+    }
+}
+impl R {
+    #[doc = "Bits 0:1 - Enable AAR."]
+    #[inline(always)]
+    pub fn enable(&self) -> ENABLE_R {
+        ENABLE_R::new((self.bits & 3) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:1 - Enable AAR."]
+    #[inline(always)]
+    pub fn enable(&mut self) -> ENABLE_W<0> {
+        ENABLE_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Enable AAR.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [enable](index.html) module"]
+pub struct ENABLE_SPEC;
+impl crate::RegisterSpec for ENABLE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [enable::R](R) reader structure"]
+impl crate::Readable for ENABLE_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [enable::W](W) writer structure"]
+impl crate::Writable for ENABLE_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets ENABLE to value 0"]
+impl crate::Resettable for ENABLE_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/aar/events_end.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `EVENTS_END` reader"]
+pub struct R(crate::R<EVENTS_END_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<EVENTS_END_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<EVENTS_END_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<EVENTS_END_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `EVENTS_END` writer"]
+pub struct W(crate::W<EVENTS_END_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<EVENTS_END_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<EVENTS_END_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<EVENTS_END_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Address resolution procedure completed.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_end](index.html) module"]
+pub struct EVENTS_END_SPEC;
+impl crate::RegisterSpec for EVENTS_END_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [events_end::R](R) reader structure"]
+impl crate::Readable for EVENTS_END_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [events_end::W](W) writer structure"]
+impl crate::Writable for EVENTS_END_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets EVENTS_END to value 0"]
+impl crate::Resettable for EVENTS_END_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/aar/events_notresolved.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `EVENTS_NOTRESOLVED` reader"]
+pub struct R(crate::R<EVENTS_NOTRESOLVED_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<EVENTS_NOTRESOLVED_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<EVENTS_NOTRESOLVED_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<EVENTS_NOTRESOLVED_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `EVENTS_NOTRESOLVED` writer"]
+pub struct W(crate::W<EVENTS_NOTRESOLVED_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<EVENTS_NOTRESOLVED_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<EVENTS_NOTRESOLVED_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<EVENTS_NOTRESOLVED_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Address not resolved.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_notresolved](index.html) module"]
+pub struct EVENTS_NOTRESOLVED_SPEC;
+impl crate::RegisterSpec for EVENTS_NOTRESOLVED_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [events_notresolved::R](R) reader structure"]
+impl crate::Readable for EVENTS_NOTRESOLVED_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [events_notresolved::W](W) writer structure"]
+impl crate::Writable for EVENTS_NOTRESOLVED_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets EVENTS_NOTRESOLVED to value 0"]
+impl crate::Resettable for EVENTS_NOTRESOLVED_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/aar/events_resolved.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `EVENTS_RESOLVED` reader"]
+pub struct R(crate::R<EVENTS_RESOLVED_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<EVENTS_RESOLVED_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<EVENTS_RESOLVED_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<EVENTS_RESOLVED_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `EVENTS_RESOLVED` writer"]
+pub struct W(crate::W<EVENTS_RESOLVED_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<EVENTS_RESOLVED_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<EVENTS_RESOLVED_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<EVENTS_RESOLVED_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Address resolved.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_resolved](index.html) module"]
+pub struct EVENTS_RESOLVED_SPEC;
+impl crate::RegisterSpec for EVENTS_RESOLVED_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [events_resolved::R](R) reader structure"]
+impl crate::Readable for EVENTS_RESOLVED_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [events_resolved::W](W) writer structure"]
+impl crate::Writable for EVENTS_RESOLVED_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets EVENTS_RESOLVED to value 0"]
+impl crate::Resettable for EVENTS_RESOLVED_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/aar/intenclr.rs

@@ -0,0 +1,268 @@
+#[doc = "Register `INTENCLR` reader"]
+pub struct R(crate::R<INTENCLR_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<INTENCLR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<INTENCLR_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<INTENCLR_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `INTENCLR` writer"]
+pub struct W(crate::W<INTENCLR_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<INTENCLR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<INTENCLR_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<INTENCLR_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `END` reader - Disable interrupt on ENDKSGEN event."]
+pub type END_R = crate::BitReader<END_A>;
+#[doc = "Disable interrupt on ENDKSGEN event.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum END_A {
+    #[doc = "0: Interrupt disabled."]
+    DISABLED = 0,
+    #[doc = "1: Interrupt enabled."]
+    ENABLED = 1,
+}
+impl From<END_A> for bool {
+    #[inline(always)]
+    fn from(variant: END_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl END_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> END_A {
+        match self.bits {
+            false => END_A::DISABLED,
+            true => END_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == END_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == END_A::ENABLED
+    }
+}
+#[doc = "Disable interrupt on ENDKSGEN event.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum END_AW {
+    #[doc = "1: Disable interrupt on write."]
+    CLEAR = 1,
+}
+impl From<END_AW> for bool {
+    #[inline(always)]
+    fn from(variant: END_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `END` writer - Disable interrupt on ENDKSGEN event."]
+pub type END_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, END_AW, O>;
+impl<'a, const O: u8> END_W<'a, O> {
+    #[doc = "Disable interrupt on write."]
+    #[inline(always)]
+    pub fn clear(self) -> &'a mut W {
+        self.variant(END_AW::CLEAR)
+    }
+}
+#[doc = "Field `RESOLVED` reader - Disable interrupt on RESOLVED event."]
+pub type RESOLVED_R = crate::BitReader<RESOLVED_A>;
+#[doc = "Disable interrupt on RESOLVED event.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum RESOLVED_A {
+    #[doc = "0: Interrupt disabled."]
+    DISABLED = 0,
+    #[doc = "1: Interrupt enabled."]
+    ENABLED = 1,
+}
+impl From<RESOLVED_A> for bool {
+    #[inline(always)]
+    fn from(variant: RESOLVED_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl RESOLVED_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> RESOLVED_A {
+        match self.bits {
+            false => RESOLVED_A::DISABLED,
+            true => RESOLVED_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == RESOLVED_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == RESOLVED_A::ENABLED
+    }
+}
+#[doc = "Disable interrupt on RESOLVED event.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum RESOLVED_AW {
+    #[doc = "1: Disable interrupt on write."]
+    CLEAR = 1,
+}
+impl From<RESOLVED_AW> for bool {
+    #[inline(always)]
+    fn from(variant: RESOLVED_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `RESOLVED` writer - Disable interrupt on RESOLVED event."]
+pub type RESOLVED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, RESOLVED_AW, O>;
+impl<'a, const O: u8> RESOLVED_W<'a, O> {
+    #[doc = "Disable interrupt on write."]
+    #[inline(always)]
+    pub fn clear(self) -> &'a mut W {
+        self.variant(RESOLVED_AW::CLEAR)
+    }
+}
+#[doc = "Field `NOTRESOLVED` reader - Disable interrupt on NOTRESOLVED event."]
+pub type NOTRESOLVED_R = crate::BitReader<NOTRESOLVED_A>;
+#[doc = "Disable interrupt on NOTRESOLVED event.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum NOTRESOLVED_A {
+    #[doc = "0: Interrupt disabled."]
+    DISABLED = 0,
+    #[doc = "1: Interrupt enabled."]
+    ENABLED = 1,
+}
+impl From<NOTRESOLVED_A> for bool {
+    #[inline(always)]
+    fn from(variant: NOTRESOLVED_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl NOTRESOLVED_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> NOTRESOLVED_A {
+        match self.bits {
+            false => NOTRESOLVED_A::DISABLED,
+            true => NOTRESOLVED_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == NOTRESOLVED_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == NOTRESOLVED_A::ENABLED
+    }
+}
+#[doc = "Disable interrupt on NOTRESOLVED event.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum NOTRESOLVED_AW {
+    #[doc = "1: Disable interrupt on write."]
+    CLEAR = 1,
+}
+impl From<NOTRESOLVED_AW> for bool {
+    #[inline(always)]
+    fn from(variant: NOTRESOLVED_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `NOTRESOLVED` writer - Disable interrupt on NOTRESOLVED event."]
+pub type NOTRESOLVED_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, INTENCLR_SPEC, NOTRESOLVED_AW, O>;
+impl<'a, const O: u8> NOTRESOLVED_W<'a, O> {
+    #[doc = "Disable interrupt on write."]
+    #[inline(always)]
+    pub fn clear(self) -> &'a mut W {
+        self.variant(NOTRESOLVED_AW::CLEAR)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Disable interrupt on ENDKSGEN event."]
+    #[inline(always)]
+    pub fn end(&self) -> END_R {
+        END_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Disable interrupt on RESOLVED event."]
+    #[inline(always)]
+    pub fn resolved(&self) -> RESOLVED_R {
+        RESOLVED_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Disable interrupt on NOTRESOLVED event."]
+    #[inline(always)]
+    pub fn notresolved(&self) -> NOTRESOLVED_R {
+        NOTRESOLVED_R::new(((self.bits >> 2) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Disable interrupt on ENDKSGEN event."]
+    #[inline(always)]
+    pub fn end(&mut self) -> END_W<0> {
+        END_W::new(self)
+    }
+    #[doc = "Bit 1 - Disable interrupt on RESOLVED event."]
+    #[inline(always)]
+    pub fn resolved(&mut self) -> RESOLVED_W<1> {
+        RESOLVED_W::new(self)
+    }
+    #[doc = "Bit 2 - Disable interrupt on NOTRESOLVED event."]
+    #[inline(always)]
+    pub fn notresolved(&mut self) -> NOTRESOLVED_W<2> {
+        NOTRESOLVED_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Interrupt enable clear register.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"]
+pub struct INTENCLR_SPEC;
+impl crate::RegisterSpec for INTENCLR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [intenclr::R](R) reader structure"]
+impl crate::Readable for INTENCLR_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"]
+impl crate::Writable for INTENCLR_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets INTENCLR to value 0"]
+impl crate::Resettable for INTENCLR_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/aar/intenset.rs

@@ -0,0 +1,268 @@
+#[doc = "Register `INTENSET` reader"]
+pub struct R(crate::R<INTENSET_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<INTENSET_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<INTENSET_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<INTENSET_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `INTENSET` writer"]
+pub struct W(crate::W<INTENSET_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<INTENSET_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<INTENSET_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<INTENSET_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `END` reader - Enable interrupt on END event."]
+pub type END_R = crate::BitReader<END_A>;
+#[doc = "Enable interrupt on END event.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum END_A {
+    #[doc = "0: Interrupt disabled."]
+    DISABLED = 0,
+    #[doc = "1: Interrupt enabled."]
+    ENABLED = 1,
+}
+impl From<END_A> for bool {
+    #[inline(always)]
+    fn from(variant: END_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl END_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> END_A {
+        match self.bits {
+            false => END_A::DISABLED,
+            true => END_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == END_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == END_A::ENABLED
+    }
+}
+#[doc = "Enable interrupt on END event.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum END_AW {
+    #[doc = "1: Enable interrupt on write."]
+    SET = 1,
+}
+impl From<END_AW> for bool {
+    #[inline(always)]
+    fn from(variant: END_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `END` writer - Enable interrupt on END event."]
+pub type END_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, END_AW, O>;
+impl<'a, const O: u8> END_W<'a, O> {
+    #[doc = "Enable interrupt on write."]
+    #[inline(always)]
+    pub fn set(self) -> &'a mut W {
+        self.variant(END_AW::SET)
+    }
+}
+#[doc = "Field `RESOLVED` reader - Enable interrupt on RESOLVED event."]
+pub type RESOLVED_R = crate::BitReader<RESOLVED_A>;
+#[doc = "Enable interrupt on RESOLVED event.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum RESOLVED_A {
+    #[doc = "0: Interrupt disabled."]
+    DISABLED = 0,
+    #[doc = "1: Interrupt enabled."]
+    ENABLED = 1,
+}
+impl From<RESOLVED_A> for bool {
+    #[inline(always)]
+    fn from(variant: RESOLVED_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl RESOLVED_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> RESOLVED_A {
+        match self.bits {
+            false => RESOLVED_A::DISABLED,
+            true => RESOLVED_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == RESOLVED_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == RESOLVED_A::ENABLED
+    }
+}
+#[doc = "Enable interrupt on RESOLVED event.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum RESOLVED_AW {
+    #[doc = "1: Enable interrupt on write."]
+    SET = 1,
+}
+impl From<RESOLVED_AW> for bool {
+    #[inline(always)]
+    fn from(variant: RESOLVED_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `RESOLVED` writer - Enable interrupt on RESOLVED event."]
+pub type RESOLVED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, RESOLVED_AW, O>;
+impl<'a, const O: u8> RESOLVED_W<'a, O> {
+    #[doc = "Enable interrupt on write."]
+    #[inline(always)]
+    pub fn set(self) -> &'a mut W {
+        self.variant(RESOLVED_AW::SET)
+    }
+}
+#[doc = "Field `NOTRESOLVED` reader - Enable interrupt on NOTRESOLVED event."]
+pub type NOTRESOLVED_R = crate::BitReader<NOTRESOLVED_A>;
+#[doc = "Enable interrupt on NOTRESOLVED event.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum NOTRESOLVED_A {
+    #[doc = "0: Interrupt disabled."]
+    DISABLED = 0,
+    #[doc = "1: Interrupt enabled."]
+    ENABLED = 1,
+}
+impl From<NOTRESOLVED_A> for bool {
+    #[inline(always)]
+    fn from(variant: NOTRESOLVED_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl NOTRESOLVED_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> NOTRESOLVED_A {
+        match self.bits {
+            false => NOTRESOLVED_A::DISABLED,
+            true => NOTRESOLVED_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == NOTRESOLVED_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == NOTRESOLVED_A::ENABLED
+    }
+}
+#[doc = "Enable interrupt on NOTRESOLVED event.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum NOTRESOLVED_AW {
+    #[doc = "1: Enable interrupt on write."]
+    SET = 1,
+}
+impl From<NOTRESOLVED_AW> for bool {
+    #[inline(always)]
+    fn from(variant: NOTRESOLVED_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `NOTRESOLVED` writer - Enable interrupt on NOTRESOLVED event."]
+pub type NOTRESOLVED_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, INTENSET_SPEC, NOTRESOLVED_AW, O>;
+impl<'a, const O: u8> NOTRESOLVED_W<'a, O> {
+    #[doc = "Enable interrupt on write."]
+    #[inline(always)]
+    pub fn set(self) -> &'a mut W {
+        self.variant(NOTRESOLVED_AW::SET)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Enable interrupt on END event."]
+    #[inline(always)]
+    pub fn end(&self) -> END_R {
+        END_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Enable interrupt on RESOLVED event."]
+    #[inline(always)]
+    pub fn resolved(&self) -> RESOLVED_R {
+        RESOLVED_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Enable interrupt on NOTRESOLVED event."]
+    #[inline(always)]
+    pub fn notresolved(&self) -> NOTRESOLVED_R {
+        NOTRESOLVED_R::new(((self.bits >> 2) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Enable interrupt on END event."]
+    #[inline(always)]
+    pub fn end(&mut self) -> END_W<0> {
+        END_W::new(self)
+    }
+    #[doc = "Bit 1 - Enable interrupt on RESOLVED event."]
+    #[inline(always)]
+    pub fn resolved(&mut self) -> RESOLVED_W<1> {
+        RESOLVED_W::new(self)
+    }
+    #[doc = "Bit 2 - Enable interrupt on NOTRESOLVED event."]
+    #[inline(always)]
+    pub fn notresolved(&mut self) -> NOTRESOLVED_W<2> {
+        NOTRESOLVED_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Interrupt enable set register.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"]
+pub struct INTENSET_SPEC;
+impl crate::RegisterSpec for INTENSET_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [intenset::R](R) reader structure"]
+impl crate::Readable for INTENSET_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"]
+impl crate::Writable for INTENSET_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets INTENSET to value 0"]
+impl crate::Resettable for INTENSET_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/aar/irkptr.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `IRKPTR` reader"]
+pub struct R(crate::R<IRKPTR_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<IRKPTR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<IRKPTR_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<IRKPTR_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `IRKPTR` writer"]
+pub struct W(crate::W<IRKPTR_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<IRKPTR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<IRKPTR_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<IRKPTR_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Pointer to the IRK data structure.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irkptr](index.html) module"]
+pub struct IRKPTR_SPEC;
+impl crate::RegisterSpec for IRKPTR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [irkptr::R](R) reader structure"]
+impl crate::Readable for IRKPTR_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [irkptr::W](W) writer structure"]
+impl crate::Writable for IRKPTR_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets IRKPTR to value 0"]
+impl crate::Resettable for IRKPTR_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/aar/nirk.rs

@@ -0,0 +1,80 @@
+#[doc = "Register `NIRK` reader"]
+pub struct R(crate::R<NIRK_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<NIRK_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<NIRK_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<NIRK_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `NIRK` writer"]
+pub struct W(crate::W<NIRK_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<NIRK_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<NIRK_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<NIRK_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `NIRK` reader - Number of Identity root Keys in the IRK data structure."]
+pub type NIRK_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `NIRK` writer - Number of Identity root Keys in the IRK data structure."]
+pub type NIRK_W<'a, const O: u8> = crate::FieldWriter<'a, u32, NIRK_SPEC, u8, u8, 5, O>;
+impl R {
+    #[doc = "Bits 0:4 - Number of Identity root Keys in the IRK data structure."]
+    #[inline(always)]
+    pub fn nirk(&self) -> NIRK_R {
+        NIRK_R::new((self.bits & 0x1f) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:4 - Number of Identity root Keys in the IRK data structure."]
+    #[inline(always)]
+    pub fn nirk(&mut self) -> NIRK_W<0> {
+        NIRK_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Number of Identity root Keys in the IRK data structure.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [nirk](index.html) module"]
+pub struct NIRK_SPEC;
+impl crate::RegisterSpec for NIRK_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [nirk::R](R) reader structure"]
+impl crate::Readable for NIRK_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [nirk::W](W) writer structure"]
+impl crate::Writable for NIRK_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets NIRK to value 0x01"]
+impl crate::Resettable for NIRK_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0x01
+    }
+}

vendor/nrf51-pac/src/aar/power.rs

@@ -0,0 +1,126 @@
+#[doc = "Register `POWER` reader"]
+pub struct R(crate::R<POWER_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<POWER_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<POWER_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<POWER_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `POWER` writer"]
+pub struct W(crate::W<POWER_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<POWER_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<POWER_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<POWER_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `POWER` reader - Peripheral power control."]
+pub type POWER_R = crate::BitReader<POWER_A>;
+#[doc = "Peripheral power control.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum POWER_A {
+    #[doc = "0: Module power disabled."]
+    DISABLED = 0,
+    #[doc = "1: Module power enabled."]
+    ENABLED = 1,
+}
+impl From<POWER_A> for bool {
+    #[inline(always)]
+    fn from(variant: POWER_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl POWER_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> POWER_A {
+        match self.bits {
+            false => POWER_A::DISABLED,
+            true => POWER_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == POWER_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == POWER_A::ENABLED
+    }
+}
+#[doc = "Field `POWER` writer - Peripheral power control."]
+pub type POWER_W<'a, const O: u8> = crate::BitWriter<'a, u32, POWER_SPEC, POWER_A, O>;
+impl<'a, const O: u8> POWER_W<'a, O> {
+    #[doc = "Module power disabled."]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(POWER_A::DISABLED)
+    }
+    #[doc = "Module power enabled."]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(POWER_A::ENABLED)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Peripheral power control."]
+    #[inline(always)]
+    pub fn power(&self) -> POWER_R {
+        POWER_R::new((self.bits & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Peripheral power control."]
+    #[inline(always)]
+    pub fn power(&mut self) -> POWER_W<0> {
+        POWER_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Peripheral power control.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [power](index.html) module"]
+pub struct POWER_SPEC;
+impl crate::RegisterSpec for POWER_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [power::R](R) reader structure"]
+impl crate::Readable for POWER_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [power::W](W) writer structure"]
+impl crate::Writable for POWER_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets POWER to value 0"]
+impl crate::Resettable for POWER_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/aar/scratchptr.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `SCRATCHPTR` reader"]
+pub struct R(crate::R<SCRATCHPTR_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<SCRATCHPTR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<SCRATCHPTR_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<SCRATCHPTR_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `SCRATCHPTR` writer"]
+pub struct W(crate::W<SCRATCHPTR_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<SCRATCHPTR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<SCRATCHPTR_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<SCRATCHPTR_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Pointer to a scratch data area used for temporary storage during resolution. A minimum of 3 bytes must be reserved.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scratchptr](index.html) module"]
+pub struct SCRATCHPTR_SPEC;
+impl crate::RegisterSpec for SCRATCHPTR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [scratchptr::R](R) reader structure"]
+impl crate::Readable for SCRATCHPTR_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [scratchptr::W](W) writer structure"]
+impl crate::Writable for SCRATCHPTR_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets SCRATCHPTR to value 0"]
+impl crate::Resettable for SCRATCHPTR_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/aar/status.rs

@@ -0,0 +1,40 @@
+#[doc = "Register `STATUS` reader"]
+pub struct R(crate::R<STATUS_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<STATUS_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<STATUS_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<STATUS_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `STATUS` reader - The IRK used last time an address was resolved."]
+pub type STATUS_R = crate::FieldReader<u8, u8>;
+impl R {
+    #[doc = "Bits 0:3 - The IRK used last time an address was resolved."]
+    #[inline(always)]
+    pub fn status(&self) -> STATUS_R {
+        STATUS_R::new((self.bits & 0x0f) as u8)
+    }
+}
+#[doc = "Resolution status.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"]
+pub struct STATUS_SPEC;
+impl crate::RegisterSpec for STATUS_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [status::R](R) reader structure"]
+impl crate::Readable for STATUS_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets STATUS to value 0"]
+impl crate::Resettable for STATUS_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/aar/tasks_start.rs

@@ -0,0 +1,45 @@
+#[doc = "Register `TASKS_START` writer"]
+pub struct W(crate::W<TASKS_START_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<TASKS_START_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<TASKS_START_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<TASKS_START_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Start resolving addresses based on IRKs specified in the IRK data structure.\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_start](index.html) module"]
+pub struct TASKS_START_SPEC;
+impl crate::RegisterSpec for TASKS_START_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [tasks_start::W](W) writer structure"]
+impl crate::Writable for TASKS_START_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets TASKS_START to value 0"]
+impl crate::Resettable for TASKS_START_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/aar/tasks_stop.rs

@@ -0,0 +1,45 @@
+#[doc = "Register `TASKS_STOP` writer"]
+pub struct W(crate::W<TASKS_STOP_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<TASKS_STOP_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<TASKS_STOP_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<TASKS_STOP_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Stop resolving addresses.\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_stop](index.html) module"]
+pub struct TASKS_STOP_SPEC;
+impl crate::RegisterSpec for TASKS_STOP_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [tasks_stop::W](W) writer structure"]
+impl crate::Writable for TASKS_STOP_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets TASKS_STOP to value 0"]
+impl crate::Resettable for TASKS_STOP_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/adc.rs

@@ -0,0 +1,69 @@
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00 - Start an ADC conversion."]
+    pub tasks_start: TASKS_START,
+    #[doc = "0x04 - Stop ADC."]
+    pub tasks_stop: TASKS_STOP,
+    _reserved2: [u8; 0xf8],
+    #[doc = "0x100 - ADC conversion complete."]
+    pub events_end: EVENTS_END,
+    _reserved3: [u8; 0x0200],
+    #[doc = "0x304 - Interrupt enable set register."]
+    pub intenset: INTENSET,
+    #[doc = "0x308 - Interrupt enable clear register."]
+    pub intenclr: INTENCLR,
+    _reserved5: [u8; 0xf4],
+    #[doc = "0x400 - ADC busy register."]
+    pub busy: BUSY,
+    _reserved6: [u8; 0xfc],
+    #[doc = "0x500 - ADC enable."]
+    pub enable: ENABLE,
+    #[doc = "0x504 - ADC configuration register."]
+    pub config: CONFIG,
+    #[doc = "0x508 - Result of ADC conversion."]
+    pub result: RESULT,
+    _reserved9: [u8; 0x0af0],
+    #[doc = "0xffc - Peripheral power control."]
+    pub power: POWER,
+}
+#[doc = "TASKS_START (w) register accessor: an alias for `Reg<TASKS_START_SPEC>`"]
+pub type TASKS_START = crate::Reg<tasks_start::TASKS_START_SPEC>;
+#[doc = "Start an ADC conversion."]
+pub mod tasks_start;
+#[doc = "TASKS_STOP (w) register accessor: an alias for `Reg<TASKS_STOP_SPEC>`"]
+pub type TASKS_STOP = crate::Reg<tasks_stop::TASKS_STOP_SPEC>;
+#[doc = "Stop ADC."]
+pub mod tasks_stop;
+#[doc = "EVENTS_END (rw) register accessor: an alias for `Reg<EVENTS_END_SPEC>`"]
+pub type EVENTS_END = crate::Reg<events_end::EVENTS_END_SPEC>;
+#[doc = "ADC conversion complete."]
+pub mod events_end;
+#[doc = "INTENSET (rw) register accessor: an alias for `Reg<INTENSET_SPEC>`"]
+pub type INTENSET = crate::Reg<intenset::INTENSET_SPEC>;
+#[doc = "Interrupt enable set register."]
+pub mod intenset;
+#[doc = "INTENCLR (rw) register accessor: an alias for `Reg<INTENCLR_SPEC>`"]
+pub type INTENCLR = crate::Reg<intenclr::INTENCLR_SPEC>;
+#[doc = "Interrupt enable clear register."]
+pub mod intenclr;
+#[doc = "BUSY (r) register accessor: an alias for `Reg<BUSY_SPEC>`"]
+pub type BUSY = crate::Reg<busy::BUSY_SPEC>;
+#[doc = "ADC busy register."]
+pub mod busy;
+#[doc = "ENABLE (rw) register accessor: an alias for `Reg<ENABLE_SPEC>`"]
+pub type ENABLE = crate::Reg<enable::ENABLE_SPEC>;
+#[doc = "ADC enable."]
+pub mod enable;
+#[doc = "CONFIG (rw) register accessor: an alias for `Reg<CONFIG_SPEC>`"]
+pub type CONFIG = crate::Reg<config::CONFIG_SPEC>;
+#[doc = "ADC configuration register."]
+pub mod config;
+#[doc = "RESULT (r) register accessor: an alias for `Reg<RESULT_SPEC>`"]
+pub type RESULT = crate::Reg<result::RESULT_SPEC>;
+#[doc = "Result of ADC conversion."]
+pub mod result;
+#[doc = "POWER (rw) register accessor: an alias for `Reg<POWER_SPEC>`"]
+pub type POWER = crate::Reg<power::POWER_SPEC>;
+#[doc = "Peripheral power control."]
+pub mod power;

vendor/nrf51-pac/src/adc/busy.rs

@@ -0,0 +1,74 @@
+#[doc = "Register `BUSY` reader"]
+pub struct R(crate::R<BUSY_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<BUSY_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<BUSY_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<BUSY_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `BUSY` reader - ADC busy register."]
+pub type BUSY_R = crate::BitReader<BUSY_A>;
+#[doc = "ADC busy register.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum BUSY_A {
+    #[doc = "0: No ongoing ADC conversion is taking place. ADC is ready."]
+    READY = 0,
+    #[doc = "1: An ADC conversion is taking place. ADC is busy."]
+    BUSY = 1,
+}
+impl From<BUSY_A> for bool {
+    #[inline(always)]
+    fn from(variant: BUSY_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl BUSY_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> BUSY_A {
+        match self.bits {
+            false => BUSY_A::READY,
+            true => BUSY_A::BUSY,
+        }
+    }
+    #[doc = "Checks if the value of the field is `READY`"]
+    #[inline(always)]
+    pub fn is_ready(&self) -> bool {
+        *self == BUSY_A::READY
+    }
+    #[doc = "Checks if the value of the field is `BUSY`"]
+    #[inline(always)]
+    pub fn is_busy(&self) -> bool {
+        *self == BUSY_A::BUSY
+    }
+}
+impl R {
+    #[doc = "Bit 0 - ADC busy register."]
+    #[inline(always)]
+    pub fn busy(&self) -> BUSY_R {
+        BUSY_R::new((self.bits & 1) != 0)
+    }
+}
+#[doc = "ADC busy register.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [busy](index.html) module"]
+pub struct BUSY_SPEC;
+impl crate::RegisterSpec for BUSY_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [busy::R](R) reader structure"]
+impl crate::Readable for BUSY_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets BUSY to value 0"]
+impl crate::Resettable for BUSY_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/adc/config.rs

@@ -0,0 +1,560 @@
+#[doc = "Register `CONFIG` reader"]
+pub struct R(crate::R<CONFIG_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<CONFIG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<CONFIG_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<CONFIG_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `CONFIG` writer"]
+pub struct W(crate::W<CONFIG_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<CONFIG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<CONFIG_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<CONFIG_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `RES` reader - ADC resolution."]
+pub type RES_R = crate::FieldReader<u8, RES_A>;
+#[doc = "ADC resolution.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum RES_A {
+    #[doc = "0: 8bit ADC resolution."]
+    _8BIT = 0,
+    #[doc = "1: 9bit ADC resolution."]
+    _9BIT = 1,
+    #[doc = "2: 10bit ADC resolution."]
+    _10BIT = 2,
+}
+impl From<RES_A> for u8 {
+    #[inline(always)]
+    fn from(variant: RES_A) -> Self {
+        variant as _
+    }
+}
+impl RES_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<RES_A> {
+        match self.bits {
+            0 => Some(RES_A::_8BIT),
+            1 => Some(RES_A::_9BIT),
+            2 => Some(RES_A::_10BIT),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_8BIT`"]
+    #[inline(always)]
+    pub fn is_8bit(&self) -> bool {
+        *self == RES_A::_8BIT
+    }
+    #[doc = "Checks if the value of the field is `_9BIT`"]
+    #[inline(always)]
+    pub fn is_9bit(&self) -> bool {
+        *self == RES_A::_9BIT
+    }
+    #[doc = "Checks if the value of the field is `_10BIT`"]
+    #[inline(always)]
+    pub fn is_10bit(&self) -> bool {
+        *self == RES_A::_10BIT
+    }
+}
+#[doc = "Field `RES` writer - ADC resolution."]
+pub type RES_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CONFIG_SPEC, u8, RES_A, 2, O>;
+impl<'a, const O: u8> RES_W<'a, O> {
+    #[doc = "8bit ADC resolution."]
+    #[inline(always)]
+    pub fn _8bit(self) -> &'a mut W {
+        self.variant(RES_A::_8BIT)
+    }
+    #[doc = "9bit ADC resolution."]
+    #[inline(always)]
+    pub fn _9bit(self) -> &'a mut W {
+        self.variant(RES_A::_9BIT)
+    }
+    #[doc = "10bit ADC resolution."]
+    #[inline(always)]
+    pub fn _10bit(self) -> &'a mut W {
+        self.variant(RES_A::_10BIT)
+    }
+}
+#[doc = "Field `INPSEL` reader - ADC input selection."]
+pub type INPSEL_R = crate::FieldReader<u8, INPSEL_A>;
+#[doc = "ADC input selection.\n\nValue on reset: 6"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum INPSEL_A {
+    #[doc = "0: Analog input specified by PSEL with no prescaling used as input for the conversion."]
+    ANALOG_INPUT_NO_PRESCALING = 0,
+    #[doc = "1: Analog input specified by PSEL with 2/3 prescaling used as input for the conversion."]
+    ANALOG_INPUT_TWO_THIRDS_PRESCALING = 1,
+    #[doc = "2: Analog input specified by PSEL with 1/3 prescaling used as input for the conversion."]
+    ANALOG_INPUT_ONE_THIRD_PRESCALING = 2,
+    #[doc = "5: Supply voltage with 2/3 prescaling used as input for the conversion."]
+    SUPPLY_TWO_THIRDS_PRESCALING = 5,
+    #[doc = "6: Supply voltage with 1/3 prescaling used as input for the conversion."]
+    SUPPLY_ONE_THIRD_PRESCALING = 6,
+}
+impl From<INPSEL_A> for u8 {
+    #[inline(always)]
+    fn from(variant: INPSEL_A) -> Self {
+        variant as _
+    }
+}
+impl INPSEL_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<INPSEL_A> {
+        match self.bits {
+            0 => Some(INPSEL_A::ANALOG_INPUT_NO_PRESCALING),
+            1 => Some(INPSEL_A::ANALOG_INPUT_TWO_THIRDS_PRESCALING),
+            2 => Some(INPSEL_A::ANALOG_INPUT_ONE_THIRD_PRESCALING),
+            5 => Some(INPSEL_A::SUPPLY_TWO_THIRDS_PRESCALING),
+            6 => Some(INPSEL_A::SUPPLY_ONE_THIRD_PRESCALING),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ANALOG_INPUT_NO_PRESCALING`"]
+    #[inline(always)]
+    pub fn is_analog_input_no_prescaling(&self) -> bool {
+        *self == INPSEL_A::ANALOG_INPUT_NO_PRESCALING
+    }
+    #[doc = "Checks if the value of the field is `ANALOG_INPUT_TWO_THIRDS_PRESCALING`"]
+    #[inline(always)]
+    pub fn is_analog_input_two_thirds_prescaling(&self) -> bool {
+        *self == INPSEL_A::ANALOG_INPUT_TWO_THIRDS_PRESCALING
+    }
+    #[doc = "Checks if the value of the field is `ANALOG_INPUT_ONE_THIRD_PRESCALING`"]
+    #[inline(always)]
+    pub fn is_analog_input_one_third_prescaling(&self) -> bool {
+        *self == INPSEL_A::ANALOG_INPUT_ONE_THIRD_PRESCALING
+    }
+    #[doc = "Checks if the value of the field is `SUPPLY_TWO_THIRDS_PRESCALING`"]
+    #[inline(always)]
+    pub fn is_supply_two_thirds_prescaling(&self) -> bool {
+        *self == INPSEL_A::SUPPLY_TWO_THIRDS_PRESCALING
+    }
+    #[doc = "Checks if the value of the field is `SUPPLY_ONE_THIRD_PRESCALING`"]
+    #[inline(always)]
+    pub fn is_supply_one_third_prescaling(&self) -> bool {
+        *self == INPSEL_A::SUPPLY_ONE_THIRD_PRESCALING
+    }
+}
+#[doc = "Field `INPSEL` writer - ADC input selection."]
+pub type INPSEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CONFIG_SPEC, u8, INPSEL_A, 3, O>;
+impl<'a, const O: u8> INPSEL_W<'a, O> {
+    #[doc = "Analog input specified by PSEL with no prescaling used as input for the conversion."]
+    #[inline(always)]
+    pub fn analog_input_no_prescaling(self) -> &'a mut W {
+        self.variant(INPSEL_A::ANALOG_INPUT_NO_PRESCALING)
+    }
+    #[doc = "Analog input specified by PSEL with 2/3 prescaling used as input for the conversion."]
+    #[inline(always)]
+    pub fn analog_input_two_thirds_prescaling(self) -> &'a mut W {
+        self.variant(INPSEL_A::ANALOG_INPUT_TWO_THIRDS_PRESCALING)
+    }
+    #[doc = "Analog input specified by PSEL with 1/3 prescaling used as input for the conversion."]
+    #[inline(always)]
+    pub fn analog_input_one_third_prescaling(self) -> &'a mut W {
+        self.variant(INPSEL_A::ANALOG_INPUT_ONE_THIRD_PRESCALING)
+    }
+    #[doc = "Supply voltage with 2/3 prescaling used as input for the conversion."]
+    #[inline(always)]
+    pub fn supply_two_thirds_prescaling(self) -> &'a mut W {
+        self.variant(INPSEL_A::SUPPLY_TWO_THIRDS_PRESCALING)
+    }
+    #[doc = "Supply voltage with 1/3 prescaling used as input for the conversion."]
+    #[inline(always)]
+    pub fn supply_one_third_prescaling(self) -> &'a mut W {
+        self.variant(INPSEL_A::SUPPLY_ONE_THIRD_PRESCALING)
+    }
+}
+#[doc = "Field `REFSEL` reader - ADC reference selection."]
+pub type REFSEL_R = crate::FieldReader<u8, REFSEL_A>;
+#[doc = "ADC reference selection.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum REFSEL_A {
+    #[doc = "0: Use internal 1.2V bandgap voltage as reference for conversion."]
+    VBG = 0,
+    #[doc = "1: Use external source configured by EXTREFSEL as reference for conversion."]
+    EXTERNAL = 1,
+    #[doc = "2: Use supply voltage with 1/2 prescaling as reference for conversion. Only usable when supply voltage is between 1.7V and 2.6V."]
+    SUPPLY_ONE_HALF_PRESCALING = 2,
+    #[doc = "3: Use supply voltage with 1/3 prescaling as reference for conversion. Only usable when supply voltage is between 2.5V and 3.6V."]
+    SUPPLY_ONE_THIRD_PRESCALING = 3,
+}
+impl From<REFSEL_A> for u8 {
+    #[inline(always)]
+    fn from(variant: REFSEL_A) -> Self {
+        variant as _
+    }
+}
+impl REFSEL_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> REFSEL_A {
+        match self.bits {
+            0 => REFSEL_A::VBG,
+            1 => REFSEL_A::EXTERNAL,
+            2 => REFSEL_A::SUPPLY_ONE_HALF_PRESCALING,
+            3 => REFSEL_A::SUPPLY_ONE_THIRD_PRESCALING,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `VBG`"]
+    #[inline(always)]
+    pub fn is_vbg(&self) -> bool {
+        *self == REFSEL_A::VBG
+    }
+    #[doc = "Checks if the value of the field is `EXTERNAL`"]
+    #[inline(always)]
+    pub fn is_external(&self) -> bool {
+        *self == REFSEL_A::EXTERNAL
+    }
+    #[doc = "Checks if the value of the field is `SUPPLY_ONE_HALF_PRESCALING`"]
+    #[inline(always)]
+    pub fn is_supply_one_half_prescaling(&self) -> bool {
+        *self == REFSEL_A::SUPPLY_ONE_HALF_PRESCALING
+    }
+    #[doc = "Checks if the value of the field is `SUPPLY_ONE_THIRD_PRESCALING`"]
+    #[inline(always)]
+    pub fn is_supply_one_third_prescaling(&self) -> bool {
+        *self == REFSEL_A::SUPPLY_ONE_THIRD_PRESCALING
+    }
+}
+#[doc = "Field `REFSEL` writer - ADC reference selection."]
+pub type REFSEL_W<'a, const O: u8> =
+    crate::FieldWriterSafe<'a, u32, CONFIG_SPEC, u8, REFSEL_A, 2, O>;
+impl<'a, const O: u8> REFSEL_W<'a, O> {
+    #[doc = "Use internal 1.2V bandgap voltage as reference for conversion."]
+    #[inline(always)]
+    pub fn vbg(self) -> &'a mut W {
+        self.variant(REFSEL_A::VBG)
+    }
+    #[doc = "Use external source configured by EXTREFSEL as reference for conversion."]
+    #[inline(always)]
+    pub fn external(self) -> &'a mut W {
+        self.variant(REFSEL_A::EXTERNAL)
+    }
+    #[doc = "Use supply voltage with 1/2 prescaling as reference for conversion. Only usable when supply voltage is between 1.7V and 2.6V."]
+    #[inline(always)]
+    pub fn supply_one_half_prescaling(self) -> &'a mut W {
+        self.variant(REFSEL_A::SUPPLY_ONE_HALF_PRESCALING)
+    }
+    #[doc = "Use supply voltage with 1/3 prescaling as reference for conversion. Only usable when supply voltage is between 2.5V and 3.6V."]
+    #[inline(always)]
+    pub fn supply_one_third_prescaling(self) -> &'a mut W {
+        self.variant(REFSEL_A::SUPPLY_ONE_THIRD_PRESCALING)
+    }
+}
+#[doc = "Field `PSEL` reader - ADC analog pin selection."]
+pub type PSEL_R = crate::FieldReader<u8, PSEL_A>;
+#[doc = "ADC analog pin selection.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum PSEL_A {
+    #[doc = "0: Analog input pins disabled."]
+    DISABLED = 0,
+    #[doc = "1: Use analog input 0 as analog input."]
+    ANALOG_INPUT0 = 1,
+    #[doc = "2: Use analog input 1 as analog input."]
+    ANALOG_INPUT1 = 2,
+    #[doc = "4: Use analog input 2 as analog input."]
+    ANALOG_INPUT2 = 4,
+    #[doc = "8: Use analog input 3 as analog input."]
+    ANALOG_INPUT3 = 8,
+    #[doc = "16: Use analog input 4 as analog input."]
+    ANALOG_INPUT4 = 16,
+    #[doc = "32: Use analog input 5 as analog input."]
+    ANALOG_INPUT5 = 32,
+    #[doc = "64: Use analog input 6 as analog input."]
+    ANALOG_INPUT6 = 64,
+    #[doc = "128: Use analog input 7 as analog input."]
+    ANALOG_INPUT7 = 128,
+}
+impl From<PSEL_A> for u8 {
+    #[inline(always)]
+    fn from(variant: PSEL_A) -> Self {
+        variant as _
+    }
+}
+impl PSEL_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<PSEL_A> {
+        match self.bits {
+            0 => Some(PSEL_A::DISABLED),
+            1 => Some(PSEL_A::ANALOG_INPUT0),
+            2 => Some(PSEL_A::ANALOG_INPUT1),
+            4 => Some(PSEL_A::ANALOG_INPUT2),
+            8 => Some(PSEL_A::ANALOG_INPUT3),
+            16 => Some(PSEL_A::ANALOG_INPUT4),
+            32 => Some(PSEL_A::ANALOG_INPUT5),
+            64 => Some(PSEL_A::ANALOG_INPUT6),
+            128 => Some(PSEL_A::ANALOG_INPUT7),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == PSEL_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ANALOG_INPUT0`"]
+    #[inline(always)]
+    pub fn is_analog_input0(&self) -> bool {
+        *self == PSEL_A::ANALOG_INPUT0
+    }
+    #[doc = "Checks if the value of the field is `ANALOG_INPUT1`"]
+    #[inline(always)]
+    pub fn is_analog_input1(&self) -> bool {
+        *self == PSEL_A::ANALOG_INPUT1
+    }
+    #[doc = "Checks if the value of the field is `ANALOG_INPUT2`"]
+    #[inline(always)]
+    pub fn is_analog_input2(&self) -> bool {
+        *self == PSEL_A::ANALOG_INPUT2
+    }
+    #[doc = "Checks if the value of the field is `ANALOG_INPUT3`"]
+    #[inline(always)]
+    pub fn is_analog_input3(&self) -> bool {
+        *self == PSEL_A::ANALOG_INPUT3
+    }
+    #[doc = "Checks if the value of the field is `ANALOG_INPUT4`"]
+    #[inline(always)]
+    pub fn is_analog_input4(&self) -> bool {
+        *self == PSEL_A::ANALOG_INPUT4
+    }
+    #[doc = "Checks if the value of the field is `ANALOG_INPUT5`"]
+    #[inline(always)]
+    pub fn is_analog_input5(&self) -> bool {
+        *self == PSEL_A::ANALOG_INPUT5
+    }
+    #[doc = "Checks if the value of the field is `ANALOG_INPUT6`"]
+    #[inline(always)]
+    pub fn is_analog_input6(&self) -> bool {
+        *self == PSEL_A::ANALOG_INPUT6
+    }
+    #[doc = "Checks if the value of the field is `ANALOG_INPUT7`"]
+    #[inline(always)]
+    pub fn is_analog_input7(&self) -> bool {
+        *self == PSEL_A::ANALOG_INPUT7
+    }
+}
+#[doc = "Field `PSEL` writer - ADC analog pin selection."]
+pub type PSEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CONFIG_SPEC, u8, PSEL_A, 8, O>;
+impl<'a, const O: u8> PSEL_W<'a, O> {
+    #[doc = "Analog input pins disabled."]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(PSEL_A::DISABLED)
+    }
+    #[doc = "Use analog input 0 as analog input."]
+    #[inline(always)]
+    pub fn analog_input0(self) -> &'a mut W {
+        self.variant(PSEL_A::ANALOG_INPUT0)
+    }
+    #[doc = "Use analog input 1 as analog input."]
+    #[inline(always)]
+    pub fn analog_input1(self) -> &'a mut W {
+        self.variant(PSEL_A::ANALOG_INPUT1)
+    }
+    #[doc = "Use analog input 2 as analog input."]
+    #[inline(always)]
+    pub fn analog_input2(self) -> &'a mut W {
+        self.variant(PSEL_A::ANALOG_INPUT2)
+    }
+    #[doc = "Use analog input 3 as analog input."]
+    #[inline(always)]
+    pub fn analog_input3(self) -> &'a mut W {
+        self.variant(PSEL_A::ANALOG_INPUT3)
+    }
+    #[doc = "Use analog input 4 as analog input."]
+    #[inline(always)]
+    pub fn analog_input4(self) -> &'a mut W {
+        self.variant(PSEL_A::ANALOG_INPUT4)
+    }
+    #[doc = "Use analog input 5 as analog input."]
+    #[inline(always)]
+    pub fn analog_input5(self) -> &'a mut W {
+        self.variant(PSEL_A::ANALOG_INPUT5)
+    }
+    #[doc = "Use analog input 6 as analog input."]
+    #[inline(always)]
+    pub fn analog_input6(self) -> &'a mut W {
+        self.variant(PSEL_A::ANALOG_INPUT6)
+    }
+    #[doc = "Use analog input 7 as analog input."]
+    #[inline(always)]
+    pub fn analog_input7(self) -> &'a mut W {
+        self.variant(PSEL_A::ANALOG_INPUT7)
+    }
+}
+#[doc = "Field `EXTREFSEL` reader - ADC external reference pin selection."]
+pub type EXTREFSEL_R = crate::FieldReader<u8, EXTREFSEL_A>;
+#[doc = "ADC external reference pin selection.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum EXTREFSEL_A {
+    #[doc = "0: Analog external reference inputs disabled."]
+    NONE = 0,
+    #[doc = "1: Use analog reference 0 as reference."]
+    ANALOG_REFERENCE0 = 1,
+    #[doc = "2: Use analog reference 1 as reference."]
+    ANALOG_REFERENCE1 = 2,
+}
+impl From<EXTREFSEL_A> for u8 {
+    #[inline(always)]
+    fn from(variant: EXTREFSEL_A) -> Self {
+        variant as _
+    }
+}
+impl EXTREFSEL_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<EXTREFSEL_A> {
+        match self.bits {
+            0 => Some(EXTREFSEL_A::NONE),
+            1 => Some(EXTREFSEL_A::ANALOG_REFERENCE0),
+            2 => Some(EXTREFSEL_A::ANALOG_REFERENCE1),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `NONE`"]
+    #[inline(always)]
+    pub fn is_none(&self) -> bool {
+        *self == EXTREFSEL_A::NONE
+    }
+    #[doc = "Checks if the value of the field is `ANALOG_REFERENCE0`"]
+    #[inline(always)]
+    pub fn is_analog_reference0(&self) -> bool {
+        *self == EXTREFSEL_A::ANALOG_REFERENCE0
+    }
+    #[doc = "Checks if the value of the field is `ANALOG_REFERENCE1`"]
+    #[inline(always)]
+    pub fn is_analog_reference1(&self) -> bool {
+        *self == EXTREFSEL_A::ANALOG_REFERENCE1
+    }
+}
+#[doc = "Field `EXTREFSEL` writer - ADC external reference pin selection."]
+pub type EXTREFSEL_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u32, CONFIG_SPEC, u8, EXTREFSEL_A, 2, O>;
+impl<'a, const O: u8> EXTREFSEL_W<'a, O> {
+    #[doc = "Analog external reference inputs disabled."]
+    #[inline(always)]
+    pub fn none(self) -> &'a mut W {
+        self.variant(EXTREFSEL_A::NONE)
+    }
+    #[doc = "Use analog reference 0 as reference."]
+    #[inline(always)]
+    pub fn analog_reference0(self) -> &'a mut W {
+        self.variant(EXTREFSEL_A::ANALOG_REFERENCE0)
+    }
+    #[doc = "Use analog reference 1 as reference."]
+    #[inline(always)]
+    pub fn analog_reference1(self) -> &'a mut W {
+        self.variant(EXTREFSEL_A::ANALOG_REFERENCE1)
+    }
+}
+impl R {
+    #[doc = "Bits 0:1 - ADC resolution."]
+    #[inline(always)]
+    pub fn res(&self) -> RES_R {
+        RES_R::new((self.bits & 3) as u8)
+    }
+    #[doc = "Bits 2:4 - ADC input selection."]
+    #[inline(always)]
+    pub fn inpsel(&self) -> INPSEL_R {
+        INPSEL_R::new(((self.bits >> 2) & 7) as u8)
+    }
+    #[doc = "Bits 5:6 - ADC reference selection."]
+    #[inline(always)]
+    pub fn refsel(&self) -> REFSEL_R {
+        REFSEL_R::new(((self.bits >> 5) & 3) as u8)
+    }
+    #[doc = "Bits 8:15 - ADC analog pin selection."]
+    #[inline(always)]
+    pub fn psel(&self) -> PSEL_R {
+        PSEL_R::new(((self.bits >> 8) & 0xff) as u8)
+    }
+    #[doc = "Bits 16:17 - ADC external reference pin selection."]
+    #[inline(always)]
+    pub fn extrefsel(&self) -> EXTREFSEL_R {
+        EXTREFSEL_R::new(((self.bits >> 16) & 3) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:1 - ADC resolution."]
+    #[inline(always)]
+    pub fn res(&mut self) -> RES_W<0> {
+        RES_W::new(self)
+    }
+    #[doc = "Bits 2:4 - ADC input selection."]
+    #[inline(always)]
+    pub fn inpsel(&mut self) -> INPSEL_W<2> {
+        INPSEL_W::new(self)
+    }
+    #[doc = "Bits 5:6 - ADC reference selection."]
+    #[inline(always)]
+    pub fn refsel(&mut self) -> REFSEL_W<5> {
+        REFSEL_W::new(self)
+    }
+    #[doc = "Bits 8:15 - ADC analog pin selection."]
+    #[inline(always)]
+    pub fn psel(&mut self) -> PSEL_W<8> {
+        PSEL_W::new(self)
+    }
+    #[doc = "Bits 16:17 - ADC external reference pin selection."]
+    #[inline(always)]
+    pub fn extrefsel(&mut self) -> EXTREFSEL_W<16> {
+        EXTREFSEL_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "ADC configuration register.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [config](index.html) module"]
+pub struct CONFIG_SPEC;
+impl crate::RegisterSpec for CONFIG_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [config::R](R) reader structure"]
+impl crate::Readable for CONFIG_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [config::W](W) writer structure"]
+impl crate::Writable for CONFIG_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets CONFIG to value 0x18"]
+impl crate::Resettable for CONFIG_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0x18
+    }
+}

vendor/nrf51-pac/src/adc/enable.rs

@@ -0,0 +1,128 @@
+#[doc = "Register `ENABLE` reader"]
+pub struct R(crate::R<ENABLE_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<ENABLE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<ENABLE_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<ENABLE_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `ENABLE` writer"]
+pub struct W(crate::W<ENABLE_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<ENABLE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<ENABLE_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<ENABLE_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `ENABLE` reader - ADC enable."]
+pub type ENABLE_R = crate::FieldReader<u8, ENABLE_A>;
+#[doc = "ADC enable.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum ENABLE_A {
+    #[doc = "0: ADC is disabled."]
+    DISABLED = 0,
+    #[doc = "1: ADC is enabled. If an analog input pin is selected as source of the conversion, the selected pin is configured as an analog input."]
+    ENABLED = 1,
+}
+impl From<ENABLE_A> for u8 {
+    #[inline(always)]
+    fn from(variant: ENABLE_A) -> Self {
+        variant as _
+    }
+}
+impl ENABLE_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<ENABLE_A> {
+        match self.bits {
+            0 => Some(ENABLE_A::DISABLED),
+            1 => Some(ENABLE_A::ENABLED),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == ENABLE_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == ENABLE_A::ENABLED
+    }
+}
+#[doc = "Field `ENABLE` writer - ADC enable."]
+pub type ENABLE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ENABLE_SPEC, u8, ENABLE_A, 2, O>;
+impl<'a, const O: u8> ENABLE_W<'a, O> {
+    #[doc = "ADC is disabled."]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(ENABLE_A::DISABLED)
+    }
+    #[doc = "ADC is enabled. If an analog input pin is selected as source of the conversion, the selected pin is configured as an analog input."]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(ENABLE_A::ENABLED)
+    }
+}
+impl R {
+    #[doc = "Bits 0:1 - ADC enable."]
+    #[inline(always)]
+    pub fn enable(&self) -> ENABLE_R {
+        ENABLE_R::new((self.bits & 3) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:1 - ADC enable."]
+    #[inline(always)]
+    pub fn enable(&mut self) -> ENABLE_W<0> {
+        ENABLE_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "ADC enable.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [enable](index.html) module"]
+pub struct ENABLE_SPEC;
+impl crate::RegisterSpec for ENABLE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [enable::R](R) reader structure"]
+impl crate::Readable for ENABLE_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [enable::W](W) writer structure"]
+impl crate::Writable for ENABLE_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets ENABLE to value 0"]
+impl crate::Resettable for ENABLE_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/adc/events_end.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `EVENTS_END` reader"]
+pub struct R(crate::R<EVENTS_END_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<EVENTS_END_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<EVENTS_END_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<EVENTS_END_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `EVENTS_END` writer"]
+pub struct W(crate::W<EVENTS_END_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<EVENTS_END_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<EVENTS_END_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<EVENTS_END_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "ADC conversion complete.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_end](index.html) module"]
+pub struct EVENTS_END_SPEC;
+impl crate::RegisterSpec for EVENTS_END_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [events_end::R](R) reader structure"]
+impl crate::Readable for EVENTS_END_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [events_end::W](W) writer structure"]
+impl crate::Writable for EVENTS_END_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets EVENTS_END to value 0"]
+impl crate::Resettable for EVENTS_END_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/adc/intenclr.rs

@@ -0,0 +1,133 @@
+#[doc = "Register `INTENCLR` reader"]
+pub struct R(crate::R<INTENCLR_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<INTENCLR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<INTENCLR_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<INTENCLR_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `INTENCLR` writer"]
+pub struct W(crate::W<INTENCLR_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<INTENCLR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<INTENCLR_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<INTENCLR_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `END` reader - Disable interrupt on END event."]
+pub type END_R = crate::BitReader<END_A>;
+#[doc = "Disable interrupt on END event.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum END_A {
+    #[doc = "0: Interrupt disabled."]
+    DISABLED = 0,
+    #[doc = "1: Interrupt enabled."]
+    ENABLED = 1,
+}
+impl From<END_A> for bool {
+    #[inline(always)]
+    fn from(variant: END_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl END_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> END_A {
+        match self.bits {
+            false => END_A::DISABLED,
+            true => END_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == END_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == END_A::ENABLED
+    }
+}
+#[doc = "Disable interrupt on END event.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum END_AW {
+    #[doc = "1: Disable interrupt on write."]
+    CLEAR = 1,
+}
+impl From<END_AW> for bool {
+    #[inline(always)]
+    fn from(variant: END_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `END` writer - Disable interrupt on END event."]
+pub type END_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, END_AW, O>;
+impl<'a, const O: u8> END_W<'a, O> {
+    #[doc = "Disable interrupt on write."]
+    #[inline(always)]
+    pub fn clear(self) -> &'a mut W {
+        self.variant(END_AW::CLEAR)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Disable interrupt on END event."]
+    #[inline(always)]
+    pub fn end(&self) -> END_R {
+        END_R::new((self.bits & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Disable interrupt on END event."]
+    #[inline(always)]
+    pub fn end(&mut self) -> END_W<0> {
+        END_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Interrupt enable clear register.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"]
+pub struct INTENCLR_SPEC;
+impl crate::RegisterSpec for INTENCLR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [intenclr::R](R) reader structure"]
+impl crate::Readable for INTENCLR_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"]
+impl crate::Writable for INTENCLR_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets INTENCLR to value 0"]
+impl crate::Resettable for INTENCLR_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/adc/intenset.rs

@@ -0,0 +1,133 @@
+#[doc = "Register `INTENSET` reader"]
+pub struct R(crate::R<INTENSET_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<INTENSET_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<INTENSET_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<INTENSET_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `INTENSET` writer"]
+pub struct W(crate::W<INTENSET_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<INTENSET_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<INTENSET_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<INTENSET_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `END` reader - Enable interrupt on END event."]
+pub type END_R = crate::BitReader<END_A>;
+#[doc = "Enable interrupt on END event.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum END_A {
+    #[doc = "0: Interrupt disabled."]
+    DISABLED = 0,
+    #[doc = "1: Interrupt enabled."]
+    ENABLED = 1,
+}
+impl From<END_A> for bool {
+    #[inline(always)]
+    fn from(variant: END_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl END_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> END_A {
+        match self.bits {
+            false => END_A::DISABLED,
+            true => END_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == END_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == END_A::ENABLED
+    }
+}
+#[doc = "Enable interrupt on END event.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum END_AW {
+    #[doc = "1: Enable interrupt on write."]
+    SET = 1,
+}
+impl From<END_AW> for bool {
+    #[inline(always)]
+    fn from(variant: END_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `END` writer - Enable interrupt on END event."]
+pub type END_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, END_AW, O>;
+impl<'a, const O: u8> END_W<'a, O> {
+    #[doc = "Enable interrupt on write."]
+    #[inline(always)]
+    pub fn set(self) -> &'a mut W {
+        self.variant(END_AW::SET)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Enable interrupt on END event."]
+    #[inline(always)]
+    pub fn end(&self) -> END_R {
+        END_R::new((self.bits & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Enable interrupt on END event."]
+    #[inline(always)]
+    pub fn end(&mut self) -> END_W<0> {
+        END_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Interrupt enable set register.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"]
+pub struct INTENSET_SPEC;
+impl crate::RegisterSpec for INTENSET_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [intenset::R](R) reader structure"]
+impl crate::Readable for INTENSET_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"]
+impl crate::Writable for INTENSET_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets INTENSET to value 0"]
+impl crate::Resettable for INTENSET_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/adc/power.rs

@@ -0,0 +1,126 @@
+#[doc = "Register `POWER` reader"]
+pub struct R(crate::R<POWER_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<POWER_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<POWER_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<POWER_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `POWER` writer"]
+pub struct W(crate::W<POWER_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<POWER_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<POWER_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<POWER_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `POWER` reader - Peripheral power control."]
+pub type POWER_R = crate::BitReader<POWER_A>;
+#[doc = "Peripheral power control.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum POWER_A {
+    #[doc = "0: Module power disabled."]
+    DISABLED = 0,
+    #[doc = "1: Module power enabled."]
+    ENABLED = 1,
+}
+impl From<POWER_A> for bool {
+    #[inline(always)]
+    fn from(variant: POWER_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl POWER_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> POWER_A {
+        match self.bits {
+            false => POWER_A::DISABLED,
+            true => POWER_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == POWER_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == POWER_A::ENABLED
+    }
+}
+#[doc = "Field `POWER` writer - Peripheral power control."]
+pub type POWER_W<'a, const O: u8> = crate::BitWriter<'a, u32, POWER_SPEC, POWER_A, O>;
+impl<'a, const O: u8> POWER_W<'a, O> {
+    #[doc = "Module power disabled."]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(POWER_A::DISABLED)
+    }
+    #[doc = "Module power enabled."]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(POWER_A::ENABLED)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Peripheral power control."]
+    #[inline(always)]
+    pub fn power(&self) -> POWER_R {
+        POWER_R::new((self.bits & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Peripheral power control."]
+    #[inline(always)]
+    pub fn power(&mut self) -> POWER_W<0> {
+        POWER_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Peripheral power control.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [power](index.html) module"]
+pub struct POWER_SPEC;
+impl crate::RegisterSpec for POWER_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [power::R](R) reader structure"]
+impl crate::Readable for POWER_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [power::W](W) writer structure"]
+impl crate::Writable for POWER_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets POWER to value 0"]
+impl crate::Resettable for POWER_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/adc/result.rs

@@ -0,0 +1,40 @@
+#[doc = "Register `RESULT` reader"]
+pub struct R(crate::R<RESULT_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<RESULT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<RESULT_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<RESULT_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `RESULT` reader - Result of ADC conversion."]
+pub type RESULT_R = crate::FieldReader<u16, u16>;
+impl R {
+    #[doc = "Bits 0:9 - Result of ADC conversion."]
+    #[inline(always)]
+    pub fn result(&self) -> RESULT_R {
+        RESULT_R::new((self.bits & 0x03ff) as u16)
+    }
+}
+#[doc = "Result of ADC conversion.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [result](index.html) module"]
+pub struct RESULT_SPEC;
+impl crate::RegisterSpec for RESULT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [result::R](R) reader structure"]
+impl crate::Readable for RESULT_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets RESULT to value 0"]
+impl crate::Resettable for RESULT_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/adc/tasks_start.rs

@@ -0,0 +1,45 @@
+#[doc = "Register `TASKS_START` writer"]
+pub struct W(crate::W<TASKS_START_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<TASKS_START_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<TASKS_START_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<TASKS_START_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Start an ADC conversion.\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_start](index.html) module"]
+pub struct TASKS_START_SPEC;
+impl crate::RegisterSpec for TASKS_START_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [tasks_start::W](W) writer structure"]
+impl crate::Writable for TASKS_START_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets TASKS_START to value 0"]
+impl crate::Resettable for TASKS_START_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/adc/tasks_stop.rs

@@ -0,0 +1,45 @@
+#[doc = "Register `TASKS_STOP` writer"]
+pub struct W(crate::W<TASKS_STOP_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<TASKS_STOP_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<TASKS_STOP_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<TASKS_STOP_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Stop ADC.\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_stop](index.html) module"]
+pub struct TASKS_STOP_SPEC;
+impl crate::RegisterSpec for TASKS_STOP_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [tasks_stop::W](W) writer structure"]
+impl crate::Writable for TASKS_STOP_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets TASKS_STOP to value 0"]
+impl crate::Resettable for TASKS_STOP_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/ccm.rs

@@ -0,0 +1,112 @@
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00 - Start generation of key-stream. This operation will stop by itself when completed."]
+    pub tasks_ksgen: TASKS_KSGEN,
+    #[doc = "0x04 - Start encrypt/decrypt. This operation will stop by itself when completed."]
+    pub tasks_crypt: TASKS_CRYPT,
+    #[doc = "0x08 - Stop encrypt/decrypt."]
+    pub tasks_stop: TASKS_STOP,
+    _reserved3: [u8; 0xf4],
+    #[doc = "0x100 - Keystream generation completed."]
+    pub events_endksgen: EVENTS_ENDKSGEN,
+    #[doc = "0x104 - Encrypt/decrypt completed."]
+    pub events_endcrypt: EVENTS_ENDCRYPT,
+    #[doc = "0x108 - Error happened."]
+    pub events_error: EVENTS_ERROR,
+    _reserved6: [u8; 0xf4],
+    #[doc = "0x200 - Shortcuts for the CCM."]
+    pub shorts: SHORTS,
+    _reserved7: [u8; 0x0100],
+    #[doc = "0x304 - Interrupt enable set register."]
+    pub intenset: INTENSET,
+    #[doc = "0x308 - Interrupt enable clear register."]
+    pub intenclr: INTENCLR,
+    _reserved9: [u8; 0xf4],
+    #[doc = "0x400 - CCM RX MIC check result."]
+    pub micstatus: MICSTATUS,
+    _reserved10: [u8; 0xfc],
+    #[doc = "0x500 - CCM enable."]
+    pub enable: ENABLE,
+    #[doc = "0x504 - Operation mode."]
+    pub mode: MODE,
+    #[doc = "0x508 - Pointer to a data structure holding AES key and NONCE vector."]
+    pub cnfptr: CNFPTR,
+    #[doc = "0x50c - Pointer to the input packet."]
+    pub inptr: INPTR,
+    #[doc = "0x510 - Pointer to the output packet."]
+    pub outptr: OUTPTR,
+    #[doc = "0x514 - Pointer to a scratch data area used for temporary storage during resolution. A minimum of 43 bytes must be reserved."]
+    pub scratchptr: SCRATCHPTR,
+    _reserved16: [u8; 0x0ae4],
+    #[doc = "0xffc - Peripheral power control."]
+    pub power: POWER,
+}
+#[doc = "TASKS_KSGEN (w) register accessor: an alias for `Reg<TASKS_KSGEN_SPEC>`"]
+pub type TASKS_KSGEN = crate::Reg<tasks_ksgen::TASKS_KSGEN_SPEC>;
+#[doc = "Start generation of key-stream. This operation will stop by itself when completed."]
+pub mod tasks_ksgen;
+#[doc = "TASKS_CRYPT (w) register accessor: an alias for `Reg<TASKS_CRYPT_SPEC>`"]
+pub type TASKS_CRYPT = crate::Reg<tasks_crypt::TASKS_CRYPT_SPEC>;
+#[doc = "Start encrypt/decrypt. This operation will stop by itself when completed."]
+pub mod tasks_crypt;
+#[doc = "TASKS_STOP (w) register accessor: an alias for `Reg<TASKS_STOP_SPEC>`"]
+pub type TASKS_STOP = crate::Reg<tasks_stop::TASKS_STOP_SPEC>;
+#[doc = "Stop encrypt/decrypt."]
+pub mod tasks_stop;
+#[doc = "EVENTS_ENDKSGEN (rw) register accessor: an alias for `Reg<EVENTS_ENDKSGEN_SPEC>`"]
+pub type EVENTS_ENDKSGEN = crate::Reg<events_endksgen::EVENTS_ENDKSGEN_SPEC>;
+#[doc = "Keystream generation completed."]
+pub mod events_endksgen;
+#[doc = "EVENTS_ENDCRYPT (rw) register accessor: an alias for `Reg<EVENTS_ENDCRYPT_SPEC>`"]
+pub type EVENTS_ENDCRYPT = crate::Reg<events_endcrypt::EVENTS_ENDCRYPT_SPEC>;
+#[doc = "Encrypt/decrypt completed."]
+pub mod events_endcrypt;
+#[doc = "EVENTS_ERROR (rw) register accessor: an alias for `Reg<EVENTS_ERROR_SPEC>`"]
+pub type EVENTS_ERROR = crate::Reg<events_error::EVENTS_ERROR_SPEC>;
+#[doc = "Error happened."]
+pub mod events_error;
+#[doc = "SHORTS (rw) register accessor: an alias for `Reg<SHORTS_SPEC>`"]
+pub type SHORTS = crate::Reg<shorts::SHORTS_SPEC>;
+#[doc = "Shortcuts for the CCM."]
+pub mod shorts;
+#[doc = "INTENSET (rw) register accessor: an alias for `Reg<INTENSET_SPEC>`"]
+pub type INTENSET = crate::Reg<intenset::INTENSET_SPEC>;
+#[doc = "Interrupt enable set register."]
+pub mod intenset;
+#[doc = "INTENCLR (rw) register accessor: an alias for `Reg<INTENCLR_SPEC>`"]
+pub type INTENCLR = crate::Reg<intenclr::INTENCLR_SPEC>;
+#[doc = "Interrupt enable clear register."]
+pub mod intenclr;
+#[doc = "MICSTATUS (r) register accessor: an alias for `Reg<MICSTATUS_SPEC>`"]
+pub type MICSTATUS = crate::Reg<micstatus::MICSTATUS_SPEC>;
+#[doc = "CCM RX MIC check result."]
+pub mod micstatus;
+#[doc = "ENABLE (rw) register accessor: an alias for `Reg<ENABLE_SPEC>`"]
+pub type ENABLE = crate::Reg<enable::ENABLE_SPEC>;
+#[doc = "CCM enable."]
+pub mod enable;
+#[doc = "MODE (rw) register accessor: an alias for `Reg<MODE_SPEC>`"]
+pub type MODE = crate::Reg<mode::MODE_SPEC>;
+#[doc = "Operation mode."]
+pub mod mode;
+#[doc = "CNFPTR (rw) register accessor: an alias for `Reg<CNFPTR_SPEC>`"]
+pub type CNFPTR = crate::Reg<cnfptr::CNFPTR_SPEC>;
+#[doc = "Pointer to a data structure holding AES key and NONCE vector."]
+pub mod cnfptr;
+#[doc = "INPTR (rw) register accessor: an alias for `Reg<INPTR_SPEC>`"]
+pub type INPTR = crate::Reg<inptr::INPTR_SPEC>;
+#[doc = "Pointer to the input packet."]
+pub mod inptr;
+#[doc = "OUTPTR (rw) register accessor: an alias for `Reg<OUTPTR_SPEC>`"]
+pub type OUTPTR = crate::Reg<outptr::OUTPTR_SPEC>;
+#[doc = "Pointer to the output packet."]
+pub mod outptr;
+#[doc = "SCRATCHPTR (rw) register accessor: an alias for `Reg<SCRATCHPTR_SPEC>`"]
+pub type SCRATCHPTR = crate::Reg<scratchptr::SCRATCHPTR_SPEC>;
+#[doc = "Pointer to a scratch data area used for temporary storage during resolution. A minimum of 43 bytes must be reserved."]
+pub mod scratchptr;
+#[doc = "POWER (rw) register accessor: an alias for `Reg<POWER_SPEC>`"]
+pub type POWER = crate::Reg<power::POWER_SPEC>;
+#[doc = "Peripheral power control."]
+pub mod power;

vendor/nrf51-pac/src/ccm/cnfptr.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `CNFPTR` reader"]
+pub struct R(crate::R<CNFPTR_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<CNFPTR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<CNFPTR_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<CNFPTR_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `CNFPTR` writer"]
+pub struct W(crate::W<CNFPTR_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<CNFPTR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<CNFPTR_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<CNFPTR_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Pointer to a data structure holding AES key and NONCE vector.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cnfptr](index.html) module"]
+pub struct CNFPTR_SPEC;
+impl crate::RegisterSpec for CNFPTR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [cnfptr::R](R) reader structure"]
+impl crate::Readable for CNFPTR_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [cnfptr::W](W) writer structure"]
+impl crate::Writable for CNFPTR_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets CNFPTR to value 0"]
+impl crate::Resettable for CNFPTR_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/ccm/enable.rs

@@ -0,0 +1,128 @@
+#[doc = "Register `ENABLE` reader"]
+pub struct R(crate::R<ENABLE_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<ENABLE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<ENABLE_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<ENABLE_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `ENABLE` writer"]
+pub struct W(crate::W<ENABLE_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<ENABLE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<ENABLE_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<ENABLE_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `ENABLE` reader - CCM enable."]
+pub type ENABLE_R = crate::FieldReader<u8, ENABLE_A>;
+#[doc = "CCM enable.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum ENABLE_A {
+    #[doc = "0: CCM is disabled."]
+    DISABLED = 0,
+    #[doc = "2: CCM is enabled."]
+    ENABLED = 2,
+}
+impl From<ENABLE_A> for u8 {
+    #[inline(always)]
+    fn from(variant: ENABLE_A) -> Self {
+        variant as _
+    }
+}
+impl ENABLE_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<ENABLE_A> {
+        match self.bits {
+            0 => Some(ENABLE_A::DISABLED),
+            2 => Some(ENABLE_A::ENABLED),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == ENABLE_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == ENABLE_A::ENABLED
+    }
+}
+#[doc = "Field `ENABLE` writer - CCM enable."]
+pub type ENABLE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ENABLE_SPEC, u8, ENABLE_A, 2, O>;
+impl<'a, const O: u8> ENABLE_W<'a, O> {
+    #[doc = "CCM is disabled."]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(ENABLE_A::DISABLED)
+    }
+    #[doc = "CCM is enabled."]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(ENABLE_A::ENABLED)
+    }
+}
+impl R {
+    #[doc = "Bits 0:1 - CCM enable."]
+    #[inline(always)]
+    pub fn enable(&self) -> ENABLE_R {
+        ENABLE_R::new((self.bits & 3) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:1 - CCM enable."]
+    #[inline(always)]
+    pub fn enable(&mut self) -> ENABLE_W<0> {
+        ENABLE_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "CCM enable.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [enable](index.html) module"]
+pub struct ENABLE_SPEC;
+impl crate::RegisterSpec for ENABLE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [enable::R](R) reader structure"]
+impl crate::Readable for ENABLE_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [enable::W](W) writer structure"]
+impl crate::Writable for ENABLE_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets ENABLE to value 0"]
+impl crate::Resettable for ENABLE_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/ccm/events_endcrypt.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `EVENTS_ENDCRYPT` reader"]
+pub struct R(crate::R<EVENTS_ENDCRYPT_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<EVENTS_ENDCRYPT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<EVENTS_ENDCRYPT_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<EVENTS_ENDCRYPT_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `EVENTS_ENDCRYPT` writer"]
+pub struct W(crate::W<EVENTS_ENDCRYPT_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<EVENTS_ENDCRYPT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<EVENTS_ENDCRYPT_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<EVENTS_ENDCRYPT_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Encrypt/decrypt completed.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_endcrypt](index.html) module"]
+pub struct EVENTS_ENDCRYPT_SPEC;
+impl crate::RegisterSpec for EVENTS_ENDCRYPT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [events_endcrypt::R](R) reader structure"]
+impl crate::Readable for EVENTS_ENDCRYPT_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [events_endcrypt::W](W) writer structure"]
+impl crate::Writable for EVENTS_ENDCRYPT_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets EVENTS_ENDCRYPT to value 0"]
+impl crate::Resettable for EVENTS_ENDCRYPT_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/ccm/events_endksgen.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `EVENTS_ENDKSGEN` reader"]
+pub struct R(crate::R<EVENTS_ENDKSGEN_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<EVENTS_ENDKSGEN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<EVENTS_ENDKSGEN_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<EVENTS_ENDKSGEN_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `EVENTS_ENDKSGEN` writer"]
+pub struct W(crate::W<EVENTS_ENDKSGEN_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<EVENTS_ENDKSGEN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<EVENTS_ENDKSGEN_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<EVENTS_ENDKSGEN_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Keystream generation completed.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_endksgen](index.html) module"]
+pub struct EVENTS_ENDKSGEN_SPEC;
+impl crate::RegisterSpec for EVENTS_ENDKSGEN_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [events_endksgen::R](R) reader structure"]
+impl crate::Readable for EVENTS_ENDKSGEN_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [events_endksgen::W](W) writer structure"]
+impl crate::Writable for EVENTS_ENDKSGEN_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets EVENTS_ENDKSGEN to value 0"]
+impl crate::Resettable for EVENTS_ENDKSGEN_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/ccm/events_error.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `EVENTS_ERROR` reader"]
+pub struct R(crate::R<EVENTS_ERROR_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<EVENTS_ERROR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<EVENTS_ERROR_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<EVENTS_ERROR_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `EVENTS_ERROR` writer"]
+pub struct W(crate::W<EVENTS_ERROR_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<EVENTS_ERROR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<EVENTS_ERROR_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<EVENTS_ERROR_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Error happened.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_error](index.html) module"]
+pub struct EVENTS_ERROR_SPEC;
+impl crate::RegisterSpec for EVENTS_ERROR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [events_error::R](R) reader structure"]
+impl crate::Readable for EVENTS_ERROR_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [events_error::W](W) writer structure"]
+impl crate::Writable for EVENTS_ERROR_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets EVENTS_ERROR to value 0"]
+impl crate::Resettable for EVENTS_ERROR_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/ccm/inptr.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `INPTR` reader"]
+pub struct R(crate::R<INPTR_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<INPTR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<INPTR_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<INPTR_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `INPTR` writer"]
+pub struct W(crate::W<INPTR_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<INPTR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<INPTR_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<INPTR_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Pointer to the input packet.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [inptr](index.html) module"]
+pub struct INPTR_SPEC;
+impl crate::RegisterSpec for INPTR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [inptr::R](R) reader structure"]
+impl crate::Readable for INPTR_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [inptr::W](W) writer structure"]
+impl crate::Writable for INPTR_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets INPTR to value 0"]
+impl crate::Resettable for INPTR_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/ccm/intenclr.rs

@@ -0,0 +1,267 @@
+#[doc = "Register `INTENCLR` reader"]
+pub struct R(crate::R<INTENCLR_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<INTENCLR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<INTENCLR_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<INTENCLR_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `INTENCLR` writer"]
+pub struct W(crate::W<INTENCLR_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<INTENCLR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<INTENCLR_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<INTENCLR_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `ENDKSGEN` reader - Disable interrupt on ENDKSGEN event."]
+pub type ENDKSGEN_R = crate::BitReader<ENDKSGEN_A>;
+#[doc = "Disable interrupt on ENDKSGEN event.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ENDKSGEN_A {
+    #[doc = "0: Interrupt disabled."]
+    DISABLED = 0,
+    #[doc = "1: Interrupt enabled."]
+    ENABLED = 1,
+}
+impl From<ENDKSGEN_A> for bool {
+    #[inline(always)]
+    fn from(variant: ENDKSGEN_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl ENDKSGEN_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> ENDKSGEN_A {
+        match self.bits {
+            false => ENDKSGEN_A::DISABLED,
+            true => ENDKSGEN_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == ENDKSGEN_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == ENDKSGEN_A::ENABLED
+    }
+}
+#[doc = "Disable interrupt on ENDKSGEN event.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ENDKSGEN_AW {
+    #[doc = "1: Disable interrupt on write."]
+    CLEAR = 1,
+}
+impl From<ENDKSGEN_AW> for bool {
+    #[inline(always)]
+    fn from(variant: ENDKSGEN_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `ENDKSGEN` writer - Disable interrupt on ENDKSGEN event."]
+pub type ENDKSGEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, ENDKSGEN_AW, O>;
+impl<'a, const O: u8> ENDKSGEN_W<'a, O> {
+    #[doc = "Disable interrupt on write."]
+    #[inline(always)]
+    pub fn clear(self) -> &'a mut W {
+        self.variant(ENDKSGEN_AW::CLEAR)
+    }
+}
+#[doc = "Field `ENDCRYPT` reader - Disable interrupt on ENDCRYPT event."]
+pub type ENDCRYPT_R = crate::BitReader<ENDCRYPT_A>;
+#[doc = "Disable interrupt on ENDCRYPT event.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ENDCRYPT_A {
+    #[doc = "0: Interrupt disabled."]
+    DISABLED = 0,
+    #[doc = "1: Interrupt enabled."]
+    ENABLED = 1,
+}
+impl From<ENDCRYPT_A> for bool {
+    #[inline(always)]
+    fn from(variant: ENDCRYPT_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl ENDCRYPT_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> ENDCRYPT_A {
+        match self.bits {
+            false => ENDCRYPT_A::DISABLED,
+            true => ENDCRYPT_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == ENDCRYPT_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == ENDCRYPT_A::ENABLED
+    }
+}
+#[doc = "Disable interrupt on ENDCRYPT event.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ENDCRYPT_AW {
+    #[doc = "1: Disable interrupt on write."]
+    CLEAR = 1,
+}
+impl From<ENDCRYPT_AW> for bool {
+    #[inline(always)]
+    fn from(variant: ENDCRYPT_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `ENDCRYPT` writer - Disable interrupt on ENDCRYPT event."]
+pub type ENDCRYPT_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, ENDCRYPT_AW, O>;
+impl<'a, const O: u8> ENDCRYPT_W<'a, O> {
+    #[doc = "Disable interrupt on write."]
+    #[inline(always)]
+    pub fn clear(self) -> &'a mut W {
+        self.variant(ENDCRYPT_AW::CLEAR)
+    }
+}
+#[doc = "Field `ERROR` reader - Disable interrupt on ERROR event."]
+pub type ERROR_R = crate::BitReader<ERROR_A>;
+#[doc = "Disable interrupt on ERROR event.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ERROR_A {
+    #[doc = "0: Interrupt disabled."]
+    DISABLED = 0,
+    #[doc = "1: Interrupt enabled."]
+    ENABLED = 1,
+}
+impl From<ERROR_A> for bool {
+    #[inline(always)]
+    fn from(variant: ERROR_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl ERROR_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> ERROR_A {
+        match self.bits {
+            false => ERROR_A::DISABLED,
+            true => ERROR_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == ERROR_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == ERROR_A::ENABLED
+    }
+}
+#[doc = "Disable interrupt on ERROR event.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ERROR_AW {
+    #[doc = "1: Disable interrupt on write."]
+    CLEAR = 1,
+}
+impl From<ERROR_AW> for bool {
+    #[inline(always)]
+    fn from(variant: ERROR_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `ERROR` writer - Disable interrupt on ERROR event."]
+pub type ERROR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, ERROR_AW, O>;
+impl<'a, const O: u8> ERROR_W<'a, O> {
+    #[doc = "Disable interrupt on write."]
+    #[inline(always)]
+    pub fn clear(self) -> &'a mut W {
+        self.variant(ERROR_AW::CLEAR)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Disable interrupt on ENDKSGEN event."]
+    #[inline(always)]
+    pub fn endksgen(&self) -> ENDKSGEN_R {
+        ENDKSGEN_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Disable interrupt on ENDCRYPT event."]
+    #[inline(always)]
+    pub fn endcrypt(&self) -> ENDCRYPT_R {
+        ENDCRYPT_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Disable interrupt on ERROR event."]
+    #[inline(always)]
+    pub fn error(&self) -> ERROR_R {
+        ERROR_R::new(((self.bits >> 2) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Disable interrupt on ENDKSGEN event."]
+    #[inline(always)]
+    pub fn endksgen(&mut self) -> ENDKSGEN_W<0> {
+        ENDKSGEN_W::new(self)
+    }
+    #[doc = "Bit 1 - Disable interrupt on ENDCRYPT event."]
+    #[inline(always)]
+    pub fn endcrypt(&mut self) -> ENDCRYPT_W<1> {
+        ENDCRYPT_W::new(self)
+    }
+    #[doc = "Bit 2 - Disable interrupt on ERROR event."]
+    #[inline(always)]
+    pub fn error(&mut self) -> ERROR_W<2> {
+        ERROR_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Interrupt enable clear register.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"]
+pub struct INTENCLR_SPEC;
+impl crate::RegisterSpec for INTENCLR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [intenclr::R](R) reader structure"]
+impl crate::Readable for INTENCLR_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"]
+impl crate::Writable for INTENCLR_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets INTENCLR to value 0"]
+impl crate::Resettable for INTENCLR_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/ccm/intenset.rs

@@ -0,0 +1,267 @@
+#[doc = "Register `INTENSET` reader"]
+pub struct R(crate::R<INTENSET_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<INTENSET_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<INTENSET_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<INTENSET_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `INTENSET` writer"]
+pub struct W(crate::W<INTENSET_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<INTENSET_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<INTENSET_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<INTENSET_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `ENDKSGEN` reader - Enable interrupt on ENDKSGEN event."]
+pub type ENDKSGEN_R = crate::BitReader<ENDKSGEN_A>;
+#[doc = "Enable interrupt on ENDKSGEN event.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ENDKSGEN_A {
+    #[doc = "0: Interrupt disabled."]
+    DISABLED = 0,
+    #[doc = "1: Interrupt enabled."]
+    ENABLED = 1,
+}
+impl From<ENDKSGEN_A> for bool {
+    #[inline(always)]
+    fn from(variant: ENDKSGEN_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl ENDKSGEN_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> ENDKSGEN_A {
+        match self.bits {
+            false => ENDKSGEN_A::DISABLED,
+            true => ENDKSGEN_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == ENDKSGEN_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == ENDKSGEN_A::ENABLED
+    }
+}
+#[doc = "Enable interrupt on ENDKSGEN event.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ENDKSGEN_AW {
+    #[doc = "1: Enable interrupt on write."]
+    SET = 1,
+}
+impl From<ENDKSGEN_AW> for bool {
+    #[inline(always)]
+    fn from(variant: ENDKSGEN_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `ENDKSGEN` writer - Enable interrupt on ENDKSGEN event."]
+pub type ENDKSGEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, ENDKSGEN_AW, O>;
+impl<'a, const O: u8> ENDKSGEN_W<'a, O> {
+    #[doc = "Enable interrupt on write."]
+    #[inline(always)]
+    pub fn set(self) -> &'a mut W {
+        self.variant(ENDKSGEN_AW::SET)
+    }
+}
+#[doc = "Field `ENDCRYPT` reader - Enable interrupt on ENDCRYPT event."]
+pub type ENDCRYPT_R = crate::BitReader<ENDCRYPT_A>;
+#[doc = "Enable interrupt on ENDCRYPT event.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ENDCRYPT_A {
+    #[doc = "0: Interrupt disabled."]
+    DISABLED = 0,
+    #[doc = "1: Interrupt enabled."]
+    ENABLED = 1,
+}
+impl From<ENDCRYPT_A> for bool {
+    #[inline(always)]
+    fn from(variant: ENDCRYPT_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl ENDCRYPT_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> ENDCRYPT_A {
+        match self.bits {
+            false => ENDCRYPT_A::DISABLED,
+            true => ENDCRYPT_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == ENDCRYPT_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == ENDCRYPT_A::ENABLED
+    }
+}
+#[doc = "Enable interrupt on ENDCRYPT event.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ENDCRYPT_AW {
+    #[doc = "1: Enable interrupt on write."]
+    SET = 1,
+}
+impl From<ENDCRYPT_AW> for bool {
+    #[inline(always)]
+    fn from(variant: ENDCRYPT_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `ENDCRYPT` writer - Enable interrupt on ENDCRYPT event."]
+pub type ENDCRYPT_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, ENDCRYPT_AW, O>;
+impl<'a, const O: u8> ENDCRYPT_W<'a, O> {
+    #[doc = "Enable interrupt on write."]
+    #[inline(always)]
+    pub fn set(self) -> &'a mut W {
+        self.variant(ENDCRYPT_AW::SET)
+    }
+}
+#[doc = "Field `ERROR` reader - Enable interrupt on ERROR event."]
+pub type ERROR_R = crate::BitReader<ERROR_A>;
+#[doc = "Enable interrupt on ERROR event.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ERROR_A {
+    #[doc = "0: Interrupt disabled."]
+    DISABLED = 0,
+    #[doc = "1: Interrupt enabled."]
+    ENABLED = 1,
+}
+impl From<ERROR_A> for bool {
+    #[inline(always)]
+    fn from(variant: ERROR_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl ERROR_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> ERROR_A {
+        match self.bits {
+            false => ERROR_A::DISABLED,
+            true => ERROR_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == ERROR_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == ERROR_A::ENABLED
+    }
+}
+#[doc = "Enable interrupt on ERROR event.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ERROR_AW {
+    #[doc = "1: Enable interrupt on write."]
+    SET = 1,
+}
+impl From<ERROR_AW> for bool {
+    #[inline(always)]
+    fn from(variant: ERROR_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `ERROR` writer - Enable interrupt on ERROR event."]
+pub type ERROR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, ERROR_AW, O>;
+impl<'a, const O: u8> ERROR_W<'a, O> {
+    #[doc = "Enable interrupt on write."]
+    #[inline(always)]
+    pub fn set(self) -> &'a mut W {
+        self.variant(ERROR_AW::SET)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Enable interrupt on ENDKSGEN event."]
+    #[inline(always)]
+    pub fn endksgen(&self) -> ENDKSGEN_R {
+        ENDKSGEN_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Enable interrupt on ENDCRYPT event."]
+    #[inline(always)]
+    pub fn endcrypt(&self) -> ENDCRYPT_R {
+        ENDCRYPT_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Enable interrupt on ERROR event."]
+    #[inline(always)]
+    pub fn error(&self) -> ERROR_R {
+        ERROR_R::new(((self.bits >> 2) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Enable interrupt on ENDKSGEN event."]
+    #[inline(always)]
+    pub fn endksgen(&mut self) -> ENDKSGEN_W<0> {
+        ENDKSGEN_W::new(self)
+    }
+    #[doc = "Bit 1 - Enable interrupt on ENDCRYPT event."]
+    #[inline(always)]
+    pub fn endcrypt(&mut self) -> ENDCRYPT_W<1> {
+        ENDCRYPT_W::new(self)
+    }
+    #[doc = "Bit 2 - Enable interrupt on ERROR event."]
+    #[inline(always)]
+    pub fn error(&mut self) -> ERROR_W<2> {
+        ERROR_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Interrupt enable set register.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"]
+pub struct INTENSET_SPEC;
+impl crate::RegisterSpec for INTENSET_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [intenset::R](R) reader structure"]
+impl crate::Readable for INTENSET_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"]
+impl crate::Writable for INTENSET_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets INTENSET to value 0"]
+impl crate::Resettable for INTENSET_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/ccm/micstatus.rs

@@ -0,0 +1,74 @@
+#[doc = "Register `MICSTATUS` reader"]
+pub struct R(crate::R<MICSTATUS_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<MICSTATUS_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<MICSTATUS_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<MICSTATUS_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `MICSTATUS` reader - Result of the MIC check performed during the previous CCM RX STARTCRYPT"]
+pub type MICSTATUS_R = crate::BitReader<MICSTATUS_A>;
+#[doc = "Result of the MIC check performed during the previous CCM RX STARTCRYPT\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum MICSTATUS_A {
+    #[doc = "0: MIC check failed."]
+    CHECK_FAILED = 0,
+    #[doc = "1: MIC check passed."]
+    CHECK_PASSED = 1,
+}
+impl From<MICSTATUS_A> for bool {
+    #[inline(always)]
+    fn from(variant: MICSTATUS_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl MICSTATUS_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> MICSTATUS_A {
+        match self.bits {
+            false => MICSTATUS_A::CHECK_FAILED,
+            true => MICSTATUS_A::CHECK_PASSED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CHECK_FAILED`"]
+    #[inline(always)]
+    pub fn is_check_failed(&self) -> bool {
+        *self == MICSTATUS_A::CHECK_FAILED
+    }
+    #[doc = "Checks if the value of the field is `CHECK_PASSED`"]
+    #[inline(always)]
+    pub fn is_check_passed(&self) -> bool {
+        *self == MICSTATUS_A::CHECK_PASSED
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Result of the MIC check performed during the previous CCM RX STARTCRYPT"]
+    #[inline(always)]
+    pub fn micstatus(&self) -> MICSTATUS_R {
+        MICSTATUS_R::new((self.bits & 1) != 0)
+    }
+}
+#[doc = "CCM RX MIC check result.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [micstatus](index.html) module"]
+pub struct MICSTATUS_SPEC;
+impl crate::RegisterSpec for MICSTATUS_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [micstatus::R](R) reader structure"]
+impl crate::Readable for MICSTATUS_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets MICSTATUS to value 0"]
+impl crate::Resettable for MICSTATUS_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/ccm/mode.rs

@@ -0,0 +1,126 @@
+#[doc = "Register `MODE` reader"]
+pub struct R(crate::R<MODE_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<MODE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<MODE_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<MODE_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `MODE` writer"]
+pub struct W(crate::W<MODE_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<MODE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<MODE_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<MODE_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `MODE` reader - CCM mode operation."]
+pub type MODE_R = crate::BitReader<MODE_A>;
+#[doc = "CCM mode operation.\n\nValue on reset: 1"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum MODE_A {
+    #[doc = "0: CCM mode TX"]
+    ENCRYPTION = 0,
+    #[doc = "1: CCM mode TX"]
+    DECRYPTION = 1,
+}
+impl From<MODE_A> for bool {
+    #[inline(always)]
+    fn from(variant: MODE_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl MODE_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> MODE_A {
+        match self.bits {
+            false => MODE_A::ENCRYPTION,
+            true => MODE_A::DECRYPTION,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ENCRYPTION`"]
+    #[inline(always)]
+    pub fn is_encryption(&self) -> bool {
+        *self == MODE_A::ENCRYPTION
+    }
+    #[doc = "Checks if the value of the field is `DECRYPTION`"]
+    #[inline(always)]
+    pub fn is_decryption(&self) -> bool {
+        *self == MODE_A::DECRYPTION
+    }
+}
+#[doc = "Field `MODE` writer - CCM mode operation."]
+pub type MODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, MODE_SPEC, MODE_A, O>;
+impl<'a, const O: u8> MODE_W<'a, O> {
+    #[doc = "CCM mode TX"]
+    #[inline(always)]
+    pub fn encryption(self) -> &'a mut W {
+        self.variant(MODE_A::ENCRYPTION)
+    }
+    #[doc = "CCM mode TX"]
+    #[inline(always)]
+    pub fn decryption(self) -> &'a mut W {
+        self.variant(MODE_A::DECRYPTION)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - CCM mode operation."]
+    #[inline(always)]
+    pub fn mode(&self) -> MODE_R {
+        MODE_R::new((self.bits & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - CCM mode operation."]
+    #[inline(always)]
+    pub fn mode(&mut self) -> MODE_W<0> {
+        MODE_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Operation mode.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mode](index.html) module"]
+pub struct MODE_SPEC;
+impl crate::RegisterSpec for MODE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [mode::R](R) reader structure"]
+impl crate::Readable for MODE_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [mode::W](W) writer structure"]
+impl crate::Writable for MODE_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets MODE to value 0x01"]
+impl crate::Resettable for MODE_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0x01
+    }
+}

vendor/nrf51-pac/src/ccm/outptr.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `OUTPTR` reader"]
+pub struct R(crate::R<OUTPTR_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<OUTPTR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<OUTPTR_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<OUTPTR_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `OUTPTR` writer"]
+pub struct W(crate::W<OUTPTR_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<OUTPTR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<OUTPTR_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<OUTPTR_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Pointer to the output packet.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [outptr](index.html) module"]
+pub struct OUTPTR_SPEC;
+impl crate::RegisterSpec for OUTPTR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [outptr::R](R) reader structure"]
+impl crate::Readable for OUTPTR_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [outptr::W](W) writer structure"]
+impl crate::Writable for OUTPTR_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets OUTPTR to value 0"]
+impl crate::Resettable for OUTPTR_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/ccm/power.rs

@@ -0,0 +1,126 @@
+#[doc = "Register `POWER` reader"]
+pub struct R(crate::R<POWER_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<POWER_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<POWER_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<POWER_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `POWER` writer"]
+pub struct W(crate::W<POWER_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<POWER_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<POWER_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<POWER_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `POWER` reader - Peripheral power control."]
+pub type POWER_R = crate::BitReader<POWER_A>;
+#[doc = "Peripheral power control.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum POWER_A {
+    #[doc = "0: Module power disabled."]
+    DISABLED = 0,
+    #[doc = "1: Module power enabled."]
+    ENABLED = 1,
+}
+impl From<POWER_A> for bool {
+    #[inline(always)]
+    fn from(variant: POWER_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl POWER_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> POWER_A {
+        match self.bits {
+            false => POWER_A::DISABLED,
+            true => POWER_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == POWER_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == POWER_A::ENABLED
+    }
+}
+#[doc = "Field `POWER` writer - Peripheral power control."]
+pub type POWER_W<'a, const O: u8> = crate::BitWriter<'a, u32, POWER_SPEC, POWER_A, O>;
+impl<'a, const O: u8> POWER_W<'a, O> {
+    #[doc = "Module power disabled."]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(POWER_A::DISABLED)
+    }
+    #[doc = "Module power enabled."]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(POWER_A::ENABLED)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Peripheral power control."]
+    #[inline(always)]
+    pub fn power(&self) -> POWER_R {
+        POWER_R::new((self.bits & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Peripheral power control."]
+    #[inline(always)]
+    pub fn power(&mut self) -> POWER_W<0> {
+        POWER_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Peripheral power control.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [power](index.html) module"]
+pub struct POWER_SPEC;
+impl crate::RegisterSpec for POWER_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [power::R](R) reader structure"]
+impl crate::Readable for POWER_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [power::W](W) writer structure"]
+impl crate::Writable for POWER_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets POWER to value 0"]
+impl crate::Resettable for POWER_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/ccm/scratchptr.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `SCRATCHPTR` reader"]
+pub struct R(crate::R<SCRATCHPTR_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<SCRATCHPTR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<SCRATCHPTR_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<SCRATCHPTR_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `SCRATCHPTR` writer"]
+pub struct W(crate::W<SCRATCHPTR_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<SCRATCHPTR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<SCRATCHPTR_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<SCRATCHPTR_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Pointer to a scratch data area used for temporary storage during resolution. A minimum of 43 bytes must be reserved.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scratchptr](index.html) module"]
+pub struct SCRATCHPTR_SPEC;
+impl crate::RegisterSpec for SCRATCHPTR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [scratchptr::R](R) reader structure"]
+impl crate::Readable for SCRATCHPTR_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [scratchptr::W](W) writer structure"]
+impl crate::Writable for SCRATCHPTR_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets SCRATCHPTR to value 0"]
+impl crate::Resettable for SCRATCHPTR_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/ccm/shorts.rs

@@ -0,0 +1,127 @@
+#[doc = "Register `SHORTS` reader"]
+pub struct R(crate::R<SHORTS_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<SHORTS_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<SHORTS_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<SHORTS_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `SHORTS` writer"]
+pub struct W(crate::W<SHORTS_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<SHORTS_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<SHORTS_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<SHORTS_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `ENDKSGEN_CRYPT` reader - Shortcut between ENDKSGEN event and CRYPT task."]
+pub type ENDKSGEN_CRYPT_R = crate::BitReader<ENDKSGEN_CRYPT_A>;
+#[doc = "Shortcut between ENDKSGEN event and CRYPT task.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ENDKSGEN_CRYPT_A {
+    #[doc = "0: Shortcut disabled."]
+    DISABLED = 0,
+    #[doc = "1: Shortcut enabled."]
+    ENABLED = 1,
+}
+impl From<ENDKSGEN_CRYPT_A> for bool {
+    #[inline(always)]
+    fn from(variant: ENDKSGEN_CRYPT_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl ENDKSGEN_CRYPT_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> ENDKSGEN_CRYPT_A {
+        match self.bits {
+            false => ENDKSGEN_CRYPT_A::DISABLED,
+            true => ENDKSGEN_CRYPT_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == ENDKSGEN_CRYPT_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == ENDKSGEN_CRYPT_A::ENABLED
+    }
+}
+#[doc = "Field `ENDKSGEN_CRYPT` writer - Shortcut between ENDKSGEN event and CRYPT task."]
+pub type ENDKSGEN_CRYPT_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, SHORTS_SPEC, ENDKSGEN_CRYPT_A, O>;
+impl<'a, const O: u8> ENDKSGEN_CRYPT_W<'a, O> {
+    #[doc = "Shortcut disabled."]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(ENDKSGEN_CRYPT_A::DISABLED)
+    }
+    #[doc = "Shortcut enabled."]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(ENDKSGEN_CRYPT_A::ENABLED)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Shortcut between ENDKSGEN event and CRYPT task."]
+    #[inline(always)]
+    pub fn endksgen_crypt(&self) -> ENDKSGEN_CRYPT_R {
+        ENDKSGEN_CRYPT_R::new((self.bits & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Shortcut between ENDKSGEN event and CRYPT task."]
+    #[inline(always)]
+    pub fn endksgen_crypt(&mut self) -> ENDKSGEN_CRYPT_W<0> {
+        ENDKSGEN_CRYPT_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Shortcuts for the CCM.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [shorts](index.html) module"]
+pub struct SHORTS_SPEC;
+impl crate::RegisterSpec for SHORTS_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [shorts::R](R) reader structure"]
+impl crate::Readable for SHORTS_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [shorts::W](W) writer structure"]
+impl crate::Writable for SHORTS_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets SHORTS to value 0"]
+impl crate::Resettable for SHORTS_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/ccm/tasks_crypt.rs

@@ -0,0 +1,45 @@
+#[doc = "Register `TASKS_CRYPT` writer"]
+pub struct W(crate::W<TASKS_CRYPT_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<TASKS_CRYPT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<TASKS_CRYPT_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<TASKS_CRYPT_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Start encrypt/decrypt. This operation will stop by itself when completed.\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_crypt](index.html) module"]
+pub struct TASKS_CRYPT_SPEC;
+impl crate::RegisterSpec for TASKS_CRYPT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [tasks_crypt::W](W) writer structure"]
+impl crate::Writable for TASKS_CRYPT_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets TASKS_CRYPT to value 0"]
+impl crate::Resettable for TASKS_CRYPT_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/ccm/tasks_ksgen.rs

@@ -0,0 +1,45 @@
+#[doc = "Register `TASKS_KSGEN` writer"]
+pub struct W(crate::W<TASKS_KSGEN_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<TASKS_KSGEN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<TASKS_KSGEN_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<TASKS_KSGEN_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Start generation of key-stream. This operation will stop by itself when completed.\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_ksgen](index.html) module"]
+pub struct TASKS_KSGEN_SPEC;
+impl crate::RegisterSpec for TASKS_KSGEN_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [tasks_ksgen::W](W) writer structure"]
+impl crate::Writable for TASKS_KSGEN_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets TASKS_KSGEN to value 0"]
+impl crate::Resettable for TASKS_KSGEN_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/ccm/tasks_stop.rs

@@ -0,0 +1,45 @@
+#[doc = "Register `TASKS_STOP` writer"]
+pub struct W(crate::W<TASKS_STOP_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<TASKS_STOP_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<TASKS_STOP_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<TASKS_STOP_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Stop encrypt/decrypt.\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_stop](index.html) module"]
+pub struct TASKS_STOP_SPEC;
+impl crate::RegisterSpec for TASKS_STOP_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [tasks_stop::W](W) writer structure"]
+impl crate::Writable for TASKS_STOP_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets TASKS_STOP to value 0"]
+impl crate::Resettable for TASKS_STOP_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/clock.rs

@@ -0,0 +1,138 @@
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00 - Start HFCLK clock source."]
+    pub tasks_hfclkstart: TASKS_HFCLKSTART,
+    #[doc = "0x04 - Stop HFCLK clock source."]
+    pub tasks_hfclkstop: TASKS_HFCLKSTOP,
+    #[doc = "0x08 - Start LFCLK clock source."]
+    pub tasks_lfclkstart: TASKS_LFCLKSTART,
+    #[doc = "0x0c - Stop LFCLK clock source."]
+    pub tasks_lfclkstop: TASKS_LFCLKSTOP,
+    #[doc = "0x10 - Start calibration of LFCLK RC oscillator."]
+    pub tasks_cal: TASKS_CAL,
+    #[doc = "0x14 - Start calibration timer."]
+    pub tasks_ctstart: TASKS_CTSTART,
+    #[doc = "0x18 - Stop calibration timer."]
+    pub tasks_ctstop: TASKS_CTSTOP,
+    _reserved7: [u8; 0xe4],
+    #[doc = "0x100 - HFCLK oscillator started."]
+    pub events_hfclkstarted: EVENTS_HFCLKSTARTED,
+    #[doc = "0x104 - LFCLK oscillator started."]
+    pub events_lfclkstarted: EVENTS_LFCLKSTARTED,
+    _reserved9: [u8; 0x04],
+    #[doc = "0x10c - Calibration of LFCLK RC oscillator completed."]
+    pub events_done: EVENTS_DONE,
+    #[doc = "0x110 - Calibration timer timeout."]
+    pub events_ctto: EVENTS_CTTO,
+    _reserved11: [u8; 0x01f0],
+    #[doc = "0x304 - Interrupt enable set register."]
+    pub intenset: INTENSET,
+    #[doc = "0x308 - Interrupt enable clear register."]
+    pub intenclr: INTENCLR,
+    _reserved13: [u8; 0xfc],
+    #[doc = "0x408 - Task HFCLKSTART trigger status."]
+    pub hfclkrun: HFCLKRUN,
+    #[doc = "0x40c - High frequency clock status."]
+    pub hfclkstat: HFCLKSTAT,
+    _reserved15: [u8; 0x04],
+    #[doc = "0x414 - Task LFCLKSTART triggered status."]
+    pub lfclkrun: LFCLKRUN,
+    #[doc = "0x418 - Low frequency clock status."]
+    pub lfclkstat: LFCLKSTAT,
+    #[doc = "0x41c - Clock source for the LFCLK clock, set when task LKCLKSTART is triggered."]
+    pub lfclksrccopy: LFCLKSRCCOPY,
+    _reserved18: [u8; 0xf8],
+    #[doc = "0x518 - Clock source for the LFCLK clock."]
+    pub lfclksrc: LFCLKSRC,
+    _reserved19: [u8; 0x1c],
+    #[doc = "0x538 - Calibration timer interval."]
+    pub ctiv: CTIV,
+    _reserved20: [u8; 0x14],
+    #[doc = "0x550 - Crystal frequency."]
+    pub xtalfreq: XTALFREQ,
+}
+#[doc = "TASKS_HFCLKSTART (w) register accessor: an alias for `Reg<TASKS_HFCLKSTART_SPEC>`"]
+pub type TASKS_HFCLKSTART = crate::Reg<tasks_hfclkstart::TASKS_HFCLKSTART_SPEC>;
+#[doc = "Start HFCLK clock source."]
+pub mod tasks_hfclkstart;
+#[doc = "TASKS_HFCLKSTOP (w) register accessor: an alias for `Reg<TASKS_HFCLKSTOP_SPEC>`"]
+pub type TASKS_HFCLKSTOP = crate::Reg<tasks_hfclkstop::TASKS_HFCLKSTOP_SPEC>;
+#[doc = "Stop HFCLK clock source."]
+pub mod tasks_hfclkstop;
+#[doc = "TASKS_LFCLKSTART (w) register accessor: an alias for `Reg<TASKS_LFCLKSTART_SPEC>`"]
+pub type TASKS_LFCLKSTART = crate::Reg<tasks_lfclkstart::TASKS_LFCLKSTART_SPEC>;
+#[doc = "Start LFCLK clock source."]
+pub mod tasks_lfclkstart;
+#[doc = "TASKS_LFCLKSTOP (w) register accessor: an alias for `Reg<TASKS_LFCLKSTOP_SPEC>`"]
+pub type TASKS_LFCLKSTOP = crate::Reg<tasks_lfclkstop::TASKS_LFCLKSTOP_SPEC>;
+#[doc = "Stop LFCLK clock source."]
+pub mod tasks_lfclkstop;
+#[doc = "TASKS_CAL (w) register accessor: an alias for `Reg<TASKS_CAL_SPEC>`"]
+pub type TASKS_CAL = crate::Reg<tasks_cal::TASKS_CAL_SPEC>;
+#[doc = "Start calibration of LFCLK RC oscillator."]
+pub mod tasks_cal;
+#[doc = "TASKS_CTSTART (w) register accessor: an alias for `Reg<TASKS_CTSTART_SPEC>`"]
+pub type TASKS_CTSTART = crate::Reg<tasks_ctstart::TASKS_CTSTART_SPEC>;
+#[doc = "Start calibration timer."]
+pub mod tasks_ctstart;
+#[doc = "TASKS_CTSTOP (w) register accessor: an alias for `Reg<TASKS_CTSTOP_SPEC>`"]
+pub type TASKS_CTSTOP = crate::Reg<tasks_ctstop::TASKS_CTSTOP_SPEC>;
+#[doc = "Stop calibration timer."]
+pub mod tasks_ctstop;
+#[doc = "EVENTS_HFCLKSTARTED (rw) register accessor: an alias for `Reg<EVENTS_HFCLKSTARTED_SPEC>`"]
+pub type EVENTS_HFCLKSTARTED = crate::Reg<events_hfclkstarted::EVENTS_HFCLKSTARTED_SPEC>;
+#[doc = "HFCLK oscillator started."]
+pub mod events_hfclkstarted;
+#[doc = "EVENTS_LFCLKSTARTED (rw) register accessor: an alias for `Reg<EVENTS_LFCLKSTARTED_SPEC>`"]
+pub type EVENTS_LFCLKSTARTED = crate::Reg<events_lfclkstarted::EVENTS_LFCLKSTARTED_SPEC>;
+#[doc = "LFCLK oscillator started."]
+pub mod events_lfclkstarted;
+#[doc = "EVENTS_DONE (rw) register accessor: an alias for `Reg<EVENTS_DONE_SPEC>`"]
+pub type EVENTS_DONE = crate::Reg<events_done::EVENTS_DONE_SPEC>;
+#[doc = "Calibration of LFCLK RC oscillator completed."]
+pub mod events_done;
+#[doc = "EVENTS_CTTO (rw) register accessor: an alias for `Reg<EVENTS_CTTO_SPEC>`"]
+pub type EVENTS_CTTO = crate::Reg<events_ctto::EVENTS_CTTO_SPEC>;
+#[doc = "Calibration timer timeout."]
+pub mod events_ctto;
+#[doc = "INTENSET (rw) register accessor: an alias for `Reg<INTENSET_SPEC>`"]
+pub type INTENSET = crate::Reg<intenset::INTENSET_SPEC>;
+#[doc = "Interrupt enable set register."]
+pub mod intenset;
+#[doc = "INTENCLR (rw) register accessor: an alias for `Reg<INTENCLR_SPEC>`"]
+pub type INTENCLR = crate::Reg<intenclr::INTENCLR_SPEC>;
+#[doc = "Interrupt enable clear register."]
+pub mod intenclr;
+#[doc = "HFCLKRUN (r) register accessor: an alias for `Reg<HFCLKRUN_SPEC>`"]
+pub type HFCLKRUN = crate::Reg<hfclkrun::HFCLKRUN_SPEC>;
+#[doc = "Task HFCLKSTART trigger status."]
+pub mod hfclkrun;
+#[doc = "HFCLKSTAT (r) register accessor: an alias for `Reg<HFCLKSTAT_SPEC>`"]
+pub type HFCLKSTAT = crate::Reg<hfclkstat::HFCLKSTAT_SPEC>;
+#[doc = "High frequency clock status."]
+pub mod hfclkstat;
+#[doc = "LFCLKRUN (r) register accessor: an alias for `Reg<LFCLKRUN_SPEC>`"]
+pub type LFCLKRUN = crate::Reg<lfclkrun::LFCLKRUN_SPEC>;
+#[doc = "Task LFCLKSTART triggered status."]
+pub mod lfclkrun;
+#[doc = "LFCLKSTAT (r) register accessor: an alias for `Reg<LFCLKSTAT_SPEC>`"]
+pub type LFCLKSTAT = crate::Reg<lfclkstat::LFCLKSTAT_SPEC>;
+#[doc = "Low frequency clock status."]
+pub mod lfclkstat;
+#[doc = "LFCLKSRCCOPY (r) register accessor: an alias for `Reg<LFCLKSRCCOPY_SPEC>`"]
+pub type LFCLKSRCCOPY = crate::Reg<lfclksrccopy::LFCLKSRCCOPY_SPEC>;
+#[doc = "Clock source for the LFCLK clock, set when task LKCLKSTART is triggered."]
+pub mod lfclksrccopy;
+#[doc = "LFCLKSRC (rw) register accessor: an alias for `Reg<LFCLKSRC_SPEC>`"]
+pub type LFCLKSRC = crate::Reg<lfclksrc::LFCLKSRC_SPEC>;
+#[doc = "Clock source for the LFCLK clock."]
+pub mod lfclksrc;
+#[doc = "CTIV (rw) register accessor: an alias for `Reg<CTIV_SPEC>`"]
+pub type CTIV = crate::Reg<ctiv::CTIV_SPEC>;
+#[doc = "Calibration timer interval."]
+pub mod ctiv;
+#[doc = "XTALFREQ (rw) register accessor: an alias for `Reg<XTALFREQ_SPEC>`"]
+pub type XTALFREQ = crate::Reg<xtalfreq::XTALFREQ_SPEC>;
+#[doc = "Crystal frequency."]
+pub mod xtalfreq;

vendor/nrf51-pac/src/clock/ctiv.rs

@@ -0,0 +1,80 @@
+#[doc = "Register `CTIV` reader"]
+pub struct R(crate::R<CTIV_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<CTIV_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<CTIV_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<CTIV_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `CTIV` writer"]
+pub struct W(crate::W<CTIV_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<CTIV_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<CTIV_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<CTIV_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `CTIV` reader - Calibration timer interval in 0.25s resolution."]
+pub type CTIV_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `CTIV` writer - Calibration timer interval in 0.25s resolution."]
+pub type CTIV_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTIV_SPEC, u8, u8, 7, O>;
+impl R {
+    #[doc = "Bits 0:6 - Calibration timer interval in 0.25s resolution."]
+    #[inline(always)]
+    pub fn ctiv(&self) -> CTIV_R {
+        CTIV_R::new((self.bits & 0x7f) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:6 - Calibration timer interval in 0.25s resolution."]
+    #[inline(always)]
+    pub fn ctiv(&mut self) -> CTIV_W<0> {
+        CTIV_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Calibration timer interval.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctiv](index.html) module"]
+pub struct CTIV_SPEC;
+impl crate::RegisterSpec for CTIV_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [ctiv::R](R) reader structure"]
+impl crate::Readable for CTIV_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [ctiv::W](W) writer structure"]
+impl crate::Writable for CTIV_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets CTIV to value 0"]
+impl crate::Resettable for CTIV_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/clock/events_ctto.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `EVENTS_CTTO` reader"]
+pub struct R(crate::R<EVENTS_CTTO_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<EVENTS_CTTO_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<EVENTS_CTTO_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<EVENTS_CTTO_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `EVENTS_CTTO` writer"]
+pub struct W(crate::W<EVENTS_CTTO_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<EVENTS_CTTO_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<EVENTS_CTTO_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<EVENTS_CTTO_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Calibration timer timeout.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_ctto](index.html) module"]
+pub struct EVENTS_CTTO_SPEC;
+impl crate::RegisterSpec for EVENTS_CTTO_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [events_ctto::R](R) reader structure"]
+impl crate::Readable for EVENTS_CTTO_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [events_ctto::W](W) writer structure"]
+impl crate::Writable for EVENTS_CTTO_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets EVENTS_CTTO to value 0"]
+impl crate::Resettable for EVENTS_CTTO_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/clock/events_done.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `EVENTS_DONE` reader"]
+pub struct R(crate::R<EVENTS_DONE_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<EVENTS_DONE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<EVENTS_DONE_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<EVENTS_DONE_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `EVENTS_DONE` writer"]
+pub struct W(crate::W<EVENTS_DONE_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<EVENTS_DONE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<EVENTS_DONE_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<EVENTS_DONE_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Calibration of LFCLK RC oscillator completed.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_done](index.html) module"]
+pub struct EVENTS_DONE_SPEC;
+impl crate::RegisterSpec for EVENTS_DONE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [events_done::R](R) reader structure"]
+impl crate::Readable for EVENTS_DONE_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [events_done::W](W) writer structure"]
+impl crate::Writable for EVENTS_DONE_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets EVENTS_DONE to value 0"]
+impl crate::Resettable for EVENTS_DONE_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/clock/events_hfclkstarted.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `EVENTS_HFCLKSTARTED` reader"]
+pub struct R(crate::R<EVENTS_HFCLKSTARTED_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<EVENTS_HFCLKSTARTED_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<EVENTS_HFCLKSTARTED_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<EVENTS_HFCLKSTARTED_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `EVENTS_HFCLKSTARTED` writer"]
+pub struct W(crate::W<EVENTS_HFCLKSTARTED_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<EVENTS_HFCLKSTARTED_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<EVENTS_HFCLKSTARTED_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<EVENTS_HFCLKSTARTED_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "HFCLK oscillator started.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_hfclkstarted](index.html) module"]
+pub struct EVENTS_HFCLKSTARTED_SPEC;
+impl crate::RegisterSpec for EVENTS_HFCLKSTARTED_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [events_hfclkstarted::R](R) reader structure"]
+impl crate::Readable for EVENTS_HFCLKSTARTED_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [events_hfclkstarted::W](W) writer structure"]
+impl crate::Writable for EVENTS_HFCLKSTARTED_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets EVENTS_HFCLKSTARTED to value 0"]
+impl crate::Resettable for EVENTS_HFCLKSTARTED_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/clock/events_lfclkstarted.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `EVENTS_LFCLKSTARTED` reader"]
+pub struct R(crate::R<EVENTS_LFCLKSTARTED_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<EVENTS_LFCLKSTARTED_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<EVENTS_LFCLKSTARTED_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<EVENTS_LFCLKSTARTED_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `EVENTS_LFCLKSTARTED` writer"]
+pub struct W(crate::W<EVENTS_LFCLKSTARTED_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<EVENTS_LFCLKSTARTED_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<EVENTS_LFCLKSTARTED_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<EVENTS_LFCLKSTARTED_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "LFCLK oscillator started.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_lfclkstarted](index.html) module"]
+pub struct EVENTS_LFCLKSTARTED_SPEC;
+impl crate::RegisterSpec for EVENTS_LFCLKSTARTED_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [events_lfclkstarted::R](R) reader structure"]
+impl crate::Readable for EVENTS_LFCLKSTARTED_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [events_lfclkstarted::W](W) writer structure"]
+impl crate::Writable for EVENTS_LFCLKSTARTED_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets EVENTS_LFCLKSTARTED to value 0"]
+impl crate::Resettable for EVENTS_LFCLKSTARTED_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/clock/hfclkrun.rs

@@ -0,0 +1,74 @@
+#[doc = "Register `HFCLKRUN` reader"]
+pub struct R(crate::R<HFCLKRUN_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<HFCLKRUN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<HFCLKRUN_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<HFCLKRUN_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `STATUS` reader - Task HFCLKSTART trigger status."]
+pub type STATUS_R = crate::BitReader<STATUS_A>;
+#[doc = "Task HFCLKSTART trigger status.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum STATUS_A {
+    #[doc = "0: Task HFCLKSTART has not been triggered."]
+    NOT_TRIGGERED = 0,
+    #[doc = "1: Task HFCLKSTART has been triggered."]
+    TRIGGERED = 1,
+}
+impl From<STATUS_A> for bool {
+    #[inline(always)]
+    fn from(variant: STATUS_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl STATUS_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> STATUS_A {
+        match self.bits {
+            false => STATUS_A::NOT_TRIGGERED,
+            true => STATUS_A::TRIGGERED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `NOT_TRIGGERED`"]
+    #[inline(always)]
+    pub fn is_not_triggered(&self) -> bool {
+        *self == STATUS_A::NOT_TRIGGERED
+    }
+    #[doc = "Checks if the value of the field is `TRIGGERED`"]
+    #[inline(always)]
+    pub fn is_triggered(&self) -> bool {
+        *self == STATUS_A::TRIGGERED
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Task HFCLKSTART trigger status."]
+    #[inline(always)]
+    pub fn status(&self) -> STATUS_R {
+        STATUS_R::new((self.bits & 1) != 0)
+    }
+}
+#[doc = "Task HFCLKSTART trigger status.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hfclkrun](index.html) module"]
+pub struct HFCLKRUN_SPEC;
+impl crate::RegisterSpec for HFCLKRUN_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [hfclkrun::R](R) reader structure"]
+impl crate::Readable for HFCLKRUN_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets HFCLKRUN to value 0"]
+impl crate::Resettable for HFCLKRUN_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/clock/hfclkstat.rs

@@ -0,0 +1,115 @@
+#[doc = "Register `HFCLKSTAT` reader"]
+pub struct R(crate::R<HFCLKSTAT_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<HFCLKSTAT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<HFCLKSTAT_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<HFCLKSTAT_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `SRC` reader - Active clock source for the HF clock."]
+pub type SRC_R = crate::BitReader<SRC_A>;
+#[doc = "Active clock source for the HF clock.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SRC_A {
+    #[doc = "0: Internal 16MHz RC oscillator running and generating the HFCLK clock."]
+    RC = 0,
+    #[doc = "1: External 16MHz/32MHz crystal oscillator running and generating the HFCLK clock."]
+    XTAL = 1,
+}
+impl From<SRC_A> for bool {
+    #[inline(always)]
+    fn from(variant: SRC_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl SRC_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> SRC_A {
+        match self.bits {
+            false => SRC_A::RC,
+            true => SRC_A::XTAL,
+        }
+    }
+    #[doc = "Checks if the value of the field is `RC`"]
+    #[inline(always)]
+    pub fn is_rc(&self) -> bool {
+        *self == SRC_A::RC
+    }
+    #[doc = "Checks if the value of the field is `XTAL`"]
+    #[inline(always)]
+    pub fn is_xtal(&self) -> bool {
+        *self == SRC_A::XTAL
+    }
+}
+#[doc = "Field `STATE` reader - State for the HFCLK."]
+pub type STATE_R = crate::BitReader<STATE_A>;
+#[doc = "State for the HFCLK.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum STATE_A {
+    #[doc = "0: HFCLK clock not running."]
+    NOT_RUNNING = 0,
+    #[doc = "1: HFCLK clock running."]
+    RUNNING = 1,
+}
+impl From<STATE_A> for bool {
+    #[inline(always)]
+    fn from(variant: STATE_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl STATE_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> STATE_A {
+        match self.bits {
+            false => STATE_A::NOT_RUNNING,
+            true => STATE_A::RUNNING,
+        }
+    }
+    #[doc = "Checks if the value of the field is `NOT_RUNNING`"]
+    #[inline(always)]
+    pub fn is_not_running(&self) -> bool {
+        *self == STATE_A::NOT_RUNNING
+    }
+    #[doc = "Checks if the value of the field is `RUNNING`"]
+    #[inline(always)]
+    pub fn is_running(&self) -> bool {
+        *self == STATE_A::RUNNING
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Active clock source for the HF clock."]
+    #[inline(always)]
+    pub fn src(&self) -> SRC_R {
+        SRC_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 16 - State for the HFCLK."]
+    #[inline(always)]
+    pub fn state(&self) -> STATE_R {
+        STATE_R::new(((self.bits >> 16) & 1) != 0)
+    }
+}
+#[doc = "High frequency clock status.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hfclkstat](index.html) module"]
+pub struct HFCLKSTAT_SPEC;
+impl crate::RegisterSpec for HFCLKSTAT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [hfclkstat::R](R) reader structure"]
+impl crate::Readable for HFCLKSTAT_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets HFCLKSTAT to value 0"]
+impl crate::Resettable for HFCLKSTAT_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/clock/intenclr.rs

@@ -0,0 +1,336 @@
+#[doc = "Register `INTENCLR` reader"]
+pub struct R(crate::R<INTENCLR_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<INTENCLR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<INTENCLR_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<INTENCLR_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `INTENCLR` writer"]
+pub struct W(crate::W<INTENCLR_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<INTENCLR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<INTENCLR_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<INTENCLR_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `HFCLKSTARTED` reader - Disable interrupt on HFCLKSTARTED event."]
+pub type HFCLKSTARTED_R = crate::BitReader<HFCLKSTARTED_A>;
+#[doc = "Disable interrupt on HFCLKSTARTED event.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum HFCLKSTARTED_A {
+    #[doc = "0: Interrupt disabled."]
+    DISABLED = 0,
+    #[doc = "1: Interrupt enabled."]
+    ENABLED = 1,
+}
+impl From<HFCLKSTARTED_A> for bool {
+    #[inline(always)]
+    fn from(variant: HFCLKSTARTED_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl HFCLKSTARTED_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> HFCLKSTARTED_A {
+        match self.bits {
+            false => HFCLKSTARTED_A::DISABLED,
+            true => HFCLKSTARTED_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == HFCLKSTARTED_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == HFCLKSTARTED_A::ENABLED
+    }
+}
+#[doc = "Disable interrupt on HFCLKSTARTED event.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum HFCLKSTARTED_AW {
+    #[doc = "1: Disable interrupt on write."]
+    CLEAR = 1,
+}
+impl From<HFCLKSTARTED_AW> for bool {
+    #[inline(always)]
+    fn from(variant: HFCLKSTARTED_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `HFCLKSTARTED` writer - Disable interrupt on HFCLKSTARTED event."]
+pub type HFCLKSTARTED_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, INTENCLR_SPEC, HFCLKSTARTED_AW, O>;
+impl<'a, const O: u8> HFCLKSTARTED_W<'a, O> {
+    #[doc = "Disable interrupt on write."]
+    #[inline(always)]
+    pub fn clear(self) -> &'a mut W {
+        self.variant(HFCLKSTARTED_AW::CLEAR)
+    }
+}
+#[doc = "Field `LFCLKSTARTED` reader - Disable interrupt on LFCLKSTARTED event."]
+pub type LFCLKSTARTED_R = crate::BitReader<LFCLKSTARTED_A>;
+#[doc = "Disable interrupt on LFCLKSTARTED event.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum LFCLKSTARTED_A {
+    #[doc = "0: Interrupt disabled."]
+    DISABLED = 0,
+    #[doc = "1: Interrupt enabled."]
+    ENABLED = 1,
+}
+impl From<LFCLKSTARTED_A> for bool {
+    #[inline(always)]
+    fn from(variant: LFCLKSTARTED_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl LFCLKSTARTED_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> LFCLKSTARTED_A {
+        match self.bits {
+            false => LFCLKSTARTED_A::DISABLED,
+            true => LFCLKSTARTED_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == LFCLKSTARTED_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == LFCLKSTARTED_A::ENABLED
+    }
+}
+#[doc = "Disable interrupt on LFCLKSTARTED event.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum LFCLKSTARTED_AW {
+    #[doc = "1: Disable interrupt on write."]
+    CLEAR = 1,
+}
+impl From<LFCLKSTARTED_AW> for bool {
+    #[inline(always)]
+    fn from(variant: LFCLKSTARTED_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `LFCLKSTARTED` writer - Disable interrupt on LFCLKSTARTED event."]
+pub type LFCLKSTARTED_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, INTENCLR_SPEC, LFCLKSTARTED_AW, O>;
+impl<'a, const O: u8> LFCLKSTARTED_W<'a, O> {
+    #[doc = "Disable interrupt on write."]
+    #[inline(always)]
+    pub fn clear(self) -> &'a mut W {
+        self.variant(LFCLKSTARTED_AW::CLEAR)
+    }
+}
+#[doc = "Field `DONE` reader - Disable interrupt on DONE event."]
+pub type DONE_R = crate::BitReader<DONE_A>;
+#[doc = "Disable interrupt on DONE event.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DONE_A {
+    #[doc = "0: Interrupt disabled."]
+    DISABLED = 0,
+    #[doc = "1: Interrupt enabled."]
+    ENABLED = 1,
+}
+impl From<DONE_A> for bool {
+    #[inline(always)]
+    fn from(variant: DONE_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl DONE_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> DONE_A {
+        match self.bits {
+            false => DONE_A::DISABLED,
+            true => DONE_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == DONE_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == DONE_A::ENABLED
+    }
+}
+#[doc = "Disable interrupt on DONE event.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DONE_AW {
+    #[doc = "1: Disable interrupt on write."]
+    CLEAR = 1,
+}
+impl From<DONE_AW> for bool {
+    #[inline(always)]
+    fn from(variant: DONE_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `DONE` writer - Disable interrupt on DONE event."]
+pub type DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, DONE_AW, O>;
+impl<'a, const O: u8> DONE_W<'a, O> {
+    #[doc = "Disable interrupt on write."]
+    #[inline(always)]
+    pub fn clear(self) -> &'a mut W {
+        self.variant(DONE_AW::CLEAR)
+    }
+}
+#[doc = "Field `CTTO` reader - Disable interrupt on CTTO event."]
+pub type CTTO_R = crate::BitReader<CTTO_A>;
+#[doc = "Disable interrupt on CTTO event.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CTTO_A {
+    #[doc = "0: Interrupt disabled."]
+    DISABLED = 0,
+    #[doc = "1: Interrupt enabled."]
+    ENABLED = 1,
+}
+impl From<CTTO_A> for bool {
+    #[inline(always)]
+    fn from(variant: CTTO_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl CTTO_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> CTTO_A {
+        match self.bits {
+            false => CTTO_A::DISABLED,
+            true => CTTO_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == CTTO_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == CTTO_A::ENABLED
+    }
+}
+#[doc = "Disable interrupt on CTTO event.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CTTO_AW {
+    #[doc = "1: Disable interrupt on write."]
+    CLEAR = 1,
+}
+impl From<CTTO_AW> for bool {
+    #[inline(always)]
+    fn from(variant: CTTO_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `CTTO` writer - Disable interrupt on CTTO event."]
+pub type CTTO_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, CTTO_AW, O>;
+impl<'a, const O: u8> CTTO_W<'a, O> {
+    #[doc = "Disable interrupt on write."]
+    #[inline(always)]
+    pub fn clear(self) -> &'a mut W {
+        self.variant(CTTO_AW::CLEAR)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Disable interrupt on HFCLKSTARTED event."]
+    #[inline(always)]
+    pub fn hfclkstarted(&self) -> HFCLKSTARTED_R {
+        HFCLKSTARTED_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Disable interrupt on LFCLKSTARTED event."]
+    #[inline(always)]
+    pub fn lfclkstarted(&self) -> LFCLKSTARTED_R {
+        LFCLKSTARTED_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Disable interrupt on DONE event."]
+    #[inline(always)]
+    pub fn done(&self) -> DONE_R {
+        DONE_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Disable interrupt on CTTO event."]
+    #[inline(always)]
+    pub fn ctto(&self) -> CTTO_R {
+        CTTO_R::new(((self.bits >> 4) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Disable interrupt on HFCLKSTARTED event."]
+    #[inline(always)]
+    pub fn hfclkstarted(&mut self) -> HFCLKSTARTED_W<0> {
+        HFCLKSTARTED_W::new(self)
+    }
+    #[doc = "Bit 1 - Disable interrupt on LFCLKSTARTED event."]
+    #[inline(always)]
+    pub fn lfclkstarted(&mut self) -> LFCLKSTARTED_W<1> {
+        LFCLKSTARTED_W::new(self)
+    }
+    #[doc = "Bit 3 - Disable interrupt on DONE event."]
+    #[inline(always)]
+    pub fn done(&mut self) -> DONE_W<3> {
+        DONE_W::new(self)
+    }
+    #[doc = "Bit 4 - Disable interrupt on CTTO event."]
+    #[inline(always)]
+    pub fn ctto(&mut self) -> CTTO_W<4> {
+        CTTO_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Interrupt enable clear register.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"]
+pub struct INTENCLR_SPEC;
+impl crate::RegisterSpec for INTENCLR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [intenclr::R](R) reader structure"]
+impl crate::Readable for INTENCLR_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"]
+impl crate::Writable for INTENCLR_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets INTENCLR to value 0"]
+impl crate::Resettable for INTENCLR_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/clock/intenset.rs

@@ -0,0 +1,336 @@
+#[doc = "Register `INTENSET` reader"]
+pub struct R(crate::R<INTENSET_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<INTENSET_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<INTENSET_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<INTENSET_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `INTENSET` writer"]
+pub struct W(crate::W<INTENSET_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<INTENSET_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<INTENSET_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<INTENSET_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `HFCLKSTARTED` reader - Enable interrupt on HFCLKSTARTED event."]
+pub type HFCLKSTARTED_R = crate::BitReader<HFCLKSTARTED_A>;
+#[doc = "Enable interrupt on HFCLKSTARTED event.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum HFCLKSTARTED_A {
+    #[doc = "0: Interrupt disabled."]
+    DISABLED = 0,
+    #[doc = "1: Interrupt enabled."]
+    ENABLED = 1,
+}
+impl From<HFCLKSTARTED_A> for bool {
+    #[inline(always)]
+    fn from(variant: HFCLKSTARTED_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl HFCLKSTARTED_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> HFCLKSTARTED_A {
+        match self.bits {
+            false => HFCLKSTARTED_A::DISABLED,
+            true => HFCLKSTARTED_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == HFCLKSTARTED_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == HFCLKSTARTED_A::ENABLED
+    }
+}
+#[doc = "Enable interrupt on HFCLKSTARTED event.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum HFCLKSTARTED_AW {
+    #[doc = "1: Enable interrupt on write."]
+    SET = 1,
+}
+impl From<HFCLKSTARTED_AW> for bool {
+    #[inline(always)]
+    fn from(variant: HFCLKSTARTED_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `HFCLKSTARTED` writer - Enable interrupt on HFCLKSTARTED event."]
+pub type HFCLKSTARTED_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, INTENSET_SPEC, HFCLKSTARTED_AW, O>;
+impl<'a, const O: u8> HFCLKSTARTED_W<'a, O> {
+    #[doc = "Enable interrupt on write."]
+    #[inline(always)]
+    pub fn set(self) -> &'a mut W {
+        self.variant(HFCLKSTARTED_AW::SET)
+    }
+}
+#[doc = "Field `LFCLKSTARTED` reader - Enable interrupt on LFCLKSTARTED event."]
+pub type LFCLKSTARTED_R = crate::BitReader<LFCLKSTARTED_A>;
+#[doc = "Enable interrupt on LFCLKSTARTED event.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum LFCLKSTARTED_A {
+    #[doc = "0: Interrupt disabled."]
+    DISABLED = 0,
+    #[doc = "1: Interrupt enabled."]
+    ENABLED = 1,
+}
+impl From<LFCLKSTARTED_A> for bool {
+    #[inline(always)]
+    fn from(variant: LFCLKSTARTED_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl LFCLKSTARTED_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> LFCLKSTARTED_A {
+        match self.bits {
+            false => LFCLKSTARTED_A::DISABLED,
+            true => LFCLKSTARTED_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == LFCLKSTARTED_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == LFCLKSTARTED_A::ENABLED
+    }
+}
+#[doc = "Enable interrupt on LFCLKSTARTED event.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum LFCLKSTARTED_AW {
+    #[doc = "1: Enable interrupt on write."]
+    SET = 1,
+}
+impl From<LFCLKSTARTED_AW> for bool {
+    #[inline(always)]
+    fn from(variant: LFCLKSTARTED_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `LFCLKSTARTED` writer - Enable interrupt on LFCLKSTARTED event."]
+pub type LFCLKSTARTED_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, INTENSET_SPEC, LFCLKSTARTED_AW, O>;
+impl<'a, const O: u8> LFCLKSTARTED_W<'a, O> {
+    #[doc = "Enable interrupt on write."]
+    #[inline(always)]
+    pub fn set(self) -> &'a mut W {
+        self.variant(LFCLKSTARTED_AW::SET)
+    }
+}
+#[doc = "Field `DONE` reader - Enable interrupt on DONE event."]
+pub type DONE_R = crate::BitReader<DONE_A>;
+#[doc = "Enable interrupt on DONE event.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DONE_A {
+    #[doc = "0: Interrupt disabled."]
+    DISABLED = 0,
+    #[doc = "1: Interrupt enabled."]
+    ENABLED = 1,
+}
+impl From<DONE_A> for bool {
+    #[inline(always)]
+    fn from(variant: DONE_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl DONE_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> DONE_A {
+        match self.bits {
+            false => DONE_A::DISABLED,
+            true => DONE_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == DONE_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == DONE_A::ENABLED
+    }
+}
+#[doc = "Enable interrupt on DONE event.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DONE_AW {
+    #[doc = "1: Enable interrupt on write."]
+    SET = 1,
+}
+impl From<DONE_AW> for bool {
+    #[inline(always)]
+    fn from(variant: DONE_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `DONE` writer - Enable interrupt on DONE event."]
+pub type DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, DONE_AW, O>;
+impl<'a, const O: u8> DONE_W<'a, O> {
+    #[doc = "Enable interrupt on write."]
+    #[inline(always)]
+    pub fn set(self) -> &'a mut W {
+        self.variant(DONE_AW::SET)
+    }
+}
+#[doc = "Field `CTTO` reader - Enable interrupt on CTTO event."]
+pub type CTTO_R = crate::BitReader<CTTO_A>;
+#[doc = "Enable interrupt on CTTO event.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CTTO_A {
+    #[doc = "0: Interrupt disabled."]
+    DISABLED = 0,
+    #[doc = "1: Interrupt enabled."]
+    ENABLED = 1,
+}
+impl From<CTTO_A> for bool {
+    #[inline(always)]
+    fn from(variant: CTTO_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl CTTO_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> CTTO_A {
+        match self.bits {
+            false => CTTO_A::DISABLED,
+            true => CTTO_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == CTTO_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == CTTO_A::ENABLED
+    }
+}
+#[doc = "Enable interrupt on CTTO event.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CTTO_AW {
+    #[doc = "1: Enable interrupt on write."]
+    SET = 1,
+}
+impl From<CTTO_AW> for bool {
+    #[inline(always)]
+    fn from(variant: CTTO_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `CTTO` writer - Enable interrupt on CTTO event."]
+pub type CTTO_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, CTTO_AW, O>;
+impl<'a, const O: u8> CTTO_W<'a, O> {
+    #[doc = "Enable interrupt on write."]
+    #[inline(always)]
+    pub fn set(self) -> &'a mut W {
+        self.variant(CTTO_AW::SET)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Enable interrupt on HFCLKSTARTED event."]
+    #[inline(always)]
+    pub fn hfclkstarted(&self) -> HFCLKSTARTED_R {
+        HFCLKSTARTED_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Enable interrupt on LFCLKSTARTED event."]
+    #[inline(always)]
+    pub fn lfclkstarted(&self) -> LFCLKSTARTED_R {
+        LFCLKSTARTED_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Enable interrupt on DONE event."]
+    #[inline(always)]
+    pub fn done(&self) -> DONE_R {
+        DONE_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Enable interrupt on CTTO event."]
+    #[inline(always)]
+    pub fn ctto(&self) -> CTTO_R {
+        CTTO_R::new(((self.bits >> 4) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Enable interrupt on HFCLKSTARTED event."]
+    #[inline(always)]
+    pub fn hfclkstarted(&mut self) -> HFCLKSTARTED_W<0> {
+        HFCLKSTARTED_W::new(self)
+    }
+    #[doc = "Bit 1 - Enable interrupt on LFCLKSTARTED event."]
+    #[inline(always)]
+    pub fn lfclkstarted(&mut self) -> LFCLKSTARTED_W<1> {
+        LFCLKSTARTED_W::new(self)
+    }
+    #[doc = "Bit 3 - Enable interrupt on DONE event."]
+    #[inline(always)]
+    pub fn done(&mut self) -> DONE_W<3> {
+        DONE_W::new(self)
+    }
+    #[doc = "Bit 4 - Enable interrupt on CTTO event."]
+    #[inline(always)]
+    pub fn ctto(&mut self) -> CTTO_W<4> {
+        CTTO_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Interrupt enable set register.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"]
+pub struct INTENSET_SPEC;
+impl crate::RegisterSpec for INTENSET_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [intenset::R](R) reader structure"]
+impl crate::Readable for INTENSET_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"]
+impl crate::Writable for INTENSET_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets INTENSET to value 0"]
+impl crate::Resettable for INTENSET_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/clock/lfclkrun.rs

@@ -0,0 +1,74 @@
+#[doc = "Register `LFCLKRUN` reader"]
+pub struct R(crate::R<LFCLKRUN_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<LFCLKRUN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<LFCLKRUN_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<LFCLKRUN_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `STATUS` reader - Task LFCLKSTART triggered status."]
+pub type STATUS_R = crate::BitReader<STATUS_A>;
+#[doc = "Task LFCLKSTART triggered status.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum STATUS_A {
+    #[doc = "0: Task LFCLKSTART has not been triggered."]
+    NOT_TRIGGERED = 0,
+    #[doc = "1: Task LFCLKSTART has been triggered."]
+    TRIGGERED = 1,
+}
+impl From<STATUS_A> for bool {
+    #[inline(always)]
+    fn from(variant: STATUS_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl STATUS_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> STATUS_A {
+        match self.bits {
+            false => STATUS_A::NOT_TRIGGERED,
+            true => STATUS_A::TRIGGERED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `NOT_TRIGGERED`"]
+    #[inline(always)]
+    pub fn is_not_triggered(&self) -> bool {
+        *self == STATUS_A::NOT_TRIGGERED
+    }
+    #[doc = "Checks if the value of the field is `TRIGGERED`"]
+    #[inline(always)]
+    pub fn is_triggered(&self) -> bool {
+        *self == STATUS_A::TRIGGERED
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Task LFCLKSTART triggered status."]
+    #[inline(always)]
+    pub fn status(&self) -> STATUS_R {
+        STATUS_R::new((self.bits & 1) != 0)
+    }
+}
+#[doc = "Task LFCLKSTART triggered status.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lfclkrun](index.html) module"]
+pub struct LFCLKRUN_SPEC;
+impl crate::RegisterSpec for LFCLKRUN_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [lfclkrun::R](R) reader structure"]
+impl crate::Readable for LFCLKRUN_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets LFCLKRUN to value 0"]
+impl crate::Resettable for LFCLKRUN_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/clock/lfclksrc.rs

@@ -0,0 +1,141 @@
+#[doc = "Register `LFCLKSRC` reader"]
+pub struct R(crate::R<LFCLKSRC_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<LFCLKSRC_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<LFCLKSRC_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<LFCLKSRC_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `LFCLKSRC` writer"]
+pub struct W(crate::W<LFCLKSRC_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<LFCLKSRC_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<LFCLKSRC_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<LFCLKSRC_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `SRC` reader - Clock source."]
+pub type SRC_R = crate::FieldReader<u8, SRC_A>;
+#[doc = "Clock source.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum SRC_A {
+    #[doc = "0: Internal 32KiHz RC oscillator."]
+    RC = 0,
+    #[doc = "1: External 32KiHz crystal."]
+    XTAL = 1,
+    #[doc = "2: Internal 32KiHz synthesizer from HFCLK system clock."]
+    SYNTH = 2,
+}
+impl From<SRC_A> for u8 {
+    #[inline(always)]
+    fn from(variant: SRC_A) -> Self {
+        variant as _
+    }
+}
+impl SRC_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<SRC_A> {
+        match self.bits {
+            0 => Some(SRC_A::RC),
+            1 => Some(SRC_A::XTAL),
+            2 => Some(SRC_A::SYNTH),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `RC`"]
+    #[inline(always)]
+    pub fn is_rc(&self) -> bool {
+        *self == SRC_A::RC
+    }
+    #[doc = "Checks if the value of the field is `XTAL`"]
+    #[inline(always)]
+    pub fn is_xtal(&self) -> bool {
+        *self == SRC_A::XTAL
+    }
+    #[doc = "Checks if the value of the field is `SYNTH`"]
+    #[inline(always)]
+    pub fn is_synth(&self) -> bool {
+        *self == SRC_A::SYNTH
+    }
+}
+#[doc = "Field `SRC` writer - Clock source."]
+pub type SRC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, LFCLKSRC_SPEC, u8, SRC_A, 2, O>;
+impl<'a, const O: u8> SRC_W<'a, O> {
+    #[doc = "Internal 32KiHz RC oscillator."]
+    #[inline(always)]
+    pub fn rc(self) -> &'a mut W {
+        self.variant(SRC_A::RC)
+    }
+    #[doc = "External 32KiHz crystal."]
+    #[inline(always)]
+    pub fn xtal(self) -> &'a mut W {
+        self.variant(SRC_A::XTAL)
+    }
+    #[doc = "Internal 32KiHz synthesizer from HFCLK system clock."]
+    #[inline(always)]
+    pub fn synth(self) -> &'a mut W {
+        self.variant(SRC_A::SYNTH)
+    }
+}
+impl R {
+    #[doc = "Bits 0:1 - Clock source."]
+    #[inline(always)]
+    pub fn src(&self) -> SRC_R {
+        SRC_R::new((self.bits & 3) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:1 - Clock source."]
+    #[inline(always)]
+    pub fn src(&mut self) -> SRC_W<0> {
+        SRC_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Clock source for the LFCLK clock.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lfclksrc](index.html) module"]
+pub struct LFCLKSRC_SPEC;
+impl crate::RegisterSpec for LFCLKSRC_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [lfclksrc::R](R) reader structure"]
+impl crate::Readable for LFCLKSRC_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [lfclksrc::W](W) writer structure"]
+impl crate::Writable for LFCLKSRC_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets LFCLKSRC to value 0"]
+impl crate::Resettable for LFCLKSRC_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/clock/lfclksrccopy.rs

@@ -0,0 +1,84 @@
+#[doc = "Register `LFCLKSRCCOPY` reader"]
+pub struct R(crate::R<LFCLKSRCCOPY_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<LFCLKSRCCOPY_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<LFCLKSRCCOPY_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<LFCLKSRCCOPY_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `SRC` reader - Clock source for the LFCLK clock, set when task LKCLKSTART is triggered."]
+pub type SRC_R = crate::FieldReader<u8, SRC_A>;
+#[doc = "Clock source for the LFCLK clock, set when task LKCLKSTART is triggered.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum SRC_A {
+    #[doc = "0: Internal 32KiHz RC oscillator."]
+    RC = 0,
+    #[doc = "1: External 32KiHz crystal."]
+    XTAL = 1,
+    #[doc = "2: Internal 32KiHz synthesizer from HFCLK system clock."]
+    SYNTH = 2,
+}
+impl From<SRC_A> for u8 {
+    #[inline(always)]
+    fn from(variant: SRC_A) -> Self {
+        variant as _
+    }
+}
+impl SRC_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<SRC_A> {
+        match self.bits {
+            0 => Some(SRC_A::RC),
+            1 => Some(SRC_A::XTAL),
+            2 => Some(SRC_A::SYNTH),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `RC`"]
+    #[inline(always)]
+    pub fn is_rc(&self) -> bool {
+        *self == SRC_A::RC
+    }
+    #[doc = "Checks if the value of the field is `XTAL`"]
+    #[inline(always)]
+    pub fn is_xtal(&self) -> bool {
+        *self == SRC_A::XTAL
+    }
+    #[doc = "Checks if the value of the field is `SYNTH`"]
+    #[inline(always)]
+    pub fn is_synth(&self) -> bool {
+        *self == SRC_A::SYNTH
+    }
+}
+impl R {
+    #[doc = "Bits 0:1 - Clock source for the LFCLK clock, set when task LKCLKSTART is triggered."]
+    #[inline(always)]
+    pub fn src(&self) -> SRC_R {
+        SRC_R::new((self.bits & 3) as u8)
+    }
+}
+#[doc = "Clock source for the LFCLK clock, set when task LKCLKSTART is triggered.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lfclksrccopy](index.html) module"]
+pub struct LFCLKSRCCOPY_SPEC;
+impl crate::RegisterSpec for LFCLKSRCCOPY_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [lfclksrccopy::R](R) reader structure"]
+impl crate::Readable for LFCLKSRCCOPY_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets LFCLKSRCCOPY to value 0"]
+impl crate::Resettable for LFCLKSRCCOPY_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/clock/lfclkstat.rs

@@ -0,0 +1,125 @@
+#[doc = "Register `LFCLKSTAT` reader"]
+pub struct R(crate::R<LFCLKSTAT_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<LFCLKSTAT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<LFCLKSTAT_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<LFCLKSTAT_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `SRC` reader - Active clock source for the LF clock."]
+pub type SRC_R = crate::FieldReader<u8, SRC_A>;
+#[doc = "Active clock source for the LF clock.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum SRC_A {
+    #[doc = "0: Internal 32KiHz RC oscillator running and generating the LFCLK clock."]
+    RC = 0,
+    #[doc = "1: External 32KiHz crystal oscillator running and generating the LFCLK clock."]
+    XTAL = 1,
+    #[doc = "2: Internal 32KiHz synthesizer from the HFCLK running and generating the LFCLK clock."]
+    SYNTH = 2,
+}
+impl From<SRC_A> for u8 {
+    #[inline(always)]
+    fn from(variant: SRC_A) -> Self {
+        variant as _
+    }
+}
+impl SRC_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<SRC_A> {
+        match self.bits {
+            0 => Some(SRC_A::RC),
+            1 => Some(SRC_A::XTAL),
+            2 => Some(SRC_A::SYNTH),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `RC`"]
+    #[inline(always)]
+    pub fn is_rc(&self) -> bool {
+        *self == SRC_A::RC
+    }
+    #[doc = "Checks if the value of the field is `XTAL`"]
+    #[inline(always)]
+    pub fn is_xtal(&self) -> bool {
+        *self == SRC_A::XTAL
+    }
+    #[doc = "Checks if the value of the field is `SYNTH`"]
+    #[inline(always)]
+    pub fn is_synth(&self) -> bool {
+        *self == SRC_A::SYNTH
+    }
+}
+#[doc = "Field `STATE` reader - State for the LF clock."]
+pub type STATE_R = crate::BitReader<STATE_A>;
+#[doc = "State for the LF clock.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum STATE_A {
+    #[doc = "0: LFCLK clock not running."]
+    NOT_RUNNING = 0,
+    #[doc = "1: LFCLK clock running."]
+    RUNNING = 1,
+}
+impl From<STATE_A> for bool {
+    #[inline(always)]
+    fn from(variant: STATE_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl STATE_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> STATE_A {
+        match self.bits {
+            false => STATE_A::NOT_RUNNING,
+            true => STATE_A::RUNNING,
+        }
+    }
+    #[doc = "Checks if the value of the field is `NOT_RUNNING`"]
+    #[inline(always)]
+    pub fn is_not_running(&self) -> bool {
+        *self == STATE_A::NOT_RUNNING
+    }
+    #[doc = "Checks if the value of the field is `RUNNING`"]
+    #[inline(always)]
+    pub fn is_running(&self) -> bool {
+        *self == STATE_A::RUNNING
+    }
+}
+impl R {
+    #[doc = "Bits 0:1 - Active clock source for the LF clock."]
+    #[inline(always)]
+    pub fn src(&self) -> SRC_R {
+        SRC_R::new((self.bits & 3) as u8)
+    }
+    #[doc = "Bit 16 - State for the LF clock."]
+    #[inline(always)]
+    pub fn state(&self) -> STATE_R {
+        STATE_R::new(((self.bits >> 16) & 1) != 0)
+    }
+}
+#[doc = "Low frequency clock status.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lfclkstat](index.html) module"]
+pub struct LFCLKSTAT_SPEC;
+impl crate::RegisterSpec for LFCLKSTAT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [lfclkstat::R](R) reader structure"]
+impl crate::Readable for LFCLKSTAT_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets LFCLKSTAT to value 0"]
+impl crate::Resettable for LFCLKSTAT_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/clock/tasks_cal.rs

@@ -0,0 +1,45 @@
+#[doc = "Register `TASKS_CAL` writer"]
+pub struct W(crate::W<TASKS_CAL_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<TASKS_CAL_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<TASKS_CAL_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<TASKS_CAL_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Start calibration of LFCLK RC oscillator.\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_cal](index.html) module"]
+pub struct TASKS_CAL_SPEC;
+impl crate::RegisterSpec for TASKS_CAL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [tasks_cal::W](W) writer structure"]
+impl crate::Writable for TASKS_CAL_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets TASKS_CAL to value 0"]
+impl crate::Resettable for TASKS_CAL_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/clock/tasks_ctstart.rs

@@ -0,0 +1,45 @@
+#[doc = "Register `TASKS_CTSTART` writer"]
+pub struct W(crate::W<TASKS_CTSTART_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<TASKS_CTSTART_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<TASKS_CTSTART_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<TASKS_CTSTART_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Start calibration timer.\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_ctstart](index.html) module"]
+pub struct TASKS_CTSTART_SPEC;
+impl crate::RegisterSpec for TASKS_CTSTART_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [tasks_ctstart::W](W) writer structure"]
+impl crate::Writable for TASKS_CTSTART_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets TASKS_CTSTART to value 0"]
+impl crate::Resettable for TASKS_CTSTART_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/clock/tasks_ctstop.rs

@@ -0,0 +1,45 @@
+#[doc = "Register `TASKS_CTSTOP` writer"]
+pub struct W(crate::W<TASKS_CTSTOP_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<TASKS_CTSTOP_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<TASKS_CTSTOP_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<TASKS_CTSTOP_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Stop calibration timer.\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_ctstop](index.html) module"]
+pub struct TASKS_CTSTOP_SPEC;
+impl crate::RegisterSpec for TASKS_CTSTOP_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [tasks_ctstop::W](W) writer structure"]
+impl crate::Writable for TASKS_CTSTOP_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets TASKS_CTSTOP to value 0"]
+impl crate::Resettable for TASKS_CTSTOP_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/clock/tasks_hfclkstart.rs

@@ -0,0 +1,45 @@
+#[doc = "Register `TASKS_HFCLKSTART` writer"]
+pub struct W(crate::W<TASKS_HFCLKSTART_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<TASKS_HFCLKSTART_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<TASKS_HFCLKSTART_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<TASKS_HFCLKSTART_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Start HFCLK clock source.\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_hfclkstart](index.html) module"]
+pub struct TASKS_HFCLKSTART_SPEC;
+impl crate::RegisterSpec for TASKS_HFCLKSTART_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [tasks_hfclkstart::W](W) writer structure"]
+impl crate::Writable for TASKS_HFCLKSTART_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets TASKS_HFCLKSTART to value 0"]
+impl crate::Resettable for TASKS_HFCLKSTART_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/clock/tasks_hfclkstop.rs

@@ -0,0 +1,45 @@
+#[doc = "Register `TASKS_HFCLKSTOP` writer"]
+pub struct W(crate::W<TASKS_HFCLKSTOP_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<TASKS_HFCLKSTOP_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<TASKS_HFCLKSTOP_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<TASKS_HFCLKSTOP_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Stop HFCLK clock source.\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_hfclkstop](index.html) module"]
+pub struct TASKS_HFCLKSTOP_SPEC;
+impl crate::RegisterSpec for TASKS_HFCLKSTOP_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [tasks_hfclkstop::W](W) writer structure"]
+impl crate::Writable for TASKS_HFCLKSTOP_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets TASKS_HFCLKSTOP to value 0"]
+impl crate::Resettable for TASKS_HFCLKSTOP_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/clock/tasks_lfclkstart.rs

@@ -0,0 +1,45 @@
+#[doc = "Register `TASKS_LFCLKSTART` writer"]
+pub struct W(crate::W<TASKS_LFCLKSTART_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<TASKS_LFCLKSTART_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<TASKS_LFCLKSTART_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<TASKS_LFCLKSTART_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Start LFCLK clock source.\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_lfclkstart](index.html) module"]
+pub struct TASKS_LFCLKSTART_SPEC;
+impl crate::RegisterSpec for TASKS_LFCLKSTART_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [tasks_lfclkstart::W](W) writer structure"]
+impl crate::Writable for TASKS_LFCLKSTART_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets TASKS_LFCLKSTART to value 0"]
+impl crate::Resettable for TASKS_LFCLKSTART_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/clock/tasks_lfclkstop.rs

@@ -0,0 +1,45 @@
+#[doc = "Register `TASKS_LFCLKSTOP` writer"]
+pub struct W(crate::W<TASKS_LFCLKSTOP_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<TASKS_LFCLKSTOP_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<TASKS_LFCLKSTOP_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<TASKS_LFCLKSTOP_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Stop LFCLK clock source.\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_lfclkstop](index.html) module"]
+pub struct TASKS_LFCLKSTOP_SPEC;
+impl crate::RegisterSpec for TASKS_LFCLKSTOP_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [tasks_lfclkstop::W](W) writer structure"]
+impl crate::Writable for TASKS_LFCLKSTOP_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets TASKS_LFCLKSTOP to value 0"]
+impl crate::Resettable for TASKS_LFCLKSTOP_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/clock/xtalfreq.rs

@@ -0,0 +1,129 @@
+#[doc = "Register `XTALFREQ` reader"]
+pub struct R(crate::R<XTALFREQ_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<XTALFREQ_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<XTALFREQ_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<XTALFREQ_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `XTALFREQ` writer"]
+pub struct W(crate::W<XTALFREQ_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<XTALFREQ_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<XTALFREQ_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<XTALFREQ_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `XTALFREQ` reader - External Xtal frequency selection."]
+pub type XTALFREQ_R = crate::FieldReader<u8, XTALFREQ_A>;
+#[doc = "External Xtal frequency selection.\n\nValue on reset: 255"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum XTALFREQ_A {
+    #[doc = "255: 16MHz xtal is used as source for the HFCLK oscillator."]
+    _16MHZ = 255,
+    #[doc = "0: 32MHz xtal is used as source for the HFCLK oscillator."]
+    _32MHZ = 0,
+}
+impl From<XTALFREQ_A> for u8 {
+    #[inline(always)]
+    fn from(variant: XTALFREQ_A) -> Self {
+        variant as _
+    }
+}
+impl XTALFREQ_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<XTALFREQ_A> {
+        match self.bits {
+            255 => Some(XTALFREQ_A::_16MHZ),
+            0 => Some(XTALFREQ_A::_32MHZ),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_16MHZ`"]
+    #[inline(always)]
+    pub fn is_16mhz(&self) -> bool {
+        *self == XTALFREQ_A::_16MHZ
+    }
+    #[doc = "Checks if the value of the field is `_32MHZ`"]
+    #[inline(always)]
+    pub fn is_32mhz(&self) -> bool {
+        *self == XTALFREQ_A::_32MHZ
+    }
+}
+#[doc = "Field `XTALFREQ` writer - External Xtal frequency selection."]
+pub type XTALFREQ_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u32, XTALFREQ_SPEC, u8, XTALFREQ_A, 8, O>;
+impl<'a, const O: u8> XTALFREQ_W<'a, O> {
+    #[doc = "16MHz xtal is used as source for the HFCLK oscillator."]
+    #[inline(always)]
+    pub fn _16mhz(self) -> &'a mut W {
+        self.variant(XTALFREQ_A::_16MHZ)
+    }
+    #[doc = "32MHz xtal is used as source for the HFCLK oscillator."]
+    #[inline(always)]
+    pub fn _32mhz(self) -> &'a mut W {
+        self.variant(XTALFREQ_A::_32MHZ)
+    }
+}
+impl R {
+    #[doc = "Bits 0:7 - External Xtal frequency selection."]
+    #[inline(always)]
+    pub fn xtalfreq(&self) -> XTALFREQ_R {
+        XTALFREQ_R::new((self.bits & 0xff) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - External Xtal frequency selection."]
+    #[inline(always)]
+    pub fn xtalfreq(&mut self) -> XTALFREQ_W<0> {
+        XTALFREQ_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Crystal frequency.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xtalfreq](index.html) module"]
+pub struct XTALFREQ_SPEC;
+impl crate::RegisterSpec for XTALFREQ_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [xtalfreq::R](R) reader structure"]
+impl crate::Readable for XTALFREQ_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [xtalfreq::W](W) writer structure"]
+impl crate::Writable for XTALFREQ_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets XTALFREQ to value 0xffff_ffff"]
+impl crate::Resettable for XTALFREQ_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0xffff_ffff
+    }
+}

vendor/nrf51-pac/src/ecb.rs

@@ -0,0 +1,56 @@
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00 - Start ECB block encrypt. If a crypto operation is running, this will not initiate a new encryption and the ERRORECB event will be triggered."]
+    pub tasks_startecb: TASKS_STARTECB,
+    #[doc = "0x04 - Stop current ECB encryption. If a crypto operation is running, this will will trigger the ERRORECB event."]
+    pub tasks_stopecb: TASKS_STOPECB,
+    _reserved2: [u8; 0xf8],
+    #[doc = "0x100 - ECB block encrypt complete."]
+    pub events_endecb: EVENTS_ENDECB,
+    #[doc = "0x104 - ECB block encrypt aborted due to a STOPECB task or due to an error."]
+    pub events_errorecb: EVENTS_ERRORECB,
+    _reserved4: [u8; 0x01fc],
+    #[doc = "0x304 - Interrupt enable set register."]
+    pub intenset: INTENSET,
+    #[doc = "0x308 - Interrupt enable clear register."]
+    pub intenclr: INTENCLR,
+    _reserved6: [u8; 0x01f8],
+    #[doc = "0x504 - ECB block encrypt memory pointer."]
+    pub ecbdataptr: ECBDATAPTR,
+    _reserved7: [u8; 0x0af4],
+    #[doc = "0xffc - Peripheral power control."]
+    pub power: POWER,
+}
+#[doc = "TASKS_STARTECB (w) register accessor: an alias for `Reg<TASKS_STARTECB_SPEC>`"]
+pub type TASKS_STARTECB = crate::Reg<tasks_startecb::TASKS_STARTECB_SPEC>;
+#[doc = "Start ECB block encrypt. If a crypto operation is running, this will not initiate a new encryption and the ERRORECB event will be triggered."]
+pub mod tasks_startecb;
+#[doc = "TASKS_STOPECB (w) register accessor: an alias for `Reg<TASKS_STOPECB_SPEC>`"]
+pub type TASKS_STOPECB = crate::Reg<tasks_stopecb::TASKS_STOPECB_SPEC>;
+#[doc = "Stop current ECB encryption. If a crypto operation is running, this will will trigger the ERRORECB event."]
+pub mod tasks_stopecb;
+#[doc = "EVENTS_ENDECB (rw) register accessor: an alias for `Reg<EVENTS_ENDECB_SPEC>`"]
+pub type EVENTS_ENDECB = crate::Reg<events_endecb::EVENTS_ENDECB_SPEC>;
+#[doc = "ECB block encrypt complete."]
+pub mod events_endecb;
+#[doc = "EVENTS_ERRORECB (rw) register accessor: an alias for `Reg<EVENTS_ERRORECB_SPEC>`"]
+pub type EVENTS_ERRORECB = crate::Reg<events_errorecb::EVENTS_ERRORECB_SPEC>;
+#[doc = "ECB block encrypt aborted due to a STOPECB task or due to an error."]
+pub mod events_errorecb;
+#[doc = "INTENSET (rw) register accessor: an alias for `Reg<INTENSET_SPEC>`"]
+pub type INTENSET = crate::Reg<intenset::INTENSET_SPEC>;
+#[doc = "Interrupt enable set register."]
+pub mod intenset;
+#[doc = "INTENCLR (rw) register accessor: an alias for `Reg<INTENCLR_SPEC>`"]
+pub type INTENCLR = crate::Reg<intenclr::INTENCLR_SPEC>;
+#[doc = "Interrupt enable clear register."]
+pub mod intenclr;
+#[doc = "ECBDATAPTR (rw) register accessor: an alias for `Reg<ECBDATAPTR_SPEC>`"]
+pub type ECBDATAPTR = crate::Reg<ecbdataptr::ECBDATAPTR_SPEC>;
+#[doc = "ECB block encrypt memory pointer."]
+pub mod ecbdataptr;
+#[doc = "POWER (rw) register accessor: an alias for `Reg<POWER_SPEC>`"]
+pub type POWER = crate::Reg<power::POWER_SPEC>;
+#[doc = "Peripheral power control."]
+pub mod power;

vendor/nrf51-pac/src/ecb/ecbdataptr.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `ECBDATAPTR` reader"]
+pub struct R(crate::R<ECBDATAPTR_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<ECBDATAPTR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<ECBDATAPTR_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<ECBDATAPTR_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `ECBDATAPTR` writer"]
+pub struct W(crate::W<ECBDATAPTR_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<ECBDATAPTR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<ECBDATAPTR_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<ECBDATAPTR_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "ECB block encrypt memory pointer.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ecbdataptr](index.html) module"]
+pub struct ECBDATAPTR_SPEC;
+impl crate::RegisterSpec for ECBDATAPTR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [ecbdataptr::R](R) reader structure"]
+impl crate::Readable for ECBDATAPTR_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [ecbdataptr::W](W) writer structure"]
+impl crate::Writable for ECBDATAPTR_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets ECBDATAPTR to value 0"]
+impl crate::Resettable for ECBDATAPTR_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/ecb/events_endecb.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `EVENTS_ENDECB` reader"]
+pub struct R(crate::R<EVENTS_ENDECB_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<EVENTS_ENDECB_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<EVENTS_ENDECB_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<EVENTS_ENDECB_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `EVENTS_ENDECB` writer"]
+pub struct W(crate::W<EVENTS_ENDECB_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<EVENTS_ENDECB_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<EVENTS_ENDECB_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<EVENTS_ENDECB_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "ECB block encrypt complete.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_endecb](index.html) module"]
+pub struct EVENTS_ENDECB_SPEC;
+impl crate::RegisterSpec for EVENTS_ENDECB_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [events_endecb::R](R) reader structure"]
+impl crate::Readable for EVENTS_ENDECB_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [events_endecb::W](W) writer structure"]
+impl crate::Writable for EVENTS_ENDECB_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets EVENTS_ENDECB to value 0"]
+impl crate::Resettable for EVENTS_ENDECB_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/ecb/events_errorecb.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `EVENTS_ERRORECB` reader"]
+pub struct R(crate::R<EVENTS_ERRORECB_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<EVENTS_ERRORECB_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<EVENTS_ERRORECB_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<EVENTS_ERRORECB_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `EVENTS_ERRORECB` writer"]
+pub struct W(crate::W<EVENTS_ERRORECB_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<EVENTS_ERRORECB_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<EVENTS_ERRORECB_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<EVENTS_ERRORECB_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "ECB block encrypt aborted due to a STOPECB task or due to an error.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_errorecb](index.html) module"]
+pub struct EVENTS_ERRORECB_SPEC;
+impl crate::RegisterSpec for EVENTS_ERRORECB_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [events_errorecb::R](R) reader structure"]
+impl crate::Readable for EVENTS_ERRORECB_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [events_errorecb::W](W) writer structure"]
+impl crate::Writable for EVENTS_ERRORECB_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets EVENTS_ERRORECB to value 0"]
+impl crate::Resettable for EVENTS_ERRORECB_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/ecb/intenclr.rs

@@ -0,0 +1,200 @@
+#[doc = "Register `INTENCLR` reader"]
+pub struct R(crate::R<INTENCLR_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<INTENCLR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<INTENCLR_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<INTENCLR_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `INTENCLR` writer"]
+pub struct W(crate::W<INTENCLR_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<INTENCLR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<INTENCLR_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<INTENCLR_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `ENDECB` reader - Disable interrupt on ENDECB event."]
+pub type ENDECB_R = crate::BitReader<ENDECB_A>;
+#[doc = "Disable interrupt on ENDECB event.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ENDECB_A {
+    #[doc = "0: Interrupt disabled."]
+    DISABLED = 0,
+    #[doc = "1: Interrupt enabled."]
+    ENABLED = 1,
+}
+impl From<ENDECB_A> for bool {
+    #[inline(always)]
+    fn from(variant: ENDECB_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl ENDECB_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> ENDECB_A {
+        match self.bits {
+            false => ENDECB_A::DISABLED,
+            true => ENDECB_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == ENDECB_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == ENDECB_A::ENABLED
+    }
+}
+#[doc = "Disable interrupt on ENDECB event.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ENDECB_AW {
+    #[doc = "1: Disable interrupt on write."]
+    CLEAR = 1,
+}
+impl From<ENDECB_AW> for bool {
+    #[inline(always)]
+    fn from(variant: ENDECB_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `ENDECB` writer - Disable interrupt on ENDECB event."]
+pub type ENDECB_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, ENDECB_AW, O>;
+impl<'a, const O: u8> ENDECB_W<'a, O> {
+    #[doc = "Disable interrupt on write."]
+    #[inline(always)]
+    pub fn clear(self) -> &'a mut W {
+        self.variant(ENDECB_AW::CLEAR)
+    }
+}
+#[doc = "Field `ERRORECB` reader - Disable interrupt on ERRORECB event."]
+pub type ERRORECB_R = crate::BitReader<ERRORECB_A>;
+#[doc = "Disable interrupt on ERRORECB event.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ERRORECB_A {
+    #[doc = "0: Interrupt disabled."]
+    DISABLED = 0,
+    #[doc = "1: Interrupt enabled."]
+    ENABLED = 1,
+}
+impl From<ERRORECB_A> for bool {
+    #[inline(always)]
+    fn from(variant: ERRORECB_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl ERRORECB_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> ERRORECB_A {
+        match self.bits {
+            false => ERRORECB_A::DISABLED,
+            true => ERRORECB_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == ERRORECB_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == ERRORECB_A::ENABLED
+    }
+}
+#[doc = "Disable interrupt on ERRORECB event.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ERRORECB_AW {
+    #[doc = "1: Disable interrupt on write."]
+    CLEAR = 1,
+}
+impl From<ERRORECB_AW> for bool {
+    #[inline(always)]
+    fn from(variant: ERRORECB_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `ERRORECB` writer - Disable interrupt on ERRORECB event."]
+pub type ERRORECB_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, ERRORECB_AW, O>;
+impl<'a, const O: u8> ERRORECB_W<'a, O> {
+    #[doc = "Disable interrupt on write."]
+    #[inline(always)]
+    pub fn clear(self) -> &'a mut W {
+        self.variant(ERRORECB_AW::CLEAR)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Disable interrupt on ENDECB event."]
+    #[inline(always)]
+    pub fn endecb(&self) -> ENDECB_R {
+        ENDECB_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Disable interrupt on ERRORECB event."]
+    #[inline(always)]
+    pub fn errorecb(&self) -> ERRORECB_R {
+        ERRORECB_R::new(((self.bits >> 1) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Disable interrupt on ENDECB event."]
+    #[inline(always)]
+    pub fn endecb(&mut self) -> ENDECB_W<0> {
+        ENDECB_W::new(self)
+    }
+    #[doc = "Bit 1 - Disable interrupt on ERRORECB event."]
+    #[inline(always)]
+    pub fn errorecb(&mut self) -> ERRORECB_W<1> {
+        ERRORECB_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Interrupt enable clear register.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"]
+pub struct INTENCLR_SPEC;
+impl crate::RegisterSpec for INTENCLR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [intenclr::R](R) reader structure"]
+impl crate::Readable for INTENCLR_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"]
+impl crate::Writable for INTENCLR_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets INTENCLR to value 0"]
+impl crate::Resettable for INTENCLR_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/ecb/intenset.rs

@@ -0,0 +1,200 @@
+#[doc = "Register `INTENSET` reader"]
+pub struct R(crate::R<INTENSET_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<INTENSET_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<INTENSET_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<INTENSET_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `INTENSET` writer"]
+pub struct W(crate::W<INTENSET_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<INTENSET_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<INTENSET_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<INTENSET_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `ENDECB` reader - Enable interrupt on ENDECB event."]
+pub type ENDECB_R = crate::BitReader<ENDECB_A>;
+#[doc = "Enable interrupt on ENDECB event.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ENDECB_A {
+    #[doc = "0: Interrupt disabled."]
+    DISABLED = 0,
+    #[doc = "1: Interrupt enabled."]
+    ENABLED = 1,
+}
+impl From<ENDECB_A> for bool {
+    #[inline(always)]
+    fn from(variant: ENDECB_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl ENDECB_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> ENDECB_A {
+        match self.bits {
+            false => ENDECB_A::DISABLED,
+            true => ENDECB_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == ENDECB_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == ENDECB_A::ENABLED
+    }
+}
+#[doc = "Enable interrupt on ENDECB event.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ENDECB_AW {
+    #[doc = "1: Enable interrupt on write."]
+    SET = 1,
+}
+impl From<ENDECB_AW> for bool {
+    #[inline(always)]
+    fn from(variant: ENDECB_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `ENDECB` writer - Enable interrupt on ENDECB event."]
+pub type ENDECB_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, ENDECB_AW, O>;
+impl<'a, const O: u8> ENDECB_W<'a, O> {
+    #[doc = "Enable interrupt on write."]
+    #[inline(always)]
+    pub fn set(self) -> &'a mut W {
+        self.variant(ENDECB_AW::SET)
+    }
+}
+#[doc = "Field `ERRORECB` reader - Enable interrupt on ERRORECB event."]
+pub type ERRORECB_R = crate::BitReader<ERRORECB_A>;
+#[doc = "Enable interrupt on ERRORECB event.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ERRORECB_A {
+    #[doc = "0: Interrupt disabled."]
+    DISABLED = 0,
+    #[doc = "1: Interrupt enabled."]
+    ENABLED = 1,
+}
+impl From<ERRORECB_A> for bool {
+    #[inline(always)]
+    fn from(variant: ERRORECB_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl ERRORECB_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> ERRORECB_A {
+        match self.bits {
+            false => ERRORECB_A::DISABLED,
+            true => ERRORECB_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == ERRORECB_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == ERRORECB_A::ENABLED
+    }
+}
+#[doc = "Enable interrupt on ERRORECB event.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ERRORECB_AW {
+    #[doc = "1: Enable interrupt on write."]
+    SET = 1,
+}
+impl From<ERRORECB_AW> for bool {
+    #[inline(always)]
+    fn from(variant: ERRORECB_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `ERRORECB` writer - Enable interrupt on ERRORECB event."]
+pub type ERRORECB_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, ERRORECB_AW, O>;
+impl<'a, const O: u8> ERRORECB_W<'a, O> {
+    #[doc = "Enable interrupt on write."]
+    #[inline(always)]
+    pub fn set(self) -> &'a mut W {
+        self.variant(ERRORECB_AW::SET)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Enable interrupt on ENDECB event."]
+    #[inline(always)]
+    pub fn endecb(&self) -> ENDECB_R {
+        ENDECB_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Enable interrupt on ERRORECB event."]
+    #[inline(always)]
+    pub fn errorecb(&self) -> ERRORECB_R {
+        ERRORECB_R::new(((self.bits >> 1) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Enable interrupt on ENDECB event."]
+    #[inline(always)]
+    pub fn endecb(&mut self) -> ENDECB_W<0> {
+        ENDECB_W::new(self)
+    }
+    #[doc = "Bit 1 - Enable interrupt on ERRORECB event."]
+    #[inline(always)]
+    pub fn errorecb(&mut self) -> ERRORECB_W<1> {
+        ERRORECB_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Interrupt enable set register.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"]
+pub struct INTENSET_SPEC;
+impl crate::RegisterSpec for INTENSET_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [intenset::R](R) reader structure"]
+impl crate::Readable for INTENSET_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"]
+impl crate::Writable for INTENSET_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets INTENSET to value 0"]
+impl crate::Resettable for INTENSET_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/ecb/power.rs

@@ -0,0 +1,126 @@
+#[doc = "Register `POWER` reader"]
+pub struct R(crate::R<POWER_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<POWER_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<POWER_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<POWER_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `POWER` writer"]
+pub struct W(crate::W<POWER_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<POWER_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<POWER_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<POWER_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `POWER` reader - Peripheral power control."]
+pub type POWER_R = crate::BitReader<POWER_A>;
+#[doc = "Peripheral power control.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum POWER_A {
+    #[doc = "0: Module power disabled."]
+    DISABLED = 0,
+    #[doc = "1: Module power enabled."]
+    ENABLED = 1,
+}
+impl From<POWER_A> for bool {
+    #[inline(always)]
+    fn from(variant: POWER_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl POWER_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> POWER_A {
+        match self.bits {
+            false => POWER_A::DISABLED,
+            true => POWER_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == POWER_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == POWER_A::ENABLED
+    }
+}
+#[doc = "Field `POWER` writer - Peripheral power control."]
+pub type POWER_W<'a, const O: u8> = crate::BitWriter<'a, u32, POWER_SPEC, POWER_A, O>;
+impl<'a, const O: u8> POWER_W<'a, O> {
+    #[doc = "Module power disabled."]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(POWER_A::DISABLED)
+    }
+    #[doc = "Module power enabled."]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(POWER_A::ENABLED)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Peripheral power control."]
+    #[inline(always)]
+    pub fn power(&self) -> POWER_R {
+        POWER_R::new((self.bits & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Peripheral power control."]
+    #[inline(always)]
+    pub fn power(&mut self) -> POWER_W<0> {
+        POWER_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Peripheral power control.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [power](index.html) module"]
+pub struct POWER_SPEC;
+impl crate::RegisterSpec for POWER_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [power::R](R) reader structure"]
+impl crate::Readable for POWER_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [power::W](W) writer structure"]
+impl crate::Writable for POWER_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets POWER to value 0"]
+impl crate::Resettable for POWER_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/ecb/tasks_startecb.rs

@@ -0,0 +1,45 @@
+#[doc = "Register `TASKS_STARTECB` writer"]
+pub struct W(crate::W<TASKS_STARTECB_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<TASKS_STARTECB_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<TASKS_STARTECB_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<TASKS_STARTECB_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Start ECB block encrypt. If a crypto operation is running, this will not initiate a new encryption and the ERRORECB event will be triggered.\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_startecb](index.html) module"]
+pub struct TASKS_STARTECB_SPEC;
+impl crate::RegisterSpec for TASKS_STARTECB_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [tasks_startecb::W](W) writer structure"]
+impl crate::Writable for TASKS_STARTECB_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets TASKS_STARTECB to value 0"]
+impl crate::Resettable for TASKS_STARTECB_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/ecb/tasks_stopecb.rs

@@ -0,0 +1,45 @@
+#[doc = "Register `TASKS_STOPECB` writer"]
+pub struct W(crate::W<TASKS_STOPECB_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<TASKS_STOPECB_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<TASKS_STOPECB_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<TASKS_STOPECB_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Stop current ECB encryption. If a crypto operation is running, this will will trigger the ERRORECB event.\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_stopecb](index.html) module"]
+pub struct TASKS_STOPECB_SPEC;
+impl crate::RegisterSpec for TASKS_STOPECB_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [tasks_stopecb::W](W) writer structure"]
+impl crate::Writable for TASKS_STOPECB_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets TASKS_STOPECB to value 0"]
+impl crate::Resettable for TASKS_STOPECB_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf51-pac/src/ficr.rs

@@ -0,0 +1,115 @@
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    _reserved0: [u8; 0x10],
+    #[doc = "0x10 - Code memory page size in bytes."]
+    pub codepagesize: CODEPAGESIZE,
+    #[doc = "0x14 - Code memory size in pages."]
+    pub codesize: CODESIZE,
+    _reserved2: [u8; 0x10],
+    #[doc = "0x28 - Length of code region 0 in bytes."]
+    pub clenr0: CLENR0,
+    #[doc = "0x2c - Pre-programmed factory code present."]
+    pub ppfc: PPFC,
+    _reserved4: [u8; 0x04],
+    #[doc = "0x34 - Number of individualy controllable RAM blocks."]
+    pub numramblock: NUMRAMBLOCK,
+    _reserved_5_sizeramblock: [u8; 0x10],
+    _reserved6: [u8; 0x14],
+    #[doc = "0x5c - Configuration identifier."]
+    pub configid: CONFIGID,
+    #[doc = "0x60..0x68 - Device identifier."]
+    pub deviceid: [DEVICEID; 2],
+    _reserved8: [u8; 0x18],
+    #[doc = "0x80..0x90 - Encryption root."]
+    pub er: [ER; 4],
+    #[doc = "0x90..0xa0 - Identity root."]
+    pub ir: [IR; 4],
+    #[doc = "0xa0 - Device address type."]
+    pub deviceaddrtype: DEVICEADDRTYPE,
+    #[doc = "0xa4..0xac - Device address."]
+    pub deviceaddr: [DEVICEADDR; 2],
+    #[doc = "0xac - Radio calibration override enable."]
+    pub overrideen: OVERRIDEEN,
+    #[doc = "0xb0..0xc4 - Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit mode."]
+    pub nrf_1mbit: [NRF_1MBIT; 5],
+    _reserved14: [u8; 0x28],
+    #[doc = "0xec..0x100 - Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit mode."]
+    pub ble_1mbit: [BLE_1MBIT; 5],
+}
+impl RegisterBlock {
+    #[doc = "0x38..0x48 - Deprecated array of size of RAM block in bytes. This name is kept for backward compatinility purposes. Use SIZERAMBLOCKS instead."]
+    #[inline(always)]
+    pub fn sizeramblock(&self) -> &[SIZERAMBLOCK; 4] {
+        unsafe { &*(((self as *const Self) as *const u8).add(56usize) as *const [SIZERAMBLOCK; 4]) }
+    }
+    #[doc = "0x38 - Size of RAM blocks in bytes."]
+    #[inline(always)]
+    pub fn sizeramblocks(&self) -> &SIZERAMBLOCKS {
+        unsafe { &*(((self as *const Self) as *const u8).add(56usize) as *const SIZERAMBLOCKS) }
+    }
+}
+#[doc = "CODEPAGESIZE (r) register accessor: an alias for `Reg<CODEPAGESIZE_SPEC>`"]
+pub type CODEPAGESIZE = crate::Reg<codepagesize::CODEPAGESIZE_SPEC>;
+#[doc = "Code memory page size in bytes."]
+pub mod codepagesize;
+#[doc = "CODESIZE (r) register accessor: an alias for `Reg<CODESIZE_SPEC>`"]
+pub type CODESIZE = crate::Reg<codesize::CODESIZE_SPEC>;
+#[doc = "Code memory size in pages."]
+pub mod codesize;
+#[doc = "CLENR0 (r) register accessor: an alias for `Reg<CLENR0_SPEC>`"]
+pub type CLENR0 = crate::Reg<clenr0::CLENR0_SPEC>;
+#[doc = "Length of code region 0 in bytes."]
+pub mod clenr0;
+#[doc = "PPFC (r) register accessor: an alias for `Reg<PPFC_SPEC>`"]
+pub type PPFC = crate::Reg<ppfc::PPFC_SPEC>;
+#[doc = "Pre-programmed factory code present."]
+pub mod ppfc;
+#[doc = "NUMRAMBLOCK (r) register accessor: an alias for `Reg<NUMRAMBLOCK_SPEC>`"]
+pub type NUMRAMBLOCK = crate::Reg<numramblock::NUMRAMBLOCK_SPEC>;
+#[doc = "Number of individualy controllable RAM blocks."]
+pub mod numramblock;
+#[doc = "SIZERAMBLOCKS (r) register accessor: an alias for `Reg<SIZERAMBLOCKS_SPEC>`"]
+pub type SIZERAMBLOCKS = crate::Reg<sizeramblocks::SIZERAMBLOCKS_SPEC>;
+#[doc = "Size of RAM blocks in bytes."]
+pub mod sizeramblocks;
+#[doc = "SIZERAMBLOCK (r) register accessor: an alias for `Reg<SIZERAMBLOCK_SPEC>`"]
+pub type SIZERAMBLOCK = crate::Reg<sizeramblock::SIZERAMBLOCK_SPEC>;
+#[doc = "Deprecated array of size of RAM block in bytes. This name is kept for backward compatinility purposes. Use SIZERAMBLOCKS instead."]
+pub mod sizeramblock;
+#[doc = "CONFIGID (r) register accessor: an alias for `Reg<CONFIGID_SPEC>`"]
+pub type CONFIGID = crate::Reg<configid::CONFIGID_SPEC>;
+#[doc = "Configuration identifier."]
+pub mod configid;
+#[doc = "DEVICEID (r) register accessor: an alias for `Reg<DEVICEID_SPEC>`"]
+pub type DEVICEID = crate::Reg<deviceid::DEVICEID_SPEC>;
+#[doc = "Device identifier."]
+pub mod deviceid;
+#[doc = "ER (r) register accessor: an alias for `Reg<ER_SPEC>`"]
+pub type ER = crate::Reg<er::ER_SPEC>;
+#[doc = "Encryption root."]
+pub mod er;
+#[doc = "IR (r) register accessor: an alias for `Reg<IR_SPEC>`"]
+pub type IR = crate::Reg<ir::IR_SPEC>;
+#[doc = "Identity root."]
+pub mod ir;
+#[doc = "DEVICEADDRTYPE (r) register accessor: an alias for `Reg<DEVICEADDRTYPE_SPEC>`"]
+pub type DEVICEADDRTYPE = crate::Reg<deviceaddrtype::DEVICEADDRTYPE_SPEC>;
+#[doc = "Device address type."]
+pub mod deviceaddrtype;
+#[doc = "DEVICEADDR (r) register accessor: an alias for `Reg<DEVICEADDR_SPEC>`"]
+pub type DEVICEADDR = crate::Reg<deviceaddr::DEVICEADDR_SPEC>;
+#[doc = "Device address."]
+pub mod deviceaddr;
+#[doc = "OVERRIDEEN (r) register accessor: an alias for `Reg<OVERRIDEEN_SPEC>`"]
+pub type OVERRIDEEN = crate::Reg<overrideen::OVERRIDEEN_SPEC>;
+#[doc = "Radio calibration override enable."]
+pub mod overrideen;
+#[doc = "NRF_1MBIT (r) register accessor: an alias for `Reg<NRF_1MBIT_SPEC>`"]
+pub type NRF_1MBIT = crate::Reg<nrf_1mbit::NRF_1MBIT_SPEC>;
+#[doc = "Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit mode."]
+pub mod nrf_1mbit;
+#[doc = "BLE_1MBIT (r) register accessor: an alias for `Reg<BLE_1MBIT_SPEC>`"]
+pub type BLE_1MBIT = crate::Reg<ble_1mbit::BLE_1MBIT_SPEC>;
+#[doc = "Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit mode."]
+pub mod ble_1mbit;

vendor/nrf51-pac/src/ficr/ble_1mbit.rs

@@ -0,0 +1,32 @@
+#[doc = "Register `BLE_1MBIT[%s]` reader"]
+pub struct R(crate::R<BLE_1MBIT_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<BLE_1MBIT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<BLE_1MBIT_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<BLE_1MBIT_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit mode.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ble_1mbit](index.html) module"]
+pub struct BLE_1MBIT_SPEC;
+impl crate::RegisterSpec for BLE_1MBIT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [ble_1mbit::R](R) reader structure"]
+impl crate::Readable for BLE_1MBIT_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets BLE_1MBIT[%s]
+to value 0xffff_ffff"]
+impl crate::Resettable for BLE_1MBIT_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0xffff_ffff
+    }
+}

vendor/nrf51-pac/src/ficr/clenr0.rs

@@ -0,0 +1,31 @@
+#[doc = "Register `CLENR0` reader"]
+pub struct R(crate::R<CLENR0_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<CLENR0_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<CLENR0_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<CLENR0_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Length of code region 0 in bytes.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clenr0](index.html) module"]
+pub struct CLENR0_SPEC;
+impl crate::RegisterSpec for CLENR0_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [clenr0::R](R) reader structure"]
+impl crate::Readable for CLENR0_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets CLENR0 to value 0xffff_ffff"]
+impl crate::Resettable for CLENR0_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0xffff_ffff
+    }
+}

vendor/nrf51-pac/src/ficr/codepagesize.rs

@@ -0,0 +1,31 @@
+#[doc = "Register `CODEPAGESIZE` reader"]
+pub struct R(crate::R<CODEPAGESIZE_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<CODEPAGESIZE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<CODEPAGESIZE_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<CODEPAGESIZE_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Code memory page size in bytes.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [codepagesize](index.html) module"]
+pub struct CODEPAGESIZE_SPEC;
+impl crate::RegisterSpec for CODEPAGESIZE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [codepagesize::R](R) reader structure"]
+impl crate::Readable for CODEPAGESIZE_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets CODEPAGESIZE to value 0xffff_ffff"]
+impl crate::Resettable for CODEPAGESIZE_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0xffff_ffff
+    }
+}

vendor/nrf51-pac/src/ficr/codesize.rs

@@ -0,0 +1,31 @@
+#[doc = "Register `CODESIZE` reader"]
+pub struct R(crate::R<CODESIZE_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<CODESIZE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<CODESIZE_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<CODESIZE_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Code memory size in pages.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [codesize](index.html) module"]
+pub struct CODESIZE_SPEC;
+impl crate::RegisterSpec for CODESIZE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [codesize::R](R) reader structure"]
+impl crate::Readable for CODESIZE_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets CODESIZE to value 0xffff_ffff"]
+impl crate::Resettable for CODESIZE_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0xffff_ffff
+    }
+}

vendor/nrf51-pac/src/ficr/configid.rs

@@ -0,0 +1,47 @@
+#[doc = "Register `CONFIGID` reader"]
+pub struct R(crate::R<CONFIGID_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<CONFIGID_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<CONFIGID_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<CONFIGID_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `HWID` reader - Hardware Identification Number."]
+pub type HWID_R = crate::FieldReader<u16, u16>;
+#[doc = "Field `FWID` reader - Firmware Identification Number pre-loaded into the flash."]
+pub type FWID_R = crate::FieldReader<u16, u16>;
+impl R {
+    #[doc = "Bits 0:15 - Hardware Identification Number."]
+    #[inline(always)]
+    pub fn hwid(&self) -> HWID_R {
+        HWID_R::new((self.bits & 0xffff) as u16)
+    }
+    #[doc = "Bits 16:31 - Firmware Identification Number pre-loaded into the flash."]
+    #[inline(always)]
+    pub fn fwid(&self) -> FWID_R {
+        FWID_R::new(((self.bits >> 16) & 0xffff) as u16)
+    }
+}
+#[doc = "Configuration identifier.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [configid](index.html) module"]
+pub struct CONFIGID_SPEC;
+impl crate::RegisterSpec for CONFIGID_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [configid::R](R) reader structure"]
+impl crate::Readable for CONFIGID_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets CONFIGID to value 0xffff_ffff"]
+impl crate::Resettable for CONFIGID_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0xffff_ffff
+    }
+}

vendor/nrf51-pac/src/ficr/deviceaddr.rs

@@ -0,0 +1,32 @@
+#[doc = "Register `DEVICEADDR[%s]` reader"]
+pub struct R(crate::R<DEVICEADDR_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<DEVICEADDR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<DEVICEADDR_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<DEVICEADDR_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Device address.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [deviceaddr](index.html) module"]
+pub struct DEVICEADDR_SPEC;
+impl crate::RegisterSpec for DEVICEADDR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [deviceaddr::R](R) reader structure"]
+impl crate::Readable for DEVICEADDR_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets DEVICEADDR[%s]
+to value 0xffff_ffff"]
+impl crate::Resettable for DEVICEADDR_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0xffff_ffff
+    }
+}

vendor/nrf51-pac/src/ficr/deviceaddrtype.rs

@@ -0,0 +1,74 @@
+#[doc = "Register `DEVICEADDRTYPE` reader"]
+pub struct R(crate::R<DEVICEADDRTYPE_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<DEVICEADDRTYPE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<DEVICEADDRTYPE_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<DEVICEADDRTYPE_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `DEVICEADDRTYPE` reader - Device address type."]
+pub type DEVICEADDRTYPE_R = crate::BitReader<DEVICEADDRTYPE_A>;
+#[doc = "Device address type.\n\nValue on reset: 1"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DEVICEADDRTYPE_A {
+    #[doc = "0: Public address."]
+    PUBLIC = 0,
+    #[doc = "1: Random address."]
+    RANDOM = 1,
+}
+impl From<DEVICEADDRTYPE_A> for bool {
+    #[inline(always)]
+    fn from(variant: DEVICEADDRTYPE_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl DEVICEADDRTYPE_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> DEVICEADDRTYPE_A {
+        match self.bits {
+            false => DEVICEADDRTYPE_A::PUBLIC,
+            true => DEVICEADDRTYPE_A::RANDOM,
+        }
+    }
+    #[doc = "Checks if the value of the field is `PUBLIC`"]
+    #[inline(always)]
+    pub fn is_public(&self) -> bool {
+        *self == DEVICEADDRTYPE_A::PUBLIC
+    }
+    #[doc = "Checks if the value of the field is `RANDOM`"]
+    #[inline(always)]
+    pub fn is_random(&self) -> bool {
+        *self == DEVICEADDRTYPE_A::RANDOM
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Device address type."]
+    #[inline(always)]
+    pub fn deviceaddrtype(&self) -> DEVICEADDRTYPE_R {
+        DEVICEADDRTYPE_R::new((self.bits & 1) != 0)
+    }
+}
+#[doc = "Device address type.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [deviceaddrtype](index.html) module"]
+pub struct DEVICEADDRTYPE_SPEC;
+impl crate::RegisterSpec for DEVICEADDRTYPE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [deviceaddrtype::R](R) reader structure"]
+impl crate::Readable for DEVICEADDRTYPE_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets DEVICEADDRTYPE to value 0xffff_ffff"]
+impl crate::Resettable for DEVICEADDRTYPE_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0xffff_ffff
+    }
+}

vendor/nrf51-pac/src/ficr/deviceid.rs

@@ -0,0 +1,32 @@
+#[doc = "Register `DEVICEID[%s]` reader"]
+pub struct R(crate::R<DEVICEID_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<DEVICEID_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<DEVICEID_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<DEVICEID_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Device identifier.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [deviceid](index.html) module"]
+pub struct DEVICEID_SPEC;
+impl crate::RegisterSpec for DEVICEID_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [deviceid::R](R) reader structure"]
+impl crate::Readable for DEVICEID_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets DEVICEID[%s]
+to value 0xffff_ffff"]
+impl crate::Resettable for DEVICEID_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0xffff_ffff
+    }
+}

vendor/nrf51-pac/src/ficr/er.rs

@@ -0,0 +1,32 @@
+#[doc = "Register `ER[%s]` reader"]
+pub struct R(crate::R<ER_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<ER_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<ER_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<ER_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Encryption root.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [er](index.html) module"]
+pub struct ER_SPEC;
+impl crate::RegisterSpec for ER_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [er::R](R) reader structure"]
+impl crate::Readable for ER_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets ER[%s]
+to value 0xffff_ffff"]
+impl crate::Resettable for ER_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0xffff_ffff
+    }
+}

vendor/nrf51-pac/src/ficr/ir.rs

@@ -0,0 +1,32 @@
+#[doc = "Register `IR[%s]` reader"]
+pub struct R(crate::R<IR_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<IR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<IR_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<IR_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Identity root.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ir](index.html) module"]
+pub struct IR_SPEC;
+impl crate::RegisterSpec for IR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [ir::R](R) reader structure"]
+impl crate::Readable for IR_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets IR[%s]
+to value 0xffff_ffff"]
+impl crate::Resettable for IR_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0xffff_ffff
+    }
+}

vendor/nrf51-pac/src/ficr/nrf_1mbit.rs

@@ -0,0 +1,32 @@
+#[doc = "Register `NRF_1MBIT[%s]` reader"]
+pub struct R(crate::R<NRF_1MBIT_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<NRF_1MBIT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<NRF_1MBIT_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<NRF_1MBIT_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit mode.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [nrf_1mbit](index.html) module"]
+pub struct NRF_1MBIT_SPEC;
+impl crate::RegisterSpec for NRF_1MBIT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [nrf_1mbit::R](R) reader structure"]
+impl crate::Readable for NRF_1MBIT_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets NRF_1MBIT[%s]
+to value 0xffff_ffff"]
+impl crate::Resettable for NRF_1MBIT_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0xffff_ffff
+    }
+}

vendor/nrf51-pac/src/ficr/numramblock.rs

@@ -0,0 +1,31 @@
+#[doc = "Register `NUMRAMBLOCK` reader"]
+pub struct R(crate::R<NUMRAMBLOCK_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<NUMRAMBLOCK_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<NUMRAMBLOCK_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<NUMRAMBLOCK_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Number of individualy controllable RAM blocks.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [numramblock](index.html) module"]
+pub struct NUMRAMBLOCK_SPEC;
+impl crate::RegisterSpec for NUMRAMBLOCK_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [numramblock::R](R) reader structure"]
+impl crate::Readable for NUMRAMBLOCK_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets NUMRAMBLOCK to value 0xffff_ffff"]
+impl crate::Resettable for NUMRAMBLOCK_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0xffff_ffff
+    }
+}

vendor/nrf51-pac/src/ficr/overrideen.rs

@@ -0,0 +1,115 @@
+#[doc = "Register `OVERRIDEEN` reader"]
+pub struct R(crate::R<OVERRIDEEN_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<OVERRIDEEN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<OVERRIDEEN_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<OVERRIDEEN_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `NRF_1MBIT` reader - Override default values for NRF_1Mbit mode."]
+pub type NRF_1MBIT_R = crate::BitReader<NRF_1MBIT_A>;
+#[doc = "Override default values for NRF_1Mbit mode.\n\nValue on reset: 1"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum NRF_1MBIT_A {
+    #[doc = "0: Override the default values for NRF_1Mbit mode."]
+    OVERRIDE = 0,
+    #[doc = "1: Do not override the default values for NRF_1Mbit mode."]
+    NOT_OVERRIDE = 1,
+}
+impl From<NRF_1MBIT_A> for bool {
+    #[inline(always)]
+    fn from(variant: NRF_1MBIT_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl NRF_1MBIT_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> NRF_1MBIT_A {
+        match self.bits {
+            false => NRF_1MBIT_A::OVERRIDE,
+            true => NRF_1MBIT_A::NOT_OVERRIDE,
+        }
+    }
+    #[doc = "Checks if the value of the field is `OVERRIDE`"]
+    #[inline(always)]
+    pub fn is_override(&self) -> bool {
+        *self == NRF_1MBIT_A::OVERRIDE
+    }
+    #[doc = "Checks if the value of the field is `NOT_OVERRIDE`"]
+    #[inline(always)]
+    pub fn is_not_override(&self) -> bool {
+        *self == NRF_1MBIT_A::NOT_OVERRIDE
+    }
+}
+#[doc = "Field `BLE_1MBIT` reader - Override default values for BLE_1Mbit mode."]
+pub type BLE_1MBIT_R = crate::BitReader<BLE_1MBIT_A>;
+#[doc = "Override default values for BLE_1Mbit mode.\n\nValue on reset: 1"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum BLE_1MBIT_A {
+    #[doc = "0: Override the default values for BLE_1Mbit mode."]
+    OVERRIDE = 0,
+    #[doc = "1: Do not override the default values for BLE_1Mbit mode."]
+    NOT_OVERRIDE = 1,
+}
+impl From<BLE_1MBIT_A> for bool {
+    #[inline(always)]
+    fn from(variant: BLE_1MBIT_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl BLE_1MBIT_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> BLE_1MBIT_A {
+        match self.bits {
+            false => BLE_1MBIT_A::OVERRIDE,
+            true => BLE_1MBIT_A::NOT_OVERRIDE,
+        }
+    }
+    #[doc = "Checks if the value of the field is `OVERRIDE`"]
+    #[inline(always)]
+    pub fn is_override(&self) -> bool {
+        *self == BLE_1MBIT_A::OVERRIDE
+    }
+    #[doc = "Checks if the value of the field is `NOT_OVERRIDE`"]
+    #[inline(always)]
+    pub fn is_not_override(&self) -> bool {
+        *self == BLE_1MBIT_A::NOT_OVERRIDE
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Override default values for NRF_1Mbit mode."]
+    #[inline(always)]
+    pub fn nrf_1mbit(&self) -> NRF_1MBIT_R {
+        NRF_1MBIT_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 3 - Override default values for BLE_1Mbit mode."]
+    #[inline(always)]
+    pub fn ble_1mbit(&self) -> BLE_1MBIT_R {
+        BLE_1MBIT_R::new(((self.bits >> 3) & 1) != 0)
+    }
+}
+#[doc = "Radio calibration override enable.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [overrideen](index.html) module"]
+pub struct OVERRIDEEN_SPEC;
+impl crate::RegisterSpec for OVERRIDEEN_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [overrideen::R](R) reader structure"]
+impl crate::Readable for OVERRIDEEN_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets OVERRIDEEN to value 0xffff_ffff"]
+impl crate::Resettable for OVERRIDEEN_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0xffff_ffff
+    }
+}

vendor/nrf51-pac/src/ficr/ppfc.rs

@@ -0,0 +1,76 @@
+#[doc = "Register `PPFC` reader"]
+pub struct R(crate::R<PPFC_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<PPFC_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<PPFC_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<PPFC_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `PPFC` reader - Pre-programmed factory code present."]
+pub type PPFC_R = crate::FieldReader<u8, PPFC_A>;
+#[doc = "Pre-programmed factory code present.\n\nValue on reset: 255"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum PPFC_A {
+    #[doc = "255: Not present."]
+    NOT_PRESENT = 255,
+    #[doc = "0: Present."]
+    PRESENT = 0,
+}
+impl From<PPFC_A> for u8 {
+    #[inline(always)]
+    fn from(variant: PPFC_A) -> Self {
+        variant as _
+    }
+}
+impl PPFC_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<PPFC_A> {
+        match self.bits {
+            255 => Some(PPFC_A::NOT_PRESENT),
+            0 => Some(PPFC_A::PRESENT),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `NOT_PRESENT`"]
+    #[inline(always)]
+    pub fn is_not_present(&self) -> bool {
+        *self == PPFC_A::NOT_PRESENT
+    }
+    #[doc = "Checks if the value of the field is `PRESENT`"]
+    #[inline(always)]
+    pub fn is_present(&self) -> bool {
+        *self == PPFC_A::PRESENT
+    }
+}
+impl R {
+    #[doc = "Bits 0:7 - Pre-programmed factory code present."]
+    #[inline(always)]
+    pub fn ppfc(&self) -> PPFC_R {
+        PPFC_R::new((self.bits & 0xff) as u8)
+    }
+}
+#[doc = "Pre-programmed factory code present.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ppfc](index.html) module"]
+pub struct PPFC_SPEC;
+impl crate::RegisterSpec for PPFC_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [ppfc::R](R) reader structure"]
+impl crate::Readable for PPFC_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets PPFC to value 0xffff_ffff"]
+impl crate::Resettable for PPFC_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0xffff_ffff
+    }
+}

vendor/nrf51-pac/src/ficr/sizeramblock.rs

@@ -0,0 +1,32 @@
+#[doc = "Register `SIZERAMBLOCK[%s]` reader"]
+pub struct R(crate::R<SIZERAMBLOCK_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<SIZERAMBLOCK_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<SIZERAMBLOCK_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<SIZERAMBLOCK_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Deprecated array of size of RAM block in bytes. This name is kept for backward compatinility purposes. Use SIZERAMBLOCKS instead.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sizeramblock](index.html) module"]
+pub struct SIZERAMBLOCK_SPEC;
+impl crate::RegisterSpec for SIZERAMBLOCK_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [sizeramblock::R](R) reader structure"]
+impl crate::Readable for SIZERAMBLOCK_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets SIZERAMBLOCK[%s]
+to value 0xffff_ffff"]
+impl crate::Resettable for SIZERAMBLOCK_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0xffff_ffff
+    }
+}

vendor/nrf51-pac/src/ficr/sizeramblocks.rs

@@ -0,0 +1,31 @@
+#[doc = "Register `SIZERAMBLOCKS` reader"]
+pub struct R(crate::R<SIZERAMBLOCKS_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<SIZERAMBLOCKS_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<SIZERAMBLOCKS_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<SIZERAMBLOCKS_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Size of RAM blocks in bytes.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sizeramblocks](index.html) module"]
+pub struct SIZERAMBLOCKS_SPEC;
+impl crate::RegisterSpec for SIZERAMBLOCKS_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [sizeramblocks::R](R) reader structure"]
+impl crate::Readable for SIZERAMBLOCKS_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets SIZERAMBLOCKS to value 0xffff_ffff"]
+impl crate::Resettable for SIZERAMBLOCKS_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0xffff_ffff
+    }
+}

vendor/nrf51-pac/src/generic.rs

@@ -0,0 +1,573 @@
+use core::marker;
+#[doc = " Raw register type"]
+pub trait RegisterSpec {
+    #[doc = " Raw register type (`u8`, `u16`, `u32`, ...)."]
+    type Ux: Copy;
+}
+#[doc = " Trait implemented by readable registers to enable the `read` method."]
+#[doc = ""]
+#[doc = " Registers marked with `Writable` can be also `modify`'ed."]
+pub trait Readable: RegisterSpec {
+    #[doc = " Result from a call to `read` and argument to `modify`."]
+    type Reader: From<R<Self>> + core::ops::Deref<Target = R<Self>>;
+}
+#[doc = " Trait implemented by writeable registers."]
+#[doc = ""]
+#[doc = " This enables the  `write`, `write_with_zero` and `reset` methods."]
+#[doc = ""]
+#[doc = " Registers marked with `Readable` can be also `modify`'ed."]
+pub trait Writable: RegisterSpec {
+    #[doc = " Writer type argument to `write`, et al."]
+    type Writer: From<W<Self>> + core::ops::DerefMut<Target = W<Self>>;
+}
+#[doc = " Reset value of the register."]
+#[doc = ""]
+#[doc = " This value is the initial value for the `write` method. It can also be directly written to the"]
+#[doc = " register by using the `reset` method."]
+pub trait Resettable: RegisterSpec {
+    #[doc = " Reset value of the register."]
+    fn reset_value() -> Self::Ux;
+}
+#[doc = " This structure provides volatile access to registers."]
+#[repr(transparent)]
+pub struct Reg<REG: RegisterSpec> {
+    register: vcell::VolatileCell<REG::Ux>,
+    _marker: marker::PhantomData<REG>,
+}
+unsafe impl<REG: RegisterSpec> Send for Reg<REG> where REG::Ux: Send {}
+impl<REG: RegisterSpec> Reg<REG> {
+    #[doc = " Returns the underlying memory address of register."]
+    #[doc = ""]
+    #[doc = " ```ignore"]
+    #[doc = " let reg_ptr = periph.reg.as_ptr();"]
+    #[doc = " ```"]
+    #[inline(always)]
+    pub fn as_ptr(&self) -> *mut REG::Ux {
+        self.register.as_ptr()
+    }
+}
+impl<REG: Readable> Reg<REG> {
+    #[doc = " Reads the contents of a `Readable` register."]
+    #[doc = ""]
+    #[doc = " You can read the raw contents of a register by using `bits`:"]
+    #[doc = " ```ignore"]
+    #[doc = " let bits = periph.reg.read().bits();"]
+    #[doc = " ```"]
+    #[doc = " or get the content of a particular field of a register:"]
+    #[doc = " ```ignore"]
+    #[doc = " let reader = periph.reg.read();"]
+    #[doc = " let bits = reader.field1().bits();"]
+    #[doc = " let flag = reader.field2().bit_is_set();"]
+    #[doc = " ```"]
+    #[inline(always)]
+    pub fn read(&self) -> REG::Reader {
+        REG::Reader::from(R {
+            bits: self.register.get(),
+            _reg: marker::PhantomData,
+        })
+    }
+}
+impl<REG: Resettable + Writable> Reg<REG> {
+    #[doc = " Writes the reset value to `Writable` register."]
+    #[doc = ""]
+    #[doc = " Resets the register to its initial state."]
+    #[inline(always)]
+    pub fn reset(&self) {
+        self.register.set(REG::reset_value())
+    }
+    #[doc = " Writes bits to a `Writable` register."]
+    #[doc = ""]
+    #[doc = " You can write raw bits into a register:"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.write(|w| unsafe { w.bits(rawbits) });"]
+    #[doc = " ```"]
+    #[doc = " or write only the fields you need:"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.write(|w| w"]
+    #[doc = "     .field1().bits(newfield1bits)"]
+    #[doc = "     .field2().set_bit()"]
+    #[doc = "     .field3().variant(VARIANT)"]
+    #[doc = " );"]
+    #[doc = " ```"]
+    #[doc = " or an alternative way of saying the same:"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.write(|w| {"]
+    #[doc = "     w.field1().bits(newfield1bits);"]
+    #[doc = "     w.field2().set_bit();"]
+    #[doc = "     w.field3().variant(VARIANT)"]
+    #[doc = " });"]
+    #[doc = " ```"]
+    #[doc = " In the latter case, other fields will be set to their reset value."]
+    #[inline(always)]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut REG::Writer) -> &mut W<REG>,
+    {
+        self.register.set(
+            f(&mut REG::Writer::from(W {
+                bits: REG::reset_value(),
+                _reg: marker::PhantomData,
+            }))
+            .bits,
+        );
+    }
+}
+impl<REG: Writable> Reg<REG>
+where
+    REG::Ux: Default,
+{
+    #[doc = " Writes 0 to a `Writable` register."]
+    #[doc = ""]
+    #[doc = " Similar to `write`, but unused bits will contain 0."]
+    #[inline(always)]
+    pub unsafe fn write_with_zero<F>(&self, f: F)
+    where
+        F: FnOnce(&mut REG::Writer) -> &mut W<REG>,
+    {
+        self.register.set(
+            (*f(&mut REG::Writer::from(W {
+                bits: REG::Ux::default(),
+                _reg: marker::PhantomData,
+            })))
+            .bits,
+        );
+    }
+}
+impl<REG: Readable + Writable> Reg<REG> {
+    #[doc = " Modifies the contents of the register by reading and then writing it."]
+    #[doc = ""]
+    #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.modify(|r, w| unsafe { w.bits("]
+    #[doc = "    r.bits() | 3"]
+    #[doc = " ) });"]
+    #[doc = " ```"]
+    #[doc = " or"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.modify(|_, w| w"]
+    #[doc = "     .field1().bits(newfield1bits)"]
+    #[doc = "     .field2().set_bit()"]
+    #[doc = "     .field3().variant(VARIANT)"]
+    #[doc = " );"]
+    #[doc = " ```"]
+    #[doc = " or an alternative way of saying the same:"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.modify(|_, w| {"]
+    #[doc = "     w.field1().bits(newfield1bits);"]
+    #[doc = "     w.field2().set_bit();"]
+    #[doc = "     w.field3().variant(VARIANT)"]
+    #[doc = " });"]
+    #[doc = " ```"]
+    #[doc = " Other fields will have the value they had before the call to `modify`."]
+    #[inline(always)]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&REG::Reader, &'w mut REG::Writer) -> &'w mut W<REG>,
+    {
+        let bits = self.register.get();
+        self.register.set(
+            f(
+                &REG::Reader::from(R {
+                    bits,
+                    _reg: marker::PhantomData,
+                }),
+                &mut REG::Writer::from(W {
+                    bits,
+                    _reg: marker::PhantomData,
+                }),
+            )
+            .bits,
+        );
+    }
+}
+#[doc = " Register reader."]
+#[doc = ""]
+#[doc = " Result of the `read` methods of registers. Also used as a closure argument in the `modify`"]
+#[doc = " method."]
+pub struct R<REG: RegisterSpec + ?Sized> {
+    pub(crate) bits: REG::Ux,
+    _reg: marker::PhantomData<REG>,
+}
+impl<REG: RegisterSpec> R<REG> {
+    #[doc = " Reads raw bits from register."]
+    #[inline(always)]
+    pub fn bits(&self) -> REG::Ux {
+        self.bits
+    }
+}
+impl<REG: RegisterSpec, FI> PartialEq<FI> for R<REG>
+where
+    REG::Ux: PartialEq,
+    FI: Copy + Into<REG::Ux>,
+{
+    #[inline(always)]
+    fn eq(&self, other: &FI) -> bool {
+        self.bits.eq(&(*other).into())
+    }
+}
+#[doc = " Register writer."]
+#[doc = ""]
+#[doc = " Used as an argument to the closures in the `write` and `modify` methods of the register."]
+pub struct W<REG: RegisterSpec + ?Sized> {
+    #[doc = "Writable bits"]
+    pub(crate) bits: REG::Ux,
+    _reg: marker::PhantomData<REG>,
+}
+impl<REG: RegisterSpec> W<REG> {
+    #[doc = " Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+}
+#[doc(hidden)]
+pub struct FieldReaderRaw<U, T> {
+    pub(crate) bits: U,
+    _reg: marker::PhantomData<T>,
+}
+impl<U, FI> FieldReaderRaw<U, FI>
+where
+    U: Copy,
+{
+    #[doc = " Creates a new instance of the reader."]
+    #[allow(unused)]
+    #[inline(always)]
+    pub(crate) fn new(bits: U) -> Self {
+        Self {
+            bits,
+            _reg: marker::PhantomData,
+        }
+    }
+}
+#[doc(hidden)]
+pub struct BitReaderRaw<T> {
+    pub(crate) bits: bool,
+    _reg: marker::PhantomData<T>,
+}
+impl<FI> BitReaderRaw<FI> {
+    #[doc = " Creates a new instance of the reader."]
+    #[allow(unused)]
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        Self {
+            bits,
+            _reg: marker::PhantomData,
+        }
+    }
+}
+#[doc = " Field reader."]
+#[doc = ""]
+#[doc = " Result of the `read` methods of fields."]
+pub type FieldReader<U, FI> = FieldReaderRaw<U, FI>;
+#[doc = " Bit-wise field reader"]
+pub type BitReader<FI> = BitReaderRaw<FI>;
+impl<U, FI> FieldReader<U, FI>
+where
+    U: Copy,
+{
+    #[doc = " Reads raw bits from field."]
+    #[inline(always)]
+    pub fn bits(&self) -> U {
+        self.bits
+    }
+}
+impl<U, FI> PartialEq<FI> for FieldReader<U, FI>
+where
+    U: PartialEq,
+    FI: Copy + Into<U>,
+{
+    #[inline(always)]
+    fn eq(&self, other: &FI) -> bool {
+        self.bits.eq(&(*other).into())
+    }
+}
+impl<FI> PartialEq<FI> for BitReader<FI>
+where
+    FI: Copy + Into<bool>,
+{
+    #[inline(always)]
+    fn eq(&self, other: &FI) -> bool {
+        self.bits.eq(&(*other).into())
+    }
+}
+impl<FI> BitReader<FI> {
+    #[doc = " Value of the field as raw bits."]
+    #[inline(always)]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = " Returns `true` if the bit is clear (0)."]
+    #[inline(always)]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = " Returns `true` if the bit is set (1)."]
+    #[inline(always)]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc(hidden)]
+pub struct Safe;
+#[doc(hidden)]
+pub struct Unsafe;
+#[doc(hidden)]
+pub struct FieldWriterRaw<'a, U, REG, N, FI, Safety, const WI: u8, const O: u8>
+where
+    REG: Writable + RegisterSpec<Ux = U>,
+    FI: Into<N>,
+{
+    pub(crate) w: &'a mut REG::Writer,
+    _field: marker::PhantomData<(N, FI, Safety)>,
+}
+impl<'a, U, REG, N, FI, Safety, const WI: u8, const O: u8>
+    FieldWriterRaw<'a, U, REG, N, FI, Safety, WI, O>
+where
+    REG: Writable + RegisterSpec<Ux = U>,
+    FI: Into<N>,
+{
+    #[doc = " Creates a new instance of the writer"]
+    #[allow(unused)]
+    #[inline(always)]
+    pub(crate) fn new(w: &'a mut REG::Writer) -> Self {
+        Self {
+            w,
+            _field: marker::PhantomData,
+        }
+    }
+}
+#[doc(hidden)]
+pub struct BitWriterRaw<'a, U, REG, FI, M, const O: u8>
+where
+    REG: Writable + RegisterSpec<Ux = U>,
+    FI: Into<bool>,
+{
+    pub(crate) w: &'a mut REG::Writer,
+    _field: marker::PhantomData<(FI, M)>,
+}
+impl<'a, U, REG, FI, M, const O: u8> BitWriterRaw<'a, U, REG, FI, M, O>
+where
+    REG: Writable + RegisterSpec<Ux = U>,
+    FI: Into<bool>,
+{
+    #[doc = " Creates a new instance of the writer"]
+    #[allow(unused)]
+    #[inline(always)]
+    pub(crate) fn new(w: &'a mut REG::Writer) -> Self {
+        Self {
+            w,
+            _field: marker::PhantomData,
+        }
+    }
+}
+#[doc = " Write field Proxy with unsafe `bits`"]
+pub type FieldWriter<'a, U, REG, N, FI, const WI: u8, const O: u8> =
+    FieldWriterRaw<'a, U, REG, N, FI, Unsafe, WI, O>;
+#[doc = " Write field Proxy with safe `bits`"]
+pub type FieldWriterSafe<'a, U, REG, N, FI, const WI: u8, const O: u8> =
+    FieldWriterRaw<'a, U, REG, N, FI, Safe, WI, O>;
+impl<'a, U, REG, N, FI, const WI: u8, const OF: u8> FieldWriter<'a, U, REG, N, FI, WI, OF>
+where
+    REG: Writable + RegisterSpec<Ux = U>,
+    FI: Into<N>,
+{
+    #[doc = " Field width"]
+    pub const WIDTH: u8 = WI;
+    #[doc = " Field offset"]
+    pub const OFFSET: u8 = OF;
+}
+impl<'a, U, REG, N, FI, const WI: u8, const OF: u8> FieldWriterSafe<'a, U, REG, N, FI, WI, OF>
+where
+    REG: Writable + RegisterSpec<Ux = U>,
+    FI: Into<N>,
+{
+    #[doc = " Field width"]
+    pub const WIDTH: u8 = WI;
+    #[doc = " Field offset"]
+    pub const OFFSET: u8 = OF;
+}
+macro_rules! bit_proxy {
+    ($ writer : ident , $ mwv : ident) => {
+        #[doc(hidden)]
+        pub struct $mwv;
+        #[doc = " Bit-wise write field proxy"]
+        pub type $writer<'a, U, REG, FI, const O: u8> = BitWriterRaw<'a, U, REG, FI, $mwv, O>;
+        impl<'a, U, REG, FI, const OF: u8> $writer<'a, U, REG, FI, OF>
+        where
+            REG: Writable + RegisterSpec<Ux = U>,
+            FI: Into<bool>,
+        {
+            #[doc = " Field width"]
+            pub const WIDTH: u8 = 1;
+            #[doc = " Field offset"]
+            pub const OFFSET: u8 = OF;
+        }
+    };
+}
+macro_rules! impl_bit_proxy {
+    ($ writer : ident , $ U : ty) => {
+        impl<'a, REG, FI, const OF: u8> $writer<'a, $U, REG, FI, OF>
+        where
+            REG: Writable + RegisterSpec<Ux = $U>,
+            FI: Into<bool>,
+        {
+            #[doc = " Writes bit to the field"]
+            #[inline(always)]
+            pub fn bit(self, value: bool) -> &'a mut REG::Writer {
+                self.w.bits = (self.w.bits & !(1 << { OF })) | ((<$U>::from(value) & 1) << { OF });
+                self.w
+            }
+            #[doc = " Writes `variant` to the field"]
+            #[inline(always)]
+            pub fn variant(self, variant: FI) -> &'a mut REG::Writer {
+                self.bit(variant.into())
+            }
+        }
+    };
+}
+bit_proxy!(BitWriter, BitM);
+bit_proxy!(BitWriter1S, Bit1S);
+bit_proxy!(BitWriter0C, Bit0C);
+bit_proxy!(BitWriter1C, Bit1C);
+bit_proxy!(BitWriter0S, Bit0S);
+bit_proxy!(BitWriter1T, Bit1T);
+bit_proxy!(BitWriter0T, Bit0T);
+macro_rules! impl_proxy {
+    ($ U : ty) => {
+        impl<'a, REG, N, FI, const WI: u8, const OF: u8> FieldWriter<'a, $U, REG, N, FI, WI, OF>
+        where
+            REG: Writable + RegisterSpec<Ux = $U>,
+            N: Into<$U>,
+            FI: Into<N>,
+        {
+            const MASK: $U = <$U>::MAX >> (<$U>::MAX.leading_ones() as u8 - { WI });
+            #[doc = " Writes raw bits to the field"]
+            #[doc = ""]
+            #[doc = " # Safety"]
+            #[doc = ""]
+            #[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"]
+            #[inline(always)]
+            pub unsafe fn bits(self, value: N) -> &'a mut REG::Writer {
+                self.w.bits = (self.w.bits & !(Self::MASK << { OF }))
+                    | ((value.into() & Self::MASK) << { OF });
+                self.w
+            }
+            #[doc = " Writes `variant` to the field"]
+            #[inline(always)]
+            pub fn variant(self, variant: FI) -> &'a mut REG::Writer {
+                unsafe { self.bits(variant.into()) }
+            }
+        }
+        impl<'a, REG, N, FI, const WI: u8, const OF: u8> FieldWriterSafe<'a, $U, REG, N, FI, WI, OF>
+        where
+            REG: Writable + RegisterSpec<Ux = $U>,
+            N: Into<$U>,
+            FI: Into<N>,
+        {
+            const MASK: $U = <$U>::MAX >> (<$U>::MAX.leading_ones() as u8 - { WI });
+            #[doc = " Writes raw bits to the field"]
+            #[inline(always)]
+            pub fn bits(self, value: N) -> &'a mut REG::Writer {
+                self.w.bits = (self.w.bits & !(Self::MASK << { OF }))
+                    | ((value.into() & Self::MASK) << { OF });
+                self.w
+            }
+            #[doc = " Writes `variant` to the field"]
+            #[inline(always)]
+            pub fn variant(self, variant: FI) -> &'a mut REG::Writer {
+                self.bits(variant.into())
+            }
+        }
+        impl_bit_proxy!(BitWriter, $U);
+        impl_bit_proxy!(BitWriter1S, $U);
+        impl_bit_proxy!(BitWriter0C, $U);
+        impl_bit_proxy!(BitWriter1C, $U);
+        impl_bit_proxy!(BitWriter0S, $U);
+        impl_bit_proxy!(BitWriter1T, $U);
+        impl_bit_proxy!(BitWriter0T, $U);
+        impl<'a, REG, FI, const OF: u8> BitWriter<'a, $U, REG, FI, OF>
+        where
+            REG: Writable + RegisterSpec<Ux = $U>,
+            FI: Into<bool>,
+        {
+            #[doc = " Sets the field bit"]
+            #[inline(always)]
+            pub fn set_bit(self) -> &'a mut REG::Writer {
+                self.bit(true)
+            }
+            #[doc = " Clears the field bit"]
+            #[inline(always)]
+            pub fn clear_bit(self) -> &'a mut REG::Writer {
+                self.bit(false)
+            }
+        }
+        impl<'a, REG, FI, const OF: u8> BitWriter1S<'a, $U, REG, FI, OF>
+        where
+            REG: Writable + RegisterSpec<Ux = $U>,
+            FI: Into<bool>,
+        {
+            #[doc = " Sets the field bit"]
+            #[inline(always)]
+            pub fn set_bit(self) -> &'a mut REG::Writer {
+                self.bit(true)
+            }
+        }
+        impl<'a, REG, FI, const OF: u8> BitWriter0C<'a, $U, REG, FI, OF>
+        where
+            REG: Writable + RegisterSpec<Ux = $U>,
+            FI: Into<bool>,
+        {
+            #[doc = " Clears the field bit"]
+            #[inline(always)]
+            pub fn clear_bit(self) -> &'a mut REG::Writer {
+                self.bit(false)
+            }
+        }
+        impl<'a, REG, FI, const OF: u8> BitWriter1C<'a, $U, REG, FI, OF>
+        where
+            REG: Writable + RegisterSpec<Ux = $U>,
+            FI: Into<bool>,
+        {
+            #[doc = "Clears the field bit by passing one"]
+            #[inline(always)]
+            pub fn clear_bit_by_one(self) -> &'a mut REG::Writer {
+                self.bit(true)
+            }
+        }
+        impl<'a, REG, FI, const OF: u8> BitWriter0S<'a, $U, REG, FI, OF>
+        where
+            REG: Writable + RegisterSpec<Ux = $U>,
+            FI: Into<bool>,
+        {
+            #[doc = "Sets the field bit by passing zero"]
+            #[inline(always)]
+            pub fn set_bit_by_zero(self) -> &'a mut REG::Writer {
+                self.bit(false)
+            }
+        }
+        impl<'a, REG, FI, const OF: u8> BitWriter1T<'a, $U, REG, FI, OF>
+        where
+            REG: Writable + RegisterSpec<Ux = $U>,
+            FI: Into<bool>,
+        {
+            #[doc = "Toggle the field bit by passing one"]
+            #[inline(always)]
+            pub fn toggle_bit(self) -> &'a mut REG::Writer {
+                self.bit(true)
+            }
+        }
+        impl<'a, REG, FI, const OF: u8> BitWriter0T<'a, $U, REG, FI, OF>
+        where
+            REG: Writable + RegisterSpec<Ux = $U>,
+            FI: Into<bool>,
+        {
+            #[doc = "Toggle the field bit by passing zero"]
+            #[inline(always)]
+            pub fn toggle_bit(self) -> &'a mut REG::Writer {
+                self.bit(false)
+            }
+        }
+    };
+}
+impl_proxy!(u32);

vendor/nrf51-pac/src/gpio.rs

@@ -0,0 +1,54 @@
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    _reserved0: [u8; 0x0504],
+    #[doc = "0x504 - Write GPIO port."]
+    pub out: OUT,
+    #[doc = "0x508 - Set individual bits in GPIO port."]
+    pub outset: OUTSET,
+    #[doc = "0x50c - Clear individual bits in GPIO port."]
+    pub outclr: OUTCLR,
+    #[doc = "0x510 - Read GPIO port."]
+    pub in_: IN,
+    #[doc = "0x514 - Direction of GPIO pins."]
+    pub dir: DIR,
+    #[doc = "0x518 - DIR set register."]
+    pub dirset: DIRSET,
+    #[doc = "0x51c - DIR clear register."]
+    pub dirclr: DIRCLR,
+    _reserved7: [u8; 0x01e0],
+    #[doc = "0x700..0x780 - Configuration of GPIO pins."]
+    pub pin_cnf: [PIN_CNF; 32],
+}
+#[doc = "OUT (rw) register accessor: an alias for `Reg<OUT_SPEC>`"]
+pub type OUT = crate::Reg<out::OUT_SPEC>;
+#[doc = "Write GPIO port."]
+pub mod out;
+#[doc = "OUTSET (rw) register accessor: an alias for `Reg<OUTSET_SPEC>`"]
+pub type OUTSET = crate::Reg<outset::OUTSET_SPEC>;
+#[doc = "Set individual bits in GPIO port."]
+pub mod outset;
+#[doc = "OUTCLR (rw) register accessor: an alias for `Reg<OUTCLR_SPEC>`"]
+pub type OUTCLR = crate::Reg<outclr::OUTCLR_SPEC>;
+#[doc = "Clear individual bits in GPIO port."]
+pub mod outclr;
+#[doc = "IN (r) register accessor: an alias for `Reg<IN_SPEC>`"]
+pub type IN = crate::Reg<in_::IN_SPEC>;
+#[doc = "Read GPIO port."]
+pub mod in_;
+#[doc = "DIR (rw) register accessor: an alias for `Reg<DIR_SPEC>`"]
+pub type DIR = crate::Reg<dir::DIR_SPEC>;
+#[doc = "Direction of GPIO pins."]
+pub mod dir;
+#[doc = "DIRSET (rw) register accessor: an alias for `Reg<DIRSET_SPEC>`"]
+pub type DIRSET = crate::Reg<dirset::DIRSET_SPEC>;
+#[doc = "DIR set register."]
+pub mod dirset;
+#[doc = "DIRCLR (rw) register accessor: an alias for `Reg<DIRCLR_SPEC>`"]
+pub type DIRCLR = crate::Reg<dirclr::DIRCLR_SPEC>;
+#[doc = "DIR clear register."]
+pub mod dirclr;
+#[doc = "PIN_CNF (rw) register accessor: an alias for `Reg<PIN_CNF_SPEC>`"]
+pub type PIN_CNF = crate::Reg<pin_cnf::PIN_CNF_SPEC>;
+#[doc = "Configuration of GPIO pins."]
+pub mod pin_cnf;