feat: add display UI with splash screen, dashboard, and RSSI sparkline

Implement full SSD1306 OLED display support:
- Splash screen on boot (1.5s) with project name, version, board
- Dashboard showing radio state, config, counters, RSSI/SNR
- RSSI history sparkline (64-sample ring buffer, 2px-wide bars)
- DisplayOn/DisplayOff host commands routed via dedicated channel
- Pure render functions against generic DrawTarget (no hardware coupling)
- Display on/off control bypasses radio task entirely

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
This commit is contained in:
swaitsandClaude Opus 4.6 committed 2026-03-29 20:42:54 -06:00
1 parent 7064110293
commit 3102fc747a
17624 files changed
+4564928 -38

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#[doc = "Register `MAXCNT` reader"]
pub struct R(crate::R<MAXCNT_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<MAXCNT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<MAXCNT_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<MAXCNT_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `MAXCNT` writer"]
pub struct W(crate::W<MAXCNT_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<MAXCNT_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<MAXCNT_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<MAXCNT_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `BUFFSIZE` reader - Length of DMA RAM allocation in number of samples"]
pub type BUFFSIZE_R = crate::FieldReader<u16, u16>;
#[doc = "Field `BUFFSIZE` writer - Length of DMA RAM allocation in number of samples"]
pub type BUFFSIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MAXCNT_SPEC, u16, u16, 15, O>;
impl R {
#[doc = "Bits 0:14 - Length of DMA RAM allocation in number of samples"]
#[inline(always)]
pub fn buffsize(&self) -> BUFFSIZE_R {
BUFFSIZE_R::new((self.bits & 0x7fff) as u16)
}
}
impl W {
#[doc = "Bits 0:14 - Length of DMA RAM allocation in number of samples"]
#[inline(always)]
pub fn buffsize(&mut self) -> BUFFSIZE_W<0> {
BUFFSIZE_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Number of samples to allocate memory for in EasyDMA mode\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [maxcnt](index.html) module"]
pub struct MAXCNT_SPEC;
impl crate::RegisterSpec for MAXCNT_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [maxcnt::R](R) reader structure"]
impl crate::Readable for MAXCNT_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [maxcnt::W](W) writer structure"]
impl crate::Writable for MAXCNT_SPEC {
type Writer = W;
}
#[doc = "`reset()` method sets MAXCNT to value 0"]
impl crate::Resettable for MAXCNT_SPEC {
#[inline(always)]
fn reset_value() -> Self::Ux {
0
}
}
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#[doc = "Register `PTR` reader"]
pub struct R(crate::R<PTR_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<PTR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<PTR_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<PTR_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `PTR` writer"]
pub struct W(crate::W<PTR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<PTR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<PTR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<PTR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `SAMPLEPTR` reader - Address to write PDM samples to over DMA"]
pub type SAMPLEPTR_R = crate::FieldReader<u32, u32>;
#[doc = "Field `SAMPLEPTR` writer - Address to write PDM samples to over DMA"]
pub type SAMPLEPTR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PTR_SPEC, u32, u32, 32, O>;
impl R {
#[doc = "Bits 0:31 - Address to write PDM samples to over DMA"]
#[inline(always)]
pub fn sampleptr(&self) -> SAMPLEPTR_R {
SAMPLEPTR_R::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Address to write PDM samples to over DMA"]
#[inline(always)]
pub fn sampleptr(&mut self) -> SAMPLEPTR_W<0> {
SAMPLEPTR_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "RAM address pointer to write samples to with EasyDMA\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ptr](index.html) module"]
pub struct PTR_SPEC;
impl crate::RegisterSpec for PTR_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ptr::R](R) reader structure"]
impl crate::Readable for PTR_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ptr::W](W) writer structure"]
impl crate::Writable for PTR_SPEC {
type Writer = W;
}
#[doc = "`reset()` method sets PTR to value 0"]
impl crate::Resettable for PTR_SPEC {
#[inline(always)]
fn reset_value() -> Self::Ux {
0
}
}