feat: add display UI with splash screen, dashboard, and RSSI sparkline

Implement full SSD1306 OLED display support:
- Splash screen on boot (1.5s) with project name, version, board
- Dashboard showing radio state, config, counters, RSSI/SNR
- RSSI history sparkline (64-sample ring buffer, 2px-wide bars)
- DisplayOn/DisplayOff host commands routed via dedicated channel
- Pure render functions against generic DrawTarget (no hardware coupling)
- Display on/off control bypasses radio task entirely

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>

vendor/nrf52820-pac/src/spi0/config.rs

@@ -0,0 +1,246 @@
+#[doc = "Register `CONFIG` reader"]
+pub struct R(crate::R<CONFIG_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<CONFIG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<CONFIG_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<CONFIG_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `CONFIG` writer"]
+pub struct W(crate::W<CONFIG_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<CONFIG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<CONFIG_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<CONFIG_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `ORDER` reader - Bit order"]
+pub type ORDER_R = crate::BitReader<ORDER_A>;
+#[doc = "Bit order\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ORDER_A {
+    #[doc = "0: Most significant bit shifted out first"]
+    MSB_FIRST = 0,
+    #[doc = "1: Least significant bit shifted out first"]
+    LSB_FIRST = 1,
+}
+impl From<ORDER_A> for bool {
+    #[inline(always)]
+    fn from(variant: ORDER_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl ORDER_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> ORDER_A {
+        match self.bits {
+            false => ORDER_A::MSB_FIRST,
+            true => ORDER_A::LSB_FIRST,
+        }
+    }
+    #[doc = "Checks if the value of the field is `MSB_FIRST`"]
+    #[inline(always)]
+    pub fn is_msb_first(&self) -> bool {
+        *self == ORDER_A::MSB_FIRST
+    }
+    #[doc = "Checks if the value of the field is `LSB_FIRST`"]
+    #[inline(always)]
+    pub fn is_lsb_first(&self) -> bool {
+        *self == ORDER_A::LSB_FIRST
+    }
+}
+#[doc = "Field `ORDER` writer - Bit order"]
+pub type ORDER_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONFIG_SPEC, ORDER_A, O>;
+impl<'a, const O: u8> ORDER_W<'a, O> {
+    #[doc = "Most significant bit shifted out first"]
+    #[inline(always)]
+    pub fn msb_first(self) -> &'a mut W {
+        self.variant(ORDER_A::MSB_FIRST)
+    }
+    #[doc = "Least significant bit shifted out first"]
+    #[inline(always)]
+    pub fn lsb_first(self) -> &'a mut W {
+        self.variant(ORDER_A::LSB_FIRST)
+    }
+}
+#[doc = "Field `CPHA` reader - Serial clock (SCK) phase"]
+pub type CPHA_R = crate::BitReader<CPHA_A>;
+#[doc = "Serial clock (SCK) phase\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CPHA_A {
+    #[doc = "0: Sample on leading edge of clock, shift serial data on trailing edge"]
+    LEADING = 0,
+    #[doc = "1: Sample on trailing edge of clock, shift serial data on leading edge"]
+    TRAILING = 1,
+}
+impl From<CPHA_A> for bool {
+    #[inline(always)]
+    fn from(variant: CPHA_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl CPHA_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> CPHA_A {
+        match self.bits {
+            false => CPHA_A::LEADING,
+            true => CPHA_A::TRAILING,
+        }
+    }
+    #[doc = "Checks if the value of the field is `LEADING`"]
+    #[inline(always)]
+    pub fn is_leading(&self) -> bool {
+        *self == CPHA_A::LEADING
+    }
+    #[doc = "Checks if the value of the field is `TRAILING`"]
+    #[inline(always)]
+    pub fn is_trailing(&self) -> bool {
+        *self == CPHA_A::TRAILING
+    }
+}
+#[doc = "Field `CPHA` writer - Serial clock (SCK) phase"]
+pub type CPHA_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONFIG_SPEC, CPHA_A, O>;
+impl<'a, const O: u8> CPHA_W<'a, O> {
+    #[doc = "Sample on leading edge of clock, shift serial data on trailing edge"]
+    #[inline(always)]
+    pub fn leading(self) -> &'a mut W {
+        self.variant(CPHA_A::LEADING)
+    }
+    #[doc = "Sample on trailing edge of clock, shift serial data on leading edge"]
+    #[inline(always)]
+    pub fn trailing(self) -> &'a mut W {
+        self.variant(CPHA_A::TRAILING)
+    }
+}
+#[doc = "Field `CPOL` reader - Serial clock (SCK) polarity"]
+pub type CPOL_R = crate::BitReader<CPOL_A>;
+#[doc = "Serial clock (SCK) polarity\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CPOL_A {
+    #[doc = "0: Active high"]
+    ACTIVE_HIGH = 0,
+    #[doc = "1: Active low"]
+    ACTIVE_LOW = 1,
+}
+impl From<CPOL_A> for bool {
+    #[inline(always)]
+    fn from(variant: CPOL_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl CPOL_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> CPOL_A {
+        match self.bits {
+            false => CPOL_A::ACTIVE_HIGH,
+            true => CPOL_A::ACTIVE_LOW,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ACTIVE_HIGH`"]
+    #[inline(always)]
+    pub fn is_active_high(&self) -> bool {
+        *self == CPOL_A::ACTIVE_HIGH
+    }
+    #[doc = "Checks if the value of the field is `ACTIVE_LOW`"]
+    #[inline(always)]
+    pub fn is_active_low(&self) -> bool {
+        *self == CPOL_A::ACTIVE_LOW
+    }
+}
+#[doc = "Field `CPOL` writer - Serial clock (SCK) polarity"]
+pub type CPOL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONFIG_SPEC, CPOL_A, O>;
+impl<'a, const O: u8> CPOL_W<'a, O> {
+    #[doc = "Active high"]
+    #[inline(always)]
+    pub fn active_high(self) -> &'a mut W {
+        self.variant(CPOL_A::ACTIVE_HIGH)
+    }
+    #[doc = "Active low"]
+    #[inline(always)]
+    pub fn active_low(self) -> &'a mut W {
+        self.variant(CPOL_A::ACTIVE_LOW)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Bit order"]
+    #[inline(always)]
+    pub fn order(&self) -> ORDER_R {
+        ORDER_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Serial clock (SCK) phase"]
+    #[inline(always)]
+    pub fn cpha(&self) -> CPHA_R {
+        CPHA_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Serial clock (SCK) polarity"]
+    #[inline(always)]
+    pub fn cpol(&self) -> CPOL_R {
+        CPOL_R::new(((self.bits >> 2) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Bit order"]
+    #[inline(always)]
+    pub fn order(&mut self) -> ORDER_W<0> {
+        ORDER_W::new(self)
+    }
+    #[doc = "Bit 1 - Serial clock (SCK) phase"]
+    #[inline(always)]
+    pub fn cpha(&mut self) -> CPHA_W<1> {
+        CPHA_W::new(self)
+    }
+    #[doc = "Bit 2 - Serial clock (SCK) polarity"]
+    #[inline(always)]
+    pub fn cpol(&mut self) -> CPOL_W<2> {
+        CPOL_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [config](index.html) module"]
+pub struct CONFIG_SPEC;
+impl crate::RegisterSpec for CONFIG_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [config::R](R) reader structure"]
+impl crate::Readable for CONFIG_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [config::W](W) writer structure"]
+impl crate::Writable for CONFIG_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets CONFIG to value 0"]
+impl crate::Resettable for CONFIG_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf52820-pac/src/spi0/enable.rs

@@ -0,0 +1,128 @@
+#[doc = "Register `ENABLE` reader"]
+pub struct R(crate::R<ENABLE_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<ENABLE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<ENABLE_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<ENABLE_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `ENABLE` writer"]
+pub struct W(crate::W<ENABLE_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<ENABLE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<ENABLE_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<ENABLE_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `ENABLE` reader - Enable or disable SPI"]
+pub type ENABLE_R = crate::FieldReader<u8, ENABLE_A>;
+#[doc = "Enable or disable SPI\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum ENABLE_A {
+    #[doc = "0: Disable SPI"]
+    DISABLED = 0,
+    #[doc = "1: Enable SPI"]
+    ENABLED = 1,
+}
+impl From<ENABLE_A> for u8 {
+    #[inline(always)]
+    fn from(variant: ENABLE_A) -> Self {
+        variant as _
+    }
+}
+impl ENABLE_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<ENABLE_A> {
+        match self.bits {
+            0 => Some(ENABLE_A::DISABLED),
+            1 => Some(ENABLE_A::ENABLED),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == ENABLE_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == ENABLE_A::ENABLED
+    }
+}
+#[doc = "Field `ENABLE` writer - Enable or disable SPI"]
+pub type ENABLE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ENABLE_SPEC, u8, ENABLE_A, 4, O>;
+impl<'a, const O: u8> ENABLE_W<'a, O> {
+    #[doc = "Disable SPI"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(ENABLE_A::DISABLED)
+    }
+    #[doc = "Enable SPI"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(ENABLE_A::ENABLED)
+    }
+}
+impl R {
+    #[doc = "Bits 0:3 - Enable or disable SPI"]
+    #[inline(always)]
+    pub fn enable(&self) -> ENABLE_R {
+        ENABLE_R::new((self.bits & 0x0f) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:3 - Enable or disable SPI"]
+    #[inline(always)]
+    pub fn enable(&mut self) -> ENABLE_W<0> {
+        ENABLE_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Enable SPI\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [enable](index.html) module"]
+pub struct ENABLE_SPEC;
+impl crate::RegisterSpec for ENABLE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [enable::R](R) reader structure"]
+impl crate::Readable for ENABLE_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [enable::W](W) writer structure"]
+impl crate::Writable for ENABLE_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets ENABLE to value 0"]
+impl crate::Resettable for ENABLE_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf52820-pac/src/spi0/events_ready.rs

@@ -0,0 +1,127 @@
+#[doc = "Register `EVENTS_READY` reader"]
+pub struct R(crate::R<EVENTS_READY_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<EVENTS_READY_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<EVENTS_READY_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<EVENTS_READY_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `EVENTS_READY` writer"]
+pub struct W(crate::W<EVENTS_READY_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<EVENTS_READY_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<EVENTS_READY_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<EVENTS_READY_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `EVENTS_READY` reader - TXD byte sent and RXD byte received"]
+pub type EVENTS_READY_R = crate::BitReader<EVENTS_READY_A>;
+#[doc = "TXD byte sent and RXD byte received\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum EVENTS_READY_A {
+    #[doc = "0: Event not generated"]
+    NOT_GENERATED = 0,
+    #[doc = "1: Event generated"]
+    GENERATED = 1,
+}
+impl From<EVENTS_READY_A> for bool {
+    #[inline(always)]
+    fn from(variant: EVENTS_READY_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl EVENTS_READY_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> EVENTS_READY_A {
+        match self.bits {
+            false => EVENTS_READY_A::NOT_GENERATED,
+            true => EVENTS_READY_A::GENERATED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `NOT_GENERATED`"]
+    #[inline(always)]
+    pub fn is_not_generated(&self) -> bool {
+        *self == EVENTS_READY_A::NOT_GENERATED
+    }
+    #[doc = "Checks if the value of the field is `GENERATED`"]
+    #[inline(always)]
+    pub fn is_generated(&self) -> bool {
+        *self == EVENTS_READY_A::GENERATED
+    }
+}
+#[doc = "Field `EVENTS_READY` writer - TXD byte sent and RXD byte received"]
+pub type EVENTS_READY_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, EVENTS_READY_SPEC, EVENTS_READY_A, O>;
+impl<'a, const O: u8> EVENTS_READY_W<'a, O> {
+    #[doc = "Event not generated"]
+    #[inline(always)]
+    pub fn not_generated(self) -> &'a mut W {
+        self.variant(EVENTS_READY_A::NOT_GENERATED)
+    }
+    #[doc = "Event generated"]
+    #[inline(always)]
+    pub fn generated(self) -> &'a mut W {
+        self.variant(EVENTS_READY_A::GENERATED)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - TXD byte sent and RXD byte received"]
+    #[inline(always)]
+    pub fn events_ready(&self) -> EVENTS_READY_R {
+        EVENTS_READY_R::new((self.bits & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - TXD byte sent and RXD byte received"]
+    #[inline(always)]
+    pub fn events_ready(&mut self) -> EVENTS_READY_W<0> {
+        EVENTS_READY_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "TXD byte sent and RXD byte received\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_ready](index.html) module"]
+pub struct EVENTS_READY_SPEC;
+impl crate::RegisterSpec for EVENTS_READY_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [events_ready::R](R) reader structure"]
+impl crate::Readable for EVENTS_READY_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [events_ready::W](W) writer structure"]
+impl crate::Writable for EVENTS_READY_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets EVENTS_READY to value 0"]
+impl crate::Resettable for EVENTS_READY_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf52820-pac/src/spi0/frequency.rs

@@ -0,0 +1,194 @@
+#[doc = "Register `FREQUENCY` reader"]
+pub struct R(crate::R<FREQUENCY_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<FREQUENCY_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<FREQUENCY_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<FREQUENCY_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `FREQUENCY` writer"]
+pub struct W(crate::W<FREQUENCY_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<FREQUENCY_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<FREQUENCY_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<FREQUENCY_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `FREQUENCY` reader - SPI master data rate"]
+pub type FREQUENCY_R = crate::FieldReader<u32, FREQUENCY_A>;
+#[doc = "SPI master data rate\n\nValue on reset: 67108864"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u32)]
+pub enum FREQUENCY_A {
+    #[doc = "33554432: 125 kbps"]
+    K125 = 33554432,
+    #[doc = "67108864: 250 kbps"]
+    K250 = 67108864,
+    #[doc = "134217728: 500 kbps"]
+    K500 = 134217728,
+    #[doc = "268435456: 1 Mbps"]
+    M1 = 268435456,
+    #[doc = "536870912: 2 Mbps"]
+    M2 = 536870912,
+    #[doc = "1073741824: 4 Mbps"]
+    M4 = 1073741824,
+    #[doc = "2147483648: 8 Mbps"]
+    M8 = 2147483648,
+}
+impl From<FREQUENCY_A> for u32 {
+    #[inline(always)]
+    fn from(variant: FREQUENCY_A) -> Self {
+        variant as _
+    }
+}
+impl FREQUENCY_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<FREQUENCY_A> {
+        match self.bits {
+            33554432 => Some(FREQUENCY_A::K125),
+            67108864 => Some(FREQUENCY_A::K250),
+            134217728 => Some(FREQUENCY_A::K500),
+            268435456 => Some(FREQUENCY_A::M1),
+            536870912 => Some(FREQUENCY_A::M2),
+            1073741824 => Some(FREQUENCY_A::M4),
+            2147483648 => Some(FREQUENCY_A::M8),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `K125`"]
+    #[inline(always)]
+    pub fn is_k125(&self) -> bool {
+        *self == FREQUENCY_A::K125
+    }
+    #[doc = "Checks if the value of the field is `K250`"]
+    #[inline(always)]
+    pub fn is_k250(&self) -> bool {
+        *self == FREQUENCY_A::K250
+    }
+    #[doc = "Checks if the value of the field is `K500`"]
+    #[inline(always)]
+    pub fn is_k500(&self) -> bool {
+        *self == FREQUENCY_A::K500
+    }
+    #[doc = "Checks if the value of the field is `M1`"]
+    #[inline(always)]
+    pub fn is_m1(&self) -> bool {
+        *self == FREQUENCY_A::M1
+    }
+    #[doc = "Checks if the value of the field is `M2`"]
+    #[inline(always)]
+    pub fn is_m2(&self) -> bool {
+        *self == FREQUENCY_A::M2
+    }
+    #[doc = "Checks if the value of the field is `M4`"]
+    #[inline(always)]
+    pub fn is_m4(&self) -> bool {
+        *self == FREQUENCY_A::M4
+    }
+    #[doc = "Checks if the value of the field is `M8`"]
+    #[inline(always)]
+    pub fn is_m8(&self) -> bool {
+        *self == FREQUENCY_A::M8
+    }
+}
+#[doc = "Field `FREQUENCY` writer - SPI master data rate"]
+pub type FREQUENCY_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u32, FREQUENCY_SPEC, u32, FREQUENCY_A, 32, O>;
+impl<'a, const O: u8> FREQUENCY_W<'a, O> {
+    #[doc = "125 kbps"]
+    #[inline(always)]
+    pub fn k125(self) -> &'a mut W {
+        self.variant(FREQUENCY_A::K125)
+    }
+    #[doc = "250 kbps"]
+    #[inline(always)]
+    pub fn k250(self) -> &'a mut W {
+        self.variant(FREQUENCY_A::K250)
+    }
+    #[doc = "500 kbps"]
+    #[inline(always)]
+    pub fn k500(self) -> &'a mut W {
+        self.variant(FREQUENCY_A::K500)
+    }
+    #[doc = "1 Mbps"]
+    #[inline(always)]
+    pub fn m1(self) -> &'a mut W {
+        self.variant(FREQUENCY_A::M1)
+    }
+    #[doc = "2 Mbps"]
+    #[inline(always)]
+    pub fn m2(self) -> &'a mut W {
+        self.variant(FREQUENCY_A::M2)
+    }
+    #[doc = "4 Mbps"]
+    #[inline(always)]
+    pub fn m4(self) -> &'a mut W {
+        self.variant(FREQUENCY_A::M4)
+    }
+    #[doc = "8 Mbps"]
+    #[inline(always)]
+    pub fn m8(self) -> &'a mut W {
+        self.variant(FREQUENCY_A::M8)
+    }
+}
+impl R {
+    #[doc = "Bits 0:31 - SPI master data rate"]
+    #[inline(always)]
+    pub fn frequency(&self) -> FREQUENCY_R {
+        FREQUENCY_R::new(self.bits)
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - SPI master data rate"]
+    #[inline(always)]
+    pub fn frequency(&mut self) -> FREQUENCY_W<0> {
+        FREQUENCY_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "SPI frequency. Accuracy depends on the HFCLK source selected.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [frequency](index.html) module"]
+pub struct FREQUENCY_SPEC;
+impl crate::RegisterSpec for FREQUENCY_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [frequency::R](R) reader structure"]
+impl crate::Readable for FREQUENCY_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [frequency::W](W) writer structure"]
+impl crate::Writable for FREQUENCY_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets FREQUENCY to value 0x0400_0000"]
+impl crate::Resettable for FREQUENCY_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0x0400_0000
+    }
+}

vendor/nrf52820-pac/src/spi0/intenclr.rs

@@ -0,0 +1,133 @@
+#[doc = "Register `INTENCLR` reader"]
+pub struct R(crate::R<INTENCLR_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<INTENCLR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<INTENCLR_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<INTENCLR_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `INTENCLR` writer"]
+pub struct W(crate::W<INTENCLR_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<INTENCLR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<INTENCLR_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<INTENCLR_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `READY` reader - Write '1' to disable interrupt for event READY"]
+pub type READY_R = crate::BitReader<READY_A>;
+#[doc = "Write '1' to disable interrupt for event READY\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum READY_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<READY_A> for bool {
+    #[inline(always)]
+    fn from(variant: READY_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl READY_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> READY_A {
+        match self.bits {
+            false => READY_A::DISABLED,
+            true => READY_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == READY_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == READY_A::ENABLED
+    }
+}
+#[doc = "Write '1' to disable interrupt for event READY\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum READY_AW {
+    #[doc = "1: Disable"]
+    CLEAR = 1,
+}
+impl From<READY_AW> for bool {
+    #[inline(always)]
+    fn from(variant: READY_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `READY` writer - Write '1' to disable interrupt for event READY"]
+pub type READY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, READY_AW, O>;
+impl<'a, const O: u8> READY_W<'a, O> {
+    #[doc = "Disable"]
+    #[inline(always)]
+    pub fn clear(self) -> &'a mut W {
+        self.variant(READY_AW::CLEAR)
+    }
+}
+impl R {
+    #[doc = "Bit 2 - Write '1' to disable interrupt for event READY"]
+    #[inline(always)]
+    pub fn ready(&self) -> READY_R {
+        READY_R::new(((self.bits >> 2) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 2 - Write '1' to disable interrupt for event READY"]
+    #[inline(always)]
+    pub fn ready(&mut self) -> READY_W<2> {
+        READY_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Disable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"]
+pub struct INTENCLR_SPEC;
+impl crate::RegisterSpec for INTENCLR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [intenclr::R](R) reader structure"]
+impl crate::Readable for INTENCLR_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"]
+impl crate::Writable for INTENCLR_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets INTENCLR to value 0"]
+impl crate::Resettable for INTENCLR_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf52820-pac/src/spi0/intenset.rs

@@ -0,0 +1,133 @@
+#[doc = "Register `INTENSET` reader"]
+pub struct R(crate::R<INTENSET_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<INTENSET_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<INTENSET_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<INTENSET_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `INTENSET` writer"]
+pub struct W(crate::W<INTENSET_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<INTENSET_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<INTENSET_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<INTENSET_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `READY` reader - Write '1' to enable interrupt for event READY"]
+pub type READY_R = crate::BitReader<READY_A>;
+#[doc = "Write '1' to enable interrupt for event READY\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum READY_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<READY_A> for bool {
+    #[inline(always)]
+    fn from(variant: READY_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl READY_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> READY_A {
+        match self.bits {
+            false => READY_A::DISABLED,
+            true => READY_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == READY_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == READY_A::ENABLED
+    }
+}
+#[doc = "Write '1' to enable interrupt for event READY\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum READY_AW {
+    #[doc = "1: Enable"]
+    SET = 1,
+}
+impl From<READY_AW> for bool {
+    #[inline(always)]
+    fn from(variant: READY_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `READY` writer - Write '1' to enable interrupt for event READY"]
+pub type READY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, READY_AW, O>;
+impl<'a, const O: u8> READY_W<'a, O> {
+    #[doc = "Enable"]
+    #[inline(always)]
+    pub fn set(self) -> &'a mut W {
+        self.variant(READY_AW::SET)
+    }
+}
+impl R {
+    #[doc = "Bit 2 - Write '1' to enable interrupt for event READY"]
+    #[inline(always)]
+    pub fn ready(&self) -> READY_R {
+        READY_R::new(((self.bits >> 2) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 2 - Write '1' to enable interrupt for event READY"]
+    #[inline(always)]
+    pub fn ready(&mut self) -> READY_W<2> {
+        READY_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Enable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"]
+pub struct INTENSET_SPEC;
+impl crate::RegisterSpec for INTENSET_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [intenset::R](R) reader structure"]
+impl crate::Readable for INTENSET_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"]
+impl crate::Writable for INTENSET_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets INTENSET to value 0"]
+impl crate::Resettable for INTENSET_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf52820-pac/src/spi0/psel.rs

@@ -0,0 +1,22 @@
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct PSEL {
+    #[doc = "0x00 - Pin select for SCK"]
+    pub sck: SCK,
+    #[doc = "0x04 - Pin select for MOSI signal"]
+    pub mosi: MOSI,
+    #[doc = "0x08 - Pin select for MISO signal"]
+    pub miso: MISO,
+}
+#[doc = "SCK (rw) register accessor: an alias for `Reg<SCK_SPEC>`"]
+pub type SCK = crate::Reg<sck::SCK_SPEC>;
+#[doc = "Pin select for SCK"]
+pub mod sck;
+#[doc = "MOSI (rw) register accessor: an alias for `Reg<MOSI_SPEC>`"]
+pub type MOSI = crate::Reg<mosi::MOSI_SPEC>;
+#[doc = "Pin select for MOSI signal"]
+pub mod mosi;
+#[doc = "MISO (rw) register accessor: an alias for `Reg<MISO_SPEC>`"]
+pub type MISO = crate::Reg<miso::MISO_SPEC>;
+#[doc = "Pin select for MISO signal"]
+pub mod miso;

vendor/nrf52820-pac/src/spi0/psel/miso.rs

@@ -0,0 +1,140 @@
+#[doc = "Register `MISO` reader"]
+pub struct R(crate::R<MISO_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<MISO_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<MISO_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<MISO_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `MISO` writer"]
+pub struct W(crate::W<MISO_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<MISO_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<MISO_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<MISO_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `PIN` reader - Pin number"]
+pub type PIN_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `PIN` writer - Pin number"]
+pub type PIN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MISO_SPEC, u8, u8, 5, O>;
+#[doc = "Field `CONNECT` reader - Connection"]
+pub type CONNECT_R = crate::BitReader<CONNECT_A>;
+#[doc = "Connection\n\nValue on reset: 1"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CONNECT_A {
+    #[doc = "1: Disconnect"]
+    DISCONNECTED = 1,
+    #[doc = "0: Connect"]
+    CONNECTED = 0,
+}
+impl From<CONNECT_A> for bool {
+    #[inline(always)]
+    fn from(variant: CONNECT_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl CONNECT_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> CONNECT_A {
+        match self.bits {
+            true => CONNECT_A::DISCONNECTED,
+            false => CONNECT_A::CONNECTED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISCONNECTED`"]
+    #[inline(always)]
+    pub fn is_disconnected(&self) -> bool {
+        *self == CONNECT_A::DISCONNECTED
+    }
+    #[doc = "Checks if the value of the field is `CONNECTED`"]
+    #[inline(always)]
+    pub fn is_connected(&self) -> bool {
+        *self == CONNECT_A::CONNECTED
+    }
+}
+#[doc = "Field `CONNECT` writer - Connection"]
+pub type CONNECT_W<'a, const O: u8> = crate::BitWriter<'a, u32, MISO_SPEC, CONNECT_A, O>;
+impl<'a, const O: u8> CONNECT_W<'a, O> {
+    #[doc = "Disconnect"]
+    #[inline(always)]
+    pub fn disconnected(self) -> &'a mut W {
+        self.variant(CONNECT_A::DISCONNECTED)
+    }
+    #[doc = "Connect"]
+    #[inline(always)]
+    pub fn connected(self) -> &'a mut W {
+        self.variant(CONNECT_A::CONNECTED)
+    }
+}
+impl R {
+    #[doc = "Bits 0:4 - Pin number"]
+    #[inline(always)]
+    pub fn pin(&self) -> PIN_R {
+        PIN_R::new((self.bits & 0x1f) as u8)
+    }
+    #[doc = "Bit 31 - Connection"]
+    #[inline(always)]
+    pub fn connect(&self) -> CONNECT_R {
+        CONNECT_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:4 - Pin number"]
+    #[inline(always)]
+    pub fn pin(&mut self) -> PIN_W<0> {
+        PIN_W::new(self)
+    }
+    #[doc = "Bit 31 - Connection"]
+    #[inline(always)]
+    pub fn connect(&mut self) -> CONNECT_W<31> {
+        CONNECT_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Pin select for MISO signal\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [miso](index.html) module"]
+pub struct MISO_SPEC;
+impl crate::RegisterSpec for MISO_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [miso::R](R) reader structure"]
+impl crate::Readable for MISO_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [miso::W](W) writer structure"]
+impl crate::Writable for MISO_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets MISO to value 0xffff_ffff"]
+impl crate::Resettable for MISO_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0xffff_ffff
+    }
+}

vendor/nrf52820-pac/src/spi0/psel/mosi.rs

@@ -0,0 +1,140 @@
+#[doc = "Register `MOSI` reader"]
+pub struct R(crate::R<MOSI_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<MOSI_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<MOSI_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<MOSI_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `MOSI` writer"]
+pub struct W(crate::W<MOSI_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<MOSI_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<MOSI_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<MOSI_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `PIN` reader - Pin number"]
+pub type PIN_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `PIN` writer - Pin number"]
+pub type PIN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MOSI_SPEC, u8, u8, 5, O>;
+#[doc = "Field `CONNECT` reader - Connection"]
+pub type CONNECT_R = crate::BitReader<CONNECT_A>;
+#[doc = "Connection\n\nValue on reset: 1"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CONNECT_A {
+    #[doc = "1: Disconnect"]
+    DISCONNECTED = 1,
+    #[doc = "0: Connect"]
+    CONNECTED = 0,
+}
+impl From<CONNECT_A> for bool {
+    #[inline(always)]
+    fn from(variant: CONNECT_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl CONNECT_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> CONNECT_A {
+        match self.bits {
+            true => CONNECT_A::DISCONNECTED,
+            false => CONNECT_A::CONNECTED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISCONNECTED`"]
+    #[inline(always)]
+    pub fn is_disconnected(&self) -> bool {
+        *self == CONNECT_A::DISCONNECTED
+    }
+    #[doc = "Checks if the value of the field is `CONNECTED`"]
+    #[inline(always)]
+    pub fn is_connected(&self) -> bool {
+        *self == CONNECT_A::CONNECTED
+    }
+}
+#[doc = "Field `CONNECT` writer - Connection"]
+pub type CONNECT_W<'a, const O: u8> = crate::BitWriter<'a, u32, MOSI_SPEC, CONNECT_A, O>;
+impl<'a, const O: u8> CONNECT_W<'a, O> {
+    #[doc = "Disconnect"]
+    #[inline(always)]
+    pub fn disconnected(self) -> &'a mut W {
+        self.variant(CONNECT_A::DISCONNECTED)
+    }
+    #[doc = "Connect"]
+    #[inline(always)]
+    pub fn connected(self) -> &'a mut W {
+        self.variant(CONNECT_A::CONNECTED)
+    }
+}
+impl R {
+    #[doc = "Bits 0:4 - Pin number"]
+    #[inline(always)]
+    pub fn pin(&self) -> PIN_R {
+        PIN_R::new((self.bits & 0x1f) as u8)
+    }
+    #[doc = "Bit 31 - Connection"]
+    #[inline(always)]
+    pub fn connect(&self) -> CONNECT_R {
+        CONNECT_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:4 - Pin number"]
+    #[inline(always)]
+    pub fn pin(&mut self) -> PIN_W<0> {
+        PIN_W::new(self)
+    }
+    #[doc = "Bit 31 - Connection"]
+    #[inline(always)]
+    pub fn connect(&mut self) -> CONNECT_W<31> {
+        CONNECT_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Pin select for MOSI signal\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mosi](index.html) module"]
+pub struct MOSI_SPEC;
+impl crate::RegisterSpec for MOSI_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [mosi::R](R) reader structure"]
+impl crate::Readable for MOSI_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [mosi::W](W) writer structure"]
+impl crate::Writable for MOSI_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets MOSI to value 0xffff_ffff"]
+impl crate::Resettable for MOSI_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0xffff_ffff
+    }
+}

vendor/nrf52820-pac/src/spi0/psel/sck.rs

@@ -0,0 +1,140 @@
+#[doc = "Register `SCK` reader"]
+pub struct R(crate::R<SCK_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<SCK_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<SCK_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<SCK_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `SCK` writer"]
+pub struct W(crate::W<SCK_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<SCK_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<SCK_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<SCK_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `PIN` reader - Pin number"]
+pub type PIN_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `PIN` writer - Pin number"]
+pub type PIN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SCK_SPEC, u8, u8, 5, O>;
+#[doc = "Field `CONNECT` reader - Connection"]
+pub type CONNECT_R = crate::BitReader<CONNECT_A>;
+#[doc = "Connection\n\nValue on reset: 1"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CONNECT_A {
+    #[doc = "1: Disconnect"]
+    DISCONNECTED = 1,
+    #[doc = "0: Connect"]
+    CONNECTED = 0,
+}
+impl From<CONNECT_A> for bool {
+    #[inline(always)]
+    fn from(variant: CONNECT_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl CONNECT_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> CONNECT_A {
+        match self.bits {
+            true => CONNECT_A::DISCONNECTED,
+            false => CONNECT_A::CONNECTED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISCONNECTED`"]
+    #[inline(always)]
+    pub fn is_disconnected(&self) -> bool {
+        *self == CONNECT_A::DISCONNECTED
+    }
+    #[doc = "Checks if the value of the field is `CONNECTED`"]
+    #[inline(always)]
+    pub fn is_connected(&self) -> bool {
+        *self == CONNECT_A::CONNECTED
+    }
+}
+#[doc = "Field `CONNECT` writer - Connection"]
+pub type CONNECT_W<'a, const O: u8> = crate::BitWriter<'a, u32, SCK_SPEC, CONNECT_A, O>;
+impl<'a, const O: u8> CONNECT_W<'a, O> {
+    #[doc = "Disconnect"]
+    #[inline(always)]
+    pub fn disconnected(self) -> &'a mut W {
+        self.variant(CONNECT_A::DISCONNECTED)
+    }
+    #[doc = "Connect"]
+    #[inline(always)]
+    pub fn connected(self) -> &'a mut W {
+        self.variant(CONNECT_A::CONNECTED)
+    }
+}
+impl R {
+    #[doc = "Bits 0:4 - Pin number"]
+    #[inline(always)]
+    pub fn pin(&self) -> PIN_R {
+        PIN_R::new((self.bits & 0x1f) as u8)
+    }
+    #[doc = "Bit 31 - Connection"]
+    #[inline(always)]
+    pub fn connect(&self) -> CONNECT_R {
+        CONNECT_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:4 - Pin number"]
+    #[inline(always)]
+    pub fn pin(&mut self) -> PIN_W<0> {
+        PIN_W::new(self)
+    }
+    #[doc = "Bit 31 - Connection"]
+    #[inline(always)]
+    pub fn connect(&mut self) -> CONNECT_W<31> {
+        CONNECT_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Pin select for SCK\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sck](index.html) module"]
+pub struct SCK_SPEC;
+impl crate::RegisterSpec for SCK_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [sck::R](R) reader structure"]
+impl crate::Readable for SCK_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [sck::W](W) writer structure"]
+impl crate::Writable for SCK_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets SCK to value 0xffff_ffff"]
+impl crate::Resettable for SCK_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0xffff_ffff
+    }
+}

vendor/nrf52820-pac/src/spi0/rxd.rs

@@ -0,0 +1,40 @@
+#[doc = "Register `RXD` reader"]
+pub struct R(crate::R<RXD_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<RXD_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<RXD_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<RXD_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `RXD` reader - RX data received. Double buffered"]
+pub type RXD_R = crate::FieldReader<u8, u8>;
+impl R {
+    #[doc = "Bits 0:7 - RX data received. Double buffered"]
+    #[inline(always)]
+    pub fn rxd(&self) -> RXD_R {
+        RXD_R::new((self.bits & 0xff) as u8)
+    }
+}
+#[doc = "RXD register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxd](index.html) module\n\nOne or more dependent resources other than the current register are immediately affected by a read operation."]
+pub struct RXD_SPEC;
+impl crate::RegisterSpec for RXD_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [rxd::R](R) reader structure"]
+impl crate::Readable for RXD_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets RXD to value 0"]
+impl crate::Resettable for RXD_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf52820-pac/src/spi0/txd.rs

@@ -0,0 +1,80 @@
+#[doc = "Register `TXD` reader"]
+pub struct R(crate::R<TXD_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<TXD_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<TXD_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<TXD_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `TXD` writer"]
+pub struct W(crate::W<TXD_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<TXD_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<TXD_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<TXD_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `TXD` reader - TX data to send. Double buffered."]
+pub type TXD_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `TXD` writer - TX data to send. Double buffered."]
+pub type TXD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, TXD_SPEC, u8, u8, 8, O>;
+impl R {
+    #[doc = "Bits 0:7 - TX data to send. Double buffered."]
+    #[inline(always)]
+    pub fn txd(&self) -> TXD_R {
+        TXD_R::new((self.bits & 0xff) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - TX data to send. Double buffered."]
+    #[inline(always)]
+    pub fn txd(&mut self) -> TXD_W<0> {
+        TXD_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "TXD register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txd](index.html) module"]
+pub struct TXD_SPEC;
+impl crate::RegisterSpec for TXD_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [txd::R](R) reader structure"]
+impl crate::Readable for TXD_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [txd::W](W) writer structure"]
+impl crate::Writable for TXD_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets TXD to value 0"]
+impl crate::Resettable for TXD_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}