feat: add display UI with splash screen, dashboard, and RSSI sparkline

Implement full SSD1306 OLED display support:
- Splash screen on boot (1.5s) with project name, version, board
- Dashboard showing radio state, config, counters, RSSI/SNR
- RSSI history sparkline (64-sample ring buffer, 2px-wide bars)
- DisplayOn/DisplayOff host commands routed via dedicated channel
- Pure render functions against generic DrawTarget (no hardware coupling)
- Display on/off control bypasses radio task entirely

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>

vendor/nrf52832-pac/src/clock/ctiv.rs

@@ -0,0 +1,80 @@
+#[doc = "Register `CTIV` reader"]
+pub struct R(crate::R<CTIV_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<CTIV_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<CTIV_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<CTIV_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `CTIV` writer"]
+pub struct W(crate::W<CTIV_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<CTIV_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<CTIV_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<CTIV_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `CTIV` reader - Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds."]
+pub type CTIV_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `CTIV` writer - Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds."]
+pub type CTIV_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTIV_SPEC, u8, u8, 7, O>;
+impl R {
+    #[doc = "Bits 0:6 - Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds."]
+    #[inline(always)]
+    pub fn ctiv(&self) -> CTIV_R {
+        CTIV_R::new((self.bits & 0x7f) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:6 - Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds."]
+    #[inline(always)]
+    pub fn ctiv(&mut self) -> CTIV_W<0> {
+        CTIV_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Calibration timer interval\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctiv](index.html) module"]
+pub struct CTIV_SPEC;
+impl crate::RegisterSpec for CTIV_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [ctiv::R](R) reader structure"]
+impl crate::Readable for CTIV_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [ctiv::W](W) writer structure"]
+impl crate::Writable for CTIV_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets CTIV to value 0"]
+impl crate::Resettable for CTIV_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf52832-pac/src/clock/events_ctto.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `EVENTS_CTTO` reader"]
+pub struct R(crate::R<EVENTS_CTTO_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<EVENTS_CTTO_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<EVENTS_CTTO_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<EVENTS_CTTO_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `EVENTS_CTTO` writer"]
+pub struct W(crate::W<EVENTS_CTTO_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<EVENTS_CTTO_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<EVENTS_CTTO_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<EVENTS_CTTO_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Calibration timer timeout\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_ctto](index.html) module"]
+pub struct EVENTS_CTTO_SPEC;
+impl crate::RegisterSpec for EVENTS_CTTO_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [events_ctto::R](R) reader structure"]
+impl crate::Readable for EVENTS_CTTO_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [events_ctto::W](W) writer structure"]
+impl crate::Writable for EVENTS_CTTO_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets EVENTS_CTTO to value 0"]
+impl crate::Resettable for EVENTS_CTTO_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf52832-pac/src/clock/events_done.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `EVENTS_DONE` reader"]
+pub struct R(crate::R<EVENTS_DONE_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<EVENTS_DONE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<EVENTS_DONE_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<EVENTS_DONE_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `EVENTS_DONE` writer"]
+pub struct W(crate::W<EVENTS_DONE_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<EVENTS_DONE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<EVENTS_DONE_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<EVENTS_DONE_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Calibration of LFCLK RC oscillator complete event\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_done](index.html) module"]
+pub struct EVENTS_DONE_SPEC;
+impl crate::RegisterSpec for EVENTS_DONE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [events_done::R](R) reader structure"]
+impl crate::Readable for EVENTS_DONE_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [events_done::W](W) writer structure"]
+impl crate::Writable for EVENTS_DONE_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets EVENTS_DONE to value 0"]
+impl crate::Resettable for EVENTS_DONE_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf52832-pac/src/clock/events_hfclkstarted.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `EVENTS_HFCLKSTARTED` reader"]
+pub struct R(crate::R<EVENTS_HFCLKSTARTED_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<EVENTS_HFCLKSTARTED_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<EVENTS_HFCLKSTARTED_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<EVENTS_HFCLKSTARTED_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `EVENTS_HFCLKSTARTED` writer"]
+pub struct W(crate::W<EVENTS_HFCLKSTARTED_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<EVENTS_HFCLKSTARTED_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<EVENTS_HFCLKSTARTED_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<EVENTS_HFCLKSTARTED_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "HFCLK oscillator started\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_hfclkstarted](index.html) module"]
+pub struct EVENTS_HFCLKSTARTED_SPEC;
+impl crate::RegisterSpec for EVENTS_HFCLKSTARTED_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [events_hfclkstarted::R](R) reader structure"]
+impl crate::Readable for EVENTS_HFCLKSTARTED_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [events_hfclkstarted::W](W) writer structure"]
+impl crate::Writable for EVENTS_HFCLKSTARTED_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets EVENTS_HFCLKSTARTED to value 0"]
+impl crate::Resettable for EVENTS_HFCLKSTARTED_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf52832-pac/src/clock/events_lfclkstarted.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `EVENTS_LFCLKSTARTED` reader"]
+pub struct R(crate::R<EVENTS_LFCLKSTARTED_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<EVENTS_LFCLKSTARTED_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<EVENTS_LFCLKSTARTED_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<EVENTS_LFCLKSTARTED_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `EVENTS_LFCLKSTARTED` writer"]
+pub struct W(crate::W<EVENTS_LFCLKSTARTED_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<EVENTS_LFCLKSTARTED_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<EVENTS_LFCLKSTARTED_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<EVENTS_LFCLKSTARTED_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "LFCLK started\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_lfclkstarted](index.html) module"]
+pub struct EVENTS_LFCLKSTARTED_SPEC;
+impl crate::RegisterSpec for EVENTS_LFCLKSTARTED_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [events_lfclkstarted::R](R) reader structure"]
+impl crate::Readable for EVENTS_LFCLKSTARTED_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [events_lfclkstarted::W](W) writer structure"]
+impl crate::Writable for EVENTS_LFCLKSTARTED_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets EVENTS_LFCLKSTARTED to value 0"]
+impl crate::Resettable for EVENTS_LFCLKSTARTED_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf52832-pac/src/clock/hfclkrun.rs

@@ -0,0 +1,74 @@
+#[doc = "Register `HFCLKRUN` reader"]
+pub struct R(crate::R<HFCLKRUN_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<HFCLKRUN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<HFCLKRUN_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<HFCLKRUN_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `STATUS` reader - HFCLKSTART task triggered or not"]
+pub type STATUS_R = crate::BitReader<STATUS_A>;
+#[doc = "HFCLKSTART task triggered or not\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum STATUS_A {
+    #[doc = "0: Task not triggered"]
+    NOT_TRIGGERED = 0,
+    #[doc = "1: Task triggered"]
+    TRIGGERED = 1,
+}
+impl From<STATUS_A> for bool {
+    #[inline(always)]
+    fn from(variant: STATUS_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl STATUS_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> STATUS_A {
+        match self.bits {
+            false => STATUS_A::NOT_TRIGGERED,
+            true => STATUS_A::TRIGGERED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `NOT_TRIGGERED`"]
+    #[inline(always)]
+    pub fn is_not_triggered(&self) -> bool {
+        *self == STATUS_A::NOT_TRIGGERED
+    }
+    #[doc = "Checks if the value of the field is `TRIGGERED`"]
+    #[inline(always)]
+    pub fn is_triggered(&self) -> bool {
+        *self == STATUS_A::TRIGGERED
+    }
+}
+impl R {
+    #[doc = "Bit 0 - HFCLKSTART task triggered or not"]
+    #[inline(always)]
+    pub fn status(&self) -> STATUS_R {
+        STATUS_R::new((self.bits & 1) != 0)
+    }
+}
+#[doc = "Status indicating that HFCLKSTART task has been triggered\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hfclkrun](index.html) module"]
+pub struct HFCLKRUN_SPEC;
+impl crate::RegisterSpec for HFCLKRUN_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [hfclkrun::R](R) reader structure"]
+impl crate::Readable for HFCLKRUN_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets HFCLKRUN to value 0"]
+impl crate::Resettable for HFCLKRUN_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf52832-pac/src/clock/hfclkstat.rs

@@ -0,0 +1,115 @@
+#[doc = "Register `HFCLKSTAT` reader"]
+pub struct R(crate::R<HFCLKSTAT_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<HFCLKSTAT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<HFCLKSTAT_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<HFCLKSTAT_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `SRC` reader - Source of HFCLK"]
+pub type SRC_R = crate::BitReader<SRC_A>;
+#[doc = "Source of HFCLK\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SRC_A {
+    #[doc = "0: 64 MHz internal oscillator (HFINT)"]
+    RC = 0,
+    #[doc = "1: 64 MHz crystal oscillator (HFXO)"]
+    XTAL = 1,
+}
+impl From<SRC_A> for bool {
+    #[inline(always)]
+    fn from(variant: SRC_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl SRC_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> SRC_A {
+        match self.bits {
+            false => SRC_A::RC,
+            true => SRC_A::XTAL,
+        }
+    }
+    #[doc = "Checks if the value of the field is `RC`"]
+    #[inline(always)]
+    pub fn is_rc(&self) -> bool {
+        *self == SRC_A::RC
+    }
+    #[doc = "Checks if the value of the field is `XTAL`"]
+    #[inline(always)]
+    pub fn is_xtal(&self) -> bool {
+        *self == SRC_A::XTAL
+    }
+}
+#[doc = "Field `STATE` reader - HFCLK state"]
+pub type STATE_R = crate::BitReader<STATE_A>;
+#[doc = "HFCLK state\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum STATE_A {
+    #[doc = "0: HFCLK not running"]
+    NOT_RUNNING = 0,
+    #[doc = "1: HFCLK running"]
+    RUNNING = 1,
+}
+impl From<STATE_A> for bool {
+    #[inline(always)]
+    fn from(variant: STATE_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl STATE_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> STATE_A {
+        match self.bits {
+            false => STATE_A::NOT_RUNNING,
+            true => STATE_A::RUNNING,
+        }
+    }
+    #[doc = "Checks if the value of the field is `NOT_RUNNING`"]
+    #[inline(always)]
+    pub fn is_not_running(&self) -> bool {
+        *self == STATE_A::NOT_RUNNING
+    }
+    #[doc = "Checks if the value of the field is `RUNNING`"]
+    #[inline(always)]
+    pub fn is_running(&self) -> bool {
+        *self == STATE_A::RUNNING
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Source of HFCLK"]
+    #[inline(always)]
+    pub fn src(&self) -> SRC_R {
+        SRC_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 16 - HFCLK state"]
+    #[inline(always)]
+    pub fn state(&self) -> STATE_R {
+        STATE_R::new(((self.bits >> 16) & 1) != 0)
+    }
+}
+#[doc = "HFCLK status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hfclkstat](index.html) module"]
+pub struct HFCLKSTAT_SPEC;
+impl crate::RegisterSpec for HFCLKSTAT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [hfclkstat::R](R) reader structure"]
+impl crate::Readable for HFCLKSTAT_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets HFCLKSTAT to value 0"]
+impl crate::Resettable for HFCLKSTAT_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf52832-pac/src/clock/intenclr.rs

@@ -0,0 +1,336 @@
+#[doc = "Register `INTENCLR` reader"]
+pub struct R(crate::R<INTENCLR_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<INTENCLR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<INTENCLR_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<INTENCLR_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `INTENCLR` writer"]
+pub struct W(crate::W<INTENCLR_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<INTENCLR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<INTENCLR_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<INTENCLR_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `HFCLKSTARTED` reader - Write '1' to Disable interrupt for HFCLKSTARTED event"]
+pub type HFCLKSTARTED_R = crate::BitReader<HFCLKSTARTED_A>;
+#[doc = "Write '1' to Disable interrupt for HFCLKSTARTED event\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum HFCLKSTARTED_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<HFCLKSTARTED_A> for bool {
+    #[inline(always)]
+    fn from(variant: HFCLKSTARTED_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl HFCLKSTARTED_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> HFCLKSTARTED_A {
+        match self.bits {
+            false => HFCLKSTARTED_A::DISABLED,
+            true => HFCLKSTARTED_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == HFCLKSTARTED_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == HFCLKSTARTED_A::ENABLED
+    }
+}
+#[doc = "Write '1' to Disable interrupt for HFCLKSTARTED event\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum HFCLKSTARTED_AW {
+    #[doc = "1: Disable"]
+    CLEAR = 1,
+}
+impl From<HFCLKSTARTED_AW> for bool {
+    #[inline(always)]
+    fn from(variant: HFCLKSTARTED_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `HFCLKSTARTED` writer - Write '1' to Disable interrupt for HFCLKSTARTED event"]
+pub type HFCLKSTARTED_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, INTENCLR_SPEC, HFCLKSTARTED_AW, O>;
+impl<'a, const O: u8> HFCLKSTARTED_W<'a, O> {
+    #[doc = "Disable"]
+    #[inline(always)]
+    pub fn clear(self) -> &'a mut W {
+        self.variant(HFCLKSTARTED_AW::CLEAR)
+    }
+}
+#[doc = "Field `LFCLKSTARTED` reader - Write '1' to Disable interrupt for LFCLKSTARTED event"]
+pub type LFCLKSTARTED_R = crate::BitReader<LFCLKSTARTED_A>;
+#[doc = "Write '1' to Disable interrupt for LFCLKSTARTED event\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum LFCLKSTARTED_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<LFCLKSTARTED_A> for bool {
+    #[inline(always)]
+    fn from(variant: LFCLKSTARTED_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl LFCLKSTARTED_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> LFCLKSTARTED_A {
+        match self.bits {
+            false => LFCLKSTARTED_A::DISABLED,
+            true => LFCLKSTARTED_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == LFCLKSTARTED_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == LFCLKSTARTED_A::ENABLED
+    }
+}
+#[doc = "Write '1' to Disable interrupt for LFCLKSTARTED event\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum LFCLKSTARTED_AW {
+    #[doc = "1: Disable"]
+    CLEAR = 1,
+}
+impl From<LFCLKSTARTED_AW> for bool {
+    #[inline(always)]
+    fn from(variant: LFCLKSTARTED_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `LFCLKSTARTED` writer - Write '1' to Disable interrupt for LFCLKSTARTED event"]
+pub type LFCLKSTARTED_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, INTENCLR_SPEC, LFCLKSTARTED_AW, O>;
+impl<'a, const O: u8> LFCLKSTARTED_W<'a, O> {
+    #[doc = "Disable"]
+    #[inline(always)]
+    pub fn clear(self) -> &'a mut W {
+        self.variant(LFCLKSTARTED_AW::CLEAR)
+    }
+}
+#[doc = "Field `DONE` reader - Write '1' to Disable interrupt for DONE event"]
+pub type DONE_R = crate::BitReader<DONE_A>;
+#[doc = "Write '1' to Disable interrupt for DONE event\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DONE_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<DONE_A> for bool {
+    #[inline(always)]
+    fn from(variant: DONE_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl DONE_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> DONE_A {
+        match self.bits {
+            false => DONE_A::DISABLED,
+            true => DONE_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == DONE_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == DONE_A::ENABLED
+    }
+}
+#[doc = "Write '1' to Disable interrupt for DONE event\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DONE_AW {
+    #[doc = "1: Disable"]
+    CLEAR = 1,
+}
+impl From<DONE_AW> for bool {
+    #[inline(always)]
+    fn from(variant: DONE_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `DONE` writer - Write '1' to Disable interrupt for DONE event"]
+pub type DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, DONE_AW, O>;
+impl<'a, const O: u8> DONE_W<'a, O> {
+    #[doc = "Disable"]
+    #[inline(always)]
+    pub fn clear(self) -> &'a mut W {
+        self.variant(DONE_AW::CLEAR)
+    }
+}
+#[doc = "Field `CTTO` reader - Write '1' to Disable interrupt for CTTO event"]
+pub type CTTO_R = crate::BitReader<CTTO_A>;
+#[doc = "Write '1' to Disable interrupt for CTTO event\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CTTO_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<CTTO_A> for bool {
+    #[inline(always)]
+    fn from(variant: CTTO_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl CTTO_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> CTTO_A {
+        match self.bits {
+            false => CTTO_A::DISABLED,
+            true => CTTO_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == CTTO_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == CTTO_A::ENABLED
+    }
+}
+#[doc = "Write '1' to Disable interrupt for CTTO event\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CTTO_AW {
+    #[doc = "1: Disable"]
+    CLEAR = 1,
+}
+impl From<CTTO_AW> for bool {
+    #[inline(always)]
+    fn from(variant: CTTO_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `CTTO` writer - Write '1' to Disable interrupt for CTTO event"]
+pub type CTTO_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, CTTO_AW, O>;
+impl<'a, const O: u8> CTTO_W<'a, O> {
+    #[doc = "Disable"]
+    #[inline(always)]
+    pub fn clear(self) -> &'a mut W {
+        self.variant(CTTO_AW::CLEAR)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Write '1' to Disable interrupt for HFCLKSTARTED event"]
+    #[inline(always)]
+    pub fn hfclkstarted(&self) -> HFCLKSTARTED_R {
+        HFCLKSTARTED_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Write '1' to Disable interrupt for LFCLKSTARTED event"]
+    #[inline(always)]
+    pub fn lfclkstarted(&self) -> LFCLKSTARTED_R {
+        LFCLKSTARTED_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Write '1' to Disable interrupt for DONE event"]
+    #[inline(always)]
+    pub fn done(&self) -> DONE_R {
+        DONE_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Write '1' to Disable interrupt for CTTO event"]
+    #[inline(always)]
+    pub fn ctto(&self) -> CTTO_R {
+        CTTO_R::new(((self.bits >> 4) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Write '1' to Disable interrupt for HFCLKSTARTED event"]
+    #[inline(always)]
+    pub fn hfclkstarted(&mut self) -> HFCLKSTARTED_W<0> {
+        HFCLKSTARTED_W::new(self)
+    }
+    #[doc = "Bit 1 - Write '1' to Disable interrupt for LFCLKSTARTED event"]
+    #[inline(always)]
+    pub fn lfclkstarted(&mut self) -> LFCLKSTARTED_W<1> {
+        LFCLKSTARTED_W::new(self)
+    }
+    #[doc = "Bit 3 - Write '1' to Disable interrupt for DONE event"]
+    #[inline(always)]
+    pub fn done(&mut self) -> DONE_W<3> {
+        DONE_W::new(self)
+    }
+    #[doc = "Bit 4 - Write '1' to Disable interrupt for CTTO event"]
+    #[inline(always)]
+    pub fn ctto(&mut self) -> CTTO_W<4> {
+        CTTO_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Disable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"]
+pub struct INTENCLR_SPEC;
+impl crate::RegisterSpec for INTENCLR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [intenclr::R](R) reader structure"]
+impl crate::Readable for INTENCLR_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"]
+impl crate::Writable for INTENCLR_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets INTENCLR to value 0"]
+impl crate::Resettable for INTENCLR_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf52832-pac/src/clock/intenset.rs

@@ -0,0 +1,336 @@
+#[doc = "Register `INTENSET` reader"]
+pub struct R(crate::R<INTENSET_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<INTENSET_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<INTENSET_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<INTENSET_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `INTENSET` writer"]
+pub struct W(crate::W<INTENSET_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<INTENSET_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<INTENSET_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<INTENSET_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `HFCLKSTARTED` reader - Write '1' to Enable interrupt for HFCLKSTARTED event"]
+pub type HFCLKSTARTED_R = crate::BitReader<HFCLKSTARTED_A>;
+#[doc = "Write '1' to Enable interrupt for HFCLKSTARTED event\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum HFCLKSTARTED_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<HFCLKSTARTED_A> for bool {
+    #[inline(always)]
+    fn from(variant: HFCLKSTARTED_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl HFCLKSTARTED_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> HFCLKSTARTED_A {
+        match self.bits {
+            false => HFCLKSTARTED_A::DISABLED,
+            true => HFCLKSTARTED_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == HFCLKSTARTED_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == HFCLKSTARTED_A::ENABLED
+    }
+}
+#[doc = "Write '1' to Enable interrupt for HFCLKSTARTED event\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum HFCLKSTARTED_AW {
+    #[doc = "1: Enable"]
+    SET = 1,
+}
+impl From<HFCLKSTARTED_AW> for bool {
+    #[inline(always)]
+    fn from(variant: HFCLKSTARTED_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `HFCLKSTARTED` writer - Write '1' to Enable interrupt for HFCLKSTARTED event"]
+pub type HFCLKSTARTED_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, INTENSET_SPEC, HFCLKSTARTED_AW, O>;
+impl<'a, const O: u8> HFCLKSTARTED_W<'a, O> {
+    #[doc = "Enable"]
+    #[inline(always)]
+    pub fn set(self) -> &'a mut W {
+        self.variant(HFCLKSTARTED_AW::SET)
+    }
+}
+#[doc = "Field `LFCLKSTARTED` reader - Write '1' to Enable interrupt for LFCLKSTARTED event"]
+pub type LFCLKSTARTED_R = crate::BitReader<LFCLKSTARTED_A>;
+#[doc = "Write '1' to Enable interrupt for LFCLKSTARTED event\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum LFCLKSTARTED_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<LFCLKSTARTED_A> for bool {
+    #[inline(always)]
+    fn from(variant: LFCLKSTARTED_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl LFCLKSTARTED_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> LFCLKSTARTED_A {
+        match self.bits {
+            false => LFCLKSTARTED_A::DISABLED,
+            true => LFCLKSTARTED_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == LFCLKSTARTED_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == LFCLKSTARTED_A::ENABLED
+    }
+}
+#[doc = "Write '1' to Enable interrupt for LFCLKSTARTED event\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum LFCLKSTARTED_AW {
+    #[doc = "1: Enable"]
+    SET = 1,
+}
+impl From<LFCLKSTARTED_AW> for bool {
+    #[inline(always)]
+    fn from(variant: LFCLKSTARTED_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `LFCLKSTARTED` writer - Write '1' to Enable interrupt for LFCLKSTARTED event"]
+pub type LFCLKSTARTED_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, INTENSET_SPEC, LFCLKSTARTED_AW, O>;
+impl<'a, const O: u8> LFCLKSTARTED_W<'a, O> {
+    #[doc = "Enable"]
+    #[inline(always)]
+    pub fn set(self) -> &'a mut W {
+        self.variant(LFCLKSTARTED_AW::SET)
+    }
+}
+#[doc = "Field `DONE` reader - Write '1' to Enable interrupt for DONE event"]
+pub type DONE_R = crate::BitReader<DONE_A>;
+#[doc = "Write '1' to Enable interrupt for DONE event\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DONE_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<DONE_A> for bool {
+    #[inline(always)]
+    fn from(variant: DONE_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl DONE_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> DONE_A {
+        match self.bits {
+            false => DONE_A::DISABLED,
+            true => DONE_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == DONE_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == DONE_A::ENABLED
+    }
+}
+#[doc = "Write '1' to Enable interrupt for DONE event\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DONE_AW {
+    #[doc = "1: Enable"]
+    SET = 1,
+}
+impl From<DONE_AW> for bool {
+    #[inline(always)]
+    fn from(variant: DONE_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `DONE` writer - Write '1' to Enable interrupt for DONE event"]
+pub type DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, DONE_AW, O>;
+impl<'a, const O: u8> DONE_W<'a, O> {
+    #[doc = "Enable"]
+    #[inline(always)]
+    pub fn set(self) -> &'a mut W {
+        self.variant(DONE_AW::SET)
+    }
+}
+#[doc = "Field `CTTO` reader - Write '1' to Enable interrupt for CTTO event"]
+pub type CTTO_R = crate::BitReader<CTTO_A>;
+#[doc = "Write '1' to Enable interrupt for CTTO event\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CTTO_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<CTTO_A> for bool {
+    #[inline(always)]
+    fn from(variant: CTTO_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl CTTO_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> CTTO_A {
+        match self.bits {
+            false => CTTO_A::DISABLED,
+            true => CTTO_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == CTTO_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == CTTO_A::ENABLED
+    }
+}
+#[doc = "Write '1' to Enable interrupt for CTTO event\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CTTO_AW {
+    #[doc = "1: Enable"]
+    SET = 1,
+}
+impl From<CTTO_AW> for bool {
+    #[inline(always)]
+    fn from(variant: CTTO_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `CTTO` writer - Write '1' to Enable interrupt for CTTO event"]
+pub type CTTO_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, CTTO_AW, O>;
+impl<'a, const O: u8> CTTO_W<'a, O> {
+    #[doc = "Enable"]
+    #[inline(always)]
+    pub fn set(self) -> &'a mut W {
+        self.variant(CTTO_AW::SET)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Write '1' to Enable interrupt for HFCLKSTARTED event"]
+    #[inline(always)]
+    pub fn hfclkstarted(&self) -> HFCLKSTARTED_R {
+        HFCLKSTARTED_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Write '1' to Enable interrupt for LFCLKSTARTED event"]
+    #[inline(always)]
+    pub fn lfclkstarted(&self) -> LFCLKSTARTED_R {
+        LFCLKSTARTED_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Write '1' to Enable interrupt for DONE event"]
+    #[inline(always)]
+    pub fn done(&self) -> DONE_R {
+        DONE_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Write '1' to Enable interrupt for CTTO event"]
+    #[inline(always)]
+    pub fn ctto(&self) -> CTTO_R {
+        CTTO_R::new(((self.bits >> 4) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Write '1' to Enable interrupt for HFCLKSTARTED event"]
+    #[inline(always)]
+    pub fn hfclkstarted(&mut self) -> HFCLKSTARTED_W<0> {
+        HFCLKSTARTED_W::new(self)
+    }
+    #[doc = "Bit 1 - Write '1' to Enable interrupt for LFCLKSTARTED event"]
+    #[inline(always)]
+    pub fn lfclkstarted(&mut self) -> LFCLKSTARTED_W<1> {
+        LFCLKSTARTED_W::new(self)
+    }
+    #[doc = "Bit 3 - Write '1' to Enable interrupt for DONE event"]
+    #[inline(always)]
+    pub fn done(&mut self) -> DONE_W<3> {
+        DONE_W::new(self)
+    }
+    #[doc = "Bit 4 - Write '1' to Enable interrupt for CTTO event"]
+    #[inline(always)]
+    pub fn ctto(&mut self) -> CTTO_W<4> {
+        CTTO_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Enable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"]
+pub struct INTENSET_SPEC;
+impl crate::RegisterSpec for INTENSET_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [intenset::R](R) reader structure"]
+impl crate::Readable for INTENSET_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"]
+impl crate::Writable for INTENSET_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets INTENSET to value 0"]
+impl crate::Resettable for INTENSET_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf52832-pac/src/clock/lfclkrun.rs

@@ -0,0 +1,74 @@
+#[doc = "Register `LFCLKRUN` reader"]
+pub struct R(crate::R<LFCLKRUN_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<LFCLKRUN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<LFCLKRUN_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<LFCLKRUN_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `STATUS` reader - LFCLKSTART task triggered or not"]
+pub type STATUS_R = crate::BitReader<STATUS_A>;
+#[doc = "LFCLKSTART task triggered or not\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum STATUS_A {
+    #[doc = "0: Task not triggered"]
+    NOT_TRIGGERED = 0,
+    #[doc = "1: Task triggered"]
+    TRIGGERED = 1,
+}
+impl From<STATUS_A> for bool {
+    #[inline(always)]
+    fn from(variant: STATUS_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl STATUS_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> STATUS_A {
+        match self.bits {
+            false => STATUS_A::NOT_TRIGGERED,
+            true => STATUS_A::TRIGGERED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `NOT_TRIGGERED`"]
+    #[inline(always)]
+    pub fn is_not_triggered(&self) -> bool {
+        *self == STATUS_A::NOT_TRIGGERED
+    }
+    #[doc = "Checks if the value of the field is `TRIGGERED`"]
+    #[inline(always)]
+    pub fn is_triggered(&self) -> bool {
+        *self == STATUS_A::TRIGGERED
+    }
+}
+impl R {
+    #[doc = "Bit 0 - LFCLKSTART task triggered or not"]
+    #[inline(always)]
+    pub fn status(&self) -> STATUS_R {
+        STATUS_R::new((self.bits & 1) != 0)
+    }
+}
+#[doc = "Status indicating that LFCLKSTART task has been triggered\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lfclkrun](index.html) module"]
+pub struct LFCLKRUN_SPEC;
+impl crate::RegisterSpec for LFCLKRUN_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [lfclkrun::R](R) reader structure"]
+impl crate::Readable for LFCLKRUN_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets LFCLKRUN to value 0"]
+impl crate::Resettable for LFCLKRUN_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf52832-pac/src/clock/lfclksrc.rs

@@ -0,0 +1,261 @@
+#[doc = "Register `LFCLKSRC` reader"]
+pub struct R(crate::R<LFCLKSRC_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<LFCLKSRC_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<LFCLKSRC_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<LFCLKSRC_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `LFCLKSRC` writer"]
+pub struct W(crate::W<LFCLKSRC_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<LFCLKSRC_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<LFCLKSRC_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<LFCLKSRC_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `SRC` reader - Clock source"]
+pub type SRC_R = crate::FieldReader<u8, SRC_A>;
+#[doc = "Clock source\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum SRC_A {
+    #[doc = "0: 32.768 kHz RC oscillator"]
+    RC = 0,
+    #[doc = "1: 32.768 kHz crystal oscillator"]
+    XTAL = 1,
+    #[doc = "2: 32.768 kHz synthesized from HFCLK"]
+    SYNTH = 2,
+}
+impl From<SRC_A> for u8 {
+    #[inline(always)]
+    fn from(variant: SRC_A) -> Self {
+        variant as _
+    }
+}
+impl SRC_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<SRC_A> {
+        match self.bits {
+            0 => Some(SRC_A::RC),
+            1 => Some(SRC_A::XTAL),
+            2 => Some(SRC_A::SYNTH),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `RC`"]
+    #[inline(always)]
+    pub fn is_rc(&self) -> bool {
+        *self == SRC_A::RC
+    }
+    #[doc = "Checks if the value of the field is `XTAL`"]
+    #[inline(always)]
+    pub fn is_xtal(&self) -> bool {
+        *self == SRC_A::XTAL
+    }
+    #[doc = "Checks if the value of the field is `SYNTH`"]
+    #[inline(always)]
+    pub fn is_synth(&self) -> bool {
+        *self == SRC_A::SYNTH
+    }
+}
+#[doc = "Field `SRC` writer - Clock source"]
+pub type SRC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, LFCLKSRC_SPEC, u8, SRC_A, 2, O>;
+impl<'a, const O: u8> SRC_W<'a, O> {
+    #[doc = "32.768 kHz RC oscillator"]
+    #[inline(always)]
+    pub fn rc(self) -> &'a mut W {
+        self.variant(SRC_A::RC)
+    }
+    #[doc = "32.768 kHz crystal oscillator"]
+    #[inline(always)]
+    pub fn xtal(self) -> &'a mut W {
+        self.variant(SRC_A::XTAL)
+    }
+    #[doc = "32.768 kHz synthesized from HFCLK"]
+    #[inline(always)]
+    pub fn synth(self) -> &'a mut W {
+        self.variant(SRC_A::SYNTH)
+    }
+}
+#[doc = "Field `BYPASS` reader - Enable or disable bypass of LFCLK crystal oscillator with external clock source"]
+pub type BYPASS_R = crate::BitReader<BYPASS_A>;
+#[doc = "Enable or disable bypass of LFCLK crystal oscillator with external clock source\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum BYPASS_A {
+    #[doc = "0: Disable (use with Xtal or low-swing external source)"]
+    DISABLED = 0,
+    #[doc = "1: Enable (use with rail-to-rail external source)"]
+    ENABLED = 1,
+}
+impl From<BYPASS_A> for bool {
+    #[inline(always)]
+    fn from(variant: BYPASS_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl BYPASS_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> BYPASS_A {
+        match self.bits {
+            false => BYPASS_A::DISABLED,
+            true => BYPASS_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == BYPASS_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == BYPASS_A::ENABLED
+    }
+}
+#[doc = "Field `BYPASS` writer - Enable or disable bypass of LFCLK crystal oscillator with external clock source"]
+pub type BYPASS_W<'a, const O: u8> = crate::BitWriter<'a, u32, LFCLKSRC_SPEC, BYPASS_A, O>;
+impl<'a, const O: u8> BYPASS_W<'a, O> {
+    #[doc = "Disable (use with Xtal or low-swing external source)"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(BYPASS_A::DISABLED)
+    }
+    #[doc = "Enable (use with rail-to-rail external source)"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(BYPASS_A::ENABLED)
+    }
+}
+#[doc = "Field `EXTERNAL` reader - Enable or disable external source for LFCLK"]
+pub type EXTERNAL_R = crate::BitReader<EXTERNAL_A>;
+#[doc = "Enable or disable external source for LFCLK\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum EXTERNAL_A {
+    #[doc = "0: Disable external source (use with Xtal)"]
+    DISABLED = 0,
+    #[doc = "1: Enable use of external source instead of Xtal (SRC needs to be set to Xtal)"]
+    ENABLED = 1,
+}
+impl From<EXTERNAL_A> for bool {
+    #[inline(always)]
+    fn from(variant: EXTERNAL_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl EXTERNAL_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> EXTERNAL_A {
+        match self.bits {
+            false => EXTERNAL_A::DISABLED,
+            true => EXTERNAL_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == EXTERNAL_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == EXTERNAL_A::ENABLED
+    }
+}
+#[doc = "Field `EXTERNAL` writer - Enable or disable external source for LFCLK"]
+pub type EXTERNAL_W<'a, const O: u8> = crate::BitWriter<'a, u32, LFCLKSRC_SPEC, EXTERNAL_A, O>;
+impl<'a, const O: u8> EXTERNAL_W<'a, O> {
+    #[doc = "Disable external source (use with Xtal)"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(EXTERNAL_A::DISABLED)
+    }
+    #[doc = "Enable use of external source instead of Xtal (SRC needs to be set to Xtal)"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(EXTERNAL_A::ENABLED)
+    }
+}
+impl R {
+    #[doc = "Bits 0:1 - Clock source"]
+    #[inline(always)]
+    pub fn src(&self) -> SRC_R {
+        SRC_R::new((self.bits & 3) as u8)
+    }
+    #[doc = "Bit 16 - Enable or disable bypass of LFCLK crystal oscillator with external clock source"]
+    #[inline(always)]
+    pub fn bypass(&self) -> BYPASS_R {
+        BYPASS_R::new(((self.bits >> 16) & 1) != 0)
+    }
+    #[doc = "Bit 17 - Enable or disable external source for LFCLK"]
+    #[inline(always)]
+    pub fn external(&self) -> EXTERNAL_R {
+        EXTERNAL_R::new(((self.bits >> 17) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:1 - Clock source"]
+    #[inline(always)]
+    pub fn src(&mut self) -> SRC_W<0> {
+        SRC_W::new(self)
+    }
+    #[doc = "Bit 16 - Enable or disable bypass of LFCLK crystal oscillator with external clock source"]
+    #[inline(always)]
+    pub fn bypass(&mut self) -> BYPASS_W<16> {
+        BYPASS_W::new(self)
+    }
+    #[doc = "Bit 17 - Enable or disable external source for LFCLK"]
+    #[inline(always)]
+    pub fn external(&mut self) -> EXTERNAL_W<17> {
+        EXTERNAL_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Clock source for the LFCLK\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lfclksrc](index.html) module"]
+pub struct LFCLKSRC_SPEC;
+impl crate::RegisterSpec for LFCLKSRC_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [lfclksrc::R](R) reader structure"]
+impl crate::Readable for LFCLKSRC_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [lfclksrc::W](W) writer structure"]
+impl crate::Writable for LFCLKSRC_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets LFCLKSRC to value 0"]
+impl crate::Resettable for LFCLKSRC_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf52832-pac/src/clock/lfclksrccopy.rs

@@ -0,0 +1,84 @@
+#[doc = "Register `LFCLKSRCCOPY` reader"]
+pub struct R(crate::R<LFCLKSRCCOPY_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<LFCLKSRCCOPY_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<LFCLKSRCCOPY_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<LFCLKSRCCOPY_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `SRC` reader - Clock source"]
+pub type SRC_R = crate::FieldReader<u8, SRC_A>;
+#[doc = "Clock source\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum SRC_A {
+    #[doc = "0: 32.768 kHz RC oscillator"]
+    RC = 0,
+    #[doc = "1: 32.768 kHz crystal oscillator"]
+    XTAL = 1,
+    #[doc = "2: 32.768 kHz synthesized from HFCLK"]
+    SYNTH = 2,
+}
+impl From<SRC_A> for u8 {
+    #[inline(always)]
+    fn from(variant: SRC_A) -> Self {
+        variant as _
+    }
+}
+impl SRC_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<SRC_A> {
+        match self.bits {
+            0 => Some(SRC_A::RC),
+            1 => Some(SRC_A::XTAL),
+            2 => Some(SRC_A::SYNTH),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `RC`"]
+    #[inline(always)]
+    pub fn is_rc(&self) -> bool {
+        *self == SRC_A::RC
+    }
+    #[doc = "Checks if the value of the field is `XTAL`"]
+    #[inline(always)]
+    pub fn is_xtal(&self) -> bool {
+        *self == SRC_A::XTAL
+    }
+    #[doc = "Checks if the value of the field is `SYNTH`"]
+    #[inline(always)]
+    pub fn is_synth(&self) -> bool {
+        *self == SRC_A::SYNTH
+    }
+}
+impl R {
+    #[doc = "Bits 0:1 - Clock source"]
+    #[inline(always)]
+    pub fn src(&self) -> SRC_R {
+        SRC_R::new((self.bits & 3) as u8)
+    }
+}
+#[doc = "Copy of LFCLKSRC register, set when LFCLKSTART task was triggered\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lfclksrccopy](index.html) module"]
+pub struct LFCLKSRCCOPY_SPEC;
+impl crate::RegisterSpec for LFCLKSRCCOPY_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [lfclksrccopy::R](R) reader structure"]
+impl crate::Readable for LFCLKSRCCOPY_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets LFCLKSRCCOPY to value 0"]
+impl crate::Resettable for LFCLKSRCCOPY_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf52832-pac/src/clock/lfclkstat.rs

@@ -0,0 +1,125 @@
+#[doc = "Register `LFCLKSTAT` reader"]
+pub struct R(crate::R<LFCLKSTAT_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<LFCLKSTAT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<LFCLKSTAT_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<LFCLKSTAT_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `SRC` reader - Source of LFCLK"]
+pub type SRC_R = crate::FieldReader<u8, SRC_A>;
+#[doc = "Source of LFCLK\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum SRC_A {
+    #[doc = "0: 32.768 kHz RC oscillator"]
+    RC = 0,
+    #[doc = "1: 32.768 kHz crystal oscillator"]
+    XTAL = 1,
+    #[doc = "2: 32.768 kHz synthesized from HFCLK"]
+    SYNTH = 2,
+}
+impl From<SRC_A> for u8 {
+    #[inline(always)]
+    fn from(variant: SRC_A) -> Self {
+        variant as _
+    }
+}
+impl SRC_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<SRC_A> {
+        match self.bits {
+            0 => Some(SRC_A::RC),
+            1 => Some(SRC_A::XTAL),
+            2 => Some(SRC_A::SYNTH),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `RC`"]
+    #[inline(always)]
+    pub fn is_rc(&self) -> bool {
+        *self == SRC_A::RC
+    }
+    #[doc = "Checks if the value of the field is `XTAL`"]
+    #[inline(always)]
+    pub fn is_xtal(&self) -> bool {
+        *self == SRC_A::XTAL
+    }
+    #[doc = "Checks if the value of the field is `SYNTH`"]
+    #[inline(always)]
+    pub fn is_synth(&self) -> bool {
+        *self == SRC_A::SYNTH
+    }
+}
+#[doc = "Field `STATE` reader - LFCLK state"]
+pub type STATE_R = crate::BitReader<STATE_A>;
+#[doc = "LFCLK state\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum STATE_A {
+    #[doc = "0: LFCLK not running"]
+    NOT_RUNNING = 0,
+    #[doc = "1: LFCLK running"]
+    RUNNING = 1,
+}
+impl From<STATE_A> for bool {
+    #[inline(always)]
+    fn from(variant: STATE_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl STATE_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> STATE_A {
+        match self.bits {
+            false => STATE_A::NOT_RUNNING,
+            true => STATE_A::RUNNING,
+        }
+    }
+    #[doc = "Checks if the value of the field is `NOT_RUNNING`"]
+    #[inline(always)]
+    pub fn is_not_running(&self) -> bool {
+        *self == STATE_A::NOT_RUNNING
+    }
+    #[doc = "Checks if the value of the field is `RUNNING`"]
+    #[inline(always)]
+    pub fn is_running(&self) -> bool {
+        *self == STATE_A::RUNNING
+    }
+}
+impl R {
+    #[doc = "Bits 0:1 - Source of LFCLK"]
+    #[inline(always)]
+    pub fn src(&self) -> SRC_R {
+        SRC_R::new((self.bits & 3) as u8)
+    }
+    #[doc = "Bit 16 - LFCLK state"]
+    #[inline(always)]
+    pub fn state(&self) -> STATE_R {
+        STATE_R::new(((self.bits >> 16) & 1) != 0)
+    }
+}
+#[doc = "LFCLK status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lfclkstat](index.html) module"]
+pub struct LFCLKSTAT_SPEC;
+impl crate::RegisterSpec for LFCLKSTAT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [lfclkstat::R](R) reader structure"]
+impl crate::Readable for LFCLKSTAT_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets LFCLKSTAT to value 0"]
+impl crate::Resettable for LFCLKSTAT_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf52832-pac/src/clock/tasks_cal.rs

@@ -0,0 +1,45 @@
+#[doc = "Register `TASKS_CAL` writer"]
+pub struct W(crate::W<TASKS_CAL_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<TASKS_CAL_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<TASKS_CAL_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<TASKS_CAL_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Start calibration of LFRC oscillator\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_cal](index.html) module"]
+pub struct TASKS_CAL_SPEC;
+impl crate::RegisterSpec for TASKS_CAL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [tasks_cal::W](W) writer structure"]
+impl crate::Writable for TASKS_CAL_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets TASKS_CAL to value 0"]
+impl crate::Resettable for TASKS_CAL_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf52832-pac/src/clock/tasks_ctstart.rs

@@ -0,0 +1,45 @@
+#[doc = "Register `TASKS_CTSTART` writer"]
+pub struct W(crate::W<TASKS_CTSTART_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<TASKS_CTSTART_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<TASKS_CTSTART_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<TASKS_CTSTART_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Start calibration timer\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_ctstart](index.html) module"]
+pub struct TASKS_CTSTART_SPEC;
+impl crate::RegisterSpec for TASKS_CTSTART_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [tasks_ctstart::W](W) writer structure"]
+impl crate::Writable for TASKS_CTSTART_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets TASKS_CTSTART to value 0"]
+impl crate::Resettable for TASKS_CTSTART_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf52832-pac/src/clock/tasks_ctstop.rs

@@ -0,0 +1,45 @@
+#[doc = "Register `TASKS_CTSTOP` writer"]
+pub struct W(crate::W<TASKS_CTSTOP_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<TASKS_CTSTOP_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<TASKS_CTSTOP_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<TASKS_CTSTOP_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Stop calibration timer\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_ctstop](index.html) module"]
+pub struct TASKS_CTSTOP_SPEC;
+impl crate::RegisterSpec for TASKS_CTSTOP_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [tasks_ctstop::W](W) writer structure"]
+impl crate::Writable for TASKS_CTSTOP_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets TASKS_CTSTOP to value 0"]
+impl crate::Resettable for TASKS_CTSTOP_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf52832-pac/src/clock/tasks_hfclkstart.rs

@@ -0,0 +1,45 @@
+#[doc = "Register `TASKS_HFCLKSTART` writer"]
+pub struct W(crate::W<TASKS_HFCLKSTART_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<TASKS_HFCLKSTART_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<TASKS_HFCLKSTART_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<TASKS_HFCLKSTART_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Start HFCLK crystal oscillator\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_hfclkstart](index.html) module"]
+pub struct TASKS_HFCLKSTART_SPEC;
+impl crate::RegisterSpec for TASKS_HFCLKSTART_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [tasks_hfclkstart::W](W) writer structure"]
+impl crate::Writable for TASKS_HFCLKSTART_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets TASKS_HFCLKSTART to value 0"]
+impl crate::Resettable for TASKS_HFCLKSTART_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf52832-pac/src/clock/tasks_hfclkstop.rs

@@ -0,0 +1,45 @@
+#[doc = "Register `TASKS_HFCLKSTOP` writer"]
+pub struct W(crate::W<TASKS_HFCLKSTOP_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<TASKS_HFCLKSTOP_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<TASKS_HFCLKSTOP_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<TASKS_HFCLKSTOP_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Stop HFCLK crystal oscillator\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_hfclkstop](index.html) module"]
+pub struct TASKS_HFCLKSTOP_SPEC;
+impl crate::RegisterSpec for TASKS_HFCLKSTOP_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [tasks_hfclkstop::W](W) writer structure"]
+impl crate::Writable for TASKS_HFCLKSTOP_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets TASKS_HFCLKSTOP to value 0"]
+impl crate::Resettable for TASKS_HFCLKSTOP_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf52832-pac/src/clock/tasks_lfclkstart.rs

@@ -0,0 +1,45 @@
+#[doc = "Register `TASKS_LFCLKSTART` writer"]
+pub struct W(crate::W<TASKS_LFCLKSTART_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<TASKS_LFCLKSTART_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<TASKS_LFCLKSTART_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<TASKS_LFCLKSTART_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Start LFCLK source\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_lfclkstart](index.html) module"]
+pub struct TASKS_LFCLKSTART_SPEC;
+impl crate::RegisterSpec for TASKS_LFCLKSTART_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [tasks_lfclkstart::W](W) writer structure"]
+impl crate::Writable for TASKS_LFCLKSTART_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets TASKS_LFCLKSTART to value 0"]
+impl crate::Resettable for TASKS_LFCLKSTART_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf52832-pac/src/clock/tasks_lfclkstop.rs

@@ -0,0 +1,45 @@
+#[doc = "Register `TASKS_LFCLKSTOP` writer"]
+pub struct W(crate::W<TASKS_LFCLKSTOP_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<TASKS_LFCLKSTOP_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<TASKS_LFCLKSTOP_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<TASKS_LFCLKSTOP_SPEC>) -> Self {
+        W(writer)
+    }
+}
+impl W {
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Stop LFCLK source\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_lfclkstop](index.html) module"]
+pub struct TASKS_LFCLKSTOP_SPEC;
+impl crate::RegisterSpec for TASKS_LFCLKSTOP_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [tasks_lfclkstop::W](W) writer structure"]
+impl crate::Writable for TASKS_LFCLKSTOP_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets TASKS_LFCLKSTOP to value 0"]
+impl crate::Resettable for TASKS_LFCLKSTOP_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf52832-pac/src/clock/traceconfig.rs

@@ -0,0 +1,231 @@
+#[doc = "Register `TRACECONFIG` reader"]
+pub struct R(crate::R<TRACECONFIG_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<TRACECONFIG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<TRACECONFIG_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<TRACECONFIG_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `TRACECONFIG` writer"]
+pub struct W(crate::W<TRACECONFIG_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<TRACECONFIG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<TRACECONFIG_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<TRACECONFIG_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `TRACEPORTSPEED` reader - Speed of Trace Port clock. Note that the TRACECLK pin will output this clock divided by two."]
+pub type TRACEPORTSPEED_R = crate::FieldReader<u8, TRACEPORTSPEED_A>;
+#[doc = "Speed of Trace Port clock. Note that the TRACECLK pin will output this clock divided by two.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum TRACEPORTSPEED_A {
+    #[doc = "0: 32 MHz Trace Port clock (TRACECLK = 16 MHz)"]
+    _32MHZ = 0,
+    #[doc = "1: 16 MHz Trace Port clock (TRACECLK = 8 MHz)"]
+    _16MHZ = 1,
+    #[doc = "2: 8 MHz Trace Port clock (TRACECLK = 4 MHz)"]
+    _8MHZ = 2,
+    #[doc = "3: 4 MHz Trace Port clock (TRACECLK = 2 MHz)"]
+    _4MHZ = 3,
+}
+impl From<TRACEPORTSPEED_A> for u8 {
+    #[inline(always)]
+    fn from(variant: TRACEPORTSPEED_A) -> Self {
+        variant as _
+    }
+}
+impl TRACEPORTSPEED_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> TRACEPORTSPEED_A {
+        match self.bits {
+            0 => TRACEPORTSPEED_A::_32MHZ,
+            1 => TRACEPORTSPEED_A::_16MHZ,
+            2 => TRACEPORTSPEED_A::_8MHZ,
+            3 => TRACEPORTSPEED_A::_4MHZ,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `_32MHZ`"]
+    #[inline(always)]
+    pub fn is_32mhz(&self) -> bool {
+        *self == TRACEPORTSPEED_A::_32MHZ
+    }
+    #[doc = "Checks if the value of the field is `_16MHZ`"]
+    #[inline(always)]
+    pub fn is_16mhz(&self) -> bool {
+        *self == TRACEPORTSPEED_A::_16MHZ
+    }
+    #[doc = "Checks if the value of the field is `_8MHZ`"]
+    #[inline(always)]
+    pub fn is_8mhz(&self) -> bool {
+        *self == TRACEPORTSPEED_A::_8MHZ
+    }
+    #[doc = "Checks if the value of the field is `_4MHZ`"]
+    #[inline(always)]
+    pub fn is_4mhz(&self) -> bool {
+        *self == TRACEPORTSPEED_A::_4MHZ
+    }
+}
+#[doc = "Field `TRACEPORTSPEED` writer - Speed of Trace Port clock. Note that the TRACECLK pin will output this clock divided by two."]
+pub type TRACEPORTSPEED_W<'a, const O: u8> =
+    crate::FieldWriterSafe<'a, u32, TRACECONFIG_SPEC, u8, TRACEPORTSPEED_A, 2, O>;
+impl<'a, const O: u8> TRACEPORTSPEED_W<'a, O> {
+    #[doc = "32 MHz Trace Port clock (TRACECLK = 16 MHz)"]
+    #[inline(always)]
+    pub fn _32mhz(self) -> &'a mut W {
+        self.variant(TRACEPORTSPEED_A::_32MHZ)
+    }
+    #[doc = "16 MHz Trace Port clock (TRACECLK = 8 MHz)"]
+    #[inline(always)]
+    pub fn _16mhz(self) -> &'a mut W {
+        self.variant(TRACEPORTSPEED_A::_16MHZ)
+    }
+    #[doc = "8 MHz Trace Port clock (TRACECLK = 4 MHz)"]
+    #[inline(always)]
+    pub fn _8mhz(self) -> &'a mut W {
+        self.variant(TRACEPORTSPEED_A::_8MHZ)
+    }
+    #[doc = "4 MHz Trace Port clock (TRACECLK = 2 MHz)"]
+    #[inline(always)]
+    pub fn _4mhz(self) -> &'a mut W {
+        self.variant(TRACEPORTSPEED_A::_4MHZ)
+    }
+}
+#[doc = "Field `TRACEMUX` reader - Pin multiplexing of trace signals."]
+pub type TRACEMUX_R = crate::FieldReader<u8, TRACEMUX_A>;
+#[doc = "Pin multiplexing of trace signals.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum TRACEMUX_A {
+    #[doc = "0: GPIOs multiplexed onto all trace-pins"]
+    GPIO = 0,
+    #[doc = "1: SWO multiplexed onto P0.18, GPIO multiplexed onto other trace pins"]
+    SERIAL = 1,
+    #[doc = "2: TRACECLK and TRACEDATA multiplexed onto P0.20, P0.18, P0.16, P0.15 and P0.14."]
+    PARALLEL = 2,
+}
+impl From<TRACEMUX_A> for u8 {
+    #[inline(always)]
+    fn from(variant: TRACEMUX_A) -> Self {
+        variant as _
+    }
+}
+impl TRACEMUX_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<TRACEMUX_A> {
+        match self.bits {
+            0 => Some(TRACEMUX_A::GPIO),
+            1 => Some(TRACEMUX_A::SERIAL),
+            2 => Some(TRACEMUX_A::PARALLEL),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `GPIO`"]
+    #[inline(always)]
+    pub fn is_gpio(&self) -> bool {
+        *self == TRACEMUX_A::GPIO
+    }
+    #[doc = "Checks if the value of the field is `SERIAL`"]
+    #[inline(always)]
+    pub fn is_serial(&self) -> bool {
+        *self == TRACEMUX_A::SERIAL
+    }
+    #[doc = "Checks if the value of the field is `PARALLEL`"]
+    #[inline(always)]
+    pub fn is_parallel(&self) -> bool {
+        *self == TRACEMUX_A::PARALLEL
+    }
+}
+#[doc = "Field `TRACEMUX` writer - Pin multiplexing of trace signals."]
+pub type TRACEMUX_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u32, TRACECONFIG_SPEC, u8, TRACEMUX_A, 2, O>;
+impl<'a, const O: u8> TRACEMUX_W<'a, O> {
+    #[doc = "GPIOs multiplexed onto all trace-pins"]
+    #[inline(always)]
+    pub fn gpio(self) -> &'a mut W {
+        self.variant(TRACEMUX_A::GPIO)
+    }
+    #[doc = "SWO multiplexed onto P0.18, GPIO multiplexed onto other trace pins"]
+    #[inline(always)]
+    pub fn serial(self) -> &'a mut W {
+        self.variant(TRACEMUX_A::SERIAL)
+    }
+    #[doc = "TRACECLK and TRACEDATA multiplexed onto P0.20, P0.18, P0.16, P0.15 and P0.14."]
+    #[inline(always)]
+    pub fn parallel(self) -> &'a mut W {
+        self.variant(TRACEMUX_A::PARALLEL)
+    }
+}
+impl R {
+    #[doc = "Bits 0:1 - Speed of Trace Port clock. Note that the TRACECLK pin will output this clock divided by two."]
+    #[inline(always)]
+    pub fn traceportspeed(&self) -> TRACEPORTSPEED_R {
+        TRACEPORTSPEED_R::new((self.bits & 3) as u8)
+    }
+    #[doc = "Bits 16:17 - Pin multiplexing of trace signals."]
+    #[inline(always)]
+    pub fn tracemux(&self) -> TRACEMUX_R {
+        TRACEMUX_R::new(((self.bits >> 16) & 3) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:1 - Speed of Trace Port clock. Note that the TRACECLK pin will output this clock divided by two."]
+    #[inline(always)]
+    pub fn traceportspeed(&mut self) -> TRACEPORTSPEED_W<0> {
+        TRACEPORTSPEED_W::new(self)
+    }
+    #[doc = "Bits 16:17 - Pin multiplexing of trace signals."]
+    #[inline(always)]
+    pub fn tracemux(&mut self) -> TRACEMUX_W<16> {
+        TRACEMUX_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Clocking options for the Trace Port debug interface\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [traceconfig](index.html) module"]
+pub struct TRACECONFIG_SPEC;
+impl crate::RegisterSpec for TRACECONFIG_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [traceconfig::R](R) reader structure"]
+impl crate::Readable for TRACECONFIG_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [traceconfig::W](W) writer structure"]
+impl crate::Writable for TRACECONFIG_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets TRACECONFIG to value 0"]
+impl crate::Resettable for TRACECONFIG_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}