feat: add display UI with splash screen, dashboard, and RSSI sparkline

Implement full SSD1306 OLED display support:
- Splash screen on boot (1.5s) with project name, version, board
- Dashboard showing radio state, config, counters, RSSI/SNR
- RSSI history sparkline (64-sample ring buffer, 2px-wide bars)
- DisplayOn/DisplayOff host commands routed via dedicated channel
- Pure render functions against generic DrawTarget (no hardware coupling)
- Display on/off control bypasses radio task entirely

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>

vendor/nrf52833-pac/src/spim0/config.rs

@@ -0,0 +1,246 @@
+#[doc = "Register `CONFIG` reader"]
+pub struct R(crate::R<CONFIG_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<CONFIG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<CONFIG_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<CONFIG_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `CONFIG` writer"]
+pub struct W(crate::W<CONFIG_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<CONFIG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<CONFIG_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<CONFIG_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `ORDER` reader - Bit order"]
+pub type ORDER_R = crate::BitReader<ORDER_A>;
+#[doc = "Bit order\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ORDER_A {
+    #[doc = "0: Most significant bit shifted out first"]
+    MSB_FIRST = 0,
+    #[doc = "1: Least significant bit shifted out first"]
+    LSB_FIRST = 1,
+}
+impl From<ORDER_A> for bool {
+    #[inline(always)]
+    fn from(variant: ORDER_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl ORDER_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> ORDER_A {
+        match self.bits {
+            false => ORDER_A::MSB_FIRST,
+            true => ORDER_A::LSB_FIRST,
+        }
+    }
+    #[doc = "Checks if the value of the field is `MSB_FIRST`"]
+    #[inline(always)]
+    pub fn is_msb_first(&self) -> bool {
+        *self == ORDER_A::MSB_FIRST
+    }
+    #[doc = "Checks if the value of the field is `LSB_FIRST`"]
+    #[inline(always)]
+    pub fn is_lsb_first(&self) -> bool {
+        *self == ORDER_A::LSB_FIRST
+    }
+}
+#[doc = "Field `ORDER` writer - Bit order"]
+pub type ORDER_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONFIG_SPEC, ORDER_A, O>;
+impl<'a, const O: u8> ORDER_W<'a, O> {
+    #[doc = "Most significant bit shifted out first"]
+    #[inline(always)]
+    pub fn msb_first(self) -> &'a mut W {
+        self.variant(ORDER_A::MSB_FIRST)
+    }
+    #[doc = "Least significant bit shifted out first"]
+    #[inline(always)]
+    pub fn lsb_first(self) -> &'a mut W {
+        self.variant(ORDER_A::LSB_FIRST)
+    }
+}
+#[doc = "Field `CPHA` reader - Serial clock (SCK) phase"]
+pub type CPHA_R = crate::BitReader<CPHA_A>;
+#[doc = "Serial clock (SCK) phase\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CPHA_A {
+    #[doc = "0: Sample on leading edge of clock, shift serial data on trailing edge"]
+    LEADING = 0,
+    #[doc = "1: Sample on trailing edge of clock, shift serial data on leading edge"]
+    TRAILING = 1,
+}
+impl From<CPHA_A> for bool {
+    #[inline(always)]
+    fn from(variant: CPHA_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl CPHA_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> CPHA_A {
+        match self.bits {
+            false => CPHA_A::LEADING,
+            true => CPHA_A::TRAILING,
+        }
+    }
+    #[doc = "Checks if the value of the field is `LEADING`"]
+    #[inline(always)]
+    pub fn is_leading(&self) -> bool {
+        *self == CPHA_A::LEADING
+    }
+    #[doc = "Checks if the value of the field is `TRAILING`"]
+    #[inline(always)]
+    pub fn is_trailing(&self) -> bool {
+        *self == CPHA_A::TRAILING
+    }
+}
+#[doc = "Field `CPHA` writer - Serial clock (SCK) phase"]
+pub type CPHA_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONFIG_SPEC, CPHA_A, O>;
+impl<'a, const O: u8> CPHA_W<'a, O> {
+    #[doc = "Sample on leading edge of clock, shift serial data on trailing edge"]
+    #[inline(always)]
+    pub fn leading(self) -> &'a mut W {
+        self.variant(CPHA_A::LEADING)
+    }
+    #[doc = "Sample on trailing edge of clock, shift serial data on leading edge"]
+    #[inline(always)]
+    pub fn trailing(self) -> &'a mut W {
+        self.variant(CPHA_A::TRAILING)
+    }
+}
+#[doc = "Field `CPOL` reader - Serial clock (SCK) polarity"]
+pub type CPOL_R = crate::BitReader<CPOL_A>;
+#[doc = "Serial clock (SCK) polarity\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CPOL_A {
+    #[doc = "0: Active high"]
+    ACTIVE_HIGH = 0,
+    #[doc = "1: Active low"]
+    ACTIVE_LOW = 1,
+}
+impl From<CPOL_A> for bool {
+    #[inline(always)]
+    fn from(variant: CPOL_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl CPOL_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> CPOL_A {
+        match self.bits {
+            false => CPOL_A::ACTIVE_HIGH,
+            true => CPOL_A::ACTIVE_LOW,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ACTIVE_HIGH`"]
+    #[inline(always)]
+    pub fn is_active_high(&self) -> bool {
+        *self == CPOL_A::ACTIVE_HIGH
+    }
+    #[doc = "Checks if the value of the field is `ACTIVE_LOW`"]
+    #[inline(always)]
+    pub fn is_active_low(&self) -> bool {
+        *self == CPOL_A::ACTIVE_LOW
+    }
+}
+#[doc = "Field `CPOL` writer - Serial clock (SCK) polarity"]
+pub type CPOL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONFIG_SPEC, CPOL_A, O>;
+impl<'a, const O: u8> CPOL_W<'a, O> {
+    #[doc = "Active high"]
+    #[inline(always)]
+    pub fn active_high(self) -> &'a mut W {
+        self.variant(CPOL_A::ACTIVE_HIGH)
+    }
+    #[doc = "Active low"]
+    #[inline(always)]
+    pub fn active_low(self) -> &'a mut W {
+        self.variant(CPOL_A::ACTIVE_LOW)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Bit order"]
+    #[inline(always)]
+    pub fn order(&self) -> ORDER_R {
+        ORDER_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Serial clock (SCK) phase"]
+    #[inline(always)]
+    pub fn cpha(&self) -> CPHA_R {
+        CPHA_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Serial clock (SCK) polarity"]
+    #[inline(always)]
+    pub fn cpol(&self) -> CPOL_R {
+        CPOL_R::new(((self.bits >> 2) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Bit order"]
+    #[inline(always)]
+    pub fn order(&mut self) -> ORDER_W<0> {
+        ORDER_W::new(self)
+    }
+    #[doc = "Bit 1 - Serial clock (SCK) phase"]
+    #[inline(always)]
+    pub fn cpha(&mut self) -> CPHA_W<1> {
+        CPHA_W::new(self)
+    }
+    #[doc = "Bit 2 - Serial clock (SCK) polarity"]
+    #[inline(always)]
+    pub fn cpol(&mut self) -> CPOL_W<2> {
+        CPOL_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [config](index.html) module"]
+pub struct CONFIG_SPEC;
+impl crate::RegisterSpec for CONFIG_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [config::R](R) reader structure"]
+impl crate::Readable for CONFIG_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [config::W](W) writer structure"]
+impl crate::Writable for CONFIG_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets CONFIG to value 0"]
+impl crate::Resettable for CONFIG_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf52833-pac/src/spim0/csnpol.rs

@@ -0,0 +1,126 @@
+#[doc = "Register `CSNPOL` reader"]
+pub struct R(crate::R<CSNPOL_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<CSNPOL_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<CSNPOL_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<CSNPOL_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `CSNPOL` writer"]
+pub struct W(crate::W<CSNPOL_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<CSNPOL_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<CSNPOL_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<CSNPOL_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `CSNPOL` reader - Polarity of CSN output"]
+pub type CSNPOL_R = crate::BitReader<CSNPOL_A>;
+#[doc = "Polarity of CSN output\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CSNPOL_A {
+    #[doc = "0: Active low (idle state high)"]
+    LOW = 0,
+    #[doc = "1: Active high (idle state low)"]
+    HIGH = 1,
+}
+impl From<CSNPOL_A> for bool {
+    #[inline(always)]
+    fn from(variant: CSNPOL_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl CSNPOL_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> CSNPOL_A {
+        match self.bits {
+            false => CSNPOL_A::LOW,
+            true => CSNPOL_A::HIGH,
+        }
+    }
+    #[doc = "Checks if the value of the field is `LOW`"]
+    #[inline(always)]
+    pub fn is_low(&self) -> bool {
+        *self == CSNPOL_A::LOW
+    }
+    #[doc = "Checks if the value of the field is `HIGH`"]
+    #[inline(always)]
+    pub fn is_high(&self) -> bool {
+        *self == CSNPOL_A::HIGH
+    }
+}
+#[doc = "Field `CSNPOL` writer - Polarity of CSN output"]
+pub type CSNPOL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CSNPOL_SPEC, CSNPOL_A, O>;
+impl<'a, const O: u8> CSNPOL_W<'a, O> {
+    #[doc = "Active low (idle state high)"]
+    #[inline(always)]
+    pub fn low(self) -> &'a mut W {
+        self.variant(CSNPOL_A::LOW)
+    }
+    #[doc = "Active high (idle state low)"]
+    #[inline(always)]
+    pub fn high(self) -> &'a mut W {
+        self.variant(CSNPOL_A::HIGH)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Polarity of CSN output"]
+    #[inline(always)]
+    pub fn csnpol(&self) -> CSNPOL_R {
+        CSNPOL_R::new((self.bits & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Polarity of CSN output"]
+    #[inline(always)]
+    pub fn csnpol(&mut self) -> CSNPOL_W<0> {
+        CSNPOL_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Polarity of CSN output\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [csnpol](index.html) module"]
+pub struct CSNPOL_SPEC;
+impl crate::RegisterSpec for CSNPOL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [csnpol::R](R) reader structure"]
+impl crate::Readable for CSNPOL_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [csnpol::W](W) writer structure"]
+impl crate::Writable for CSNPOL_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets CSNPOL to value 0"]
+impl crate::Resettable for CSNPOL_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf52833-pac/src/spim0/dcxcnt.rs

@@ -0,0 +1,80 @@
+#[doc = "Register `DCXCNT` reader"]
+pub struct R(crate::R<DCXCNT_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<DCXCNT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<DCXCNT_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<DCXCNT_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `DCXCNT` writer"]
+pub struct W(crate::W<DCXCNT_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<DCXCNT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<DCXCNT_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<DCXCNT_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `DCXCNT` reader - This register specifies the number of command bytes preceding the data bytes. The PSEL.DCX line will be low during transmission of command bytes and high during transmission of data bytes. Value 0xF indicates that all bytes are command bytes."]
+pub type DCXCNT_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `DCXCNT` writer - This register specifies the number of command bytes preceding the data bytes. The PSEL.DCX line will be low during transmission of command bytes and high during transmission of data bytes. Value 0xF indicates that all bytes are command bytes."]
+pub type DCXCNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DCXCNT_SPEC, u8, u8, 4, O>;
+impl R {
+    #[doc = "Bits 0:3 - This register specifies the number of command bytes preceding the data bytes. The PSEL.DCX line will be low during transmission of command bytes and high during transmission of data bytes. Value 0xF indicates that all bytes are command bytes."]
+    #[inline(always)]
+    pub fn dcxcnt(&self) -> DCXCNT_R {
+        DCXCNT_R::new((self.bits & 0x0f) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:3 - This register specifies the number of command bytes preceding the data bytes. The PSEL.DCX line will be low during transmission of command bytes and high during transmission of data bytes. Value 0xF indicates that all bytes are command bytes."]
+    #[inline(always)]
+    pub fn dcxcnt(&mut self) -> DCXCNT_W<0> {
+        DCXCNT_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "DCX configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dcxcnt](index.html) module"]
+pub struct DCXCNT_SPEC;
+impl crate::RegisterSpec for DCXCNT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [dcxcnt::R](R) reader structure"]
+impl crate::Readable for DCXCNT_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [dcxcnt::W](W) writer structure"]
+impl crate::Writable for DCXCNT_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets DCXCNT to value 0"]
+impl crate::Resettable for DCXCNT_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf52833-pac/src/spim0/enable.rs

@@ -0,0 +1,128 @@
+#[doc = "Register `ENABLE` reader"]
+pub struct R(crate::R<ENABLE_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<ENABLE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<ENABLE_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<ENABLE_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `ENABLE` writer"]
+pub struct W(crate::W<ENABLE_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<ENABLE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<ENABLE_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<ENABLE_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `ENABLE` reader - Enable or disable SPIM"]
+pub type ENABLE_R = crate::FieldReader<u8, ENABLE_A>;
+#[doc = "Enable or disable SPIM\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum ENABLE_A {
+    #[doc = "0: Disable SPIM"]
+    DISABLED = 0,
+    #[doc = "7: Enable SPIM"]
+    ENABLED = 7,
+}
+impl From<ENABLE_A> for u8 {
+    #[inline(always)]
+    fn from(variant: ENABLE_A) -> Self {
+        variant as _
+    }
+}
+impl ENABLE_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<ENABLE_A> {
+        match self.bits {
+            0 => Some(ENABLE_A::DISABLED),
+            7 => Some(ENABLE_A::ENABLED),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == ENABLE_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == ENABLE_A::ENABLED
+    }
+}
+#[doc = "Field `ENABLE` writer - Enable or disable SPIM"]
+pub type ENABLE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ENABLE_SPEC, u8, ENABLE_A, 4, O>;
+impl<'a, const O: u8> ENABLE_W<'a, O> {
+    #[doc = "Disable SPIM"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(ENABLE_A::DISABLED)
+    }
+    #[doc = "Enable SPIM"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(ENABLE_A::ENABLED)
+    }
+}
+impl R {
+    #[doc = "Bits 0:3 - Enable or disable SPIM"]
+    #[inline(always)]
+    pub fn enable(&self) -> ENABLE_R {
+        ENABLE_R::new((self.bits & 0x0f) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:3 - Enable or disable SPIM"]
+    #[inline(always)]
+    pub fn enable(&mut self) -> ENABLE_W<0> {
+        ENABLE_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Enable SPIM\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [enable](index.html) module"]
+pub struct ENABLE_SPEC;
+impl crate::RegisterSpec for ENABLE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [enable::R](R) reader structure"]
+impl crate::Readable for ENABLE_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [enable::W](W) writer structure"]
+impl crate::Writable for ENABLE_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets ENABLE to value 0"]
+impl crate::Resettable for ENABLE_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf52833-pac/src/spim0/events_end.rs

@@ -0,0 +1,127 @@
+#[doc = "Register `EVENTS_END` reader"]
+pub struct R(crate::R<EVENTS_END_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<EVENTS_END_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<EVENTS_END_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<EVENTS_END_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `EVENTS_END` writer"]
+pub struct W(crate::W<EVENTS_END_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<EVENTS_END_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<EVENTS_END_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<EVENTS_END_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `EVENTS_END` reader - End of RXD buffer and TXD buffer reached"]
+pub type EVENTS_END_R = crate::BitReader<EVENTS_END_A>;
+#[doc = "End of RXD buffer and TXD buffer reached\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum EVENTS_END_A {
+    #[doc = "0: Event not generated"]
+    NOT_GENERATED = 0,
+    #[doc = "1: Event generated"]
+    GENERATED = 1,
+}
+impl From<EVENTS_END_A> for bool {
+    #[inline(always)]
+    fn from(variant: EVENTS_END_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl EVENTS_END_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> EVENTS_END_A {
+        match self.bits {
+            false => EVENTS_END_A::NOT_GENERATED,
+            true => EVENTS_END_A::GENERATED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `NOT_GENERATED`"]
+    #[inline(always)]
+    pub fn is_not_generated(&self) -> bool {
+        *self == EVENTS_END_A::NOT_GENERATED
+    }
+    #[doc = "Checks if the value of the field is `GENERATED`"]
+    #[inline(always)]
+    pub fn is_generated(&self) -> bool {
+        *self == EVENTS_END_A::GENERATED
+    }
+}
+#[doc = "Field `EVENTS_END` writer - End of RXD buffer and TXD buffer reached"]
+pub type EVENTS_END_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, EVENTS_END_SPEC, EVENTS_END_A, O>;
+impl<'a, const O: u8> EVENTS_END_W<'a, O> {
+    #[doc = "Event not generated"]
+    #[inline(always)]
+    pub fn not_generated(self) -> &'a mut W {
+        self.variant(EVENTS_END_A::NOT_GENERATED)
+    }
+    #[doc = "Event generated"]
+    #[inline(always)]
+    pub fn generated(self) -> &'a mut W {
+        self.variant(EVENTS_END_A::GENERATED)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - End of RXD buffer and TXD buffer reached"]
+    #[inline(always)]
+    pub fn events_end(&self) -> EVENTS_END_R {
+        EVENTS_END_R::new((self.bits & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - End of RXD buffer and TXD buffer reached"]
+    #[inline(always)]
+    pub fn events_end(&mut self) -> EVENTS_END_W<0> {
+        EVENTS_END_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "End of RXD buffer and TXD buffer reached\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_end](index.html) module"]
+pub struct EVENTS_END_SPEC;
+impl crate::RegisterSpec for EVENTS_END_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [events_end::R](R) reader structure"]
+impl crate::Readable for EVENTS_END_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [events_end::W](W) writer structure"]
+impl crate::Writable for EVENTS_END_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets EVENTS_END to value 0"]
+impl crate::Resettable for EVENTS_END_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf52833-pac/src/spim0/events_endrx.rs

@@ -0,0 +1,127 @@
+#[doc = "Register `EVENTS_ENDRX` reader"]
+pub struct R(crate::R<EVENTS_ENDRX_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<EVENTS_ENDRX_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<EVENTS_ENDRX_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<EVENTS_ENDRX_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `EVENTS_ENDRX` writer"]
+pub struct W(crate::W<EVENTS_ENDRX_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<EVENTS_ENDRX_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<EVENTS_ENDRX_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<EVENTS_ENDRX_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `EVENTS_ENDRX` reader - End of RXD buffer reached"]
+pub type EVENTS_ENDRX_R = crate::BitReader<EVENTS_ENDRX_A>;
+#[doc = "End of RXD buffer reached\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum EVENTS_ENDRX_A {
+    #[doc = "0: Event not generated"]
+    NOT_GENERATED = 0,
+    #[doc = "1: Event generated"]
+    GENERATED = 1,
+}
+impl From<EVENTS_ENDRX_A> for bool {
+    #[inline(always)]
+    fn from(variant: EVENTS_ENDRX_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl EVENTS_ENDRX_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> EVENTS_ENDRX_A {
+        match self.bits {
+            false => EVENTS_ENDRX_A::NOT_GENERATED,
+            true => EVENTS_ENDRX_A::GENERATED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `NOT_GENERATED`"]
+    #[inline(always)]
+    pub fn is_not_generated(&self) -> bool {
+        *self == EVENTS_ENDRX_A::NOT_GENERATED
+    }
+    #[doc = "Checks if the value of the field is `GENERATED`"]
+    #[inline(always)]
+    pub fn is_generated(&self) -> bool {
+        *self == EVENTS_ENDRX_A::GENERATED
+    }
+}
+#[doc = "Field `EVENTS_ENDRX` writer - End of RXD buffer reached"]
+pub type EVENTS_ENDRX_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, EVENTS_ENDRX_SPEC, EVENTS_ENDRX_A, O>;
+impl<'a, const O: u8> EVENTS_ENDRX_W<'a, O> {
+    #[doc = "Event not generated"]
+    #[inline(always)]
+    pub fn not_generated(self) -> &'a mut W {
+        self.variant(EVENTS_ENDRX_A::NOT_GENERATED)
+    }
+    #[doc = "Event generated"]
+    #[inline(always)]
+    pub fn generated(self) -> &'a mut W {
+        self.variant(EVENTS_ENDRX_A::GENERATED)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - End of RXD buffer reached"]
+    #[inline(always)]
+    pub fn events_endrx(&self) -> EVENTS_ENDRX_R {
+        EVENTS_ENDRX_R::new((self.bits & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - End of RXD buffer reached"]
+    #[inline(always)]
+    pub fn events_endrx(&mut self) -> EVENTS_ENDRX_W<0> {
+        EVENTS_ENDRX_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "End of RXD buffer reached\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_endrx](index.html) module"]
+pub struct EVENTS_ENDRX_SPEC;
+impl crate::RegisterSpec for EVENTS_ENDRX_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [events_endrx::R](R) reader structure"]
+impl crate::Readable for EVENTS_ENDRX_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [events_endrx::W](W) writer structure"]
+impl crate::Writable for EVENTS_ENDRX_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets EVENTS_ENDRX to value 0"]
+impl crate::Resettable for EVENTS_ENDRX_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf52833-pac/src/spim0/events_endtx.rs

@@ -0,0 +1,127 @@
+#[doc = "Register `EVENTS_ENDTX` reader"]
+pub struct R(crate::R<EVENTS_ENDTX_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<EVENTS_ENDTX_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<EVENTS_ENDTX_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<EVENTS_ENDTX_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `EVENTS_ENDTX` writer"]
+pub struct W(crate::W<EVENTS_ENDTX_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<EVENTS_ENDTX_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<EVENTS_ENDTX_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<EVENTS_ENDTX_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `EVENTS_ENDTX` reader - End of TXD buffer reached"]
+pub type EVENTS_ENDTX_R = crate::BitReader<EVENTS_ENDTX_A>;
+#[doc = "End of TXD buffer reached\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum EVENTS_ENDTX_A {
+    #[doc = "0: Event not generated"]
+    NOT_GENERATED = 0,
+    #[doc = "1: Event generated"]
+    GENERATED = 1,
+}
+impl From<EVENTS_ENDTX_A> for bool {
+    #[inline(always)]
+    fn from(variant: EVENTS_ENDTX_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl EVENTS_ENDTX_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> EVENTS_ENDTX_A {
+        match self.bits {
+            false => EVENTS_ENDTX_A::NOT_GENERATED,
+            true => EVENTS_ENDTX_A::GENERATED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `NOT_GENERATED`"]
+    #[inline(always)]
+    pub fn is_not_generated(&self) -> bool {
+        *self == EVENTS_ENDTX_A::NOT_GENERATED
+    }
+    #[doc = "Checks if the value of the field is `GENERATED`"]
+    #[inline(always)]
+    pub fn is_generated(&self) -> bool {
+        *self == EVENTS_ENDTX_A::GENERATED
+    }
+}
+#[doc = "Field `EVENTS_ENDTX` writer - End of TXD buffer reached"]
+pub type EVENTS_ENDTX_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, EVENTS_ENDTX_SPEC, EVENTS_ENDTX_A, O>;
+impl<'a, const O: u8> EVENTS_ENDTX_W<'a, O> {
+    #[doc = "Event not generated"]
+    #[inline(always)]
+    pub fn not_generated(self) -> &'a mut W {
+        self.variant(EVENTS_ENDTX_A::NOT_GENERATED)
+    }
+    #[doc = "Event generated"]
+    #[inline(always)]
+    pub fn generated(self) -> &'a mut W {
+        self.variant(EVENTS_ENDTX_A::GENERATED)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - End of TXD buffer reached"]
+    #[inline(always)]
+    pub fn events_endtx(&self) -> EVENTS_ENDTX_R {
+        EVENTS_ENDTX_R::new((self.bits & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - End of TXD buffer reached"]
+    #[inline(always)]
+    pub fn events_endtx(&mut self) -> EVENTS_ENDTX_W<0> {
+        EVENTS_ENDTX_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "End of TXD buffer reached\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_endtx](index.html) module"]
+pub struct EVENTS_ENDTX_SPEC;
+impl crate::RegisterSpec for EVENTS_ENDTX_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [events_endtx::R](R) reader structure"]
+impl crate::Readable for EVENTS_ENDTX_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [events_endtx::W](W) writer structure"]
+impl crate::Writable for EVENTS_ENDTX_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets EVENTS_ENDTX to value 0"]
+impl crate::Resettable for EVENTS_ENDTX_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf52833-pac/src/spim0/events_started.rs

@@ -0,0 +1,127 @@
+#[doc = "Register `EVENTS_STARTED` reader"]
+pub struct R(crate::R<EVENTS_STARTED_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<EVENTS_STARTED_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<EVENTS_STARTED_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<EVENTS_STARTED_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `EVENTS_STARTED` writer"]
+pub struct W(crate::W<EVENTS_STARTED_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<EVENTS_STARTED_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<EVENTS_STARTED_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<EVENTS_STARTED_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `EVENTS_STARTED` reader - Transaction started"]
+pub type EVENTS_STARTED_R = crate::BitReader<EVENTS_STARTED_A>;
+#[doc = "Transaction started\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum EVENTS_STARTED_A {
+    #[doc = "0: Event not generated"]
+    NOT_GENERATED = 0,
+    #[doc = "1: Event generated"]
+    GENERATED = 1,
+}
+impl From<EVENTS_STARTED_A> for bool {
+    #[inline(always)]
+    fn from(variant: EVENTS_STARTED_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl EVENTS_STARTED_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> EVENTS_STARTED_A {
+        match self.bits {
+            false => EVENTS_STARTED_A::NOT_GENERATED,
+            true => EVENTS_STARTED_A::GENERATED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `NOT_GENERATED`"]
+    #[inline(always)]
+    pub fn is_not_generated(&self) -> bool {
+        *self == EVENTS_STARTED_A::NOT_GENERATED
+    }
+    #[doc = "Checks if the value of the field is `GENERATED`"]
+    #[inline(always)]
+    pub fn is_generated(&self) -> bool {
+        *self == EVENTS_STARTED_A::GENERATED
+    }
+}
+#[doc = "Field `EVENTS_STARTED` writer - Transaction started"]
+pub type EVENTS_STARTED_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, EVENTS_STARTED_SPEC, EVENTS_STARTED_A, O>;
+impl<'a, const O: u8> EVENTS_STARTED_W<'a, O> {
+    #[doc = "Event not generated"]
+    #[inline(always)]
+    pub fn not_generated(self) -> &'a mut W {
+        self.variant(EVENTS_STARTED_A::NOT_GENERATED)
+    }
+    #[doc = "Event generated"]
+    #[inline(always)]
+    pub fn generated(self) -> &'a mut W {
+        self.variant(EVENTS_STARTED_A::GENERATED)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Transaction started"]
+    #[inline(always)]
+    pub fn events_started(&self) -> EVENTS_STARTED_R {
+        EVENTS_STARTED_R::new((self.bits & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Transaction started"]
+    #[inline(always)]
+    pub fn events_started(&mut self) -> EVENTS_STARTED_W<0> {
+        EVENTS_STARTED_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Transaction started\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_started](index.html) module"]
+pub struct EVENTS_STARTED_SPEC;
+impl crate::RegisterSpec for EVENTS_STARTED_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [events_started::R](R) reader structure"]
+impl crate::Readable for EVENTS_STARTED_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [events_started::W](W) writer structure"]
+impl crate::Writable for EVENTS_STARTED_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets EVENTS_STARTED to value 0"]
+impl crate::Resettable for EVENTS_STARTED_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf52833-pac/src/spim0/events_stopped.rs

@@ -0,0 +1,127 @@
+#[doc = "Register `EVENTS_STOPPED` reader"]
+pub struct R(crate::R<EVENTS_STOPPED_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<EVENTS_STOPPED_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<EVENTS_STOPPED_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<EVENTS_STOPPED_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `EVENTS_STOPPED` writer"]
+pub struct W(crate::W<EVENTS_STOPPED_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<EVENTS_STOPPED_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<EVENTS_STOPPED_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<EVENTS_STOPPED_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `EVENTS_STOPPED` reader - SPI transaction has stopped"]
+pub type EVENTS_STOPPED_R = crate::BitReader<EVENTS_STOPPED_A>;
+#[doc = "SPI transaction has stopped\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum EVENTS_STOPPED_A {
+    #[doc = "0: Event not generated"]
+    NOT_GENERATED = 0,
+    #[doc = "1: Event generated"]
+    GENERATED = 1,
+}
+impl From<EVENTS_STOPPED_A> for bool {
+    #[inline(always)]
+    fn from(variant: EVENTS_STOPPED_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl EVENTS_STOPPED_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> EVENTS_STOPPED_A {
+        match self.bits {
+            false => EVENTS_STOPPED_A::NOT_GENERATED,
+            true => EVENTS_STOPPED_A::GENERATED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `NOT_GENERATED`"]
+    #[inline(always)]
+    pub fn is_not_generated(&self) -> bool {
+        *self == EVENTS_STOPPED_A::NOT_GENERATED
+    }
+    #[doc = "Checks if the value of the field is `GENERATED`"]
+    #[inline(always)]
+    pub fn is_generated(&self) -> bool {
+        *self == EVENTS_STOPPED_A::GENERATED
+    }
+}
+#[doc = "Field `EVENTS_STOPPED` writer - SPI transaction has stopped"]
+pub type EVENTS_STOPPED_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, EVENTS_STOPPED_SPEC, EVENTS_STOPPED_A, O>;
+impl<'a, const O: u8> EVENTS_STOPPED_W<'a, O> {
+    #[doc = "Event not generated"]
+    #[inline(always)]
+    pub fn not_generated(self) -> &'a mut W {
+        self.variant(EVENTS_STOPPED_A::NOT_GENERATED)
+    }
+    #[doc = "Event generated"]
+    #[inline(always)]
+    pub fn generated(self) -> &'a mut W {
+        self.variant(EVENTS_STOPPED_A::GENERATED)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - SPI transaction has stopped"]
+    #[inline(always)]
+    pub fn events_stopped(&self) -> EVENTS_STOPPED_R {
+        EVENTS_STOPPED_R::new((self.bits & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - SPI transaction has stopped"]
+    #[inline(always)]
+    pub fn events_stopped(&mut self) -> EVENTS_STOPPED_W<0> {
+        EVENTS_STOPPED_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "SPI transaction has stopped\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_stopped](index.html) module"]
+pub struct EVENTS_STOPPED_SPEC;
+impl crate::RegisterSpec for EVENTS_STOPPED_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [events_stopped::R](R) reader structure"]
+impl crate::Readable for EVENTS_STOPPED_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [events_stopped::W](W) writer structure"]
+impl crate::Writable for EVENTS_STOPPED_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets EVENTS_STOPPED to value 0"]
+impl crate::Resettable for EVENTS_STOPPED_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf52833-pac/src/spim0/frequency.rs

@@ -0,0 +1,220 @@
+#[doc = "Register `FREQUENCY` reader"]
+pub struct R(crate::R<FREQUENCY_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<FREQUENCY_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<FREQUENCY_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<FREQUENCY_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `FREQUENCY` writer"]
+pub struct W(crate::W<FREQUENCY_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<FREQUENCY_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<FREQUENCY_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<FREQUENCY_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `FREQUENCY` reader - SPI master data rate"]
+pub type FREQUENCY_R = crate::FieldReader<u32, FREQUENCY_A>;
+#[doc = "SPI master data rate\n\nValue on reset: 67108864"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u32)]
+pub enum FREQUENCY_A {
+    #[doc = "33554432: 125 kbps"]
+    K125 = 33554432,
+    #[doc = "67108864: 250 kbps"]
+    K250 = 67108864,
+    #[doc = "134217728: 500 kbps"]
+    K500 = 134217728,
+    #[doc = "268435456: 1 Mbps"]
+    M1 = 268435456,
+    #[doc = "536870912: 2 Mbps"]
+    M2 = 536870912,
+    #[doc = "1073741824: 4 Mbps"]
+    M4 = 1073741824,
+    #[doc = "2147483648: 8 Mbps"]
+    M8 = 2147483648,
+    #[doc = "167772160: 16 Mbps"]
+    M16 = 167772160,
+    #[doc = "335544320: 32 Mbps"]
+    M32 = 335544320,
+}
+impl From<FREQUENCY_A> for u32 {
+    #[inline(always)]
+    fn from(variant: FREQUENCY_A) -> Self {
+        variant as _
+    }
+}
+impl FREQUENCY_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<FREQUENCY_A> {
+        match self.bits {
+            33554432 => Some(FREQUENCY_A::K125),
+            67108864 => Some(FREQUENCY_A::K250),
+            134217728 => Some(FREQUENCY_A::K500),
+            268435456 => Some(FREQUENCY_A::M1),
+            536870912 => Some(FREQUENCY_A::M2),
+            1073741824 => Some(FREQUENCY_A::M4),
+            2147483648 => Some(FREQUENCY_A::M8),
+            167772160 => Some(FREQUENCY_A::M16),
+            335544320 => Some(FREQUENCY_A::M32),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `K125`"]
+    #[inline(always)]
+    pub fn is_k125(&self) -> bool {
+        *self == FREQUENCY_A::K125
+    }
+    #[doc = "Checks if the value of the field is `K250`"]
+    #[inline(always)]
+    pub fn is_k250(&self) -> bool {
+        *self == FREQUENCY_A::K250
+    }
+    #[doc = "Checks if the value of the field is `K500`"]
+    #[inline(always)]
+    pub fn is_k500(&self) -> bool {
+        *self == FREQUENCY_A::K500
+    }
+    #[doc = "Checks if the value of the field is `M1`"]
+    #[inline(always)]
+    pub fn is_m1(&self) -> bool {
+        *self == FREQUENCY_A::M1
+    }
+    #[doc = "Checks if the value of the field is `M2`"]
+    #[inline(always)]
+    pub fn is_m2(&self) -> bool {
+        *self == FREQUENCY_A::M2
+    }
+    #[doc = "Checks if the value of the field is `M4`"]
+    #[inline(always)]
+    pub fn is_m4(&self) -> bool {
+        *self == FREQUENCY_A::M4
+    }
+    #[doc = "Checks if the value of the field is `M8`"]
+    #[inline(always)]
+    pub fn is_m8(&self) -> bool {
+        *self == FREQUENCY_A::M8
+    }
+    #[doc = "Checks if the value of the field is `M16`"]
+    #[inline(always)]
+    pub fn is_m16(&self) -> bool {
+        *self == FREQUENCY_A::M16
+    }
+    #[doc = "Checks if the value of the field is `M32`"]
+    #[inline(always)]
+    pub fn is_m32(&self) -> bool {
+        *self == FREQUENCY_A::M32
+    }
+}
+#[doc = "Field `FREQUENCY` writer - SPI master data rate"]
+pub type FREQUENCY_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u32, FREQUENCY_SPEC, u32, FREQUENCY_A, 32, O>;
+impl<'a, const O: u8> FREQUENCY_W<'a, O> {
+    #[doc = "125 kbps"]
+    #[inline(always)]
+    pub fn k125(self) -> &'a mut W {
+        self.variant(FREQUENCY_A::K125)
+    }
+    #[doc = "250 kbps"]
+    #[inline(always)]
+    pub fn k250(self) -> &'a mut W {
+        self.variant(FREQUENCY_A::K250)
+    }
+    #[doc = "500 kbps"]
+    #[inline(always)]
+    pub fn k500(self) -> &'a mut W {
+        self.variant(FREQUENCY_A::K500)
+    }
+    #[doc = "1 Mbps"]
+    #[inline(always)]
+    pub fn m1(self) -> &'a mut W {
+        self.variant(FREQUENCY_A::M1)
+    }
+    #[doc = "2 Mbps"]
+    #[inline(always)]
+    pub fn m2(self) -> &'a mut W {
+        self.variant(FREQUENCY_A::M2)
+    }
+    #[doc = "4 Mbps"]
+    #[inline(always)]
+    pub fn m4(self) -> &'a mut W {
+        self.variant(FREQUENCY_A::M4)
+    }
+    #[doc = "8 Mbps"]
+    #[inline(always)]
+    pub fn m8(self) -> &'a mut W {
+        self.variant(FREQUENCY_A::M8)
+    }
+    #[doc = "16 Mbps"]
+    #[inline(always)]
+    pub fn m16(self) -> &'a mut W {
+        self.variant(FREQUENCY_A::M16)
+    }
+    #[doc = "32 Mbps"]
+    #[inline(always)]
+    pub fn m32(self) -> &'a mut W {
+        self.variant(FREQUENCY_A::M32)
+    }
+}
+impl R {
+    #[doc = "Bits 0:31 - SPI master data rate"]
+    #[inline(always)]
+    pub fn frequency(&self) -> FREQUENCY_R {
+        FREQUENCY_R::new(self.bits)
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - SPI master data rate"]
+    #[inline(always)]
+    pub fn frequency(&mut self) -> FREQUENCY_W<0> {
+        FREQUENCY_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "SPI frequency. Accuracy depends on the HFCLK source selected.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [frequency](index.html) module"]
+pub struct FREQUENCY_SPEC;
+impl crate::RegisterSpec for FREQUENCY_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [frequency::R](R) reader structure"]
+impl crate::Readable for FREQUENCY_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [frequency::W](W) writer structure"]
+impl crate::Writable for FREQUENCY_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets FREQUENCY to value 0x0400_0000"]
+impl crate::Resettable for FREQUENCY_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0x0400_0000
+    }
+}

vendor/nrf52833-pac/src/spim0/iftiming.rs

@@ -0,0 +1,16 @@
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct IFTIMING {
+    #[doc = "0x00 - Sample delay for input serial data on MISO"]
+    pub rxdelay: RXDELAY,
+    #[doc = "0x04 - Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions"]
+    pub csndur: CSNDUR,
+}
+#[doc = "RXDELAY (rw) register accessor: an alias for `Reg<RXDELAY_SPEC>`"]
+pub type RXDELAY = crate::Reg<rxdelay::RXDELAY_SPEC>;
+#[doc = "Sample delay for input serial data on MISO"]
+pub mod rxdelay;
+#[doc = "CSNDUR (rw) register accessor: an alias for `Reg<CSNDUR_SPEC>`"]
+pub type CSNDUR = crate::Reg<csndur::CSNDUR_SPEC>;
+#[doc = "Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions"]
+pub mod csndur;

vendor/nrf52833-pac/src/spim0/iftiming/csndur.rs

@@ -0,0 +1,80 @@
+#[doc = "Register `CSNDUR` reader"]
+pub struct R(crate::R<CSNDUR_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<CSNDUR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<CSNDUR_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<CSNDUR_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `CSNDUR` writer"]
+pub struct W(crate::W<CSNDUR_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<CSNDUR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<CSNDUR_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<CSNDUR_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `CSNDUR` reader - Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns)."]
+pub type CSNDUR_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `CSNDUR` writer - Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns)."]
+pub type CSNDUR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CSNDUR_SPEC, u8, u8, 8, O>;
+impl R {
+    #[doc = "Bits 0:7 - Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns)."]
+    #[inline(always)]
+    pub fn csndur(&self) -> CSNDUR_R {
+        CSNDUR_R::new((self.bits & 0xff) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns)."]
+    #[inline(always)]
+    pub fn csndur(&mut self) -> CSNDUR_W<0> {
+        CSNDUR_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [csndur](index.html) module"]
+pub struct CSNDUR_SPEC;
+impl crate::RegisterSpec for CSNDUR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [csndur::R](R) reader structure"]
+impl crate::Readable for CSNDUR_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [csndur::W](W) writer structure"]
+impl crate::Writable for CSNDUR_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets CSNDUR to value 0x02"]
+impl crate::Resettable for CSNDUR_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0x02
+    }
+}

vendor/nrf52833-pac/src/spim0/iftiming/rxdelay.rs

@@ -0,0 +1,80 @@
+#[doc = "Register `RXDELAY` reader"]
+pub struct R(crate::R<RXDELAY_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<RXDELAY_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<RXDELAY_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<RXDELAY_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `RXDELAY` writer"]
+pub struct W(crate::W<RXDELAY_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<RXDELAY_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<RXDELAY_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<RXDELAY_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `RXDELAY` reader - Sample delay for input serial data on MISO. The value specifies the number of 64 MHz clock cycles (15.625 ns) delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA = 0, the input serial data is sampled on the rising edge of SCK."]
+pub type RXDELAY_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `RXDELAY` writer - Sample delay for input serial data on MISO. The value specifies the number of 64 MHz clock cycles (15.625 ns) delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA = 0, the input serial data is sampled on the rising edge of SCK."]
+pub type RXDELAY_W<'a, const O: u8> = crate::FieldWriter<'a, u32, RXDELAY_SPEC, u8, u8, 3, O>;
+impl R {
+    #[doc = "Bits 0:2 - Sample delay for input serial data on MISO. The value specifies the number of 64 MHz clock cycles (15.625 ns) delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA = 0, the input serial data is sampled on the rising edge of SCK."]
+    #[inline(always)]
+    pub fn rxdelay(&self) -> RXDELAY_R {
+        RXDELAY_R::new((self.bits & 7) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:2 - Sample delay for input serial data on MISO. The value specifies the number of 64 MHz clock cycles (15.625 ns) delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA = 0, the input serial data is sampled on the rising edge of SCK."]
+    #[inline(always)]
+    pub fn rxdelay(&mut self) -> RXDELAY_W<0> {
+        RXDELAY_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Sample delay for input serial data on MISO\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxdelay](index.html) module"]
+pub struct RXDELAY_SPEC;
+impl crate::RegisterSpec for RXDELAY_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [rxdelay::R](R) reader structure"]
+impl crate::Readable for RXDELAY_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [rxdelay::W](W) writer structure"]
+impl crate::Writable for RXDELAY_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets RXDELAY to value 0x02"]
+impl crate::Resettable for RXDELAY_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0x02
+    }
+}

vendor/nrf52833-pac/src/spim0/intenclr.rs

@@ -0,0 +1,401 @@
+#[doc = "Register `INTENCLR` reader"]
+pub struct R(crate::R<INTENCLR_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<INTENCLR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<INTENCLR_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<INTENCLR_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `INTENCLR` writer"]
+pub struct W(crate::W<INTENCLR_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<INTENCLR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<INTENCLR_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<INTENCLR_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `STOPPED` reader - Write '1' to disable interrupt for event STOPPED"]
+pub type STOPPED_R = crate::BitReader<STOPPED_A>;
+#[doc = "Write '1' to disable interrupt for event STOPPED\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum STOPPED_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<STOPPED_A> for bool {
+    #[inline(always)]
+    fn from(variant: STOPPED_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl STOPPED_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> STOPPED_A {
+        match self.bits {
+            false => STOPPED_A::DISABLED,
+            true => STOPPED_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == STOPPED_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == STOPPED_A::ENABLED
+    }
+}
+#[doc = "Write '1' to disable interrupt for event STOPPED\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum STOPPED_AW {
+    #[doc = "1: Disable"]
+    CLEAR = 1,
+}
+impl From<STOPPED_AW> for bool {
+    #[inline(always)]
+    fn from(variant: STOPPED_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `STOPPED` writer - Write '1' to disable interrupt for event STOPPED"]
+pub type STOPPED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, STOPPED_AW, O>;
+impl<'a, const O: u8> STOPPED_W<'a, O> {
+    #[doc = "Disable"]
+    #[inline(always)]
+    pub fn clear(self) -> &'a mut W {
+        self.variant(STOPPED_AW::CLEAR)
+    }
+}
+#[doc = "Field `ENDRX` reader - Write '1' to disable interrupt for event ENDRX"]
+pub type ENDRX_R = crate::BitReader<ENDRX_A>;
+#[doc = "Write '1' to disable interrupt for event ENDRX\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ENDRX_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<ENDRX_A> for bool {
+    #[inline(always)]
+    fn from(variant: ENDRX_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl ENDRX_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> ENDRX_A {
+        match self.bits {
+            false => ENDRX_A::DISABLED,
+            true => ENDRX_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == ENDRX_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == ENDRX_A::ENABLED
+    }
+}
+#[doc = "Write '1' to disable interrupt for event ENDRX\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ENDRX_AW {
+    #[doc = "1: Disable"]
+    CLEAR = 1,
+}
+impl From<ENDRX_AW> for bool {
+    #[inline(always)]
+    fn from(variant: ENDRX_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `ENDRX` writer - Write '1' to disable interrupt for event ENDRX"]
+pub type ENDRX_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, ENDRX_AW, O>;
+impl<'a, const O: u8> ENDRX_W<'a, O> {
+    #[doc = "Disable"]
+    #[inline(always)]
+    pub fn clear(self) -> &'a mut W {
+        self.variant(ENDRX_AW::CLEAR)
+    }
+}
+#[doc = "Field `END` reader - Write '1' to disable interrupt for event END"]
+pub type END_R = crate::BitReader<END_A>;
+#[doc = "Write '1' to disable interrupt for event END\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum END_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<END_A> for bool {
+    #[inline(always)]
+    fn from(variant: END_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl END_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> END_A {
+        match self.bits {
+            false => END_A::DISABLED,
+            true => END_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == END_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == END_A::ENABLED
+    }
+}
+#[doc = "Write '1' to disable interrupt for event END\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum END_AW {
+    #[doc = "1: Disable"]
+    CLEAR = 1,
+}
+impl From<END_AW> for bool {
+    #[inline(always)]
+    fn from(variant: END_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `END` writer - Write '1' to disable interrupt for event END"]
+pub type END_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, END_AW, O>;
+impl<'a, const O: u8> END_W<'a, O> {
+    #[doc = "Disable"]
+    #[inline(always)]
+    pub fn clear(self) -> &'a mut W {
+        self.variant(END_AW::CLEAR)
+    }
+}
+#[doc = "Field `ENDTX` reader - Write '1' to disable interrupt for event ENDTX"]
+pub type ENDTX_R = crate::BitReader<ENDTX_A>;
+#[doc = "Write '1' to disable interrupt for event ENDTX\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ENDTX_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<ENDTX_A> for bool {
+    #[inline(always)]
+    fn from(variant: ENDTX_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl ENDTX_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> ENDTX_A {
+        match self.bits {
+            false => ENDTX_A::DISABLED,
+            true => ENDTX_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == ENDTX_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == ENDTX_A::ENABLED
+    }
+}
+#[doc = "Write '1' to disable interrupt for event ENDTX\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ENDTX_AW {
+    #[doc = "1: Disable"]
+    CLEAR = 1,
+}
+impl From<ENDTX_AW> for bool {
+    #[inline(always)]
+    fn from(variant: ENDTX_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `ENDTX` writer - Write '1' to disable interrupt for event ENDTX"]
+pub type ENDTX_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, ENDTX_AW, O>;
+impl<'a, const O: u8> ENDTX_W<'a, O> {
+    #[doc = "Disable"]
+    #[inline(always)]
+    pub fn clear(self) -> &'a mut W {
+        self.variant(ENDTX_AW::CLEAR)
+    }
+}
+#[doc = "Field `STARTED` reader - Write '1' to disable interrupt for event STARTED"]
+pub type STARTED_R = crate::BitReader<STARTED_A>;
+#[doc = "Write '1' to disable interrupt for event STARTED\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum STARTED_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<STARTED_A> for bool {
+    #[inline(always)]
+    fn from(variant: STARTED_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl STARTED_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> STARTED_A {
+        match self.bits {
+            false => STARTED_A::DISABLED,
+            true => STARTED_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == STARTED_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == STARTED_A::ENABLED
+    }
+}
+#[doc = "Write '1' to disable interrupt for event STARTED\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum STARTED_AW {
+    #[doc = "1: Disable"]
+    CLEAR = 1,
+}
+impl From<STARTED_AW> for bool {
+    #[inline(always)]
+    fn from(variant: STARTED_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `STARTED` writer - Write '1' to disable interrupt for event STARTED"]
+pub type STARTED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, STARTED_AW, O>;
+impl<'a, const O: u8> STARTED_W<'a, O> {
+    #[doc = "Disable"]
+    #[inline(always)]
+    pub fn clear(self) -> &'a mut W {
+        self.variant(STARTED_AW::CLEAR)
+    }
+}
+impl R {
+    #[doc = "Bit 1 - Write '1' to disable interrupt for event STOPPED"]
+    #[inline(always)]
+    pub fn stopped(&self) -> STOPPED_R {
+        STOPPED_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Write '1' to disable interrupt for event ENDRX"]
+    #[inline(always)]
+    pub fn endrx(&self) -> ENDRX_R {
+        ENDRX_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 6 - Write '1' to disable interrupt for event END"]
+    #[inline(always)]
+    pub fn end(&self) -> END_R {
+        END_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 8 - Write '1' to disable interrupt for event ENDTX"]
+    #[inline(always)]
+    pub fn endtx(&self) -> ENDTX_R {
+        ENDTX_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 19 - Write '1' to disable interrupt for event STARTED"]
+    #[inline(always)]
+    pub fn started(&self) -> STARTED_R {
+        STARTED_R::new(((self.bits >> 19) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 1 - Write '1' to disable interrupt for event STOPPED"]
+    #[inline(always)]
+    pub fn stopped(&mut self) -> STOPPED_W<1> {
+        STOPPED_W::new(self)
+    }
+    #[doc = "Bit 4 - Write '1' to disable interrupt for event ENDRX"]
+    #[inline(always)]
+    pub fn endrx(&mut self) -> ENDRX_W<4> {
+        ENDRX_W::new(self)
+    }
+    #[doc = "Bit 6 - Write '1' to disable interrupt for event END"]
+    #[inline(always)]
+    pub fn end(&mut self) -> END_W<6> {
+        END_W::new(self)
+    }
+    #[doc = "Bit 8 - Write '1' to disable interrupt for event ENDTX"]
+    #[inline(always)]
+    pub fn endtx(&mut self) -> ENDTX_W<8> {
+        ENDTX_W::new(self)
+    }
+    #[doc = "Bit 19 - Write '1' to disable interrupt for event STARTED"]
+    #[inline(always)]
+    pub fn started(&mut self) -> STARTED_W<19> {
+        STARTED_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Disable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"]
+pub struct INTENCLR_SPEC;
+impl crate::RegisterSpec for INTENCLR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [intenclr::R](R) reader structure"]
+impl crate::Readable for INTENCLR_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"]
+impl crate::Writable for INTENCLR_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets INTENCLR to value 0"]
+impl crate::Resettable for INTENCLR_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf52833-pac/src/spim0/intenset.rs

@@ -0,0 +1,401 @@
+#[doc = "Register `INTENSET` reader"]
+pub struct R(crate::R<INTENSET_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<INTENSET_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<INTENSET_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<INTENSET_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `INTENSET` writer"]
+pub struct W(crate::W<INTENSET_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<INTENSET_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<INTENSET_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<INTENSET_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `STOPPED` reader - Write '1' to enable interrupt for event STOPPED"]
+pub type STOPPED_R = crate::BitReader<STOPPED_A>;
+#[doc = "Write '1' to enable interrupt for event STOPPED\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum STOPPED_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<STOPPED_A> for bool {
+    #[inline(always)]
+    fn from(variant: STOPPED_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl STOPPED_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> STOPPED_A {
+        match self.bits {
+            false => STOPPED_A::DISABLED,
+            true => STOPPED_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == STOPPED_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == STOPPED_A::ENABLED
+    }
+}
+#[doc = "Write '1' to enable interrupt for event STOPPED\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum STOPPED_AW {
+    #[doc = "1: Enable"]
+    SET = 1,
+}
+impl From<STOPPED_AW> for bool {
+    #[inline(always)]
+    fn from(variant: STOPPED_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `STOPPED` writer - Write '1' to enable interrupt for event STOPPED"]
+pub type STOPPED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, STOPPED_AW, O>;
+impl<'a, const O: u8> STOPPED_W<'a, O> {
+    #[doc = "Enable"]
+    #[inline(always)]
+    pub fn set(self) -> &'a mut W {
+        self.variant(STOPPED_AW::SET)
+    }
+}
+#[doc = "Field `ENDRX` reader - Write '1' to enable interrupt for event ENDRX"]
+pub type ENDRX_R = crate::BitReader<ENDRX_A>;
+#[doc = "Write '1' to enable interrupt for event ENDRX\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ENDRX_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<ENDRX_A> for bool {
+    #[inline(always)]
+    fn from(variant: ENDRX_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl ENDRX_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> ENDRX_A {
+        match self.bits {
+            false => ENDRX_A::DISABLED,
+            true => ENDRX_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == ENDRX_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == ENDRX_A::ENABLED
+    }
+}
+#[doc = "Write '1' to enable interrupt for event ENDRX\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ENDRX_AW {
+    #[doc = "1: Enable"]
+    SET = 1,
+}
+impl From<ENDRX_AW> for bool {
+    #[inline(always)]
+    fn from(variant: ENDRX_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `ENDRX` writer - Write '1' to enable interrupt for event ENDRX"]
+pub type ENDRX_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, ENDRX_AW, O>;
+impl<'a, const O: u8> ENDRX_W<'a, O> {
+    #[doc = "Enable"]
+    #[inline(always)]
+    pub fn set(self) -> &'a mut W {
+        self.variant(ENDRX_AW::SET)
+    }
+}
+#[doc = "Field `END` reader - Write '1' to enable interrupt for event END"]
+pub type END_R = crate::BitReader<END_A>;
+#[doc = "Write '1' to enable interrupt for event END\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum END_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<END_A> for bool {
+    #[inline(always)]
+    fn from(variant: END_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl END_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> END_A {
+        match self.bits {
+            false => END_A::DISABLED,
+            true => END_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == END_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == END_A::ENABLED
+    }
+}
+#[doc = "Write '1' to enable interrupt for event END\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum END_AW {
+    #[doc = "1: Enable"]
+    SET = 1,
+}
+impl From<END_AW> for bool {
+    #[inline(always)]
+    fn from(variant: END_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `END` writer - Write '1' to enable interrupt for event END"]
+pub type END_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, END_AW, O>;
+impl<'a, const O: u8> END_W<'a, O> {
+    #[doc = "Enable"]
+    #[inline(always)]
+    pub fn set(self) -> &'a mut W {
+        self.variant(END_AW::SET)
+    }
+}
+#[doc = "Field `ENDTX` reader - Write '1' to enable interrupt for event ENDTX"]
+pub type ENDTX_R = crate::BitReader<ENDTX_A>;
+#[doc = "Write '1' to enable interrupt for event ENDTX\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ENDTX_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<ENDTX_A> for bool {
+    #[inline(always)]
+    fn from(variant: ENDTX_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl ENDTX_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> ENDTX_A {
+        match self.bits {
+            false => ENDTX_A::DISABLED,
+            true => ENDTX_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == ENDTX_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == ENDTX_A::ENABLED
+    }
+}
+#[doc = "Write '1' to enable interrupt for event ENDTX\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ENDTX_AW {
+    #[doc = "1: Enable"]
+    SET = 1,
+}
+impl From<ENDTX_AW> for bool {
+    #[inline(always)]
+    fn from(variant: ENDTX_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `ENDTX` writer - Write '1' to enable interrupt for event ENDTX"]
+pub type ENDTX_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, ENDTX_AW, O>;
+impl<'a, const O: u8> ENDTX_W<'a, O> {
+    #[doc = "Enable"]
+    #[inline(always)]
+    pub fn set(self) -> &'a mut W {
+        self.variant(ENDTX_AW::SET)
+    }
+}
+#[doc = "Field `STARTED` reader - Write '1' to enable interrupt for event STARTED"]
+pub type STARTED_R = crate::BitReader<STARTED_A>;
+#[doc = "Write '1' to enable interrupt for event STARTED\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum STARTED_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<STARTED_A> for bool {
+    #[inline(always)]
+    fn from(variant: STARTED_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl STARTED_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> STARTED_A {
+        match self.bits {
+            false => STARTED_A::DISABLED,
+            true => STARTED_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == STARTED_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == STARTED_A::ENABLED
+    }
+}
+#[doc = "Write '1' to enable interrupt for event STARTED\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum STARTED_AW {
+    #[doc = "1: Enable"]
+    SET = 1,
+}
+impl From<STARTED_AW> for bool {
+    #[inline(always)]
+    fn from(variant: STARTED_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `STARTED` writer - Write '1' to enable interrupt for event STARTED"]
+pub type STARTED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, STARTED_AW, O>;
+impl<'a, const O: u8> STARTED_W<'a, O> {
+    #[doc = "Enable"]
+    #[inline(always)]
+    pub fn set(self) -> &'a mut W {
+        self.variant(STARTED_AW::SET)
+    }
+}
+impl R {
+    #[doc = "Bit 1 - Write '1' to enable interrupt for event STOPPED"]
+    #[inline(always)]
+    pub fn stopped(&self) -> STOPPED_R {
+        STOPPED_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Write '1' to enable interrupt for event ENDRX"]
+    #[inline(always)]
+    pub fn endrx(&self) -> ENDRX_R {
+        ENDRX_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 6 - Write '1' to enable interrupt for event END"]
+    #[inline(always)]
+    pub fn end(&self) -> END_R {
+        END_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 8 - Write '1' to enable interrupt for event ENDTX"]
+    #[inline(always)]
+    pub fn endtx(&self) -> ENDTX_R {
+        ENDTX_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 19 - Write '1' to enable interrupt for event STARTED"]
+    #[inline(always)]
+    pub fn started(&self) -> STARTED_R {
+        STARTED_R::new(((self.bits >> 19) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 1 - Write '1' to enable interrupt for event STOPPED"]
+    #[inline(always)]
+    pub fn stopped(&mut self) -> STOPPED_W<1> {
+        STOPPED_W::new(self)
+    }
+    #[doc = "Bit 4 - Write '1' to enable interrupt for event ENDRX"]
+    #[inline(always)]
+    pub fn endrx(&mut self) -> ENDRX_W<4> {
+        ENDRX_W::new(self)
+    }
+    #[doc = "Bit 6 - Write '1' to enable interrupt for event END"]
+    #[inline(always)]
+    pub fn end(&mut self) -> END_W<6> {
+        END_W::new(self)
+    }
+    #[doc = "Bit 8 - Write '1' to enable interrupt for event ENDTX"]
+    #[inline(always)]
+    pub fn endtx(&mut self) -> ENDTX_W<8> {
+        ENDTX_W::new(self)
+    }
+    #[doc = "Bit 19 - Write '1' to enable interrupt for event STARTED"]
+    #[inline(always)]
+    pub fn started(&mut self) -> STARTED_W<19> {
+        STARTED_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Enable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"]
+pub struct INTENSET_SPEC;
+impl crate::RegisterSpec for INTENSET_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [intenset::R](R) reader structure"]
+impl crate::Readable for INTENSET_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"]
+impl crate::Writable for INTENSET_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets INTENSET to value 0"]
+impl crate::Resettable for INTENSET_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf52833-pac/src/spim0/orc.rs

@@ -0,0 +1,80 @@
+#[doc = "Register `ORC` reader"]
+pub struct R(crate::R<ORC_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<ORC_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<ORC_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<ORC_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `ORC` writer"]
+pub struct W(crate::W<ORC_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<ORC_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<ORC_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<ORC_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `ORC` reader - Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT."]
+pub type ORC_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `ORC` writer - Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT."]
+pub type ORC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ORC_SPEC, u8, u8, 8, O>;
+impl R {
+    #[doc = "Bits 0:7 - Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT."]
+    #[inline(always)]
+    pub fn orc(&self) -> ORC_R {
+        ORC_R::new((self.bits & 0xff) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT."]
+    #[inline(always)]
+    pub fn orc(&mut self) -> ORC_W<0> {
+        ORC_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [orc](index.html) module"]
+pub struct ORC_SPEC;
+impl crate::RegisterSpec for ORC_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [orc::R](R) reader structure"]
+impl crate::Readable for ORC_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [orc::W](W) writer structure"]
+impl crate::Writable for ORC_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets ORC to value 0"]
+impl crate::Resettable for ORC_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf52833-pac/src/spim0/psel.rs

@@ -0,0 +1,28 @@
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct PSEL {
+    #[doc = "0x00 - Pin select for SCK"]
+    pub sck: SCK,
+    #[doc = "0x04 - Pin select for MOSI signal"]
+    pub mosi: MOSI,
+    #[doc = "0x08 - Pin select for MISO signal"]
+    pub miso: MISO,
+    #[doc = "0x0c - Pin select for CSN"]
+    pub csn: CSN,
+}
+#[doc = "SCK (rw) register accessor: an alias for `Reg<SCK_SPEC>`"]
+pub type SCK = crate::Reg<sck::SCK_SPEC>;
+#[doc = "Pin select for SCK"]
+pub mod sck;
+#[doc = "MOSI (rw) register accessor: an alias for `Reg<MOSI_SPEC>`"]
+pub type MOSI = crate::Reg<mosi::MOSI_SPEC>;
+#[doc = "Pin select for MOSI signal"]
+pub mod mosi;
+#[doc = "MISO (rw) register accessor: an alias for `Reg<MISO_SPEC>`"]
+pub type MISO = crate::Reg<miso::MISO_SPEC>;
+#[doc = "Pin select for MISO signal"]
+pub mod miso;
+#[doc = "CSN (rw) register accessor: an alias for `Reg<CSN_SPEC>`"]
+pub type CSN = crate::Reg<csn::CSN_SPEC>;
+#[doc = "Pin select for CSN"]
+pub mod csn;

vendor/nrf52833-pac/src/spim0/psel/csn.rs

@@ -0,0 +1,154 @@
+#[doc = "Register `CSN` reader"]
+pub struct R(crate::R<CSN_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<CSN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<CSN_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<CSN_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `CSN` writer"]
+pub struct W(crate::W<CSN_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<CSN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<CSN_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<CSN_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `PIN` reader - Pin number"]
+pub type PIN_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `PIN` writer - Pin number"]
+pub type PIN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CSN_SPEC, u8, u8, 5, O>;
+#[doc = "Field `PORT` reader - Port number"]
+pub type PORT_R = crate::BitReader<bool>;
+#[doc = "Field `PORT` writer - Port number"]
+pub type PORT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CSN_SPEC, bool, O>;
+#[doc = "Field `CONNECT` reader - Connection"]
+pub type CONNECT_R = crate::BitReader<CONNECT_A>;
+#[doc = "Connection\n\nValue on reset: 1"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CONNECT_A {
+    #[doc = "1: Disconnect"]
+    DISCONNECTED = 1,
+    #[doc = "0: Connect"]
+    CONNECTED = 0,
+}
+impl From<CONNECT_A> for bool {
+    #[inline(always)]
+    fn from(variant: CONNECT_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl CONNECT_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> CONNECT_A {
+        match self.bits {
+            true => CONNECT_A::DISCONNECTED,
+            false => CONNECT_A::CONNECTED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISCONNECTED`"]
+    #[inline(always)]
+    pub fn is_disconnected(&self) -> bool {
+        *self == CONNECT_A::DISCONNECTED
+    }
+    #[doc = "Checks if the value of the field is `CONNECTED`"]
+    #[inline(always)]
+    pub fn is_connected(&self) -> bool {
+        *self == CONNECT_A::CONNECTED
+    }
+}
+#[doc = "Field `CONNECT` writer - Connection"]
+pub type CONNECT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CSN_SPEC, CONNECT_A, O>;
+impl<'a, const O: u8> CONNECT_W<'a, O> {
+    #[doc = "Disconnect"]
+    #[inline(always)]
+    pub fn disconnected(self) -> &'a mut W {
+        self.variant(CONNECT_A::DISCONNECTED)
+    }
+    #[doc = "Connect"]
+    #[inline(always)]
+    pub fn connected(self) -> &'a mut W {
+        self.variant(CONNECT_A::CONNECTED)
+    }
+}
+impl R {
+    #[doc = "Bits 0:4 - Pin number"]
+    #[inline(always)]
+    pub fn pin(&self) -> PIN_R {
+        PIN_R::new((self.bits & 0x1f) as u8)
+    }
+    #[doc = "Bit 5 - Port number"]
+    #[inline(always)]
+    pub fn port(&self) -> PORT_R {
+        PORT_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 31 - Connection"]
+    #[inline(always)]
+    pub fn connect(&self) -> CONNECT_R {
+        CONNECT_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:4 - Pin number"]
+    #[inline(always)]
+    pub fn pin(&mut self) -> PIN_W<0> {
+        PIN_W::new(self)
+    }
+    #[doc = "Bit 5 - Port number"]
+    #[inline(always)]
+    pub fn port(&mut self) -> PORT_W<5> {
+        PORT_W::new(self)
+    }
+    #[doc = "Bit 31 - Connection"]
+    #[inline(always)]
+    pub fn connect(&mut self) -> CONNECT_W<31> {
+        CONNECT_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Pin select for CSN\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [csn](index.html) module"]
+pub struct CSN_SPEC;
+impl crate::RegisterSpec for CSN_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [csn::R](R) reader structure"]
+impl crate::Readable for CSN_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [csn::W](W) writer structure"]
+impl crate::Writable for CSN_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets CSN to value 0xffff_ffff"]
+impl crate::Resettable for CSN_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0xffff_ffff
+    }
+}

vendor/nrf52833-pac/src/spim0/psel/miso.rs

@@ -0,0 +1,154 @@
+#[doc = "Register `MISO` reader"]
+pub struct R(crate::R<MISO_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<MISO_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<MISO_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<MISO_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `MISO` writer"]
+pub struct W(crate::W<MISO_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<MISO_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<MISO_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<MISO_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `PIN` reader - Pin number"]
+pub type PIN_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `PIN` writer - Pin number"]
+pub type PIN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MISO_SPEC, u8, u8, 5, O>;
+#[doc = "Field `PORT` reader - Port number"]
+pub type PORT_R = crate::BitReader<bool>;
+#[doc = "Field `PORT` writer - Port number"]
+pub type PORT_W<'a, const O: u8> = crate::BitWriter<'a, u32, MISO_SPEC, bool, O>;
+#[doc = "Field `CONNECT` reader - Connection"]
+pub type CONNECT_R = crate::BitReader<CONNECT_A>;
+#[doc = "Connection\n\nValue on reset: 1"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CONNECT_A {
+    #[doc = "1: Disconnect"]
+    DISCONNECTED = 1,
+    #[doc = "0: Connect"]
+    CONNECTED = 0,
+}
+impl From<CONNECT_A> for bool {
+    #[inline(always)]
+    fn from(variant: CONNECT_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl CONNECT_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> CONNECT_A {
+        match self.bits {
+            true => CONNECT_A::DISCONNECTED,
+            false => CONNECT_A::CONNECTED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISCONNECTED`"]
+    #[inline(always)]
+    pub fn is_disconnected(&self) -> bool {
+        *self == CONNECT_A::DISCONNECTED
+    }
+    #[doc = "Checks if the value of the field is `CONNECTED`"]
+    #[inline(always)]
+    pub fn is_connected(&self) -> bool {
+        *self == CONNECT_A::CONNECTED
+    }
+}
+#[doc = "Field `CONNECT` writer - Connection"]
+pub type CONNECT_W<'a, const O: u8> = crate::BitWriter<'a, u32, MISO_SPEC, CONNECT_A, O>;
+impl<'a, const O: u8> CONNECT_W<'a, O> {
+    #[doc = "Disconnect"]
+    #[inline(always)]
+    pub fn disconnected(self) -> &'a mut W {
+        self.variant(CONNECT_A::DISCONNECTED)
+    }
+    #[doc = "Connect"]
+    #[inline(always)]
+    pub fn connected(self) -> &'a mut W {
+        self.variant(CONNECT_A::CONNECTED)
+    }
+}
+impl R {
+    #[doc = "Bits 0:4 - Pin number"]
+    #[inline(always)]
+    pub fn pin(&self) -> PIN_R {
+        PIN_R::new((self.bits & 0x1f) as u8)
+    }
+    #[doc = "Bit 5 - Port number"]
+    #[inline(always)]
+    pub fn port(&self) -> PORT_R {
+        PORT_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 31 - Connection"]
+    #[inline(always)]
+    pub fn connect(&self) -> CONNECT_R {
+        CONNECT_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:4 - Pin number"]
+    #[inline(always)]
+    pub fn pin(&mut self) -> PIN_W<0> {
+        PIN_W::new(self)
+    }
+    #[doc = "Bit 5 - Port number"]
+    #[inline(always)]
+    pub fn port(&mut self) -> PORT_W<5> {
+        PORT_W::new(self)
+    }
+    #[doc = "Bit 31 - Connection"]
+    #[inline(always)]
+    pub fn connect(&mut self) -> CONNECT_W<31> {
+        CONNECT_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Pin select for MISO signal\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [miso](index.html) module"]
+pub struct MISO_SPEC;
+impl crate::RegisterSpec for MISO_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [miso::R](R) reader structure"]
+impl crate::Readable for MISO_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [miso::W](W) writer structure"]
+impl crate::Writable for MISO_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets MISO to value 0xffff_ffff"]
+impl crate::Resettable for MISO_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0xffff_ffff
+    }
+}

vendor/nrf52833-pac/src/spim0/psel/mosi.rs

@@ -0,0 +1,154 @@
+#[doc = "Register `MOSI` reader"]
+pub struct R(crate::R<MOSI_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<MOSI_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<MOSI_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<MOSI_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `MOSI` writer"]
+pub struct W(crate::W<MOSI_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<MOSI_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<MOSI_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<MOSI_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `PIN` reader - Pin number"]
+pub type PIN_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `PIN` writer - Pin number"]
+pub type PIN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MOSI_SPEC, u8, u8, 5, O>;
+#[doc = "Field `PORT` reader - Port number"]
+pub type PORT_R = crate::BitReader<bool>;
+#[doc = "Field `PORT` writer - Port number"]
+pub type PORT_W<'a, const O: u8> = crate::BitWriter<'a, u32, MOSI_SPEC, bool, O>;
+#[doc = "Field `CONNECT` reader - Connection"]
+pub type CONNECT_R = crate::BitReader<CONNECT_A>;
+#[doc = "Connection\n\nValue on reset: 1"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CONNECT_A {
+    #[doc = "1: Disconnect"]
+    DISCONNECTED = 1,
+    #[doc = "0: Connect"]
+    CONNECTED = 0,
+}
+impl From<CONNECT_A> for bool {
+    #[inline(always)]
+    fn from(variant: CONNECT_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl CONNECT_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> CONNECT_A {
+        match self.bits {
+            true => CONNECT_A::DISCONNECTED,
+            false => CONNECT_A::CONNECTED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISCONNECTED`"]
+    #[inline(always)]
+    pub fn is_disconnected(&self) -> bool {
+        *self == CONNECT_A::DISCONNECTED
+    }
+    #[doc = "Checks if the value of the field is `CONNECTED`"]
+    #[inline(always)]
+    pub fn is_connected(&self) -> bool {
+        *self == CONNECT_A::CONNECTED
+    }
+}
+#[doc = "Field `CONNECT` writer - Connection"]
+pub type CONNECT_W<'a, const O: u8> = crate::BitWriter<'a, u32, MOSI_SPEC, CONNECT_A, O>;
+impl<'a, const O: u8> CONNECT_W<'a, O> {
+    #[doc = "Disconnect"]
+    #[inline(always)]
+    pub fn disconnected(self) -> &'a mut W {
+        self.variant(CONNECT_A::DISCONNECTED)
+    }
+    #[doc = "Connect"]
+    #[inline(always)]
+    pub fn connected(self) -> &'a mut W {
+        self.variant(CONNECT_A::CONNECTED)
+    }
+}
+impl R {
+    #[doc = "Bits 0:4 - Pin number"]
+    #[inline(always)]
+    pub fn pin(&self) -> PIN_R {
+        PIN_R::new((self.bits & 0x1f) as u8)
+    }
+    #[doc = "Bit 5 - Port number"]
+    #[inline(always)]
+    pub fn port(&self) -> PORT_R {
+        PORT_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 31 - Connection"]
+    #[inline(always)]
+    pub fn connect(&self) -> CONNECT_R {
+        CONNECT_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:4 - Pin number"]
+    #[inline(always)]
+    pub fn pin(&mut self) -> PIN_W<0> {
+        PIN_W::new(self)
+    }
+    #[doc = "Bit 5 - Port number"]
+    #[inline(always)]
+    pub fn port(&mut self) -> PORT_W<5> {
+        PORT_W::new(self)
+    }
+    #[doc = "Bit 31 - Connection"]
+    #[inline(always)]
+    pub fn connect(&mut self) -> CONNECT_W<31> {
+        CONNECT_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Pin select for MOSI signal\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mosi](index.html) module"]
+pub struct MOSI_SPEC;
+impl crate::RegisterSpec for MOSI_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [mosi::R](R) reader structure"]
+impl crate::Readable for MOSI_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [mosi::W](W) writer structure"]
+impl crate::Writable for MOSI_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets MOSI to value 0xffff_ffff"]
+impl crate::Resettable for MOSI_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0xffff_ffff
+    }
+}

vendor/nrf52833-pac/src/spim0/psel/sck.rs

@@ -0,0 +1,154 @@
+#[doc = "Register `SCK` reader"]
+pub struct R(crate::R<SCK_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<SCK_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<SCK_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<SCK_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `SCK` writer"]
+pub struct W(crate::W<SCK_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<SCK_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<SCK_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<SCK_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `PIN` reader - Pin number"]
+pub type PIN_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `PIN` writer - Pin number"]
+pub type PIN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SCK_SPEC, u8, u8, 5, O>;
+#[doc = "Field `PORT` reader - Port number"]
+pub type PORT_R = crate::BitReader<bool>;
+#[doc = "Field `PORT` writer - Port number"]
+pub type PORT_W<'a, const O: u8> = crate::BitWriter<'a, u32, SCK_SPEC, bool, O>;
+#[doc = "Field `CONNECT` reader - Connection"]
+pub type CONNECT_R = crate::BitReader<CONNECT_A>;
+#[doc = "Connection\n\nValue on reset: 1"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CONNECT_A {
+    #[doc = "1: Disconnect"]
+    DISCONNECTED = 1,
+    #[doc = "0: Connect"]
+    CONNECTED = 0,
+}
+impl From<CONNECT_A> for bool {
+    #[inline(always)]
+    fn from(variant: CONNECT_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl CONNECT_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> CONNECT_A {
+        match self.bits {
+            true => CONNECT_A::DISCONNECTED,
+            false => CONNECT_A::CONNECTED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISCONNECTED`"]
+    #[inline(always)]
+    pub fn is_disconnected(&self) -> bool {
+        *self == CONNECT_A::DISCONNECTED
+    }
+    #[doc = "Checks if the value of the field is `CONNECTED`"]
+    #[inline(always)]
+    pub fn is_connected(&self) -> bool {
+        *self == CONNECT_A::CONNECTED
+    }
+}
+#[doc = "Field `CONNECT` writer - Connection"]
+pub type CONNECT_W<'a, const O: u8> = crate::BitWriter<'a, u32, SCK_SPEC, CONNECT_A, O>;
+impl<'a, const O: u8> CONNECT_W<'a, O> {
+    #[doc = "Disconnect"]
+    #[inline(always)]
+    pub fn disconnected(self) -> &'a mut W {
+        self.variant(CONNECT_A::DISCONNECTED)
+    }
+    #[doc = "Connect"]
+    #[inline(always)]
+    pub fn connected(self) -> &'a mut W {
+        self.variant(CONNECT_A::CONNECTED)
+    }
+}
+impl R {
+    #[doc = "Bits 0:4 - Pin number"]
+    #[inline(always)]
+    pub fn pin(&self) -> PIN_R {
+        PIN_R::new((self.bits & 0x1f) as u8)
+    }
+    #[doc = "Bit 5 - Port number"]
+    #[inline(always)]
+    pub fn port(&self) -> PORT_R {
+        PORT_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 31 - Connection"]
+    #[inline(always)]
+    pub fn connect(&self) -> CONNECT_R {
+        CONNECT_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:4 - Pin number"]
+    #[inline(always)]
+    pub fn pin(&mut self) -> PIN_W<0> {
+        PIN_W::new(self)
+    }
+    #[doc = "Bit 5 - Port number"]
+    #[inline(always)]
+    pub fn port(&mut self) -> PORT_W<5> {
+        PORT_W::new(self)
+    }
+    #[doc = "Bit 31 - Connection"]
+    #[inline(always)]
+    pub fn connect(&mut self) -> CONNECT_W<31> {
+        CONNECT_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Pin select for SCK\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sck](index.html) module"]
+pub struct SCK_SPEC;
+impl crate::RegisterSpec for SCK_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [sck::R](R) reader structure"]
+impl crate::Readable for SCK_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [sck::W](W) writer structure"]
+impl crate::Writable for SCK_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets SCK to value 0xffff_ffff"]
+impl crate::Resettable for SCK_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0xffff_ffff
+    }
+}

vendor/nrf52833-pac/src/spim0/pseldcx.rs

@@ -0,0 +1,154 @@
+#[doc = "Register `PSELDCX` reader"]
+pub struct R(crate::R<PSELDCX_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<PSELDCX_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<PSELDCX_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<PSELDCX_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `PSELDCX` writer"]
+pub struct W(crate::W<PSELDCX_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<PSELDCX_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<PSELDCX_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<PSELDCX_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `PIN` reader - Pin number"]
+pub type PIN_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `PIN` writer - Pin number"]
+pub type PIN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PSELDCX_SPEC, u8, u8, 5, O>;
+#[doc = "Field `PORT` reader - Port number"]
+pub type PORT_R = crate::BitReader<bool>;
+#[doc = "Field `PORT` writer - Port number"]
+pub type PORT_W<'a, const O: u8> = crate::BitWriter<'a, u32, PSELDCX_SPEC, bool, O>;
+#[doc = "Field `CONNECT` reader - Connection"]
+pub type CONNECT_R = crate::BitReader<CONNECT_A>;
+#[doc = "Connection\n\nValue on reset: 1"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CONNECT_A {
+    #[doc = "1: Disconnect"]
+    DISCONNECTED = 1,
+    #[doc = "0: Connect"]
+    CONNECTED = 0,
+}
+impl From<CONNECT_A> for bool {
+    #[inline(always)]
+    fn from(variant: CONNECT_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl CONNECT_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> CONNECT_A {
+        match self.bits {
+            true => CONNECT_A::DISCONNECTED,
+            false => CONNECT_A::CONNECTED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISCONNECTED`"]
+    #[inline(always)]
+    pub fn is_disconnected(&self) -> bool {
+        *self == CONNECT_A::DISCONNECTED
+    }
+    #[doc = "Checks if the value of the field is `CONNECTED`"]
+    #[inline(always)]
+    pub fn is_connected(&self) -> bool {
+        *self == CONNECT_A::CONNECTED
+    }
+}
+#[doc = "Field `CONNECT` writer - Connection"]
+pub type CONNECT_W<'a, const O: u8> = crate::BitWriter<'a, u32, PSELDCX_SPEC, CONNECT_A, O>;
+impl<'a, const O: u8> CONNECT_W<'a, O> {
+    #[doc = "Disconnect"]
+    #[inline(always)]
+    pub fn disconnected(self) -> &'a mut W {
+        self.variant(CONNECT_A::DISCONNECTED)
+    }
+    #[doc = "Connect"]
+    #[inline(always)]
+    pub fn connected(self) -> &'a mut W {
+        self.variant(CONNECT_A::CONNECTED)
+    }
+}
+impl R {
+    #[doc = "Bits 0:4 - Pin number"]
+    #[inline(always)]
+    pub fn pin(&self) -> PIN_R {
+        PIN_R::new((self.bits & 0x1f) as u8)
+    }
+    #[doc = "Bit 5 - Port number"]
+    #[inline(always)]
+    pub fn port(&self) -> PORT_R {
+        PORT_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 31 - Connection"]
+    #[inline(always)]
+    pub fn connect(&self) -> CONNECT_R {
+        CONNECT_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:4 - Pin number"]
+    #[inline(always)]
+    pub fn pin(&mut self) -> PIN_W<0> {
+        PIN_W::new(self)
+    }
+    #[doc = "Bit 5 - Port number"]
+    #[inline(always)]
+    pub fn port(&mut self) -> PORT_W<5> {
+        PORT_W::new(self)
+    }
+    #[doc = "Bit 31 - Connection"]
+    #[inline(always)]
+    pub fn connect(&mut self) -> CONNECT_W<31> {
+        CONNECT_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Pin select for DCX signal\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pseldcx](index.html) module"]
+pub struct PSELDCX_SPEC;
+impl crate::RegisterSpec for PSELDCX_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [pseldcx::R](R) reader structure"]
+impl crate::Readable for PSELDCX_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [pseldcx::W](W) writer structure"]
+impl crate::Writable for PSELDCX_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets PSELDCX to value 0xffff_ffff"]
+impl crate::Resettable for PSELDCX_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0xffff_ffff
+    }
+}

vendor/nrf52833-pac/src/spim0/rxd.rs

@@ -0,0 +1,28 @@
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct RXD {
+    #[doc = "0x00 - Data pointer"]
+    pub ptr: PTR,
+    #[doc = "0x04 - Maximum number of bytes in receive buffer"]
+    pub maxcnt: MAXCNT,
+    #[doc = "0x08 - Number of bytes transferred in the last transaction"]
+    pub amount: AMOUNT,
+    #[doc = "0x0c - EasyDMA list type"]
+    pub list: LIST,
+}
+#[doc = "PTR (rw) register accessor: an alias for `Reg<PTR_SPEC>`"]
+pub type PTR = crate::Reg<ptr::PTR_SPEC>;
+#[doc = "Data pointer"]
+pub mod ptr;
+#[doc = "MAXCNT (rw) register accessor: an alias for `Reg<MAXCNT_SPEC>`"]
+pub type MAXCNT = crate::Reg<maxcnt::MAXCNT_SPEC>;
+#[doc = "Maximum number of bytes in receive buffer"]
+pub mod maxcnt;
+#[doc = "AMOUNT (r) register accessor: an alias for `Reg<AMOUNT_SPEC>`"]
+pub type AMOUNT = crate::Reg<amount::AMOUNT_SPEC>;
+#[doc = "Number of bytes transferred in the last transaction"]
+pub mod amount;
+#[doc = "LIST (rw) register accessor: an alias for `Reg<LIST_SPEC>`"]
+pub type LIST = crate::Reg<list::LIST_SPEC>;
+#[doc = "EasyDMA list type"]
+pub mod list;

vendor/nrf52833-pac/src/spim0/rxd/amount.rs

@@ -0,0 +1,40 @@
+#[doc = "Register `AMOUNT` reader"]
+pub struct R(crate::R<AMOUNT_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<AMOUNT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<AMOUNT_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<AMOUNT_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `AMOUNT` reader - Number of bytes transferred in the last transaction"]
+pub type AMOUNT_R = crate::FieldReader<u16, u16>;
+impl R {
+    #[doc = "Bits 0:15 - Number of bytes transferred in the last transaction"]
+    #[inline(always)]
+    pub fn amount(&self) -> AMOUNT_R {
+        AMOUNT_R::new((self.bits & 0xffff) as u16)
+    }
+}
+#[doc = "Number of bytes transferred in the last transaction\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [amount](index.html) module"]
+pub struct AMOUNT_SPEC;
+impl crate::RegisterSpec for AMOUNT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [amount::R](R) reader structure"]
+impl crate::Readable for AMOUNT_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets AMOUNT to value 0"]
+impl crate::Resettable for AMOUNT_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf52833-pac/src/spim0/rxd/list.rs

@@ -0,0 +1,128 @@
+#[doc = "Register `LIST` reader"]
+pub struct R(crate::R<LIST_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<LIST_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<LIST_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<LIST_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `LIST` writer"]
+pub struct W(crate::W<LIST_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<LIST_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<LIST_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<LIST_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `LIST` reader - List type"]
+pub type LIST_R = crate::FieldReader<u8, LIST_A>;
+#[doc = "List type\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum LIST_A {
+    #[doc = "0: Disable EasyDMA list"]
+    DISABLED = 0,
+    #[doc = "1: Use array list"]
+    ARRAY_LIST = 1,
+}
+impl From<LIST_A> for u8 {
+    #[inline(always)]
+    fn from(variant: LIST_A) -> Self {
+        variant as _
+    }
+}
+impl LIST_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<LIST_A> {
+        match self.bits {
+            0 => Some(LIST_A::DISABLED),
+            1 => Some(LIST_A::ARRAY_LIST),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == LIST_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ARRAY_LIST`"]
+    #[inline(always)]
+    pub fn is_array_list(&self) -> bool {
+        *self == LIST_A::ARRAY_LIST
+    }
+}
+#[doc = "Field `LIST` writer - List type"]
+pub type LIST_W<'a, const O: u8> = crate::FieldWriter<'a, u32, LIST_SPEC, u8, LIST_A, 2, O>;
+impl<'a, const O: u8> LIST_W<'a, O> {
+    #[doc = "Disable EasyDMA list"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(LIST_A::DISABLED)
+    }
+    #[doc = "Use array list"]
+    #[inline(always)]
+    pub fn array_list(self) -> &'a mut W {
+        self.variant(LIST_A::ARRAY_LIST)
+    }
+}
+impl R {
+    #[doc = "Bits 0:1 - List type"]
+    #[inline(always)]
+    pub fn list(&self) -> LIST_R {
+        LIST_R::new((self.bits & 3) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:1 - List type"]
+    #[inline(always)]
+    pub fn list(&mut self) -> LIST_W<0> {
+        LIST_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "EasyDMA list type\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [list](index.html) module"]
+pub struct LIST_SPEC;
+impl crate::RegisterSpec for LIST_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [list::R](R) reader structure"]
+impl crate::Readable for LIST_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [list::W](W) writer structure"]
+impl crate::Writable for LIST_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets LIST to value 0"]
+impl crate::Resettable for LIST_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf52833-pac/src/spim0/rxd/maxcnt.rs

@@ -0,0 +1,80 @@
+#[doc = "Register `MAXCNT` reader"]
+pub struct R(crate::R<MAXCNT_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<MAXCNT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<MAXCNT_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<MAXCNT_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `MAXCNT` writer"]
+pub struct W(crate::W<MAXCNT_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<MAXCNT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<MAXCNT_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<MAXCNT_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `MAXCNT` reader - Maximum number of bytes in receive buffer"]
+pub type MAXCNT_R = crate::FieldReader<u16, u16>;
+#[doc = "Field `MAXCNT` writer - Maximum number of bytes in receive buffer"]
+pub type MAXCNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MAXCNT_SPEC, u16, u16, 16, O>;
+impl R {
+    #[doc = "Bits 0:15 - Maximum number of bytes in receive buffer"]
+    #[inline(always)]
+    pub fn maxcnt(&self) -> MAXCNT_R {
+        MAXCNT_R::new((self.bits & 0xffff) as u16)
+    }
+}
+impl W {
+    #[doc = "Bits 0:15 - Maximum number of bytes in receive buffer"]
+    #[inline(always)]
+    pub fn maxcnt(&mut self) -> MAXCNT_W<0> {
+        MAXCNT_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Maximum number of bytes in receive buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [maxcnt](index.html) module"]
+pub struct MAXCNT_SPEC;
+impl crate::RegisterSpec for MAXCNT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [maxcnt::R](R) reader structure"]
+impl crate::Readable for MAXCNT_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [maxcnt::W](W) writer structure"]
+impl crate::Writable for MAXCNT_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets MAXCNT to value 0"]
+impl crate::Resettable for MAXCNT_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf52833-pac/src/spim0/rxd/ptr.rs

@@ -0,0 +1,80 @@
+#[doc = "Register `PTR` reader"]
+pub struct R(crate::R<PTR_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<PTR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<PTR_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<PTR_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `PTR` writer"]
+pub struct W(crate::W<PTR_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<PTR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<PTR_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<PTR_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `PTR` reader - Data pointer"]
+pub type PTR_R = crate::FieldReader<u32, u32>;
+#[doc = "Field `PTR` writer - Data pointer"]
+pub type PTR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PTR_SPEC, u32, u32, 32, O>;
+impl R {
+    #[doc = "Bits 0:31 - Data pointer"]
+    #[inline(always)]
+    pub fn ptr(&self) -> PTR_R {
+        PTR_R::new(self.bits)
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Data pointer"]
+    #[inline(always)]
+    pub fn ptr(&mut self) -> PTR_W<0> {
+        PTR_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Data pointer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ptr](index.html) module"]
+pub struct PTR_SPEC;
+impl crate::RegisterSpec for PTR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [ptr::R](R) reader structure"]
+impl crate::Readable for PTR_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [ptr::W](W) writer structure"]
+impl crate::Writable for PTR_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets PTR to value 0"]
+impl crate::Resettable for PTR_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf52833-pac/src/spim0/shorts.rs

@@ -0,0 +1,126 @@
+#[doc = "Register `SHORTS` reader"]
+pub struct R(crate::R<SHORTS_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<SHORTS_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<SHORTS_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<SHORTS_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `SHORTS` writer"]
+pub struct W(crate::W<SHORTS_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<SHORTS_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<SHORTS_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<SHORTS_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `END_START` reader - Shortcut between event END and task START"]
+pub type END_START_R = crate::BitReader<END_START_A>;
+#[doc = "Shortcut between event END and task START\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum END_START_A {
+    #[doc = "0: Disable shortcut"]
+    DISABLED = 0,
+    #[doc = "1: Enable shortcut"]
+    ENABLED = 1,
+}
+impl From<END_START_A> for bool {
+    #[inline(always)]
+    fn from(variant: END_START_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl END_START_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> END_START_A {
+        match self.bits {
+            false => END_START_A::DISABLED,
+            true => END_START_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == END_START_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == END_START_A::ENABLED
+    }
+}
+#[doc = "Field `END_START` writer - Shortcut between event END and task START"]
+pub type END_START_W<'a, const O: u8> = crate::BitWriter<'a, u32, SHORTS_SPEC, END_START_A, O>;
+impl<'a, const O: u8> END_START_W<'a, O> {
+    #[doc = "Disable shortcut"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(END_START_A::DISABLED)
+    }
+    #[doc = "Enable shortcut"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(END_START_A::ENABLED)
+    }
+}
+impl R {
+    #[doc = "Bit 17 - Shortcut between event END and task START"]
+    #[inline(always)]
+    pub fn end_start(&self) -> END_START_R {
+        END_START_R::new(((self.bits >> 17) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 17 - Shortcut between event END and task START"]
+    #[inline(always)]
+    pub fn end_start(&mut self) -> END_START_W<17> {
+        END_START_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Shortcuts between local events and tasks\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [shorts](index.html) module"]
+pub struct SHORTS_SPEC;
+impl crate::RegisterSpec for SHORTS_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [shorts::R](R) reader structure"]
+impl crate::Readable for SHORTS_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [shorts::W](W) writer structure"]
+impl crate::Writable for SHORTS_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets SHORTS to value 0"]
+impl crate::Resettable for SHORTS_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf52833-pac/src/spim0/stallstat.rs

@@ -0,0 +1,186 @@
+#[doc = "Register `STALLSTAT` reader"]
+pub struct R(crate::R<STALLSTAT_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<STALLSTAT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<STALLSTAT_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<STALLSTAT_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `STALLSTAT` writer"]
+pub struct W(crate::W<STALLSTAT_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<STALLSTAT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<STALLSTAT_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<STALLSTAT_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `TX` reader - Stall status for EasyDMA RAM reads"]
+pub type TX_R = crate::BitReader<TX_A>;
+#[doc = "Stall status for EasyDMA RAM reads\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TX_A {
+    #[doc = "0: No stall"]
+    NOSTALL = 0,
+    #[doc = "1: A stall has occurred"]
+    STALL = 1,
+}
+impl From<TX_A> for bool {
+    #[inline(always)]
+    fn from(variant: TX_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl TX_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> TX_A {
+        match self.bits {
+            false => TX_A::NOSTALL,
+            true => TX_A::STALL,
+        }
+    }
+    #[doc = "Checks if the value of the field is `NOSTALL`"]
+    #[inline(always)]
+    pub fn is_nostall(&self) -> bool {
+        *self == TX_A::NOSTALL
+    }
+    #[doc = "Checks if the value of the field is `STALL`"]
+    #[inline(always)]
+    pub fn is_stall(&self) -> bool {
+        *self == TX_A::STALL
+    }
+}
+#[doc = "Field `TX` writer - Stall status for EasyDMA RAM reads"]
+pub type TX_W<'a, const O: u8> = crate::BitWriter<'a, u32, STALLSTAT_SPEC, TX_A, O>;
+impl<'a, const O: u8> TX_W<'a, O> {
+    #[doc = "No stall"]
+    #[inline(always)]
+    pub fn nostall(self) -> &'a mut W {
+        self.variant(TX_A::NOSTALL)
+    }
+    #[doc = "A stall has occurred"]
+    #[inline(always)]
+    pub fn stall(self) -> &'a mut W {
+        self.variant(TX_A::STALL)
+    }
+}
+#[doc = "Field `RX` reader - Stall status for EasyDMA RAM writes"]
+pub type RX_R = crate::BitReader<RX_A>;
+#[doc = "Stall status for EasyDMA RAM writes\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum RX_A {
+    #[doc = "0: No stall"]
+    NOSTALL = 0,
+    #[doc = "1: A stall has occurred"]
+    STALL = 1,
+}
+impl From<RX_A> for bool {
+    #[inline(always)]
+    fn from(variant: RX_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl RX_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> RX_A {
+        match self.bits {
+            false => RX_A::NOSTALL,
+            true => RX_A::STALL,
+        }
+    }
+    #[doc = "Checks if the value of the field is `NOSTALL`"]
+    #[inline(always)]
+    pub fn is_nostall(&self) -> bool {
+        *self == RX_A::NOSTALL
+    }
+    #[doc = "Checks if the value of the field is `STALL`"]
+    #[inline(always)]
+    pub fn is_stall(&self) -> bool {
+        *self == RX_A::STALL
+    }
+}
+#[doc = "Field `RX` writer - Stall status for EasyDMA RAM writes"]
+pub type RX_W<'a, const O: u8> = crate::BitWriter<'a, u32, STALLSTAT_SPEC, RX_A, O>;
+impl<'a, const O: u8> RX_W<'a, O> {
+    #[doc = "No stall"]
+    #[inline(always)]
+    pub fn nostall(self) -> &'a mut W {
+        self.variant(RX_A::NOSTALL)
+    }
+    #[doc = "A stall has occurred"]
+    #[inline(always)]
+    pub fn stall(self) -> &'a mut W {
+        self.variant(RX_A::STALL)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Stall status for EasyDMA RAM reads"]
+    #[inline(always)]
+    pub fn tx(&self) -> TX_R {
+        TX_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Stall status for EasyDMA RAM writes"]
+    #[inline(always)]
+    pub fn rx(&self) -> RX_R {
+        RX_R::new(((self.bits >> 1) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Stall status for EasyDMA RAM reads"]
+    #[inline(always)]
+    pub fn tx(&mut self) -> TX_W<0> {
+        TX_W::new(self)
+    }
+    #[doc = "Bit 1 - Stall status for EasyDMA RAM writes"]
+    #[inline(always)]
+    pub fn rx(&mut self) -> RX_W<1> {
+        RX_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Stall status for EasyDMA RAM accesses. The fields in this register is set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [stallstat](index.html) module"]
+pub struct STALLSTAT_SPEC;
+impl crate::RegisterSpec for STALLSTAT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [stallstat::R](R) reader structure"]
+impl crate::Readable for STALLSTAT_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [stallstat::W](W) writer structure"]
+impl crate::Writable for STALLSTAT_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets STALLSTAT to value 0"]
+impl crate::Resettable for STALLSTAT_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf52833-pac/src/spim0/tasks_resume.rs

@@ -0,0 +1,72 @@
+#[doc = "Register `TASKS_RESUME` writer"]
+pub struct W(crate::W<TASKS_RESUME_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<TASKS_RESUME_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<TASKS_RESUME_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<TASKS_RESUME_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Resume SPI transaction\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TASKS_RESUME_AW {
+    #[doc = "1: Trigger task"]
+    TRIGGER = 1,
+}
+impl From<TASKS_RESUME_AW> for bool {
+    #[inline(always)]
+    fn from(variant: TASKS_RESUME_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `TASKS_RESUME` writer - Resume SPI transaction"]
+pub type TASKS_RESUME_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, TASKS_RESUME_SPEC, TASKS_RESUME_AW, O>;
+impl<'a, const O: u8> TASKS_RESUME_W<'a, O> {
+    #[doc = "Trigger task"]
+    #[inline(always)]
+    pub fn trigger(self) -> &'a mut W {
+        self.variant(TASKS_RESUME_AW::TRIGGER)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Resume SPI transaction"]
+    #[inline(always)]
+    pub fn tasks_resume(&mut self) -> TASKS_RESUME_W<0> {
+        TASKS_RESUME_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Resume SPI transaction\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_resume](index.html) module"]
+pub struct TASKS_RESUME_SPEC;
+impl crate::RegisterSpec for TASKS_RESUME_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [tasks_resume::W](W) writer structure"]
+impl crate::Writable for TASKS_RESUME_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets TASKS_RESUME to value 0"]
+impl crate::Resettable for TASKS_RESUME_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf52833-pac/src/spim0/tasks_start.rs

@@ -0,0 +1,72 @@
+#[doc = "Register `TASKS_START` writer"]
+pub struct W(crate::W<TASKS_START_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<TASKS_START_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<TASKS_START_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<TASKS_START_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Start SPI transaction\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TASKS_START_AW {
+    #[doc = "1: Trigger task"]
+    TRIGGER = 1,
+}
+impl From<TASKS_START_AW> for bool {
+    #[inline(always)]
+    fn from(variant: TASKS_START_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `TASKS_START` writer - Start SPI transaction"]
+pub type TASKS_START_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, TASKS_START_SPEC, TASKS_START_AW, O>;
+impl<'a, const O: u8> TASKS_START_W<'a, O> {
+    #[doc = "Trigger task"]
+    #[inline(always)]
+    pub fn trigger(self) -> &'a mut W {
+        self.variant(TASKS_START_AW::TRIGGER)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Start SPI transaction"]
+    #[inline(always)]
+    pub fn tasks_start(&mut self) -> TASKS_START_W<0> {
+        TASKS_START_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Start SPI transaction\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_start](index.html) module"]
+pub struct TASKS_START_SPEC;
+impl crate::RegisterSpec for TASKS_START_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [tasks_start::W](W) writer structure"]
+impl crate::Writable for TASKS_START_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets TASKS_START to value 0"]
+impl crate::Resettable for TASKS_START_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf52833-pac/src/spim0/tasks_stop.rs

@@ -0,0 +1,72 @@
+#[doc = "Register `TASKS_STOP` writer"]
+pub struct W(crate::W<TASKS_STOP_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<TASKS_STOP_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<TASKS_STOP_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<TASKS_STOP_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Stop SPI transaction\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TASKS_STOP_AW {
+    #[doc = "1: Trigger task"]
+    TRIGGER = 1,
+}
+impl From<TASKS_STOP_AW> for bool {
+    #[inline(always)]
+    fn from(variant: TASKS_STOP_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `TASKS_STOP` writer - Stop SPI transaction"]
+pub type TASKS_STOP_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, TASKS_STOP_SPEC, TASKS_STOP_AW, O>;
+impl<'a, const O: u8> TASKS_STOP_W<'a, O> {
+    #[doc = "Trigger task"]
+    #[inline(always)]
+    pub fn trigger(self) -> &'a mut W {
+        self.variant(TASKS_STOP_AW::TRIGGER)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Stop SPI transaction"]
+    #[inline(always)]
+    pub fn tasks_stop(&mut self) -> TASKS_STOP_W<0> {
+        TASKS_STOP_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Stop SPI transaction\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_stop](index.html) module"]
+pub struct TASKS_STOP_SPEC;
+impl crate::RegisterSpec for TASKS_STOP_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [tasks_stop::W](W) writer structure"]
+impl crate::Writable for TASKS_STOP_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets TASKS_STOP to value 0"]
+impl crate::Resettable for TASKS_STOP_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf52833-pac/src/spim0/tasks_suspend.rs

@@ -0,0 +1,72 @@
+#[doc = "Register `TASKS_SUSPEND` writer"]
+pub struct W(crate::W<TASKS_SUSPEND_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<TASKS_SUSPEND_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<TASKS_SUSPEND_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<TASKS_SUSPEND_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Suspend SPI transaction\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TASKS_SUSPEND_AW {
+    #[doc = "1: Trigger task"]
+    TRIGGER = 1,
+}
+impl From<TASKS_SUSPEND_AW> for bool {
+    #[inline(always)]
+    fn from(variant: TASKS_SUSPEND_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `TASKS_SUSPEND` writer - Suspend SPI transaction"]
+pub type TASKS_SUSPEND_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, TASKS_SUSPEND_SPEC, TASKS_SUSPEND_AW, O>;
+impl<'a, const O: u8> TASKS_SUSPEND_W<'a, O> {
+    #[doc = "Trigger task"]
+    #[inline(always)]
+    pub fn trigger(self) -> &'a mut W {
+        self.variant(TASKS_SUSPEND_AW::TRIGGER)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Suspend SPI transaction"]
+    #[inline(always)]
+    pub fn tasks_suspend(&mut self) -> TASKS_SUSPEND_W<0> {
+        TASKS_SUSPEND_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Suspend SPI transaction\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_suspend](index.html) module"]
+pub struct TASKS_SUSPEND_SPEC;
+impl crate::RegisterSpec for TASKS_SUSPEND_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [tasks_suspend::W](W) writer structure"]
+impl crate::Writable for TASKS_SUSPEND_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets TASKS_SUSPEND to value 0"]
+impl crate::Resettable for TASKS_SUSPEND_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf52833-pac/src/spim0/txd.rs

@@ -0,0 +1,28 @@
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct TXD {
+    #[doc = "0x00 - Data pointer"]
+    pub ptr: PTR,
+    #[doc = "0x04 - Number of bytes in transmit buffer"]
+    pub maxcnt: MAXCNT,
+    #[doc = "0x08 - Number of bytes transferred in the last transaction"]
+    pub amount: AMOUNT,
+    #[doc = "0x0c - EasyDMA list type"]
+    pub list: LIST,
+}
+#[doc = "PTR (rw) register accessor: an alias for `Reg<PTR_SPEC>`"]
+pub type PTR = crate::Reg<ptr::PTR_SPEC>;
+#[doc = "Data pointer"]
+pub mod ptr;
+#[doc = "MAXCNT (rw) register accessor: an alias for `Reg<MAXCNT_SPEC>`"]
+pub type MAXCNT = crate::Reg<maxcnt::MAXCNT_SPEC>;
+#[doc = "Number of bytes in transmit buffer"]
+pub mod maxcnt;
+#[doc = "AMOUNT (r) register accessor: an alias for `Reg<AMOUNT_SPEC>`"]
+pub type AMOUNT = crate::Reg<amount::AMOUNT_SPEC>;
+#[doc = "Number of bytes transferred in the last transaction"]
+pub mod amount;
+#[doc = "LIST (rw) register accessor: an alias for `Reg<LIST_SPEC>`"]
+pub type LIST = crate::Reg<list::LIST_SPEC>;
+#[doc = "EasyDMA list type"]
+pub mod list;

vendor/nrf52833-pac/src/spim0/txd/amount.rs

@@ -0,0 +1,40 @@
+#[doc = "Register `AMOUNT` reader"]
+pub struct R(crate::R<AMOUNT_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<AMOUNT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<AMOUNT_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<AMOUNT_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `AMOUNT` reader - Number of bytes transferred in the last transaction"]
+pub type AMOUNT_R = crate::FieldReader<u16, u16>;
+impl R {
+    #[doc = "Bits 0:15 - Number of bytes transferred in the last transaction"]
+    #[inline(always)]
+    pub fn amount(&self) -> AMOUNT_R {
+        AMOUNT_R::new((self.bits & 0xffff) as u16)
+    }
+}
+#[doc = "Number of bytes transferred in the last transaction\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [amount](index.html) module"]
+pub struct AMOUNT_SPEC;
+impl crate::RegisterSpec for AMOUNT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [amount::R](R) reader structure"]
+impl crate::Readable for AMOUNT_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets AMOUNT to value 0"]
+impl crate::Resettable for AMOUNT_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf52833-pac/src/spim0/txd/list.rs

@@ -0,0 +1,128 @@
+#[doc = "Register `LIST` reader"]
+pub struct R(crate::R<LIST_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<LIST_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<LIST_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<LIST_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `LIST` writer"]
+pub struct W(crate::W<LIST_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<LIST_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<LIST_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<LIST_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `LIST` reader - List type"]
+pub type LIST_R = crate::FieldReader<u8, LIST_A>;
+#[doc = "List type\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum LIST_A {
+    #[doc = "0: Disable EasyDMA list"]
+    DISABLED = 0,
+    #[doc = "1: Use array list"]
+    ARRAY_LIST = 1,
+}
+impl From<LIST_A> for u8 {
+    #[inline(always)]
+    fn from(variant: LIST_A) -> Self {
+        variant as _
+    }
+}
+impl LIST_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<LIST_A> {
+        match self.bits {
+            0 => Some(LIST_A::DISABLED),
+            1 => Some(LIST_A::ARRAY_LIST),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == LIST_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ARRAY_LIST`"]
+    #[inline(always)]
+    pub fn is_array_list(&self) -> bool {
+        *self == LIST_A::ARRAY_LIST
+    }
+}
+#[doc = "Field `LIST` writer - List type"]
+pub type LIST_W<'a, const O: u8> = crate::FieldWriter<'a, u32, LIST_SPEC, u8, LIST_A, 2, O>;
+impl<'a, const O: u8> LIST_W<'a, O> {
+    #[doc = "Disable EasyDMA list"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(LIST_A::DISABLED)
+    }
+    #[doc = "Use array list"]
+    #[inline(always)]
+    pub fn array_list(self) -> &'a mut W {
+        self.variant(LIST_A::ARRAY_LIST)
+    }
+}
+impl R {
+    #[doc = "Bits 0:1 - List type"]
+    #[inline(always)]
+    pub fn list(&self) -> LIST_R {
+        LIST_R::new((self.bits & 3) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:1 - List type"]
+    #[inline(always)]
+    pub fn list(&mut self) -> LIST_W<0> {
+        LIST_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "EasyDMA list type\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [list](index.html) module"]
+pub struct LIST_SPEC;
+impl crate::RegisterSpec for LIST_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [list::R](R) reader structure"]
+impl crate::Readable for LIST_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [list::W](W) writer structure"]
+impl crate::Writable for LIST_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets LIST to value 0"]
+impl crate::Resettable for LIST_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf52833-pac/src/spim0/txd/maxcnt.rs

@@ -0,0 +1,80 @@
+#[doc = "Register `MAXCNT` reader"]
+pub struct R(crate::R<MAXCNT_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<MAXCNT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<MAXCNT_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<MAXCNT_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `MAXCNT` writer"]
+pub struct W(crate::W<MAXCNT_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<MAXCNT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<MAXCNT_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<MAXCNT_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `MAXCNT` reader - Maximum number of bytes in transmit buffer"]
+pub type MAXCNT_R = crate::FieldReader<u16, u16>;
+#[doc = "Field `MAXCNT` writer - Maximum number of bytes in transmit buffer"]
+pub type MAXCNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MAXCNT_SPEC, u16, u16, 16, O>;
+impl R {
+    #[doc = "Bits 0:15 - Maximum number of bytes in transmit buffer"]
+    #[inline(always)]
+    pub fn maxcnt(&self) -> MAXCNT_R {
+        MAXCNT_R::new((self.bits & 0xffff) as u16)
+    }
+}
+impl W {
+    #[doc = "Bits 0:15 - Maximum number of bytes in transmit buffer"]
+    #[inline(always)]
+    pub fn maxcnt(&mut self) -> MAXCNT_W<0> {
+        MAXCNT_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Number of bytes in transmit buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [maxcnt](index.html) module"]
+pub struct MAXCNT_SPEC;
+impl crate::RegisterSpec for MAXCNT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [maxcnt::R](R) reader structure"]
+impl crate::Readable for MAXCNT_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [maxcnt::W](W) writer structure"]
+impl crate::Writable for MAXCNT_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets MAXCNT to value 0"]
+impl crate::Resettable for MAXCNT_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf52833-pac/src/spim0/txd/ptr.rs

@@ -0,0 +1,80 @@
+#[doc = "Register `PTR` reader"]
+pub struct R(crate::R<PTR_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<PTR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<PTR_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<PTR_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `PTR` writer"]
+pub struct W(crate::W<PTR_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<PTR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<PTR_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<PTR_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `PTR` reader - Data pointer"]
+pub type PTR_R = crate::FieldReader<u32, u32>;
+#[doc = "Field `PTR` writer - Data pointer"]
+pub type PTR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PTR_SPEC, u32, u32, 32, O>;
+impl R {
+    #[doc = "Bits 0:31 - Data pointer"]
+    #[inline(always)]
+    pub fn ptr(&self) -> PTR_R {
+        PTR_R::new(self.bits)
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Data pointer"]
+    #[inline(always)]
+    pub fn ptr(&mut self) -> PTR_W<0> {
+        PTR_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Data pointer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ptr](index.html) module"]
+pub struct PTR_SPEC;
+impl crate::RegisterSpec for PTR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [ptr::R](R) reader structure"]
+impl crate::Readable for PTR_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [ptr::W](W) writer structure"]
+impl crate::Writable for PTR_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets PTR to value 0"]
+impl crate::Resettable for PTR_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}