feat: add display UI with splash screen, dashboard, and RSSI sparkline

Implement full SSD1306 OLED display support:
- Splash screen on boot (1.5s) with project name, version, board
- Dashboard showing radio state, config, counters, RSSI/SNR
- RSSI history sparkline (64-sample ring buffer, 2px-wide bars)
- DisplayOn/DisplayOff host commands routed via dedicated channel
- Pure render functions against generic DrawTarget (no hardware coupling)
- Display on/off control bypasses radio task entirely

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>

vendor/nrf52840-pac/src/cc_host_rgf/host_cryptokey_sel.rs

@@ -0,0 +1,142 @@
+#[doc = "Register `HOST_CRYPTOKEY_SEL` reader"]
+pub struct R(crate::R<HOST_CRYPTOKEY_SEL_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<HOST_CRYPTOKEY_SEL_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<HOST_CRYPTOKEY_SEL_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<HOST_CRYPTOKEY_SEL_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `HOST_CRYPTOKEY_SEL` writer"]
+pub struct W(crate::W<HOST_CRYPTOKEY_SEL_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<HOST_CRYPTOKEY_SEL_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<HOST_CRYPTOKEY_SEL_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<HOST_CRYPTOKEY_SEL_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `HOST_CRYPTOKEY_SEL` reader - Select the source of the HW key that is used by the AES engine"]
+pub type HOST_CRYPTOKEY_SEL_R = crate::FieldReader<u8, HOST_CRYPTOKEY_SEL_A>;
+#[doc = "Select the source of the HW key that is used by the AES engine\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum HOST_CRYPTOKEY_SEL_A {
+    #[doc = "0: Use device root key K_DR from CRYPTOCELL AO power domain"]
+    K_DR = 0,
+    #[doc = "1: Use hard-coded RTL key K_PRTL"]
+    K_PRTL = 1,
+    #[doc = "2: Use provided session key"]
+    SESSION = 2,
+}
+impl From<HOST_CRYPTOKEY_SEL_A> for u8 {
+    #[inline(always)]
+    fn from(variant: HOST_CRYPTOKEY_SEL_A) -> Self {
+        variant as _
+    }
+}
+impl HOST_CRYPTOKEY_SEL_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<HOST_CRYPTOKEY_SEL_A> {
+        match self.bits {
+            0 => Some(HOST_CRYPTOKEY_SEL_A::K_DR),
+            1 => Some(HOST_CRYPTOKEY_SEL_A::K_PRTL),
+            2 => Some(HOST_CRYPTOKEY_SEL_A::SESSION),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `K_DR`"]
+    #[inline(always)]
+    pub fn is_k_dr(&self) -> bool {
+        *self == HOST_CRYPTOKEY_SEL_A::K_DR
+    }
+    #[doc = "Checks if the value of the field is `K_PRTL`"]
+    #[inline(always)]
+    pub fn is_k_prtl(&self) -> bool {
+        *self == HOST_CRYPTOKEY_SEL_A::K_PRTL
+    }
+    #[doc = "Checks if the value of the field is `SESSION`"]
+    #[inline(always)]
+    pub fn is_session(&self) -> bool {
+        *self == HOST_CRYPTOKEY_SEL_A::SESSION
+    }
+}
+#[doc = "Field `HOST_CRYPTOKEY_SEL` writer - Select the source of the HW key that is used by the AES engine"]
+pub type HOST_CRYPTOKEY_SEL_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u32, HOST_CRYPTOKEY_SEL_SPEC, u8, HOST_CRYPTOKEY_SEL_A, 2, O>;
+impl<'a, const O: u8> HOST_CRYPTOKEY_SEL_W<'a, O> {
+    #[doc = "Use device root key K_DR from CRYPTOCELL AO power domain"]
+    #[inline(always)]
+    pub fn k_dr(self) -> &'a mut W {
+        self.variant(HOST_CRYPTOKEY_SEL_A::K_DR)
+    }
+    #[doc = "Use hard-coded RTL key K_PRTL"]
+    #[inline(always)]
+    pub fn k_prtl(self) -> &'a mut W {
+        self.variant(HOST_CRYPTOKEY_SEL_A::K_PRTL)
+    }
+    #[doc = "Use provided session key"]
+    #[inline(always)]
+    pub fn session(self) -> &'a mut W {
+        self.variant(HOST_CRYPTOKEY_SEL_A::SESSION)
+    }
+}
+impl R {
+    #[doc = "Bits 0:1 - Select the source of the HW key that is used by the AES engine"]
+    #[inline(always)]
+    pub fn host_cryptokey_sel(&self) -> HOST_CRYPTOKEY_SEL_R {
+        HOST_CRYPTOKEY_SEL_R::new((self.bits & 3) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:1 - Select the source of the HW key that is used by the AES engine"]
+    #[inline(always)]
+    pub fn host_cryptokey_sel(&mut self) -> HOST_CRYPTOKEY_SEL_W<0> {
+        HOST_CRYPTOKEY_SEL_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "AES hardware key select\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [host_cryptokey_sel](index.html) module"]
+pub struct HOST_CRYPTOKEY_SEL_SPEC;
+impl crate::RegisterSpec for HOST_CRYPTOKEY_SEL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [host_cryptokey_sel::R](R) reader structure"]
+impl crate::Readable for HOST_CRYPTOKEY_SEL_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [host_cryptokey_sel::W](W) writer structure"]
+impl crate::Writable for HOST_CRYPTOKEY_SEL_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets HOST_CRYPTOKEY_SEL to value 0"]
+impl crate::Resettable for HOST_CRYPTOKEY_SEL_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf52840-pac/src/cc_host_rgf/host_iot_kdr0.rs

@@ -0,0 +1,81 @@
+#[doc = "Register `HOST_IOT_KDR0` reader"]
+pub struct R(crate::R<HOST_IOT_KDR0_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<HOST_IOT_KDR0_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<HOST_IOT_KDR0_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<HOST_IOT_KDR0_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `HOST_IOT_KDR0` writer"]
+pub struct W(crate::W<HOST_IOT_KDR0_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<HOST_IOT_KDR0_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<HOST_IOT_KDR0_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<HOST_IOT_KDR0_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `HOST_IOT_KDR0` reader - Write: K_DR bits 31:0 Read: 0x00000000 when 128-bit K_DR key value is not yet retained in the CRYPTOCELL AO power domain Read: 0x00000001 when 128-bit K_DR key value is successfully retained in the CRYPTOCELL AO power domain"]
+pub type HOST_IOT_KDR0_R = crate::FieldReader<u32, u32>;
+#[doc = "Field `HOST_IOT_KDR0` writer - Write: K_DR bits 31:0 Read: 0x00000000 when 128-bit K_DR key value is not yet retained in the CRYPTOCELL AO power domain Read: 0x00000001 when 128-bit K_DR key value is successfully retained in the CRYPTOCELL AO power domain"]
+pub type HOST_IOT_KDR0_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u32, HOST_IOT_KDR0_SPEC, u32, u32, 32, O>;
+impl R {
+    #[doc = "Bits 0:31 - Write: K_DR bits 31:0 Read: 0x00000000 when 128-bit K_DR key value is not yet retained in the CRYPTOCELL AO power domain Read: 0x00000001 when 128-bit K_DR key value is successfully retained in the CRYPTOCELL AO power domain"]
+    #[inline(always)]
+    pub fn host_iot_kdr0(&self) -> HOST_IOT_KDR0_R {
+        HOST_IOT_KDR0_R::new(self.bits)
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Write: K_DR bits 31:0 Read: 0x00000000 when 128-bit K_DR key value is not yet retained in the CRYPTOCELL AO power domain Read: 0x00000001 when 128-bit K_DR key value is successfully retained in the CRYPTOCELL AO power domain"]
+    #[inline(always)]
+    pub fn host_iot_kdr0(&mut self) -> HOST_IOT_KDR0_W<0> {
+        HOST_IOT_KDR0_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "This register holds bits 31:0 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. Reading from this address returns the K_DR valid status indicating if K_DR is successfully retained.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [host_iot_kdr0](index.html) module"]
+pub struct HOST_IOT_KDR0_SPEC;
+impl crate::RegisterSpec for HOST_IOT_KDR0_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [host_iot_kdr0::R](R) reader structure"]
+impl crate::Readable for HOST_IOT_KDR0_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [host_iot_kdr0::W](W) writer structure"]
+impl crate::Writable for HOST_IOT_KDR0_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets HOST_IOT_KDR0 to value 0"]
+impl crate::Resettable for HOST_IOT_KDR0_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf52840-pac/src/cc_host_rgf/host_iot_kdr1.rs

@@ -0,0 +1,53 @@
+#[doc = "Register `HOST_IOT_KDR1` writer"]
+pub struct W(crate::W<HOST_IOT_KDR1_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<HOST_IOT_KDR1_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<HOST_IOT_KDR1_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<HOST_IOT_KDR1_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `HOST_IOT_KDR1` writer - K_DR bits 63:32"]
+pub type HOST_IOT_KDR1_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u32, HOST_IOT_KDR1_SPEC, u32, u32, 32, O>;
+impl W {
+    #[doc = "Bits 0:31 - K_DR bits 63:32"]
+    #[inline(always)]
+    pub fn host_iot_kdr1(&mut self) -> HOST_IOT_KDR1_W<0> {
+        HOST_IOT_KDR1_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "This register holds bits 63:32 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain.\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [host_iot_kdr1](index.html) module"]
+pub struct HOST_IOT_KDR1_SPEC;
+impl crate::RegisterSpec for HOST_IOT_KDR1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [host_iot_kdr1::W](W) writer structure"]
+impl crate::Writable for HOST_IOT_KDR1_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets HOST_IOT_KDR1 to value 0"]
+impl crate::Resettable for HOST_IOT_KDR1_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf52840-pac/src/cc_host_rgf/host_iot_kdr2.rs

@@ -0,0 +1,53 @@
+#[doc = "Register `HOST_IOT_KDR2` writer"]
+pub struct W(crate::W<HOST_IOT_KDR2_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<HOST_IOT_KDR2_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<HOST_IOT_KDR2_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<HOST_IOT_KDR2_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `HOST_IOT_KDR2` writer - K_DR bits 95:64"]
+pub type HOST_IOT_KDR2_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u32, HOST_IOT_KDR2_SPEC, u32, u32, 32, O>;
+impl W {
+    #[doc = "Bits 0:31 - K_DR bits 95:64"]
+    #[inline(always)]
+    pub fn host_iot_kdr2(&mut self) -> HOST_IOT_KDR2_W<0> {
+        HOST_IOT_KDR2_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "This register holds bits 95:64 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain.\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [host_iot_kdr2](index.html) module"]
+pub struct HOST_IOT_KDR2_SPEC;
+impl crate::RegisterSpec for HOST_IOT_KDR2_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [host_iot_kdr2::W](W) writer structure"]
+impl crate::Writable for HOST_IOT_KDR2_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets HOST_IOT_KDR2 to value 0"]
+impl crate::Resettable for HOST_IOT_KDR2_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf52840-pac/src/cc_host_rgf/host_iot_kdr3.rs

@@ -0,0 +1,53 @@
+#[doc = "Register `HOST_IOT_KDR3` writer"]
+pub struct W(crate::W<HOST_IOT_KDR3_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<HOST_IOT_KDR3_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<HOST_IOT_KDR3_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<HOST_IOT_KDR3_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `HOST_IOT_KDR3` writer - K_DR bits 127:96"]
+pub type HOST_IOT_KDR3_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u32, HOST_IOT_KDR3_SPEC, u32, u32, 32, O>;
+impl W {
+    #[doc = "Bits 0:31 - K_DR bits 127:96"]
+    #[inline(always)]
+    pub fn host_iot_kdr3(&mut self) -> HOST_IOT_KDR3_W<0> {
+        HOST_IOT_KDR3_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "This register holds bits 127:96 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain.\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [host_iot_kdr3](index.html) module"]
+pub struct HOST_IOT_KDR3_SPEC;
+impl crate::RegisterSpec for HOST_IOT_KDR3_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [host_iot_kdr3::W](W) writer structure"]
+impl crate::Writable for HOST_IOT_KDR3_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets HOST_IOT_KDR3 to value 0"]
+impl crate::Resettable for HOST_IOT_KDR3_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf52840-pac/src/cc_host_rgf/host_iot_kprtl_lock.rs

@@ -0,0 +1,127 @@
+#[doc = "Register `HOST_IOT_KPRTL_LOCK` reader"]
+pub struct R(crate::R<HOST_IOT_KPRTL_LOCK_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<HOST_IOT_KPRTL_LOCK_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<HOST_IOT_KPRTL_LOCK_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<HOST_IOT_KPRTL_LOCK_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `HOST_IOT_KPRTL_LOCK` writer"]
+pub struct W(crate::W<HOST_IOT_KPRTL_LOCK_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<HOST_IOT_KPRTL_LOCK_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<HOST_IOT_KPRTL_LOCK_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<HOST_IOT_KPRTL_LOCK_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `HOST_IOT_KPRTL_LOCK` reader - This register is the K_PRTL lock register. When this register is set, K_PRTL can not be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain."]
+pub type HOST_IOT_KPRTL_LOCK_R = crate::BitReader<HOST_IOT_KPRTL_LOCK_A>;
+#[doc = "This register is the K_PRTL lock register. When this register is set, K_PRTL can not be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum HOST_IOT_KPRTL_LOCK_A {
+    #[doc = "0: K_PRTL can be selected for use from register HOST_CRYPTOKEY_SEL"]
+    DISABLED = 0,
+    #[doc = "1: K_PRTL has been locked until next power-on reset (POR). If K_PRTL is selected anyway, a zeroed key will be used instead."]
+    ENABLED = 1,
+}
+impl From<HOST_IOT_KPRTL_LOCK_A> for bool {
+    #[inline(always)]
+    fn from(variant: HOST_IOT_KPRTL_LOCK_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl HOST_IOT_KPRTL_LOCK_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> HOST_IOT_KPRTL_LOCK_A {
+        match self.bits {
+            false => HOST_IOT_KPRTL_LOCK_A::DISABLED,
+            true => HOST_IOT_KPRTL_LOCK_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == HOST_IOT_KPRTL_LOCK_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == HOST_IOT_KPRTL_LOCK_A::ENABLED
+    }
+}
+#[doc = "Field `HOST_IOT_KPRTL_LOCK` writer - This register is the K_PRTL lock register. When this register is set, K_PRTL can not be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain."]
+pub type HOST_IOT_KPRTL_LOCK_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, HOST_IOT_KPRTL_LOCK_SPEC, HOST_IOT_KPRTL_LOCK_A, O>;
+impl<'a, const O: u8> HOST_IOT_KPRTL_LOCK_W<'a, O> {
+    #[doc = "K_PRTL can be selected for use from register HOST_CRYPTOKEY_SEL"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(HOST_IOT_KPRTL_LOCK_A::DISABLED)
+    }
+    #[doc = "K_PRTL has been locked until next power-on reset (POR). If K_PRTL is selected anyway, a zeroed key will be used instead."]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(HOST_IOT_KPRTL_LOCK_A::ENABLED)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - This register is the K_PRTL lock register. When this register is set, K_PRTL can not be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain."]
+    #[inline(always)]
+    pub fn host_iot_kprtl_lock(&self) -> HOST_IOT_KPRTL_LOCK_R {
+        HOST_IOT_KPRTL_LOCK_R::new((self.bits & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - This register is the K_PRTL lock register. When this register is set, K_PRTL can not be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain."]
+    #[inline(always)]
+    pub fn host_iot_kprtl_lock(&mut self) -> HOST_IOT_KPRTL_LOCK_W<0> {
+        HOST_IOT_KPRTL_LOCK_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "This write-once register is the K_PRTL lock register. When this register is set, K_PRTL can not be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [host_iot_kprtl_lock](index.html) module"]
+pub struct HOST_IOT_KPRTL_LOCK_SPEC;
+impl crate::RegisterSpec for HOST_IOT_KPRTL_LOCK_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [host_iot_kprtl_lock::R](R) reader structure"]
+impl crate::Readable for HOST_IOT_KPRTL_LOCK_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [host_iot_kprtl_lock::W](W) writer structure"]
+impl crate::Writable for HOST_IOT_KPRTL_LOCK_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets HOST_IOT_KPRTL_LOCK to value 0"]
+impl crate::Resettable for HOST_IOT_KPRTL_LOCK_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf52840-pac/src/cc_host_rgf/host_iot_lcs.rs

@@ -0,0 +1,189 @@
+#[doc = "Register `HOST_IOT_LCS` reader"]
+pub struct R(crate::R<HOST_IOT_LCS_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<HOST_IOT_LCS_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<HOST_IOT_LCS_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<HOST_IOT_LCS_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `HOST_IOT_LCS` writer"]
+pub struct W(crate::W<HOST_IOT_LCS_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<HOST_IOT_LCS_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<HOST_IOT_LCS_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<HOST_IOT_LCS_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `LCS` reader - Lifecycle state value. This field is write-once per reset."]
+pub type LCS_R = crate::FieldReader<u8, LCS_A>;
+#[doc = "Lifecycle state value. This field is write-once per reset.\n\nValue on reset: 2"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum LCS_A {
+    #[doc = "0: CC310 operates in debug mode"]
+    DEBUG = 0,
+    #[doc = "2: CC310 operates in secure mode"]
+    SECURE = 2,
+}
+impl From<LCS_A> for u8 {
+    #[inline(always)]
+    fn from(variant: LCS_A) -> Self {
+        variant as _
+    }
+}
+impl LCS_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<LCS_A> {
+        match self.bits {
+            0 => Some(LCS_A::DEBUG),
+            2 => Some(LCS_A::SECURE),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DEBUG`"]
+    #[inline(always)]
+    pub fn is_debug(&self) -> bool {
+        *self == LCS_A::DEBUG
+    }
+    #[doc = "Checks if the value of the field is `SECURE`"]
+    #[inline(always)]
+    pub fn is_secure(&self) -> bool {
+        *self == LCS_A::SECURE
+    }
+}
+#[doc = "Field `LCS` writer - Lifecycle state value. This field is write-once per reset."]
+pub type LCS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HOST_IOT_LCS_SPEC, u8, LCS_A, 3, O>;
+impl<'a, const O: u8> LCS_W<'a, O> {
+    #[doc = "CC310 operates in debug mode"]
+    #[inline(always)]
+    pub fn debug(self) -> &'a mut W {
+        self.variant(LCS_A::DEBUG)
+    }
+    #[doc = "CC310 operates in secure mode"]
+    #[inline(always)]
+    pub fn secure(self) -> &'a mut W {
+        self.variant(LCS_A::SECURE)
+    }
+}
+#[doc = "Field `LCS_IS_VALID` reader - This field is read-only and indicates if CRYPTOCELL LCS has been successfully configured since last reset"]
+pub type LCS_IS_VALID_R = crate::BitReader<LCS_IS_VALID_A>;
+#[doc = "This field is read-only and indicates if CRYPTOCELL LCS has been successfully configured since last reset\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum LCS_IS_VALID_A {
+    #[doc = "0: A valid LCS is not yet retained in the CRYPTOCELL AO power domain"]
+    INVALID = 0,
+    #[doc = "1: A valid LCS is successfully retained in the CRYPTOCELL AO power domain"]
+    VALID = 1,
+}
+impl From<LCS_IS_VALID_A> for bool {
+    #[inline(always)]
+    fn from(variant: LCS_IS_VALID_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl LCS_IS_VALID_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> LCS_IS_VALID_A {
+        match self.bits {
+            false => LCS_IS_VALID_A::INVALID,
+            true => LCS_IS_VALID_A::VALID,
+        }
+    }
+    #[doc = "Checks if the value of the field is `INVALID`"]
+    #[inline(always)]
+    pub fn is_invalid(&self) -> bool {
+        *self == LCS_IS_VALID_A::INVALID
+    }
+    #[doc = "Checks if the value of the field is `VALID`"]
+    #[inline(always)]
+    pub fn is_valid(&self) -> bool {
+        *self == LCS_IS_VALID_A::VALID
+    }
+}
+#[doc = "Field `LCS_IS_VALID` writer - This field is read-only and indicates if CRYPTOCELL LCS has been successfully configured since last reset"]
+pub type LCS_IS_VALID_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, HOST_IOT_LCS_SPEC, LCS_IS_VALID_A, O>;
+impl<'a, const O: u8> LCS_IS_VALID_W<'a, O> {
+    #[doc = "A valid LCS is not yet retained in the CRYPTOCELL AO power domain"]
+    #[inline(always)]
+    pub fn invalid(self) -> &'a mut W {
+        self.variant(LCS_IS_VALID_A::INVALID)
+    }
+    #[doc = "A valid LCS is successfully retained in the CRYPTOCELL AO power domain"]
+    #[inline(always)]
+    pub fn valid(self) -> &'a mut W {
+        self.variant(LCS_IS_VALID_A::VALID)
+    }
+}
+impl R {
+    #[doc = "Bits 0:2 - Lifecycle state value. This field is write-once per reset."]
+    #[inline(always)]
+    pub fn lcs(&self) -> LCS_R {
+        LCS_R::new((self.bits & 7) as u8)
+    }
+    #[doc = "Bit 8 - This field is read-only and indicates if CRYPTOCELL LCS has been successfully configured since last reset"]
+    #[inline(always)]
+    pub fn lcs_is_valid(&self) -> LCS_IS_VALID_R {
+        LCS_IS_VALID_R::new(((self.bits >> 8) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:2 - Lifecycle state value. This field is write-once per reset."]
+    #[inline(always)]
+    pub fn lcs(&mut self) -> LCS_W<0> {
+        LCS_W::new(self)
+    }
+    #[doc = "Bit 8 - This field is read-only and indicates if CRYPTOCELL LCS has been successfully configured since last reset"]
+    #[inline(always)]
+    pub fn lcs_is_valid(&mut self) -> LCS_IS_VALID_W<8> {
+        LCS_IS_VALID_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Controls lifecycle state (LCS) for CRYPTOCELL subsystem\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [host_iot_lcs](index.html) module"]
+pub struct HOST_IOT_LCS_SPEC;
+impl crate::RegisterSpec for HOST_IOT_LCS_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [host_iot_lcs::R](R) reader structure"]
+impl crate::Readable for HOST_IOT_LCS_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [host_iot_lcs::W](W) writer structure"]
+impl crate::Writable for HOST_IOT_LCS_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets HOST_IOT_LCS to value 0x02"]
+impl crate::Resettable for HOST_IOT_LCS_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0x02
+    }
+}