feat: add display UI with splash screen, dashboard, and RSSI sparkline

Implement full SSD1306 OLED display support:
- Splash screen on boot (1.5s) with project name, version, board
- Dashboard showing radio state, config, counters, RSSI/SNR
- RSSI history sparkline (64-sample ring buffer, 2px-wide bars)
- DisplayOn/DisplayOff host commands routed via dedicated channel
- Pure render functions against generic DrawTarget (no hardware coupling)
- Display on/off control bypasses radio task entirely

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>

vendor/nrf5340-app-pac/src/fpu_ns/events_denormalinput.rs

@@ -0,0 +1,127 @@
+#[doc = "Register `EVENTS_DENORMALINPUT` reader"]
+pub struct R(crate::R<EVENTS_DENORMALINPUT_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<EVENTS_DENORMALINPUT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<EVENTS_DENORMALINPUT_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<EVENTS_DENORMALINPUT_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `EVENTS_DENORMALINPUT` writer"]
+pub struct W(crate::W<EVENTS_DENORMALINPUT_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<EVENTS_DENORMALINPUT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<EVENTS_DENORMALINPUT_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<EVENTS_DENORMALINPUT_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `EVENTS_DENORMALINPUT` reader - An FPUIDC exception triggered by a denormal floating-point input has occurred in the FPU"]
+pub type EVENTS_DENORMALINPUT_R = crate::BitReader<EVENTS_DENORMALINPUT_A>;
+#[doc = "An FPUIDC exception triggered by a denormal floating-point input has occurred in the FPU\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum EVENTS_DENORMALINPUT_A {
+    #[doc = "0: Event not generated"]
+    NOT_GENERATED = 0,
+    #[doc = "1: Event generated"]
+    GENERATED = 1,
+}
+impl From<EVENTS_DENORMALINPUT_A> for bool {
+    #[inline(always)]
+    fn from(variant: EVENTS_DENORMALINPUT_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl EVENTS_DENORMALINPUT_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> EVENTS_DENORMALINPUT_A {
+        match self.bits {
+            false => EVENTS_DENORMALINPUT_A::NOT_GENERATED,
+            true => EVENTS_DENORMALINPUT_A::GENERATED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `NOT_GENERATED`"]
+    #[inline(always)]
+    pub fn is_not_generated(&self) -> bool {
+        *self == EVENTS_DENORMALINPUT_A::NOT_GENERATED
+    }
+    #[doc = "Checks if the value of the field is `GENERATED`"]
+    #[inline(always)]
+    pub fn is_generated(&self) -> bool {
+        *self == EVENTS_DENORMALINPUT_A::GENERATED
+    }
+}
+#[doc = "Field `EVENTS_DENORMALINPUT` writer - An FPUIDC exception triggered by a denormal floating-point input has occurred in the FPU"]
+pub type EVENTS_DENORMALINPUT_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, EVENTS_DENORMALINPUT_SPEC, EVENTS_DENORMALINPUT_A, O>;
+impl<'a, const O: u8> EVENTS_DENORMALINPUT_W<'a, O> {
+    #[doc = "Event not generated"]
+    #[inline(always)]
+    pub fn not_generated(self) -> &'a mut W {
+        self.variant(EVENTS_DENORMALINPUT_A::NOT_GENERATED)
+    }
+    #[doc = "Event generated"]
+    #[inline(always)]
+    pub fn generated(self) -> &'a mut W {
+        self.variant(EVENTS_DENORMALINPUT_A::GENERATED)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - An FPUIDC exception triggered by a denormal floating-point input has occurred in the FPU"]
+    #[inline(always)]
+    pub fn events_denormalinput(&self) -> EVENTS_DENORMALINPUT_R {
+        EVENTS_DENORMALINPUT_R::new((self.bits & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - An FPUIDC exception triggered by a denormal floating-point input has occurred in the FPU"]
+    #[inline(always)]
+    pub fn events_denormalinput(&mut self) -> EVENTS_DENORMALINPUT_W<0> {
+        EVENTS_DENORMALINPUT_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "An FPUIDC exception triggered by a denormal floating-point input has occurred in the FPU\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_denormalinput](index.html) module"]
+pub struct EVENTS_DENORMALINPUT_SPEC;
+impl crate::RegisterSpec for EVENTS_DENORMALINPUT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [events_denormalinput::R](R) reader structure"]
+impl crate::Readable for EVENTS_DENORMALINPUT_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [events_denormalinput::W](W) writer structure"]
+impl crate::Writable for EVENTS_DENORMALINPUT_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets EVENTS_DENORMALINPUT to value 0"]
+impl crate::Resettable for EVENTS_DENORMALINPUT_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf5340-app-pac/src/fpu_ns/events_dividebyzero.rs

@@ -0,0 +1,127 @@
+#[doc = "Register `EVENTS_DIVIDEBYZERO` reader"]
+pub struct R(crate::R<EVENTS_DIVIDEBYZERO_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<EVENTS_DIVIDEBYZERO_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<EVENTS_DIVIDEBYZERO_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<EVENTS_DIVIDEBYZERO_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `EVENTS_DIVIDEBYZERO` writer"]
+pub struct W(crate::W<EVENTS_DIVIDEBYZERO_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<EVENTS_DIVIDEBYZERO_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<EVENTS_DIVIDEBYZERO_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<EVENTS_DIVIDEBYZERO_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `EVENTS_DIVIDEBYZERO` reader - An FPUDZC exception triggered by a floating-point divide-by-zero operation has occurred in the FPU"]
+pub type EVENTS_DIVIDEBYZERO_R = crate::BitReader<EVENTS_DIVIDEBYZERO_A>;
+#[doc = "An FPUDZC exception triggered by a floating-point divide-by-zero operation has occurred in the FPU\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum EVENTS_DIVIDEBYZERO_A {
+    #[doc = "0: Event not generated"]
+    NOT_GENERATED = 0,
+    #[doc = "1: Event generated"]
+    GENERATED = 1,
+}
+impl From<EVENTS_DIVIDEBYZERO_A> for bool {
+    #[inline(always)]
+    fn from(variant: EVENTS_DIVIDEBYZERO_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl EVENTS_DIVIDEBYZERO_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> EVENTS_DIVIDEBYZERO_A {
+        match self.bits {
+            false => EVENTS_DIVIDEBYZERO_A::NOT_GENERATED,
+            true => EVENTS_DIVIDEBYZERO_A::GENERATED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `NOT_GENERATED`"]
+    #[inline(always)]
+    pub fn is_not_generated(&self) -> bool {
+        *self == EVENTS_DIVIDEBYZERO_A::NOT_GENERATED
+    }
+    #[doc = "Checks if the value of the field is `GENERATED`"]
+    #[inline(always)]
+    pub fn is_generated(&self) -> bool {
+        *self == EVENTS_DIVIDEBYZERO_A::GENERATED
+    }
+}
+#[doc = "Field `EVENTS_DIVIDEBYZERO` writer - An FPUDZC exception triggered by a floating-point divide-by-zero operation has occurred in the FPU"]
+pub type EVENTS_DIVIDEBYZERO_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, EVENTS_DIVIDEBYZERO_SPEC, EVENTS_DIVIDEBYZERO_A, O>;
+impl<'a, const O: u8> EVENTS_DIVIDEBYZERO_W<'a, O> {
+    #[doc = "Event not generated"]
+    #[inline(always)]
+    pub fn not_generated(self) -> &'a mut W {
+        self.variant(EVENTS_DIVIDEBYZERO_A::NOT_GENERATED)
+    }
+    #[doc = "Event generated"]
+    #[inline(always)]
+    pub fn generated(self) -> &'a mut W {
+        self.variant(EVENTS_DIVIDEBYZERO_A::GENERATED)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - An FPUDZC exception triggered by a floating-point divide-by-zero operation has occurred in the FPU"]
+    #[inline(always)]
+    pub fn events_dividebyzero(&self) -> EVENTS_DIVIDEBYZERO_R {
+        EVENTS_DIVIDEBYZERO_R::new((self.bits & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - An FPUDZC exception triggered by a floating-point divide-by-zero operation has occurred in the FPU"]
+    #[inline(always)]
+    pub fn events_dividebyzero(&mut self) -> EVENTS_DIVIDEBYZERO_W<0> {
+        EVENTS_DIVIDEBYZERO_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "An FPUDZC exception triggered by a floating-point divide-by-zero operation has occurred in the FPU\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_dividebyzero](index.html) module"]
+pub struct EVENTS_DIVIDEBYZERO_SPEC;
+impl crate::RegisterSpec for EVENTS_DIVIDEBYZERO_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [events_dividebyzero::R](R) reader structure"]
+impl crate::Readable for EVENTS_DIVIDEBYZERO_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [events_dividebyzero::W](W) writer structure"]
+impl crate::Writable for EVENTS_DIVIDEBYZERO_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets EVENTS_DIVIDEBYZERO to value 0"]
+impl crate::Resettable for EVENTS_DIVIDEBYZERO_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf5340-app-pac/src/fpu_ns/events_inexact.rs

@@ -0,0 +1,127 @@
+#[doc = "Register `EVENTS_INEXACT` reader"]
+pub struct R(crate::R<EVENTS_INEXACT_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<EVENTS_INEXACT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<EVENTS_INEXACT_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<EVENTS_INEXACT_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `EVENTS_INEXACT` writer"]
+pub struct W(crate::W<EVENTS_INEXACT_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<EVENTS_INEXACT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<EVENTS_INEXACT_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<EVENTS_INEXACT_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `EVENTS_INEXACT` reader - An FPUIXC exception triggered by an inexact floating-point operation has occurred in the FPU"]
+pub type EVENTS_INEXACT_R = crate::BitReader<EVENTS_INEXACT_A>;
+#[doc = "An FPUIXC exception triggered by an inexact floating-point operation has occurred in the FPU\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum EVENTS_INEXACT_A {
+    #[doc = "0: Event not generated"]
+    NOT_GENERATED = 0,
+    #[doc = "1: Event generated"]
+    GENERATED = 1,
+}
+impl From<EVENTS_INEXACT_A> for bool {
+    #[inline(always)]
+    fn from(variant: EVENTS_INEXACT_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl EVENTS_INEXACT_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> EVENTS_INEXACT_A {
+        match self.bits {
+            false => EVENTS_INEXACT_A::NOT_GENERATED,
+            true => EVENTS_INEXACT_A::GENERATED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `NOT_GENERATED`"]
+    #[inline(always)]
+    pub fn is_not_generated(&self) -> bool {
+        *self == EVENTS_INEXACT_A::NOT_GENERATED
+    }
+    #[doc = "Checks if the value of the field is `GENERATED`"]
+    #[inline(always)]
+    pub fn is_generated(&self) -> bool {
+        *self == EVENTS_INEXACT_A::GENERATED
+    }
+}
+#[doc = "Field `EVENTS_INEXACT` writer - An FPUIXC exception triggered by an inexact floating-point operation has occurred in the FPU"]
+pub type EVENTS_INEXACT_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, EVENTS_INEXACT_SPEC, EVENTS_INEXACT_A, O>;
+impl<'a, const O: u8> EVENTS_INEXACT_W<'a, O> {
+    #[doc = "Event not generated"]
+    #[inline(always)]
+    pub fn not_generated(self) -> &'a mut W {
+        self.variant(EVENTS_INEXACT_A::NOT_GENERATED)
+    }
+    #[doc = "Event generated"]
+    #[inline(always)]
+    pub fn generated(self) -> &'a mut W {
+        self.variant(EVENTS_INEXACT_A::GENERATED)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - An FPUIXC exception triggered by an inexact floating-point operation has occurred in the FPU"]
+    #[inline(always)]
+    pub fn events_inexact(&self) -> EVENTS_INEXACT_R {
+        EVENTS_INEXACT_R::new((self.bits & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - An FPUIXC exception triggered by an inexact floating-point operation has occurred in the FPU"]
+    #[inline(always)]
+    pub fn events_inexact(&mut self) -> EVENTS_INEXACT_W<0> {
+        EVENTS_INEXACT_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "An FPUIXC exception triggered by an inexact floating-point operation has occurred in the FPU\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_inexact](index.html) module"]
+pub struct EVENTS_INEXACT_SPEC;
+impl crate::RegisterSpec for EVENTS_INEXACT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [events_inexact::R](R) reader structure"]
+impl crate::Readable for EVENTS_INEXACT_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [events_inexact::W](W) writer structure"]
+impl crate::Writable for EVENTS_INEXACT_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets EVENTS_INEXACT to value 0"]
+impl crate::Resettable for EVENTS_INEXACT_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf5340-app-pac/src/fpu_ns/events_invalidoperation.rs

@@ -0,0 +1,127 @@
+#[doc = "Register `EVENTS_INVALIDOPERATION` reader"]
+pub struct R(crate::R<EVENTS_INVALIDOPERATION_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<EVENTS_INVALIDOPERATION_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<EVENTS_INVALIDOPERATION_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<EVENTS_INVALIDOPERATION_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `EVENTS_INVALIDOPERATION` writer"]
+pub struct W(crate::W<EVENTS_INVALIDOPERATION_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<EVENTS_INVALIDOPERATION_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<EVENTS_INVALIDOPERATION_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<EVENTS_INVALIDOPERATION_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `EVENTS_INVALIDOPERATION` reader - An FPUIOC exception triggered by an invalid operation has occurred in the FPU"]
+pub type EVENTS_INVALIDOPERATION_R = crate::BitReader<EVENTS_INVALIDOPERATION_A>;
+#[doc = "An FPUIOC exception triggered by an invalid operation has occurred in the FPU\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum EVENTS_INVALIDOPERATION_A {
+    #[doc = "0: Event not generated"]
+    NOT_GENERATED = 0,
+    #[doc = "1: Event generated"]
+    GENERATED = 1,
+}
+impl From<EVENTS_INVALIDOPERATION_A> for bool {
+    #[inline(always)]
+    fn from(variant: EVENTS_INVALIDOPERATION_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl EVENTS_INVALIDOPERATION_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> EVENTS_INVALIDOPERATION_A {
+        match self.bits {
+            false => EVENTS_INVALIDOPERATION_A::NOT_GENERATED,
+            true => EVENTS_INVALIDOPERATION_A::GENERATED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `NOT_GENERATED`"]
+    #[inline(always)]
+    pub fn is_not_generated(&self) -> bool {
+        *self == EVENTS_INVALIDOPERATION_A::NOT_GENERATED
+    }
+    #[doc = "Checks if the value of the field is `GENERATED`"]
+    #[inline(always)]
+    pub fn is_generated(&self) -> bool {
+        *self == EVENTS_INVALIDOPERATION_A::GENERATED
+    }
+}
+#[doc = "Field `EVENTS_INVALIDOPERATION` writer - An FPUIOC exception triggered by an invalid operation has occurred in the FPU"]
+pub type EVENTS_INVALIDOPERATION_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, EVENTS_INVALIDOPERATION_SPEC, EVENTS_INVALIDOPERATION_A, O>;
+impl<'a, const O: u8> EVENTS_INVALIDOPERATION_W<'a, O> {
+    #[doc = "Event not generated"]
+    #[inline(always)]
+    pub fn not_generated(self) -> &'a mut W {
+        self.variant(EVENTS_INVALIDOPERATION_A::NOT_GENERATED)
+    }
+    #[doc = "Event generated"]
+    #[inline(always)]
+    pub fn generated(self) -> &'a mut W {
+        self.variant(EVENTS_INVALIDOPERATION_A::GENERATED)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - An FPUIOC exception triggered by an invalid operation has occurred in the FPU"]
+    #[inline(always)]
+    pub fn events_invalidoperation(&self) -> EVENTS_INVALIDOPERATION_R {
+        EVENTS_INVALIDOPERATION_R::new((self.bits & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - An FPUIOC exception triggered by an invalid operation has occurred in the FPU"]
+    #[inline(always)]
+    pub fn events_invalidoperation(&mut self) -> EVENTS_INVALIDOPERATION_W<0> {
+        EVENTS_INVALIDOPERATION_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "An FPUIOC exception triggered by an invalid operation has occurred in the FPU\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_invalidoperation](index.html) module"]
+pub struct EVENTS_INVALIDOPERATION_SPEC;
+impl crate::RegisterSpec for EVENTS_INVALIDOPERATION_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [events_invalidoperation::R](R) reader structure"]
+impl crate::Readable for EVENTS_INVALIDOPERATION_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [events_invalidoperation::W](W) writer structure"]
+impl crate::Writable for EVENTS_INVALIDOPERATION_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets EVENTS_INVALIDOPERATION to value 0"]
+impl crate::Resettable for EVENTS_INVALIDOPERATION_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf5340-app-pac/src/fpu_ns/events_overflow.rs

@@ -0,0 +1,127 @@
+#[doc = "Register `EVENTS_OVERFLOW` reader"]
+pub struct R(crate::R<EVENTS_OVERFLOW_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<EVENTS_OVERFLOW_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<EVENTS_OVERFLOW_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<EVENTS_OVERFLOW_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `EVENTS_OVERFLOW` writer"]
+pub struct W(crate::W<EVENTS_OVERFLOW_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<EVENTS_OVERFLOW_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<EVENTS_OVERFLOW_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<EVENTS_OVERFLOW_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `EVENTS_OVERFLOW` reader - An FPUOFC exception triggered by a floating-point overflow has occurred in the FPU"]
+pub type EVENTS_OVERFLOW_R = crate::BitReader<EVENTS_OVERFLOW_A>;
+#[doc = "An FPUOFC exception triggered by a floating-point overflow has occurred in the FPU\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum EVENTS_OVERFLOW_A {
+    #[doc = "0: Event not generated"]
+    NOT_GENERATED = 0,
+    #[doc = "1: Event generated"]
+    GENERATED = 1,
+}
+impl From<EVENTS_OVERFLOW_A> for bool {
+    #[inline(always)]
+    fn from(variant: EVENTS_OVERFLOW_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl EVENTS_OVERFLOW_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> EVENTS_OVERFLOW_A {
+        match self.bits {
+            false => EVENTS_OVERFLOW_A::NOT_GENERATED,
+            true => EVENTS_OVERFLOW_A::GENERATED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `NOT_GENERATED`"]
+    #[inline(always)]
+    pub fn is_not_generated(&self) -> bool {
+        *self == EVENTS_OVERFLOW_A::NOT_GENERATED
+    }
+    #[doc = "Checks if the value of the field is `GENERATED`"]
+    #[inline(always)]
+    pub fn is_generated(&self) -> bool {
+        *self == EVENTS_OVERFLOW_A::GENERATED
+    }
+}
+#[doc = "Field `EVENTS_OVERFLOW` writer - An FPUOFC exception triggered by a floating-point overflow has occurred in the FPU"]
+pub type EVENTS_OVERFLOW_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, EVENTS_OVERFLOW_SPEC, EVENTS_OVERFLOW_A, O>;
+impl<'a, const O: u8> EVENTS_OVERFLOW_W<'a, O> {
+    #[doc = "Event not generated"]
+    #[inline(always)]
+    pub fn not_generated(self) -> &'a mut W {
+        self.variant(EVENTS_OVERFLOW_A::NOT_GENERATED)
+    }
+    #[doc = "Event generated"]
+    #[inline(always)]
+    pub fn generated(self) -> &'a mut W {
+        self.variant(EVENTS_OVERFLOW_A::GENERATED)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - An FPUOFC exception triggered by a floating-point overflow has occurred in the FPU"]
+    #[inline(always)]
+    pub fn events_overflow(&self) -> EVENTS_OVERFLOW_R {
+        EVENTS_OVERFLOW_R::new((self.bits & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - An FPUOFC exception triggered by a floating-point overflow has occurred in the FPU"]
+    #[inline(always)]
+    pub fn events_overflow(&mut self) -> EVENTS_OVERFLOW_W<0> {
+        EVENTS_OVERFLOW_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "An FPUOFC exception triggered by a floating-point overflow has occurred in the FPU\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_overflow](index.html) module"]
+pub struct EVENTS_OVERFLOW_SPEC;
+impl crate::RegisterSpec for EVENTS_OVERFLOW_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [events_overflow::R](R) reader structure"]
+impl crate::Readable for EVENTS_OVERFLOW_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [events_overflow::W](W) writer structure"]
+impl crate::Writable for EVENTS_OVERFLOW_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets EVENTS_OVERFLOW to value 0"]
+impl crate::Resettable for EVENTS_OVERFLOW_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf5340-app-pac/src/fpu_ns/events_underflow.rs

@@ -0,0 +1,127 @@
+#[doc = "Register `EVENTS_UNDERFLOW` reader"]
+pub struct R(crate::R<EVENTS_UNDERFLOW_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<EVENTS_UNDERFLOW_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<EVENTS_UNDERFLOW_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<EVENTS_UNDERFLOW_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `EVENTS_UNDERFLOW` writer"]
+pub struct W(crate::W<EVENTS_UNDERFLOW_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<EVENTS_UNDERFLOW_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<EVENTS_UNDERFLOW_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<EVENTS_UNDERFLOW_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `EVENTS_UNDERFLOW` reader - An FPUUFC exception triggered by a floating-point underflow has occurred in the FPU"]
+pub type EVENTS_UNDERFLOW_R = crate::BitReader<EVENTS_UNDERFLOW_A>;
+#[doc = "An FPUUFC exception triggered by a floating-point underflow has occurred in the FPU\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum EVENTS_UNDERFLOW_A {
+    #[doc = "0: Event not generated"]
+    NOT_GENERATED = 0,
+    #[doc = "1: Event generated"]
+    GENERATED = 1,
+}
+impl From<EVENTS_UNDERFLOW_A> for bool {
+    #[inline(always)]
+    fn from(variant: EVENTS_UNDERFLOW_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl EVENTS_UNDERFLOW_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> EVENTS_UNDERFLOW_A {
+        match self.bits {
+            false => EVENTS_UNDERFLOW_A::NOT_GENERATED,
+            true => EVENTS_UNDERFLOW_A::GENERATED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `NOT_GENERATED`"]
+    #[inline(always)]
+    pub fn is_not_generated(&self) -> bool {
+        *self == EVENTS_UNDERFLOW_A::NOT_GENERATED
+    }
+    #[doc = "Checks if the value of the field is `GENERATED`"]
+    #[inline(always)]
+    pub fn is_generated(&self) -> bool {
+        *self == EVENTS_UNDERFLOW_A::GENERATED
+    }
+}
+#[doc = "Field `EVENTS_UNDERFLOW` writer - An FPUUFC exception triggered by a floating-point underflow has occurred in the FPU"]
+pub type EVENTS_UNDERFLOW_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, EVENTS_UNDERFLOW_SPEC, EVENTS_UNDERFLOW_A, O>;
+impl<'a, const O: u8> EVENTS_UNDERFLOW_W<'a, O> {
+    #[doc = "Event not generated"]
+    #[inline(always)]
+    pub fn not_generated(self) -> &'a mut W {
+        self.variant(EVENTS_UNDERFLOW_A::NOT_GENERATED)
+    }
+    #[doc = "Event generated"]
+    #[inline(always)]
+    pub fn generated(self) -> &'a mut W {
+        self.variant(EVENTS_UNDERFLOW_A::GENERATED)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - An FPUUFC exception triggered by a floating-point underflow has occurred in the FPU"]
+    #[inline(always)]
+    pub fn events_underflow(&self) -> EVENTS_UNDERFLOW_R {
+        EVENTS_UNDERFLOW_R::new((self.bits & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - An FPUUFC exception triggered by a floating-point underflow has occurred in the FPU"]
+    #[inline(always)]
+    pub fn events_underflow(&mut self) -> EVENTS_UNDERFLOW_W<0> {
+        EVENTS_UNDERFLOW_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "An FPUUFC exception triggered by a floating-point underflow has occurred in the FPU\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_underflow](index.html) module"]
+pub struct EVENTS_UNDERFLOW_SPEC;
+impl crate::RegisterSpec for EVENTS_UNDERFLOW_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [events_underflow::R](R) reader structure"]
+impl crate::Readable for EVENTS_UNDERFLOW_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [events_underflow::W](W) writer structure"]
+impl crate::Writable for EVENTS_UNDERFLOW_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets EVENTS_UNDERFLOW to value 0"]
+impl crate::Resettable for EVENTS_UNDERFLOW_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf5340-app-pac/src/fpu_ns/inten.rs

@@ -0,0 +1,428 @@
+#[doc = "Register `INTEN` reader"]
+pub struct R(crate::R<INTEN_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<INTEN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<INTEN_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<INTEN_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `INTEN` writer"]
+pub struct W(crate::W<INTEN_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<INTEN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<INTEN_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<INTEN_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `INVALIDOPERATION` reader - Enable or disable interrupt for event INVALIDOPERATION"]
+pub type INVALIDOPERATION_R = crate::BitReader<INVALIDOPERATION_A>;
+#[doc = "Enable or disable interrupt for event INVALIDOPERATION\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum INVALIDOPERATION_A {
+    #[doc = "0: Disable"]
+    DISABLED = 0,
+    #[doc = "1: Enable"]
+    ENABLED = 1,
+}
+impl From<INVALIDOPERATION_A> for bool {
+    #[inline(always)]
+    fn from(variant: INVALIDOPERATION_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl INVALIDOPERATION_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> INVALIDOPERATION_A {
+        match self.bits {
+            false => INVALIDOPERATION_A::DISABLED,
+            true => INVALIDOPERATION_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == INVALIDOPERATION_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == INVALIDOPERATION_A::ENABLED
+    }
+}
+#[doc = "Field `INVALIDOPERATION` writer - Enable or disable interrupt for event INVALIDOPERATION"]
+pub type INVALIDOPERATION_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, INTEN_SPEC, INVALIDOPERATION_A, O>;
+impl<'a, const O: u8> INVALIDOPERATION_W<'a, O> {
+    #[doc = "Disable"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(INVALIDOPERATION_A::DISABLED)
+    }
+    #[doc = "Enable"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(INVALIDOPERATION_A::ENABLED)
+    }
+}
+#[doc = "Field `DIVIDEBYZERO` reader - Enable or disable interrupt for event DIVIDEBYZERO"]
+pub type DIVIDEBYZERO_R = crate::BitReader<DIVIDEBYZERO_A>;
+#[doc = "Enable or disable interrupt for event DIVIDEBYZERO\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DIVIDEBYZERO_A {
+    #[doc = "0: Disable"]
+    DISABLED = 0,
+    #[doc = "1: Enable"]
+    ENABLED = 1,
+}
+impl From<DIVIDEBYZERO_A> for bool {
+    #[inline(always)]
+    fn from(variant: DIVIDEBYZERO_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl DIVIDEBYZERO_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> DIVIDEBYZERO_A {
+        match self.bits {
+            false => DIVIDEBYZERO_A::DISABLED,
+            true => DIVIDEBYZERO_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == DIVIDEBYZERO_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == DIVIDEBYZERO_A::ENABLED
+    }
+}
+#[doc = "Field `DIVIDEBYZERO` writer - Enable or disable interrupt for event DIVIDEBYZERO"]
+pub type DIVIDEBYZERO_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, DIVIDEBYZERO_A, O>;
+impl<'a, const O: u8> DIVIDEBYZERO_W<'a, O> {
+    #[doc = "Disable"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(DIVIDEBYZERO_A::DISABLED)
+    }
+    #[doc = "Enable"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(DIVIDEBYZERO_A::ENABLED)
+    }
+}
+#[doc = "Field `OVERFLOW` reader - Enable or disable interrupt for event OVERFLOW"]
+pub type OVERFLOW_R = crate::BitReader<OVERFLOW_A>;
+#[doc = "Enable or disable interrupt for event OVERFLOW\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum OVERFLOW_A {
+    #[doc = "0: Disable"]
+    DISABLED = 0,
+    #[doc = "1: Enable"]
+    ENABLED = 1,
+}
+impl From<OVERFLOW_A> for bool {
+    #[inline(always)]
+    fn from(variant: OVERFLOW_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl OVERFLOW_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> OVERFLOW_A {
+        match self.bits {
+            false => OVERFLOW_A::DISABLED,
+            true => OVERFLOW_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == OVERFLOW_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == OVERFLOW_A::ENABLED
+    }
+}
+#[doc = "Field `OVERFLOW` writer - Enable or disable interrupt for event OVERFLOW"]
+pub type OVERFLOW_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, OVERFLOW_A, O>;
+impl<'a, const O: u8> OVERFLOW_W<'a, O> {
+    #[doc = "Disable"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(OVERFLOW_A::DISABLED)
+    }
+    #[doc = "Enable"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(OVERFLOW_A::ENABLED)
+    }
+}
+#[doc = "Field `UNDERFLOW` reader - Enable or disable interrupt for event UNDERFLOW"]
+pub type UNDERFLOW_R = crate::BitReader<UNDERFLOW_A>;
+#[doc = "Enable or disable interrupt for event UNDERFLOW\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UNDERFLOW_A {
+    #[doc = "0: Disable"]
+    DISABLED = 0,
+    #[doc = "1: Enable"]
+    ENABLED = 1,
+}
+impl From<UNDERFLOW_A> for bool {
+    #[inline(always)]
+    fn from(variant: UNDERFLOW_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl UNDERFLOW_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> UNDERFLOW_A {
+        match self.bits {
+            false => UNDERFLOW_A::DISABLED,
+            true => UNDERFLOW_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == UNDERFLOW_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == UNDERFLOW_A::ENABLED
+    }
+}
+#[doc = "Field `UNDERFLOW` writer - Enable or disable interrupt for event UNDERFLOW"]
+pub type UNDERFLOW_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, UNDERFLOW_A, O>;
+impl<'a, const O: u8> UNDERFLOW_W<'a, O> {
+    #[doc = "Disable"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(UNDERFLOW_A::DISABLED)
+    }
+    #[doc = "Enable"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(UNDERFLOW_A::ENABLED)
+    }
+}
+#[doc = "Field `INEXACT` reader - Enable or disable interrupt for event INEXACT"]
+pub type INEXACT_R = crate::BitReader<INEXACT_A>;
+#[doc = "Enable or disable interrupt for event INEXACT\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum INEXACT_A {
+    #[doc = "0: Disable"]
+    DISABLED = 0,
+    #[doc = "1: Enable"]
+    ENABLED = 1,
+}
+impl From<INEXACT_A> for bool {
+    #[inline(always)]
+    fn from(variant: INEXACT_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl INEXACT_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> INEXACT_A {
+        match self.bits {
+            false => INEXACT_A::DISABLED,
+            true => INEXACT_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == INEXACT_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == INEXACT_A::ENABLED
+    }
+}
+#[doc = "Field `INEXACT` writer - Enable or disable interrupt for event INEXACT"]
+pub type INEXACT_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, INEXACT_A, O>;
+impl<'a, const O: u8> INEXACT_W<'a, O> {
+    #[doc = "Disable"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(INEXACT_A::DISABLED)
+    }
+    #[doc = "Enable"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(INEXACT_A::ENABLED)
+    }
+}
+#[doc = "Field `DENORMALINPUT` reader - Enable or disable interrupt for event DENORMALINPUT"]
+pub type DENORMALINPUT_R = crate::BitReader<DENORMALINPUT_A>;
+#[doc = "Enable or disable interrupt for event DENORMALINPUT\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DENORMALINPUT_A {
+    #[doc = "0: Disable"]
+    DISABLED = 0,
+    #[doc = "1: Enable"]
+    ENABLED = 1,
+}
+impl From<DENORMALINPUT_A> for bool {
+    #[inline(always)]
+    fn from(variant: DENORMALINPUT_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl DENORMALINPUT_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> DENORMALINPUT_A {
+        match self.bits {
+            false => DENORMALINPUT_A::DISABLED,
+            true => DENORMALINPUT_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == DENORMALINPUT_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == DENORMALINPUT_A::ENABLED
+    }
+}
+#[doc = "Field `DENORMALINPUT` writer - Enable or disable interrupt for event DENORMALINPUT"]
+pub type DENORMALINPUT_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, INTEN_SPEC, DENORMALINPUT_A, O>;
+impl<'a, const O: u8> DENORMALINPUT_W<'a, O> {
+    #[doc = "Disable"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(DENORMALINPUT_A::DISABLED)
+    }
+    #[doc = "Enable"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(DENORMALINPUT_A::ENABLED)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Enable or disable interrupt for event INVALIDOPERATION"]
+    #[inline(always)]
+    pub fn invalidoperation(&self) -> INVALIDOPERATION_R {
+        INVALIDOPERATION_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Enable or disable interrupt for event DIVIDEBYZERO"]
+    #[inline(always)]
+    pub fn dividebyzero(&self) -> DIVIDEBYZERO_R {
+        DIVIDEBYZERO_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Enable or disable interrupt for event OVERFLOW"]
+    #[inline(always)]
+    pub fn overflow(&self) -> OVERFLOW_R {
+        OVERFLOW_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Enable or disable interrupt for event UNDERFLOW"]
+    #[inline(always)]
+    pub fn underflow(&self) -> UNDERFLOW_R {
+        UNDERFLOW_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Enable or disable interrupt for event INEXACT"]
+    #[inline(always)]
+    pub fn inexact(&self) -> INEXACT_R {
+        INEXACT_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - Enable or disable interrupt for event DENORMALINPUT"]
+    #[inline(always)]
+    pub fn denormalinput(&self) -> DENORMALINPUT_R {
+        DENORMALINPUT_R::new(((self.bits >> 5) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Enable or disable interrupt for event INVALIDOPERATION"]
+    #[inline(always)]
+    pub fn invalidoperation(&mut self) -> INVALIDOPERATION_W<0> {
+        INVALIDOPERATION_W::new(self)
+    }
+    #[doc = "Bit 1 - Enable or disable interrupt for event DIVIDEBYZERO"]
+    #[inline(always)]
+    pub fn dividebyzero(&mut self) -> DIVIDEBYZERO_W<1> {
+        DIVIDEBYZERO_W::new(self)
+    }
+    #[doc = "Bit 2 - Enable or disable interrupt for event OVERFLOW"]
+    #[inline(always)]
+    pub fn overflow(&mut self) -> OVERFLOW_W<2> {
+        OVERFLOW_W::new(self)
+    }
+    #[doc = "Bit 3 - Enable or disable interrupt for event UNDERFLOW"]
+    #[inline(always)]
+    pub fn underflow(&mut self) -> UNDERFLOW_W<3> {
+        UNDERFLOW_W::new(self)
+    }
+    #[doc = "Bit 4 - Enable or disable interrupt for event INEXACT"]
+    #[inline(always)]
+    pub fn inexact(&mut self) -> INEXACT_W<4> {
+        INEXACT_W::new(self)
+    }
+    #[doc = "Bit 5 - Enable or disable interrupt for event DENORMALINPUT"]
+    #[inline(always)]
+    pub fn denormalinput(&mut self) -> DENORMALINPUT_W<5> {
+        DENORMALINPUT_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Enable or disable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [inten](index.html) module"]
+pub struct INTEN_SPEC;
+impl crate::RegisterSpec for INTEN_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [inten::R](R) reader structure"]
+impl crate::Readable for INTEN_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [inten::W](W) writer structure"]
+impl crate::Writable for INTEN_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets INTEN to value 0"]
+impl crate::Resettable for INTEN_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf5340-app-pac/src/fpu_ns/intenclr.rs

@@ -0,0 +1,471 @@
+#[doc = "Register `INTENCLR` reader"]
+pub struct R(crate::R<INTENCLR_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<INTENCLR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<INTENCLR_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<INTENCLR_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `INTENCLR` writer"]
+pub struct W(crate::W<INTENCLR_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<INTENCLR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<INTENCLR_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<INTENCLR_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `INVALIDOPERATION` reader - Write '1' to disable interrupt for event INVALIDOPERATION"]
+pub type INVALIDOPERATION_R = crate::BitReader<INVALIDOPERATION_A>;
+#[doc = "Write '1' to disable interrupt for event INVALIDOPERATION\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum INVALIDOPERATION_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<INVALIDOPERATION_A> for bool {
+    #[inline(always)]
+    fn from(variant: INVALIDOPERATION_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl INVALIDOPERATION_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> INVALIDOPERATION_A {
+        match self.bits {
+            false => INVALIDOPERATION_A::DISABLED,
+            true => INVALIDOPERATION_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == INVALIDOPERATION_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == INVALIDOPERATION_A::ENABLED
+    }
+}
+#[doc = "Write '1' to disable interrupt for event INVALIDOPERATION\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum INVALIDOPERATION_AW {
+    #[doc = "1: Disable"]
+    CLEAR = 1,
+}
+impl From<INVALIDOPERATION_AW> for bool {
+    #[inline(always)]
+    fn from(variant: INVALIDOPERATION_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `INVALIDOPERATION` writer - Write '1' to disable interrupt for event INVALIDOPERATION"]
+pub type INVALIDOPERATION_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, INTENCLR_SPEC, INVALIDOPERATION_AW, O>;
+impl<'a, const O: u8> INVALIDOPERATION_W<'a, O> {
+    #[doc = "Disable"]
+    #[inline(always)]
+    pub fn clear(self) -> &'a mut W {
+        self.variant(INVALIDOPERATION_AW::CLEAR)
+    }
+}
+#[doc = "Field `DIVIDEBYZERO` reader - Write '1' to disable interrupt for event DIVIDEBYZERO"]
+pub type DIVIDEBYZERO_R = crate::BitReader<DIVIDEBYZERO_A>;
+#[doc = "Write '1' to disable interrupt for event DIVIDEBYZERO\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DIVIDEBYZERO_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<DIVIDEBYZERO_A> for bool {
+    #[inline(always)]
+    fn from(variant: DIVIDEBYZERO_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl DIVIDEBYZERO_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> DIVIDEBYZERO_A {
+        match self.bits {
+            false => DIVIDEBYZERO_A::DISABLED,
+            true => DIVIDEBYZERO_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == DIVIDEBYZERO_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == DIVIDEBYZERO_A::ENABLED
+    }
+}
+#[doc = "Write '1' to disable interrupt for event DIVIDEBYZERO\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DIVIDEBYZERO_AW {
+    #[doc = "1: Disable"]
+    CLEAR = 1,
+}
+impl From<DIVIDEBYZERO_AW> for bool {
+    #[inline(always)]
+    fn from(variant: DIVIDEBYZERO_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `DIVIDEBYZERO` writer - Write '1' to disable interrupt for event DIVIDEBYZERO"]
+pub type DIVIDEBYZERO_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, INTENCLR_SPEC, DIVIDEBYZERO_AW, O>;
+impl<'a, const O: u8> DIVIDEBYZERO_W<'a, O> {
+    #[doc = "Disable"]
+    #[inline(always)]
+    pub fn clear(self) -> &'a mut W {
+        self.variant(DIVIDEBYZERO_AW::CLEAR)
+    }
+}
+#[doc = "Field `OVERFLOW` reader - Write '1' to disable interrupt for event OVERFLOW"]
+pub type OVERFLOW_R = crate::BitReader<OVERFLOW_A>;
+#[doc = "Write '1' to disable interrupt for event OVERFLOW\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum OVERFLOW_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<OVERFLOW_A> for bool {
+    #[inline(always)]
+    fn from(variant: OVERFLOW_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl OVERFLOW_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> OVERFLOW_A {
+        match self.bits {
+            false => OVERFLOW_A::DISABLED,
+            true => OVERFLOW_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == OVERFLOW_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == OVERFLOW_A::ENABLED
+    }
+}
+#[doc = "Write '1' to disable interrupt for event OVERFLOW\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum OVERFLOW_AW {
+    #[doc = "1: Disable"]
+    CLEAR = 1,
+}
+impl From<OVERFLOW_AW> for bool {
+    #[inline(always)]
+    fn from(variant: OVERFLOW_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `OVERFLOW` writer - Write '1' to disable interrupt for event OVERFLOW"]
+pub type OVERFLOW_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, OVERFLOW_AW, O>;
+impl<'a, const O: u8> OVERFLOW_W<'a, O> {
+    #[doc = "Disable"]
+    #[inline(always)]
+    pub fn clear(self) -> &'a mut W {
+        self.variant(OVERFLOW_AW::CLEAR)
+    }
+}
+#[doc = "Field `UNDERFLOW` reader - Write '1' to disable interrupt for event UNDERFLOW"]
+pub type UNDERFLOW_R = crate::BitReader<UNDERFLOW_A>;
+#[doc = "Write '1' to disable interrupt for event UNDERFLOW\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UNDERFLOW_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<UNDERFLOW_A> for bool {
+    #[inline(always)]
+    fn from(variant: UNDERFLOW_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl UNDERFLOW_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> UNDERFLOW_A {
+        match self.bits {
+            false => UNDERFLOW_A::DISABLED,
+            true => UNDERFLOW_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == UNDERFLOW_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == UNDERFLOW_A::ENABLED
+    }
+}
+#[doc = "Write '1' to disable interrupt for event UNDERFLOW\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UNDERFLOW_AW {
+    #[doc = "1: Disable"]
+    CLEAR = 1,
+}
+impl From<UNDERFLOW_AW> for bool {
+    #[inline(always)]
+    fn from(variant: UNDERFLOW_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `UNDERFLOW` writer - Write '1' to disable interrupt for event UNDERFLOW"]
+pub type UNDERFLOW_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, UNDERFLOW_AW, O>;
+impl<'a, const O: u8> UNDERFLOW_W<'a, O> {
+    #[doc = "Disable"]
+    #[inline(always)]
+    pub fn clear(self) -> &'a mut W {
+        self.variant(UNDERFLOW_AW::CLEAR)
+    }
+}
+#[doc = "Field `INEXACT` reader - Write '1' to disable interrupt for event INEXACT"]
+pub type INEXACT_R = crate::BitReader<INEXACT_A>;
+#[doc = "Write '1' to disable interrupt for event INEXACT\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum INEXACT_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<INEXACT_A> for bool {
+    #[inline(always)]
+    fn from(variant: INEXACT_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl INEXACT_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> INEXACT_A {
+        match self.bits {
+            false => INEXACT_A::DISABLED,
+            true => INEXACT_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == INEXACT_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == INEXACT_A::ENABLED
+    }
+}
+#[doc = "Write '1' to disable interrupt for event INEXACT\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum INEXACT_AW {
+    #[doc = "1: Disable"]
+    CLEAR = 1,
+}
+impl From<INEXACT_AW> for bool {
+    #[inline(always)]
+    fn from(variant: INEXACT_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `INEXACT` writer - Write '1' to disable interrupt for event INEXACT"]
+pub type INEXACT_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, INEXACT_AW, O>;
+impl<'a, const O: u8> INEXACT_W<'a, O> {
+    #[doc = "Disable"]
+    #[inline(always)]
+    pub fn clear(self) -> &'a mut W {
+        self.variant(INEXACT_AW::CLEAR)
+    }
+}
+#[doc = "Field `DENORMALINPUT` reader - Write '1' to disable interrupt for event DENORMALINPUT"]
+pub type DENORMALINPUT_R = crate::BitReader<DENORMALINPUT_A>;
+#[doc = "Write '1' to disable interrupt for event DENORMALINPUT\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DENORMALINPUT_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<DENORMALINPUT_A> for bool {
+    #[inline(always)]
+    fn from(variant: DENORMALINPUT_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl DENORMALINPUT_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> DENORMALINPUT_A {
+        match self.bits {
+            false => DENORMALINPUT_A::DISABLED,
+            true => DENORMALINPUT_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == DENORMALINPUT_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == DENORMALINPUT_A::ENABLED
+    }
+}
+#[doc = "Write '1' to disable interrupt for event DENORMALINPUT\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DENORMALINPUT_AW {
+    #[doc = "1: Disable"]
+    CLEAR = 1,
+}
+impl From<DENORMALINPUT_AW> for bool {
+    #[inline(always)]
+    fn from(variant: DENORMALINPUT_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `DENORMALINPUT` writer - Write '1' to disable interrupt for event DENORMALINPUT"]
+pub type DENORMALINPUT_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, INTENCLR_SPEC, DENORMALINPUT_AW, O>;
+impl<'a, const O: u8> DENORMALINPUT_W<'a, O> {
+    #[doc = "Disable"]
+    #[inline(always)]
+    pub fn clear(self) -> &'a mut W {
+        self.variant(DENORMALINPUT_AW::CLEAR)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Write '1' to disable interrupt for event INVALIDOPERATION"]
+    #[inline(always)]
+    pub fn invalidoperation(&self) -> INVALIDOPERATION_R {
+        INVALIDOPERATION_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Write '1' to disable interrupt for event DIVIDEBYZERO"]
+    #[inline(always)]
+    pub fn dividebyzero(&self) -> DIVIDEBYZERO_R {
+        DIVIDEBYZERO_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Write '1' to disable interrupt for event OVERFLOW"]
+    #[inline(always)]
+    pub fn overflow(&self) -> OVERFLOW_R {
+        OVERFLOW_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Write '1' to disable interrupt for event UNDERFLOW"]
+    #[inline(always)]
+    pub fn underflow(&self) -> UNDERFLOW_R {
+        UNDERFLOW_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Write '1' to disable interrupt for event INEXACT"]
+    #[inline(always)]
+    pub fn inexact(&self) -> INEXACT_R {
+        INEXACT_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - Write '1' to disable interrupt for event DENORMALINPUT"]
+    #[inline(always)]
+    pub fn denormalinput(&self) -> DENORMALINPUT_R {
+        DENORMALINPUT_R::new(((self.bits >> 5) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Write '1' to disable interrupt for event INVALIDOPERATION"]
+    #[inline(always)]
+    pub fn invalidoperation(&mut self) -> INVALIDOPERATION_W<0> {
+        INVALIDOPERATION_W::new(self)
+    }
+    #[doc = "Bit 1 - Write '1' to disable interrupt for event DIVIDEBYZERO"]
+    #[inline(always)]
+    pub fn dividebyzero(&mut self) -> DIVIDEBYZERO_W<1> {
+        DIVIDEBYZERO_W::new(self)
+    }
+    #[doc = "Bit 2 - Write '1' to disable interrupt for event OVERFLOW"]
+    #[inline(always)]
+    pub fn overflow(&mut self) -> OVERFLOW_W<2> {
+        OVERFLOW_W::new(self)
+    }
+    #[doc = "Bit 3 - Write '1' to disable interrupt for event UNDERFLOW"]
+    #[inline(always)]
+    pub fn underflow(&mut self) -> UNDERFLOW_W<3> {
+        UNDERFLOW_W::new(self)
+    }
+    #[doc = "Bit 4 - Write '1' to disable interrupt for event INEXACT"]
+    #[inline(always)]
+    pub fn inexact(&mut self) -> INEXACT_W<4> {
+        INEXACT_W::new(self)
+    }
+    #[doc = "Bit 5 - Write '1' to disable interrupt for event DENORMALINPUT"]
+    #[inline(always)]
+    pub fn denormalinput(&mut self) -> DENORMALINPUT_W<5> {
+        DENORMALINPUT_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Disable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"]
+pub struct INTENCLR_SPEC;
+impl crate::RegisterSpec for INTENCLR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [intenclr::R](R) reader structure"]
+impl crate::Readable for INTENCLR_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"]
+impl crate::Writable for INTENCLR_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets INTENCLR to value 0"]
+impl crate::Resettable for INTENCLR_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf5340-app-pac/src/fpu_ns/intenset.rs

@@ -0,0 +1,471 @@
+#[doc = "Register `INTENSET` reader"]
+pub struct R(crate::R<INTENSET_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<INTENSET_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<INTENSET_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<INTENSET_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `INTENSET` writer"]
+pub struct W(crate::W<INTENSET_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<INTENSET_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<INTENSET_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<INTENSET_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `INVALIDOPERATION` reader - Write '1' to enable interrupt for event INVALIDOPERATION"]
+pub type INVALIDOPERATION_R = crate::BitReader<INVALIDOPERATION_A>;
+#[doc = "Write '1' to enable interrupt for event INVALIDOPERATION\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum INVALIDOPERATION_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<INVALIDOPERATION_A> for bool {
+    #[inline(always)]
+    fn from(variant: INVALIDOPERATION_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl INVALIDOPERATION_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> INVALIDOPERATION_A {
+        match self.bits {
+            false => INVALIDOPERATION_A::DISABLED,
+            true => INVALIDOPERATION_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == INVALIDOPERATION_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == INVALIDOPERATION_A::ENABLED
+    }
+}
+#[doc = "Write '1' to enable interrupt for event INVALIDOPERATION\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum INVALIDOPERATION_AW {
+    #[doc = "1: Enable"]
+    SET = 1,
+}
+impl From<INVALIDOPERATION_AW> for bool {
+    #[inline(always)]
+    fn from(variant: INVALIDOPERATION_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `INVALIDOPERATION` writer - Write '1' to enable interrupt for event INVALIDOPERATION"]
+pub type INVALIDOPERATION_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, INTENSET_SPEC, INVALIDOPERATION_AW, O>;
+impl<'a, const O: u8> INVALIDOPERATION_W<'a, O> {
+    #[doc = "Enable"]
+    #[inline(always)]
+    pub fn set(self) -> &'a mut W {
+        self.variant(INVALIDOPERATION_AW::SET)
+    }
+}
+#[doc = "Field `DIVIDEBYZERO` reader - Write '1' to enable interrupt for event DIVIDEBYZERO"]
+pub type DIVIDEBYZERO_R = crate::BitReader<DIVIDEBYZERO_A>;
+#[doc = "Write '1' to enable interrupt for event DIVIDEBYZERO\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DIVIDEBYZERO_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<DIVIDEBYZERO_A> for bool {
+    #[inline(always)]
+    fn from(variant: DIVIDEBYZERO_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl DIVIDEBYZERO_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> DIVIDEBYZERO_A {
+        match self.bits {
+            false => DIVIDEBYZERO_A::DISABLED,
+            true => DIVIDEBYZERO_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == DIVIDEBYZERO_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == DIVIDEBYZERO_A::ENABLED
+    }
+}
+#[doc = "Write '1' to enable interrupt for event DIVIDEBYZERO\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DIVIDEBYZERO_AW {
+    #[doc = "1: Enable"]
+    SET = 1,
+}
+impl From<DIVIDEBYZERO_AW> for bool {
+    #[inline(always)]
+    fn from(variant: DIVIDEBYZERO_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `DIVIDEBYZERO` writer - Write '1' to enable interrupt for event DIVIDEBYZERO"]
+pub type DIVIDEBYZERO_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, INTENSET_SPEC, DIVIDEBYZERO_AW, O>;
+impl<'a, const O: u8> DIVIDEBYZERO_W<'a, O> {
+    #[doc = "Enable"]
+    #[inline(always)]
+    pub fn set(self) -> &'a mut W {
+        self.variant(DIVIDEBYZERO_AW::SET)
+    }
+}
+#[doc = "Field `OVERFLOW` reader - Write '1' to enable interrupt for event OVERFLOW"]
+pub type OVERFLOW_R = crate::BitReader<OVERFLOW_A>;
+#[doc = "Write '1' to enable interrupt for event OVERFLOW\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum OVERFLOW_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<OVERFLOW_A> for bool {
+    #[inline(always)]
+    fn from(variant: OVERFLOW_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl OVERFLOW_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> OVERFLOW_A {
+        match self.bits {
+            false => OVERFLOW_A::DISABLED,
+            true => OVERFLOW_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == OVERFLOW_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == OVERFLOW_A::ENABLED
+    }
+}
+#[doc = "Write '1' to enable interrupt for event OVERFLOW\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum OVERFLOW_AW {
+    #[doc = "1: Enable"]
+    SET = 1,
+}
+impl From<OVERFLOW_AW> for bool {
+    #[inline(always)]
+    fn from(variant: OVERFLOW_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `OVERFLOW` writer - Write '1' to enable interrupt for event OVERFLOW"]
+pub type OVERFLOW_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, OVERFLOW_AW, O>;
+impl<'a, const O: u8> OVERFLOW_W<'a, O> {
+    #[doc = "Enable"]
+    #[inline(always)]
+    pub fn set(self) -> &'a mut W {
+        self.variant(OVERFLOW_AW::SET)
+    }
+}
+#[doc = "Field `UNDERFLOW` reader - Write '1' to enable interrupt for event UNDERFLOW"]
+pub type UNDERFLOW_R = crate::BitReader<UNDERFLOW_A>;
+#[doc = "Write '1' to enable interrupt for event UNDERFLOW\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UNDERFLOW_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<UNDERFLOW_A> for bool {
+    #[inline(always)]
+    fn from(variant: UNDERFLOW_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl UNDERFLOW_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> UNDERFLOW_A {
+        match self.bits {
+            false => UNDERFLOW_A::DISABLED,
+            true => UNDERFLOW_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == UNDERFLOW_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == UNDERFLOW_A::ENABLED
+    }
+}
+#[doc = "Write '1' to enable interrupt for event UNDERFLOW\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UNDERFLOW_AW {
+    #[doc = "1: Enable"]
+    SET = 1,
+}
+impl From<UNDERFLOW_AW> for bool {
+    #[inline(always)]
+    fn from(variant: UNDERFLOW_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `UNDERFLOW` writer - Write '1' to enable interrupt for event UNDERFLOW"]
+pub type UNDERFLOW_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, UNDERFLOW_AW, O>;
+impl<'a, const O: u8> UNDERFLOW_W<'a, O> {
+    #[doc = "Enable"]
+    #[inline(always)]
+    pub fn set(self) -> &'a mut W {
+        self.variant(UNDERFLOW_AW::SET)
+    }
+}
+#[doc = "Field `INEXACT` reader - Write '1' to enable interrupt for event INEXACT"]
+pub type INEXACT_R = crate::BitReader<INEXACT_A>;
+#[doc = "Write '1' to enable interrupt for event INEXACT\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum INEXACT_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<INEXACT_A> for bool {
+    #[inline(always)]
+    fn from(variant: INEXACT_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl INEXACT_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> INEXACT_A {
+        match self.bits {
+            false => INEXACT_A::DISABLED,
+            true => INEXACT_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == INEXACT_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == INEXACT_A::ENABLED
+    }
+}
+#[doc = "Write '1' to enable interrupt for event INEXACT\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum INEXACT_AW {
+    #[doc = "1: Enable"]
+    SET = 1,
+}
+impl From<INEXACT_AW> for bool {
+    #[inline(always)]
+    fn from(variant: INEXACT_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `INEXACT` writer - Write '1' to enable interrupt for event INEXACT"]
+pub type INEXACT_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, INEXACT_AW, O>;
+impl<'a, const O: u8> INEXACT_W<'a, O> {
+    #[doc = "Enable"]
+    #[inline(always)]
+    pub fn set(self) -> &'a mut W {
+        self.variant(INEXACT_AW::SET)
+    }
+}
+#[doc = "Field `DENORMALINPUT` reader - Write '1' to enable interrupt for event DENORMALINPUT"]
+pub type DENORMALINPUT_R = crate::BitReader<DENORMALINPUT_A>;
+#[doc = "Write '1' to enable interrupt for event DENORMALINPUT\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DENORMALINPUT_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<DENORMALINPUT_A> for bool {
+    #[inline(always)]
+    fn from(variant: DENORMALINPUT_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl DENORMALINPUT_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> DENORMALINPUT_A {
+        match self.bits {
+            false => DENORMALINPUT_A::DISABLED,
+            true => DENORMALINPUT_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == DENORMALINPUT_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == DENORMALINPUT_A::ENABLED
+    }
+}
+#[doc = "Write '1' to enable interrupt for event DENORMALINPUT\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DENORMALINPUT_AW {
+    #[doc = "1: Enable"]
+    SET = 1,
+}
+impl From<DENORMALINPUT_AW> for bool {
+    #[inline(always)]
+    fn from(variant: DENORMALINPUT_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `DENORMALINPUT` writer - Write '1' to enable interrupt for event DENORMALINPUT"]
+pub type DENORMALINPUT_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, INTENSET_SPEC, DENORMALINPUT_AW, O>;
+impl<'a, const O: u8> DENORMALINPUT_W<'a, O> {
+    #[doc = "Enable"]
+    #[inline(always)]
+    pub fn set(self) -> &'a mut W {
+        self.variant(DENORMALINPUT_AW::SET)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Write '1' to enable interrupt for event INVALIDOPERATION"]
+    #[inline(always)]
+    pub fn invalidoperation(&self) -> INVALIDOPERATION_R {
+        INVALIDOPERATION_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Write '1' to enable interrupt for event DIVIDEBYZERO"]
+    #[inline(always)]
+    pub fn dividebyzero(&self) -> DIVIDEBYZERO_R {
+        DIVIDEBYZERO_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Write '1' to enable interrupt for event OVERFLOW"]
+    #[inline(always)]
+    pub fn overflow(&self) -> OVERFLOW_R {
+        OVERFLOW_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Write '1' to enable interrupt for event UNDERFLOW"]
+    #[inline(always)]
+    pub fn underflow(&self) -> UNDERFLOW_R {
+        UNDERFLOW_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Write '1' to enable interrupt for event INEXACT"]
+    #[inline(always)]
+    pub fn inexact(&self) -> INEXACT_R {
+        INEXACT_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - Write '1' to enable interrupt for event DENORMALINPUT"]
+    #[inline(always)]
+    pub fn denormalinput(&self) -> DENORMALINPUT_R {
+        DENORMALINPUT_R::new(((self.bits >> 5) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Write '1' to enable interrupt for event INVALIDOPERATION"]
+    #[inline(always)]
+    pub fn invalidoperation(&mut self) -> INVALIDOPERATION_W<0> {
+        INVALIDOPERATION_W::new(self)
+    }
+    #[doc = "Bit 1 - Write '1' to enable interrupt for event DIVIDEBYZERO"]
+    #[inline(always)]
+    pub fn dividebyzero(&mut self) -> DIVIDEBYZERO_W<1> {
+        DIVIDEBYZERO_W::new(self)
+    }
+    #[doc = "Bit 2 - Write '1' to enable interrupt for event OVERFLOW"]
+    #[inline(always)]
+    pub fn overflow(&mut self) -> OVERFLOW_W<2> {
+        OVERFLOW_W::new(self)
+    }
+    #[doc = "Bit 3 - Write '1' to enable interrupt for event UNDERFLOW"]
+    #[inline(always)]
+    pub fn underflow(&mut self) -> UNDERFLOW_W<3> {
+        UNDERFLOW_W::new(self)
+    }
+    #[doc = "Bit 4 - Write '1' to enable interrupt for event INEXACT"]
+    #[inline(always)]
+    pub fn inexact(&mut self) -> INEXACT_W<4> {
+        INEXACT_W::new(self)
+    }
+    #[doc = "Bit 5 - Write '1' to enable interrupt for event DENORMALINPUT"]
+    #[inline(always)]
+    pub fn denormalinput(&mut self) -> DENORMALINPUT_W<5> {
+        DENORMALINPUT_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Enable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"]
+pub struct INTENSET_SPEC;
+impl crate::RegisterSpec for INTENSET_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [intenset::R](R) reader structure"]
+impl crate::Readable for INTENSET_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"]
+impl crate::Writable for INTENSET_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets INTENSET to value 0"]
+impl crate::Resettable for INTENSET_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}