feat: add display UI with splash screen, dashboard, and RSSI sparkline

Implement full SSD1306 OLED display support:
- Splash screen on boot (1.5s) with project name, version, board
- Dashboard showing radio state, config, counters, RSSI/SNR
- RSSI history sparkline (64-sample ring buffer, 2px-wide bars)
- DisplayOn/DisplayOff host commands routed via dedicated channel
- Pure render functions against generic DrawTarget (no hardware coupling)
- Display on/off control bypasses radio task entirely

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>

vendor/nrf5340-app-pac/src/qspi_ns/addrconf.rs

@@ -0,0 +1,316 @@
+#[doc = "Register `ADDRCONF` reader"]
+pub struct R(crate::R<ADDRCONF_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<ADDRCONF_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<ADDRCONF_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<ADDRCONF_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `ADDRCONF` writer"]
+pub struct W(crate::W<ADDRCONF_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<ADDRCONF_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<ADDRCONF_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<ADDRCONF_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `OPCODE` reader - Opcode that enters the 32-bit addressing mode."]
+pub type OPCODE_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `OPCODE` writer - Opcode that enters the 32-bit addressing mode."]
+pub type OPCODE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ADDRCONF_SPEC, u8, u8, 8, O>;
+#[doc = "Field `BYTE0` reader - Byte 0 following opcode."]
+pub type BYTE0_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `BYTE0` writer - Byte 0 following opcode."]
+pub type BYTE0_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ADDRCONF_SPEC, u8, u8, 8, O>;
+#[doc = "Field `BYTE1` reader - Byte 1 following byte 0."]
+pub type BYTE1_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `BYTE1` writer - Byte 1 following byte 0."]
+pub type BYTE1_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ADDRCONF_SPEC, u8, u8, 8, O>;
+#[doc = "Field `MODE` reader - Extended addressing mode."]
+pub type MODE_R = crate::FieldReader<u8, MODE_A>;
+#[doc = "Extended addressing mode.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum MODE_A {
+    #[doc = "0: Do not send any instruction."]
+    NO_INSTR = 0,
+    #[doc = "1: Send opcode."]
+    OPCODE = 1,
+    #[doc = "2: Send opcode, BYTE0."]
+    OP_BYTE0 = 2,
+    #[doc = "3: Send opcode, BYTE0, BYTE1."]
+    ALL = 3,
+}
+impl From<MODE_A> for u8 {
+    #[inline(always)]
+    fn from(variant: MODE_A) -> Self {
+        variant as _
+    }
+}
+impl MODE_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> MODE_A {
+        match self.bits {
+            0 => MODE_A::NO_INSTR,
+            1 => MODE_A::OPCODE,
+            2 => MODE_A::OP_BYTE0,
+            3 => MODE_A::ALL,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `NO_INSTR`"]
+    #[inline(always)]
+    pub fn is_no_instr(&self) -> bool {
+        *self == MODE_A::NO_INSTR
+    }
+    #[doc = "Checks if the value of the field is `OPCODE`"]
+    #[inline(always)]
+    pub fn is_opcode(&self) -> bool {
+        *self == MODE_A::OPCODE
+    }
+    #[doc = "Checks if the value of the field is `OP_BYTE0`"]
+    #[inline(always)]
+    pub fn is_op_byte0(&self) -> bool {
+        *self == MODE_A::OP_BYTE0
+    }
+    #[doc = "Checks if the value of the field is `ALL`"]
+    #[inline(always)]
+    pub fn is_all(&self) -> bool {
+        *self == MODE_A::ALL
+    }
+}
+#[doc = "Field `MODE` writer - Extended addressing mode."]
+pub type MODE_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u32, ADDRCONF_SPEC, u8, MODE_A, 2, O>;
+impl<'a, const O: u8> MODE_W<'a, O> {
+    #[doc = "Do not send any instruction."]
+    #[inline(always)]
+    pub fn no_instr(self) -> &'a mut W {
+        self.variant(MODE_A::NO_INSTR)
+    }
+    #[doc = "Send opcode."]
+    #[inline(always)]
+    pub fn opcode(self) -> &'a mut W {
+        self.variant(MODE_A::OPCODE)
+    }
+    #[doc = "Send opcode, BYTE0."]
+    #[inline(always)]
+    pub fn op_byte0(self) -> &'a mut W {
+        self.variant(MODE_A::OP_BYTE0)
+    }
+    #[doc = "Send opcode, BYTE0, BYTE1."]
+    #[inline(always)]
+    pub fn all(self) -> &'a mut W {
+        self.variant(MODE_A::ALL)
+    }
+}
+#[doc = "Field `WIPWAIT` reader - Wait for write complete before sending command."]
+pub type WIPWAIT_R = crate::BitReader<WIPWAIT_A>;
+#[doc = "Wait for write complete before sending command.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum WIPWAIT_A {
+    #[doc = "0: No wait."]
+    DISABLE = 0,
+    #[doc = "1: Wait."]
+    ENABLE = 1,
+}
+impl From<WIPWAIT_A> for bool {
+    #[inline(always)]
+    fn from(variant: WIPWAIT_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl WIPWAIT_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> WIPWAIT_A {
+        match self.bits {
+            false => WIPWAIT_A::DISABLE,
+            true => WIPWAIT_A::ENABLE,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLE`"]
+    #[inline(always)]
+    pub fn is_disable(&self) -> bool {
+        *self == WIPWAIT_A::DISABLE
+    }
+    #[doc = "Checks if the value of the field is `ENABLE`"]
+    #[inline(always)]
+    pub fn is_enable(&self) -> bool {
+        *self == WIPWAIT_A::ENABLE
+    }
+}
+#[doc = "Field `WIPWAIT` writer - Wait for write complete before sending command."]
+pub type WIPWAIT_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADDRCONF_SPEC, WIPWAIT_A, O>;
+impl<'a, const O: u8> WIPWAIT_W<'a, O> {
+    #[doc = "No wait."]
+    #[inline(always)]
+    pub fn disable(self) -> &'a mut W {
+        self.variant(WIPWAIT_A::DISABLE)
+    }
+    #[doc = "Wait."]
+    #[inline(always)]
+    pub fn enable(self) -> &'a mut W {
+        self.variant(WIPWAIT_A::ENABLE)
+    }
+}
+#[doc = "Field `WREN` reader - Send WREN (write enable opcode 0x06) before instruction."]
+pub type WREN_R = crate::BitReader<WREN_A>;
+#[doc = "Send WREN (write enable opcode 0x06) before instruction.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum WREN_A {
+    #[doc = "0: Do not send WREN."]
+    DISABLE = 0,
+    #[doc = "1: Send WREN."]
+    ENABLE = 1,
+}
+impl From<WREN_A> for bool {
+    #[inline(always)]
+    fn from(variant: WREN_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl WREN_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> WREN_A {
+        match self.bits {
+            false => WREN_A::DISABLE,
+            true => WREN_A::ENABLE,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLE`"]
+    #[inline(always)]
+    pub fn is_disable(&self) -> bool {
+        *self == WREN_A::DISABLE
+    }
+    #[doc = "Checks if the value of the field is `ENABLE`"]
+    #[inline(always)]
+    pub fn is_enable(&self) -> bool {
+        *self == WREN_A::ENABLE
+    }
+}
+#[doc = "Field `WREN` writer - Send WREN (write enable opcode 0x06) before instruction."]
+pub type WREN_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADDRCONF_SPEC, WREN_A, O>;
+impl<'a, const O: u8> WREN_W<'a, O> {
+    #[doc = "Do not send WREN."]
+    #[inline(always)]
+    pub fn disable(self) -> &'a mut W {
+        self.variant(WREN_A::DISABLE)
+    }
+    #[doc = "Send WREN."]
+    #[inline(always)]
+    pub fn enable(self) -> &'a mut W {
+        self.variant(WREN_A::ENABLE)
+    }
+}
+impl R {
+    #[doc = "Bits 0:7 - Opcode that enters the 32-bit addressing mode."]
+    #[inline(always)]
+    pub fn opcode(&self) -> OPCODE_R {
+        OPCODE_R::new((self.bits & 0xff) as u8)
+    }
+    #[doc = "Bits 8:15 - Byte 0 following opcode."]
+    #[inline(always)]
+    pub fn byte0(&self) -> BYTE0_R {
+        BYTE0_R::new(((self.bits >> 8) & 0xff) as u8)
+    }
+    #[doc = "Bits 16:23 - Byte 1 following byte 0."]
+    #[inline(always)]
+    pub fn byte1(&self) -> BYTE1_R {
+        BYTE1_R::new(((self.bits >> 16) & 0xff) as u8)
+    }
+    #[doc = "Bits 24:25 - Extended addressing mode."]
+    #[inline(always)]
+    pub fn mode(&self) -> MODE_R {
+        MODE_R::new(((self.bits >> 24) & 3) as u8)
+    }
+    #[doc = "Bit 26 - Wait for write complete before sending command."]
+    #[inline(always)]
+    pub fn wipwait(&self) -> WIPWAIT_R {
+        WIPWAIT_R::new(((self.bits >> 26) & 1) != 0)
+    }
+    #[doc = "Bit 27 - Send WREN (write enable opcode 0x06) before instruction."]
+    #[inline(always)]
+    pub fn wren(&self) -> WREN_R {
+        WREN_R::new(((self.bits >> 27) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - Opcode that enters the 32-bit addressing mode."]
+    #[inline(always)]
+    pub fn opcode(&mut self) -> OPCODE_W<0> {
+        OPCODE_W::new(self)
+    }
+    #[doc = "Bits 8:15 - Byte 0 following opcode."]
+    #[inline(always)]
+    pub fn byte0(&mut self) -> BYTE0_W<8> {
+        BYTE0_W::new(self)
+    }
+    #[doc = "Bits 16:23 - Byte 1 following byte 0."]
+    #[inline(always)]
+    pub fn byte1(&mut self) -> BYTE1_W<16> {
+        BYTE1_W::new(self)
+    }
+    #[doc = "Bits 24:25 - Extended addressing mode."]
+    #[inline(always)]
+    pub fn mode(&mut self) -> MODE_W<24> {
+        MODE_W::new(self)
+    }
+    #[doc = "Bit 26 - Wait for write complete before sending command."]
+    #[inline(always)]
+    pub fn wipwait(&mut self) -> WIPWAIT_W<26> {
+        WIPWAIT_W::new(self)
+    }
+    #[doc = "Bit 27 - Send WREN (write enable opcode 0x06) before instruction."]
+    #[inline(always)]
+    pub fn wren(&mut self) -> WREN_W<27> {
+        WREN_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Extended address configuration.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addrconf](index.html) module"]
+pub struct ADDRCONF_SPEC;
+impl crate::RegisterSpec for ADDRCONF_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [addrconf::R](R) reader structure"]
+impl crate::Readable for ADDRCONF_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [addrconf::W](W) writer structure"]
+impl crate::Writable for ADDRCONF_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets ADDRCONF to value 0xb7"]
+impl crate::Resettable for ADDRCONF_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0xb7
+    }
+}

vendor/nrf5340-app-pac/src/qspi_ns/cinstrconf.rs

@@ -0,0 +1,490 @@
+#[doc = "Register `CINSTRCONF` reader"]
+pub struct R(crate::R<CINSTRCONF_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<CINSTRCONF_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<CINSTRCONF_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<CINSTRCONF_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `CINSTRCONF` writer"]
+pub struct W(crate::W<CINSTRCONF_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<CINSTRCONF_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<CINSTRCONF_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<CINSTRCONF_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `OPCODE` reader - Opcode of Custom instruction."]
+pub type OPCODE_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `OPCODE` writer - Opcode of Custom instruction."]
+pub type OPCODE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CINSTRCONF_SPEC, u8, u8, 8, O>;
+#[doc = "Field `LENGTH` reader - Length of custom instruction in number of bytes."]
+pub type LENGTH_R = crate::FieldReader<u8, LENGTH_A>;
+#[doc = "Length of custom instruction in number of bytes.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum LENGTH_A {
+    #[doc = "1: Send opcode only."]
+    _1B = 1,
+    #[doc = "2: Send opcode, CINSTRDAT0.BYTE0."]
+    _2B = 2,
+    #[doc = "3: Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT0.BYTE1."]
+    _3B = 3,
+    #[doc = "4: Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT0.BYTE2."]
+    _4B = 4,
+    #[doc = "5: Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT0.BYTE3."]
+    _5B = 5,
+    #[doc = "6: Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE4."]
+    _6B = 6,
+    #[doc = "7: Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE5."]
+    _7B = 7,
+    #[doc = "8: Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE6."]
+    _8B = 8,
+    #[doc = "9: Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE7."]
+    _9B = 9,
+}
+impl From<LENGTH_A> for u8 {
+    #[inline(always)]
+    fn from(variant: LENGTH_A) -> Self {
+        variant as _
+    }
+}
+impl LENGTH_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<LENGTH_A> {
+        match self.bits {
+            1 => Some(LENGTH_A::_1B),
+            2 => Some(LENGTH_A::_2B),
+            3 => Some(LENGTH_A::_3B),
+            4 => Some(LENGTH_A::_4B),
+            5 => Some(LENGTH_A::_5B),
+            6 => Some(LENGTH_A::_6B),
+            7 => Some(LENGTH_A::_7B),
+            8 => Some(LENGTH_A::_8B),
+            9 => Some(LENGTH_A::_9B),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_1B`"]
+    #[inline(always)]
+    pub fn is_1b(&self) -> bool {
+        *self == LENGTH_A::_1B
+    }
+    #[doc = "Checks if the value of the field is `_2B`"]
+    #[inline(always)]
+    pub fn is_2b(&self) -> bool {
+        *self == LENGTH_A::_2B
+    }
+    #[doc = "Checks if the value of the field is `_3B`"]
+    #[inline(always)]
+    pub fn is_3b(&self) -> bool {
+        *self == LENGTH_A::_3B
+    }
+    #[doc = "Checks if the value of the field is `_4B`"]
+    #[inline(always)]
+    pub fn is_4b(&self) -> bool {
+        *self == LENGTH_A::_4B
+    }
+    #[doc = "Checks if the value of the field is `_5B`"]
+    #[inline(always)]
+    pub fn is_5b(&self) -> bool {
+        *self == LENGTH_A::_5B
+    }
+    #[doc = "Checks if the value of the field is `_6B`"]
+    #[inline(always)]
+    pub fn is_6b(&self) -> bool {
+        *self == LENGTH_A::_6B
+    }
+    #[doc = "Checks if the value of the field is `_7B`"]
+    #[inline(always)]
+    pub fn is_7b(&self) -> bool {
+        *self == LENGTH_A::_7B
+    }
+    #[doc = "Checks if the value of the field is `_8B`"]
+    #[inline(always)]
+    pub fn is_8b(&self) -> bool {
+        *self == LENGTH_A::_8B
+    }
+    #[doc = "Checks if the value of the field is `_9B`"]
+    #[inline(always)]
+    pub fn is_9b(&self) -> bool {
+        *self == LENGTH_A::_9B
+    }
+}
+#[doc = "Field `LENGTH` writer - Length of custom instruction in number of bytes."]
+pub type LENGTH_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u32, CINSTRCONF_SPEC, u8, LENGTH_A, 4, O>;
+impl<'a, const O: u8> LENGTH_W<'a, O> {
+    #[doc = "Send opcode only."]
+    #[inline(always)]
+    pub fn _1b(self) -> &'a mut W {
+        self.variant(LENGTH_A::_1B)
+    }
+    #[doc = "Send opcode, CINSTRDAT0.BYTE0."]
+    #[inline(always)]
+    pub fn _2b(self) -> &'a mut W {
+        self.variant(LENGTH_A::_2B)
+    }
+    #[doc = "Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT0.BYTE1."]
+    #[inline(always)]
+    pub fn _3b(self) -> &'a mut W {
+        self.variant(LENGTH_A::_3B)
+    }
+    #[doc = "Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT0.BYTE2."]
+    #[inline(always)]
+    pub fn _4b(self) -> &'a mut W {
+        self.variant(LENGTH_A::_4B)
+    }
+    #[doc = "Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT0.BYTE3."]
+    #[inline(always)]
+    pub fn _5b(self) -> &'a mut W {
+        self.variant(LENGTH_A::_5B)
+    }
+    #[doc = "Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE4."]
+    #[inline(always)]
+    pub fn _6b(self) -> &'a mut W {
+        self.variant(LENGTH_A::_6B)
+    }
+    #[doc = "Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE5."]
+    #[inline(always)]
+    pub fn _7b(self) -> &'a mut W {
+        self.variant(LENGTH_A::_7B)
+    }
+    #[doc = "Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE6."]
+    #[inline(always)]
+    pub fn _8b(self) -> &'a mut W {
+        self.variant(LENGTH_A::_8B)
+    }
+    #[doc = "Send opcode, CINSTRDAT0.BYTE0 -&gt; CINSTRDAT1.BYTE7."]
+    #[inline(always)]
+    pub fn _9b(self) -> &'a mut W {
+        self.variant(LENGTH_A::_9B)
+    }
+}
+#[doc = "Field `LIO2` reader - Level of the IO2 pin (if connected) during transmission of custom instruction."]
+pub type LIO2_R = crate::BitReader<bool>;
+#[doc = "Field `LIO2` writer - Level of the IO2 pin (if connected) during transmission of custom instruction."]
+pub type LIO2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CINSTRCONF_SPEC, bool, O>;
+#[doc = "Field `LIO3` reader - Level of the IO3 pin (if connected) during transmission of custom instruction."]
+pub type LIO3_R = crate::BitReader<bool>;
+#[doc = "Field `LIO3` writer - Level of the IO3 pin (if connected) during transmission of custom instruction."]
+pub type LIO3_W<'a, const O: u8> = crate::BitWriter<'a, u32, CINSTRCONF_SPEC, bool, O>;
+#[doc = "Field `WIPWAIT` reader - Wait for write complete before sending command."]
+pub type WIPWAIT_R = crate::BitReader<WIPWAIT_A>;
+#[doc = "Wait for write complete before sending command.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum WIPWAIT_A {
+    #[doc = "0: No wait."]
+    DISABLE = 0,
+    #[doc = "1: Wait."]
+    ENABLE = 1,
+}
+impl From<WIPWAIT_A> for bool {
+    #[inline(always)]
+    fn from(variant: WIPWAIT_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl WIPWAIT_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> WIPWAIT_A {
+        match self.bits {
+            false => WIPWAIT_A::DISABLE,
+            true => WIPWAIT_A::ENABLE,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLE`"]
+    #[inline(always)]
+    pub fn is_disable(&self) -> bool {
+        *self == WIPWAIT_A::DISABLE
+    }
+    #[doc = "Checks if the value of the field is `ENABLE`"]
+    #[inline(always)]
+    pub fn is_enable(&self) -> bool {
+        *self == WIPWAIT_A::ENABLE
+    }
+}
+#[doc = "Field `WIPWAIT` writer - Wait for write complete before sending command."]
+pub type WIPWAIT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CINSTRCONF_SPEC, WIPWAIT_A, O>;
+impl<'a, const O: u8> WIPWAIT_W<'a, O> {
+    #[doc = "No wait."]
+    #[inline(always)]
+    pub fn disable(self) -> &'a mut W {
+        self.variant(WIPWAIT_A::DISABLE)
+    }
+    #[doc = "Wait."]
+    #[inline(always)]
+    pub fn enable(self) -> &'a mut W {
+        self.variant(WIPWAIT_A::ENABLE)
+    }
+}
+#[doc = "Field `WREN` reader - Send WREN (write enable opcode 0x06) before instruction."]
+pub type WREN_R = crate::BitReader<WREN_A>;
+#[doc = "Send WREN (write enable opcode 0x06) before instruction.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum WREN_A {
+    #[doc = "0: Do not send WREN."]
+    DISABLE = 0,
+    #[doc = "1: Send WREN."]
+    ENABLE = 1,
+}
+impl From<WREN_A> for bool {
+    #[inline(always)]
+    fn from(variant: WREN_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl WREN_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> WREN_A {
+        match self.bits {
+            false => WREN_A::DISABLE,
+            true => WREN_A::ENABLE,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLE`"]
+    #[inline(always)]
+    pub fn is_disable(&self) -> bool {
+        *self == WREN_A::DISABLE
+    }
+    #[doc = "Checks if the value of the field is `ENABLE`"]
+    #[inline(always)]
+    pub fn is_enable(&self) -> bool {
+        *self == WREN_A::ENABLE
+    }
+}
+#[doc = "Field `WREN` writer - Send WREN (write enable opcode 0x06) before instruction."]
+pub type WREN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CINSTRCONF_SPEC, WREN_A, O>;
+impl<'a, const O: u8> WREN_W<'a, O> {
+    #[doc = "Do not send WREN."]
+    #[inline(always)]
+    pub fn disable(self) -> &'a mut W {
+        self.variant(WREN_A::DISABLE)
+    }
+    #[doc = "Send WREN."]
+    #[inline(always)]
+    pub fn enable(self) -> &'a mut W {
+        self.variant(WREN_A::ENABLE)
+    }
+}
+#[doc = "Field `LFEN` reader - Enable Long frame mode. When enabled, a custom instruction transaction has to be ended by writing the LFSTOP field."]
+pub type LFEN_R = crate::BitReader<LFEN_A>;
+#[doc = "Enable Long frame mode. When enabled, a custom instruction transaction has to be ended by writing the LFSTOP field.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum LFEN_A {
+    #[doc = "0: Long frame mode disabled"]
+    DISABLE = 0,
+    #[doc = "1: Long frame mode enabled"]
+    ENABLE = 1,
+}
+impl From<LFEN_A> for bool {
+    #[inline(always)]
+    fn from(variant: LFEN_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl LFEN_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> LFEN_A {
+        match self.bits {
+            false => LFEN_A::DISABLE,
+            true => LFEN_A::ENABLE,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLE`"]
+    #[inline(always)]
+    pub fn is_disable(&self) -> bool {
+        *self == LFEN_A::DISABLE
+    }
+    #[doc = "Checks if the value of the field is `ENABLE`"]
+    #[inline(always)]
+    pub fn is_enable(&self) -> bool {
+        *self == LFEN_A::ENABLE
+    }
+}
+#[doc = "Field `LFEN` writer - Enable Long frame mode. When enabled, a custom instruction transaction has to be ended by writing the LFSTOP field."]
+pub type LFEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CINSTRCONF_SPEC, LFEN_A, O>;
+impl<'a, const O: u8> LFEN_W<'a, O> {
+    #[doc = "Long frame mode disabled"]
+    #[inline(always)]
+    pub fn disable(self) -> &'a mut W {
+        self.variant(LFEN_A::DISABLE)
+    }
+    #[doc = "Long frame mode enabled"]
+    #[inline(always)]
+    pub fn enable(self) -> &'a mut W {
+        self.variant(LFEN_A::ENABLE)
+    }
+}
+#[doc = "Field `LFSTOP` reader - Stop (finalize) long frame transaction"]
+pub type LFSTOP_R = crate::BitReader<LFSTOP_A>;
+#[doc = "Stop (finalize) long frame transaction\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum LFSTOP_A {
+    #[doc = "1: Stop"]
+    STOP = 1,
+}
+impl From<LFSTOP_A> for bool {
+    #[inline(always)]
+    fn from(variant: LFSTOP_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl LFSTOP_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<LFSTOP_A> {
+        match self.bits {
+            true => Some(LFSTOP_A::STOP),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `STOP`"]
+    #[inline(always)]
+    pub fn is_stop(&self) -> bool {
+        *self == LFSTOP_A::STOP
+    }
+}
+#[doc = "Field `LFSTOP` writer - Stop (finalize) long frame transaction"]
+pub type LFSTOP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CINSTRCONF_SPEC, LFSTOP_A, O>;
+impl<'a, const O: u8> LFSTOP_W<'a, O> {
+    #[doc = "Stop"]
+    #[inline(always)]
+    pub fn stop(self) -> &'a mut W {
+        self.variant(LFSTOP_A::STOP)
+    }
+}
+impl R {
+    #[doc = "Bits 0:7 - Opcode of Custom instruction."]
+    #[inline(always)]
+    pub fn opcode(&self) -> OPCODE_R {
+        OPCODE_R::new((self.bits & 0xff) as u8)
+    }
+    #[doc = "Bits 8:11 - Length of custom instruction in number of bytes."]
+    #[inline(always)]
+    pub fn length(&self) -> LENGTH_R {
+        LENGTH_R::new(((self.bits >> 8) & 0x0f) as u8)
+    }
+    #[doc = "Bit 12 - Level of the IO2 pin (if connected) during transmission of custom instruction."]
+    #[inline(always)]
+    pub fn lio2(&self) -> LIO2_R {
+        LIO2_R::new(((self.bits >> 12) & 1) != 0)
+    }
+    #[doc = "Bit 13 - Level of the IO3 pin (if connected) during transmission of custom instruction."]
+    #[inline(always)]
+    pub fn lio3(&self) -> LIO3_R {
+        LIO3_R::new(((self.bits >> 13) & 1) != 0)
+    }
+    #[doc = "Bit 14 - Wait for write complete before sending command."]
+    #[inline(always)]
+    pub fn wipwait(&self) -> WIPWAIT_R {
+        WIPWAIT_R::new(((self.bits >> 14) & 1) != 0)
+    }
+    #[doc = "Bit 15 - Send WREN (write enable opcode 0x06) before instruction."]
+    #[inline(always)]
+    pub fn wren(&self) -> WREN_R {
+        WREN_R::new(((self.bits >> 15) & 1) != 0)
+    }
+    #[doc = "Bit 16 - Enable Long frame mode. When enabled, a custom instruction transaction has to be ended by writing the LFSTOP field."]
+    #[inline(always)]
+    pub fn lfen(&self) -> LFEN_R {
+        LFEN_R::new(((self.bits >> 16) & 1) != 0)
+    }
+    #[doc = "Bit 17 - Stop (finalize) long frame transaction"]
+    #[inline(always)]
+    pub fn lfstop(&self) -> LFSTOP_R {
+        LFSTOP_R::new(((self.bits >> 17) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - Opcode of Custom instruction."]
+    #[inline(always)]
+    pub fn opcode(&mut self) -> OPCODE_W<0> {
+        OPCODE_W::new(self)
+    }
+    #[doc = "Bits 8:11 - Length of custom instruction in number of bytes."]
+    #[inline(always)]
+    pub fn length(&mut self) -> LENGTH_W<8> {
+        LENGTH_W::new(self)
+    }
+    #[doc = "Bit 12 - Level of the IO2 pin (if connected) during transmission of custom instruction."]
+    #[inline(always)]
+    pub fn lio2(&mut self) -> LIO2_W<12> {
+        LIO2_W::new(self)
+    }
+    #[doc = "Bit 13 - Level of the IO3 pin (if connected) during transmission of custom instruction."]
+    #[inline(always)]
+    pub fn lio3(&mut self) -> LIO3_W<13> {
+        LIO3_W::new(self)
+    }
+    #[doc = "Bit 14 - Wait for write complete before sending command."]
+    #[inline(always)]
+    pub fn wipwait(&mut self) -> WIPWAIT_W<14> {
+        WIPWAIT_W::new(self)
+    }
+    #[doc = "Bit 15 - Send WREN (write enable opcode 0x06) before instruction."]
+    #[inline(always)]
+    pub fn wren(&mut self) -> WREN_W<15> {
+        WREN_W::new(self)
+    }
+    #[doc = "Bit 16 - Enable Long frame mode. When enabled, a custom instruction transaction has to be ended by writing the LFSTOP field."]
+    #[inline(always)]
+    pub fn lfen(&mut self) -> LFEN_W<16> {
+        LFEN_W::new(self)
+    }
+    #[doc = "Bit 17 - Stop (finalize) long frame transaction"]
+    #[inline(always)]
+    pub fn lfstop(&mut self) -> LFSTOP_W<17> {
+        LFSTOP_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Custom instruction configuration register.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cinstrconf](index.html) module"]
+pub struct CINSTRCONF_SPEC;
+impl crate::RegisterSpec for CINSTRCONF_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [cinstrconf::R](R) reader structure"]
+impl crate::Readable for CINSTRCONF_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [cinstrconf::W](W) writer structure"]
+impl crate::Writable for CINSTRCONF_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets CINSTRCONF to value 0x2000"]
+impl crate::Resettable for CINSTRCONF_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0x2000
+    }
+}

vendor/nrf5340-app-pac/src/qspi_ns/cinstrdat0.rs

@@ -0,0 +1,122 @@
+#[doc = "Register `CINSTRDAT0` reader"]
+pub struct R(crate::R<CINSTRDAT0_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<CINSTRDAT0_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<CINSTRDAT0_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<CINSTRDAT0_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `CINSTRDAT0` writer"]
+pub struct W(crate::W<CINSTRDAT0_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<CINSTRDAT0_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<CINSTRDAT0_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<CINSTRDAT0_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `BYTE0` reader - Data byte 0"]
+pub type BYTE0_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `BYTE0` writer - Data byte 0"]
+pub type BYTE0_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CINSTRDAT0_SPEC, u8, u8, 8, O>;
+#[doc = "Field `BYTE1` reader - Data byte 1"]
+pub type BYTE1_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `BYTE1` writer - Data byte 1"]
+pub type BYTE1_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CINSTRDAT0_SPEC, u8, u8, 8, O>;
+#[doc = "Field `BYTE2` reader - Data byte 2"]
+pub type BYTE2_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `BYTE2` writer - Data byte 2"]
+pub type BYTE2_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CINSTRDAT0_SPEC, u8, u8, 8, O>;
+#[doc = "Field `BYTE3` reader - Data byte 3"]
+pub type BYTE3_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `BYTE3` writer - Data byte 3"]
+pub type BYTE3_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CINSTRDAT0_SPEC, u8, u8, 8, O>;
+impl R {
+    #[doc = "Bits 0:7 - Data byte 0"]
+    #[inline(always)]
+    pub fn byte0(&self) -> BYTE0_R {
+        BYTE0_R::new((self.bits & 0xff) as u8)
+    }
+    #[doc = "Bits 8:15 - Data byte 1"]
+    #[inline(always)]
+    pub fn byte1(&self) -> BYTE1_R {
+        BYTE1_R::new(((self.bits >> 8) & 0xff) as u8)
+    }
+    #[doc = "Bits 16:23 - Data byte 2"]
+    #[inline(always)]
+    pub fn byte2(&self) -> BYTE2_R {
+        BYTE2_R::new(((self.bits >> 16) & 0xff) as u8)
+    }
+    #[doc = "Bits 24:31 - Data byte 3"]
+    #[inline(always)]
+    pub fn byte3(&self) -> BYTE3_R {
+        BYTE3_R::new(((self.bits >> 24) & 0xff) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - Data byte 0"]
+    #[inline(always)]
+    pub fn byte0(&mut self) -> BYTE0_W<0> {
+        BYTE0_W::new(self)
+    }
+    #[doc = "Bits 8:15 - Data byte 1"]
+    #[inline(always)]
+    pub fn byte1(&mut self) -> BYTE1_W<8> {
+        BYTE1_W::new(self)
+    }
+    #[doc = "Bits 16:23 - Data byte 2"]
+    #[inline(always)]
+    pub fn byte2(&mut self) -> BYTE2_W<16> {
+        BYTE2_W::new(self)
+    }
+    #[doc = "Bits 24:31 - Data byte 3"]
+    #[inline(always)]
+    pub fn byte3(&mut self) -> BYTE3_W<24> {
+        BYTE3_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Custom instruction data register 0.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cinstrdat0](index.html) module"]
+pub struct CINSTRDAT0_SPEC;
+impl crate::RegisterSpec for CINSTRDAT0_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [cinstrdat0::R](R) reader structure"]
+impl crate::Readable for CINSTRDAT0_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [cinstrdat0::W](W) writer structure"]
+impl crate::Writable for CINSTRDAT0_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets CINSTRDAT0 to value 0"]
+impl crate::Resettable for CINSTRDAT0_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf5340-app-pac/src/qspi_ns/cinstrdat1.rs

@@ -0,0 +1,122 @@
+#[doc = "Register `CINSTRDAT1` reader"]
+pub struct R(crate::R<CINSTRDAT1_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<CINSTRDAT1_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<CINSTRDAT1_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<CINSTRDAT1_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `CINSTRDAT1` writer"]
+pub struct W(crate::W<CINSTRDAT1_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<CINSTRDAT1_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<CINSTRDAT1_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<CINSTRDAT1_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `BYTE4` reader - Data byte 4"]
+pub type BYTE4_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `BYTE4` writer - Data byte 4"]
+pub type BYTE4_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CINSTRDAT1_SPEC, u8, u8, 8, O>;
+#[doc = "Field `BYTE5` reader - Data byte 5"]
+pub type BYTE5_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `BYTE5` writer - Data byte 5"]
+pub type BYTE5_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CINSTRDAT1_SPEC, u8, u8, 8, O>;
+#[doc = "Field `BYTE6` reader - Data byte 6"]
+pub type BYTE6_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `BYTE6` writer - Data byte 6"]
+pub type BYTE6_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CINSTRDAT1_SPEC, u8, u8, 8, O>;
+#[doc = "Field `BYTE7` reader - Data byte 7"]
+pub type BYTE7_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `BYTE7` writer - Data byte 7"]
+pub type BYTE7_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CINSTRDAT1_SPEC, u8, u8, 8, O>;
+impl R {
+    #[doc = "Bits 0:7 - Data byte 4"]
+    #[inline(always)]
+    pub fn byte4(&self) -> BYTE4_R {
+        BYTE4_R::new((self.bits & 0xff) as u8)
+    }
+    #[doc = "Bits 8:15 - Data byte 5"]
+    #[inline(always)]
+    pub fn byte5(&self) -> BYTE5_R {
+        BYTE5_R::new(((self.bits >> 8) & 0xff) as u8)
+    }
+    #[doc = "Bits 16:23 - Data byte 6"]
+    #[inline(always)]
+    pub fn byte6(&self) -> BYTE6_R {
+        BYTE6_R::new(((self.bits >> 16) & 0xff) as u8)
+    }
+    #[doc = "Bits 24:31 - Data byte 7"]
+    #[inline(always)]
+    pub fn byte7(&self) -> BYTE7_R {
+        BYTE7_R::new(((self.bits >> 24) & 0xff) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - Data byte 4"]
+    #[inline(always)]
+    pub fn byte4(&mut self) -> BYTE4_W<0> {
+        BYTE4_W::new(self)
+    }
+    #[doc = "Bits 8:15 - Data byte 5"]
+    #[inline(always)]
+    pub fn byte5(&mut self) -> BYTE5_W<8> {
+        BYTE5_W::new(self)
+    }
+    #[doc = "Bits 16:23 - Data byte 6"]
+    #[inline(always)]
+    pub fn byte6(&mut self) -> BYTE6_W<16> {
+        BYTE6_W::new(self)
+    }
+    #[doc = "Bits 24:31 - Data byte 7"]
+    #[inline(always)]
+    pub fn byte7(&mut self) -> BYTE7_W<24> {
+        BYTE7_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Custom instruction data register 1.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cinstrdat1](index.html) module"]
+pub struct CINSTRDAT1_SPEC;
+impl crate::RegisterSpec for CINSTRDAT1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [cinstrdat1::R](R) reader structure"]
+impl crate::Readable for CINSTRDAT1_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [cinstrdat1::W](W) writer structure"]
+impl crate::Writable for CINSTRDAT1_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets CINSTRDAT1 to value 0"]
+impl crate::Resettable for CINSTRDAT1_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf5340-app-pac/src/qspi_ns/dma_enc.rs

@@ -0,0 +1,52 @@
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct DMA_ENC {
+    #[doc = "0x00 - Bits 31:0 of DMA AES KEY"]
+    pub key0: KEY0,
+    #[doc = "0x04 - Bits 63:32 of DMA AES KEY"]
+    pub key1: KEY1,
+    #[doc = "0x08 - Bits 95:64 of DMA AES KEY"]
+    pub key2: KEY2,
+    #[doc = "0x0c - Bits 127:96 of DMA AES KEY"]
+    pub key3: KEY3,
+    #[doc = "0x10 - Bits 31:0 of DMA NONCE"]
+    pub nonce0: NONCE0,
+    #[doc = "0x14 - Bits 63:32 of DMA NONCE"]
+    pub nonce1: NONCE1,
+    #[doc = "0x18 - Bits 95:64 of DMA NONCE"]
+    pub nonce2: NONCE2,
+    #[doc = "0x1c - Enable stream cipher for EasyDMA"]
+    pub enable: ENABLE,
+}
+#[doc = "KEY0 (w) register accessor: an alias for `Reg<KEY0_SPEC>`"]
+pub type KEY0 = crate::Reg<key0::KEY0_SPEC>;
+#[doc = "Bits 31:0 of DMA AES KEY"]
+pub mod key0;
+#[doc = "KEY1 (w) register accessor: an alias for `Reg<KEY1_SPEC>`"]
+pub type KEY1 = crate::Reg<key1::KEY1_SPEC>;
+#[doc = "Bits 63:32 of DMA AES KEY"]
+pub mod key1;
+#[doc = "KEY2 (w) register accessor: an alias for `Reg<KEY2_SPEC>`"]
+pub type KEY2 = crate::Reg<key2::KEY2_SPEC>;
+#[doc = "Bits 95:64 of DMA AES KEY"]
+pub mod key2;
+#[doc = "KEY3 (w) register accessor: an alias for `Reg<KEY3_SPEC>`"]
+pub type KEY3 = crate::Reg<key3::KEY3_SPEC>;
+#[doc = "Bits 127:96 of DMA AES KEY"]
+pub mod key3;
+#[doc = "NONCE0 (w) register accessor: an alias for `Reg<NONCE0_SPEC>`"]
+pub type NONCE0 = crate::Reg<nonce0::NONCE0_SPEC>;
+#[doc = "Bits 31:0 of DMA NONCE"]
+pub mod nonce0;
+#[doc = "NONCE1 (w) register accessor: an alias for `Reg<NONCE1_SPEC>`"]
+pub type NONCE1 = crate::Reg<nonce1::NONCE1_SPEC>;
+#[doc = "Bits 63:32 of DMA NONCE"]
+pub mod nonce1;
+#[doc = "NONCE2 (w) register accessor: an alias for `Reg<NONCE2_SPEC>`"]
+pub type NONCE2 = crate::Reg<nonce2::NONCE2_SPEC>;
+#[doc = "Bits 95:64 of DMA NONCE"]
+pub mod nonce2;
+#[doc = "ENABLE (rw) register accessor: an alias for `Reg<ENABLE_SPEC>`"]
+pub type ENABLE = crate::Reg<enable::ENABLE_SPEC>;
+#[doc = "Enable stream cipher for EasyDMA"]
+pub mod enable;

vendor/nrf5340-app-pac/src/qspi_ns/dma_enc/enable.rs

@@ -0,0 +1,126 @@
+#[doc = "Register `ENABLE` reader"]
+pub struct R(crate::R<ENABLE_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<ENABLE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<ENABLE_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<ENABLE_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `ENABLE` writer"]
+pub struct W(crate::W<ENABLE_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<ENABLE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<ENABLE_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<ENABLE_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `ENABLE` reader - Enable or disable stream cipher for EasyDMA"]
+pub type ENABLE_R = crate::BitReader<ENABLE_A>;
+#[doc = "Enable or disable stream cipher for EasyDMA\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ENABLE_A {
+    #[doc = "0: Disable stream cipher for QSPI EasyDMA"]
+    DISABLED = 0,
+    #[doc = "1: Enable stream cipher for QSPI EasyDMA"]
+    ENABLED = 1,
+}
+impl From<ENABLE_A> for bool {
+    #[inline(always)]
+    fn from(variant: ENABLE_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl ENABLE_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> ENABLE_A {
+        match self.bits {
+            false => ENABLE_A::DISABLED,
+            true => ENABLE_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == ENABLE_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == ENABLE_A::ENABLED
+    }
+}
+#[doc = "Field `ENABLE` writer - Enable or disable stream cipher for EasyDMA"]
+pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, ENABLE_SPEC, ENABLE_A, O>;
+impl<'a, const O: u8> ENABLE_W<'a, O> {
+    #[doc = "Disable stream cipher for QSPI EasyDMA"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(ENABLE_A::DISABLED)
+    }
+    #[doc = "Enable stream cipher for QSPI EasyDMA"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(ENABLE_A::ENABLED)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Enable or disable stream cipher for EasyDMA"]
+    #[inline(always)]
+    pub fn enable(&self) -> ENABLE_R {
+        ENABLE_R::new((self.bits & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Enable or disable stream cipher for EasyDMA"]
+    #[inline(always)]
+    pub fn enable(&mut self) -> ENABLE_W<0> {
+        ENABLE_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Enable stream cipher for EasyDMA\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [enable](index.html) module"]
+pub struct ENABLE_SPEC;
+impl crate::RegisterSpec for ENABLE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [enable::R](R) reader structure"]
+impl crate::Readable for ENABLE_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [enable::W](W) writer structure"]
+impl crate::Writable for ENABLE_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets ENABLE to value 0"]
+impl crate::Resettable for ENABLE_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf5340-app-pac/src/qspi_ns/dma_enc/key0.rs

@@ -0,0 +1,52 @@
+#[doc = "Register `KEY0` writer"]
+pub struct W(crate::W<KEY0_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<KEY0_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<KEY0_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<KEY0_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `KEY0` writer - Bits 31:0 of DMA AES KEY"]
+pub type KEY0_W<'a, const O: u8> = crate::FieldWriter<'a, u32, KEY0_SPEC, u32, u32, 32, O>;
+impl W {
+    #[doc = "Bits 0:31 - Bits 31:0 of DMA AES KEY"]
+    #[inline(always)]
+    pub fn key0(&mut self) -> KEY0_W<0> {
+        KEY0_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Bits 31:0 of DMA AES KEY\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [key0](index.html) module"]
+pub struct KEY0_SPEC;
+impl crate::RegisterSpec for KEY0_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [key0::W](W) writer structure"]
+impl crate::Writable for KEY0_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets KEY0 to value 0"]
+impl crate::Resettable for KEY0_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf5340-app-pac/src/qspi_ns/dma_enc/key1.rs

@@ -0,0 +1,52 @@
+#[doc = "Register `KEY1` writer"]
+pub struct W(crate::W<KEY1_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<KEY1_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<KEY1_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<KEY1_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `KEY1` writer - Bits 63:32 of DMA AES KEY"]
+pub type KEY1_W<'a, const O: u8> = crate::FieldWriter<'a, u32, KEY1_SPEC, u32, u32, 32, O>;
+impl W {
+    #[doc = "Bits 0:31 - Bits 63:32 of DMA AES KEY"]
+    #[inline(always)]
+    pub fn key1(&mut self) -> KEY1_W<0> {
+        KEY1_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Bits 63:32 of DMA AES KEY\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [key1](index.html) module"]
+pub struct KEY1_SPEC;
+impl crate::RegisterSpec for KEY1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [key1::W](W) writer structure"]
+impl crate::Writable for KEY1_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets KEY1 to value 0"]
+impl crate::Resettable for KEY1_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf5340-app-pac/src/qspi_ns/dma_enc/key2.rs

@@ -0,0 +1,52 @@
+#[doc = "Register `KEY2` writer"]
+pub struct W(crate::W<KEY2_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<KEY2_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<KEY2_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<KEY2_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `KEY2` writer - Bits 95:64 of DMA AES KEY"]
+pub type KEY2_W<'a, const O: u8> = crate::FieldWriter<'a, u32, KEY2_SPEC, u32, u32, 32, O>;
+impl W {
+    #[doc = "Bits 0:31 - Bits 95:64 of DMA AES KEY"]
+    #[inline(always)]
+    pub fn key2(&mut self) -> KEY2_W<0> {
+        KEY2_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Bits 95:64 of DMA AES KEY\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [key2](index.html) module"]
+pub struct KEY2_SPEC;
+impl crate::RegisterSpec for KEY2_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [key2::W](W) writer structure"]
+impl crate::Writable for KEY2_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets KEY2 to value 0"]
+impl crate::Resettable for KEY2_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf5340-app-pac/src/qspi_ns/dma_enc/key3.rs

@@ -0,0 +1,52 @@
+#[doc = "Register `KEY3` writer"]
+pub struct W(crate::W<KEY3_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<KEY3_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<KEY3_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<KEY3_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `KEY3` writer - Bits 127:96 of DMA AES KEY"]
+pub type KEY3_W<'a, const O: u8> = crate::FieldWriter<'a, u32, KEY3_SPEC, u32, u32, 32, O>;
+impl W {
+    #[doc = "Bits 0:31 - Bits 127:96 of DMA AES KEY"]
+    #[inline(always)]
+    pub fn key3(&mut self) -> KEY3_W<0> {
+        KEY3_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Bits 127:96 of DMA AES KEY\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [key3](index.html) module"]
+pub struct KEY3_SPEC;
+impl crate::RegisterSpec for KEY3_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [key3::W](W) writer structure"]
+impl crate::Writable for KEY3_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets KEY3 to value 0"]
+impl crate::Resettable for KEY3_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf5340-app-pac/src/qspi_ns/dma_enc/nonce0.rs

@@ -0,0 +1,52 @@
+#[doc = "Register `NONCE0` writer"]
+pub struct W(crate::W<NONCE0_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<NONCE0_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<NONCE0_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<NONCE0_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `NONCE0` writer - Bits 31:0 of DMA NONCE"]
+pub type NONCE0_W<'a, const O: u8> = crate::FieldWriter<'a, u32, NONCE0_SPEC, u32, u32, 32, O>;
+impl W {
+    #[doc = "Bits 0:31 - Bits 31:0 of DMA NONCE"]
+    #[inline(always)]
+    pub fn nonce0(&mut self) -> NONCE0_W<0> {
+        NONCE0_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Bits 31:0 of DMA NONCE\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [nonce0](index.html) module"]
+pub struct NONCE0_SPEC;
+impl crate::RegisterSpec for NONCE0_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [nonce0::W](W) writer structure"]
+impl crate::Writable for NONCE0_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets NONCE0 to value 0"]
+impl crate::Resettable for NONCE0_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf5340-app-pac/src/qspi_ns/dma_enc/nonce1.rs

@@ -0,0 +1,52 @@
+#[doc = "Register `NONCE1` writer"]
+pub struct W(crate::W<NONCE1_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<NONCE1_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<NONCE1_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<NONCE1_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `NONCE1` writer - Bits 63:32 of DMA NONCE"]
+pub type NONCE1_W<'a, const O: u8> = crate::FieldWriter<'a, u32, NONCE1_SPEC, u32, u32, 32, O>;
+impl W {
+    #[doc = "Bits 0:31 - Bits 63:32 of DMA NONCE"]
+    #[inline(always)]
+    pub fn nonce1(&mut self) -> NONCE1_W<0> {
+        NONCE1_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Bits 63:32 of DMA NONCE\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [nonce1](index.html) module"]
+pub struct NONCE1_SPEC;
+impl crate::RegisterSpec for NONCE1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [nonce1::W](W) writer structure"]
+impl crate::Writable for NONCE1_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets NONCE1 to value 0"]
+impl crate::Resettable for NONCE1_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf5340-app-pac/src/qspi_ns/dma_enc/nonce2.rs

@@ -0,0 +1,52 @@
+#[doc = "Register `NONCE2` writer"]
+pub struct W(crate::W<NONCE2_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<NONCE2_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<NONCE2_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<NONCE2_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `NONCE2` writer - Bits 95:64 of DMA NONCE"]
+pub type NONCE2_W<'a, const O: u8> = crate::FieldWriter<'a, u32, NONCE2_SPEC, u32, u32, 32, O>;
+impl W {
+    #[doc = "Bits 0:31 - Bits 95:64 of DMA NONCE"]
+    #[inline(always)]
+    pub fn nonce2(&mut self) -> NONCE2_W<0> {
+        NONCE2_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Bits 95:64 of DMA NONCE\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [nonce2](index.html) module"]
+pub struct NONCE2_SPEC;
+impl crate::RegisterSpec for NONCE2_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [nonce2::W](W) writer structure"]
+impl crate::Writable for NONCE2_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets NONCE2 to value 0"]
+impl crate::Resettable for NONCE2_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf5340-app-pac/src/qspi_ns/dpmdur.rs

@@ -0,0 +1,94 @@
+#[doc = "Register `DPMDUR` reader"]
+pub struct R(crate::R<DPMDUR_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<DPMDUR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<DPMDUR_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<DPMDUR_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `DPMDUR` writer"]
+pub struct W(crate::W<DPMDUR_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<DPMDUR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<DPMDUR_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<DPMDUR_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `ENTER` reader - Duration needed by external flash to enter DPM. Duration is given as ENTER * 256 * 62.5 ns."]
+pub type ENTER_R = crate::FieldReader<u16, u16>;
+#[doc = "Field `ENTER` writer - Duration needed by external flash to enter DPM. Duration is given as ENTER * 256 * 62.5 ns."]
+pub type ENTER_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DPMDUR_SPEC, u16, u16, 16, O>;
+#[doc = "Field `EXIT` reader - Duration needed by external flash to exit DPM. Duration is given as EXIT * 256 * 62.5 ns."]
+pub type EXIT_R = crate::FieldReader<u16, u16>;
+#[doc = "Field `EXIT` writer - Duration needed by external flash to exit DPM. Duration is given as EXIT * 256 * 62.5 ns."]
+pub type EXIT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DPMDUR_SPEC, u16, u16, 16, O>;
+impl R {
+    #[doc = "Bits 0:15 - Duration needed by external flash to enter DPM. Duration is given as ENTER * 256 * 62.5 ns."]
+    #[inline(always)]
+    pub fn enter(&self) -> ENTER_R {
+        ENTER_R::new((self.bits & 0xffff) as u16)
+    }
+    #[doc = "Bits 16:31 - Duration needed by external flash to exit DPM. Duration is given as EXIT * 256 * 62.5 ns."]
+    #[inline(always)]
+    pub fn exit(&self) -> EXIT_R {
+        EXIT_R::new(((self.bits >> 16) & 0xffff) as u16)
+    }
+}
+impl W {
+    #[doc = "Bits 0:15 - Duration needed by external flash to enter DPM. Duration is given as ENTER * 256 * 62.5 ns."]
+    #[inline(always)]
+    pub fn enter(&mut self) -> ENTER_W<0> {
+        ENTER_W::new(self)
+    }
+    #[doc = "Bits 16:31 - Duration needed by external flash to exit DPM. Duration is given as EXIT * 256 * 62.5 ns."]
+    #[inline(always)]
+    pub fn exit(&mut self) -> EXIT_W<16> {
+        EXIT_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Set the duration required to enter/exit deep power-down mode (DPM).\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpmdur](index.html) module"]
+pub struct DPMDUR_SPEC;
+impl crate::RegisterSpec for DPMDUR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [dpmdur::R](R) reader structure"]
+impl crate::Readable for DPMDUR_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [dpmdur::W](W) writer structure"]
+impl crate::Writable for DPMDUR_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets DPMDUR to value 0xffff_ffff"]
+impl crate::Resettable for DPMDUR_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0xffff_ffff
+    }
+}

vendor/nrf5340-app-pac/src/qspi_ns/enable.rs

@@ -0,0 +1,126 @@
+#[doc = "Register `ENABLE` reader"]
+pub struct R(crate::R<ENABLE_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<ENABLE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<ENABLE_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<ENABLE_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `ENABLE` writer"]
+pub struct W(crate::W<ENABLE_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<ENABLE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<ENABLE_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<ENABLE_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `ENABLE` reader - Enable or disable QSPI"]
+pub type ENABLE_R = crate::BitReader<ENABLE_A>;
+#[doc = "Enable or disable QSPI\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ENABLE_A {
+    #[doc = "0: Disable QSPI"]
+    DISABLED = 0,
+    #[doc = "1: Enable QSPI"]
+    ENABLED = 1,
+}
+impl From<ENABLE_A> for bool {
+    #[inline(always)]
+    fn from(variant: ENABLE_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl ENABLE_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> ENABLE_A {
+        match self.bits {
+            false => ENABLE_A::DISABLED,
+            true => ENABLE_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == ENABLE_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == ENABLE_A::ENABLED
+    }
+}
+#[doc = "Field `ENABLE` writer - Enable or disable QSPI"]
+pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, ENABLE_SPEC, ENABLE_A, O>;
+impl<'a, const O: u8> ENABLE_W<'a, O> {
+    #[doc = "Disable QSPI"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(ENABLE_A::DISABLED)
+    }
+    #[doc = "Enable QSPI"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(ENABLE_A::ENABLED)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Enable or disable QSPI"]
+    #[inline(always)]
+    pub fn enable(&self) -> ENABLE_R {
+        ENABLE_R::new((self.bits & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Enable or disable QSPI"]
+    #[inline(always)]
+    pub fn enable(&mut self) -> ENABLE_W<0> {
+        ENABLE_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Enable QSPI peripheral and acquire the pins selected in PSELn registers\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [enable](index.html) module"]
+pub struct ENABLE_SPEC;
+impl crate::RegisterSpec for ENABLE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [enable::R](R) reader structure"]
+impl crate::Readable for ENABLE_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [enable::W](W) writer structure"]
+impl crate::Writable for ENABLE_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets ENABLE to value 0"]
+impl crate::Resettable for ENABLE_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf5340-app-pac/src/qspi_ns/erase.rs

@@ -0,0 +1,16 @@
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct ERASE {
+    #[doc = "0x00 - Start address of flash block to be erased"]
+    pub ptr: PTR,
+    #[doc = "0x04 - Size of block to be erased."]
+    pub len: LEN,
+}
+#[doc = "PTR (rw) register accessor: an alias for `Reg<PTR_SPEC>`"]
+pub type PTR = crate::Reg<ptr::PTR_SPEC>;
+#[doc = "Start address of flash block to be erased"]
+pub mod ptr;
+#[doc = "LEN (rw) register accessor: an alias for `Reg<LEN_SPEC>`"]
+pub type LEN = crate::Reg<len::LEN_SPEC>;
+#[doc = "Size of block to be erased."]
+pub mod len;

vendor/nrf5340-app-pac/src/qspi_ns/erase/len.rs

@@ -0,0 +1,141 @@
+#[doc = "Register `LEN` reader"]
+pub struct R(crate::R<LEN_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<LEN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<LEN_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<LEN_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `LEN` writer"]
+pub struct W(crate::W<LEN_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<LEN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<LEN_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<LEN_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `LEN` reader - LEN"]
+pub type LEN_R = crate::FieldReader<u8, LEN_A>;
+#[doc = "LEN\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum LEN_A {
+    #[doc = "0: Erase 4 kB block (flash command 0x20)"]
+    _4KB = 0,
+    #[doc = "1: Erase 64 kB block (flash command 0xD8)"]
+    _64KB = 1,
+    #[doc = "2: Erase all (flash command 0xC7)"]
+    ALL = 2,
+}
+impl From<LEN_A> for u8 {
+    #[inline(always)]
+    fn from(variant: LEN_A) -> Self {
+        variant as _
+    }
+}
+impl LEN_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<LEN_A> {
+        match self.bits {
+            0 => Some(LEN_A::_4KB),
+            1 => Some(LEN_A::_64KB),
+            2 => Some(LEN_A::ALL),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_4KB`"]
+    #[inline(always)]
+    pub fn is_4kb(&self) -> bool {
+        *self == LEN_A::_4KB
+    }
+    #[doc = "Checks if the value of the field is `_64KB`"]
+    #[inline(always)]
+    pub fn is_64kb(&self) -> bool {
+        *self == LEN_A::_64KB
+    }
+    #[doc = "Checks if the value of the field is `ALL`"]
+    #[inline(always)]
+    pub fn is_all(&self) -> bool {
+        *self == LEN_A::ALL
+    }
+}
+#[doc = "Field `LEN` writer - LEN"]
+pub type LEN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, LEN_SPEC, u8, LEN_A, 2, O>;
+impl<'a, const O: u8> LEN_W<'a, O> {
+    #[doc = "Erase 4 kB block (flash command 0x20)"]
+    #[inline(always)]
+    pub fn _4kb(self) -> &'a mut W {
+        self.variant(LEN_A::_4KB)
+    }
+    #[doc = "Erase 64 kB block (flash command 0xD8)"]
+    #[inline(always)]
+    pub fn _64kb(self) -> &'a mut W {
+        self.variant(LEN_A::_64KB)
+    }
+    #[doc = "Erase all (flash command 0xC7)"]
+    #[inline(always)]
+    pub fn all(self) -> &'a mut W {
+        self.variant(LEN_A::ALL)
+    }
+}
+impl R {
+    #[doc = "Bits 0:1 - LEN"]
+    #[inline(always)]
+    pub fn len(&self) -> LEN_R {
+        LEN_R::new((self.bits & 3) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:1 - LEN"]
+    #[inline(always)]
+    pub fn len(&mut self) -> LEN_W<0> {
+        LEN_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Size of block to be erased.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [len](index.html) module"]
+pub struct LEN_SPEC;
+impl crate::RegisterSpec for LEN_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [len::R](R) reader structure"]
+impl crate::Readable for LEN_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [len::W](W) writer structure"]
+impl crate::Writable for LEN_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets LEN to value 0"]
+impl crate::Resettable for LEN_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf5340-app-pac/src/qspi_ns/erase/ptr.rs

@@ -0,0 +1,80 @@
+#[doc = "Register `PTR` reader"]
+pub struct R(crate::R<PTR_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<PTR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<PTR_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<PTR_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `PTR` writer"]
+pub struct W(crate::W<PTR_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<PTR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<PTR_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<PTR_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `PTR` reader - Word-aligned start address of block to be erased."]
+pub type PTR_R = crate::FieldReader<u32, u32>;
+#[doc = "Field `PTR` writer - Word-aligned start address of block to be erased."]
+pub type PTR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PTR_SPEC, u32, u32, 32, O>;
+impl R {
+    #[doc = "Bits 0:31 - Word-aligned start address of block to be erased."]
+    #[inline(always)]
+    pub fn ptr(&self) -> PTR_R {
+        PTR_R::new(self.bits)
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Word-aligned start address of block to be erased."]
+    #[inline(always)]
+    pub fn ptr(&mut self) -> PTR_W<0> {
+        PTR_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Start address of flash block to be erased\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ptr](index.html) module"]
+pub struct PTR_SPEC;
+impl crate::RegisterSpec for PTR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [ptr::R](R) reader structure"]
+impl crate::Readable for PTR_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [ptr::W](W) writer structure"]
+impl crate::Writable for PTR_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets PTR to value 0"]
+impl crate::Resettable for PTR_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf5340-app-pac/src/qspi_ns/events_ready.rs

@@ -0,0 +1,127 @@
+#[doc = "Register `EVENTS_READY` reader"]
+pub struct R(crate::R<EVENTS_READY_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<EVENTS_READY_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<EVENTS_READY_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<EVENTS_READY_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `EVENTS_READY` writer"]
+pub struct W(crate::W<EVENTS_READY_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<EVENTS_READY_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<EVENTS_READY_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<EVENTS_READY_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `EVENTS_READY` reader - QSPI peripheral is ready. This event will be generated as a response to all QSPI tasks except DEACTIVATE."]
+pub type EVENTS_READY_R = crate::BitReader<EVENTS_READY_A>;
+#[doc = "QSPI peripheral is ready. This event will be generated as a response to all QSPI tasks except DEACTIVATE.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum EVENTS_READY_A {
+    #[doc = "0: Event not generated"]
+    NOT_GENERATED = 0,
+    #[doc = "1: Event generated"]
+    GENERATED = 1,
+}
+impl From<EVENTS_READY_A> for bool {
+    #[inline(always)]
+    fn from(variant: EVENTS_READY_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl EVENTS_READY_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> EVENTS_READY_A {
+        match self.bits {
+            false => EVENTS_READY_A::NOT_GENERATED,
+            true => EVENTS_READY_A::GENERATED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `NOT_GENERATED`"]
+    #[inline(always)]
+    pub fn is_not_generated(&self) -> bool {
+        *self == EVENTS_READY_A::NOT_GENERATED
+    }
+    #[doc = "Checks if the value of the field is `GENERATED`"]
+    #[inline(always)]
+    pub fn is_generated(&self) -> bool {
+        *self == EVENTS_READY_A::GENERATED
+    }
+}
+#[doc = "Field `EVENTS_READY` writer - QSPI peripheral is ready. This event will be generated as a response to all QSPI tasks except DEACTIVATE."]
+pub type EVENTS_READY_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, EVENTS_READY_SPEC, EVENTS_READY_A, O>;
+impl<'a, const O: u8> EVENTS_READY_W<'a, O> {
+    #[doc = "Event not generated"]
+    #[inline(always)]
+    pub fn not_generated(self) -> &'a mut W {
+        self.variant(EVENTS_READY_A::NOT_GENERATED)
+    }
+    #[doc = "Event generated"]
+    #[inline(always)]
+    pub fn generated(self) -> &'a mut W {
+        self.variant(EVENTS_READY_A::GENERATED)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - QSPI peripheral is ready. This event will be generated as a response to all QSPI tasks except DEACTIVATE."]
+    #[inline(always)]
+    pub fn events_ready(&self) -> EVENTS_READY_R {
+        EVENTS_READY_R::new((self.bits & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - QSPI peripheral is ready. This event will be generated as a response to all QSPI tasks except DEACTIVATE."]
+    #[inline(always)]
+    pub fn events_ready(&mut self) -> EVENTS_READY_W<0> {
+        EVENTS_READY_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "QSPI peripheral is ready. This event will be generated as a response to all QSPI tasks except DEACTIVATE.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_ready](index.html) module"]
+pub struct EVENTS_READY_SPEC;
+impl crate::RegisterSpec for EVENTS_READY_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [events_ready::R](R) reader structure"]
+impl crate::Readable for EVENTS_READY_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [events_ready::W](W) writer structure"]
+impl crate::Writable for EVENTS_READY_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets EVENTS_READY to value 0"]
+impl crate::Resettable for EVENTS_READY_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf5340-app-pac/src/qspi_ns/ifconfig0.rs

@@ -0,0 +1,437 @@
+#[doc = "Register `IFCONFIG0` reader"]
+pub struct R(crate::R<IFCONFIG0_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<IFCONFIG0_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<IFCONFIG0_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<IFCONFIG0_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `IFCONFIG0` writer"]
+pub struct W(crate::W<IFCONFIG0_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<IFCONFIG0_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<IFCONFIG0_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<IFCONFIG0_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `READOC` reader - Configure number of data lines and opcode used for reading."]
+pub type READOC_R = crate::FieldReader<u8, READOC_A>;
+#[doc = "Configure number of data lines and opcode used for reading.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum READOC_A {
+    #[doc = "0: Single data line SPI. FAST_READ (opcode 0x0B)."]
+    FASTREAD = 0,
+    #[doc = "1: Dual data line SPI. READ2O (opcode 0x3B)."]
+    READ2O = 1,
+    #[doc = "2: Dual data line SPI. READ2IO (opcode 0xBB)."]
+    READ2IO = 2,
+    #[doc = "3: Quad data line SPI. READ4O (opcode 0x6B)."]
+    READ4O = 3,
+    #[doc = "4: Quad data line SPI. READ4IO (opcode 0xEB)."]
+    READ4IO = 4,
+}
+impl From<READOC_A> for u8 {
+    #[inline(always)]
+    fn from(variant: READOC_A) -> Self {
+        variant as _
+    }
+}
+impl READOC_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<READOC_A> {
+        match self.bits {
+            0 => Some(READOC_A::FASTREAD),
+            1 => Some(READOC_A::READ2O),
+            2 => Some(READOC_A::READ2IO),
+            3 => Some(READOC_A::READ4O),
+            4 => Some(READOC_A::READ4IO),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `FASTREAD`"]
+    #[inline(always)]
+    pub fn is_fastread(&self) -> bool {
+        *self == READOC_A::FASTREAD
+    }
+    #[doc = "Checks if the value of the field is `READ2O`"]
+    #[inline(always)]
+    pub fn is_read2o(&self) -> bool {
+        *self == READOC_A::READ2O
+    }
+    #[doc = "Checks if the value of the field is `READ2IO`"]
+    #[inline(always)]
+    pub fn is_read2io(&self) -> bool {
+        *self == READOC_A::READ2IO
+    }
+    #[doc = "Checks if the value of the field is `READ4O`"]
+    #[inline(always)]
+    pub fn is_read4o(&self) -> bool {
+        *self == READOC_A::READ4O
+    }
+    #[doc = "Checks if the value of the field is `READ4IO`"]
+    #[inline(always)]
+    pub fn is_read4io(&self) -> bool {
+        *self == READOC_A::READ4IO
+    }
+}
+#[doc = "Field `READOC` writer - Configure number of data lines and opcode used for reading."]
+pub type READOC_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u32, IFCONFIG0_SPEC, u8, READOC_A, 3, O>;
+impl<'a, const O: u8> READOC_W<'a, O> {
+    #[doc = "Single data line SPI. FAST_READ (opcode 0x0B)."]
+    #[inline(always)]
+    pub fn fastread(self) -> &'a mut W {
+        self.variant(READOC_A::FASTREAD)
+    }
+    #[doc = "Dual data line SPI. READ2O (opcode 0x3B)."]
+    #[inline(always)]
+    pub fn read2o(self) -> &'a mut W {
+        self.variant(READOC_A::READ2O)
+    }
+    #[doc = "Dual data line SPI. READ2IO (opcode 0xBB)."]
+    #[inline(always)]
+    pub fn read2io(self) -> &'a mut W {
+        self.variant(READOC_A::READ2IO)
+    }
+    #[doc = "Quad data line SPI. READ4O (opcode 0x6B)."]
+    #[inline(always)]
+    pub fn read4o(self) -> &'a mut W {
+        self.variant(READOC_A::READ4O)
+    }
+    #[doc = "Quad data line SPI. READ4IO (opcode 0xEB)."]
+    #[inline(always)]
+    pub fn read4io(self) -> &'a mut W {
+        self.variant(READOC_A::READ4IO)
+    }
+}
+#[doc = "Field `WRITEOC` reader - Configure number of data lines and opcode used for writing."]
+pub type WRITEOC_R = crate::FieldReader<u8, WRITEOC_A>;
+#[doc = "Configure number of data lines and opcode used for writing.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum WRITEOC_A {
+    #[doc = "0: Single data line SPI. PP (opcode 0x02)."]
+    PP = 0,
+    #[doc = "1: Dual data line SPI. PP2O (opcode 0xA2)."]
+    PP2O = 1,
+    #[doc = "2: Quad data line SPI. PP4O (opcode 0x32)."]
+    PP4O = 2,
+    #[doc = "3: Quad data line SPI. PP4IO (opcode 0x38)."]
+    PP4IO = 3,
+}
+impl From<WRITEOC_A> for u8 {
+    #[inline(always)]
+    fn from(variant: WRITEOC_A) -> Self {
+        variant as _
+    }
+}
+impl WRITEOC_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<WRITEOC_A> {
+        match self.bits {
+            0 => Some(WRITEOC_A::PP),
+            1 => Some(WRITEOC_A::PP2O),
+            2 => Some(WRITEOC_A::PP4O),
+            3 => Some(WRITEOC_A::PP4IO),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `PP`"]
+    #[inline(always)]
+    pub fn is_pp(&self) -> bool {
+        *self == WRITEOC_A::PP
+    }
+    #[doc = "Checks if the value of the field is `PP2O`"]
+    #[inline(always)]
+    pub fn is_pp2o(&self) -> bool {
+        *self == WRITEOC_A::PP2O
+    }
+    #[doc = "Checks if the value of the field is `PP4O`"]
+    #[inline(always)]
+    pub fn is_pp4o(&self) -> bool {
+        *self == WRITEOC_A::PP4O
+    }
+    #[doc = "Checks if the value of the field is `PP4IO`"]
+    #[inline(always)]
+    pub fn is_pp4io(&self) -> bool {
+        *self == WRITEOC_A::PP4IO
+    }
+}
+#[doc = "Field `WRITEOC` writer - Configure number of data lines and opcode used for writing."]
+pub type WRITEOC_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u32, IFCONFIG0_SPEC, u8, WRITEOC_A, 3, O>;
+impl<'a, const O: u8> WRITEOC_W<'a, O> {
+    #[doc = "Single data line SPI. PP (opcode 0x02)."]
+    #[inline(always)]
+    pub fn pp(self) -> &'a mut W {
+        self.variant(WRITEOC_A::PP)
+    }
+    #[doc = "Dual data line SPI. PP2O (opcode 0xA2)."]
+    #[inline(always)]
+    pub fn pp2o(self) -> &'a mut W {
+        self.variant(WRITEOC_A::PP2O)
+    }
+    #[doc = "Quad data line SPI. PP4O (opcode 0x32)."]
+    #[inline(always)]
+    pub fn pp4o(self) -> &'a mut W {
+        self.variant(WRITEOC_A::PP4O)
+    }
+    #[doc = "Quad data line SPI. PP4IO (opcode 0x38)."]
+    #[inline(always)]
+    pub fn pp4io(self) -> &'a mut W {
+        self.variant(WRITEOC_A::PP4IO)
+    }
+}
+#[doc = "Field `ADDRMODE` reader - Addressing mode."]
+pub type ADDRMODE_R = crate::BitReader<ADDRMODE_A>;
+#[doc = "Addressing mode.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADDRMODE_A {
+    #[doc = "0: 24-bit addressing."]
+    _24BIT = 0,
+    #[doc = "1: 32-bit addressing."]
+    _32BIT = 1,
+}
+impl From<ADDRMODE_A> for bool {
+    #[inline(always)]
+    fn from(variant: ADDRMODE_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl ADDRMODE_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> ADDRMODE_A {
+        match self.bits {
+            false => ADDRMODE_A::_24BIT,
+            true => ADDRMODE_A::_32BIT,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_24BIT`"]
+    #[inline(always)]
+    pub fn is_24bit(&self) -> bool {
+        *self == ADDRMODE_A::_24BIT
+    }
+    #[doc = "Checks if the value of the field is `_32BIT`"]
+    #[inline(always)]
+    pub fn is_32bit(&self) -> bool {
+        *self == ADDRMODE_A::_32BIT
+    }
+}
+#[doc = "Field `ADDRMODE` writer - Addressing mode."]
+pub type ADDRMODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IFCONFIG0_SPEC, ADDRMODE_A, O>;
+impl<'a, const O: u8> ADDRMODE_W<'a, O> {
+    #[doc = "24-bit addressing."]
+    #[inline(always)]
+    pub fn _24bit(self) -> &'a mut W {
+        self.variant(ADDRMODE_A::_24BIT)
+    }
+    #[doc = "32-bit addressing."]
+    #[inline(always)]
+    pub fn _32bit(self) -> &'a mut W {
+        self.variant(ADDRMODE_A::_32BIT)
+    }
+}
+#[doc = "Field `DPMENABLE` reader - Enable deep power-down mode (DPM) feature."]
+pub type DPMENABLE_R = crate::BitReader<DPMENABLE_A>;
+#[doc = "Enable deep power-down mode (DPM) feature.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DPMENABLE_A {
+    #[doc = "0: Disable DPM feature."]
+    DISABLE = 0,
+    #[doc = "1: Enable DPM feature."]
+    ENABLE = 1,
+}
+impl From<DPMENABLE_A> for bool {
+    #[inline(always)]
+    fn from(variant: DPMENABLE_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl DPMENABLE_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> DPMENABLE_A {
+        match self.bits {
+            false => DPMENABLE_A::DISABLE,
+            true => DPMENABLE_A::ENABLE,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLE`"]
+    #[inline(always)]
+    pub fn is_disable(&self) -> bool {
+        *self == DPMENABLE_A::DISABLE
+    }
+    #[doc = "Checks if the value of the field is `ENABLE`"]
+    #[inline(always)]
+    pub fn is_enable(&self) -> bool {
+        *self == DPMENABLE_A::ENABLE
+    }
+}
+#[doc = "Field `DPMENABLE` writer - Enable deep power-down mode (DPM) feature."]
+pub type DPMENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IFCONFIG0_SPEC, DPMENABLE_A, O>;
+impl<'a, const O: u8> DPMENABLE_W<'a, O> {
+    #[doc = "Disable DPM feature."]
+    #[inline(always)]
+    pub fn disable(self) -> &'a mut W {
+        self.variant(DPMENABLE_A::DISABLE)
+    }
+    #[doc = "Enable DPM feature."]
+    #[inline(always)]
+    pub fn enable(self) -> &'a mut W {
+        self.variant(DPMENABLE_A::ENABLE)
+    }
+}
+#[doc = "Field `PPSIZE` reader - Page size for commands PP, PP2O, PP4O and PP4IO."]
+pub type PPSIZE_R = crate::BitReader<PPSIZE_A>;
+#[doc = "Page size for commands PP, PP2O, PP4O and PP4IO.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum PPSIZE_A {
+    #[doc = "0: 256 bytes."]
+    _256BYTES = 0,
+    #[doc = "1: 512 bytes."]
+    _512BYTES = 1,
+}
+impl From<PPSIZE_A> for bool {
+    #[inline(always)]
+    fn from(variant: PPSIZE_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl PPSIZE_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> PPSIZE_A {
+        match self.bits {
+            false => PPSIZE_A::_256BYTES,
+            true => PPSIZE_A::_512BYTES,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_256BYTES`"]
+    #[inline(always)]
+    pub fn is_256bytes(&self) -> bool {
+        *self == PPSIZE_A::_256BYTES
+    }
+    #[doc = "Checks if the value of the field is `_512BYTES`"]
+    #[inline(always)]
+    pub fn is_512bytes(&self) -> bool {
+        *self == PPSIZE_A::_512BYTES
+    }
+}
+#[doc = "Field `PPSIZE` writer - Page size for commands PP, PP2O, PP4O and PP4IO."]
+pub type PPSIZE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IFCONFIG0_SPEC, PPSIZE_A, O>;
+impl<'a, const O: u8> PPSIZE_W<'a, O> {
+    #[doc = "256 bytes."]
+    #[inline(always)]
+    pub fn _256bytes(self) -> &'a mut W {
+        self.variant(PPSIZE_A::_256BYTES)
+    }
+    #[doc = "512 bytes."]
+    #[inline(always)]
+    pub fn _512bytes(self) -> &'a mut W {
+        self.variant(PPSIZE_A::_512BYTES)
+    }
+}
+impl R {
+    #[doc = "Bits 0:2 - Configure number of data lines and opcode used for reading."]
+    #[inline(always)]
+    pub fn readoc(&self) -> READOC_R {
+        READOC_R::new((self.bits & 7) as u8)
+    }
+    #[doc = "Bits 3:5 - Configure number of data lines and opcode used for writing."]
+    #[inline(always)]
+    pub fn writeoc(&self) -> WRITEOC_R {
+        WRITEOC_R::new(((self.bits >> 3) & 7) as u8)
+    }
+    #[doc = "Bit 6 - Addressing mode."]
+    #[inline(always)]
+    pub fn addrmode(&self) -> ADDRMODE_R {
+        ADDRMODE_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - Enable deep power-down mode (DPM) feature."]
+    #[inline(always)]
+    pub fn dpmenable(&self) -> DPMENABLE_R {
+        DPMENABLE_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 12 - Page size for commands PP, PP2O, PP4O and PP4IO."]
+    #[inline(always)]
+    pub fn ppsize(&self) -> PPSIZE_R {
+        PPSIZE_R::new(((self.bits >> 12) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:2 - Configure number of data lines and opcode used for reading."]
+    #[inline(always)]
+    pub fn readoc(&mut self) -> READOC_W<0> {
+        READOC_W::new(self)
+    }
+    #[doc = "Bits 3:5 - Configure number of data lines and opcode used for writing."]
+    #[inline(always)]
+    pub fn writeoc(&mut self) -> WRITEOC_W<3> {
+        WRITEOC_W::new(self)
+    }
+    #[doc = "Bit 6 - Addressing mode."]
+    #[inline(always)]
+    pub fn addrmode(&mut self) -> ADDRMODE_W<6> {
+        ADDRMODE_W::new(self)
+    }
+    #[doc = "Bit 7 - Enable deep power-down mode (DPM) feature."]
+    #[inline(always)]
+    pub fn dpmenable(&mut self) -> DPMENABLE_W<7> {
+        DPMENABLE_W::new(self)
+    }
+    #[doc = "Bit 12 - Page size for commands PP, PP2O, PP4O and PP4IO."]
+    #[inline(always)]
+    pub fn ppsize(&mut self) -> PPSIZE_W<12> {
+        PPSIZE_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Interface configuration.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ifconfig0](index.html) module"]
+pub struct IFCONFIG0_SPEC;
+impl crate::RegisterSpec for IFCONFIG0_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [ifconfig0::R](R) reader structure"]
+impl crate::Readable for IFCONFIG0_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [ifconfig0::W](W) writer structure"]
+impl crate::Writable for IFCONFIG0_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets IFCONFIG0 to value 0"]
+impl crate::Resettable for IFCONFIG0_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf5340-app-pac/src/qspi_ns/ifconfig1.rs

@@ -0,0 +1,214 @@
+#[doc = "Register `IFCONFIG1` reader"]
+pub struct R(crate::R<IFCONFIG1_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<IFCONFIG1_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<IFCONFIG1_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<IFCONFIG1_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `IFCONFIG1` writer"]
+pub struct W(crate::W<IFCONFIG1_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<IFCONFIG1_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<IFCONFIG1_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<IFCONFIG1_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `SCKDELAY` reader - Minimum amount of time that the CSN pin must stay high before it can go low again. Value is specified in number of 16 MHz periods (62.5 ns)."]
+pub type SCKDELAY_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `SCKDELAY` writer - Minimum amount of time that the CSN pin must stay high before it can go low again. Value is specified in number of 16 MHz periods (62.5 ns)."]
+pub type SCKDELAY_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IFCONFIG1_SPEC, u8, u8, 8, O>;
+#[doc = "Field `DPMEN` reader - Enter/exit deep power-down mode (DPM) for external flash memory."]
+pub type DPMEN_R = crate::BitReader<DPMEN_A>;
+#[doc = "Enter/exit deep power-down mode (DPM) for external flash memory.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DPMEN_A {
+    #[doc = "0: Exit DPM."]
+    EXIT = 0,
+    #[doc = "1: Enter DPM."]
+    ENTER = 1,
+}
+impl From<DPMEN_A> for bool {
+    #[inline(always)]
+    fn from(variant: DPMEN_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl DPMEN_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> DPMEN_A {
+        match self.bits {
+            false => DPMEN_A::EXIT,
+            true => DPMEN_A::ENTER,
+        }
+    }
+    #[doc = "Checks if the value of the field is `EXIT`"]
+    #[inline(always)]
+    pub fn is_exit(&self) -> bool {
+        *self == DPMEN_A::EXIT
+    }
+    #[doc = "Checks if the value of the field is `ENTER`"]
+    #[inline(always)]
+    pub fn is_enter(&self) -> bool {
+        *self == DPMEN_A::ENTER
+    }
+}
+#[doc = "Field `DPMEN` writer - Enter/exit deep power-down mode (DPM) for external flash memory."]
+pub type DPMEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, IFCONFIG1_SPEC, DPMEN_A, O>;
+impl<'a, const O: u8> DPMEN_W<'a, O> {
+    #[doc = "Exit DPM."]
+    #[inline(always)]
+    pub fn exit(self) -> &'a mut W {
+        self.variant(DPMEN_A::EXIT)
+    }
+    #[doc = "Enter DPM."]
+    #[inline(always)]
+    pub fn enter(self) -> &'a mut W {
+        self.variant(DPMEN_A::ENTER)
+    }
+}
+#[doc = "Field `SPIMODE` reader - Select SPI mode."]
+pub type SPIMODE_R = crate::BitReader<SPIMODE_A>;
+#[doc = "Select SPI mode.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SPIMODE_A {
+    #[doc = "0: Mode 0: Data are captured on the clock rising edge and data is output on a falling edge. Base level of clock is 0 (CPOL=0, CPHA=0)."]
+    MODE0 = 0,
+    #[doc = "1: Mode 3: Data are captured on the clock rising edge and data is output on a falling edge. Base level of clock is 1 (CPOL=1, CPHA=1)."]
+    MODE3 = 1,
+}
+impl From<SPIMODE_A> for bool {
+    #[inline(always)]
+    fn from(variant: SPIMODE_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl SPIMODE_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> SPIMODE_A {
+        match self.bits {
+            false => SPIMODE_A::MODE0,
+            true => SPIMODE_A::MODE3,
+        }
+    }
+    #[doc = "Checks if the value of the field is `MODE0`"]
+    #[inline(always)]
+    pub fn is_mode0(&self) -> bool {
+        *self == SPIMODE_A::MODE0
+    }
+    #[doc = "Checks if the value of the field is `MODE3`"]
+    #[inline(always)]
+    pub fn is_mode3(&self) -> bool {
+        *self == SPIMODE_A::MODE3
+    }
+}
+#[doc = "Field `SPIMODE` writer - Select SPI mode."]
+pub type SPIMODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IFCONFIG1_SPEC, SPIMODE_A, O>;
+impl<'a, const O: u8> SPIMODE_W<'a, O> {
+    #[doc = "Mode 0: Data are captured on the clock rising edge and data is output on a falling edge. Base level of clock is 0 (CPOL=0, CPHA=0)."]
+    #[inline(always)]
+    pub fn mode0(self) -> &'a mut W {
+        self.variant(SPIMODE_A::MODE0)
+    }
+    #[doc = "Mode 3: Data are captured on the clock rising edge and data is output on a falling edge. Base level of clock is 1 (CPOL=1, CPHA=1)."]
+    #[inline(always)]
+    pub fn mode3(self) -> &'a mut W {
+        self.variant(SPIMODE_A::MODE3)
+    }
+}
+#[doc = "Field `SCKFREQ` reader - SCK frequency is derived from PCLK192M with SCK frequency = PCLK192M / (2*(SCKFREQ + 1))."]
+pub type SCKFREQ_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `SCKFREQ` writer - SCK frequency is derived from PCLK192M with SCK frequency = PCLK192M / (2*(SCKFREQ + 1))."]
+pub type SCKFREQ_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IFCONFIG1_SPEC, u8, u8, 4, O>;
+impl R {
+    #[doc = "Bits 0:7 - Minimum amount of time that the CSN pin must stay high before it can go low again. Value is specified in number of 16 MHz periods (62.5 ns)."]
+    #[inline(always)]
+    pub fn sckdelay(&self) -> SCKDELAY_R {
+        SCKDELAY_R::new((self.bits & 0xff) as u8)
+    }
+    #[doc = "Bit 24 - Enter/exit deep power-down mode (DPM) for external flash memory."]
+    #[inline(always)]
+    pub fn dpmen(&self) -> DPMEN_R {
+        DPMEN_R::new(((self.bits >> 24) & 1) != 0)
+    }
+    #[doc = "Bit 25 - Select SPI mode."]
+    #[inline(always)]
+    pub fn spimode(&self) -> SPIMODE_R {
+        SPIMODE_R::new(((self.bits >> 25) & 1) != 0)
+    }
+    #[doc = "Bits 28:31 - SCK frequency is derived from PCLK192M with SCK frequency = PCLK192M / (2*(SCKFREQ + 1))."]
+    #[inline(always)]
+    pub fn sckfreq(&self) -> SCKFREQ_R {
+        SCKFREQ_R::new(((self.bits >> 28) & 0x0f) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - Minimum amount of time that the CSN pin must stay high before it can go low again. Value is specified in number of 16 MHz periods (62.5 ns)."]
+    #[inline(always)]
+    pub fn sckdelay(&mut self) -> SCKDELAY_W<0> {
+        SCKDELAY_W::new(self)
+    }
+    #[doc = "Bit 24 - Enter/exit deep power-down mode (DPM) for external flash memory."]
+    #[inline(always)]
+    pub fn dpmen(&mut self) -> DPMEN_W<24> {
+        DPMEN_W::new(self)
+    }
+    #[doc = "Bit 25 - Select SPI mode."]
+    #[inline(always)]
+    pub fn spimode(&mut self) -> SPIMODE_W<25> {
+        SPIMODE_W::new(self)
+    }
+    #[doc = "Bits 28:31 - SCK frequency is derived from PCLK192M with SCK frequency = PCLK192M / (2*(SCKFREQ + 1))."]
+    #[inline(always)]
+    pub fn sckfreq(&mut self) -> SCKFREQ_W<28> {
+        SCKFREQ_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Interface configuration.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ifconfig1](index.html) module"]
+pub struct IFCONFIG1_SPEC;
+impl crate::RegisterSpec for IFCONFIG1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [ifconfig1::R](R) reader structure"]
+impl crate::Readable for IFCONFIG1_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [ifconfig1::W](W) writer structure"]
+impl crate::Writable for IFCONFIG1_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets IFCONFIG1 to value 0x0004_0480"]
+impl crate::Resettable for IFCONFIG1_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0x0004_0480
+    }
+}

vendor/nrf5340-app-pac/src/qspi_ns/iftiming.rs

@@ -0,0 +1,80 @@
+#[doc = "Register `IFTIMING` reader"]
+pub struct R(crate::R<IFTIMING_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<IFTIMING_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<IFTIMING_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<IFTIMING_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `IFTIMING` writer"]
+pub struct W(crate::W<IFTIMING_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<IFTIMING_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<IFTIMING_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<IFTIMING_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `RXDELAY` reader - Timing related to sampling of the input serial data. The value of RXDELAY specifies the number of prescaled 192 MHz cycles delay from the the rising edge of the SPI Clock (SCK) until the input serial data is sampled. For example, if RXDELAY is set to 0, the input serial data is sampled on the rising edge of SCK."]
+pub type RXDELAY_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `RXDELAY` writer - Timing related to sampling of the input serial data. The value of RXDELAY specifies the number of prescaled 192 MHz cycles delay from the the rising edge of the SPI Clock (SCK) until the input serial data is sampled. For example, if RXDELAY is set to 0, the input serial data is sampled on the rising edge of SCK."]
+pub type RXDELAY_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IFTIMING_SPEC, u8, u8, 3, O>;
+impl R {
+    #[doc = "Bits 8:10 - Timing related to sampling of the input serial data. The value of RXDELAY specifies the number of prescaled 192 MHz cycles delay from the the rising edge of the SPI Clock (SCK) until the input serial data is sampled. For example, if RXDELAY is set to 0, the input serial data is sampled on the rising edge of SCK."]
+    #[inline(always)]
+    pub fn rxdelay(&self) -> RXDELAY_R {
+        RXDELAY_R::new(((self.bits >> 8) & 7) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 8:10 - Timing related to sampling of the input serial data. The value of RXDELAY specifies the number of prescaled 192 MHz cycles delay from the the rising edge of the SPI Clock (SCK) until the input serial data is sampled. For example, if RXDELAY is set to 0, the input serial data is sampled on the rising edge of SCK."]
+    #[inline(always)]
+    pub fn rxdelay(&mut self) -> RXDELAY_W<8> {
+        RXDELAY_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "SPI interface timing.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [iftiming](index.html) module"]
+pub struct IFTIMING_SPEC;
+impl crate::RegisterSpec for IFTIMING_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [iftiming::R](R) reader structure"]
+impl crate::Readable for IFTIMING_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [iftiming::W](W) writer structure"]
+impl crate::Writable for IFTIMING_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets IFTIMING to value 0x0200"]
+impl crate::Resettable for IFTIMING_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0x0200
+    }
+}

vendor/nrf5340-app-pac/src/qspi_ns/inten.rs

@@ -0,0 +1,126 @@
+#[doc = "Register `INTEN` reader"]
+pub struct R(crate::R<INTEN_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<INTEN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<INTEN_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<INTEN_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `INTEN` writer"]
+pub struct W(crate::W<INTEN_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<INTEN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<INTEN_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<INTEN_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `READY` reader - Enable or disable interrupt for event READY"]
+pub type READY_R = crate::BitReader<READY_A>;
+#[doc = "Enable or disable interrupt for event READY\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum READY_A {
+    #[doc = "0: Disable"]
+    DISABLED = 0,
+    #[doc = "1: Enable"]
+    ENABLED = 1,
+}
+impl From<READY_A> for bool {
+    #[inline(always)]
+    fn from(variant: READY_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl READY_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> READY_A {
+        match self.bits {
+            false => READY_A::DISABLED,
+            true => READY_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == READY_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == READY_A::ENABLED
+    }
+}
+#[doc = "Field `READY` writer - Enable or disable interrupt for event READY"]
+pub type READY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, READY_A, O>;
+impl<'a, const O: u8> READY_W<'a, O> {
+    #[doc = "Disable"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(READY_A::DISABLED)
+    }
+    #[doc = "Enable"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(READY_A::ENABLED)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Enable or disable interrupt for event READY"]
+    #[inline(always)]
+    pub fn ready(&self) -> READY_R {
+        READY_R::new((self.bits & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Enable or disable interrupt for event READY"]
+    #[inline(always)]
+    pub fn ready(&mut self) -> READY_W<0> {
+        READY_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Enable or disable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [inten](index.html) module"]
+pub struct INTEN_SPEC;
+impl crate::RegisterSpec for INTEN_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [inten::R](R) reader structure"]
+impl crate::Readable for INTEN_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [inten::W](W) writer structure"]
+impl crate::Writable for INTEN_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets INTEN to value 0"]
+impl crate::Resettable for INTEN_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf5340-app-pac/src/qspi_ns/intenclr.rs

@@ -0,0 +1,133 @@
+#[doc = "Register `INTENCLR` reader"]
+pub struct R(crate::R<INTENCLR_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<INTENCLR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<INTENCLR_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<INTENCLR_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `INTENCLR` writer"]
+pub struct W(crate::W<INTENCLR_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<INTENCLR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<INTENCLR_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<INTENCLR_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `READY` reader - Write '1' to disable interrupt for event READY"]
+pub type READY_R = crate::BitReader<READY_A>;
+#[doc = "Write '1' to disable interrupt for event READY\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum READY_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<READY_A> for bool {
+    #[inline(always)]
+    fn from(variant: READY_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl READY_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> READY_A {
+        match self.bits {
+            false => READY_A::DISABLED,
+            true => READY_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == READY_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == READY_A::ENABLED
+    }
+}
+#[doc = "Write '1' to disable interrupt for event READY\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum READY_AW {
+    #[doc = "1: Disable"]
+    CLEAR = 1,
+}
+impl From<READY_AW> for bool {
+    #[inline(always)]
+    fn from(variant: READY_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `READY` writer - Write '1' to disable interrupt for event READY"]
+pub type READY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, READY_AW, O>;
+impl<'a, const O: u8> READY_W<'a, O> {
+    #[doc = "Disable"]
+    #[inline(always)]
+    pub fn clear(self) -> &'a mut W {
+        self.variant(READY_AW::CLEAR)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Write '1' to disable interrupt for event READY"]
+    #[inline(always)]
+    pub fn ready(&self) -> READY_R {
+        READY_R::new((self.bits & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Write '1' to disable interrupt for event READY"]
+    #[inline(always)]
+    pub fn ready(&mut self) -> READY_W<0> {
+        READY_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Disable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"]
+pub struct INTENCLR_SPEC;
+impl crate::RegisterSpec for INTENCLR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [intenclr::R](R) reader structure"]
+impl crate::Readable for INTENCLR_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"]
+impl crate::Writable for INTENCLR_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets INTENCLR to value 0"]
+impl crate::Resettable for INTENCLR_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf5340-app-pac/src/qspi_ns/intenset.rs

@@ -0,0 +1,133 @@
+#[doc = "Register `INTENSET` reader"]
+pub struct R(crate::R<INTENSET_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<INTENSET_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<INTENSET_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<INTENSET_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `INTENSET` writer"]
+pub struct W(crate::W<INTENSET_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<INTENSET_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<INTENSET_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<INTENSET_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `READY` reader - Write '1' to enable interrupt for event READY"]
+pub type READY_R = crate::BitReader<READY_A>;
+#[doc = "Write '1' to enable interrupt for event READY\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum READY_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<READY_A> for bool {
+    #[inline(always)]
+    fn from(variant: READY_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl READY_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> READY_A {
+        match self.bits {
+            false => READY_A::DISABLED,
+            true => READY_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == READY_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == READY_A::ENABLED
+    }
+}
+#[doc = "Write '1' to enable interrupt for event READY\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum READY_AW {
+    #[doc = "1: Enable"]
+    SET = 1,
+}
+impl From<READY_AW> for bool {
+    #[inline(always)]
+    fn from(variant: READY_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `READY` writer - Write '1' to enable interrupt for event READY"]
+pub type READY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, READY_AW, O>;
+impl<'a, const O: u8> READY_W<'a, O> {
+    #[doc = "Enable"]
+    #[inline(always)]
+    pub fn set(self) -> &'a mut W {
+        self.variant(READY_AW::SET)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Write '1' to enable interrupt for event READY"]
+    #[inline(always)]
+    pub fn ready(&self) -> READY_R {
+        READY_R::new((self.bits & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Write '1' to enable interrupt for event READY"]
+    #[inline(always)]
+    pub fn ready(&mut self) -> READY_W<0> {
+        READY_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Enable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"]
+pub struct INTENSET_SPEC;
+impl crate::RegisterSpec for INTENSET_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [intenset::R](R) reader structure"]
+impl crate::Readable for INTENSET_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"]
+impl crate::Writable for INTENSET_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets INTENSET to value 0"]
+impl crate::Resettable for INTENSET_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf5340-app-pac/src/qspi_ns/psel.rs

@@ -0,0 +1,41 @@
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct PSEL {
+    #[doc = "0x00 - Pin select for serial clock SCK"]
+    pub sck: SCK,
+    #[doc = "0x04 - Pin select for chip select signal CSN."]
+    pub csn: CSN,
+    _reserved2: [u8; 0x04],
+    #[doc = "0x0c - Pin select for serial data MOSI/IO0."]
+    pub io0: IO0,
+    #[doc = "0x10 - Pin select for serial data MISO/IO1."]
+    pub io1: IO1,
+    #[doc = "0x14 - Pin select for serial data WP/IO2."]
+    pub io2: IO2,
+    #[doc = "0x18 - Pin select for serial data HOLD/IO3."]
+    pub io3: IO3,
+}
+#[doc = "SCK (rw) register accessor: an alias for `Reg<SCK_SPEC>`"]
+pub type SCK = crate::Reg<sck::SCK_SPEC>;
+#[doc = "Pin select for serial clock SCK"]
+pub mod sck;
+#[doc = "CSN (rw) register accessor: an alias for `Reg<CSN_SPEC>`"]
+pub type CSN = crate::Reg<csn::CSN_SPEC>;
+#[doc = "Pin select for chip select signal CSN."]
+pub mod csn;
+#[doc = "IO0 (rw) register accessor: an alias for `Reg<IO0_SPEC>`"]
+pub type IO0 = crate::Reg<io0::IO0_SPEC>;
+#[doc = "Pin select for serial data MOSI/IO0."]
+pub mod io0;
+#[doc = "IO1 (rw) register accessor: an alias for `Reg<IO1_SPEC>`"]
+pub type IO1 = crate::Reg<io1::IO1_SPEC>;
+#[doc = "Pin select for serial data MISO/IO1."]
+pub mod io1;
+#[doc = "IO2 (rw) register accessor: an alias for `Reg<IO2_SPEC>`"]
+pub type IO2 = crate::Reg<io2::IO2_SPEC>;
+#[doc = "Pin select for serial data WP/IO2."]
+pub mod io2;
+#[doc = "IO3 (rw) register accessor: an alias for `Reg<IO3_SPEC>`"]
+pub type IO3 = crate::Reg<io3::IO3_SPEC>;
+#[doc = "Pin select for serial data HOLD/IO3."]
+pub mod io3;

vendor/nrf5340-app-pac/src/qspi_ns/psel/csn.rs

@@ -0,0 +1,154 @@
+#[doc = "Register `CSN` reader"]
+pub struct R(crate::R<CSN_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<CSN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<CSN_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<CSN_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `CSN` writer"]
+pub struct W(crate::W<CSN_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<CSN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<CSN_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<CSN_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `PIN` reader - Pin number"]
+pub type PIN_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `PIN` writer - Pin number"]
+pub type PIN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CSN_SPEC, u8, u8, 5, O>;
+#[doc = "Field `PORT` reader - Port number"]
+pub type PORT_R = crate::BitReader<bool>;
+#[doc = "Field `PORT` writer - Port number"]
+pub type PORT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CSN_SPEC, bool, O>;
+#[doc = "Field `CONNECT` reader - Connection"]
+pub type CONNECT_R = crate::BitReader<CONNECT_A>;
+#[doc = "Connection\n\nValue on reset: 1"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CONNECT_A {
+    #[doc = "1: Disconnect"]
+    DISCONNECTED = 1,
+    #[doc = "0: Connect"]
+    CONNECTED = 0,
+}
+impl From<CONNECT_A> for bool {
+    #[inline(always)]
+    fn from(variant: CONNECT_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl CONNECT_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> CONNECT_A {
+        match self.bits {
+            true => CONNECT_A::DISCONNECTED,
+            false => CONNECT_A::CONNECTED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISCONNECTED`"]
+    #[inline(always)]
+    pub fn is_disconnected(&self) -> bool {
+        *self == CONNECT_A::DISCONNECTED
+    }
+    #[doc = "Checks if the value of the field is `CONNECTED`"]
+    #[inline(always)]
+    pub fn is_connected(&self) -> bool {
+        *self == CONNECT_A::CONNECTED
+    }
+}
+#[doc = "Field `CONNECT` writer - Connection"]
+pub type CONNECT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CSN_SPEC, CONNECT_A, O>;
+impl<'a, const O: u8> CONNECT_W<'a, O> {
+    #[doc = "Disconnect"]
+    #[inline(always)]
+    pub fn disconnected(self) -> &'a mut W {
+        self.variant(CONNECT_A::DISCONNECTED)
+    }
+    #[doc = "Connect"]
+    #[inline(always)]
+    pub fn connected(self) -> &'a mut W {
+        self.variant(CONNECT_A::CONNECTED)
+    }
+}
+impl R {
+    #[doc = "Bits 0:4 - Pin number"]
+    #[inline(always)]
+    pub fn pin(&self) -> PIN_R {
+        PIN_R::new((self.bits & 0x1f) as u8)
+    }
+    #[doc = "Bit 5 - Port number"]
+    #[inline(always)]
+    pub fn port(&self) -> PORT_R {
+        PORT_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 31 - Connection"]
+    #[inline(always)]
+    pub fn connect(&self) -> CONNECT_R {
+        CONNECT_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:4 - Pin number"]
+    #[inline(always)]
+    pub fn pin(&mut self) -> PIN_W<0> {
+        PIN_W::new(self)
+    }
+    #[doc = "Bit 5 - Port number"]
+    #[inline(always)]
+    pub fn port(&mut self) -> PORT_W<5> {
+        PORT_W::new(self)
+    }
+    #[doc = "Bit 31 - Connection"]
+    #[inline(always)]
+    pub fn connect(&mut self) -> CONNECT_W<31> {
+        CONNECT_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Pin select for chip select signal CSN.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [csn](index.html) module"]
+pub struct CSN_SPEC;
+impl crate::RegisterSpec for CSN_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [csn::R](R) reader structure"]
+impl crate::Readable for CSN_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [csn::W](W) writer structure"]
+impl crate::Writable for CSN_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets CSN to value 0xffff_ffff"]
+impl crate::Resettable for CSN_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0xffff_ffff
+    }
+}

vendor/nrf5340-app-pac/src/qspi_ns/psel/io0.rs

@@ -0,0 +1,154 @@
+#[doc = "Register `IO0` reader"]
+pub struct R(crate::R<IO0_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<IO0_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<IO0_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<IO0_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `IO0` writer"]
+pub struct W(crate::W<IO0_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<IO0_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<IO0_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<IO0_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `PIN` reader - Pin number"]
+pub type PIN_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `PIN` writer - Pin number"]
+pub type PIN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IO0_SPEC, u8, u8, 5, O>;
+#[doc = "Field `PORT` reader - Port number"]
+pub type PORT_R = crate::BitReader<bool>;
+#[doc = "Field `PORT` writer - Port number"]
+pub type PORT_W<'a, const O: u8> = crate::BitWriter<'a, u32, IO0_SPEC, bool, O>;
+#[doc = "Field `CONNECT` reader - Connection"]
+pub type CONNECT_R = crate::BitReader<CONNECT_A>;
+#[doc = "Connection\n\nValue on reset: 1"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CONNECT_A {
+    #[doc = "1: Disconnect"]
+    DISCONNECTED = 1,
+    #[doc = "0: Connect"]
+    CONNECTED = 0,
+}
+impl From<CONNECT_A> for bool {
+    #[inline(always)]
+    fn from(variant: CONNECT_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl CONNECT_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> CONNECT_A {
+        match self.bits {
+            true => CONNECT_A::DISCONNECTED,
+            false => CONNECT_A::CONNECTED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISCONNECTED`"]
+    #[inline(always)]
+    pub fn is_disconnected(&self) -> bool {
+        *self == CONNECT_A::DISCONNECTED
+    }
+    #[doc = "Checks if the value of the field is `CONNECTED`"]
+    #[inline(always)]
+    pub fn is_connected(&self) -> bool {
+        *self == CONNECT_A::CONNECTED
+    }
+}
+#[doc = "Field `CONNECT` writer - Connection"]
+pub type CONNECT_W<'a, const O: u8> = crate::BitWriter<'a, u32, IO0_SPEC, CONNECT_A, O>;
+impl<'a, const O: u8> CONNECT_W<'a, O> {
+    #[doc = "Disconnect"]
+    #[inline(always)]
+    pub fn disconnected(self) -> &'a mut W {
+        self.variant(CONNECT_A::DISCONNECTED)
+    }
+    #[doc = "Connect"]
+    #[inline(always)]
+    pub fn connected(self) -> &'a mut W {
+        self.variant(CONNECT_A::CONNECTED)
+    }
+}
+impl R {
+    #[doc = "Bits 0:4 - Pin number"]
+    #[inline(always)]
+    pub fn pin(&self) -> PIN_R {
+        PIN_R::new((self.bits & 0x1f) as u8)
+    }
+    #[doc = "Bit 5 - Port number"]
+    #[inline(always)]
+    pub fn port(&self) -> PORT_R {
+        PORT_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 31 - Connection"]
+    #[inline(always)]
+    pub fn connect(&self) -> CONNECT_R {
+        CONNECT_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:4 - Pin number"]
+    #[inline(always)]
+    pub fn pin(&mut self) -> PIN_W<0> {
+        PIN_W::new(self)
+    }
+    #[doc = "Bit 5 - Port number"]
+    #[inline(always)]
+    pub fn port(&mut self) -> PORT_W<5> {
+        PORT_W::new(self)
+    }
+    #[doc = "Bit 31 - Connection"]
+    #[inline(always)]
+    pub fn connect(&mut self) -> CONNECT_W<31> {
+        CONNECT_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Pin select for serial data MOSI/IO0.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [io0](index.html) module"]
+pub struct IO0_SPEC;
+impl crate::RegisterSpec for IO0_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [io0::R](R) reader structure"]
+impl crate::Readable for IO0_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [io0::W](W) writer structure"]
+impl crate::Writable for IO0_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets IO0 to value 0xffff_ffff"]
+impl crate::Resettable for IO0_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0xffff_ffff
+    }
+}

vendor/nrf5340-app-pac/src/qspi_ns/psel/io1.rs

@@ -0,0 +1,154 @@
+#[doc = "Register `IO1` reader"]
+pub struct R(crate::R<IO1_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<IO1_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<IO1_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<IO1_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `IO1` writer"]
+pub struct W(crate::W<IO1_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<IO1_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<IO1_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<IO1_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `PIN` reader - Pin number"]
+pub type PIN_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `PIN` writer - Pin number"]
+pub type PIN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IO1_SPEC, u8, u8, 5, O>;
+#[doc = "Field `PORT` reader - Port number"]
+pub type PORT_R = crate::BitReader<bool>;
+#[doc = "Field `PORT` writer - Port number"]
+pub type PORT_W<'a, const O: u8> = crate::BitWriter<'a, u32, IO1_SPEC, bool, O>;
+#[doc = "Field `CONNECT` reader - Connection"]
+pub type CONNECT_R = crate::BitReader<CONNECT_A>;
+#[doc = "Connection\n\nValue on reset: 1"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CONNECT_A {
+    #[doc = "1: Disconnect"]
+    DISCONNECTED = 1,
+    #[doc = "0: Connect"]
+    CONNECTED = 0,
+}
+impl From<CONNECT_A> for bool {
+    #[inline(always)]
+    fn from(variant: CONNECT_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl CONNECT_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> CONNECT_A {
+        match self.bits {
+            true => CONNECT_A::DISCONNECTED,
+            false => CONNECT_A::CONNECTED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISCONNECTED`"]
+    #[inline(always)]
+    pub fn is_disconnected(&self) -> bool {
+        *self == CONNECT_A::DISCONNECTED
+    }
+    #[doc = "Checks if the value of the field is `CONNECTED`"]
+    #[inline(always)]
+    pub fn is_connected(&self) -> bool {
+        *self == CONNECT_A::CONNECTED
+    }
+}
+#[doc = "Field `CONNECT` writer - Connection"]
+pub type CONNECT_W<'a, const O: u8> = crate::BitWriter<'a, u32, IO1_SPEC, CONNECT_A, O>;
+impl<'a, const O: u8> CONNECT_W<'a, O> {
+    #[doc = "Disconnect"]
+    #[inline(always)]
+    pub fn disconnected(self) -> &'a mut W {
+        self.variant(CONNECT_A::DISCONNECTED)
+    }
+    #[doc = "Connect"]
+    #[inline(always)]
+    pub fn connected(self) -> &'a mut W {
+        self.variant(CONNECT_A::CONNECTED)
+    }
+}
+impl R {
+    #[doc = "Bits 0:4 - Pin number"]
+    #[inline(always)]
+    pub fn pin(&self) -> PIN_R {
+        PIN_R::new((self.bits & 0x1f) as u8)
+    }
+    #[doc = "Bit 5 - Port number"]
+    #[inline(always)]
+    pub fn port(&self) -> PORT_R {
+        PORT_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 31 - Connection"]
+    #[inline(always)]
+    pub fn connect(&self) -> CONNECT_R {
+        CONNECT_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:4 - Pin number"]
+    #[inline(always)]
+    pub fn pin(&mut self) -> PIN_W<0> {
+        PIN_W::new(self)
+    }
+    #[doc = "Bit 5 - Port number"]
+    #[inline(always)]
+    pub fn port(&mut self) -> PORT_W<5> {
+        PORT_W::new(self)
+    }
+    #[doc = "Bit 31 - Connection"]
+    #[inline(always)]
+    pub fn connect(&mut self) -> CONNECT_W<31> {
+        CONNECT_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Pin select for serial data MISO/IO1.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [io1](index.html) module"]
+pub struct IO1_SPEC;
+impl crate::RegisterSpec for IO1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [io1::R](R) reader structure"]
+impl crate::Readable for IO1_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [io1::W](W) writer structure"]
+impl crate::Writable for IO1_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets IO1 to value 0xffff_ffff"]
+impl crate::Resettable for IO1_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0xffff_ffff
+    }
+}

vendor/nrf5340-app-pac/src/qspi_ns/psel/io2.rs

@@ -0,0 +1,154 @@
+#[doc = "Register `IO2` reader"]
+pub struct R(crate::R<IO2_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<IO2_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<IO2_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<IO2_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `IO2` writer"]
+pub struct W(crate::W<IO2_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<IO2_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<IO2_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<IO2_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `PIN` reader - Pin number"]
+pub type PIN_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `PIN` writer - Pin number"]
+pub type PIN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IO2_SPEC, u8, u8, 5, O>;
+#[doc = "Field `PORT` reader - Port number"]
+pub type PORT_R = crate::BitReader<bool>;
+#[doc = "Field `PORT` writer - Port number"]
+pub type PORT_W<'a, const O: u8> = crate::BitWriter<'a, u32, IO2_SPEC, bool, O>;
+#[doc = "Field `CONNECT` reader - Connection"]
+pub type CONNECT_R = crate::BitReader<CONNECT_A>;
+#[doc = "Connection\n\nValue on reset: 1"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CONNECT_A {
+    #[doc = "1: Disconnect"]
+    DISCONNECTED = 1,
+    #[doc = "0: Connect"]
+    CONNECTED = 0,
+}
+impl From<CONNECT_A> for bool {
+    #[inline(always)]
+    fn from(variant: CONNECT_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl CONNECT_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> CONNECT_A {
+        match self.bits {
+            true => CONNECT_A::DISCONNECTED,
+            false => CONNECT_A::CONNECTED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISCONNECTED`"]
+    #[inline(always)]
+    pub fn is_disconnected(&self) -> bool {
+        *self == CONNECT_A::DISCONNECTED
+    }
+    #[doc = "Checks if the value of the field is `CONNECTED`"]
+    #[inline(always)]
+    pub fn is_connected(&self) -> bool {
+        *self == CONNECT_A::CONNECTED
+    }
+}
+#[doc = "Field `CONNECT` writer - Connection"]
+pub type CONNECT_W<'a, const O: u8> = crate::BitWriter<'a, u32, IO2_SPEC, CONNECT_A, O>;
+impl<'a, const O: u8> CONNECT_W<'a, O> {
+    #[doc = "Disconnect"]
+    #[inline(always)]
+    pub fn disconnected(self) -> &'a mut W {
+        self.variant(CONNECT_A::DISCONNECTED)
+    }
+    #[doc = "Connect"]
+    #[inline(always)]
+    pub fn connected(self) -> &'a mut W {
+        self.variant(CONNECT_A::CONNECTED)
+    }
+}
+impl R {
+    #[doc = "Bits 0:4 - Pin number"]
+    #[inline(always)]
+    pub fn pin(&self) -> PIN_R {
+        PIN_R::new((self.bits & 0x1f) as u8)
+    }
+    #[doc = "Bit 5 - Port number"]
+    #[inline(always)]
+    pub fn port(&self) -> PORT_R {
+        PORT_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 31 - Connection"]
+    #[inline(always)]
+    pub fn connect(&self) -> CONNECT_R {
+        CONNECT_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:4 - Pin number"]
+    #[inline(always)]
+    pub fn pin(&mut self) -> PIN_W<0> {
+        PIN_W::new(self)
+    }
+    #[doc = "Bit 5 - Port number"]
+    #[inline(always)]
+    pub fn port(&mut self) -> PORT_W<5> {
+        PORT_W::new(self)
+    }
+    #[doc = "Bit 31 - Connection"]
+    #[inline(always)]
+    pub fn connect(&mut self) -> CONNECT_W<31> {
+        CONNECT_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Pin select for serial data WP/IO2.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [io2](index.html) module"]
+pub struct IO2_SPEC;
+impl crate::RegisterSpec for IO2_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [io2::R](R) reader structure"]
+impl crate::Readable for IO2_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [io2::W](W) writer structure"]
+impl crate::Writable for IO2_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets IO2 to value 0xffff_ffff"]
+impl crate::Resettable for IO2_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0xffff_ffff
+    }
+}

vendor/nrf5340-app-pac/src/qspi_ns/psel/io3.rs

@@ -0,0 +1,154 @@
+#[doc = "Register `IO3` reader"]
+pub struct R(crate::R<IO3_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<IO3_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<IO3_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<IO3_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `IO3` writer"]
+pub struct W(crate::W<IO3_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<IO3_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<IO3_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<IO3_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `PIN` reader - Pin number"]
+pub type PIN_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `PIN` writer - Pin number"]
+pub type PIN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IO3_SPEC, u8, u8, 5, O>;
+#[doc = "Field `PORT` reader - Port number"]
+pub type PORT_R = crate::BitReader<bool>;
+#[doc = "Field `PORT` writer - Port number"]
+pub type PORT_W<'a, const O: u8> = crate::BitWriter<'a, u32, IO3_SPEC, bool, O>;
+#[doc = "Field `CONNECT` reader - Connection"]
+pub type CONNECT_R = crate::BitReader<CONNECT_A>;
+#[doc = "Connection\n\nValue on reset: 1"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CONNECT_A {
+    #[doc = "1: Disconnect"]
+    DISCONNECTED = 1,
+    #[doc = "0: Connect"]
+    CONNECTED = 0,
+}
+impl From<CONNECT_A> for bool {
+    #[inline(always)]
+    fn from(variant: CONNECT_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl CONNECT_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> CONNECT_A {
+        match self.bits {
+            true => CONNECT_A::DISCONNECTED,
+            false => CONNECT_A::CONNECTED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISCONNECTED`"]
+    #[inline(always)]
+    pub fn is_disconnected(&self) -> bool {
+        *self == CONNECT_A::DISCONNECTED
+    }
+    #[doc = "Checks if the value of the field is `CONNECTED`"]
+    #[inline(always)]
+    pub fn is_connected(&self) -> bool {
+        *self == CONNECT_A::CONNECTED
+    }
+}
+#[doc = "Field `CONNECT` writer - Connection"]
+pub type CONNECT_W<'a, const O: u8> = crate::BitWriter<'a, u32, IO3_SPEC, CONNECT_A, O>;
+impl<'a, const O: u8> CONNECT_W<'a, O> {
+    #[doc = "Disconnect"]
+    #[inline(always)]
+    pub fn disconnected(self) -> &'a mut W {
+        self.variant(CONNECT_A::DISCONNECTED)
+    }
+    #[doc = "Connect"]
+    #[inline(always)]
+    pub fn connected(self) -> &'a mut W {
+        self.variant(CONNECT_A::CONNECTED)
+    }
+}
+impl R {
+    #[doc = "Bits 0:4 - Pin number"]
+    #[inline(always)]
+    pub fn pin(&self) -> PIN_R {
+        PIN_R::new((self.bits & 0x1f) as u8)
+    }
+    #[doc = "Bit 5 - Port number"]
+    #[inline(always)]
+    pub fn port(&self) -> PORT_R {
+        PORT_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 31 - Connection"]
+    #[inline(always)]
+    pub fn connect(&self) -> CONNECT_R {
+        CONNECT_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:4 - Pin number"]
+    #[inline(always)]
+    pub fn pin(&mut self) -> PIN_W<0> {
+        PIN_W::new(self)
+    }
+    #[doc = "Bit 5 - Port number"]
+    #[inline(always)]
+    pub fn port(&mut self) -> PORT_W<5> {
+        PORT_W::new(self)
+    }
+    #[doc = "Bit 31 - Connection"]
+    #[inline(always)]
+    pub fn connect(&mut self) -> CONNECT_W<31> {
+        CONNECT_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Pin select for serial data HOLD/IO3.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [io3](index.html) module"]
+pub struct IO3_SPEC;
+impl crate::RegisterSpec for IO3_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [io3::R](R) reader structure"]
+impl crate::Readable for IO3_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [io3::W](W) writer structure"]
+impl crate::Writable for IO3_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets IO3 to value 0xffff_ffff"]
+impl crate::Resettable for IO3_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0xffff_ffff
+    }
+}

vendor/nrf5340-app-pac/src/qspi_ns/psel/sck.rs

@@ -0,0 +1,154 @@
+#[doc = "Register `SCK` reader"]
+pub struct R(crate::R<SCK_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<SCK_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<SCK_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<SCK_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `SCK` writer"]
+pub struct W(crate::W<SCK_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<SCK_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<SCK_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<SCK_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `PIN` reader - Pin number"]
+pub type PIN_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `PIN` writer - Pin number"]
+pub type PIN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SCK_SPEC, u8, u8, 5, O>;
+#[doc = "Field `PORT` reader - Port number"]
+pub type PORT_R = crate::BitReader<bool>;
+#[doc = "Field `PORT` writer - Port number"]
+pub type PORT_W<'a, const O: u8> = crate::BitWriter<'a, u32, SCK_SPEC, bool, O>;
+#[doc = "Field `CONNECT` reader - Connection"]
+pub type CONNECT_R = crate::BitReader<CONNECT_A>;
+#[doc = "Connection\n\nValue on reset: 1"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CONNECT_A {
+    #[doc = "1: Disconnect"]
+    DISCONNECTED = 1,
+    #[doc = "0: Connect"]
+    CONNECTED = 0,
+}
+impl From<CONNECT_A> for bool {
+    #[inline(always)]
+    fn from(variant: CONNECT_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl CONNECT_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> CONNECT_A {
+        match self.bits {
+            true => CONNECT_A::DISCONNECTED,
+            false => CONNECT_A::CONNECTED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISCONNECTED`"]
+    #[inline(always)]
+    pub fn is_disconnected(&self) -> bool {
+        *self == CONNECT_A::DISCONNECTED
+    }
+    #[doc = "Checks if the value of the field is `CONNECTED`"]
+    #[inline(always)]
+    pub fn is_connected(&self) -> bool {
+        *self == CONNECT_A::CONNECTED
+    }
+}
+#[doc = "Field `CONNECT` writer - Connection"]
+pub type CONNECT_W<'a, const O: u8> = crate::BitWriter<'a, u32, SCK_SPEC, CONNECT_A, O>;
+impl<'a, const O: u8> CONNECT_W<'a, O> {
+    #[doc = "Disconnect"]
+    #[inline(always)]
+    pub fn disconnected(self) -> &'a mut W {
+        self.variant(CONNECT_A::DISCONNECTED)
+    }
+    #[doc = "Connect"]
+    #[inline(always)]
+    pub fn connected(self) -> &'a mut W {
+        self.variant(CONNECT_A::CONNECTED)
+    }
+}
+impl R {
+    #[doc = "Bits 0:4 - Pin number"]
+    #[inline(always)]
+    pub fn pin(&self) -> PIN_R {
+        PIN_R::new((self.bits & 0x1f) as u8)
+    }
+    #[doc = "Bit 5 - Port number"]
+    #[inline(always)]
+    pub fn port(&self) -> PORT_R {
+        PORT_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 31 - Connection"]
+    #[inline(always)]
+    pub fn connect(&self) -> CONNECT_R {
+        CONNECT_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:4 - Pin number"]
+    #[inline(always)]
+    pub fn pin(&mut self) -> PIN_W<0> {
+        PIN_W::new(self)
+    }
+    #[doc = "Bit 5 - Port number"]
+    #[inline(always)]
+    pub fn port(&mut self) -> PORT_W<5> {
+        PORT_W::new(self)
+    }
+    #[doc = "Bit 31 - Connection"]
+    #[inline(always)]
+    pub fn connect(&mut self) -> CONNECT_W<31> {
+        CONNECT_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Pin select for serial clock SCK\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sck](index.html) module"]
+pub struct SCK_SPEC;
+impl crate::RegisterSpec for SCK_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [sck::R](R) reader structure"]
+impl crate::Readable for SCK_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [sck::W](W) writer structure"]
+impl crate::Writable for SCK_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets SCK to value 0xffff_ffff"]
+impl crate::Resettable for SCK_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0xffff_ffff
+    }
+}

vendor/nrf5340-app-pac/src/qspi_ns/publish_ready.rs

@@ -0,0 +1,140 @@
+#[doc = "Register `PUBLISH_READY` reader"]
+pub struct R(crate::R<PUBLISH_READY_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<PUBLISH_READY_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<PUBLISH_READY_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<PUBLISH_READY_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `PUBLISH_READY` writer"]
+pub struct W(crate::W<PUBLISH_READY_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<PUBLISH_READY_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<PUBLISH_READY_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<PUBLISH_READY_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `CHIDX` reader - DPPI channel that event READY will publish to."]
+pub type CHIDX_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `CHIDX` writer - DPPI channel that event READY will publish to."]
+pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PUBLISH_READY_SPEC, u8, u8, 8, O>;
+#[doc = "Field `EN` reader - "]
+pub type EN_R = crate::BitReader<EN_A>;
+#[doc = "\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum EN_A {
+    #[doc = "0: Disable publishing"]
+    DISABLED = 0,
+    #[doc = "1: Enable publishing"]
+    ENABLED = 1,
+}
+impl From<EN_A> for bool {
+    #[inline(always)]
+    fn from(variant: EN_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl EN_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> EN_A {
+        match self.bits {
+            false => EN_A::DISABLED,
+            true => EN_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == EN_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == EN_A::ENABLED
+    }
+}
+#[doc = "Field `EN` writer - "]
+pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_READY_SPEC, EN_A, O>;
+impl<'a, const O: u8> EN_W<'a, O> {
+    #[doc = "Disable publishing"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(EN_A::DISABLED)
+    }
+    #[doc = "Enable publishing"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(EN_A::ENABLED)
+    }
+}
+impl R {
+    #[doc = "Bits 0:7 - DPPI channel that event READY will publish to."]
+    #[inline(always)]
+    pub fn chidx(&self) -> CHIDX_R {
+        CHIDX_R::new((self.bits & 0xff) as u8)
+    }
+    #[doc = "Bit 31"]
+    #[inline(always)]
+    pub fn en(&self) -> EN_R {
+        EN_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - DPPI channel that event READY will publish to."]
+    #[inline(always)]
+    pub fn chidx(&mut self) -> CHIDX_W<0> {
+        CHIDX_W::new(self)
+    }
+    #[doc = "Bit 31"]
+    #[inline(always)]
+    pub fn en(&mut self) -> EN_W<31> {
+        EN_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Publish configuration for event READY\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_ready](index.html) module"]
+pub struct PUBLISH_READY_SPEC;
+impl crate::RegisterSpec for PUBLISH_READY_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [publish_ready::R](R) reader structure"]
+impl crate::Readable for PUBLISH_READY_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [publish_ready::W](W) writer structure"]
+impl crate::Writable for PUBLISH_READY_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets PUBLISH_READY to value 0"]
+impl crate::Resettable for PUBLISH_READY_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf5340-app-pac/src/qspi_ns/read.rs

@@ -0,0 +1,22 @@
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct READ {
+    #[doc = "0x00 - Flash memory source address"]
+    pub src: SRC,
+    #[doc = "0x04 - RAM destination address"]
+    pub dst: DST,
+    #[doc = "0x08 - Read transfer length"]
+    pub cnt: CNT,
+}
+#[doc = "SRC (rw) register accessor: an alias for `Reg<SRC_SPEC>`"]
+pub type SRC = crate::Reg<src::SRC_SPEC>;
+#[doc = "Flash memory source address"]
+pub mod src;
+#[doc = "DST (rw) register accessor: an alias for `Reg<DST_SPEC>`"]
+pub type DST = crate::Reg<dst::DST_SPEC>;
+#[doc = "RAM destination address"]
+pub mod dst;
+#[doc = "CNT (rw) register accessor: an alias for `Reg<CNT_SPEC>`"]
+pub type CNT = crate::Reg<cnt::CNT_SPEC>;
+#[doc = "Read transfer length"]
+pub mod cnt;

vendor/nrf5340-app-pac/src/qspi_ns/read/cnt.rs

@@ -0,0 +1,80 @@
+#[doc = "Register `CNT` reader"]
+pub struct R(crate::R<CNT_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<CNT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<CNT_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<CNT_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `CNT` writer"]
+pub struct W(crate::W<CNT_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<CNT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<CNT_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<CNT_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `CNT` reader - Read transfer length in number of bytes. The length must be a multiple of 4 bytes."]
+pub type CNT_R = crate::FieldReader<u32, u32>;
+#[doc = "Field `CNT` writer - Read transfer length in number of bytes. The length must be a multiple of 4 bytes."]
+pub type CNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CNT_SPEC, u32, u32, 21, O>;
+impl R {
+    #[doc = "Bits 0:20 - Read transfer length in number of bytes. The length must be a multiple of 4 bytes."]
+    #[inline(always)]
+    pub fn cnt(&self) -> CNT_R {
+        CNT_R::new((self.bits & 0x001f_ffff) as u32)
+    }
+}
+impl W {
+    #[doc = "Bits 0:20 - Read transfer length in number of bytes. The length must be a multiple of 4 bytes."]
+    #[inline(always)]
+    pub fn cnt(&mut self) -> CNT_W<0> {
+        CNT_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Read transfer length\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cnt](index.html) module"]
+pub struct CNT_SPEC;
+impl crate::RegisterSpec for CNT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [cnt::R](R) reader structure"]
+impl crate::Readable for CNT_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [cnt::W](W) writer structure"]
+impl crate::Writable for CNT_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets CNT to value 0"]
+impl crate::Resettable for CNT_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf5340-app-pac/src/qspi_ns/read/dst.rs

@@ -0,0 +1,80 @@
+#[doc = "Register `DST` reader"]
+pub struct R(crate::R<DST_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<DST_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<DST_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<DST_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `DST` writer"]
+pub struct W(crate::W<DST_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<DST_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<DST_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<DST_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `DST` reader - Word-aligned RAM destination address."]
+pub type DST_R = crate::FieldReader<u32, u32>;
+#[doc = "Field `DST` writer - Word-aligned RAM destination address."]
+pub type DST_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DST_SPEC, u32, u32, 32, O>;
+impl R {
+    #[doc = "Bits 0:31 - Word-aligned RAM destination address."]
+    #[inline(always)]
+    pub fn dst(&self) -> DST_R {
+        DST_R::new(self.bits)
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Word-aligned RAM destination address."]
+    #[inline(always)]
+    pub fn dst(&mut self) -> DST_W<0> {
+        DST_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "RAM destination address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dst](index.html) module"]
+pub struct DST_SPEC;
+impl crate::RegisterSpec for DST_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [dst::R](R) reader structure"]
+impl crate::Readable for DST_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [dst::W](W) writer structure"]
+impl crate::Writable for DST_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets DST to value 0"]
+impl crate::Resettable for DST_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf5340-app-pac/src/qspi_ns/read/src.rs

@@ -0,0 +1,80 @@
+#[doc = "Register `SRC` reader"]
+pub struct R(crate::R<SRC_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<SRC_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<SRC_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<SRC_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `SRC` writer"]
+pub struct W(crate::W<SRC_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<SRC_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<SRC_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<SRC_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `SRC` reader - Word-aligned flash memory source address."]
+pub type SRC_R = crate::FieldReader<u32, u32>;
+#[doc = "Field `SRC` writer - Word-aligned flash memory source address."]
+pub type SRC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SRC_SPEC, u32, u32, 32, O>;
+impl R {
+    #[doc = "Bits 0:31 - Word-aligned flash memory source address."]
+    #[inline(always)]
+    pub fn src(&self) -> SRC_R {
+        SRC_R::new(self.bits)
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Word-aligned flash memory source address."]
+    #[inline(always)]
+    pub fn src(&mut self) -> SRC_W<0> {
+        SRC_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Flash memory source address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [src](index.html) module"]
+pub struct SRC_SPEC;
+impl crate::RegisterSpec for SRC_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [src::R](R) reader structure"]
+impl crate::Readable for SRC_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [src::W](W) writer structure"]
+impl crate::Writable for SRC_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets SRC to value 0"]
+impl crate::Resettable for SRC_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf5340-app-pac/src/qspi_ns/status.rs

@@ -0,0 +1,122 @@
+#[doc = "Register `STATUS` reader"]
+pub struct R(crate::R<STATUS_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<STATUS_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<STATUS_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<STATUS_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `DPM` reader - Deep power-down mode (DPM) status of external flash."]
+pub type DPM_R = crate::BitReader<DPM_A>;
+#[doc = "Deep power-down mode (DPM) status of external flash.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DPM_A {
+    #[doc = "0: External flash is not in DPM."]
+    DISABLED = 0,
+    #[doc = "1: External flash is in DPM."]
+    ENABLED = 1,
+}
+impl From<DPM_A> for bool {
+    #[inline(always)]
+    fn from(variant: DPM_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl DPM_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> DPM_A {
+        match self.bits {
+            false => DPM_A::DISABLED,
+            true => DPM_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == DPM_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == DPM_A::ENABLED
+    }
+}
+#[doc = "Field `READY` reader - Ready status."]
+pub type READY_R = crate::BitReader<READY_A>;
+#[doc = "Ready status.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum READY_A {
+    #[doc = "1: QSPI peripheral is ready. It is allowed to trigger new tasks, writing custom instructions or enter/exit DPM."]
+    READY = 1,
+    #[doc = "0: QSPI peripheral is busy. It is not allowed to trigger any new tasks, writing custom instructions or enter/exit DPM."]
+    BUSY = 0,
+}
+impl From<READY_A> for bool {
+    #[inline(always)]
+    fn from(variant: READY_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl READY_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> READY_A {
+        match self.bits {
+            true => READY_A::READY,
+            false => READY_A::BUSY,
+        }
+    }
+    #[doc = "Checks if the value of the field is `READY`"]
+    #[inline(always)]
+    pub fn is_ready(&self) -> bool {
+        *self == READY_A::READY
+    }
+    #[doc = "Checks if the value of the field is `BUSY`"]
+    #[inline(always)]
+    pub fn is_busy(&self) -> bool {
+        *self == READY_A::BUSY
+    }
+}
+#[doc = "Field `SREG` reader - Value of external flash device Status Register. When the external flash has two bytes status register this field includes the value of the low byte."]
+pub type SREG_R = crate::FieldReader<u8, u8>;
+impl R {
+    #[doc = "Bit 2 - Deep power-down mode (DPM) status of external flash."]
+    #[inline(always)]
+    pub fn dpm(&self) -> DPM_R {
+        DPM_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Ready status."]
+    #[inline(always)]
+    pub fn ready(&self) -> READY_R {
+        READY_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bits 24:31 - Value of external flash device Status Register. When the external flash has two bytes status register this field includes the value of the low byte."]
+    #[inline(always)]
+    pub fn sreg(&self) -> SREG_R {
+        SREG_R::new(((self.bits >> 24) & 0xff) as u8)
+    }
+}
+#[doc = "Status register.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"]
+pub struct STATUS_SPEC;
+impl crate::RegisterSpec for STATUS_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [status::R](R) reader structure"]
+impl crate::Readable for STATUS_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets STATUS to value 0"]
+impl crate::Resettable for STATUS_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf5340-app-pac/src/qspi_ns/subscribe_activate.rs

@@ -0,0 +1,141 @@
+#[doc = "Register `SUBSCRIBE_ACTIVATE` reader"]
+pub struct R(crate::R<SUBSCRIBE_ACTIVATE_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<SUBSCRIBE_ACTIVATE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<SUBSCRIBE_ACTIVATE_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<SUBSCRIBE_ACTIVATE_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `SUBSCRIBE_ACTIVATE` writer"]
+pub struct W(crate::W<SUBSCRIBE_ACTIVATE_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<SUBSCRIBE_ACTIVATE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<SUBSCRIBE_ACTIVATE_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<SUBSCRIBE_ACTIVATE_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `CHIDX` reader - DPPI channel that task ACTIVATE will subscribe to"]
+pub type CHIDX_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `CHIDX` writer - DPPI channel that task ACTIVATE will subscribe to"]
+pub type CHIDX_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u32, SUBSCRIBE_ACTIVATE_SPEC, u8, u8, 8, O>;
+#[doc = "Field `EN` reader - "]
+pub type EN_R = crate::BitReader<EN_A>;
+#[doc = "\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum EN_A {
+    #[doc = "0: Disable subscription"]
+    DISABLED = 0,
+    #[doc = "1: Enable subscription"]
+    ENABLED = 1,
+}
+impl From<EN_A> for bool {
+    #[inline(always)]
+    fn from(variant: EN_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl EN_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> EN_A {
+        match self.bits {
+            false => EN_A::DISABLED,
+            true => EN_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == EN_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == EN_A::ENABLED
+    }
+}
+#[doc = "Field `EN` writer - "]
+pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_ACTIVATE_SPEC, EN_A, O>;
+impl<'a, const O: u8> EN_W<'a, O> {
+    #[doc = "Disable subscription"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(EN_A::DISABLED)
+    }
+    #[doc = "Enable subscription"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(EN_A::ENABLED)
+    }
+}
+impl R {
+    #[doc = "Bits 0:7 - DPPI channel that task ACTIVATE will subscribe to"]
+    #[inline(always)]
+    pub fn chidx(&self) -> CHIDX_R {
+        CHIDX_R::new((self.bits & 0xff) as u8)
+    }
+    #[doc = "Bit 31"]
+    #[inline(always)]
+    pub fn en(&self) -> EN_R {
+        EN_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - DPPI channel that task ACTIVATE will subscribe to"]
+    #[inline(always)]
+    pub fn chidx(&mut self) -> CHIDX_W<0> {
+        CHIDX_W::new(self)
+    }
+    #[doc = "Bit 31"]
+    #[inline(always)]
+    pub fn en(&mut self) -> EN_W<31> {
+        EN_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Subscribe configuration for task ACTIVATE\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_activate](index.html) module"]
+pub struct SUBSCRIBE_ACTIVATE_SPEC;
+impl crate::RegisterSpec for SUBSCRIBE_ACTIVATE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [subscribe_activate::R](R) reader structure"]
+impl crate::Readable for SUBSCRIBE_ACTIVATE_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [subscribe_activate::W](W) writer structure"]
+impl crate::Writable for SUBSCRIBE_ACTIVATE_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets SUBSCRIBE_ACTIVATE to value 0"]
+impl crate::Resettable for SUBSCRIBE_ACTIVATE_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf5340-app-pac/src/qspi_ns/subscribe_deactivate.rs

@@ -0,0 +1,141 @@
+#[doc = "Register `SUBSCRIBE_DEACTIVATE` reader"]
+pub struct R(crate::R<SUBSCRIBE_DEACTIVATE_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<SUBSCRIBE_DEACTIVATE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<SUBSCRIBE_DEACTIVATE_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<SUBSCRIBE_DEACTIVATE_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `SUBSCRIBE_DEACTIVATE` writer"]
+pub struct W(crate::W<SUBSCRIBE_DEACTIVATE_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<SUBSCRIBE_DEACTIVATE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<SUBSCRIBE_DEACTIVATE_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<SUBSCRIBE_DEACTIVATE_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `CHIDX` reader - DPPI channel that task DEACTIVATE will subscribe to"]
+pub type CHIDX_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `CHIDX` writer - DPPI channel that task DEACTIVATE will subscribe to"]
+pub type CHIDX_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u32, SUBSCRIBE_DEACTIVATE_SPEC, u8, u8, 8, O>;
+#[doc = "Field `EN` reader - "]
+pub type EN_R = crate::BitReader<EN_A>;
+#[doc = "\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum EN_A {
+    #[doc = "0: Disable subscription"]
+    DISABLED = 0,
+    #[doc = "1: Enable subscription"]
+    ENABLED = 1,
+}
+impl From<EN_A> for bool {
+    #[inline(always)]
+    fn from(variant: EN_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl EN_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> EN_A {
+        match self.bits {
+            false => EN_A::DISABLED,
+            true => EN_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == EN_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == EN_A::ENABLED
+    }
+}
+#[doc = "Field `EN` writer - "]
+pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_DEACTIVATE_SPEC, EN_A, O>;
+impl<'a, const O: u8> EN_W<'a, O> {
+    #[doc = "Disable subscription"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(EN_A::DISABLED)
+    }
+    #[doc = "Enable subscription"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(EN_A::ENABLED)
+    }
+}
+impl R {
+    #[doc = "Bits 0:7 - DPPI channel that task DEACTIVATE will subscribe to"]
+    #[inline(always)]
+    pub fn chidx(&self) -> CHIDX_R {
+        CHIDX_R::new((self.bits & 0xff) as u8)
+    }
+    #[doc = "Bit 31"]
+    #[inline(always)]
+    pub fn en(&self) -> EN_R {
+        EN_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - DPPI channel that task DEACTIVATE will subscribe to"]
+    #[inline(always)]
+    pub fn chidx(&mut self) -> CHIDX_W<0> {
+        CHIDX_W::new(self)
+    }
+    #[doc = "Bit 31"]
+    #[inline(always)]
+    pub fn en(&mut self) -> EN_W<31> {
+        EN_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Subscribe configuration for task DEACTIVATE\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_deactivate](index.html) module"]
+pub struct SUBSCRIBE_DEACTIVATE_SPEC;
+impl crate::RegisterSpec for SUBSCRIBE_DEACTIVATE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [subscribe_deactivate::R](R) reader structure"]
+impl crate::Readable for SUBSCRIBE_DEACTIVATE_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [subscribe_deactivate::W](W) writer structure"]
+impl crate::Writable for SUBSCRIBE_DEACTIVATE_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets SUBSCRIBE_DEACTIVATE to value 0"]
+impl crate::Resettable for SUBSCRIBE_DEACTIVATE_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf5340-app-pac/src/qspi_ns/subscribe_erasestart.rs

@@ -0,0 +1,141 @@
+#[doc = "Register `SUBSCRIBE_ERASESTART` reader"]
+pub struct R(crate::R<SUBSCRIBE_ERASESTART_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<SUBSCRIBE_ERASESTART_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<SUBSCRIBE_ERASESTART_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<SUBSCRIBE_ERASESTART_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `SUBSCRIBE_ERASESTART` writer"]
+pub struct W(crate::W<SUBSCRIBE_ERASESTART_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<SUBSCRIBE_ERASESTART_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<SUBSCRIBE_ERASESTART_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<SUBSCRIBE_ERASESTART_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `CHIDX` reader - DPPI channel that task ERASESTART will subscribe to"]
+pub type CHIDX_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `CHIDX` writer - DPPI channel that task ERASESTART will subscribe to"]
+pub type CHIDX_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u32, SUBSCRIBE_ERASESTART_SPEC, u8, u8, 8, O>;
+#[doc = "Field `EN` reader - "]
+pub type EN_R = crate::BitReader<EN_A>;
+#[doc = "\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum EN_A {
+    #[doc = "0: Disable subscription"]
+    DISABLED = 0,
+    #[doc = "1: Enable subscription"]
+    ENABLED = 1,
+}
+impl From<EN_A> for bool {
+    #[inline(always)]
+    fn from(variant: EN_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl EN_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> EN_A {
+        match self.bits {
+            false => EN_A::DISABLED,
+            true => EN_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == EN_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == EN_A::ENABLED
+    }
+}
+#[doc = "Field `EN` writer - "]
+pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_ERASESTART_SPEC, EN_A, O>;
+impl<'a, const O: u8> EN_W<'a, O> {
+    #[doc = "Disable subscription"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(EN_A::DISABLED)
+    }
+    #[doc = "Enable subscription"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(EN_A::ENABLED)
+    }
+}
+impl R {
+    #[doc = "Bits 0:7 - DPPI channel that task ERASESTART will subscribe to"]
+    #[inline(always)]
+    pub fn chidx(&self) -> CHIDX_R {
+        CHIDX_R::new((self.bits & 0xff) as u8)
+    }
+    #[doc = "Bit 31"]
+    #[inline(always)]
+    pub fn en(&self) -> EN_R {
+        EN_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - DPPI channel that task ERASESTART will subscribe to"]
+    #[inline(always)]
+    pub fn chidx(&mut self) -> CHIDX_W<0> {
+        CHIDX_W::new(self)
+    }
+    #[doc = "Bit 31"]
+    #[inline(always)]
+    pub fn en(&mut self) -> EN_W<31> {
+        EN_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Subscribe configuration for task ERASESTART\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_erasestart](index.html) module"]
+pub struct SUBSCRIBE_ERASESTART_SPEC;
+impl crate::RegisterSpec for SUBSCRIBE_ERASESTART_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [subscribe_erasestart::R](R) reader structure"]
+impl crate::Readable for SUBSCRIBE_ERASESTART_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [subscribe_erasestart::W](W) writer structure"]
+impl crate::Writable for SUBSCRIBE_ERASESTART_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets SUBSCRIBE_ERASESTART to value 0"]
+impl crate::Resettable for SUBSCRIBE_ERASESTART_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf5340-app-pac/src/qspi_ns/subscribe_readstart.rs

@@ -0,0 +1,141 @@
+#[doc = "Register `SUBSCRIBE_READSTART` reader"]
+pub struct R(crate::R<SUBSCRIBE_READSTART_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<SUBSCRIBE_READSTART_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<SUBSCRIBE_READSTART_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<SUBSCRIBE_READSTART_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `SUBSCRIBE_READSTART` writer"]
+pub struct W(crate::W<SUBSCRIBE_READSTART_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<SUBSCRIBE_READSTART_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<SUBSCRIBE_READSTART_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<SUBSCRIBE_READSTART_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `CHIDX` reader - DPPI channel that task READSTART will subscribe to"]
+pub type CHIDX_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `CHIDX` writer - DPPI channel that task READSTART will subscribe to"]
+pub type CHIDX_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u32, SUBSCRIBE_READSTART_SPEC, u8, u8, 8, O>;
+#[doc = "Field `EN` reader - "]
+pub type EN_R = crate::BitReader<EN_A>;
+#[doc = "\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum EN_A {
+    #[doc = "0: Disable subscription"]
+    DISABLED = 0,
+    #[doc = "1: Enable subscription"]
+    ENABLED = 1,
+}
+impl From<EN_A> for bool {
+    #[inline(always)]
+    fn from(variant: EN_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl EN_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> EN_A {
+        match self.bits {
+            false => EN_A::DISABLED,
+            true => EN_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == EN_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == EN_A::ENABLED
+    }
+}
+#[doc = "Field `EN` writer - "]
+pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_READSTART_SPEC, EN_A, O>;
+impl<'a, const O: u8> EN_W<'a, O> {
+    #[doc = "Disable subscription"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(EN_A::DISABLED)
+    }
+    #[doc = "Enable subscription"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(EN_A::ENABLED)
+    }
+}
+impl R {
+    #[doc = "Bits 0:7 - DPPI channel that task READSTART will subscribe to"]
+    #[inline(always)]
+    pub fn chidx(&self) -> CHIDX_R {
+        CHIDX_R::new((self.bits & 0xff) as u8)
+    }
+    #[doc = "Bit 31"]
+    #[inline(always)]
+    pub fn en(&self) -> EN_R {
+        EN_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - DPPI channel that task READSTART will subscribe to"]
+    #[inline(always)]
+    pub fn chidx(&mut self) -> CHIDX_W<0> {
+        CHIDX_W::new(self)
+    }
+    #[doc = "Bit 31"]
+    #[inline(always)]
+    pub fn en(&mut self) -> EN_W<31> {
+        EN_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Subscribe configuration for task READSTART\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_readstart](index.html) module"]
+pub struct SUBSCRIBE_READSTART_SPEC;
+impl crate::RegisterSpec for SUBSCRIBE_READSTART_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [subscribe_readstart::R](R) reader structure"]
+impl crate::Readable for SUBSCRIBE_READSTART_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [subscribe_readstart::W](W) writer structure"]
+impl crate::Writable for SUBSCRIBE_READSTART_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets SUBSCRIBE_READSTART to value 0"]
+impl crate::Resettable for SUBSCRIBE_READSTART_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf5340-app-pac/src/qspi_ns/subscribe_writestart.rs

@@ -0,0 +1,141 @@
+#[doc = "Register `SUBSCRIBE_WRITESTART` reader"]
+pub struct R(crate::R<SUBSCRIBE_WRITESTART_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<SUBSCRIBE_WRITESTART_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<SUBSCRIBE_WRITESTART_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<SUBSCRIBE_WRITESTART_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `SUBSCRIBE_WRITESTART` writer"]
+pub struct W(crate::W<SUBSCRIBE_WRITESTART_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<SUBSCRIBE_WRITESTART_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<SUBSCRIBE_WRITESTART_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<SUBSCRIBE_WRITESTART_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `CHIDX` reader - DPPI channel that task WRITESTART will subscribe to"]
+pub type CHIDX_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `CHIDX` writer - DPPI channel that task WRITESTART will subscribe to"]
+pub type CHIDX_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u32, SUBSCRIBE_WRITESTART_SPEC, u8, u8, 8, O>;
+#[doc = "Field `EN` reader - "]
+pub type EN_R = crate::BitReader<EN_A>;
+#[doc = "\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum EN_A {
+    #[doc = "0: Disable subscription"]
+    DISABLED = 0,
+    #[doc = "1: Enable subscription"]
+    ENABLED = 1,
+}
+impl From<EN_A> for bool {
+    #[inline(always)]
+    fn from(variant: EN_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl EN_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> EN_A {
+        match self.bits {
+            false => EN_A::DISABLED,
+            true => EN_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == EN_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == EN_A::ENABLED
+    }
+}
+#[doc = "Field `EN` writer - "]
+pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_WRITESTART_SPEC, EN_A, O>;
+impl<'a, const O: u8> EN_W<'a, O> {
+    #[doc = "Disable subscription"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(EN_A::DISABLED)
+    }
+    #[doc = "Enable subscription"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(EN_A::ENABLED)
+    }
+}
+impl R {
+    #[doc = "Bits 0:7 - DPPI channel that task WRITESTART will subscribe to"]
+    #[inline(always)]
+    pub fn chidx(&self) -> CHIDX_R {
+        CHIDX_R::new((self.bits & 0xff) as u8)
+    }
+    #[doc = "Bit 31"]
+    #[inline(always)]
+    pub fn en(&self) -> EN_R {
+        EN_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - DPPI channel that task WRITESTART will subscribe to"]
+    #[inline(always)]
+    pub fn chidx(&mut self) -> CHIDX_W<0> {
+        CHIDX_W::new(self)
+    }
+    #[doc = "Bit 31"]
+    #[inline(always)]
+    pub fn en(&mut self) -> EN_W<31> {
+        EN_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Subscribe configuration for task WRITESTART\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_writestart](index.html) module"]
+pub struct SUBSCRIBE_WRITESTART_SPEC;
+impl crate::RegisterSpec for SUBSCRIBE_WRITESTART_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [subscribe_writestart::R](R) reader structure"]
+impl crate::Readable for SUBSCRIBE_WRITESTART_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [subscribe_writestart::W](W) writer structure"]
+impl crate::Writable for SUBSCRIBE_WRITESTART_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets SUBSCRIBE_WRITESTART to value 0"]
+impl crate::Resettable for SUBSCRIBE_WRITESTART_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf5340-app-pac/src/qspi_ns/tasks_activate.rs

@@ -0,0 +1,72 @@
+#[doc = "Register `TASKS_ACTIVATE` writer"]
+pub struct W(crate::W<TASKS_ACTIVATE_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<TASKS_ACTIVATE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<TASKS_ACTIVATE_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<TASKS_ACTIVATE_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Activate QSPI interface\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TASKS_ACTIVATE_AW {
+    #[doc = "1: Trigger task"]
+    TRIGGER = 1,
+}
+impl From<TASKS_ACTIVATE_AW> for bool {
+    #[inline(always)]
+    fn from(variant: TASKS_ACTIVATE_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `TASKS_ACTIVATE` writer - Activate QSPI interface"]
+pub type TASKS_ACTIVATE_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, TASKS_ACTIVATE_SPEC, TASKS_ACTIVATE_AW, O>;
+impl<'a, const O: u8> TASKS_ACTIVATE_W<'a, O> {
+    #[doc = "Trigger task"]
+    #[inline(always)]
+    pub fn trigger(self) -> &'a mut W {
+        self.variant(TASKS_ACTIVATE_AW::TRIGGER)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Activate QSPI interface"]
+    #[inline(always)]
+    pub fn tasks_activate(&mut self) -> TASKS_ACTIVATE_W<0> {
+        TASKS_ACTIVATE_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Activate QSPI interface\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_activate](index.html) module"]
+pub struct TASKS_ACTIVATE_SPEC;
+impl crate::RegisterSpec for TASKS_ACTIVATE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [tasks_activate::W](W) writer structure"]
+impl crate::Writable for TASKS_ACTIVATE_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets TASKS_ACTIVATE to value 0"]
+impl crate::Resettable for TASKS_ACTIVATE_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf5340-app-pac/src/qspi_ns/tasks_deactivate.rs

@@ -0,0 +1,72 @@
+#[doc = "Register `TASKS_DEACTIVATE` writer"]
+pub struct W(crate::W<TASKS_DEACTIVATE_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<TASKS_DEACTIVATE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<TASKS_DEACTIVATE_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<TASKS_DEACTIVATE_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Deactivate QSPI interface\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TASKS_DEACTIVATE_AW {
+    #[doc = "1: Trigger task"]
+    TRIGGER = 1,
+}
+impl From<TASKS_DEACTIVATE_AW> for bool {
+    #[inline(always)]
+    fn from(variant: TASKS_DEACTIVATE_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `TASKS_DEACTIVATE` writer - Deactivate QSPI interface"]
+pub type TASKS_DEACTIVATE_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, TASKS_DEACTIVATE_SPEC, TASKS_DEACTIVATE_AW, O>;
+impl<'a, const O: u8> TASKS_DEACTIVATE_W<'a, O> {
+    #[doc = "Trigger task"]
+    #[inline(always)]
+    pub fn trigger(self) -> &'a mut W {
+        self.variant(TASKS_DEACTIVATE_AW::TRIGGER)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Deactivate QSPI interface"]
+    #[inline(always)]
+    pub fn tasks_deactivate(&mut self) -> TASKS_DEACTIVATE_W<0> {
+        TASKS_DEACTIVATE_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Deactivate QSPI interface\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_deactivate](index.html) module"]
+pub struct TASKS_DEACTIVATE_SPEC;
+impl crate::RegisterSpec for TASKS_DEACTIVATE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [tasks_deactivate::W](W) writer structure"]
+impl crate::Writable for TASKS_DEACTIVATE_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets TASKS_DEACTIVATE to value 0"]
+impl crate::Resettable for TASKS_DEACTIVATE_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf5340-app-pac/src/qspi_ns/tasks_erasestart.rs

@@ -0,0 +1,72 @@
+#[doc = "Register `TASKS_ERASESTART` writer"]
+pub struct W(crate::W<TASKS_ERASESTART_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<TASKS_ERASESTART_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<TASKS_ERASESTART_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<TASKS_ERASESTART_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Start external flash memory erase operation\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TASKS_ERASESTART_AW {
+    #[doc = "1: Trigger task"]
+    TRIGGER = 1,
+}
+impl From<TASKS_ERASESTART_AW> for bool {
+    #[inline(always)]
+    fn from(variant: TASKS_ERASESTART_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `TASKS_ERASESTART` writer - Start external flash memory erase operation"]
+pub type TASKS_ERASESTART_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, TASKS_ERASESTART_SPEC, TASKS_ERASESTART_AW, O>;
+impl<'a, const O: u8> TASKS_ERASESTART_W<'a, O> {
+    #[doc = "Trigger task"]
+    #[inline(always)]
+    pub fn trigger(self) -> &'a mut W {
+        self.variant(TASKS_ERASESTART_AW::TRIGGER)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Start external flash memory erase operation"]
+    #[inline(always)]
+    pub fn tasks_erasestart(&mut self) -> TASKS_ERASESTART_W<0> {
+        TASKS_ERASESTART_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Start external flash memory erase operation\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_erasestart](index.html) module"]
+pub struct TASKS_ERASESTART_SPEC;
+impl crate::RegisterSpec for TASKS_ERASESTART_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [tasks_erasestart::W](W) writer structure"]
+impl crate::Writable for TASKS_ERASESTART_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets TASKS_ERASESTART to value 0"]
+impl crate::Resettable for TASKS_ERASESTART_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf5340-app-pac/src/qspi_ns/tasks_readstart.rs

@@ -0,0 +1,72 @@
+#[doc = "Register `TASKS_READSTART` writer"]
+pub struct W(crate::W<TASKS_READSTART_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<TASKS_READSTART_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<TASKS_READSTART_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<TASKS_READSTART_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Start transfer from external flash memory to internal RAM\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TASKS_READSTART_AW {
+    #[doc = "1: Trigger task"]
+    TRIGGER = 1,
+}
+impl From<TASKS_READSTART_AW> for bool {
+    #[inline(always)]
+    fn from(variant: TASKS_READSTART_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `TASKS_READSTART` writer - Start transfer from external flash memory to internal RAM"]
+pub type TASKS_READSTART_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, TASKS_READSTART_SPEC, TASKS_READSTART_AW, O>;
+impl<'a, const O: u8> TASKS_READSTART_W<'a, O> {
+    #[doc = "Trigger task"]
+    #[inline(always)]
+    pub fn trigger(self) -> &'a mut W {
+        self.variant(TASKS_READSTART_AW::TRIGGER)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Start transfer from external flash memory to internal RAM"]
+    #[inline(always)]
+    pub fn tasks_readstart(&mut self) -> TASKS_READSTART_W<0> {
+        TASKS_READSTART_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Start transfer from external flash memory to internal RAM\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_readstart](index.html) module"]
+pub struct TASKS_READSTART_SPEC;
+impl crate::RegisterSpec for TASKS_READSTART_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [tasks_readstart::W](W) writer structure"]
+impl crate::Writable for TASKS_READSTART_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets TASKS_READSTART to value 0"]
+impl crate::Resettable for TASKS_READSTART_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf5340-app-pac/src/qspi_ns/tasks_writestart.rs

@@ -0,0 +1,72 @@
+#[doc = "Register `TASKS_WRITESTART` writer"]
+pub struct W(crate::W<TASKS_WRITESTART_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<TASKS_WRITESTART_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<TASKS_WRITESTART_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<TASKS_WRITESTART_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Start transfer from internal RAM to external flash memory\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TASKS_WRITESTART_AW {
+    #[doc = "1: Trigger task"]
+    TRIGGER = 1,
+}
+impl From<TASKS_WRITESTART_AW> for bool {
+    #[inline(always)]
+    fn from(variant: TASKS_WRITESTART_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `TASKS_WRITESTART` writer - Start transfer from internal RAM to external flash memory"]
+pub type TASKS_WRITESTART_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, TASKS_WRITESTART_SPEC, TASKS_WRITESTART_AW, O>;
+impl<'a, const O: u8> TASKS_WRITESTART_W<'a, O> {
+    #[doc = "Trigger task"]
+    #[inline(always)]
+    pub fn trigger(self) -> &'a mut W {
+        self.variant(TASKS_WRITESTART_AW::TRIGGER)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Start transfer from internal RAM to external flash memory"]
+    #[inline(always)]
+    pub fn tasks_writestart(&mut self) -> TASKS_WRITESTART_W<0> {
+        TASKS_WRITESTART_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Start transfer from internal RAM to external flash memory\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_writestart](index.html) module"]
+pub struct TASKS_WRITESTART_SPEC;
+impl crate::RegisterSpec for TASKS_WRITESTART_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [tasks_writestart::W](W) writer structure"]
+impl crate::Writable for TASKS_WRITESTART_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets TASKS_WRITESTART to value 0"]
+impl crate::Resettable for TASKS_WRITESTART_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf5340-app-pac/src/qspi_ns/write.rs

@@ -0,0 +1,22 @@
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct WRITE {
+    #[doc = "0x00 - Flash destination address"]
+    pub dst: DST,
+    #[doc = "0x04 - RAM source address"]
+    pub src: SRC,
+    #[doc = "0x08 - Write transfer length"]
+    pub cnt: CNT,
+}
+#[doc = "DST (rw) register accessor: an alias for `Reg<DST_SPEC>`"]
+pub type DST = crate::Reg<dst::DST_SPEC>;
+#[doc = "Flash destination address"]
+pub mod dst;
+#[doc = "SRC (rw) register accessor: an alias for `Reg<SRC_SPEC>`"]
+pub type SRC = crate::Reg<src::SRC_SPEC>;
+#[doc = "RAM source address"]
+pub mod src;
+#[doc = "CNT (rw) register accessor: an alias for `Reg<CNT_SPEC>`"]
+pub type CNT = crate::Reg<cnt::CNT_SPEC>;
+#[doc = "Write transfer length"]
+pub mod cnt;

vendor/nrf5340-app-pac/src/qspi_ns/write/cnt.rs

@@ -0,0 +1,80 @@
+#[doc = "Register `CNT` reader"]
+pub struct R(crate::R<CNT_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<CNT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<CNT_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<CNT_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `CNT` writer"]
+pub struct W(crate::W<CNT_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<CNT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<CNT_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<CNT_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `CNT` reader - Write transfer length in number of bytes. The length must be a multiple of 4 bytes."]
+pub type CNT_R = crate::FieldReader<u32, u32>;
+#[doc = "Field `CNT` writer - Write transfer length in number of bytes. The length must be a multiple of 4 bytes."]
+pub type CNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CNT_SPEC, u32, u32, 21, O>;
+impl R {
+    #[doc = "Bits 0:20 - Write transfer length in number of bytes. The length must be a multiple of 4 bytes."]
+    #[inline(always)]
+    pub fn cnt(&self) -> CNT_R {
+        CNT_R::new((self.bits & 0x001f_ffff) as u32)
+    }
+}
+impl W {
+    #[doc = "Bits 0:20 - Write transfer length in number of bytes. The length must be a multiple of 4 bytes."]
+    #[inline(always)]
+    pub fn cnt(&mut self) -> CNT_W<0> {
+        CNT_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Write transfer length\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cnt](index.html) module"]
+pub struct CNT_SPEC;
+impl crate::RegisterSpec for CNT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [cnt::R](R) reader structure"]
+impl crate::Readable for CNT_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [cnt::W](W) writer structure"]
+impl crate::Writable for CNT_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets CNT to value 0"]
+impl crate::Resettable for CNT_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf5340-app-pac/src/qspi_ns/write/dst.rs

@@ -0,0 +1,80 @@
+#[doc = "Register `DST` reader"]
+pub struct R(crate::R<DST_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<DST_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<DST_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<DST_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `DST` writer"]
+pub struct W(crate::W<DST_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<DST_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<DST_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<DST_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `DST` reader - Word-aligned flash destination address."]
+pub type DST_R = crate::FieldReader<u32, u32>;
+#[doc = "Field `DST` writer - Word-aligned flash destination address."]
+pub type DST_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DST_SPEC, u32, u32, 32, O>;
+impl R {
+    #[doc = "Bits 0:31 - Word-aligned flash destination address."]
+    #[inline(always)]
+    pub fn dst(&self) -> DST_R {
+        DST_R::new(self.bits)
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Word-aligned flash destination address."]
+    #[inline(always)]
+    pub fn dst(&mut self) -> DST_W<0> {
+        DST_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Flash destination address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dst](index.html) module"]
+pub struct DST_SPEC;
+impl crate::RegisterSpec for DST_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [dst::R](R) reader structure"]
+impl crate::Readable for DST_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [dst::W](W) writer structure"]
+impl crate::Writable for DST_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets DST to value 0"]
+impl crate::Resettable for DST_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf5340-app-pac/src/qspi_ns/write/src.rs

@@ -0,0 +1,80 @@
+#[doc = "Register `SRC` reader"]
+pub struct R(crate::R<SRC_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<SRC_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<SRC_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<SRC_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `SRC` writer"]
+pub struct W(crate::W<SRC_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<SRC_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<SRC_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<SRC_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `SRC` reader - Word-aligned RAM source address."]
+pub type SRC_R = crate::FieldReader<u32, u32>;
+#[doc = "Field `SRC` writer - Word-aligned RAM source address."]
+pub type SRC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SRC_SPEC, u32, u32, 32, O>;
+impl R {
+    #[doc = "Bits 0:31 - Word-aligned RAM source address."]
+    #[inline(always)]
+    pub fn src(&self) -> SRC_R {
+        SRC_R::new(self.bits)
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Word-aligned RAM source address."]
+    #[inline(always)]
+    pub fn src(&mut self) -> SRC_W<0> {
+        SRC_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "RAM source address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [src](index.html) module"]
+pub struct SRC_SPEC;
+impl crate::RegisterSpec for SRC_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [src::R](R) reader structure"]
+impl crate::Readable for SRC_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [src::W](W) writer structure"]
+impl crate::Writable for SRC_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets SRC to value 0"]
+impl crate::Resettable for SRC_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf5340-app-pac/src/qspi_ns/xip_enc.rs

@@ -0,0 +1,52 @@
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct XIP_ENC {
+    #[doc = "0x00 - Bits 31:0 of XIP AES KEY"]
+    pub key0: KEY0,
+    #[doc = "0x04 - Bits 63:32 of XIP AES KEY"]
+    pub key1: KEY1,
+    #[doc = "0x08 - Bits 95:64 of XIP AES KEY"]
+    pub key2: KEY2,
+    #[doc = "0x0c - Bits 127:96 of XIP AES KEY"]
+    pub key3: KEY3,
+    #[doc = "0x10 - Bits 31:0 of XIP NONCE"]
+    pub nonce0: NONCE0,
+    #[doc = "0x14 - Bits 63:32 of XIP NONCE"]
+    pub nonce1: NONCE1,
+    #[doc = "0x18 - Bits 95:64 of XIP NONCE"]
+    pub nonce2: NONCE2,
+    #[doc = "0x1c - Enable stream cipher for XIP"]
+    pub enable: ENABLE,
+}
+#[doc = "KEY0 (w) register accessor: an alias for `Reg<KEY0_SPEC>`"]
+pub type KEY0 = crate::Reg<key0::KEY0_SPEC>;
+#[doc = "Bits 31:0 of XIP AES KEY"]
+pub mod key0;
+#[doc = "KEY1 (w) register accessor: an alias for `Reg<KEY1_SPEC>`"]
+pub type KEY1 = crate::Reg<key1::KEY1_SPEC>;
+#[doc = "Bits 63:32 of XIP AES KEY"]
+pub mod key1;
+#[doc = "KEY2 (w) register accessor: an alias for `Reg<KEY2_SPEC>`"]
+pub type KEY2 = crate::Reg<key2::KEY2_SPEC>;
+#[doc = "Bits 95:64 of XIP AES KEY"]
+pub mod key2;
+#[doc = "KEY3 (w) register accessor: an alias for `Reg<KEY3_SPEC>`"]
+pub type KEY3 = crate::Reg<key3::KEY3_SPEC>;
+#[doc = "Bits 127:96 of XIP AES KEY"]
+pub mod key3;
+#[doc = "NONCE0 (w) register accessor: an alias for `Reg<NONCE0_SPEC>`"]
+pub type NONCE0 = crate::Reg<nonce0::NONCE0_SPEC>;
+#[doc = "Bits 31:0 of XIP NONCE"]
+pub mod nonce0;
+#[doc = "NONCE1 (w) register accessor: an alias for `Reg<NONCE1_SPEC>`"]
+pub type NONCE1 = crate::Reg<nonce1::NONCE1_SPEC>;
+#[doc = "Bits 63:32 of XIP NONCE"]
+pub mod nonce1;
+#[doc = "NONCE2 (w) register accessor: an alias for `Reg<NONCE2_SPEC>`"]
+pub type NONCE2 = crate::Reg<nonce2::NONCE2_SPEC>;
+#[doc = "Bits 95:64 of XIP NONCE"]
+pub mod nonce2;
+#[doc = "ENABLE (rw) register accessor: an alias for `Reg<ENABLE_SPEC>`"]
+pub type ENABLE = crate::Reg<enable::ENABLE_SPEC>;
+#[doc = "Enable stream cipher for XIP"]
+pub mod enable;

vendor/nrf5340-app-pac/src/qspi_ns/xip_enc/enable.rs

@@ -0,0 +1,126 @@
+#[doc = "Register `ENABLE` reader"]
+pub struct R(crate::R<ENABLE_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<ENABLE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<ENABLE_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<ENABLE_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `ENABLE` writer"]
+pub struct W(crate::W<ENABLE_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<ENABLE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<ENABLE_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<ENABLE_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `ENABLE` reader - Enable or disable stream cipher for XIP"]
+pub type ENABLE_R = crate::BitReader<ENABLE_A>;
+#[doc = "Enable or disable stream cipher for XIP\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ENABLE_A {
+    #[doc = "0: Disable stream cipher for QSPI XIP"]
+    DISABLED = 0,
+    #[doc = "1: Enable stream cipher for QSPI XIP"]
+    ENABLED = 1,
+}
+impl From<ENABLE_A> for bool {
+    #[inline(always)]
+    fn from(variant: ENABLE_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl ENABLE_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> ENABLE_A {
+        match self.bits {
+            false => ENABLE_A::DISABLED,
+            true => ENABLE_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == ENABLE_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == ENABLE_A::ENABLED
+    }
+}
+#[doc = "Field `ENABLE` writer - Enable or disable stream cipher for XIP"]
+pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, ENABLE_SPEC, ENABLE_A, O>;
+impl<'a, const O: u8> ENABLE_W<'a, O> {
+    #[doc = "Disable stream cipher for QSPI XIP"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(ENABLE_A::DISABLED)
+    }
+    #[doc = "Enable stream cipher for QSPI XIP"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(ENABLE_A::ENABLED)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Enable or disable stream cipher for XIP"]
+    #[inline(always)]
+    pub fn enable(&self) -> ENABLE_R {
+        ENABLE_R::new((self.bits & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Enable or disable stream cipher for XIP"]
+    #[inline(always)]
+    pub fn enable(&mut self) -> ENABLE_W<0> {
+        ENABLE_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Enable stream cipher for XIP\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [enable](index.html) module"]
+pub struct ENABLE_SPEC;
+impl crate::RegisterSpec for ENABLE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [enable::R](R) reader structure"]
+impl crate::Readable for ENABLE_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [enable::W](W) writer structure"]
+impl crate::Writable for ENABLE_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets ENABLE to value 0"]
+impl crate::Resettable for ENABLE_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf5340-app-pac/src/qspi_ns/xip_enc/key0.rs

@@ -0,0 +1,52 @@
+#[doc = "Register `KEY0` writer"]
+pub struct W(crate::W<KEY0_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<KEY0_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<KEY0_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<KEY0_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `KEY0` writer - Bits 31:0 of XIP AES KEY"]
+pub type KEY0_W<'a, const O: u8> = crate::FieldWriter<'a, u32, KEY0_SPEC, u32, u32, 32, O>;
+impl W {
+    #[doc = "Bits 0:31 - Bits 31:0 of XIP AES KEY"]
+    #[inline(always)]
+    pub fn key0(&mut self) -> KEY0_W<0> {
+        KEY0_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Bits 31:0 of XIP AES KEY\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [key0](index.html) module"]
+pub struct KEY0_SPEC;
+impl crate::RegisterSpec for KEY0_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [key0::W](W) writer structure"]
+impl crate::Writable for KEY0_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets KEY0 to value 0"]
+impl crate::Resettable for KEY0_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf5340-app-pac/src/qspi_ns/xip_enc/key1.rs

@@ -0,0 +1,52 @@
+#[doc = "Register `KEY1` writer"]
+pub struct W(crate::W<KEY1_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<KEY1_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<KEY1_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<KEY1_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `KEY1` writer - Bits 63:32 of XIP AES KEY"]
+pub type KEY1_W<'a, const O: u8> = crate::FieldWriter<'a, u32, KEY1_SPEC, u32, u32, 32, O>;
+impl W {
+    #[doc = "Bits 0:31 - Bits 63:32 of XIP AES KEY"]
+    #[inline(always)]
+    pub fn key1(&mut self) -> KEY1_W<0> {
+        KEY1_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Bits 63:32 of XIP AES KEY\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [key1](index.html) module"]
+pub struct KEY1_SPEC;
+impl crate::RegisterSpec for KEY1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [key1::W](W) writer structure"]
+impl crate::Writable for KEY1_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets KEY1 to value 0"]
+impl crate::Resettable for KEY1_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf5340-app-pac/src/qspi_ns/xip_enc/key2.rs

@@ -0,0 +1,52 @@
+#[doc = "Register `KEY2` writer"]
+pub struct W(crate::W<KEY2_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<KEY2_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<KEY2_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<KEY2_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `KEY2` writer - Bits 95:64 of XIP AES KEY"]
+pub type KEY2_W<'a, const O: u8> = crate::FieldWriter<'a, u32, KEY2_SPEC, u32, u32, 32, O>;
+impl W {
+    #[doc = "Bits 0:31 - Bits 95:64 of XIP AES KEY"]
+    #[inline(always)]
+    pub fn key2(&mut self) -> KEY2_W<0> {
+        KEY2_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Bits 95:64 of XIP AES KEY\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [key2](index.html) module"]
+pub struct KEY2_SPEC;
+impl crate::RegisterSpec for KEY2_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [key2::W](W) writer structure"]
+impl crate::Writable for KEY2_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets KEY2 to value 0"]
+impl crate::Resettable for KEY2_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf5340-app-pac/src/qspi_ns/xip_enc/key3.rs

@@ -0,0 +1,52 @@
+#[doc = "Register `KEY3` writer"]
+pub struct W(crate::W<KEY3_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<KEY3_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<KEY3_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<KEY3_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `KEY3` writer - Bits 127:96 of XIP AES KEY"]
+pub type KEY3_W<'a, const O: u8> = crate::FieldWriter<'a, u32, KEY3_SPEC, u32, u32, 32, O>;
+impl W {
+    #[doc = "Bits 0:31 - Bits 127:96 of XIP AES KEY"]
+    #[inline(always)]
+    pub fn key3(&mut self) -> KEY3_W<0> {
+        KEY3_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Bits 127:96 of XIP AES KEY\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [key3](index.html) module"]
+pub struct KEY3_SPEC;
+impl crate::RegisterSpec for KEY3_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [key3::W](W) writer structure"]
+impl crate::Writable for KEY3_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets KEY3 to value 0"]
+impl crate::Resettable for KEY3_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf5340-app-pac/src/qspi_ns/xip_enc/nonce0.rs

@@ -0,0 +1,52 @@
+#[doc = "Register `NONCE0` writer"]
+pub struct W(crate::W<NONCE0_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<NONCE0_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<NONCE0_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<NONCE0_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `NONCE0` writer - Bits 31:0 of XIP NONCE"]
+pub type NONCE0_W<'a, const O: u8> = crate::FieldWriter<'a, u32, NONCE0_SPEC, u32, u32, 32, O>;
+impl W {
+    #[doc = "Bits 0:31 - Bits 31:0 of XIP NONCE"]
+    #[inline(always)]
+    pub fn nonce0(&mut self) -> NONCE0_W<0> {
+        NONCE0_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Bits 31:0 of XIP NONCE\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [nonce0](index.html) module"]
+pub struct NONCE0_SPEC;
+impl crate::RegisterSpec for NONCE0_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [nonce0::W](W) writer structure"]
+impl crate::Writable for NONCE0_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets NONCE0 to value 0"]
+impl crate::Resettable for NONCE0_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf5340-app-pac/src/qspi_ns/xip_enc/nonce1.rs

@@ -0,0 +1,52 @@
+#[doc = "Register `NONCE1` writer"]
+pub struct W(crate::W<NONCE1_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<NONCE1_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<NONCE1_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<NONCE1_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `NONCE1` writer - Bits 63:32 of XIP NONCE"]
+pub type NONCE1_W<'a, const O: u8> = crate::FieldWriter<'a, u32, NONCE1_SPEC, u32, u32, 32, O>;
+impl W {
+    #[doc = "Bits 0:31 - Bits 63:32 of XIP NONCE"]
+    #[inline(always)]
+    pub fn nonce1(&mut self) -> NONCE1_W<0> {
+        NONCE1_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Bits 63:32 of XIP NONCE\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [nonce1](index.html) module"]
+pub struct NONCE1_SPEC;
+impl crate::RegisterSpec for NONCE1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [nonce1::W](W) writer structure"]
+impl crate::Writable for NONCE1_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets NONCE1 to value 0"]
+impl crate::Resettable for NONCE1_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf5340-app-pac/src/qspi_ns/xip_enc/nonce2.rs

@@ -0,0 +1,52 @@
+#[doc = "Register `NONCE2` writer"]
+pub struct W(crate::W<NONCE2_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<NONCE2_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<NONCE2_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<NONCE2_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `NONCE2` writer - Bits 95:64 of XIP NONCE"]
+pub type NONCE2_W<'a, const O: u8> = crate::FieldWriter<'a, u32, NONCE2_SPEC, u32, u32, 32, O>;
+impl W {
+    #[doc = "Bits 0:31 - Bits 95:64 of XIP NONCE"]
+    #[inline(always)]
+    pub fn nonce2(&mut self) -> NONCE2_W<0> {
+        NONCE2_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Bits 95:64 of XIP NONCE\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [nonce2](index.html) module"]
+pub struct NONCE2_SPEC;
+impl crate::RegisterSpec for NONCE2_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [nonce2::W](W) writer structure"]
+impl crate::Writable for NONCE2_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets NONCE2 to value 0"]
+impl crate::Resettable for NONCE2_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf5340-app-pac/src/qspi_ns/xipen.rs

@@ -0,0 +1,126 @@
+#[doc = "Register `XIPEN` reader"]
+pub struct R(crate::R<XIPEN_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<XIPEN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<XIPEN_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<XIPEN_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `XIPEN` writer"]
+pub struct W(crate::W<XIPEN_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<XIPEN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<XIPEN_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<XIPEN_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `XIPEN` reader - Enable XIP AHB Slave interface and access to XIP memory range"]
+pub type XIPEN_R = crate::BitReader<XIPEN_A>;
+#[doc = "Enable XIP AHB Slave interface and access to XIP memory range\n\nValue on reset: 1"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum XIPEN_A {
+    #[doc = "0: Disable XIP interface"]
+    DISABLE = 0,
+    #[doc = "1: Enable XIP interface"]
+    ENABLE = 1,
+}
+impl From<XIPEN_A> for bool {
+    #[inline(always)]
+    fn from(variant: XIPEN_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl XIPEN_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> XIPEN_A {
+        match self.bits {
+            false => XIPEN_A::DISABLE,
+            true => XIPEN_A::ENABLE,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLE`"]
+    #[inline(always)]
+    pub fn is_disable(&self) -> bool {
+        *self == XIPEN_A::DISABLE
+    }
+    #[doc = "Checks if the value of the field is `ENABLE`"]
+    #[inline(always)]
+    pub fn is_enable(&self) -> bool {
+        *self == XIPEN_A::ENABLE
+    }
+}
+#[doc = "Field `XIPEN` writer - Enable XIP AHB Slave interface and access to XIP memory range"]
+pub type XIPEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, XIPEN_SPEC, XIPEN_A, O>;
+impl<'a, const O: u8> XIPEN_W<'a, O> {
+    #[doc = "Disable XIP interface"]
+    #[inline(always)]
+    pub fn disable(self) -> &'a mut W {
+        self.variant(XIPEN_A::DISABLE)
+    }
+    #[doc = "Enable XIP interface"]
+    #[inline(always)]
+    pub fn enable(self) -> &'a mut W {
+        self.variant(XIPEN_A::ENABLE)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Enable XIP AHB Slave interface and access to XIP memory range"]
+    #[inline(always)]
+    pub fn xipen(&self) -> XIPEN_R {
+        XIPEN_R::new((self.bits & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Enable XIP AHB Slave interface and access to XIP memory range"]
+    #[inline(always)]
+    pub fn xipen(&mut self) -> XIPEN_W<0> {
+        XIPEN_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Enable Execute in Place operation.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xipen](index.html) module"]
+pub struct XIPEN_SPEC;
+impl crate::RegisterSpec for XIPEN_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [xipen::R](R) reader structure"]
+impl crate::Readable for XIPEN_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [xipen::W](W) writer structure"]
+impl crate::Writable for XIPEN_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets XIPEN to value 0x01"]
+impl crate::Resettable for XIPEN_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0x01
+    }
+}

vendor/nrf5340-app-pac/src/qspi_ns/xipoffset.rs

@@ -0,0 +1,81 @@
+#[doc = "Register `XIPOFFSET` reader"]
+pub struct R(crate::R<XIPOFFSET_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<XIPOFFSET_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<XIPOFFSET_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<XIPOFFSET_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `XIPOFFSET` writer"]
+pub struct W(crate::W<XIPOFFSET_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<XIPOFFSET_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<XIPOFFSET_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<XIPOFFSET_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `XIPOFFSET` reader - Address offset into the external memory for Execute in Place operation. Value must be a multiple of 4."]
+pub type XIPOFFSET_R = crate::FieldReader<u32, u32>;
+#[doc = "Field `XIPOFFSET` writer - Address offset into the external memory for Execute in Place operation. Value must be a multiple of 4."]
+pub type XIPOFFSET_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u32, XIPOFFSET_SPEC, u32, u32, 32, O>;
+impl R {
+    #[doc = "Bits 0:31 - Address offset into the external memory for Execute in Place operation. Value must be a multiple of 4."]
+    #[inline(always)]
+    pub fn xipoffset(&self) -> XIPOFFSET_R {
+        XIPOFFSET_R::new(self.bits)
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Address offset into the external memory for Execute in Place operation. Value must be a multiple of 4."]
+    #[inline(always)]
+    pub fn xipoffset(&mut self) -> XIPOFFSET_W<0> {
+        XIPOFFSET_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Address offset into the external memory for Execute in Place operation.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xipoffset](index.html) module"]
+pub struct XIPOFFSET_SPEC;
+impl crate::RegisterSpec for XIPOFFSET_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [xipoffset::R](R) reader structure"]
+impl crate::Readable for XIPOFFSET_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [xipoffset::W](W) writer structure"]
+impl crate::Writable for XIPOFFSET_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets XIPOFFSET to value 0"]
+impl crate::Resettable for XIPOFFSET_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}