feat: add display UI with splash screen, dashboard, and RSSI sparkline

Implement full SSD1306 OLED display support:
- Splash screen on boot (1.5s) with project name, version, board
- Dashboard showing radio state, config, counters, RSSI/SNR
- RSSI history sparkline (64-sample ring buffer, 2px-wide bars)
- DisplayOn/DisplayOff host commands routed via dedicated channel
- Pure render functions against generic DrawTarget (no hardware coupling)
- Display on/off control bypasses radio task entirely

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>

vendor/nrf5340-net-pac/src/nvmc_ns/config.rs

@@ -0,0 +1,154 @@
+#[doc = "Register `CONFIG` reader"]
+pub struct R(crate::R<CONFIG_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<CONFIG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<CONFIG_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<CONFIG_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `CONFIG` writer"]
+pub struct W(crate::W<CONFIG_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<CONFIG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<CONFIG_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<CONFIG_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `WEN` reader - Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated."]
+pub type WEN_R = crate::FieldReader<u8, WEN_A>;
+#[doc = "Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum WEN_A {
+    #[doc = "0: Read only access"]
+    REN = 0,
+    #[doc = "1: Write enabled"]
+    WEN = 1,
+    #[doc = "2: Erase enabled"]
+    EEN = 2,
+    #[doc = "4: Partial erase enabled"]
+    PEEN = 4,
+}
+impl From<WEN_A> for u8 {
+    #[inline(always)]
+    fn from(variant: WEN_A) -> Self {
+        variant as _
+    }
+}
+impl WEN_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<WEN_A> {
+        match self.bits {
+            0 => Some(WEN_A::REN),
+            1 => Some(WEN_A::WEN),
+            2 => Some(WEN_A::EEN),
+            4 => Some(WEN_A::PEEN),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `REN`"]
+    #[inline(always)]
+    pub fn is_ren(&self) -> bool {
+        *self == WEN_A::REN
+    }
+    #[doc = "Checks if the value of the field is `WEN`"]
+    #[inline(always)]
+    pub fn is_wen(&self) -> bool {
+        *self == WEN_A::WEN
+    }
+    #[doc = "Checks if the value of the field is `EEN`"]
+    #[inline(always)]
+    pub fn is_een(&self) -> bool {
+        *self == WEN_A::EEN
+    }
+    #[doc = "Checks if the value of the field is `PEEN`"]
+    #[inline(always)]
+    pub fn is_peen(&self) -> bool {
+        *self == WEN_A::PEEN
+    }
+}
+#[doc = "Field `WEN` writer - Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated."]
+pub type WEN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CONFIG_SPEC, u8, WEN_A, 3, O>;
+impl<'a, const O: u8> WEN_W<'a, O> {
+    #[doc = "Read only access"]
+    #[inline(always)]
+    pub fn ren(self) -> &'a mut W {
+        self.variant(WEN_A::REN)
+    }
+    #[doc = "Write enabled"]
+    #[inline(always)]
+    pub fn wen(self) -> &'a mut W {
+        self.variant(WEN_A::WEN)
+    }
+    #[doc = "Erase enabled"]
+    #[inline(always)]
+    pub fn een(self) -> &'a mut W {
+        self.variant(WEN_A::EEN)
+    }
+    #[doc = "Partial erase enabled"]
+    #[inline(always)]
+    pub fn peen(self) -> &'a mut W {
+        self.variant(WEN_A::PEEN)
+    }
+}
+impl R {
+    #[doc = "Bits 0:2 - Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated."]
+    #[inline(always)]
+    pub fn wen(&self) -> WEN_R {
+        WEN_R::new((self.bits & 7) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:2 - Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated."]
+    #[inline(always)]
+    pub fn wen(&mut self) -> WEN_W<0> {
+        WEN_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [config](index.html) module"]
+pub struct CONFIG_SPEC;
+impl crate::RegisterSpec for CONFIG_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [config::R](R) reader structure"]
+impl crate::Readable for CONFIG_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [config::W](W) writer structure"]
+impl crate::Writable for CONFIG_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets CONFIG to value 0"]
+impl crate::Resettable for CONFIG_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf5340-net-pac/src/nvmc_ns/eraseall.rs

@@ -0,0 +1,78 @@
+#[doc = "Register `ERASEALL` writer"]
+pub struct W(crate::W<ERASEALL_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<ERASEALL_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<ERASEALL_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<ERASEALL_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Erase all non-volatile memory including UICR registers. Before the non-volatile memory can be erased, erasing must be enabled by setting CONFIG.WEN=Een.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ERASEALL_AW {
+    #[doc = "0: No operation"]
+    NO_OPERATION = 0,
+    #[doc = "1: Start chip erase"]
+    ERASE = 1,
+}
+impl From<ERASEALL_AW> for bool {
+    #[inline(always)]
+    fn from(variant: ERASEALL_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `ERASEALL` writer - Erase all non-volatile memory including UICR registers. Before the non-volatile memory can be erased, erasing must be enabled by setting CONFIG.WEN=Een."]
+pub type ERASEALL_W<'a, const O: u8> = crate::BitWriter<'a, u32, ERASEALL_SPEC, ERASEALL_AW, O>;
+impl<'a, const O: u8> ERASEALL_W<'a, O> {
+    #[doc = "No operation"]
+    #[inline(always)]
+    pub fn no_operation(self) -> &'a mut W {
+        self.variant(ERASEALL_AW::NO_OPERATION)
+    }
+    #[doc = "Start chip erase"]
+    #[inline(always)]
+    pub fn erase(self) -> &'a mut W {
+        self.variant(ERASEALL_AW::ERASE)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Erase all non-volatile memory including UICR registers. Before the non-volatile memory can be erased, erasing must be enabled by setting CONFIG.WEN=Een."]
+    #[inline(always)]
+    pub fn eraseall(&mut self) -> ERASEALL_W<0> {
+        ERASEALL_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Register for erasing all non-volatile user memory\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [eraseall](index.html) module"]
+pub struct ERASEALL_SPEC;
+impl crate::RegisterSpec for ERASEALL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [eraseall::W](W) writer structure"]
+impl crate::Writable for ERASEALL_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets ERASEALL to value 0"]
+impl crate::Resettable for ERASEALL_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf5340-net-pac/src/nvmc_ns/erasepagepartialcfg.rs

@@ -0,0 +1,81 @@
+#[doc = "Register `ERASEPAGEPARTIALCFG` reader"]
+pub struct R(crate::R<ERASEPAGEPARTIALCFG_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<ERASEPAGEPARTIALCFG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<ERASEPAGEPARTIALCFG_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<ERASEPAGEPARTIALCFG_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `ERASEPAGEPARTIALCFG` writer"]
+pub struct W(crate::W<ERASEPAGEPARTIALCFG_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<ERASEPAGEPARTIALCFG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<ERASEPAGEPARTIALCFG_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<ERASEPAGEPARTIALCFG_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `DURATION` reader - Duration of the partial erase in milliseconds"]
+pub type DURATION_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `DURATION` writer - Duration of the partial erase in milliseconds"]
+pub type DURATION_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u32, ERASEPAGEPARTIALCFG_SPEC, u8, u8, 7, O>;
+impl R {
+    #[doc = "Bits 0:6 - Duration of the partial erase in milliseconds"]
+    #[inline(always)]
+    pub fn duration(&self) -> DURATION_R {
+        DURATION_R::new((self.bits & 0x7f) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:6 - Duration of the partial erase in milliseconds"]
+    #[inline(always)]
+    pub fn duration(&mut self) -> DURATION_W<0> {
+        DURATION_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Register for partial erase configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [erasepagepartialcfg](index.html) module"]
+pub struct ERASEPAGEPARTIALCFG_SPEC;
+impl crate::RegisterSpec for ERASEPAGEPARTIALCFG_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [erasepagepartialcfg::R](R) reader structure"]
+impl crate::Readable for ERASEPAGEPARTIALCFG_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [erasepagepartialcfg::W](W) writer structure"]
+impl crate::Writable for ERASEPAGEPARTIALCFG_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets ERASEPAGEPARTIALCFG to value 0x0a"]
+impl crate::Resettable for ERASEPAGEPARTIALCFG_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0x0a
+    }
+}

vendor/nrf5340-net-pac/src/nvmc_ns/icachecnf.rs

@@ -0,0 +1,187 @@
+#[doc = "Register `ICACHECNF` reader"]
+pub struct R(crate::R<ICACHECNF_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<ICACHECNF_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<ICACHECNF_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<ICACHECNF_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `ICACHECNF` writer"]
+pub struct W(crate::W<ICACHECNF_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<ICACHECNF_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<ICACHECNF_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<ICACHECNF_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `CACHEEN` reader - Cache enable"]
+pub type CACHEEN_R = crate::BitReader<CACHEEN_A>;
+#[doc = "Cache enable\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CACHEEN_A {
+    #[doc = "0: Disable cache. Invalidates all cache entries."]
+    DISABLED = 0,
+    #[doc = "1: Enable cache"]
+    ENABLED = 1,
+}
+impl From<CACHEEN_A> for bool {
+    #[inline(always)]
+    fn from(variant: CACHEEN_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl CACHEEN_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> CACHEEN_A {
+        match self.bits {
+            false => CACHEEN_A::DISABLED,
+            true => CACHEEN_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == CACHEEN_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == CACHEEN_A::ENABLED
+    }
+}
+#[doc = "Field `CACHEEN` writer - Cache enable"]
+pub type CACHEEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, ICACHECNF_SPEC, CACHEEN_A, O>;
+impl<'a, const O: u8> CACHEEN_W<'a, O> {
+    #[doc = "Disable cache. Invalidates all cache entries."]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(CACHEEN_A::DISABLED)
+    }
+    #[doc = "Enable cache"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(CACHEEN_A::ENABLED)
+    }
+}
+#[doc = "Field `CACHEPROFEN` reader - Cache profiling enable"]
+pub type CACHEPROFEN_R = crate::BitReader<CACHEPROFEN_A>;
+#[doc = "Cache profiling enable\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CACHEPROFEN_A {
+    #[doc = "0: Disable cache profiling"]
+    DISABLED = 0,
+    #[doc = "1: Enable cache profiling"]
+    ENABLED = 1,
+}
+impl From<CACHEPROFEN_A> for bool {
+    #[inline(always)]
+    fn from(variant: CACHEPROFEN_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl CACHEPROFEN_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> CACHEPROFEN_A {
+        match self.bits {
+            false => CACHEPROFEN_A::DISABLED,
+            true => CACHEPROFEN_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == CACHEPROFEN_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == CACHEPROFEN_A::ENABLED
+    }
+}
+#[doc = "Field `CACHEPROFEN` writer - Cache profiling enable"]
+pub type CACHEPROFEN_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, ICACHECNF_SPEC, CACHEPROFEN_A, O>;
+impl<'a, const O: u8> CACHEPROFEN_W<'a, O> {
+    #[doc = "Disable cache profiling"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(CACHEPROFEN_A::DISABLED)
+    }
+    #[doc = "Enable cache profiling"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(CACHEPROFEN_A::ENABLED)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Cache enable"]
+    #[inline(always)]
+    pub fn cacheen(&self) -> CACHEEN_R {
+        CACHEEN_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 8 - Cache profiling enable"]
+    #[inline(always)]
+    pub fn cacheprofen(&self) -> CACHEPROFEN_R {
+        CACHEPROFEN_R::new(((self.bits >> 8) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Cache enable"]
+    #[inline(always)]
+    pub fn cacheen(&mut self) -> CACHEEN_W<0> {
+        CACHEEN_W::new(self)
+    }
+    #[doc = "Bit 8 - Cache profiling enable"]
+    #[inline(always)]
+    pub fn cacheprofen(&mut self) -> CACHEPROFEN_W<8> {
+        CACHEPROFEN_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "I-code cache configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [icachecnf](index.html) module"]
+pub struct ICACHECNF_SPEC;
+impl crate::RegisterSpec for ICACHECNF_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [icachecnf::R](R) reader structure"]
+impl crate::Readable for ICACHECNF_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [icachecnf::W](W) writer structure"]
+impl crate::Writable for ICACHECNF_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets ICACHECNF to value 0"]
+impl crate::Resettable for ICACHECNF_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf5340-net-pac/src/nvmc_ns/ihit.rs

@@ -0,0 +1,80 @@
+#[doc = "Register `IHIT` reader"]
+pub struct R(crate::R<IHIT_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<IHIT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<IHIT_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<IHIT_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `IHIT` writer"]
+pub struct W(crate::W<IHIT_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<IHIT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<IHIT_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<IHIT_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `HITS` reader - Number of cache hits Write zero to clear"]
+pub type HITS_R = crate::FieldReader<u32, u32>;
+#[doc = "Field `HITS` writer - Number of cache hits Write zero to clear"]
+pub type HITS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IHIT_SPEC, u32, u32, 32, O>;
+impl R {
+    #[doc = "Bits 0:31 - Number of cache hits Write zero to clear"]
+    #[inline(always)]
+    pub fn hits(&self) -> HITS_R {
+        HITS_R::new(self.bits)
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Number of cache hits Write zero to clear"]
+    #[inline(always)]
+    pub fn hits(&mut self) -> HITS_W<0> {
+        HITS_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "I-code cache hit counter\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ihit](index.html) module"]
+pub struct IHIT_SPEC;
+impl crate::RegisterSpec for IHIT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [ihit::R](R) reader structure"]
+impl crate::Readable for IHIT_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [ihit::W](W) writer structure"]
+impl crate::Writable for IHIT_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets IHIT to value 0"]
+impl crate::Resettable for IHIT_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf5340-net-pac/src/nvmc_ns/imiss.rs

@@ -0,0 +1,80 @@
+#[doc = "Register `IMISS` reader"]
+pub struct R(crate::R<IMISS_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<IMISS_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<IMISS_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<IMISS_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `IMISS` writer"]
+pub struct W(crate::W<IMISS_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<IMISS_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<IMISS_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<IMISS_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `MISSES` reader - Number of cache misses Write zero to clear"]
+pub type MISSES_R = crate::FieldReader<u32, u32>;
+#[doc = "Field `MISSES` writer - Number of cache misses Write zero to clear"]
+pub type MISSES_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IMISS_SPEC, u32, u32, 32, O>;
+impl R {
+    #[doc = "Bits 0:31 - Number of cache misses Write zero to clear"]
+    #[inline(always)]
+    pub fn misses(&self) -> MISSES_R {
+        MISSES_R::new(self.bits)
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Number of cache misses Write zero to clear"]
+    #[inline(always)]
+    pub fn misses(&mut self) -> MISSES_W<0> {
+        MISSES_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "I-code cache miss counter\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [imiss](index.html) module"]
+pub struct IMISS_SPEC;
+impl crate::RegisterSpec for IMISS_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [imiss::R](R) reader structure"]
+impl crate::Readable for IMISS_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [imiss::W](W) writer structure"]
+impl crate::Writable for IMISS_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets IMISS to value 0"]
+impl crate::Resettable for IMISS_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf5340-net-pac/src/nvmc_ns/ready.rs

@@ -0,0 +1,74 @@
+#[doc = "Register `READY` reader"]
+pub struct R(crate::R<READY_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<READY_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<READY_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<READY_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `READY` reader - NVMC is ready or busy"]
+pub type READY_R = crate::BitReader<READY_A>;
+#[doc = "NVMC is ready or busy\n\nValue on reset: 1"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum READY_A {
+    #[doc = "0: NVMC is busy (ongoing write or erase operation)"]
+    BUSY = 0,
+    #[doc = "1: NVMC is ready"]
+    READY = 1,
+}
+impl From<READY_A> for bool {
+    #[inline(always)]
+    fn from(variant: READY_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl READY_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> READY_A {
+        match self.bits {
+            false => READY_A::BUSY,
+            true => READY_A::READY,
+        }
+    }
+    #[doc = "Checks if the value of the field is `BUSY`"]
+    #[inline(always)]
+    pub fn is_busy(&self) -> bool {
+        *self == READY_A::BUSY
+    }
+    #[doc = "Checks if the value of the field is `READY`"]
+    #[inline(always)]
+    pub fn is_ready(&self) -> bool {
+        *self == READY_A::READY
+    }
+}
+impl R {
+    #[doc = "Bit 0 - NVMC is ready or busy"]
+    #[inline(always)]
+    pub fn ready(&self) -> READY_R {
+        READY_R::new((self.bits & 1) != 0)
+    }
+}
+#[doc = "Ready flag\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ready](index.html) module"]
+pub struct READY_SPEC;
+impl crate::RegisterSpec for READY_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [ready::R](R) reader structure"]
+impl crate::Readable for READY_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets READY to value 0x01"]
+impl crate::Resettable for READY_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0x01
+    }
+}

vendor/nrf5340-net-pac/src/nvmc_ns/readynext.rs

@@ -0,0 +1,74 @@
+#[doc = "Register `READYNEXT` reader"]
+pub struct R(crate::R<READYNEXT_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<READYNEXT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<READYNEXT_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<READYNEXT_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `READYNEXT` reader - NVMC can accept a new write operation"]
+pub type READYNEXT_R = crate::BitReader<READYNEXT_A>;
+#[doc = "NVMC can accept a new write operation\n\nValue on reset: 1"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum READYNEXT_A {
+    #[doc = "0: NVMC cannot accept any write operation"]
+    BUSY = 0,
+    #[doc = "1: NVMC is ready"]
+    READY = 1,
+}
+impl From<READYNEXT_A> for bool {
+    #[inline(always)]
+    fn from(variant: READYNEXT_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl READYNEXT_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> READYNEXT_A {
+        match self.bits {
+            false => READYNEXT_A::BUSY,
+            true => READYNEXT_A::READY,
+        }
+    }
+    #[doc = "Checks if the value of the field is `BUSY`"]
+    #[inline(always)]
+    pub fn is_busy(&self) -> bool {
+        *self == READYNEXT_A::BUSY
+    }
+    #[doc = "Checks if the value of the field is `READY`"]
+    #[inline(always)]
+    pub fn is_ready(&self) -> bool {
+        *self == READYNEXT_A::READY
+    }
+}
+impl R {
+    #[doc = "Bit 0 - NVMC can accept a new write operation"]
+    #[inline(always)]
+    pub fn readynext(&self) -> READYNEXT_R {
+        READYNEXT_R::new((self.bits & 1) != 0)
+    }
+}
+#[doc = "Ready flag\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [readynext](index.html) module"]
+pub struct READYNEXT_SPEC;
+impl crate::RegisterSpec for READYNEXT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [readynext::R](R) reader structure"]
+impl crate::Readable for READYNEXT_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets READYNEXT to value 0x01"]
+impl crate::Resettable for READYNEXT_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0x01
+    }
+}