feat: add display UI with splash screen, dashboard, and RSSI sparkline

Implement full SSD1306 OLED display support:
- Splash screen on boot (1.5s) with project name, version, board
- Dashboard showing radio state, config, counters, RSSI/SNR
- RSSI history sparkline (64-sample ring buffer, 2px-wide bars)
- DisplayOn/DisplayOff host commands routed via dedicated channel
- Pure render functions against generic DrawTarget (no hardware coupling)
- Display on/off control bypasses radio task entirely

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>

vendor/nrf9120-pac/src/spu_s/cap.rs

@@ -0,0 +1,74 @@
+#[doc = "Register `CAP` reader"]
+pub struct R(crate::R<CAP_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<CAP_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<CAP_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<CAP_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `TZM` reader - Show ARM TrustZone status"]
+pub type TZM_R = crate::BitReader<TZM_A>;
+#[doc = "Show ARM TrustZone status\n\nValue on reset: 1"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TZM_A {
+    #[doc = "0: ARM TrustZone support not available"]
+    NOT_AVAILABLE = 0,
+    #[doc = "1: ARM TrustZone support is available"]
+    ENABLED = 1,
+}
+impl From<TZM_A> for bool {
+    #[inline(always)]
+    fn from(variant: TZM_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl TZM_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> TZM_A {
+        match self.bits {
+            false => TZM_A::NOT_AVAILABLE,
+            true => TZM_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `NOT_AVAILABLE`"]
+    #[inline(always)]
+    pub fn is_not_available(&self) -> bool {
+        *self == TZM_A::NOT_AVAILABLE
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == TZM_A::ENABLED
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Show ARM TrustZone status"]
+    #[inline(always)]
+    pub fn tzm(&self) -> TZM_R {
+        TZM_R::new((self.bits & 1) != 0)
+    }
+}
+#[doc = "Show implemented features for the current device\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cap](index.html) module"]
+pub struct CAP_SPEC;
+impl crate::RegisterSpec for CAP_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [cap::R](R) reader structure"]
+impl crate::Readable for CAP_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets CAP to value 0x01"]
+impl crate::Resettable for CAP_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0x01
+    }
+}

vendor/nrf9120-pac/src/spu_s/dppi.rs

@@ -0,0 +1,16 @@
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct DPPI {
+    #[doc = "0x00 - Description cluster: Select between secure and non-secure attribute for the DPPI channels."]
+    pub perm: PERM,
+    #[doc = "0x04 - Description cluster: Prevent further modification of the corresponding PERM register"]
+    pub lock: LOCK,
+}
+#[doc = "PERM (rw) register accessor: an alias for `Reg<PERM_SPEC>`"]
+pub type PERM = crate::Reg<perm::PERM_SPEC>;
+#[doc = "Description cluster: Select between secure and non-secure attribute for the DPPI channels."]
+pub mod perm;
+#[doc = "LOCK (rw) register accessor: an alias for `Reg<LOCK_SPEC>`"]
+pub type LOCK = crate::Reg<lock::LOCK_SPEC>;
+#[doc = "Description cluster: Prevent further modification of the corresponding PERM register"]
+pub mod lock;

vendor/nrf9120-pac/src/spu_s/dppi/lock.rs

@@ -0,0 +1,126 @@
+#[doc = "Register `LOCK` reader"]
+pub struct R(crate::R<LOCK_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<LOCK_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<LOCK_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<LOCK_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `LOCK` writer"]
+pub struct W(crate::W<LOCK_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<LOCK_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<LOCK_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<LOCK_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `LOCK` reader - "]
+pub type LOCK_R = crate::BitReader<LOCK_A>;
+#[doc = "\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum LOCK_A {
+    #[doc = "1: DPPI\\[n\\].PERM register can't be changed until next reset"]
+    LOCKED = 1,
+    #[doc = "0: DPPI\\[n\\].PERM register content can be changed"]
+    UNLOCKED = 0,
+}
+impl From<LOCK_A> for bool {
+    #[inline(always)]
+    fn from(variant: LOCK_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl LOCK_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> LOCK_A {
+        match self.bits {
+            true => LOCK_A::LOCKED,
+            false => LOCK_A::UNLOCKED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `LOCKED`"]
+    #[inline(always)]
+    pub fn is_locked(&self) -> bool {
+        *self == LOCK_A::LOCKED
+    }
+    #[doc = "Checks if the value of the field is `UNLOCKED`"]
+    #[inline(always)]
+    pub fn is_unlocked(&self) -> bool {
+        *self == LOCK_A::UNLOCKED
+    }
+}
+#[doc = "Field `LOCK` writer - "]
+pub type LOCK_W<'a, const O: u8> = crate::BitWriter<'a, u32, LOCK_SPEC, LOCK_A, O>;
+impl<'a, const O: u8> LOCK_W<'a, O> {
+    #[doc = "DPPI\\[n\\].PERM register can't be changed until next reset"]
+    #[inline(always)]
+    pub fn locked(self) -> &'a mut W {
+        self.variant(LOCK_A::LOCKED)
+    }
+    #[doc = "DPPI\\[n\\].PERM register content can be changed"]
+    #[inline(always)]
+    pub fn unlocked(self) -> &'a mut W {
+        self.variant(LOCK_A::UNLOCKED)
+    }
+}
+impl R {
+    #[doc = "Bit 0"]
+    #[inline(always)]
+    pub fn lock(&self) -> LOCK_R {
+        LOCK_R::new((self.bits & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0"]
+    #[inline(always)]
+    pub fn lock(&mut self) -> LOCK_W<0> {
+        LOCK_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Description cluster: Prevent further modification of the corresponding PERM register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lock](index.html) module"]
+pub struct LOCK_SPEC;
+impl crate::RegisterSpec for LOCK_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [lock::R](R) reader structure"]
+impl crate::Readable for LOCK_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [lock::W](W) writer structure"]
+impl crate::Writable for LOCK_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets LOCK to value 0"]
+impl crate::Resettable for LOCK_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9120-pac/src/spu_s/events_flashaccerr.rs

@@ -0,0 +1,127 @@
+#[doc = "Register `EVENTS_FLASHACCERR` reader"]
+pub struct R(crate::R<EVENTS_FLASHACCERR_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<EVENTS_FLASHACCERR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<EVENTS_FLASHACCERR_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<EVENTS_FLASHACCERR_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `EVENTS_FLASHACCERR` writer"]
+pub struct W(crate::W<EVENTS_FLASHACCERR_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<EVENTS_FLASHACCERR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<EVENTS_FLASHACCERR_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<EVENTS_FLASHACCERR_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `EVENTS_FLASHACCERR` reader - A security violation has been detected for the flash memory space"]
+pub type EVENTS_FLASHACCERR_R = crate::BitReader<EVENTS_FLASHACCERR_A>;
+#[doc = "A security violation has been detected for the flash memory space\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum EVENTS_FLASHACCERR_A {
+    #[doc = "0: Event not generated"]
+    NOT_GENERATED = 0,
+    #[doc = "1: Event generated"]
+    GENERATED = 1,
+}
+impl From<EVENTS_FLASHACCERR_A> for bool {
+    #[inline(always)]
+    fn from(variant: EVENTS_FLASHACCERR_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl EVENTS_FLASHACCERR_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> EVENTS_FLASHACCERR_A {
+        match self.bits {
+            false => EVENTS_FLASHACCERR_A::NOT_GENERATED,
+            true => EVENTS_FLASHACCERR_A::GENERATED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `NOT_GENERATED`"]
+    #[inline(always)]
+    pub fn is_not_generated(&self) -> bool {
+        *self == EVENTS_FLASHACCERR_A::NOT_GENERATED
+    }
+    #[doc = "Checks if the value of the field is `GENERATED`"]
+    #[inline(always)]
+    pub fn is_generated(&self) -> bool {
+        *self == EVENTS_FLASHACCERR_A::GENERATED
+    }
+}
+#[doc = "Field `EVENTS_FLASHACCERR` writer - A security violation has been detected for the flash memory space"]
+pub type EVENTS_FLASHACCERR_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, EVENTS_FLASHACCERR_SPEC, EVENTS_FLASHACCERR_A, O>;
+impl<'a, const O: u8> EVENTS_FLASHACCERR_W<'a, O> {
+    #[doc = "Event not generated"]
+    #[inline(always)]
+    pub fn not_generated(self) -> &'a mut W {
+        self.variant(EVENTS_FLASHACCERR_A::NOT_GENERATED)
+    }
+    #[doc = "Event generated"]
+    #[inline(always)]
+    pub fn generated(self) -> &'a mut W {
+        self.variant(EVENTS_FLASHACCERR_A::GENERATED)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - A security violation has been detected for the flash memory space"]
+    #[inline(always)]
+    pub fn events_flashaccerr(&self) -> EVENTS_FLASHACCERR_R {
+        EVENTS_FLASHACCERR_R::new((self.bits & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - A security violation has been detected for the flash memory space"]
+    #[inline(always)]
+    pub fn events_flashaccerr(&mut self) -> EVENTS_FLASHACCERR_W<0> {
+        EVENTS_FLASHACCERR_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "A security violation has been detected for the flash memory space\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_flashaccerr](index.html) module"]
+pub struct EVENTS_FLASHACCERR_SPEC;
+impl crate::RegisterSpec for EVENTS_FLASHACCERR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [events_flashaccerr::R](R) reader structure"]
+impl crate::Readable for EVENTS_FLASHACCERR_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [events_flashaccerr::W](W) writer structure"]
+impl crate::Writable for EVENTS_FLASHACCERR_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets EVENTS_FLASHACCERR to value 0"]
+impl crate::Resettable for EVENTS_FLASHACCERR_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9120-pac/src/spu_s/events_periphaccerr.rs

@@ -0,0 +1,127 @@
+#[doc = "Register `EVENTS_PERIPHACCERR` reader"]
+pub struct R(crate::R<EVENTS_PERIPHACCERR_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<EVENTS_PERIPHACCERR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<EVENTS_PERIPHACCERR_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<EVENTS_PERIPHACCERR_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `EVENTS_PERIPHACCERR` writer"]
+pub struct W(crate::W<EVENTS_PERIPHACCERR_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<EVENTS_PERIPHACCERR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<EVENTS_PERIPHACCERR_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<EVENTS_PERIPHACCERR_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `EVENTS_PERIPHACCERR` reader - A security violation has been detected on one or several peripherals"]
+pub type EVENTS_PERIPHACCERR_R = crate::BitReader<EVENTS_PERIPHACCERR_A>;
+#[doc = "A security violation has been detected on one or several peripherals\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum EVENTS_PERIPHACCERR_A {
+    #[doc = "0: Event not generated"]
+    NOT_GENERATED = 0,
+    #[doc = "1: Event generated"]
+    GENERATED = 1,
+}
+impl From<EVENTS_PERIPHACCERR_A> for bool {
+    #[inline(always)]
+    fn from(variant: EVENTS_PERIPHACCERR_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl EVENTS_PERIPHACCERR_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> EVENTS_PERIPHACCERR_A {
+        match self.bits {
+            false => EVENTS_PERIPHACCERR_A::NOT_GENERATED,
+            true => EVENTS_PERIPHACCERR_A::GENERATED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `NOT_GENERATED`"]
+    #[inline(always)]
+    pub fn is_not_generated(&self) -> bool {
+        *self == EVENTS_PERIPHACCERR_A::NOT_GENERATED
+    }
+    #[doc = "Checks if the value of the field is `GENERATED`"]
+    #[inline(always)]
+    pub fn is_generated(&self) -> bool {
+        *self == EVENTS_PERIPHACCERR_A::GENERATED
+    }
+}
+#[doc = "Field `EVENTS_PERIPHACCERR` writer - A security violation has been detected on one or several peripherals"]
+pub type EVENTS_PERIPHACCERR_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, EVENTS_PERIPHACCERR_SPEC, EVENTS_PERIPHACCERR_A, O>;
+impl<'a, const O: u8> EVENTS_PERIPHACCERR_W<'a, O> {
+    #[doc = "Event not generated"]
+    #[inline(always)]
+    pub fn not_generated(self) -> &'a mut W {
+        self.variant(EVENTS_PERIPHACCERR_A::NOT_GENERATED)
+    }
+    #[doc = "Event generated"]
+    #[inline(always)]
+    pub fn generated(self) -> &'a mut W {
+        self.variant(EVENTS_PERIPHACCERR_A::GENERATED)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - A security violation has been detected on one or several peripherals"]
+    #[inline(always)]
+    pub fn events_periphaccerr(&self) -> EVENTS_PERIPHACCERR_R {
+        EVENTS_PERIPHACCERR_R::new((self.bits & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - A security violation has been detected on one or several peripherals"]
+    #[inline(always)]
+    pub fn events_periphaccerr(&mut self) -> EVENTS_PERIPHACCERR_W<0> {
+        EVENTS_PERIPHACCERR_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "A security violation has been detected on one or several peripherals\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_periphaccerr](index.html) module"]
+pub struct EVENTS_PERIPHACCERR_SPEC;
+impl crate::RegisterSpec for EVENTS_PERIPHACCERR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [events_periphaccerr::R](R) reader structure"]
+impl crate::Readable for EVENTS_PERIPHACCERR_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [events_periphaccerr::W](W) writer structure"]
+impl crate::Writable for EVENTS_PERIPHACCERR_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets EVENTS_PERIPHACCERR to value 0"]
+impl crate::Resettable for EVENTS_PERIPHACCERR_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9120-pac/src/spu_s/events_ramaccerr.rs

@@ -0,0 +1,127 @@
+#[doc = "Register `EVENTS_RAMACCERR` reader"]
+pub struct R(crate::R<EVENTS_RAMACCERR_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<EVENTS_RAMACCERR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<EVENTS_RAMACCERR_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<EVENTS_RAMACCERR_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `EVENTS_RAMACCERR` writer"]
+pub struct W(crate::W<EVENTS_RAMACCERR_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<EVENTS_RAMACCERR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<EVENTS_RAMACCERR_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<EVENTS_RAMACCERR_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `EVENTS_RAMACCERR` reader - A security violation has been detected for the RAM memory space"]
+pub type EVENTS_RAMACCERR_R = crate::BitReader<EVENTS_RAMACCERR_A>;
+#[doc = "A security violation has been detected for the RAM memory space\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum EVENTS_RAMACCERR_A {
+    #[doc = "0: Event not generated"]
+    NOT_GENERATED = 0,
+    #[doc = "1: Event generated"]
+    GENERATED = 1,
+}
+impl From<EVENTS_RAMACCERR_A> for bool {
+    #[inline(always)]
+    fn from(variant: EVENTS_RAMACCERR_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl EVENTS_RAMACCERR_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> EVENTS_RAMACCERR_A {
+        match self.bits {
+            false => EVENTS_RAMACCERR_A::NOT_GENERATED,
+            true => EVENTS_RAMACCERR_A::GENERATED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `NOT_GENERATED`"]
+    #[inline(always)]
+    pub fn is_not_generated(&self) -> bool {
+        *self == EVENTS_RAMACCERR_A::NOT_GENERATED
+    }
+    #[doc = "Checks if the value of the field is `GENERATED`"]
+    #[inline(always)]
+    pub fn is_generated(&self) -> bool {
+        *self == EVENTS_RAMACCERR_A::GENERATED
+    }
+}
+#[doc = "Field `EVENTS_RAMACCERR` writer - A security violation has been detected for the RAM memory space"]
+pub type EVENTS_RAMACCERR_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, EVENTS_RAMACCERR_SPEC, EVENTS_RAMACCERR_A, O>;
+impl<'a, const O: u8> EVENTS_RAMACCERR_W<'a, O> {
+    #[doc = "Event not generated"]
+    #[inline(always)]
+    pub fn not_generated(self) -> &'a mut W {
+        self.variant(EVENTS_RAMACCERR_A::NOT_GENERATED)
+    }
+    #[doc = "Event generated"]
+    #[inline(always)]
+    pub fn generated(self) -> &'a mut W {
+        self.variant(EVENTS_RAMACCERR_A::GENERATED)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - A security violation has been detected for the RAM memory space"]
+    #[inline(always)]
+    pub fn events_ramaccerr(&self) -> EVENTS_RAMACCERR_R {
+        EVENTS_RAMACCERR_R::new((self.bits & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - A security violation has been detected for the RAM memory space"]
+    #[inline(always)]
+    pub fn events_ramaccerr(&mut self) -> EVENTS_RAMACCERR_W<0> {
+        EVENTS_RAMACCERR_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "A security violation has been detected for the RAM memory space\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_ramaccerr](index.html) module"]
+pub struct EVENTS_RAMACCERR_SPEC;
+impl crate::RegisterSpec for EVENTS_RAMACCERR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [events_ramaccerr::R](R) reader structure"]
+impl crate::Readable for EVENTS_RAMACCERR_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [events_ramaccerr::W](W) writer structure"]
+impl crate::Writable for EVENTS_RAMACCERR_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets EVENTS_RAMACCERR to value 0"]
+impl crate::Resettable for EVENTS_RAMACCERR_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9120-pac/src/spu_s/extdomain.rs

@@ -0,0 +1,10 @@
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct EXTDOMAIN {
+    #[doc = "0x00 - Description cluster: Access for bus access generated from the external domain n List capabilities of the external domain n"]
+    pub perm: PERM,
+}
+#[doc = "PERM (rw) register accessor: an alias for `Reg<PERM_SPEC>`"]
+pub type PERM = crate::Reg<perm::PERM_SPEC>;
+#[doc = "Description cluster: Access for bus access generated from the external domain n List capabilities of the external domain n"]
+pub mod perm;

vendor/nrf9120-pac/src/spu_s/extdomain/perm.rs

@@ -0,0 +1,237 @@
+#[doc = "Register `PERM` reader"]
+pub struct R(crate::R<PERM_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<PERM_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<PERM_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<PERM_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `PERM` writer"]
+pub struct W(crate::W<PERM_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<PERM_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<PERM_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<PERM_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `SECUREMAPPING` reader - Define configuration capabilities for TrustZone Cortex-M secure attribute"]
+pub type SECUREMAPPING_R = crate::FieldReader<u8, SECUREMAPPING_A>;
+#[doc = "Define configuration capabilities for TrustZone Cortex-M secure attribute\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum SECUREMAPPING_A {
+    #[doc = "0: The bus access from this external domain always have the non-secure attribute set"]
+    NON_SECURE = 0,
+    #[doc = "1: The bus access from this external domain always have the secure attribute set"]
+    SECURE = 1,
+    #[doc = "2: Non-secure or secure attribute for bus access from this domain is defined by the EXTDOMAIN\\[n\\].PERM register"]
+    USER_SELECTABLE = 2,
+}
+impl From<SECUREMAPPING_A> for u8 {
+    #[inline(always)]
+    fn from(variant: SECUREMAPPING_A) -> Self {
+        variant as _
+    }
+}
+impl SECUREMAPPING_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<SECUREMAPPING_A> {
+        match self.bits {
+            0 => Some(SECUREMAPPING_A::NON_SECURE),
+            1 => Some(SECUREMAPPING_A::SECURE),
+            2 => Some(SECUREMAPPING_A::USER_SELECTABLE),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `NON_SECURE`"]
+    #[inline(always)]
+    pub fn is_non_secure(&self) -> bool {
+        *self == SECUREMAPPING_A::NON_SECURE
+    }
+    #[doc = "Checks if the value of the field is `SECURE`"]
+    #[inline(always)]
+    pub fn is_secure(&self) -> bool {
+        *self == SECUREMAPPING_A::SECURE
+    }
+    #[doc = "Checks if the value of the field is `USER_SELECTABLE`"]
+    #[inline(always)]
+    pub fn is_user_selectable(&self) -> bool {
+        *self == SECUREMAPPING_A::USER_SELECTABLE
+    }
+}
+#[doc = "Field `SECATTR` reader - Peripheral security mapping"]
+pub type SECATTR_R = crate::BitReader<SECATTR_A>;
+#[doc = "Peripheral security mapping\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SECATTR_A {
+    #[doc = "0: Bus accesses from this domain have the non-secure attribute set"]
+    NON_SECURE = 0,
+    #[doc = "1: Bus accesses from this domain have secure attribute set"]
+    SECURE = 1,
+}
+impl From<SECATTR_A> for bool {
+    #[inline(always)]
+    fn from(variant: SECATTR_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl SECATTR_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> SECATTR_A {
+        match self.bits {
+            false => SECATTR_A::NON_SECURE,
+            true => SECATTR_A::SECURE,
+        }
+    }
+    #[doc = "Checks if the value of the field is `NON_SECURE`"]
+    #[inline(always)]
+    pub fn is_non_secure(&self) -> bool {
+        *self == SECATTR_A::NON_SECURE
+    }
+    #[doc = "Checks if the value of the field is `SECURE`"]
+    #[inline(always)]
+    pub fn is_secure(&self) -> bool {
+        *self == SECATTR_A::SECURE
+    }
+}
+#[doc = "Field `SECATTR` writer - Peripheral security mapping"]
+pub type SECATTR_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, SECATTR_A, O>;
+impl<'a, const O: u8> SECATTR_W<'a, O> {
+    #[doc = "Bus accesses from this domain have the non-secure attribute set"]
+    #[inline(always)]
+    pub fn non_secure(self) -> &'a mut W {
+        self.variant(SECATTR_A::NON_SECURE)
+    }
+    #[doc = "Bus accesses from this domain have secure attribute set"]
+    #[inline(always)]
+    pub fn secure(self) -> &'a mut W {
+        self.variant(SECATTR_A::SECURE)
+    }
+}
+#[doc = "Field `LOCK` reader - "]
+pub type LOCK_R = crate::BitReader<LOCK_A>;
+#[doc = "\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum LOCK_A {
+    #[doc = "0: This register can be updated"]
+    UNLOCKED = 0,
+    #[doc = "1: The content of this register can't be changed until the next reset"]
+    LOCKED = 1,
+}
+impl From<LOCK_A> for bool {
+    #[inline(always)]
+    fn from(variant: LOCK_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl LOCK_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> LOCK_A {
+        match self.bits {
+            false => LOCK_A::UNLOCKED,
+            true => LOCK_A::LOCKED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UNLOCKED`"]
+    #[inline(always)]
+    pub fn is_unlocked(&self) -> bool {
+        *self == LOCK_A::UNLOCKED
+    }
+    #[doc = "Checks if the value of the field is `LOCKED`"]
+    #[inline(always)]
+    pub fn is_locked(&self) -> bool {
+        *self == LOCK_A::LOCKED
+    }
+}
+#[doc = "Field `LOCK` writer - "]
+pub type LOCK_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, LOCK_A, O>;
+impl<'a, const O: u8> LOCK_W<'a, O> {
+    #[doc = "This register can be updated"]
+    #[inline(always)]
+    pub fn unlocked(self) -> &'a mut W {
+        self.variant(LOCK_A::UNLOCKED)
+    }
+    #[doc = "The content of this register can't be changed until the next reset"]
+    #[inline(always)]
+    pub fn locked(self) -> &'a mut W {
+        self.variant(LOCK_A::LOCKED)
+    }
+}
+impl R {
+    #[doc = "Bits 0:1 - Define configuration capabilities for TrustZone Cortex-M secure attribute"]
+    #[inline(always)]
+    pub fn securemapping(&self) -> SECUREMAPPING_R {
+        SECUREMAPPING_R::new((self.bits & 3) as u8)
+    }
+    #[doc = "Bit 4 - Peripheral security mapping"]
+    #[inline(always)]
+    pub fn secattr(&self) -> SECATTR_R {
+        SECATTR_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 8"]
+    #[inline(always)]
+    pub fn lock(&self) -> LOCK_R {
+        LOCK_R::new(((self.bits >> 8) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 4 - Peripheral security mapping"]
+    #[inline(always)]
+    pub fn secattr(&mut self) -> SECATTR_W<4> {
+        SECATTR_W::new(self)
+    }
+    #[doc = "Bit 8"]
+    #[inline(always)]
+    pub fn lock(&mut self) -> LOCK_W<8> {
+        LOCK_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Description cluster: Access for bus access generated from the external domain n List capabilities of the external domain n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perm](index.html) module"]
+pub struct PERM_SPEC;
+impl crate::RegisterSpec for PERM_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [perm::R](R) reader structure"]
+impl crate::Readable for PERM_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [perm::W](W) writer structure"]
+impl crate::Writable for PERM_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets PERM to value 0"]
+impl crate::Resettable for PERM_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9120-pac/src/spu_s/flashnsc.rs

@@ -0,0 +1,16 @@
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct FLASHNSC {
+    #[doc = "0x00 - Description cluster: Define which flash region can contain the non-secure callable (NSC) region n"]
+    pub region: REGION,
+    #[doc = "0x04 - Description cluster: Define the size of the non-secure callable (NSC) region n"]
+    pub size: SIZE,
+}
+#[doc = "REGION (rw) register accessor: an alias for `Reg<REGION_SPEC>`"]
+pub type REGION = crate::Reg<region::REGION_SPEC>;
+#[doc = "Description cluster: Define which flash region can contain the non-secure callable (NSC) region n"]
+pub mod region;
+#[doc = "SIZE (rw) register accessor: an alias for `Reg<SIZE_SPEC>`"]
+pub type SIZE = crate::Reg<size::SIZE_SPEC>;
+#[doc = "Description cluster: Define the size of the non-secure callable (NSC) region n"]
+pub mod size;

vendor/nrf9120-pac/src/spu_s/flashnsc/region.rs

@@ -0,0 +1,140 @@
+#[doc = "Register `REGION` reader"]
+pub struct R(crate::R<REGION_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<REGION_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<REGION_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<REGION_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `REGION` writer"]
+pub struct W(crate::W<REGION_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<REGION_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<REGION_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<REGION_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `REGION` reader - Region number"]
+pub type REGION_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `REGION` writer - Region number"]
+pub type REGION_W<'a, const O: u8> = crate::FieldWriter<'a, u32, REGION_SPEC, u8, u8, 5, O>;
+#[doc = "Field `LOCK` reader - "]
+pub type LOCK_R = crate::BitReader<LOCK_A>;
+#[doc = "\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum LOCK_A {
+    #[doc = "0: This register can be updated"]
+    UNLOCKED = 0,
+    #[doc = "1: The content of this register can't be changed until the next reset"]
+    LOCKED = 1,
+}
+impl From<LOCK_A> for bool {
+    #[inline(always)]
+    fn from(variant: LOCK_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl LOCK_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> LOCK_A {
+        match self.bits {
+            false => LOCK_A::UNLOCKED,
+            true => LOCK_A::LOCKED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UNLOCKED`"]
+    #[inline(always)]
+    pub fn is_unlocked(&self) -> bool {
+        *self == LOCK_A::UNLOCKED
+    }
+    #[doc = "Checks if the value of the field is `LOCKED`"]
+    #[inline(always)]
+    pub fn is_locked(&self) -> bool {
+        *self == LOCK_A::LOCKED
+    }
+}
+#[doc = "Field `LOCK` writer - "]
+pub type LOCK_W<'a, const O: u8> = crate::BitWriter<'a, u32, REGION_SPEC, LOCK_A, O>;
+impl<'a, const O: u8> LOCK_W<'a, O> {
+    #[doc = "This register can be updated"]
+    #[inline(always)]
+    pub fn unlocked(self) -> &'a mut W {
+        self.variant(LOCK_A::UNLOCKED)
+    }
+    #[doc = "The content of this register can't be changed until the next reset"]
+    #[inline(always)]
+    pub fn locked(self) -> &'a mut W {
+        self.variant(LOCK_A::LOCKED)
+    }
+}
+impl R {
+    #[doc = "Bits 0:4 - Region number"]
+    #[inline(always)]
+    pub fn region(&self) -> REGION_R {
+        REGION_R::new((self.bits & 0x1f) as u8)
+    }
+    #[doc = "Bit 8"]
+    #[inline(always)]
+    pub fn lock(&self) -> LOCK_R {
+        LOCK_R::new(((self.bits >> 8) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:4 - Region number"]
+    #[inline(always)]
+    pub fn region(&mut self) -> REGION_W<0> {
+        REGION_W::new(self)
+    }
+    #[doc = "Bit 8"]
+    #[inline(always)]
+    pub fn lock(&mut self) -> LOCK_W<8> {
+        LOCK_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Description cluster: Define which flash region can contain the non-secure callable (NSC) region n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [region](index.html) module"]
+pub struct REGION_SPEC;
+impl crate::RegisterSpec for REGION_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [region::R](R) reader structure"]
+impl crate::Readable for REGION_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [region::W](W) writer structure"]
+impl crate::Writable for REGION_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets REGION to value 0"]
+impl crate::Resettable for REGION_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9120-pac/src/spu_s/flashnsc/size.rs

@@ -0,0 +1,279 @@
+#[doc = "Register `SIZE` reader"]
+pub struct R(crate::R<SIZE_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<SIZE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<SIZE_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<SIZE_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `SIZE` writer"]
+pub struct W(crate::W<SIZE_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<SIZE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<SIZE_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<SIZE_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `SIZE` reader - Size of the non-secure callable (NSC) region n"]
+pub type SIZE_R = crate::FieldReader<u8, SIZE_A>;
+#[doc = "Size of the non-secure callable (NSC) region n\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum SIZE_A {
+    #[doc = "0: The region n is not defined as a non-secure callable region. Normal security attributes (secure or non-secure) are enforced."]
+    DISABLED = 0,
+    #[doc = "1: The region n is defined as non-secure callable with a 32-byte size"]
+    _32 = 1,
+    #[doc = "2: The region n is defined as non-secure callable with a 64-byte size"]
+    _64 = 2,
+    #[doc = "3: The region n is defined as non-secure callable with a 128-byte size"]
+    _128 = 3,
+    #[doc = "4: The region n is defined as non-secure callable with a 256-byte size"]
+    _256 = 4,
+    #[doc = "5: The region n is defined as non-secure callable with a 512-byte size"]
+    _512 = 5,
+    #[doc = "6: The region n is defined as non-secure callable with a 1024-byte size"]
+    _1024 = 6,
+    #[doc = "7: The region n is defined as non-secure callable with a 2048-byte size"]
+    _2048 = 7,
+    #[doc = "8: The region n is defined as non-secure callable with a 4096-byte size"]
+    _4096 = 8,
+}
+impl From<SIZE_A> for u8 {
+    #[inline(always)]
+    fn from(variant: SIZE_A) -> Self {
+        variant as _
+    }
+}
+impl SIZE_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<SIZE_A> {
+        match self.bits {
+            0 => Some(SIZE_A::DISABLED),
+            1 => Some(SIZE_A::_32),
+            2 => Some(SIZE_A::_64),
+            3 => Some(SIZE_A::_128),
+            4 => Some(SIZE_A::_256),
+            5 => Some(SIZE_A::_512),
+            6 => Some(SIZE_A::_1024),
+            7 => Some(SIZE_A::_2048),
+            8 => Some(SIZE_A::_4096),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == SIZE_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `_32`"]
+    #[inline(always)]
+    pub fn is_32(&self) -> bool {
+        *self == SIZE_A::_32
+    }
+    #[doc = "Checks if the value of the field is `_64`"]
+    #[inline(always)]
+    pub fn is_64(&self) -> bool {
+        *self == SIZE_A::_64
+    }
+    #[doc = "Checks if the value of the field is `_128`"]
+    #[inline(always)]
+    pub fn is_128(&self) -> bool {
+        *self == SIZE_A::_128
+    }
+    #[doc = "Checks if the value of the field is `_256`"]
+    #[inline(always)]
+    pub fn is_256(&self) -> bool {
+        *self == SIZE_A::_256
+    }
+    #[doc = "Checks if the value of the field is `_512`"]
+    #[inline(always)]
+    pub fn is_512(&self) -> bool {
+        *self == SIZE_A::_512
+    }
+    #[doc = "Checks if the value of the field is `_1024`"]
+    #[inline(always)]
+    pub fn is_1024(&self) -> bool {
+        *self == SIZE_A::_1024
+    }
+    #[doc = "Checks if the value of the field is `_2048`"]
+    #[inline(always)]
+    pub fn is_2048(&self) -> bool {
+        *self == SIZE_A::_2048
+    }
+    #[doc = "Checks if the value of the field is `_4096`"]
+    #[inline(always)]
+    pub fn is_4096(&self) -> bool {
+        *self == SIZE_A::_4096
+    }
+}
+#[doc = "Field `SIZE` writer - Size of the non-secure callable (NSC) region n"]
+pub type SIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SIZE_SPEC, u8, SIZE_A, 4, O>;
+impl<'a, const O: u8> SIZE_W<'a, O> {
+    #[doc = "The region n is not defined as a non-secure callable region. Normal security attributes (secure or non-secure) are enforced."]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(SIZE_A::DISABLED)
+    }
+    #[doc = "The region n is defined as non-secure callable with a 32-byte size"]
+    #[inline(always)]
+    pub fn _32(self) -> &'a mut W {
+        self.variant(SIZE_A::_32)
+    }
+    #[doc = "The region n is defined as non-secure callable with a 64-byte size"]
+    #[inline(always)]
+    pub fn _64(self) -> &'a mut W {
+        self.variant(SIZE_A::_64)
+    }
+    #[doc = "The region n is defined as non-secure callable with a 128-byte size"]
+    #[inline(always)]
+    pub fn _128(self) -> &'a mut W {
+        self.variant(SIZE_A::_128)
+    }
+    #[doc = "The region n is defined as non-secure callable with a 256-byte size"]
+    #[inline(always)]
+    pub fn _256(self) -> &'a mut W {
+        self.variant(SIZE_A::_256)
+    }
+    #[doc = "The region n is defined as non-secure callable with a 512-byte size"]
+    #[inline(always)]
+    pub fn _512(self) -> &'a mut W {
+        self.variant(SIZE_A::_512)
+    }
+    #[doc = "The region n is defined as non-secure callable with a 1024-byte size"]
+    #[inline(always)]
+    pub fn _1024(self) -> &'a mut W {
+        self.variant(SIZE_A::_1024)
+    }
+    #[doc = "The region n is defined as non-secure callable with a 2048-byte size"]
+    #[inline(always)]
+    pub fn _2048(self) -> &'a mut W {
+        self.variant(SIZE_A::_2048)
+    }
+    #[doc = "The region n is defined as non-secure callable with a 4096-byte size"]
+    #[inline(always)]
+    pub fn _4096(self) -> &'a mut W {
+        self.variant(SIZE_A::_4096)
+    }
+}
+#[doc = "Field `LOCK` reader - "]
+pub type LOCK_R = crate::BitReader<LOCK_A>;
+#[doc = "\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum LOCK_A {
+    #[doc = "0: This register can be updated"]
+    UNLOCKED = 0,
+    #[doc = "1: The content of this register can't be changed until the next reset"]
+    LOCKED = 1,
+}
+impl From<LOCK_A> for bool {
+    #[inline(always)]
+    fn from(variant: LOCK_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl LOCK_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> LOCK_A {
+        match self.bits {
+            false => LOCK_A::UNLOCKED,
+            true => LOCK_A::LOCKED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UNLOCKED`"]
+    #[inline(always)]
+    pub fn is_unlocked(&self) -> bool {
+        *self == LOCK_A::UNLOCKED
+    }
+    #[doc = "Checks if the value of the field is `LOCKED`"]
+    #[inline(always)]
+    pub fn is_locked(&self) -> bool {
+        *self == LOCK_A::LOCKED
+    }
+}
+#[doc = "Field `LOCK` writer - "]
+pub type LOCK_W<'a, const O: u8> = crate::BitWriter<'a, u32, SIZE_SPEC, LOCK_A, O>;
+impl<'a, const O: u8> LOCK_W<'a, O> {
+    #[doc = "This register can be updated"]
+    #[inline(always)]
+    pub fn unlocked(self) -> &'a mut W {
+        self.variant(LOCK_A::UNLOCKED)
+    }
+    #[doc = "The content of this register can't be changed until the next reset"]
+    #[inline(always)]
+    pub fn locked(self) -> &'a mut W {
+        self.variant(LOCK_A::LOCKED)
+    }
+}
+impl R {
+    #[doc = "Bits 0:3 - Size of the non-secure callable (NSC) region n"]
+    #[inline(always)]
+    pub fn size(&self) -> SIZE_R {
+        SIZE_R::new((self.bits & 0x0f) as u8)
+    }
+    #[doc = "Bit 8"]
+    #[inline(always)]
+    pub fn lock(&self) -> LOCK_R {
+        LOCK_R::new(((self.bits >> 8) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:3 - Size of the non-secure callable (NSC) region n"]
+    #[inline(always)]
+    pub fn size(&mut self) -> SIZE_W<0> {
+        SIZE_W::new(self)
+    }
+    #[doc = "Bit 8"]
+    #[inline(always)]
+    pub fn lock(&mut self) -> LOCK_W<8> {
+        LOCK_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Description cluster: Define the size of the non-secure callable (NSC) region n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [size](index.html) module"]
+pub struct SIZE_SPEC;
+impl crate::RegisterSpec for SIZE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [size::R](R) reader structure"]
+impl crate::Readable for SIZE_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [size::W](W) writer structure"]
+impl crate::Writable for SIZE_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets SIZE to value 0"]
+impl crate::Resettable for SIZE_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9120-pac/src/spu_s/flashregion.rs

@@ -0,0 +1,10 @@
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct FLASHREGION {
+    #[doc = "0x00 - Description cluster: Access permissions for flash region n"]
+    pub perm: PERM,
+}
+#[doc = "PERM (rw) register accessor: an alias for `Reg<PERM_SPEC>`"]
+pub type PERM = crate::Reg<perm::PERM_SPEC>;
+#[doc = "Description cluster: Access permissions for flash region n"]
+pub mod perm;

vendor/nrf9120-pac/src/spu_s/flashregion/perm.rs

@@ -0,0 +1,366 @@
+#[doc = "Register `PERM` reader"]
+pub struct R(crate::R<PERM_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<PERM_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<PERM_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<PERM_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `PERM` writer"]
+pub struct W(crate::W<PERM_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<PERM_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<PERM_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<PERM_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `EXECUTE` reader - Configure instruction fetch permissions from flash region n"]
+pub type EXECUTE_R = crate::BitReader<EXECUTE_A>;
+#[doc = "Configure instruction fetch permissions from flash region n\n\nValue on reset: 1"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum EXECUTE_A {
+    #[doc = "1: Allow instruction fetches from flash region n"]
+    ENABLE = 1,
+    #[doc = "0: Block instruction fetches from flash region n"]
+    DISABLE = 0,
+}
+impl From<EXECUTE_A> for bool {
+    #[inline(always)]
+    fn from(variant: EXECUTE_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl EXECUTE_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> EXECUTE_A {
+        match self.bits {
+            true => EXECUTE_A::ENABLE,
+            false => EXECUTE_A::DISABLE,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ENABLE`"]
+    #[inline(always)]
+    pub fn is_enable(&self) -> bool {
+        *self == EXECUTE_A::ENABLE
+    }
+    #[doc = "Checks if the value of the field is `DISABLE`"]
+    #[inline(always)]
+    pub fn is_disable(&self) -> bool {
+        *self == EXECUTE_A::DISABLE
+    }
+}
+#[doc = "Field `EXECUTE` writer - Configure instruction fetch permissions from flash region n"]
+pub type EXECUTE_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, EXECUTE_A, O>;
+impl<'a, const O: u8> EXECUTE_W<'a, O> {
+    #[doc = "Allow instruction fetches from flash region n"]
+    #[inline(always)]
+    pub fn enable(self) -> &'a mut W {
+        self.variant(EXECUTE_A::ENABLE)
+    }
+    #[doc = "Block instruction fetches from flash region n"]
+    #[inline(always)]
+    pub fn disable(self) -> &'a mut W {
+        self.variant(EXECUTE_A::DISABLE)
+    }
+}
+#[doc = "Field `WRITE` reader - Configure write permission for flash region n"]
+pub type WRITE_R = crate::BitReader<WRITE_A>;
+#[doc = "Configure write permission for flash region n\n\nValue on reset: 1"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum WRITE_A {
+    #[doc = "1: Allow write operation to region n"]
+    ENABLE = 1,
+    #[doc = "0: Block write operation to region n"]
+    DISABLE = 0,
+}
+impl From<WRITE_A> for bool {
+    #[inline(always)]
+    fn from(variant: WRITE_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl WRITE_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> WRITE_A {
+        match self.bits {
+            true => WRITE_A::ENABLE,
+            false => WRITE_A::DISABLE,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ENABLE`"]
+    #[inline(always)]
+    pub fn is_enable(&self) -> bool {
+        *self == WRITE_A::ENABLE
+    }
+    #[doc = "Checks if the value of the field is `DISABLE`"]
+    #[inline(always)]
+    pub fn is_disable(&self) -> bool {
+        *self == WRITE_A::DISABLE
+    }
+}
+#[doc = "Field `WRITE` writer - Configure write permission for flash region n"]
+pub type WRITE_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, WRITE_A, O>;
+impl<'a, const O: u8> WRITE_W<'a, O> {
+    #[doc = "Allow write operation to region n"]
+    #[inline(always)]
+    pub fn enable(self) -> &'a mut W {
+        self.variant(WRITE_A::ENABLE)
+    }
+    #[doc = "Block write operation to region n"]
+    #[inline(always)]
+    pub fn disable(self) -> &'a mut W {
+        self.variant(WRITE_A::DISABLE)
+    }
+}
+#[doc = "Field `READ` reader - Configure read permissions for flash region n"]
+pub type READ_R = crate::BitReader<READ_A>;
+#[doc = "Configure read permissions for flash region n\n\nValue on reset: 1"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum READ_A {
+    #[doc = "1: Allow read operation from flash region n"]
+    ENABLE = 1,
+    #[doc = "0: Block read operation from flash region n"]
+    DISABLE = 0,
+}
+impl From<READ_A> for bool {
+    #[inline(always)]
+    fn from(variant: READ_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl READ_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> READ_A {
+        match self.bits {
+            true => READ_A::ENABLE,
+            false => READ_A::DISABLE,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ENABLE`"]
+    #[inline(always)]
+    pub fn is_enable(&self) -> bool {
+        *self == READ_A::ENABLE
+    }
+    #[doc = "Checks if the value of the field is `DISABLE`"]
+    #[inline(always)]
+    pub fn is_disable(&self) -> bool {
+        *self == READ_A::DISABLE
+    }
+}
+#[doc = "Field `READ` writer - Configure read permissions for flash region n"]
+pub type READ_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, READ_A, O>;
+impl<'a, const O: u8> READ_W<'a, O> {
+    #[doc = "Allow read operation from flash region n"]
+    #[inline(always)]
+    pub fn enable(self) -> &'a mut W {
+        self.variant(READ_A::ENABLE)
+    }
+    #[doc = "Block read operation from flash region n"]
+    #[inline(always)]
+    pub fn disable(self) -> &'a mut W {
+        self.variant(READ_A::DISABLE)
+    }
+}
+#[doc = "Field `SECATTR` reader - Security attribute for flash region n"]
+pub type SECATTR_R = crate::BitReader<SECATTR_A>;
+#[doc = "Security attribute for flash region n\n\nValue on reset: 1"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SECATTR_A {
+    #[doc = "0: Flash region n security attribute is non-secure"]
+    NON_SECURE = 0,
+    #[doc = "1: Flash region n security attribute is secure"]
+    SECURE = 1,
+}
+impl From<SECATTR_A> for bool {
+    #[inline(always)]
+    fn from(variant: SECATTR_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl SECATTR_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> SECATTR_A {
+        match self.bits {
+            false => SECATTR_A::NON_SECURE,
+            true => SECATTR_A::SECURE,
+        }
+    }
+    #[doc = "Checks if the value of the field is `NON_SECURE`"]
+    #[inline(always)]
+    pub fn is_non_secure(&self) -> bool {
+        *self == SECATTR_A::NON_SECURE
+    }
+    #[doc = "Checks if the value of the field is `SECURE`"]
+    #[inline(always)]
+    pub fn is_secure(&self) -> bool {
+        *self == SECATTR_A::SECURE
+    }
+}
+#[doc = "Field `SECATTR` writer - Security attribute for flash region n"]
+pub type SECATTR_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, SECATTR_A, O>;
+impl<'a, const O: u8> SECATTR_W<'a, O> {
+    #[doc = "Flash region n security attribute is non-secure"]
+    #[inline(always)]
+    pub fn non_secure(self) -> &'a mut W {
+        self.variant(SECATTR_A::NON_SECURE)
+    }
+    #[doc = "Flash region n security attribute is secure"]
+    #[inline(always)]
+    pub fn secure(self) -> &'a mut W {
+        self.variant(SECATTR_A::SECURE)
+    }
+}
+#[doc = "Field `LOCK` reader - "]
+pub type LOCK_R = crate::BitReader<LOCK_A>;
+#[doc = "\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum LOCK_A {
+    #[doc = "0: This register can be updated"]
+    UNLOCKED = 0,
+    #[doc = "1: The content of this register can't be changed until the next reset"]
+    LOCKED = 1,
+}
+impl From<LOCK_A> for bool {
+    #[inline(always)]
+    fn from(variant: LOCK_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl LOCK_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> LOCK_A {
+        match self.bits {
+            false => LOCK_A::UNLOCKED,
+            true => LOCK_A::LOCKED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UNLOCKED`"]
+    #[inline(always)]
+    pub fn is_unlocked(&self) -> bool {
+        *self == LOCK_A::UNLOCKED
+    }
+    #[doc = "Checks if the value of the field is `LOCKED`"]
+    #[inline(always)]
+    pub fn is_locked(&self) -> bool {
+        *self == LOCK_A::LOCKED
+    }
+}
+#[doc = "Field `LOCK` writer - "]
+pub type LOCK_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, LOCK_A, O>;
+impl<'a, const O: u8> LOCK_W<'a, O> {
+    #[doc = "This register can be updated"]
+    #[inline(always)]
+    pub fn unlocked(self) -> &'a mut W {
+        self.variant(LOCK_A::UNLOCKED)
+    }
+    #[doc = "The content of this register can't be changed until the next reset"]
+    #[inline(always)]
+    pub fn locked(self) -> &'a mut W {
+        self.variant(LOCK_A::LOCKED)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Configure instruction fetch permissions from flash region n"]
+    #[inline(always)]
+    pub fn execute(&self) -> EXECUTE_R {
+        EXECUTE_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Configure write permission for flash region n"]
+    #[inline(always)]
+    pub fn write(&self) -> WRITE_R {
+        WRITE_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Configure read permissions for flash region n"]
+    #[inline(always)]
+    pub fn read(&self) -> READ_R {
+        READ_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Security attribute for flash region n"]
+    #[inline(always)]
+    pub fn secattr(&self) -> SECATTR_R {
+        SECATTR_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 8"]
+    #[inline(always)]
+    pub fn lock(&self) -> LOCK_R {
+        LOCK_R::new(((self.bits >> 8) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Configure instruction fetch permissions from flash region n"]
+    #[inline(always)]
+    pub fn execute(&mut self) -> EXECUTE_W<0> {
+        EXECUTE_W::new(self)
+    }
+    #[doc = "Bit 1 - Configure write permission for flash region n"]
+    #[inline(always)]
+    pub fn write(&mut self) -> WRITE_W<1> {
+        WRITE_W::new(self)
+    }
+    #[doc = "Bit 2 - Configure read permissions for flash region n"]
+    #[inline(always)]
+    pub fn read(&mut self) -> READ_W<2> {
+        READ_W::new(self)
+    }
+    #[doc = "Bit 4 - Security attribute for flash region n"]
+    #[inline(always)]
+    pub fn secattr(&mut self) -> SECATTR_W<4> {
+        SECATTR_W::new(self)
+    }
+    #[doc = "Bit 8"]
+    #[inline(always)]
+    pub fn lock(&mut self) -> LOCK_W<8> {
+        LOCK_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Description cluster: Access permissions for flash region n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perm](index.html) module"]
+pub struct PERM_SPEC;
+impl crate::RegisterSpec for PERM_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [perm::R](R) reader structure"]
+impl crate::Readable for PERM_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [perm::W](W) writer structure"]
+impl crate::Writable for PERM_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets PERM to value 0x17"]
+impl crate::Resettable for PERM_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0x17
+    }
+}

vendor/nrf9120-pac/src/spu_s/gpioport.rs

@@ -0,0 +1,16 @@
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct GPIOPORT {
+    #[doc = "0x00 - Description cluster: Select between secure and non-secure attribute for pins 0 to 31 of port n."]
+    pub perm: PERM,
+    #[doc = "0x04 - Description cluster: Prevent further modification of the corresponding PERM register"]
+    pub lock: LOCK,
+}
+#[doc = "PERM (rw) register accessor: an alias for `Reg<PERM_SPEC>`"]
+pub type PERM = crate::Reg<perm::PERM_SPEC>;
+#[doc = "Description cluster: Select between secure and non-secure attribute for pins 0 to 31 of port n."]
+pub mod perm;
+#[doc = "LOCK (rw) register accessor: an alias for `Reg<LOCK_SPEC>`"]
+pub type LOCK = crate::Reg<lock::LOCK_SPEC>;
+#[doc = "Description cluster: Prevent further modification of the corresponding PERM register"]
+pub mod lock;

vendor/nrf9120-pac/src/spu_s/gpioport/lock.rs

@@ -0,0 +1,126 @@
+#[doc = "Register `LOCK` reader"]
+pub struct R(crate::R<LOCK_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<LOCK_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<LOCK_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<LOCK_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `LOCK` writer"]
+pub struct W(crate::W<LOCK_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<LOCK_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<LOCK_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<LOCK_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `LOCK` reader - "]
+pub type LOCK_R = crate::BitReader<LOCK_A>;
+#[doc = "\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum LOCK_A {
+    #[doc = "1: GPIOPORT\\[n\\].PERM register can't be changed until next reset"]
+    LOCKED = 1,
+    #[doc = "0: GPIOPORT\\[n\\].PERM register content can be changed"]
+    UNLOCKED = 0,
+}
+impl From<LOCK_A> for bool {
+    #[inline(always)]
+    fn from(variant: LOCK_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl LOCK_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> LOCK_A {
+        match self.bits {
+            true => LOCK_A::LOCKED,
+            false => LOCK_A::UNLOCKED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `LOCKED`"]
+    #[inline(always)]
+    pub fn is_locked(&self) -> bool {
+        *self == LOCK_A::LOCKED
+    }
+    #[doc = "Checks if the value of the field is `UNLOCKED`"]
+    #[inline(always)]
+    pub fn is_unlocked(&self) -> bool {
+        *self == LOCK_A::UNLOCKED
+    }
+}
+#[doc = "Field `LOCK` writer - "]
+pub type LOCK_W<'a, const O: u8> = crate::BitWriter<'a, u32, LOCK_SPEC, LOCK_A, O>;
+impl<'a, const O: u8> LOCK_W<'a, O> {
+    #[doc = "GPIOPORT\\[n\\].PERM register can't be changed until next reset"]
+    #[inline(always)]
+    pub fn locked(self) -> &'a mut W {
+        self.variant(LOCK_A::LOCKED)
+    }
+    #[doc = "GPIOPORT\\[n\\].PERM register content can be changed"]
+    #[inline(always)]
+    pub fn unlocked(self) -> &'a mut W {
+        self.variant(LOCK_A::UNLOCKED)
+    }
+}
+impl R {
+    #[doc = "Bit 0"]
+    #[inline(always)]
+    pub fn lock(&self) -> LOCK_R {
+        LOCK_R::new((self.bits & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0"]
+    #[inline(always)]
+    pub fn lock(&mut self) -> LOCK_W<0> {
+        LOCK_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Description cluster: Prevent further modification of the corresponding PERM register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lock](index.html) module"]
+pub struct LOCK_SPEC;
+impl crate::RegisterSpec for LOCK_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [lock::R](R) reader structure"]
+impl crate::Readable for LOCK_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [lock::W](W) writer structure"]
+impl crate::Writable for LOCK_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets LOCK to value 0"]
+impl crate::Resettable for LOCK_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9120-pac/src/spu_s/inten.rs

@@ -0,0 +1,246 @@
+#[doc = "Register `INTEN` reader"]
+pub struct R(crate::R<INTEN_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<INTEN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<INTEN_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<INTEN_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `INTEN` writer"]
+pub struct W(crate::W<INTEN_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<INTEN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<INTEN_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<INTEN_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `RAMACCERR` reader - Enable or disable interrupt for event RAMACCERR"]
+pub type RAMACCERR_R = crate::BitReader<RAMACCERR_A>;
+#[doc = "Enable or disable interrupt for event RAMACCERR\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum RAMACCERR_A {
+    #[doc = "0: Disable"]
+    DISABLED = 0,
+    #[doc = "1: Enable"]
+    ENABLED = 1,
+}
+impl From<RAMACCERR_A> for bool {
+    #[inline(always)]
+    fn from(variant: RAMACCERR_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl RAMACCERR_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> RAMACCERR_A {
+        match self.bits {
+            false => RAMACCERR_A::DISABLED,
+            true => RAMACCERR_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == RAMACCERR_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == RAMACCERR_A::ENABLED
+    }
+}
+#[doc = "Field `RAMACCERR` writer - Enable or disable interrupt for event RAMACCERR"]
+pub type RAMACCERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, RAMACCERR_A, O>;
+impl<'a, const O: u8> RAMACCERR_W<'a, O> {
+    #[doc = "Disable"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(RAMACCERR_A::DISABLED)
+    }
+    #[doc = "Enable"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(RAMACCERR_A::ENABLED)
+    }
+}
+#[doc = "Field `FLASHACCERR` reader - Enable or disable interrupt for event FLASHACCERR"]
+pub type FLASHACCERR_R = crate::BitReader<FLASHACCERR_A>;
+#[doc = "Enable or disable interrupt for event FLASHACCERR\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FLASHACCERR_A {
+    #[doc = "0: Disable"]
+    DISABLED = 0,
+    #[doc = "1: Enable"]
+    ENABLED = 1,
+}
+impl From<FLASHACCERR_A> for bool {
+    #[inline(always)]
+    fn from(variant: FLASHACCERR_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl FLASHACCERR_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> FLASHACCERR_A {
+        match self.bits {
+            false => FLASHACCERR_A::DISABLED,
+            true => FLASHACCERR_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == FLASHACCERR_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == FLASHACCERR_A::ENABLED
+    }
+}
+#[doc = "Field `FLASHACCERR` writer - Enable or disable interrupt for event FLASHACCERR"]
+pub type FLASHACCERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, FLASHACCERR_A, O>;
+impl<'a, const O: u8> FLASHACCERR_W<'a, O> {
+    #[doc = "Disable"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(FLASHACCERR_A::DISABLED)
+    }
+    #[doc = "Enable"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(FLASHACCERR_A::ENABLED)
+    }
+}
+#[doc = "Field `PERIPHACCERR` reader - Enable or disable interrupt for event PERIPHACCERR"]
+pub type PERIPHACCERR_R = crate::BitReader<PERIPHACCERR_A>;
+#[doc = "Enable or disable interrupt for event PERIPHACCERR\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum PERIPHACCERR_A {
+    #[doc = "0: Disable"]
+    DISABLED = 0,
+    #[doc = "1: Enable"]
+    ENABLED = 1,
+}
+impl From<PERIPHACCERR_A> for bool {
+    #[inline(always)]
+    fn from(variant: PERIPHACCERR_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl PERIPHACCERR_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> PERIPHACCERR_A {
+        match self.bits {
+            false => PERIPHACCERR_A::DISABLED,
+            true => PERIPHACCERR_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == PERIPHACCERR_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == PERIPHACCERR_A::ENABLED
+    }
+}
+#[doc = "Field `PERIPHACCERR` writer - Enable or disable interrupt for event PERIPHACCERR"]
+pub type PERIPHACCERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, PERIPHACCERR_A, O>;
+impl<'a, const O: u8> PERIPHACCERR_W<'a, O> {
+    #[doc = "Disable"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(PERIPHACCERR_A::DISABLED)
+    }
+    #[doc = "Enable"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(PERIPHACCERR_A::ENABLED)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Enable or disable interrupt for event RAMACCERR"]
+    #[inline(always)]
+    pub fn ramaccerr(&self) -> RAMACCERR_R {
+        RAMACCERR_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Enable or disable interrupt for event FLASHACCERR"]
+    #[inline(always)]
+    pub fn flashaccerr(&self) -> FLASHACCERR_R {
+        FLASHACCERR_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Enable or disable interrupt for event PERIPHACCERR"]
+    #[inline(always)]
+    pub fn periphaccerr(&self) -> PERIPHACCERR_R {
+        PERIPHACCERR_R::new(((self.bits >> 2) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Enable or disable interrupt for event RAMACCERR"]
+    #[inline(always)]
+    pub fn ramaccerr(&mut self) -> RAMACCERR_W<0> {
+        RAMACCERR_W::new(self)
+    }
+    #[doc = "Bit 1 - Enable or disable interrupt for event FLASHACCERR"]
+    #[inline(always)]
+    pub fn flashaccerr(&mut self) -> FLASHACCERR_W<1> {
+        FLASHACCERR_W::new(self)
+    }
+    #[doc = "Bit 2 - Enable or disable interrupt for event PERIPHACCERR"]
+    #[inline(always)]
+    pub fn periphaccerr(&mut self) -> PERIPHACCERR_W<2> {
+        PERIPHACCERR_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Enable or disable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [inten](index.html) module"]
+pub struct INTEN_SPEC;
+impl crate::RegisterSpec for INTEN_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [inten::R](R) reader structure"]
+impl crate::Readable for INTEN_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [inten::W](W) writer structure"]
+impl crate::Writable for INTEN_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets INTEN to value 0"]
+impl crate::Resettable for INTEN_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9120-pac/src/spu_s/intenclr.rs

@@ -0,0 +1,269 @@
+#[doc = "Register `INTENCLR` reader"]
+pub struct R(crate::R<INTENCLR_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<INTENCLR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<INTENCLR_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<INTENCLR_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `INTENCLR` writer"]
+pub struct W(crate::W<INTENCLR_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<INTENCLR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<INTENCLR_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<INTENCLR_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `RAMACCERR` reader - Write '1' to disable interrupt for event RAMACCERR"]
+pub type RAMACCERR_R = crate::BitReader<RAMACCERR_A>;
+#[doc = "Write '1' to disable interrupt for event RAMACCERR\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum RAMACCERR_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<RAMACCERR_A> for bool {
+    #[inline(always)]
+    fn from(variant: RAMACCERR_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl RAMACCERR_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> RAMACCERR_A {
+        match self.bits {
+            false => RAMACCERR_A::DISABLED,
+            true => RAMACCERR_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == RAMACCERR_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == RAMACCERR_A::ENABLED
+    }
+}
+#[doc = "Write '1' to disable interrupt for event RAMACCERR\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum RAMACCERR_AW {
+    #[doc = "1: Disable"]
+    CLEAR = 1,
+}
+impl From<RAMACCERR_AW> for bool {
+    #[inline(always)]
+    fn from(variant: RAMACCERR_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `RAMACCERR` writer - Write '1' to disable interrupt for event RAMACCERR"]
+pub type RAMACCERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, RAMACCERR_AW, O>;
+impl<'a, const O: u8> RAMACCERR_W<'a, O> {
+    #[doc = "Disable"]
+    #[inline(always)]
+    pub fn clear(self) -> &'a mut W {
+        self.variant(RAMACCERR_AW::CLEAR)
+    }
+}
+#[doc = "Field `FLASHACCERR` reader - Write '1' to disable interrupt for event FLASHACCERR"]
+pub type FLASHACCERR_R = crate::BitReader<FLASHACCERR_A>;
+#[doc = "Write '1' to disable interrupt for event FLASHACCERR\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FLASHACCERR_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<FLASHACCERR_A> for bool {
+    #[inline(always)]
+    fn from(variant: FLASHACCERR_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl FLASHACCERR_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> FLASHACCERR_A {
+        match self.bits {
+            false => FLASHACCERR_A::DISABLED,
+            true => FLASHACCERR_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == FLASHACCERR_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == FLASHACCERR_A::ENABLED
+    }
+}
+#[doc = "Write '1' to disable interrupt for event FLASHACCERR\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FLASHACCERR_AW {
+    #[doc = "1: Disable"]
+    CLEAR = 1,
+}
+impl From<FLASHACCERR_AW> for bool {
+    #[inline(always)]
+    fn from(variant: FLASHACCERR_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `FLASHACCERR` writer - Write '1' to disable interrupt for event FLASHACCERR"]
+pub type FLASHACCERR_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, INTENCLR_SPEC, FLASHACCERR_AW, O>;
+impl<'a, const O: u8> FLASHACCERR_W<'a, O> {
+    #[doc = "Disable"]
+    #[inline(always)]
+    pub fn clear(self) -> &'a mut W {
+        self.variant(FLASHACCERR_AW::CLEAR)
+    }
+}
+#[doc = "Field `PERIPHACCERR` reader - Write '1' to disable interrupt for event PERIPHACCERR"]
+pub type PERIPHACCERR_R = crate::BitReader<PERIPHACCERR_A>;
+#[doc = "Write '1' to disable interrupt for event PERIPHACCERR\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum PERIPHACCERR_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<PERIPHACCERR_A> for bool {
+    #[inline(always)]
+    fn from(variant: PERIPHACCERR_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl PERIPHACCERR_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> PERIPHACCERR_A {
+        match self.bits {
+            false => PERIPHACCERR_A::DISABLED,
+            true => PERIPHACCERR_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == PERIPHACCERR_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == PERIPHACCERR_A::ENABLED
+    }
+}
+#[doc = "Write '1' to disable interrupt for event PERIPHACCERR\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum PERIPHACCERR_AW {
+    #[doc = "1: Disable"]
+    CLEAR = 1,
+}
+impl From<PERIPHACCERR_AW> for bool {
+    #[inline(always)]
+    fn from(variant: PERIPHACCERR_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `PERIPHACCERR` writer - Write '1' to disable interrupt for event PERIPHACCERR"]
+pub type PERIPHACCERR_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, INTENCLR_SPEC, PERIPHACCERR_AW, O>;
+impl<'a, const O: u8> PERIPHACCERR_W<'a, O> {
+    #[doc = "Disable"]
+    #[inline(always)]
+    pub fn clear(self) -> &'a mut W {
+        self.variant(PERIPHACCERR_AW::CLEAR)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Write '1' to disable interrupt for event RAMACCERR"]
+    #[inline(always)]
+    pub fn ramaccerr(&self) -> RAMACCERR_R {
+        RAMACCERR_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Write '1' to disable interrupt for event FLASHACCERR"]
+    #[inline(always)]
+    pub fn flashaccerr(&self) -> FLASHACCERR_R {
+        FLASHACCERR_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Write '1' to disable interrupt for event PERIPHACCERR"]
+    #[inline(always)]
+    pub fn periphaccerr(&self) -> PERIPHACCERR_R {
+        PERIPHACCERR_R::new(((self.bits >> 2) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Write '1' to disable interrupt for event RAMACCERR"]
+    #[inline(always)]
+    pub fn ramaccerr(&mut self) -> RAMACCERR_W<0> {
+        RAMACCERR_W::new(self)
+    }
+    #[doc = "Bit 1 - Write '1' to disable interrupt for event FLASHACCERR"]
+    #[inline(always)]
+    pub fn flashaccerr(&mut self) -> FLASHACCERR_W<1> {
+        FLASHACCERR_W::new(self)
+    }
+    #[doc = "Bit 2 - Write '1' to disable interrupt for event PERIPHACCERR"]
+    #[inline(always)]
+    pub fn periphaccerr(&mut self) -> PERIPHACCERR_W<2> {
+        PERIPHACCERR_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Disable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"]
+pub struct INTENCLR_SPEC;
+impl crate::RegisterSpec for INTENCLR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [intenclr::R](R) reader structure"]
+impl crate::Readable for INTENCLR_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"]
+impl crate::Writable for INTENCLR_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets INTENCLR to value 0"]
+impl crate::Resettable for INTENCLR_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9120-pac/src/spu_s/intenset.rs

@@ -0,0 +1,269 @@
+#[doc = "Register `INTENSET` reader"]
+pub struct R(crate::R<INTENSET_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<INTENSET_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<INTENSET_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<INTENSET_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `INTENSET` writer"]
+pub struct W(crate::W<INTENSET_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<INTENSET_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<INTENSET_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<INTENSET_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `RAMACCERR` reader - Write '1' to enable interrupt for event RAMACCERR"]
+pub type RAMACCERR_R = crate::BitReader<RAMACCERR_A>;
+#[doc = "Write '1' to enable interrupt for event RAMACCERR\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum RAMACCERR_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<RAMACCERR_A> for bool {
+    #[inline(always)]
+    fn from(variant: RAMACCERR_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl RAMACCERR_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> RAMACCERR_A {
+        match self.bits {
+            false => RAMACCERR_A::DISABLED,
+            true => RAMACCERR_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == RAMACCERR_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == RAMACCERR_A::ENABLED
+    }
+}
+#[doc = "Write '1' to enable interrupt for event RAMACCERR\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum RAMACCERR_AW {
+    #[doc = "1: Enable"]
+    SET = 1,
+}
+impl From<RAMACCERR_AW> for bool {
+    #[inline(always)]
+    fn from(variant: RAMACCERR_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `RAMACCERR` writer - Write '1' to enable interrupt for event RAMACCERR"]
+pub type RAMACCERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, RAMACCERR_AW, O>;
+impl<'a, const O: u8> RAMACCERR_W<'a, O> {
+    #[doc = "Enable"]
+    #[inline(always)]
+    pub fn set(self) -> &'a mut W {
+        self.variant(RAMACCERR_AW::SET)
+    }
+}
+#[doc = "Field `FLASHACCERR` reader - Write '1' to enable interrupt for event FLASHACCERR"]
+pub type FLASHACCERR_R = crate::BitReader<FLASHACCERR_A>;
+#[doc = "Write '1' to enable interrupt for event FLASHACCERR\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FLASHACCERR_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<FLASHACCERR_A> for bool {
+    #[inline(always)]
+    fn from(variant: FLASHACCERR_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl FLASHACCERR_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> FLASHACCERR_A {
+        match self.bits {
+            false => FLASHACCERR_A::DISABLED,
+            true => FLASHACCERR_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == FLASHACCERR_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == FLASHACCERR_A::ENABLED
+    }
+}
+#[doc = "Write '1' to enable interrupt for event FLASHACCERR\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FLASHACCERR_AW {
+    #[doc = "1: Enable"]
+    SET = 1,
+}
+impl From<FLASHACCERR_AW> for bool {
+    #[inline(always)]
+    fn from(variant: FLASHACCERR_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `FLASHACCERR` writer - Write '1' to enable interrupt for event FLASHACCERR"]
+pub type FLASHACCERR_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, INTENSET_SPEC, FLASHACCERR_AW, O>;
+impl<'a, const O: u8> FLASHACCERR_W<'a, O> {
+    #[doc = "Enable"]
+    #[inline(always)]
+    pub fn set(self) -> &'a mut W {
+        self.variant(FLASHACCERR_AW::SET)
+    }
+}
+#[doc = "Field `PERIPHACCERR` reader - Write '1' to enable interrupt for event PERIPHACCERR"]
+pub type PERIPHACCERR_R = crate::BitReader<PERIPHACCERR_A>;
+#[doc = "Write '1' to enable interrupt for event PERIPHACCERR\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum PERIPHACCERR_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<PERIPHACCERR_A> for bool {
+    #[inline(always)]
+    fn from(variant: PERIPHACCERR_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl PERIPHACCERR_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> PERIPHACCERR_A {
+        match self.bits {
+            false => PERIPHACCERR_A::DISABLED,
+            true => PERIPHACCERR_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == PERIPHACCERR_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == PERIPHACCERR_A::ENABLED
+    }
+}
+#[doc = "Write '1' to enable interrupt for event PERIPHACCERR\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum PERIPHACCERR_AW {
+    #[doc = "1: Enable"]
+    SET = 1,
+}
+impl From<PERIPHACCERR_AW> for bool {
+    #[inline(always)]
+    fn from(variant: PERIPHACCERR_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `PERIPHACCERR` writer - Write '1' to enable interrupt for event PERIPHACCERR"]
+pub type PERIPHACCERR_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, INTENSET_SPEC, PERIPHACCERR_AW, O>;
+impl<'a, const O: u8> PERIPHACCERR_W<'a, O> {
+    #[doc = "Enable"]
+    #[inline(always)]
+    pub fn set(self) -> &'a mut W {
+        self.variant(PERIPHACCERR_AW::SET)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Write '1' to enable interrupt for event RAMACCERR"]
+    #[inline(always)]
+    pub fn ramaccerr(&self) -> RAMACCERR_R {
+        RAMACCERR_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Write '1' to enable interrupt for event FLASHACCERR"]
+    #[inline(always)]
+    pub fn flashaccerr(&self) -> FLASHACCERR_R {
+        FLASHACCERR_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Write '1' to enable interrupt for event PERIPHACCERR"]
+    #[inline(always)]
+    pub fn periphaccerr(&self) -> PERIPHACCERR_R {
+        PERIPHACCERR_R::new(((self.bits >> 2) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Write '1' to enable interrupt for event RAMACCERR"]
+    #[inline(always)]
+    pub fn ramaccerr(&mut self) -> RAMACCERR_W<0> {
+        RAMACCERR_W::new(self)
+    }
+    #[doc = "Bit 1 - Write '1' to enable interrupt for event FLASHACCERR"]
+    #[inline(always)]
+    pub fn flashaccerr(&mut self) -> FLASHACCERR_W<1> {
+        FLASHACCERR_W::new(self)
+    }
+    #[doc = "Bit 2 - Write '1' to enable interrupt for event PERIPHACCERR"]
+    #[inline(always)]
+    pub fn periphaccerr(&mut self) -> PERIPHACCERR_W<2> {
+        PERIPHACCERR_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Enable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"]
+pub struct INTENSET_SPEC;
+impl crate::RegisterSpec for INTENSET_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [intenset::R](R) reader structure"]
+impl crate::Readable for INTENSET_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"]
+impl crate::Writable for INTENSET_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets INTENSET to value 0"]
+impl crate::Resettable for INTENSET_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9120-pac/src/spu_s/periphid.rs

@@ -0,0 +1,10 @@
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct PERIPHID {
+    #[doc = "0x00 - Description cluster: List capabilities and access permissions for the peripheral with ID n"]
+    pub perm: PERM,
+}
+#[doc = "PERM (rw) register accessor: an alias for `Reg<PERM_SPEC>`"]
+pub type PERM = crate::Reg<perm::PERM_SPEC>;
+#[doc = "Description cluster: List capabilities and access permissions for the peripheral with ID n"]
+pub mod perm;

vendor/nrf9120-pac/src/spu_s/periphid/perm.rs

@@ -0,0 +1,397 @@
+#[doc = "Register `PERM` reader"]
+pub struct R(crate::R<PERM_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<PERM_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<PERM_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<PERM_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `PERM` writer"]
+pub struct W(crate::W<PERM_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<PERM_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<PERM_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<PERM_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `SECUREMAPPING` reader - Define configuration capabilities for TrustZone Cortex-M secure attribute"]
+pub type SECUREMAPPING_R = crate::FieldReader<u8, SECUREMAPPING_A>;
+#[doc = "Define configuration capabilities for TrustZone Cortex-M secure attribute\n\nValue on reset: 2"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum SECUREMAPPING_A {
+    #[doc = "0: This peripheral is always accessible as a non-secure peripheral"]
+    NON_SECURE = 0,
+    #[doc = "1: This peripheral is always accessible as a secure peripheral"]
+    SECURE = 1,
+    #[doc = "2: Non-secure or secure attribute for this peripheral is defined by the PERIPHID\\[n\\].PERM register"]
+    USER_SELECTABLE = 2,
+    #[doc = "3: This peripheral implements the split security mechanism. Non-secure or secure attribute for this peripheral is defined by the PERIPHID\\[n\\].PERM register."]
+    SPLIT = 3,
+}
+impl From<SECUREMAPPING_A> for u8 {
+    #[inline(always)]
+    fn from(variant: SECUREMAPPING_A) -> Self {
+        variant as _
+    }
+}
+impl SECUREMAPPING_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> SECUREMAPPING_A {
+        match self.bits {
+            0 => SECUREMAPPING_A::NON_SECURE,
+            1 => SECUREMAPPING_A::SECURE,
+            2 => SECUREMAPPING_A::USER_SELECTABLE,
+            3 => SECUREMAPPING_A::SPLIT,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `NON_SECURE`"]
+    #[inline(always)]
+    pub fn is_non_secure(&self) -> bool {
+        *self == SECUREMAPPING_A::NON_SECURE
+    }
+    #[doc = "Checks if the value of the field is `SECURE`"]
+    #[inline(always)]
+    pub fn is_secure(&self) -> bool {
+        *self == SECUREMAPPING_A::SECURE
+    }
+    #[doc = "Checks if the value of the field is `USER_SELECTABLE`"]
+    #[inline(always)]
+    pub fn is_user_selectable(&self) -> bool {
+        *self == SECUREMAPPING_A::USER_SELECTABLE
+    }
+    #[doc = "Checks if the value of the field is `SPLIT`"]
+    #[inline(always)]
+    pub fn is_split(&self) -> bool {
+        *self == SECUREMAPPING_A::SPLIT
+    }
+}
+#[doc = "Field `DMA` reader - Indicate if the peripheral has DMA capabilities and if DMA transfer can be assigned to a different security attribute than the peripheral itself"]
+pub type DMA_R = crate::FieldReader<u8, DMA_A>;
+#[doc = "Indicate if the peripheral has DMA capabilities and if DMA transfer can be assigned to a different security attribute than the peripheral itself\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum DMA_A {
+    #[doc = "0: Peripheral has no DMA capability"]
+    NO_DMA = 0,
+    #[doc = "1: Peripheral has DMA and DMA transfers always have the same security attribute as assigned to the peripheral"]
+    NO_SEPARATE_ATTRIBUTE = 1,
+    #[doc = "2: Peripheral has DMA and DMA transfers can have a different security attribute than the one assigned to the peripheral"]
+    SEPARATE_ATTRIBUTE = 2,
+}
+impl From<DMA_A> for u8 {
+    #[inline(always)]
+    fn from(variant: DMA_A) -> Self {
+        variant as _
+    }
+}
+impl DMA_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<DMA_A> {
+        match self.bits {
+            0 => Some(DMA_A::NO_DMA),
+            1 => Some(DMA_A::NO_SEPARATE_ATTRIBUTE),
+            2 => Some(DMA_A::SEPARATE_ATTRIBUTE),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `NO_DMA`"]
+    #[inline(always)]
+    pub fn is_no_dma(&self) -> bool {
+        *self == DMA_A::NO_DMA
+    }
+    #[doc = "Checks if the value of the field is `NO_SEPARATE_ATTRIBUTE`"]
+    #[inline(always)]
+    pub fn is_no_separate_attribute(&self) -> bool {
+        *self == DMA_A::NO_SEPARATE_ATTRIBUTE
+    }
+    #[doc = "Checks if the value of the field is `SEPARATE_ATTRIBUTE`"]
+    #[inline(always)]
+    pub fn is_separate_attribute(&self) -> bool {
+        *self == DMA_A::SEPARATE_ATTRIBUTE
+    }
+}
+#[doc = "Field `SECATTR` reader - Peripheral security mapping"]
+pub type SECATTR_R = crate::BitReader<SECATTR_A>;
+#[doc = "Peripheral security mapping\n\nValue on reset: 1"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SECATTR_A {
+    #[doc = "1: Peripheral is mapped in secure peripheral address space"]
+    SECURE = 1,
+    #[doc = "0: If SECUREMAPPING == UserSelectable: Peripheral is mapped in non-secure peripheral address space. If SECUREMAPPING == Split: Peripheral is mapped in non-secure and secure peripheral address space."]
+    NON_SECURE = 0,
+}
+impl From<SECATTR_A> for bool {
+    #[inline(always)]
+    fn from(variant: SECATTR_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl SECATTR_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> SECATTR_A {
+        match self.bits {
+            true => SECATTR_A::SECURE,
+            false => SECATTR_A::NON_SECURE,
+        }
+    }
+    #[doc = "Checks if the value of the field is `SECURE`"]
+    #[inline(always)]
+    pub fn is_secure(&self) -> bool {
+        *self == SECATTR_A::SECURE
+    }
+    #[doc = "Checks if the value of the field is `NON_SECURE`"]
+    #[inline(always)]
+    pub fn is_non_secure(&self) -> bool {
+        *self == SECATTR_A::NON_SECURE
+    }
+}
+#[doc = "Field `SECATTR` writer - Peripheral security mapping"]
+pub type SECATTR_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, SECATTR_A, O>;
+impl<'a, const O: u8> SECATTR_W<'a, O> {
+    #[doc = "Peripheral is mapped in secure peripheral address space"]
+    #[inline(always)]
+    pub fn secure(self) -> &'a mut W {
+        self.variant(SECATTR_A::SECURE)
+    }
+    #[doc = "If SECUREMAPPING == UserSelectable: Peripheral is mapped in non-secure peripheral address space. If SECUREMAPPING == Split: Peripheral is mapped in non-secure and secure peripheral address space."]
+    #[inline(always)]
+    pub fn non_secure(self) -> &'a mut W {
+        self.variant(SECATTR_A::NON_SECURE)
+    }
+}
+#[doc = "Field `DMASEC` reader - Security attribution for the DMA transfer"]
+pub type DMASEC_R = crate::BitReader<DMASEC_A>;
+#[doc = "Security attribution for the DMA transfer\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DMASEC_A {
+    #[doc = "1: DMA transfers initiated by this peripheral have the secure attribute set"]
+    SECURE = 1,
+    #[doc = "0: DMA transfers initiated by this peripheral have the non-secure attribute set"]
+    NON_SECURE = 0,
+}
+impl From<DMASEC_A> for bool {
+    #[inline(always)]
+    fn from(variant: DMASEC_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl DMASEC_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> DMASEC_A {
+        match self.bits {
+            true => DMASEC_A::SECURE,
+            false => DMASEC_A::NON_SECURE,
+        }
+    }
+    #[doc = "Checks if the value of the field is `SECURE`"]
+    #[inline(always)]
+    pub fn is_secure(&self) -> bool {
+        *self == DMASEC_A::SECURE
+    }
+    #[doc = "Checks if the value of the field is `NON_SECURE`"]
+    #[inline(always)]
+    pub fn is_non_secure(&self) -> bool {
+        *self == DMASEC_A::NON_SECURE
+    }
+}
+#[doc = "Field `DMASEC` writer - Security attribution for the DMA transfer"]
+pub type DMASEC_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, DMASEC_A, O>;
+impl<'a, const O: u8> DMASEC_W<'a, O> {
+    #[doc = "DMA transfers initiated by this peripheral have the secure attribute set"]
+    #[inline(always)]
+    pub fn secure(self) -> &'a mut W {
+        self.variant(DMASEC_A::SECURE)
+    }
+    #[doc = "DMA transfers initiated by this peripheral have the non-secure attribute set"]
+    #[inline(always)]
+    pub fn non_secure(self) -> &'a mut W {
+        self.variant(DMASEC_A::NON_SECURE)
+    }
+}
+#[doc = "Field `LOCK` reader - "]
+pub type LOCK_R = crate::BitReader<LOCK_A>;
+#[doc = "\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum LOCK_A {
+    #[doc = "0: This register can be updated"]
+    UNLOCKED = 0,
+    #[doc = "1: The content of this register can't be changed until the next reset"]
+    LOCKED = 1,
+}
+impl From<LOCK_A> for bool {
+    #[inline(always)]
+    fn from(variant: LOCK_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl LOCK_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> LOCK_A {
+        match self.bits {
+            false => LOCK_A::UNLOCKED,
+            true => LOCK_A::LOCKED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UNLOCKED`"]
+    #[inline(always)]
+    pub fn is_unlocked(&self) -> bool {
+        *self == LOCK_A::UNLOCKED
+    }
+    #[doc = "Checks if the value of the field is `LOCKED`"]
+    #[inline(always)]
+    pub fn is_locked(&self) -> bool {
+        *self == LOCK_A::LOCKED
+    }
+}
+#[doc = "Field `LOCK` writer - "]
+pub type LOCK_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, LOCK_A, O>;
+impl<'a, const O: u8> LOCK_W<'a, O> {
+    #[doc = "This register can be updated"]
+    #[inline(always)]
+    pub fn unlocked(self) -> &'a mut W {
+        self.variant(LOCK_A::UNLOCKED)
+    }
+    #[doc = "The content of this register can't be changed until the next reset"]
+    #[inline(always)]
+    pub fn locked(self) -> &'a mut W {
+        self.variant(LOCK_A::LOCKED)
+    }
+}
+#[doc = "Field `PRESENT` reader - Indicate if a peripheral is present with ID n"]
+pub type PRESENT_R = crate::BitReader<PRESENT_A>;
+#[doc = "Indicate if a peripheral is present with ID n\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum PRESENT_A {
+    #[doc = "0: Peripheral is not present"]
+    NOT_PRESENT = 0,
+    #[doc = "1: Peripheral is present"]
+    IS_PRESENT = 1,
+}
+impl From<PRESENT_A> for bool {
+    #[inline(always)]
+    fn from(variant: PRESENT_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl PRESENT_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> PRESENT_A {
+        match self.bits {
+            false => PRESENT_A::NOT_PRESENT,
+            true => PRESENT_A::IS_PRESENT,
+        }
+    }
+    #[doc = "Checks if the value of the field is `NOT_PRESENT`"]
+    #[inline(always)]
+    pub fn is_not_present(&self) -> bool {
+        *self == PRESENT_A::NOT_PRESENT
+    }
+    #[doc = "Checks if the value of the field is `IS_PRESENT`"]
+    #[inline(always)]
+    pub fn is_is_present(&self) -> bool {
+        *self == PRESENT_A::IS_PRESENT
+    }
+}
+impl R {
+    #[doc = "Bits 0:1 - Define configuration capabilities for TrustZone Cortex-M secure attribute"]
+    #[inline(always)]
+    pub fn securemapping(&self) -> SECUREMAPPING_R {
+        SECUREMAPPING_R::new((self.bits & 3) as u8)
+    }
+    #[doc = "Bits 2:3 - Indicate if the peripheral has DMA capabilities and if DMA transfer can be assigned to a different security attribute than the peripheral itself"]
+    #[inline(always)]
+    pub fn dma(&self) -> DMA_R {
+        DMA_R::new(((self.bits >> 2) & 3) as u8)
+    }
+    #[doc = "Bit 4 - Peripheral security mapping"]
+    #[inline(always)]
+    pub fn secattr(&self) -> SECATTR_R {
+        SECATTR_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - Security attribution for the DMA transfer"]
+    #[inline(always)]
+    pub fn dmasec(&self) -> DMASEC_R {
+        DMASEC_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 8"]
+    #[inline(always)]
+    pub fn lock(&self) -> LOCK_R {
+        LOCK_R::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 31 - Indicate if a peripheral is present with ID n"]
+    #[inline(always)]
+    pub fn present(&self) -> PRESENT_R {
+        PRESENT_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 4 - Peripheral security mapping"]
+    #[inline(always)]
+    pub fn secattr(&mut self) -> SECATTR_W<4> {
+        SECATTR_W::new(self)
+    }
+    #[doc = "Bit 5 - Security attribution for the DMA transfer"]
+    #[inline(always)]
+    pub fn dmasec(&mut self) -> DMASEC_W<5> {
+        DMASEC_W::new(self)
+    }
+    #[doc = "Bit 8"]
+    #[inline(always)]
+    pub fn lock(&mut self) -> LOCK_W<8> {
+        LOCK_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Description cluster: List capabilities and access permissions for the peripheral with ID n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perm](index.html) module"]
+pub struct PERM_SPEC;
+impl crate::RegisterSpec for PERM_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [perm::R](R) reader structure"]
+impl crate::Readable for PERM_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [perm::W](W) writer structure"]
+impl crate::Writable for PERM_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets PERM to value 0x12"]
+impl crate::Resettable for PERM_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0x12
+    }
+}

vendor/nrf9120-pac/src/spu_s/publish_flashaccerr.rs

@@ -0,0 +1,141 @@
+#[doc = "Register `PUBLISH_FLASHACCERR` reader"]
+pub struct R(crate::R<PUBLISH_FLASHACCERR_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<PUBLISH_FLASHACCERR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<PUBLISH_FLASHACCERR_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<PUBLISH_FLASHACCERR_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `PUBLISH_FLASHACCERR` writer"]
+pub struct W(crate::W<PUBLISH_FLASHACCERR_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<PUBLISH_FLASHACCERR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<PUBLISH_FLASHACCERR_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<PUBLISH_FLASHACCERR_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `CHIDX` reader - DPPI channel that event FLASHACCERR will publish to"]
+pub type CHIDX_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `CHIDX` writer - DPPI channel that event FLASHACCERR will publish to"]
+pub type CHIDX_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u32, PUBLISH_FLASHACCERR_SPEC, u8, u8, 8, O>;
+#[doc = "Field `EN` reader - "]
+pub type EN_R = crate::BitReader<EN_A>;
+#[doc = "\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum EN_A {
+    #[doc = "0: Disable publishing"]
+    DISABLED = 0,
+    #[doc = "1: Enable publishing"]
+    ENABLED = 1,
+}
+impl From<EN_A> for bool {
+    #[inline(always)]
+    fn from(variant: EN_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl EN_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> EN_A {
+        match self.bits {
+            false => EN_A::DISABLED,
+            true => EN_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == EN_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == EN_A::ENABLED
+    }
+}
+#[doc = "Field `EN` writer - "]
+pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_FLASHACCERR_SPEC, EN_A, O>;
+impl<'a, const O: u8> EN_W<'a, O> {
+    #[doc = "Disable publishing"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(EN_A::DISABLED)
+    }
+    #[doc = "Enable publishing"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(EN_A::ENABLED)
+    }
+}
+impl R {
+    #[doc = "Bits 0:7 - DPPI channel that event FLASHACCERR will publish to"]
+    #[inline(always)]
+    pub fn chidx(&self) -> CHIDX_R {
+        CHIDX_R::new((self.bits & 0xff) as u8)
+    }
+    #[doc = "Bit 31"]
+    #[inline(always)]
+    pub fn en(&self) -> EN_R {
+        EN_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - DPPI channel that event FLASHACCERR will publish to"]
+    #[inline(always)]
+    pub fn chidx(&mut self) -> CHIDX_W<0> {
+        CHIDX_W::new(self)
+    }
+    #[doc = "Bit 31"]
+    #[inline(always)]
+    pub fn en(&mut self) -> EN_W<31> {
+        EN_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Publish configuration for event FLASHACCERR\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_flashaccerr](index.html) module"]
+pub struct PUBLISH_FLASHACCERR_SPEC;
+impl crate::RegisterSpec for PUBLISH_FLASHACCERR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [publish_flashaccerr::R](R) reader structure"]
+impl crate::Readable for PUBLISH_FLASHACCERR_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [publish_flashaccerr::W](W) writer structure"]
+impl crate::Writable for PUBLISH_FLASHACCERR_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets PUBLISH_FLASHACCERR to value 0"]
+impl crate::Resettable for PUBLISH_FLASHACCERR_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9120-pac/src/spu_s/publish_periphaccerr.rs

@@ -0,0 +1,141 @@
+#[doc = "Register `PUBLISH_PERIPHACCERR` reader"]
+pub struct R(crate::R<PUBLISH_PERIPHACCERR_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<PUBLISH_PERIPHACCERR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<PUBLISH_PERIPHACCERR_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<PUBLISH_PERIPHACCERR_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `PUBLISH_PERIPHACCERR` writer"]
+pub struct W(crate::W<PUBLISH_PERIPHACCERR_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<PUBLISH_PERIPHACCERR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<PUBLISH_PERIPHACCERR_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<PUBLISH_PERIPHACCERR_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `CHIDX` reader - DPPI channel that event PERIPHACCERR will publish to"]
+pub type CHIDX_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `CHIDX` writer - DPPI channel that event PERIPHACCERR will publish to"]
+pub type CHIDX_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u32, PUBLISH_PERIPHACCERR_SPEC, u8, u8, 8, O>;
+#[doc = "Field `EN` reader - "]
+pub type EN_R = crate::BitReader<EN_A>;
+#[doc = "\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum EN_A {
+    #[doc = "0: Disable publishing"]
+    DISABLED = 0,
+    #[doc = "1: Enable publishing"]
+    ENABLED = 1,
+}
+impl From<EN_A> for bool {
+    #[inline(always)]
+    fn from(variant: EN_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl EN_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> EN_A {
+        match self.bits {
+            false => EN_A::DISABLED,
+            true => EN_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == EN_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == EN_A::ENABLED
+    }
+}
+#[doc = "Field `EN` writer - "]
+pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_PERIPHACCERR_SPEC, EN_A, O>;
+impl<'a, const O: u8> EN_W<'a, O> {
+    #[doc = "Disable publishing"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(EN_A::DISABLED)
+    }
+    #[doc = "Enable publishing"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(EN_A::ENABLED)
+    }
+}
+impl R {
+    #[doc = "Bits 0:7 - DPPI channel that event PERIPHACCERR will publish to"]
+    #[inline(always)]
+    pub fn chidx(&self) -> CHIDX_R {
+        CHIDX_R::new((self.bits & 0xff) as u8)
+    }
+    #[doc = "Bit 31"]
+    #[inline(always)]
+    pub fn en(&self) -> EN_R {
+        EN_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - DPPI channel that event PERIPHACCERR will publish to"]
+    #[inline(always)]
+    pub fn chidx(&mut self) -> CHIDX_W<0> {
+        CHIDX_W::new(self)
+    }
+    #[doc = "Bit 31"]
+    #[inline(always)]
+    pub fn en(&mut self) -> EN_W<31> {
+        EN_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Publish configuration for event PERIPHACCERR\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_periphaccerr](index.html) module"]
+pub struct PUBLISH_PERIPHACCERR_SPEC;
+impl crate::RegisterSpec for PUBLISH_PERIPHACCERR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [publish_periphaccerr::R](R) reader structure"]
+impl crate::Readable for PUBLISH_PERIPHACCERR_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [publish_periphaccerr::W](W) writer structure"]
+impl crate::Writable for PUBLISH_PERIPHACCERR_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets PUBLISH_PERIPHACCERR to value 0"]
+impl crate::Resettable for PUBLISH_PERIPHACCERR_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9120-pac/src/spu_s/publish_ramaccerr.rs

@@ -0,0 +1,141 @@
+#[doc = "Register `PUBLISH_RAMACCERR` reader"]
+pub struct R(crate::R<PUBLISH_RAMACCERR_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<PUBLISH_RAMACCERR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<PUBLISH_RAMACCERR_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<PUBLISH_RAMACCERR_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `PUBLISH_RAMACCERR` writer"]
+pub struct W(crate::W<PUBLISH_RAMACCERR_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<PUBLISH_RAMACCERR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<PUBLISH_RAMACCERR_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<PUBLISH_RAMACCERR_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `CHIDX` reader - DPPI channel that event RAMACCERR will publish to"]
+pub type CHIDX_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `CHIDX` writer - DPPI channel that event RAMACCERR will publish to"]
+pub type CHIDX_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u32, PUBLISH_RAMACCERR_SPEC, u8, u8, 8, O>;
+#[doc = "Field `EN` reader - "]
+pub type EN_R = crate::BitReader<EN_A>;
+#[doc = "\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum EN_A {
+    #[doc = "0: Disable publishing"]
+    DISABLED = 0,
+    #[doc = "1: Enable publishing"]
+    ENABLED = 1,
+}
+impl From<EN_A> for bool {
+    #[inline(always)]
+    fn from(variant: EN_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl EN_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> EN_A {
+        match self.bits {
+            false => EN_A::DISABLED,
+            true => EN_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == EN_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == EN_A::ENABLED
+    }
+}
+#[doc = "Field `EN` writer - "]
+pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_RAMACCERR_SPEC, EN_A, O>;
+impl<'a, const O: u8> EN_W<'a, O> {
+    #[doc = "Disable publishing"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(EN_A::DISABLED)
+    }
+    #[doc = "Enable publishing"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(EN_A::ENABLED)
+    }
+}
+impl R {
+    #[doc = "Bits 0:7 - DPPI channel that event RAMACCERR will publish to"]
+    #[inline(always)]
+    pub fn chidx(&self) -> CHIDX_R {
+        CHIDX_R::new((self.bits & 0xff) as u8)
+    }
+    #[doc = "Bit 31"]
+    #[inline(always)]
+    pub fn en(&self) -> EN_R {
+        EN_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - DPPI channel that event RAMACCERR will publish to"]
+    #[inline(always)]
+    pub fn chidx(&mut self) -> CHIDX_W<0> {
+        CHIDX_W::new(self)
+    }
+    #[doc = "Bit 31"]
+    #[inline(always)]
+    pub fn en(&mut self) -> EN_W<31> {
+        EN_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Publish configuration for event RAMACCERR\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_ramaccerr](index.html) module"]
+pub struct PUBLISH_RAMACCERR_SPEC;
+impl crate::RegisterSpec for PUBLISH_RAMACCERR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [publish_ramaccerr::R](R) reader structure"]
+impl crate::Readable for PUBLISH_RAMACCERR_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [publish_ramaccerr::W](W) writer structure"]
+impl crate::Writable for PUBLISH_RAMACCERR_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets PUBLISH_RAMACCERR to value 0"]
+impl crate::Resettable for PUBLISH_RAMACCERR_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9120-pac/src/spu_s/ramnsc.rs

@@ -0,0 +1,16 @@
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct RAMNSC {
+    #[doc = "0x00 - Description cluster: Define which RAM region can contain the non-secure callable (NSC) region n"]
+    pub region: REGION,
+    #[doc = "0x04 - Description cluster: Define the size of the non-secure callable (NSC) region n"]
+    pub size: SIZE,
+}
+#[doc = "REGION (rw) register accessor: an alias for `Reg<REGION_SPEC>`"]
+pub type REGION = crate::Reg<region::REGION_SPEC>;
+#[doc = "Description cluster: Define which RAM region can contain the non-secure callable (NSC) region n"]
+pub mod region;
+#[doc = "SIZE (rw) register accessor: an alias for `Reg<SIZE_SPEC>`"]
+pub type SIZE = crate::Reg<size::SIZE_SPEC>;
+#[doc = "Description cluster: Define the size of the non-secure callable (NSC) region n"]
+pub mod size;

vendor/nrf9120-pac/src/spu_s/ramnsc/region.rs

@@ -0,0 +1,140 @@
+#[doc = "Register `REGION` reader"]
+pub struct R(crate::R<REGION_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<REGION_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<REGION_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<REGION_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `REGION` writer"]
+pub struct W(crate::W<REGION_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<REGION_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<REGION_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<REGION_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `REGION` reader - Region number"]
+pub type REGION_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `REGION` writer - Region number"]
+pub type REGION_W<'a, const O: u8> = crate::FieldWriter<'a, u32, REGION_SPEC, u8, u8, 5, O>;
+#[doc = "Field `LOCK` reader - "]
+pub type LOCK_R = crate::BitReader<LOCK_A>;
+#[doc = "\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum LOCK_A {
+    #[doc = "0: This register can be updated"]
+    UNLOCKED = 0,
+    #[doc = "1: The content of this register can't be changed until the next reset"]
+    LOCKED = 1,
+}
+impl From<LOCK_A> for bool {
+    #[inline(always)]
+    fn from(variant: LOCK_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl LOCK_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> LOCK_A {
+        match self.bits {
+            false => LOCK_A::UNLOCKED,
+            true => LOCK_A::LOCKED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UNLOCKED`"]
+    #[inline(always)]
+    pub fn is_unlocked(&self) -> bool {
+        *self == LOCK_A::UNLOCKED
+    }
+    #[doc = "Checks if the value of the field is `LOCKED`"]
+    #[inline(always)]
+    pub fn is_locked(&self) -> bool {
+        *self == LOCK_A::LOCKED
+    }
+}
+#[doc = "Field `LOCK` writer - "]
+pub type LOCK_W<'a, const O: u8> = crate::BitWriter<'a, u32, REGION_SPEC, LOCK_A, O>;
+impl<'a, const O: u8> LOCK_W<'a, O> {
+    #[doc = "This register can be updated"]
+    #[inline(always)]
+    pub fn unlocked(self) -> &'a mut W {
+        self.variant(LOCK_A::UNLOCKED)
+    }
+    #[doc = "The content of this register can't be changed until the next reset"]
+    #[inline(always)]
+    pub fn locked(self) -> &'a mut W {
+        self.variant(LOCK_A::LOCKED)
+    }
+}
+impl R {
+    #[doc = "Bits 0:4 - Region number"]
+    #[inline(always)]
+    pub fn region(&self) -> REGION_R {
+        REGION_R::new((self.bits & 0x1f) as u8)
+    }
+    #[doc = "Bit 8"]
+    #[inline(always)]
+    pub fn lock(&self) -> LOCK_R {
+        LOCK_R::new(((self.bits >> 8) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:4 - Region number"]
+    #[inline(always)]
+    pub fn region(&mut self) -> REGION_W<0> {
+        REGION_W::new(self)
+    }
+    #[doc = "Bit 8"]
+    #[inline(always)]
+    pub fn lock(&mut self) -> LOCK_W<8> {
+        LOCK_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Description cluster: Define which RAM region can contain the non-secure callable (NSC) region n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [region](index.html) module"]
+pub struct REGION_SPEC;
+impl crate::RegisterSpec for REGION_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [region::R](R) reader structure"]
+impl crate::Readable for REGION_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [region::W](W) writer structure"]
+impl crate::Writable for REGION_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets REGION to value 0"]
+impl crate::Resettable for REGION_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9120-pac/src/spu_s/ramnsc/size.rs

@@ -0,0 +1,279 @@
+#[doc = "Register `SIZE` reader"]
+pub struct R(crate::R<SIZE_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<SIZE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<SIZE_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<SIZE_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `SIZE` writer"]
+pub struct W(crate::W<SIZE_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<SIZE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<SIZE_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<SIZE_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `SIZE` reader - Size of the non-secure callable (NSC) region n"]
+pub type SIZE_R = crate::FieldReader<u8, SIZE_A>;
+#[doc = "Size of the non-secure callable (NSC) region n\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum SIZE_A {
+    #[doc = "0: The region n is not defined as a non-secure callable region. Normal security attributes (secure or non-secure) are enforced."]
+    DISABLED = 0,
+    #[doc = "1: The region n is defined as non-secure callable with a 32-byte size"]
+    _32 = 1,
+    #[doc = "2: The region n is defined as non-secure callable with a 64-byte size"]
+    _64 = 2,
+    #[doc = "3: The region n is defined as non-secure callable with a 128-byte size"]
+    _128 = 3,
+    #[doc = "4: The region n is defined as non-secure callable with a 256-byte size"]
+    _256 = 4,
+    #[doc = "5: The region n is defined as non-secure callable with a 512-byte size"]
+    _512 = 5,
+    #[doc = "6: The region n is defined as non-secure callable with a 1024-byte size"]
+    _1024 = 6,
+    #[doc = "7: The region n is defined as non-secure callable with a 2048-byte size"]
+    _2048 = 7,
+    #[doc = "8: The region n is defined as non-secure callable with a 4096-byte size"]
+    _4096 = 8,
+}
+impl From<SIZE_A> for u8 {
+    #[inline(always)]
+    fn from(variant: SIZE_A) -> Self {
+        variant as _
+    }
+}
+impl SIZE_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<SIZE_A> {
+        match self.bits {
+            0 => Some(SIZE_A::DISABLED),
+            1 => Some(SIZE_A::_32),
+            2 => Some(SIZE_A::_64),
+            3 => Some(SIZE_A::_128),
+            4 => Some(SIZE_A::_256),
+            5 => Some(SIZE_A::_512),
+            6 => Some(SIZE_A::_1024),
+            7 => Some(SIZE_A::_2048),
+            8 => Some(SIZE_A::_4096),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == SIZE_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `_32`"]
+    #[inline(always)]
+    pub fn is_32(&self) -> bool {
+        *self == SIZE_A::_32
+    }
+    #[doc = "Checks if the value of the field is `_64`"]
+    #[inline(always)]
+    pub fn is_64(&self) -> bool {
+        *self == SIZE_A::_64
+    }
+    #[doc = "Checks if the value of the field is `_128`"]
+    #[inline(always)]
+    pub fn is_128(&self) -> bool {
+        *self == SIZE_A::_128
+    }
+    #[doc = "Checks if the value of the field is `_256`"]
+    #[inline(always)]
+    pub fn is_256(&self) -> bool {
+        *self == SIZE_A::_256
+    }
+    #[doc = "Checks if the value of the field is `_512`"]
+    #[inline(always)]
+    pub fn is_512(&self) -> bool {
+        *self == SIZE_A::_512
+    }
+    #[doc = "Checks if the value of the field is `_1024`"]
+    #[inline(always)]
+    pub fn is_1024(&self) -> bool {
+        *self == SIZE_A::_1024
+    }
+    #[doc = "Checks if the value of the field is `_2048`"]
+    #[inline(always)]
+    pub fn is_2048(&self) -> bool {
+        *self == SIZE_A::_2048
+    }
+    #[doc = "Checks if the value of the field is `_4096`"]
+    #[inline(always)]
+    pub fn is_4096(&self) -> bool {
+        *self == SIZE_A::_4096
+    }
+}
+#[doc = "Field `SIZE` writer - Size of the non-secure callable (NSC) region n"]
+pub type SIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SIZE_SPEC, u8, SIZE_A, 4, O>;
+impl<'a, const O: u8> SIZE_W<'a, O> {
+    #[doc = "The region n is not defined as a non-secure callable region. Normal security attributes (secure or non-secure) are enforced."]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(SIZE_A::DISABLED)
+    }
+    #[doc = "The region n is defined as non-secure callable with a 32-byte size"]
+    #[inline(always)]
+    pub fn _32(self) -> &'a mut W {
+        self.variant(SIZE_A::_32)
+    }
+    #[doc = "The region n is defined as non-secure callable with a 64-byte size"]
+    #[inline(always)]
+    pub fn _64(self) -> &'a mut W {
+        self.variant(SIZE_A::_64)
+    }
+    #[doc = "The region n is defined as non-secure callable with a 128-byte size"]
+    #[inline(always)]
+    pub fn _128(self) -> &'a mut W {
+        self.variant(SIZE_A::_128)
+    }
+    #[doc = "The region n is defined as non-secure callable with a 256-byte size"]
+    #[inline(always)]
+    pub fn _256(self) -> &'a mut W {
+        self.variant(SIZE_A::_256)
+    }
+    #[doc = "The region n is defined as non-secure callable with a 512-byte size"]
+    #[inline(always)]
+    pub fn _512(self) -> &'a mut W {
+        self.variant(SIZE_A::_512)
+    }
+    #[doc = "The region n is defined as non-secure callable with a 1024-byte size"]
+    #[inline(always)]
+    pub fn _1024(self) -> &'a mut W {
+        self.variant(SIZE_A::_1024)
+    }
+    #[doc = "The region n is defined as non-secure callable with a 2048-byte size"]
+    #[inline(always)]
+    pub fn _2048(self) -> &'a mut W {
+        self.variant(SIZE_A::_2048)
+    }
+    #[doc = "The region n is defined as non-secure callable with a 4096-byte size"]
+    #[inline(always)]
+    pub fn _4096(self) -> &'a mut W {
+        self.variant(SIZE_A::_4096)
+    }
+}
+#[doc = "Field `LOCK` reader - "]
+pub type LOCK_R = crate::BitReader<LOCK_A>;
+#[doc = "\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum LOCK_A {
+    #[doc = "0: This register can be updated"]
+    UNLOCKED = 0,
+    #[doc = "1: The content of this register can't be changed until the next reset"]
+    LOCKED = 1,
+}
+impl From<LOCK_A> for bool {
+    #[inline(always)]
+    fn from(variant: LOCK_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl LOCK_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> LOCK_A {
+        match self.bits {
+            false => LOCK_A::UNLOCKED,
+            true => LOCK_A::LOCKED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UNLOCKED`"]
+    #[inline(always)]
+    pub fn is_unlocked(&self) -> bool {
+        *self == LOCK_A::UNLOCKED
+    }
+    #[doc = "Checks if the value of the field is `LOCKED`"]
+    #[inline(always)]
+    pub fn is_locked(&self) -> bool {
+        *self == LOCK_A::LOCKED
+    }
+}
+#[doc = "Field `LOCK` writer - "]
+pub type LOCK_W<'a, const O: u8> = crate::BitWriter<'a, u32, SIZE_SPEC, LOCK_A, O>;
+impl<'a, const O: u8> LOCK_W<'a, O> {
+    #[doc = "This register can be updated"]
+    #[inline(always)]
+    pub fn unlocked(self) -> &'a mut W {
+        self.variant(LOCK_A::UNLOCKED)
+    }
+    #[doc = "The content of this register can't be changed until the next reset"]
+    #[inline(always)]
+    pub fn locked(self) -> &'a mut W {
+        self.variant(LOCK_A::LOCKED)
+    }
+}
+impl R {
+    #[doc = "Bits 0:3 - Size of the non-secure callable (NSC) region n"]
+    #[inline(always)]
+    pub fn size(&self) -> SIZE_R {
+        SIZE_R::new((self.bits & 0x0f) as u8)
+    }
+    #[doc = "Bit 8"]
+    #[inline(always)]
+    pub fn lock(&self) -> LOCK_R {
+        LOCK_R::new(((self.bits >> 8) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:3 - Size of the non-secure callable (NSC) region n"]
+    #[inline(always)]
+    pub fn size(&mut self) -> SIZE_W<0> {
+        SIZE_W::new(self)
+    }
+    #[doc = "Bit 8"]
+    #[inline(always)]
+    pub fn lock(&mut self) -> LOCK_W<8> {
+        LOCK_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Description cluster: Define the size of the non-secure callable (NSC) region n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [size](index.html) module"]
+pub struct SIZE_SPEC;
+impl crate::RegisterSpec for SIZE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [size::R](R) reader structure"]
+impl crate::Readable for SIZE_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [size::W](W) writer structure"]
+impl crate::Writable for SIZE_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets SIZE to value 0"]
+impl crate::Resettable for SIZE_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9120-pac/src/spu_s/ramregion.rs

@@ -0,0 +1,10 @@
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct RAMREGION {
+    #[doc = "0x00 - Description cluster: Access permissions for RAM region n"]
+    pub perm: PERM,
+}
+#[doc = "PERM (rw) register accessor: an alias for `Reg<PERM_SPEC>`"]
+pub type PERM = crate::Reg<perm::PERM_SPEC>;
+#[doc = "Description cluster: Access permissions for RAM region n"]
+pub mod perm;

vendor/nrf9120-pac/src/spu_s/ramregion/perm.rs

@@ -0,0 +1,366 @@
+#[doc = "Register `PERM` reader"]
+pub struct R(crate::R<PERM_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<PERM_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<PERM_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<PERM_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `PERM` writer"]
+pub struct W(crate::W<PERM_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<PERM_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<PERM_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<PERM_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `EXECUTE` reader - Configure instruction fetch permissions from RAM region n"]
+pub type EXECUTE_R = crate::BitReader<EXECUTE_A>;
+#[doc = "Configure instruction fetch permissions from RAM region n\n\nValue on reset: 1"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum EXECUTE_A {
+    #[doc = "1: Allow instruction fetches from RAM region n"]
+    ENABLE = 1,
+    #[doc = "0: Block instruction fetches from RAM region n"]
+    DISABLE = 0,
+}
+impl From<EXECUTE_A> for bool {
+    #[inline(always)]
+    fn from(variant: EXECUTE_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl EXECUTE_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> EXECUTE_A {
+        match self.bits {
+            true => EXECUTE_A::ENABLE,
+            false => EXECUTE_A::DISABLE,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ENABLE`"]
+    #[inline(always)]
+    pub fn is_enable(&self) -> bool {
+        *self == EXECUTE_A::ENABLE
+    }
+    #[doc = "Checks if the value of the field is `DISABLE`"]
+    #[inline(always)]
+    pub fn is_disable(&self) -> bool {
+        *self == EXECUTE_A::DISABLE
+    }
+}
+#[doc = "Field `EXECUTE` writer - Configure instruction fetch permissions from RAM region n"]
+pub type EXECUTE_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, EXECUTE_A, O>;
+impl<'a, const O: u8> EXECUTE_W<'a, O> {
+    #[doc = "Allow instruction fetches from RAM region n"]
+    #[inline(always)]
+    pub fn enable(self) -> &'a mut W {
+        self.variant(EXECUTE_A::ENABLE)
+    }
+    #[doc = "Block instruction fetches from RAM region n"]
+    #[inline(always)]
+    pub fn disable(self) -> &'a mut W {
+        self.variant(EXECUTE_A::DISABLE)
+    }
+}
+#[doc = "Field `WRITE` reader - Configure write permission for RAM region n"]
+pub type WRITE_R = crate::BitReader<WRITE_A>;
+#[doc = "Configure write permission for RAM region n\n\nValue on reset: 1"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum WRITE_A {
+    #[doc = "1: Allow write operation to RAM region n"]
+    ENABLE = 1,
+    #[doc = "0: Block write operation to RAM region n"]
+    DISABLE = 0,
+}
+impl From<WRITE_A> for bool {
+    #[inline(always)]
+    fn from(variant: WRITE_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl WRITE_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> WRITE_A {
+        match self.bits {
+            true => WRITE_A::ENABLE,
+            false => WRITE_A::DISABLE,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ENABLE`"]
+    #[inline(always)]
+    pub fn is_enable(&self) -> bool {
+        *self == WRITE_A::ENABLE
+    }
+    #[doc = "Checks if the value of the field is `DISABLE`"]
+    #[inline(always)]
+    pub fn is_disable(&self) -> bool {
+        *self == WRITE_A::DISABLE
+    }
+}
+#[doc = "Field `WRITE` writer - Configure write permission for RAM region n"]
+pub type WRITE_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, WRITE_A, O>;
+impl<'a, const O: u8> WRITE_W<'a, O> {
+    #[doc = "Allow write operation to RAM region n"]
+    #[inline(always)]
+    pub fn enable(self) -> &'a mut W {
+        self.variant(WRITE_A::ENABLE)
+    }
+    #[doc = "Block write operation to RAM region n"]
+    #[inline(always)]
+    pub fn disable(self) -> &'a mut W {
+        self.variant(WRITE_A::DISABLE)
+    }
+}
+#[doc = "Field `READ` reader - Configure read permissions for RAM region n"]
+pub type READ_R = crate::BitReader<READ_A>;
+#[doc = "Configure read permissions for RAM region n\n\nValue on reset: 1"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum READ_A {
+    #[doc = "1: Allow read operation from RAM region n"]
+    ENABLE = 1,
+    #[doc = "0: Block read operation from RAM region n"]
+    DISABLE = 0,
+}
+impl From<READ_A> for bool {
+    #[inline(always)]
+    fn from(variant: READ_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl READ_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> READ_A {
+        match self.bits {
+            true => READ_A::ENABLE,
+            false => READ_A::DISABLE,
+        }
+    }
+    #[doc = "Checks if the value of the field is `ENABLE`"]
+    #[inline(always)]
+    pub fn is_enable(&self) -> bool {
+        *self == READ_A::ENABLE
+    }
+    #[doc = "Checks if the value of the field is `DISABLE`"]
+    #[inline(always)]
+    pub fn is_disable(&self) -> bool {
+        *self == READ_A::DISABLE
+    }
+}
+#[doc = "Field `READ` writer - Configure read permissions for RAM region n"]
+pub type READ_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, READ_A, O>;
+impl<'a, const O: u8> READ_W<'a, O> {
+    #[doc = "Allow read operation from RAM region n"]
+    #[inline(always)]
+    pub fn enable(self) -> &'a mut W {
+        self.variant(READ_A::ENABLE)
+    }
+    #[doc = "Block read operation from RAM region n"]
+    #[inline(always)]
+    pub fn disable(self) -> &'a mut W {
+        self.variant(READ_A::DISABLE)
+    }
+}
+#[doc = "Field `SECATTR` reader - Security attribute for RAM region n"]
+pub type SECATTR_R = crate::BitReader<SECATTR_A>;
+#[doc = "Security attribute for RAM region n\n\nValue on reset: 1"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SECATTR_A {
+    #[doc = "0: RAM region n security attribute is non-secure"]
+    NON_SECURE = 0,
+    #[doc = "1: RAM region n security attribute is secure"]
+    SECURE = 1,
+}
+impl From<SECATTR_A> for bool {
+    #[inline(always)]
+    fn from(variant: SECATTR_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl SECATTR_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> SECATTR_A {
+        match self.bits {
+            false => SECATTR_A::NON_SECURE,
+            true => SECATTR_A::SECURE,
+        }
+    }
+    #[doc = "Checks if the value of the field is `NON_SECURE`"]
+    #[inline(always)]
+    pub fn is_non_secure(&self) -> bool {
+        *self == SECATTR_A::NON_SECURE
+    }
+    #[doc = "Checks if the value of the field is `SECURE`"]
+    #[inline(always)]
+    pub fn is_secure(&self) -> bool {
+        *self == SECATTR_A::SECURE
+    }
+}
+#[doc = "Field `SECATTR` writer - Security attribute for RAM region n"]
+pub type SECATTR_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, SECATTR_A, O>;
+impl<'a, const O: u8> SECATTR_W<'a, O> {
+    #[doc = "RAM region n security attribute is non-secure"]
+    #[inline(always)]
+    pub fn non_secure(self) -> &'a mut W {
+        self.variant(SECATTR_A::NON_SECURE)
+    }
+    #[doc = "RAM region n security attribute is secure"]
+    #[inline(always)]
+    pub fn secure(self) -> &'a mut W {
+        self.variant(SECATTR_A::SECURE)
+    }
+}
+#[doc = "Field `LOCK` reader - "]
+pub type LOCK_R = crate::BitReader<LOCK_A>;
+#[doc = "\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum LOCK_A {
+    #[doc = "0: This register can be updated"]
+    UNLOCKED = 0,
+    #[doc = "1: The content of this register can't be changed until the next reset"]
+    LOCKED = 1,
+}
+impl From<LOCK_A> for bool {
+    #[inline(always)]
+    fn from(variant: LOCK_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl LOCK_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> LOCK_A {
+        match self.bits {
+            false => LOCK_A::UNLOCKED,
+            true => LOCK_A::LOCKED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UNLOCKED`"]
+    #[inline(always)]
+    pub fn is_unlocked(&self) -> bool {
+        *self == LOCK_A::UNLOCKED
+    }
+    #[doc = "Checks if the value of the field is `LOCKED`"]
+    #[inline(always)]
+    pub fn is_locked(&self) -> bool {
+        *self == LOCK_A::LOCKED
+    }
+}
+#[doc = "Field `LOCK` writer - "]
+pub type LOCK_W<'a, const O: u8> = crate::BitWriter<'a, u32, PERM_SPEC, LOCK_A, O>;
+impl<'a, const O: u8> LOCK_W<'a, O> {
+    #[doc = "This register can be updated"]
+    #[inline(always)]
+    pub fn unlocked(self) -> &'a mut W {
+        self.variant(LOCK_A::UNLOCKED)
+    }
+    #[doc = "The content of this register can't be changed until the next reset"]
+    #[inline(always)]
+    pub fn locked(self) -> &'a mut W {
+        self.variant(LOCK_A::LOCKED)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Configure instruction fetch permissions from RAM region n"]
+    #[inline(always)]
+    pub fn execute(&self) -> EXECUTE_R {
+        EXECUTE_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Configure write permission for RAM region n"]
+    #[inline(always)]
+    pub fn write(&self) -> WRITE_R {
+        WRITE_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Configure read permissions for RAM region n"]
+    #[inline(always)]
+    pub fn read(&self) -> READ_R {
+        READ_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Security attribute for RAM region n"]
+    #[inline(always)]
+    pub fn secattr(&self) -> SECATTR_R {
+        SECATTR_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 8"]
+    #[inline(always)]
+    pub fn lock(&self) -> LOCK_R {
+        LOCK_R::new(((self.bits >> 8) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Configure instruction fetch permissions from RAM region n"]
+    #[inline(always)]
+    pub fn execute(&mut self) -> EXECUTE_W<0> {
+        EXECUTE_W::new(self)
+    }
+    #[doc = "Bit 1 - Configure write permission for RAM region n"]
+    #[inline(always)]
+    pub fn write(&mut self) -> WRITE_W<1> {
+        WRITE_W::new(self)
+    }
+    #[doc = "Bit 2 - Configure read permissions for RAM region n"]
+    #[inline(always)]
+    pub fn read(&mut self) -> READ_W<2> {
+        READ_W::new(self)
+    }
+    #[doc = "Bit 4 - Security attribute for RAM region n"]
+    #[inline(always)]
+    pub fn secattr(&mut self) -> SECATTR_W<4> {
+        SECATTR_W::new(self)
+    }
+    #[doc = "Bit 8"]
+    #[inline(always)]
+    pub fn lock(&mut self) -> LOCK_W<8> {
+        LOCK_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Description cluster: Access permissions for RAM region n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perm](index.html) module"]
+pub struct PERM_SPEC;
+impl crate::RegisterSpec for PERM_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [perm::R](R) reader structure"]
+impl crate::Readable for PERM_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [perm::W](W) writer structure"]
+impl crate::Writable for PERM_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets PERM to value 0x17"]
+impl crate::Resettable for PERM_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0x17
+    }
+}