feat: add display UI with splash screen, dashboard, and RSSI sparkline

Implement full SSD1306 OLED display support:
- Splash screen on boot (1.5s) with project name, version, board
- Dashboard showing radio state, config, counters, RSSI/SNR
- RSSI history sparkline (64-sample ring buffer, 2px-wide bars)
- DisplayOn/DisplayOff host commands routed via dedicated channel
- Pure render functions against generic DrawTarget (no hardware coupling)
- Display on/off control bypasses radio task entirely

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>

vendor/nrf9160-pac/src/cc_host_rgf_s.rs

@@ -0,0 +1,48 @@
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    _reserved0: [u8; 0x1a38],
+    #[doc = "0x1a38 - AES hardware key select"]
+    pub host_cryptokey_sel: HOST_CRYPTOKEY_SEL,
+    _reserved1: [u8; 0x10],
+    #[doc = "0x1a4c - This write-once register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain."]
+    pub host_iot_kprtl_lock: HOST_IOT_KPRTL_LOCK,
+    #[doc = "0x1a50 - This register holds bits 31:0 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. Reading from this address returns the K_DR valid status indicating if K_DR is successfully retained."]
+    pub host_iot_kdr0: HOST_IOT_KDR0,
+    #[doc = "0x1a54 - This register holds bits 63:32 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain."]
+    pub host_iot_kdr1: HOST_IOT_KDR1,
+    #[doc = "0x1a58 - This register holds bits 95:64 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain."]
+    pub host_iot_kdr2: HOST_IOT_KDR2,
+    #[doc = "0x1a5c - This register holds bits 127:96 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain."]
+    pub host_iot_kdr3: HOST_IOT_KDR3,
+    #[doc = "0x1a60 - Controls lifecycle state (LCS) for CRYPTOCELL subsystem"]
+    pub host_iot_lcs: HOST_IOT_LCS,
+}
+#[doc = "HOST_CRYPTOKEY_SEL (rw) register accessor: an alias for `Reg<HOST_CRYPTOKEY_SEL_SPEC>`"]
+pub type HOST_CRYPTOKEY_SEL = crate::Reg<host_cryptokey_sel::HOST_CRYPTOKEY_SEL_SPEC>;
+#[doc = "AES hardware key select"]
+pub mod host_cryptokey_sel;
+#[doc = "HOST_IOT_KPRTL_LOCK (rw) register accessor: an alias for `Reg<HOST_IOT_KPRTL_LOCK_SPEC>`"]
+pub type HOST_IOT_KPRTL_LOCK = crate::Reg<host_iot_kprtl_lock::HOST_IOT_KPRTL_LOCK_SPEC>;
+#[doc = "This write-once register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain."]
+pub mod host_iot_kprtl_lock;
+#[doc = "HOST_IOT_KDR0 (rw) register accessor: an alias for `Reg<HOST_IOT_KDR0_SPEC>`"]
+pub type HOST_IOT_KDR0 = crate::Reg<host_iot_kdr0::HOST_IOT_KDR0_SPEC>;
+#[doc = "This register holds bits 31:0 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. Reading from this address returns the K_DR valid status indicating if K_DR is successfully retained."]
+pub mod host_iot_kdr0;
+#[doc = "HOST_IOT_KDR1 (w) register accessor: an alias for `Reg<HOST_IOT_KDR1_SPEC>`"]
+pub type HOST_IOT_KDR1 = crate::Reg<host_iot_kdr1::HOST_IOT_KDR1_SPEC>;
+#[doc = "This register holds bits 63:32 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain."]
+pub mod host_iot_kdr1;
+#[doc = "HOST_IOT_KDR2 (w) register accessor: an alias for `Reg<HOST_IOT_KDR2_SPEC>`"]
+pub type HOST_IOT_KDR2 = crate::Reg<host_iot_kdr2::HOST_IOT_KDR2_SPEC>;
+#[doc = "This register holds bits 95:64 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain."]
+pub mod host_iot_kdr2;
+#[doc = "HOST_IOT_KDR3 (w) register accessor: an alias for `Reg<HOST_IOT_KDR3_SPEC>`"]
+pub type HOST_IOT_KDR3 = crate::Reg<host_iot_kdr3::HOST_IOT_KDR3_SPEC>;
+#[doc = "This register holds bits 127:96 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain."]
+pub mod host_iot_kdr3;
+#[doc = "HOST_IOT_LCS (rw) register accessor: an alias for `Reg<HOST_IOT_LCS_SPEC>`"]
+pub type HOST_IOT_LCS = crate::Reg<host_iot_lcs::HOST_IOT_LCS_SPEC>;
+#[doc = "Controls lifecycle state (LCS) for CRYPTOCELL subsystem"]
+pub mod host_iot_lcs;

vendor/nrf9160-pac/src/cc_host_rgf_s/host_cryptokey_sel.rs

@@ -0,0 +1,142 @@
+#[doc = "Register `HOST_CRYPTOKEY_SEL` reader"]
+pub struct R(crate::R<HOST_CRYPTOKEY_SEL_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<HOST_CRYPTOKEY_SEL_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<HOST_CRYPTOKEY_SEL_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<HOST_CRYPTOKEY_SEL_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `HOST_CRYPTOKEY_SEL` writer"]
+pub struct W(crate::W<HOST_CRYPTOKEY_SEL_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<HOST_CRYPTOKEY_SEL_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<HOST_CRYPTOKEY_SEL_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<HOST_CRYPTOKEY_SEL_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `HOST_CRYPTOKEY_SEL` reader - Select the source of the HW key that is used by the AES engine"]
+pub type HOST_CRYPTOKEY_SEL_R = crate::FieldReader<u8, HOST_CRYPTOKEY_SEL_A>;
+#[doc = "Select the source of the HW key that is used by the AES engine\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum HOST_CRYPTOKEY_SEL_A {
+    #[doc = "0: Use device root key K_DR from CRYPTOCELL AO power domain"]
+    K_DR = 0,
+    #[doc = "1: Use hard-coded RTL key K_PRTL"]
+    K_PRTL = 1,
+    #[doc = "2: Use provided session key"]
+    SESSION = 2,
+}
+impl From<HOST_CRYPTOKEY_SEL_A> for u8 {
+    #[inline(always)]
+    fn from(variant: HOST_CRYPTOKEY_SEL_A) -> Self {
+        variant as _
+    }
+}
+impl HOST_CRYPTOKEY_SEL_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<HOST_CRYPTOKEY_SEL_A> {
+        match self.bits {
+            0 => Some(HOST_CRYPTOKEY_SEL_A::K_DR),
+            1 => Some(HOST_CRYPTOKEY_SEL_A::K_PRTL),
+            2 => Some(HOST_CRYPTOKEY_SEL_A::SESSION),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `K_DR`"]
+    #[inline(always)]
+    pub fn is_k_dr(&self) -> bool {
+        *self == HOST_CRYPTOKEY_SEL_A::K_DR
+    }
+    #[doc = "Checks if the value of the field is `K_PRTL`"]
+    #[inline(always)]
+    pub fn is_k_prtl(&self) -> bool {
+        *self == HOST_CRYPTOKEY_SEL_A::K_PRTL
+    }
+    #[doc = "Checks if the value of the field is `SESSION`"]
+    #[inline(always)]
+    pub fn is_session(&self) -> bool {
+        *self == HOST_CRYPTOKEY_SEL_A::SESSION
+    }
+}
+#[doc = "Field `HOST_CRYPTOKEY_SEL` writer - Select the source of the HW key that is used by the AES engine"]
+pub type HOST_CRYPTOKEY_SEL_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u32, HOST_CRYPTOKEY_SEL_SPEC, u8, HOST_CRYPTOKEY_SEL_A, 2, O>;
+impl<'a, const O: u8> HOST_CRYPTOKEY_SEL_W<'a, O> {
+    #[doc = "Use device root key K_DR from CRYPTOCELL AO power domain"]
+    #[inline(always)]
+    pub fn k_dr(self) -> &'a mut W {
+        self.variant(HOST_CRYPTOKEY_SEL_A::K_DR)
+    }
+    #[doc = "Use hard-coded RTL key K_PRTL"]
+    #[inline(always)]
+    pub fn k_prtl(self) -> &'a mut W {
+        self.variant(HOST_CRYPTOKEY_SEL_A::K_PRTL)
+    }
+    #[doc = "Use provided session key"]
+    #[inline(always)]
+    pub fn session(self) -> &'a mut W {
+        self.variant(HOST_CRYPTOKEY_SEL_A::SESSION)
+    }
+}
+impl R {
+    #[doc = "Bits 0:1 - Select the source of the HW key that is used by the AES engine"]
+    #[inline(always)]
+    pub fn host_cryptokey_sel(&self) -> HOST_CRYPTOKEY_SEL_R {
+        HOST_CRYPTOKEY_SEL_R::new((self.bits & 3) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:1 - Select the source of the HW key that is used by the AES engine"]
+    #[inline(always)]
+    pub fn host_cryptokey_sel(&mut self) -> HOST_CRYPTOKEY_SEL_W<0> {
+        HOST_CRYPTOKEY_SEL_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "AES hardware key select\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [host_cryptokey_sel](index.html) module"]
+pub struct HOST_CRYPTOKEY_SEL_SPEC;
+impl crate::RegisterSpec for HOST_CRYPTOKEY_SEL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [host_cryptokey_sel::R](R) reader structure"]
+impl crate::Readable for HOST_CRYPTOKEY_SEL_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [host_cryptokey_sel::W](W) writer structure"]
+impl crate::Writable for HOST_CRYPTOKEY_SEL_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets HOST_CRYPTOKEY_SEL to value 0"]
+impl crate::Resettable for HOST_CRYPTOKEY_SEL_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9160-pac/src/cc_host_rgf_s/host_iot_kdr0.rs

@@ -0,0 +1,81 @@
+#[doc = "Register `HOST_IOT_KDR0` reader"]
+pub struct R(crate::R<HOST_IOT_KDR0_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<HOST_IOT_KDR0_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<HOST_IOT_KDR0_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<HOST_IOT_KDR0_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `HOST_IOT_KDR0` writer"]
+pub struct W(crate::W<HOST_IOT_KDR0_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<HOST_IOT_KDR0_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<HOST_IOT_KDR0_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<HOST_IOT_KDR0_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `HOST_IOT_KDR0` reader - Write: K_DR bits 31:0. Read: 0x00000000 when 128-bit K_DR key value is not yet retained in the CRYPTOCELL AO power domain. Read: 0x00000001 when 128-bit K_DR key value is successfully retained in the CRYPTOCELL AO power domain."]
+pub type HOST_IOT_KDR0_R = crate::FieldReader<u32, u32>;
+#[doc = "Field `HOST_IOT_KDR0` writer - Write: K_DR bits 31:0. Read: 0x00000000 when 128-bit K_DR key value is not yet retained in the CRYPTOCELL AO power domain. Read: 0x00000001 when 128-bit K_DR key value is successfully retained in the CRYPTOCELL AO power domain."]
+pub type HOST_IOT_KDR0_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u32, HOST_IOT_KDR0_SPEC, u32, u32, 32, O>;
+impl R {
+    #[doc = "Bits 0:31 - Write: K_DR bits 31:0. Read: 0x00000000 when 128-bit K_DR key value is not yet retained in the CRYPTOCELL AO power domain. Read: 0x00000001 when 128-bit K_DR key value is successfully retained in the CRYPTOCELL AO power domain."]
+    #[inline(always)]
+    pub fn host_iot_kdr0(&self) -> HOST_IOT_KDR0_R {
+        HOST_IOT_KDR0_R::new(self.bits)
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Write: K_DR bits 31:0. Read: 0x00000000 when 128-bit K_DR key value is not yet retained in the CRYPTOCELL AO power domain. Read: 0x00000001 when 128-bit K_DR key value is successfully retained in the CRYPTOCELL AO power domain."]
+    #[inline(always)]
+    pub fn host_iot_kdr0(&mut self) -> HOST_IOT_KDR0_W<0> {
+        HOST_IOT_KDR0_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "This register holds bits 31:0 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. Reading from this address returns the K_DR valid status indicating if K_DR is successfully retained.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [host_iot_kdr0](index.html) module"]
+pub struct HOST_IOT_KDR0_SPEC;
+impl crate::RegisterSpec for HOST_IOT_KDR0_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [host_iot_kdr0::R](R) reader structure"]
+impl crate::Readable for HOST_IOT_KDR0_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [host_iot_kdr0::W](W) writer structure"]
+impl crate::Writable for HOST_IOT_KDR0_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets HOST_IOT_KDR0 to value 0"]
+impl crate::Resettable for HOST_IOT_KDR0_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9160-pac/src/cc_host_rgf_s/host_iot_kdr1.rs

@@ -0,0 +1,53 @@
+#[doc = "Register `HOST_IOT_KDR1` writer"]
+pub struct W(crate::W<HOST_IOT_KDR1_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<HOST_IOT_KDR1_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<HOST_IOT_KDR1_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<HOST_IOT_KDR1_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `HOST_IOT_KDR1` writer - K_DR bits 63:32"]
+pub type HOST_IOT_KDR1_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u32, HOST_IOT_KDR1_SPEC, u32, u32, 32, O>;
+impl W {
+    #[doc = "Bits 0:31 - K_DR bits 63:32"]
+    #[inline(always)]
+    pub fn host_iot_kdr1(&mut self) -> HOST_IOT_KDR1_W<0> {
+        HOST_IOT_KDR1_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "This register holds bits 63:32 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain.\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [host_iot_kdr1](index.html) module"]
+pub struct HOST_IOT_KDR1_SPEC;
+impl crate::RegisterSpec for HOST_IOT_KDR1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [host_iot_kdr1::W](W) writer structure"]
+impl crate::Writable for HOST_IOT_KDR1_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets HOST_IOT_KDR1 to value 0"]
+impl crate::Resettable for HOST_IOT_KDR1_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9160-pac/src/cc_host_rgf_s/host_iot_kdr2.rs

@@ -0,0 +1,53 @@
+#[doc = "Register `HOST_IOT_KDR2` writer"]
+pub struct W(crate::W<HOST_IOT_KDR2_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<HOST_IOT_KDR2_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<HOST_IOT_KDR2_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<HOST_IOT_KDR2_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `HOST_IOT_KDR2` writer - K_DR bits 95:64"]
+pub type HOST_IOT_KDR2_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u32, HOST_IOT_KDR2_SPEC, u32, u32, 32, O>;
+impl W {
+    #[doc = "Bits 0:31 - K_DR bits 95:64"]
+    #[inline(always)]
+    pub fn host_iot_kdr2(&mut self) -> HOST_IOT_KDR2_W<0> {
+        HOST_IOT_KDR2_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "This register holds bits 95:64 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain.\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [host_iot_kdr2](index.html) module"]
+pub struct HOST_IOT_KDR2_SPEC;
+impl crate::RegisterSpec for HOST_IOT_KDR2_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [host_iot_kdr2::W](W) writer structure"]
+impl crate::Writable for HOST_IOT_KDR2_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets HOST_IOT_KDR2 to value 0"]
+impl crate::Resettable for HOST_IOT_KDR2_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9160-pac/src/cc_host_rgf_s/host_iot_kdr3.rs

@@ -0,0 +1,53 @@
+#[doc = "Register `HOST_IOT_KDR3` writer"]
+pub struct W(crate::W<HOST_IOT_KDR3_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<HOST_IOT_KDR3_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<HOST_IOT_KDR3_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<HOST_IOT_KDR3_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `HOST_IOT_KDR3` writer - K_DR bits 127:96"]
+pub type HOST_IOT_KDR3_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u32, HOST_IOT_KDR3_SPEC, u32, u32, 32, O>;
+impl W {
+    #[doc = "Bits 0:31 - K_DR bits 127:96"]
+    #[inline(always)]
+    pub fn host_iot_kdr3(&mut self) -> HOST_IOT_KDR3_W<0> {
+        HOST_IOT_KDR3_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "This register holds bits 127:96 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain.\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [host_iot_kdr3](index.html) module"]
+pub struct HOST_IOT_KDR3_SPEC;
+impl crate::RegisterSpec for HOST_IOT_KDR3_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [host_iot_kdr3::W](W) writer structure"]
+impl crate::Writable for HOST_IOT_KDR3_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets HOST_IOT_KDR3 to value 0"]
+impl crate::Resettable for HOST_IOT_KDR3_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9160-pac/src/cc_host_rgf_s/host_iot_kprtl_lock.rs

@@ -0,0 +1,127 @@
+#[doc = "Register `HOST_IOT_KPRTL_LOCK` reader"]
+pub struct R(crate::R<HOST_IOT_KPRTL_LOCK_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<HOST_IOT_KPRTL_LOCK_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<HOST_IOT_KPRTL_LOCK_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<HOST_IOT_KPRTL_LOCK_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `HOST_IOT_KPRTL_LOCK` writer"]
+pub struct W(crate::W<HOST_IOT_KPRTL_LOCK_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<HOST_IOT_KPRTL_LOCK_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<HOST_IOT_KPRTL_LOCK_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<HOST_IOT_KPRTL_LOCK_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `HOST_IOT_KPRTL_LOCK` reader - This register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain."]
+pub type HOST_IOT_KPRTL_LOCK_R = crate::BitReader<HOST_IOT_KPRTL_LOCK_A>;
+#[doc = "This register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum HOST_IOT_KPRTL_LOCK_A {
+    #[doc = "0: K_PRTL can be selected for use from register HOST_CRYPTOKEY_SEL"]
+    DISABLED = 0,
+    #[doc = "1: K_PRTL has been locked until next power-on reset (POR). If K_PRTL is selected anyway, a zeroed key will be used instead."]
+    ENABLED = 1,
+}
+impl From<HOST_IOT_KPRTL_LOCK_A> for bool {
+    #[inline(always)]
+    fn from(variant: HOST_IOT_KPRTL_LOCK_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl HOST_IOT_KPRTL_LOCK_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> HOST_IOT_KPRTL_LOCK_A {
+        match self.bits {
+            false => HOST_IOT_KPRTL_LOCK_A::DISABLED,
+            true => HOST_IOT_KPRTL_LOCK_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == HOST_IOT_KPRTL_LOCK_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == HOST_IOT_KPRTL_LOCK_A::ENABLED
+    }
+}
+#[doc = "Field `HOST_IOT_KPRTL_LOCK` writer - This register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain."]
+pub type HOST_IOT_KPRTL_LOCK_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, HOST_IOT_KPRTL_LOCK_SPEC, HOST_IOT_KPRTL_LOCK_A, O>;
+impl<'a, const O: u8> HOST_IOT_KPRTL_LOCK_W<'a, O> {
+    #[doc = "K_PRTL can be selected for use from register HOST_CRYPTOKEY_SEL"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(HOST_IOT_KPRTL_LOCK_A::DISABLED)
+    }
+    #[doc = "K_PRTL has been locked until next power-on reset (POR). If K_PRTL is selected anyway, a zeroed key will be used instead."]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(HOST_IOT_KPRTL_LOCK_A::ENABLED)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - This register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain."]
+    #[inline(always)]
+    pub fn host_iot_kprtl_lock(&self) -> HOST_IOT_KPRTL_LOCK_R {
+        HOST_IOT_KPRTL_LOCK_R::new((self.bits & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - This register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain."]
+    #[inline(always)]
+    pub fn host_iot_kprtl_lock(&mut self) -> HOST_IOT_KPRTL_LOCK_W<0> {
+        HOST_IOT_KPRTL_LOCK_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "This write-once register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [host_iot_kprtl_lock](index.html) module"]
+pub struct HOST_IOT_KPRTL_LOCK_SPEC;
+impl crate::RegisterSpec for HOST_IOT_KPRTL_LOCK_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [host_iot_kprtl_lock::R](R) reader structure"]
+impl crate::Readable for HOST_IOT_KPRTL_LOCK_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [host_iot_kprtl_lock::W](W) writer structure"]
+impl crate::Writable for HOST_IOT_KPRTL_LOCK_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets HOST_IOT_KPRTL_LOCK to value 0"]
+impl crate::Resettable for HOST_IOT_KPRTL_LOCK_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9160-pac/src/cc_host_rgf_s/host_iot_lcs.rs

@@ -0,0 +1,189 @@
+#[doc = "Register `HOST_IOT_LCS` reader"]
+pub struct R(crate::R<HOST_IOT_LCS_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<HOST_IOT_LCS_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<HOST_IOT_LCS_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<HOST_IOT_LCS_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `HOST_IOT_LCS` writer"]
+pub struct W(crate::W<HOST_IOT_LCS_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<HOST_IOT_LCS_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<HOST_IOT_LCS_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<HOST_IOT_LCS_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `LCS` reader - Lifecycle state value. This field is write-once per reset."]
+pub type LCS_R = crate::FieldReader<u8, LCS_A>;
+#[doc = "Lifecycle state value. This field is write-once per reset.\n\nValue on reset: 2"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum LCS_A {
+    #[doc = "0: CC310 operates in debug mode"]
+    DEBUG = 0,
+    #[doc = "2: CC310 operates in secure mode"]
+    SECURE = 2,
+}
+impl From<LCS_A> for u8 {
+    #[inline(always)]
+    fn from(variant: LCS_A) -> Self {
+        variant as _
+    }
+}
+impl LCS_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<LCS_A> {
+        match self.bits {
+            0 => Some(LCS_A::DEBUG),
+            2 => Some(LCS_A::SECURE),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DEBUG`"]
+    #[inline(always)]
+    pub fn is_debug(&self) -> bool {
+        *self == LCS_A::DEBUG
+    }
+    #[doc = "Checks if the value of the field is `SECURE`"]
+    #[inline(always)]
+    pub fn is_secure(&self) -> bool {
+        *self == LCS_A::SECURE
+    }
+}
+#[doc = "Field `LCS` writer - Lifecycle state value. This field is write-once per reset."]
+pub type LCS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HOST_IOT_LCS_SPEC, u8, LCS_A, 3, O>;
+impl<'a, const O: u8> LCS_W<'a, O> {
+    #[doc = "CC310 operates in debug mode"]
+    #[inline(always)]
+    pub fn debug(self) -> &'a mut W {
+        self.variant(LCS_A::DEBUG)
+    }
+    #[doc = "CC310 operates in secure mode"]
+    #[inline(always)]
+    pub fn secure(self) -> &'a mut W {
+        self.variant(LCS_A::SECURE)
+    }
+}
+#[doc = "Field `LCS_IS_VALID` reader - Read-only field. Indicates if CRYPTOCELL LCS has been successfully configured since last reset."]
+pub type LCS_IS_VALID_R = crate::BitReader<LCS_IS_VALID_A>;
+#[doc = "Read-only field. Indicates if CRYPTOCELL LCS has been successfully configured since last reset.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum LCS_IS_VALID_A {
+    #[doc = "0: Valid LCS not yet retained in the CRYPTOCELL AO power domain"]
+    INVALID = 0,
+    #[doc = "1: Valid LCS successfully retained in the CRYPTOCELL AO power domain"]
+    VALID = 1,
+}
+impl From<LCS_IS_VALID_A> for bool {
+    #[inline(always)]
+    fn from(variant: LCS_IS_VALID_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl LCS_IS_VALID_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> LCS_IS_VALID_A {
+        match self.bits {
+            false => LCS_IS_VALID_A::INVALID,
+            true => LCS_IS_VALID_A::VALID,
+        }
+    }
+    #[doc = "Checks if the value of the field is `INVALID`"]
+    #[inline(always)]
+    pub fn is_invalid(&self) -> bool {
+        *self == LCS_IS_VALID_A::INVALID
+    }
+    #[doc = "Checks if the value of the field is `VALID`"]
+    #[inline(always)]
+    pub fn is_valid(&self) -> bool {
+        *self == LCS_IS_VALID_A::VALID
+    }
+}
+#[doc = "Field `LCS_IS_VALID` writer - Read-only field. Indicates if CRYPTOCELL LCS has been successfully configured since last reset."]
+pub type LCS_IS_VALID_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, HOST_IOT_LCS_SPEC, LCS_IS_VALID_A, O>;
+impl<'a, const O: u8> LCS_IS_VALID_W<'a, O> {
+    #[doc = "Valid LCS not yet retained in the CRYPTOCELL AO power domain"]
+    #[inline(always)]
+    pub fn invalid(self) -> &'a mut W {
+        self.variant(LCS_IS_VALID_A::INVALID)
+    }
+    #[doc = "Valid LCS successfully retained in the CRYPTOCELL AO power domain"]
+    #[inline(always)]
+    pub fn valid(self) -> &'a mut W {
+        self.variant(LCS_IS_VALID_A::VALID)
+    }
+}
+impl R {
+    #[doc = "Bits 0:2 - Lifecycle state value. This field is write-once per reset."]
+    #[inline(always)]
+    pub fn lcs(&self) -> LCS_R {
+        LCS_R::new((self.bits & 7) as u8)
+    }
+    #[doc = "Bit 8 - Read-only field. Indicates if CRYPTOCELL LCS has been successfully configured since last reset."]
+    #[inline(always)]
+    pub fn lcs_is_valid(&self) -> LCS_IS_VALID_R {
+        LCS_IS_VALID_R::new(((self.bits >> 8) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:2 - Lifecycle state value. This field is write-once per reset."]
+    #[inline(always)]
+    pub fn lcs(&mut self) -> LCS_W<0> {
+        LCS_W::new(self)
+    }
+    #[doc = "Bit 8 - Read-only field. Indicates if CRYPTOCELL LCS has been successfully configured since last reset."]
+    #[inline(always)]
+    pub fn lcs_is_valid(&mut self) -> LCS_IS_VALID_W<8> {
+        LCS_IS_VALID_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Controls lifecycle state (LCS) for CRYPTOCELL subsystem\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [host_iot_lcs](index.html) module"]
+pub struct HOST_IOT_LCS_SPEC;
+impl crate::RegisterSpec for HOST_IOT_LCS_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [host_iot_lcs::R](R) reader structure"]
+impl crate::Readable for HOST_IOT_LCS_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [host_iot_lcs::W](W) writer structure"]
+impl crate::Writable for HOST_IOT_LCS_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets HOST_IOT_LCS to value 0x02"]
+impl crate::Resettable for HOST_IOT_LCS_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0x02
+    }
+}

vendor/nrf9160-pac/src/clock_ns.rs

@@ -0,0 +1,143 @@
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00 - Start HFCLK source"]
+    pub tasks_hfclkstart: TASKS_HFCLKSTART,
+    #[doc = "0x04 - Stop HFCLK source"]
+    pub tasks_hfclkstop: TASKS_HFCLKSTOP,
+    #[doc = "0x08 - Start LFCLK source"]
+    pub tasks_lfclkstart: TASKS_LFCLKSTART,
+    #[doc = "0x0c - Stop LFCLK source"]
+    pub tasks_lfclkstop: TASKS_LFCLKSTOP,
+    _reserved4: [u8; 0x70],
+    #[doc = "0x80 - Subscribe configuration for task HFCLKSTART"]
+    pub subscribe_hfclkstart: SUBSCRIBE_HFCLKSTART,
+    #[doc = "0x84 - Subscribe configuration for task HFCLKSTOP"]
+    pub subscribe_hfclkstop: SUBSCRIBE_HFCLKSTOP,
+    #[doc = "0x88 - Subscribe configuration for task LFCLKSTART"]
+    pub subscribe_lfclkstart: SUBSCRIBE_LFCLKSTART,
+    #[doc = "0x8c - Subscribe configuration for task LFCLKSTOP"]
+    pub subscribe_lfclkstop: SUBSCRIBE_LFCLKSTOP,
+    _reserved8: [u8; 0x70],
+    #[doc = "0x100 - HFCLK oscillator started"]
+    pub events_hfclkstarted: EVENTS_HFCLKSTARTED,
+    #[doc = "0x104 - LFCLK started"]
+    pub events_lfclkstarted: EVENTS_LFCLKSTARTED,
+    _reserved10: [u8; 0x78],
+    #[doc = "0x180 - Publish configuration for event HFCLKSTARTED"]
+    pub publish_hfclkstarted: PUBLISH_HFCLKSTARTED,
+    #[doc = "0x184 - Publish configuration for event LFCLKSTARTED"]
+    pub publish_lfclkstarted: PUBLISH_LFCLKSTARTED,
+    _reserved12: [u8; 0x0178],
+    #[doc = "0x300 - Enable or disable interrupt"]
+    pub inten: INTEN,
+    #[doc = "0x304 - Enable interrupt"]
+    pub intenset: INTENSET,
+    #[doc = "0x308 - Disable interrupt"]
+    pub intenclr: INTENCLR,
+    #[doc = "0x30c - Pending interrupts"]
+    pub intpend: INTPEND,
+    _reserved16: [u8; 0xf8],
+    #[doc = "0x408 - Status indicating that HFCLKSTART task has been triggered"]
+    pub hfclkrun: HFCLKRUN,
+    #[doc = "0x40c - The register shows if HFXO has been requested by triggering HFCLKSTART task and if it has been started (STATE)"]
+    pub hfclkstat: HFCLKSTAT,
+    _reserved18: [u8; 0x04],
+    #[doc = "0x414 - Status indicating that LFCLKSTART task has been triggered"]
+    pub lfclkrun: LFCLKRUN,
+    #[doc = "0x418 - The register shows which LFCLK source has been requested (SRC) when triggering LFCLKSTART task and if the source has been started (STATE)"]
+    pub lfclkstat: LFCLKSTAT,
+    #[doc = "0x41c - Copy of LFCLKSRC register, set after LFCLKSTART task has been triggered"]
+    pub lfclksrccopy: LFCLKSRCCOPY,
+    _reserved21: [u8; 0xf8],
+    #[doc = "0x518 - Clock source for the LFCLK. LFCLKSTART task starts starts a clock source selected with this register."]
+    pub lfclksrc: LFCLKSRC,
+}
+#[doc = "TASKS_HFCLKSTART (w) register accessor: an alias for `Reg<TASKS_HFCLKSTART_SPEC>`"]
+pub type TASKS_HFCLKSTART = crate::Reg<tasks_hfclkstart::TASKS_HFCLKSTART_SPEC>;
+#[doc = "Start HFCLK source"]
+pub mod tasks_hfclkstart;
+#[doc = "TASKS_HFCLKSTOP (w) register accessor: an alias for `Reg<TASKS_HFCLKSTOP_SPEC>`"]
+pub type TASKS_HFCLKSTOP = crate::Reg<tasks_hfclkstop::TASKS_HFCLKSTOP_SPEC>;
+#[doc = "Stop HFCLK source"]
+pub mod tasks_hfclkstop;
+#[doc = "TASKS_LFCLKSTART (w) register accessor: an alias for `Reg<TASKS_LFCLKSTART_SPEC>`"]
+pub type TASKS_LFCLKSTART = crate::Reg<tasks_lfclkstart::TASKS_LFCLKSTART_SPEC>;
+#[doc = "Start LFCLK source"]
+pub mod tasks_lfclkstart;
+#[doc = "TASKS_LFCLKSTOP (w) register accessor: an alias for `Reg<TASKS_LFCLKSTOP_SPEC>`"]
+pub type TASKS_LFCLKSTOP = crate::Reg<tasks_lfclkstop::TASKS_LFCLKSTOP_SPEC>;
+#[doc = "Stop LFCLK source"]
+pub mod tasks_lfclkstop;
+#[doc = "SUBSCRIBE_HFCLKSTART (rw) register accessor: an alias for `Reg<SUBSCRIBE_HFCLKSTART_SPEC>`"]
+pub type SUBSCRIBE_HFCLKSTART = crate::Reg<subscribe_hfclkstart::SUBSCRIBE_HFCLKSTART_SPEC>;
+#[doc = "Subscribe configuration for task HFCLKSTART"]
+pub mod subscribe_hfclkstart;
+#[doc = "SUBSCRIBE_HFCLKSTOP (rw) register accessor: an alias for `Reg<SUBSCRIBE_HFCLKSTOP_SPEC>`"]
+pub type SUBSCRIBE_HFCLKSTOP = crate::Reg<subscribe_hfclkstop::SUBSCRIBE_HFCLKSTOP_SPEC>;
+#[doc = "Subscribe configuration for task HFCLKSTOP"]
+pub mod subscribe_hfclkstop;
+#[doc = "SUBSCRIBE_LFCLKSTART (rw) register accessor: an alias for `Reg<SUBSCRIBE_LFCLKSTART_SPEC>`"]
+pub type SUBSCRIBE_LFCLKSTART = crate::Reg<subscribe_lfclkstart::SUBSCRIBE_LFCLKSTART_SPEC>;
+#[doc = "Subscribe configuration for task LFCLKSTART"]
+pub mod subscribe_lfclkstart;
+#[doc = "SUBSCRIBE_LFCLKSTOP (rw) register accessor: an alias for `Reg<SUBSCRIBE_LFCLKSTOP_SPEC>`"]
+pub type SUBSCRIBE_LFCLKSTOP = crate::Reg<subscribe_lfclkstop::SUBSCRIBE_LFCLKSTOP_SPEC>;
+#[doc = "Subscribe configuration for task LFCLKSTOP"]
+pub mod subscribe_lfclkstop;
+#[doc = "EVENTS_HFCLKSTARTED (rw) register accessor: an alias for `Reg<EVENTS_HFCLKSTARTED_SPEC>`"]
+pub type EVENTS_HFCLKSTARTED = crate::Reg<events_hfclkstarted::EVENTS_HFCLKSTARTED_SPEC>;
+#[doc = "HFCLK oscillator started"]
+pub mod events_hfclkstarted;
+#[doc = "EVENTS_LFCLKSTARTED (rw) register accessor: an alias for `Reg<EVENTS_LFCLKSTARTED_SPEC>`"]
+pub type EVENTS_LFCLKSTARTED = crate::Reg<events_lfclkstarted::EVENTS_LFCLKSTARTED_SPEC>;
+#[doc = "LFCLK started"]
+pub mod events_lfclkstarted;
+#[doc = "PUBLISH_HFCLKSTARTED (rw) register accessor: an alias for `Reg<PUBLISH_HFCLKSTARTED_SPEC>`"]
+pub type PUBLISH_HFCLKSTARTED = crate::Reg<publish_hfclkstarted::PUBLISH_HFCLKSTARTED_SPEC>;
+#[doc = "Publish configuration for event HFCLKSTARTED"]
+pub mod publish_hfclkstarted;
+#[doc = "PUBLISH_LFCLKSTARTED (rw) register accessor: an alias for `Reg<PUBLISH_LFCLKSTARTED_SPEC>`"]
+pub type PUBLISH_LFCLKSTARTED = crate::Reg<publish_lfclkstarted::PUBLISH_LFCLKSTARTED_SPEC>;
+#[doc = "Publish configuration for event LFCLKSTARTED"]
+pub mod publish_lfclkstarted;
+#[doc = "INTEN (rw) register accessor: an alias for `Reg<INTEN_SPEC>`"]
+pub type INTEN = crate::Reg<inten::INTEN_SPEC>;
+#[doc = "Enable or disable interrupt"]
+pub mod inten;
+#[doc = "INTENSET (rw) register accessor: an alias for `Reg<INTENSET_SPEC>`"]
+pub type INTENSET = crate::Reg<intenset::INTENSET_SPEC>;
+#[doc = "Enable interrupt"]
+pub mod intenset;
+#[doc = "INTENCLR (rw) register accessor: an alias for `Reg<INTENCLR_SPEC>`"]
+pub type INTENCLR = crate::Reg<intenclr::INTENCLR_SPEC>;
+#[doc = "Disable interrupt"]
+pub mod intenclr;
+#[doc = "INTPEND (r) register accessor: an alias for `Reg<INTPEND_SPEC>`"]
+pub type INTPEND = crate::Reg<intpend::INTPEND_SPEC>;
+#[doc = "Pending interrupts"]
+pub mod intpend;
+#[doc = "HFCLKRUN (r) register accessor: an alias for `Reg<HFCLKRUN_SPEC>`"]
+pub type HFCLKRUN = crate::Reg<hfclkrun::HFCLKRUN_SPEC>;
+#[doc = "Status indicating that HFCLKSTART task has been triggered"]
+pub mod hfclkrun;
+#[doc = "HFCLKSTAT (r) register accessor: an alias for `Reg<HFCLKSTAT_SPEC>`"]
+pub type HFCLKSTAT = crate::Reg<hfclkstat::HFCLKSTAT_SPEC>;
+#[doc = "The register shows if HFXO has been requested by triggering HFCLKSTART task and if it has been started (STATE)"]
+pub mod hfclkstat;
+#[doc = "LFCLKRUN (r) register accessor: an alias for `Reg<LFCLKRUN_SPEC>`"]
+pub type LFCLKRUN = crate::Reg<lfclkrun::LFCLKRUN_SPEC>;
+#[doc = "Status indicating that LFCLKSTART task has been triggered"]
+pub mod lfclkrun;
+#[doc = "LFCLKSTAT (r) register accessor: an alias for `Reg<LFCLKSTAT_SPEC>`"]
+pub type LFCLKSTAT = crate::Reg<lfclkstat::LFCLKSTAT_SPEC>;
+#[doc = "The register shows which LFCLK source has been requested (SRC) when triggering LFCLKSTART task and if the source has been started (STATE)"]
+pub mod lfclkstat;
+#[doc = "LFCLKSRCCOPY (r) register accessor: an alias for `Reg<LFCLKSRCCOPY_SPEC>`"]
+pub type LFCLKSRCCOPY = crate::Reg<lfclksrccopy::LFCLKSRCCOPY_SPEC>;
+#[doc = "Copy of LFCLKSRC register, set after LFCLKSTART task has been triggered"]
+pub mod lfclksrccopy;
+#[doc = "LFCLKSRC (rw) register accessor: an alias for `Reg<LFCLKSRC_SPEC>`"]
+pub type LFCLKSRC = crate::Reg<lfclksrc::LFCLKSRC_SPEC>;
+#[doc = "Clock source for the LFCLK. LFCLKSTART task starts starts a clock source selected with this register."]
+pub mod lfclksrc;

vendor/nrf9160-pac/src/clock_ns/events_hfclkstarted.rs

@@ -0,0 +1,127 @@
+#[doc = "Register `EVENTS_HFCLKSTARTED` reader"]
+pub struct R(crate::R<EVENTS_HFCLKSTARTED_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<EVENTS_HFCLKSTARTED_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<EVENTS_HFCLKSTARTED_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<EVENTS_HFCLKSTARTED_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `EVENTS_HFCLKSTARTED` writer"]
+pub struct W(crate::W<EVENTS_HFCLKSTARTED_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<EVENTS_HFCLKSTARTED_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<EVENTS_HFCLKSTARTED_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<EVENTS_HFCLKSTARTED_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `EVENTS_HFCLKSTARTED` reader - HFCLK oscillator started"]
+pub type EVENTS_HFCLKSTARTED_R = crate::BitReader<EVENTS_HFCLKSTARTED_A>;
+#[doc = "HFCLK oscillator started\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum EVENTS_HFCLKSTARTED_A {
+    #[doc = "0: Event not generated"]
+    NOT_GENERATED = 0,
+    #[doc = "1: Event generated"]
+    GENERATED = 1,
+}
+impl From<EVENTS_HFCLKSTARTED_A> for bool {
+    #[inline(always)]
+    fn from(variant: EVENTS_HFCLKSTARTED_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl EVENTS_HFCLKSTARTED_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> EVENTS_HFCLKSTARTED_A {
+        match self.bits {
+            false => EVENTS_HFCLKSTARTED_A::NOT_GENERATED,
+            true => EVENTS_HFCLKSTARTED_A::GENERATED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `NOT_GENERATED`"]
+    #[inline(always)]
+    pub fn is_not_generated(&self) -> bool {
+        *self == EVENTS_HFCLKSTARTED_A::NOT_GENERATED
+    }
+    #[doc = "Checks if the value of the field is `GENERATED`"]
+    #[inline(always)]
+    pub fn is_generated(&self) -> bool {
+        *self == EVENTS_HFCLKSTARTED_A::GENERATED
+    }
+}
+#[doc = "Field `EVENTS_HFCLKSTARTED` writer - HFCLK oscillator started"]
+pub type EVENTS_HFCLKSTARTED_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, EVENTS_HFCLKSTARTED_SPEC, EVENTS_HFCLKSTARTED_A, O>;
+impl<'a, const O: u8> EVENTS_HFCLKSTARTED_W<'a, O> {
+    #[doc = "Event not generated"]
+    #[inline(always)]
+    pub fn not_generated(self) -> &'a mut W {
+        self.variant(EVENTS_HFCLKSTARTED_A::NOT_GENERATED)
+    }
+    #[doc = "Event generated"]
+    #[inline(always)]
+    pub fn generated(self) -> &'a mut W {
+        self.variant(EVENTS_HFCLKSTARTED_A::GENERATED)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - HFCLK oscillator started"]
+    #[inline(always)]
+    pub fn events_hfclkstarted(&self) -> EVENTS_HFCLKSTARTED_R {
+        EVENTS_HFCLKSTARTED_R::new((self.bits & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - HFCLK oscillator started"]
+    #[inline(always)]
+    pub fn events_hfclkstarted(&mut self) -> EVENTS_HFCLKSTARTED_W<0> {
+        EVENTS_HFCLKSTARTED_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "HFCLK oscillator started\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_hfclkstarted](index.html) module"]
+pub struct EVENTS_HFCLKSTARTED_SPEC;
+impl crate::RegisterSpec for EVENTS_HFCLKSTARTED_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [events_hfclkstarted::R](R) reader structure"]
+impl crate::Readable for EVENTS_HFCLKSTARTED_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [events_hfclkstarted::W](W) writer structure"]
+impl crate::Writable for EVENTS_HFCLKSTARTED_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets EVENTS_HFCLKSTARTED to value 0"]
+impl crate::Resettable for EVENTS_HFCLKSTARTED_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9160-pac/src/clock_ns/events_lfclkstarted.rs

@@ -0,0 +1,127 @@
+#[doc = "Register `EVENTS_LFCLKSTARTED` reader"]
+pub struct R(crate::R<EVENTS_LFCLKSTARTED_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<EVENTS_LFCLKSTARTED_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<EVENTS_LFCLKSTARTED_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<EVENTS_LFCLKSTARTED_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `EVENTS_LFCLKSTARTED` writer"]
+pub struct W(crate::W<EVENTS_LFCLKSTARTED_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<EVENTS_LFCLKSTARTED_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<EVENTS_LFCLKSTARTED_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<EVENTS_LFCLKSTARTED_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `EVENTS_LFCLKSTARTED` reader - LFCLK started"]
+pub type EVENTS_LFCLKSTARTED_R = crate::BitReader<EVENTS_LFCLKSTARTED_A>;
+#[doc = "LFCLK started\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum EVENTS_LFCLKSTARTED_A {
+    #[doc = "0: Event not generated"]
+    NOT_GENERATED = 0,
+    #[doc = "1: Event generated"]
+    GENERATED = 1,
+}
+impl From<EVENTS_LFCLKSTARTED_A> for bool {
+    #[inline(always)]
+    fn from(variant: EVENTS_LFCLKSTARTED_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl EVENTS_LFCLKSTARTED_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> EVENTS_LFCLKSTARTED_A {
+        match self.bits {
+            false => EVENTS_LFCLKSTARTED_A::NOT_GENERATED,
+            true => EVENTS_LFCLKSTARTED_A::GENERATED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `NOT_GENERATED`"]
+    #[inline(always)]
+    pub fn is_not_generated(&self) -> bool {
+        *self == EVENTS_LFCLKSTARTED_A::NOT_GENERATED
+    }
+    #[doc = "Checks if the value of the field is `GENERATED`"]
+    #[inline(always)]
+    pub fn is_generated(&self) -> bool {
+        *self == EVENTS_LFCLKSTARTED_A::GENERATED
+    }
+}
+#[doc = "Field `EVENTS_LFCLKSTARTED` writer - LFCLK started"]
+pub type EVENTS_LFCLKSTARTED_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, EVENTS_LFCLKSTARTED_SPEC, EVENTS_LFCLKSTARTED_A, O>;
+impl<'a, const O: u8> EVENTS_LFCLKSTARTED_W<'a, O> {
+    #[doc = "Event not generated"]
+    #[inline(always)]
+    pub fn not_generated(self) -> &'a mut W {
+        self.variant(EVENTS_LFCLKSTARTED_A::NOT_GENERATED)
+    }
+    #[doc = "Event generated"]
+    #[inline(always)]
+    pub fn generated(self) -> &'a mut W {
+        self.variant(EVENTS_LFCLKSTARTED_A::GENERATED)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - LFCLK started"]
+    #[inline(always)]
+    pub fn events_lfclkstarted(&self) -> EVENTS_LFCLKSTARTED_R {
+        EVENTS_LFCLKSTARTED_R::new((self.bits & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - LFCLK started"]
+    #[inline(always)]
+    pub fn events_lfclkstarted(&mut self) -> EVENTS_LFCLKSTARTED_W<0> {
+        EVENTS_LFCLKSTARTED_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "LFCLK started\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_lfclkstarted](index.html) module"]
+pub struct EVENTS_LFCLKSTARTED_SPEC;
+impl crate::RegisterSpec for EVENTS_LFCLKSTARTED_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [events_lfclkstarted::R](R) reader structure"]
+impl crate::Readable for EVENTS_LFCLKSTARTED_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [events_lfclkstarted::W](W) writer structure"]
+impl crate::Writable for EVENTS_LFCLKSTARTED_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets EVENTS_LFCLKSTARTED to value 0"]
+impl crate::Resettable for EVENTS_LFCLKSTARTED_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9160-pac/src/clock_ns/hfclkrun.rs

@@ -0,0 +1,74 @@
+#[doc = "Register `HFCLKRUN` reader"]
+pub struct R(crate::R<HFCLKRUN_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<HFCLKRUN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<HFCLKRUN_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<HFCLKRUN_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `STATUS` reader - HFCLKSTART task triggered or not"]
+pub type STATUS_R = crate::BitReader<STATUS_A>;
+#[doc = "HFCLKSTART task triggered or not\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum STATUS_A {
+    #[doc = "0: Task not triggered"]
+    NOT_TRIGGERED = 0,
+    #[doc = "1: Task triggered"]
+    TRIGGERED = 1,
+}
+impl From<STATUS_A> for bool {
+    #[inline(always)]
+    fn from(variant: STATUS_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl STATUS_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> STATUS_A {
+        match self.bits {
+            false => STATUS_A::NOT_TRIGGERED,
+            true => STATUS_A::TRIGGERED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `NOT_TRIGGERED`"]
+    #[inline(always)]
+    pub fn is_not_triggered(&self) -> bool {
+        *self == STATUS_A::NOT_TRIGGERED
+    }
+    #[doc = "Checks if the value of the field is `TRIGGERED`"]
+    #[inline(always)]
+    pub fn is_triggered(&self) -> bool {
+        *self == STATUS_A::TRIGGERED
+    }
+}
+impl R {
+    #[doc = "Bit 0 - HFCLKSTART task triggered or not"]
+    #[inline(always)]
+    pub fn status(&self) -> STATUS_R {
+        STATUS_R::new((self.bits & 1) != 0)
+    }
+}
+#[doc = "Status indicating that HFCLKSTART task has been triggered\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hfclkrun](index.html) module"]
+pub struct HFCLKRUN_SPEC;
+impl crate::RegisterSpec for HFCLKRUN_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [hfclkrun::R](R) reader structure"]
+impl crate::Readable for HFCLKRUN_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets HFCLKRUN to value 0"]
+impl crate::Resettable for HFCLKRUN_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9160-pac/src/clock_ns/hfclkstat.rs

@@ -0,0 +1,108 @@
+#[doc = "Register `HFCLKSTAT` reader"]
+pub struct R(crate::R<HFCLKSTAT_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<HFCLKSTAT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<HFCLKSTAT_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<HFCLKSTAT_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `SRC` reader - Active clock source"]
+pub type SRC_R = crate::BitReader<SRC_A>;
+#[doc = "Active clock source\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SRC_A {
+    #[doc = "1: HFXO - 64 MHz clock derived from external 32 MHz crystal oscillator"]
+    HFXO = 1,
+}
+impl From<SRC_A> for bool {
+    #[inline(always)]
+    fn from(variant: SRC_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl SRC_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<SRC_A> {
+        match self.bits {
+            true => Some(SRC_A::HFXO),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `HFXO`"]
+    #[inline(always)]
+    pub fn is_hfxo(&self) -> bool {
+        *self == SRC_A::HFXO
+    }
+}
+#[doc = "Field `STATE` reader - HFCLK state"]
+pub type STATE_R = crate::BitReader<STATE_A>;
+#[doc = "HFCLK state\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum STATE_A {
+    #[doc = "0: HFXO has not been started or HFCLKSTOP task has been triggered"]
+    NOT_RUNNING = 0,
+    #[doc = "1: HFXO has been started (HFCLKSTARTED event has been generated)"]
+    RUNNING = 1,
+}
+impl From<STATE_A> for bool {
+    #[inline(always)]
+    fn from(variant: STATE_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl STATE_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> STATE_A {
+        match self.bits {
+            false => STATE_A::NOT_RUNNING,
+            true => STATE_A::RUNNING,
+        }
+    }
+    #[doc = "Checks if the value of the field is `NOT_RUNNING`"]
+    #[inline(always)]
+    pub fn is_not_running(&self) -> bool {
+        *self == STATE_A::NOT_RUNNING
+    }
+    #[doc = "Checks if the value of the field is `RUNNING`"]
+    #[inline(always)]
+    pub fn is_running(&self) -> bool {
+        *self == STATE_A::RUNNING
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Active clock source"]
+    #[inline(always)]
+    pub fn src(&self) -> SRC_R {
+        SRC_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 16 - HFCLK state"]
+    #[inline(always)]
+    pub fn state(&self) -> STATE_R {
+        STATE_R::new(((self.bits >> 16) & 1) != 0)
+    }
+}
+#[doc = "The register shows if HFXO has been requested by triggering HFCLKSTART task and if it has been started (STATE)\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hfclkstat](index.html) module"]
+pub struct HFCLKSTAT_SPEC;
+impl crate::RegisterSpec for HFCLKSTAT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [hfclkstat::R](R) reader structure"]
+impl crate::Readable for HFCLKSTAT_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets HFCLKSTAT to value 0"]
+impl crate::Resettable for HFCLKSTAT_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9160-pac/src/clock_ns/inten.rs

@@ -0,0 +1,186 @@
+#[doc = "Register `INTEN` reader"]
+pub struct R(crate::R<INTEN_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<INTEN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<INTEN_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<INTEN_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `INTEN` writer"]
+pub struct W(crate::W<INTEN_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<INTEN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<INTEN_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<INTEN_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `HFCLKSTARTED` reader - Enable or disable interrupt for event HFCLKSTARTED"]
+pub type HFCLKSTARTED_R = crate::BitReader<HFCLKSTARTED_A>;
+#[doc = "Enable or disable interrupt for event HFCLKSTARTED\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum HFCLKSTARTED_A {
+    #[doc = "0: Disable"]
+    DISABLED = 0,
+    #[doc = "1: Enable"]
+    ENABLED = 1,
+}
+impl From<HFCLKSTARTED_A> for bool {
+    #[inline(always)]
+    fn from(variant: HFCLKSTARTED_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl HFCLKSTARTED_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> HFCLKSTARTED_A {
+        match self.bits {
+            false => HFCLKSTARTED_A::DISABLED,
+            true => HFCLKSTARTED_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == HFCLKSTARTED_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == HFCLKSTARTED_A::ENABLED
+    }
+}
+#[doc = "Field `HFCLKSTARTED` writer - Enable or disable interrupt for event HFCLKSTARTED"]
+pub type HFCLKSTARTED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, HFCLKSTARTED_A, O>;
+impl<'a, const O: u8> HFCLKSTARTED_W<'a, O> {
+    #[doc = "Disable"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(HFCLKSTARTED_A::DISABLED)
+    }
+    #[doc = "Enable"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(HFCLKSTARTED_A::ENABLED)
+    }
+}
+#[doc = "Field `LFCLKSTARTED` reader - Enable or disable interrupt for event LFCLKSTARTED"]
+pub type LFCLKSTARTED_R = crate::BitReader<LFCLKSTARTED_A>;
+#[doc = "Enable or disable interrupt for event LFCLKSTARTED\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum LFCLKSTARTED_A {
+    #[doc = "0: Disable"]
+    DISABLED = 0,
+    #[doc = "1: Enable"]
+    ENABLED = 1,
+}
+impl From<LFCLKSTARTED_A> for bool {
+    #[inline(always)]
+    fn from(variant: LFCLKSTARTED_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl LFCLKSTARTED_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> LFCLKSTARTED_A {
+        match self.bits {
+            false => LFCLKSTARTED_A::DISABLED,
+            true => LFCLKSTARTED_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == LFCLKSTARTED_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == LFCLKSTARTED_A::ENABLED
+    }
+}
+#[doc = "Field `LFCLKSTARTED` writer - Enable or disable interrupt for event LFCLKSTARTED"]
+pub type LFCLKSTARTED_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTEN_SPEC, LFCLKSTARTED_A, O>;
+impl<'a, const O: u8> LFCLKSTARTED_W<'a, O> {
+    #[doc = "Disable"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(LFCLKSTARTED_A::DISABLED)
+    }
+    #[doc = "Enable"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(LFCLKSTARTED_A::ENABLED)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Enable or disable interrupt for event HFCLKSTARTED"]
+    #[inline(always)]
+    pub fn hfclkstarted(&self) -> HFCLKSTARTED_R {
+        HFCLKSTARTED_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Enable or disable interrupt for event LFCLKSTARTED"]
+    #[inline(always)]
+    pub fn lfclkstarted(&self) -> LFCLKSTARTED_R {
+        LFCLKSTARTED_R::new(((self.bits >> 1) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Enable or disable interrupt for event HFCLKSTARTED"]
+    #[inline(always)]
+    pub fn hfclkstarted(&mut self) -> HFCLKSTARTED_W<0> {
+        HFCLKSTARTED_W::new(self)
+    }
+    #[doc = "Bit 1 - Enable or disable interrupt for event LFCLKSTARTED"]
+    #[inline(always)]
+    pub fn lfclkstarted(&mut self) -> LFCLKSTARTED_W<1> {
+        LFCLKSTARTED_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Enable or disable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [inten](index.html) module"]
+pub struct INTEN_SPEC;
+impl crate::RegisterSpec for INTEN_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [inten::R](R) reader structure"]
+impl crate::Readable for INTEN_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [inten::W](W) writer structure"]
+impl crate::Writable for INTEN_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets INTEN to value 0"]
+impl crate::Resettable for INTEN_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9160-pac/src/clock_ns/intenclr.rs

@@ -0,0 +1,202 @@
+#[doc = "Register `INTENCLR` reader"]
+pub struct R(crate::R<INTENCLR_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<INTENCLR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<INTENCLR_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<INTENCLR_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `INTENCLR` writer"]
+pub struct W(crate::W<INTENCLR_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<INTENCLR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<INTENCLR_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<INTENCLR_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `HFCLKSTARTED` reader - Write '1' to disable interrupt for event HFCLKSTARTED"]
+pub type HFCLKSTARTED_R = crate::BitReader<HFCLKSTARTED_A>;
+#[doc = "Write '1' to disable interrupt for event HFCLKSTARTED\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum HFCLKSTARTED_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<HFCLKSTARTED_A> for bool {
+    #[inline(always)]
+    fn from(variant: HFCLKSTARTED_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl HFCLKSTARTED_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> HFCLKSTARTED_A {
+        match self.bits {
+            false => HFCLKSTARTED_A::DISABLED,
+            true => HFCLKSTARTED_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == HFCLKSTARTED_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == HFCLKSTARTED_A::ENABLED
+    }
+}
+#[doc = "Write '1' to disable interrupt for event HFCLKSTARTED\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum HFCLKSTARTED_AW {
+    #[doc = "1: Disable"]
+    CLEAR = 1,
+}
+impl From<HFCLKSTARTED_AW> for bool {
+    #[inline(always)]
+    fn from(variant: HFCLKSTARTED_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `HFCLKSTARTED` writer - Write '1' to disable interrupt for event HFCLKSTARTED"]
+pub type HFCLKSTARTED_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, INTENCLR_SPEC, HFCLKSTARTED_AW, O>;
+impl<'a, const O: u8> HFCLKSTARTED_W<'a, O> {
+    #[doc = "Disable"]
+    #[inline(always)]
+    pub fn clear(self) -> &'a mut W {
+        self.variant(HFCLKSTARTED_AW::CLEAR)
+    }
+}
+#[doc = "Field `LFCLKSTARTED` reader - Write '1' to disable interrupt for event LFCLKSTARTED"]
+pub type LFCLKSTARTED_R = crate::BitReader<LFCLKSTARTED_A>;
+#[doc = "Write '1' to disable interrupt for event LFCLKSTARTED\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum LFCLKSTARTED_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<LFCLKSTARTED_A> for bool {
+    #[inline(always)]
+    fn from(variant: LFCLKSTARTED_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl LFCLKSTARTED_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> LFCLKSTARTED_A {
+        match self.bits {
+            false => LFCLKSTARTED_A::DISABLED,
+            true => LFCLKSTARTED_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == LFCLKSTARTED_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == LFCLKSTARTED_A::ENABLED
+    }
+}
+#[doc = "Write '1' to disable interrupt for event LFCLKSTARTED\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum LFCLKSTARTED_AW {
+    #[doc = "1: Disable"]
+    CLEAR = 1,
+}
+impl From<LFCLKSTARTED_AW> for bool {
+    #[inline(always)]
+    fn from(variant: LFCLKSTARTED_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `LFCLKSTARTED` writer - Write '1' to disable interrupt for event LFCLKSTARTED"]
+pub type LFCLKSTARTED_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, INTENCLR_SPEC, LFCLKSTARTED_AW, O>;
+impl<'a, const O: u8> LFCLKSTARTED_W<'a, O> {
+    #[doc = "Disable"]
+    #[inline(always)]
+    pub fn clear(self) -> &'a mut W {
+        self.variant(LFCLKSTARTED_AW::CLEAR)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Write '1' to disable interrupt for event HFCLKSTARTED"]
+    #[inline(always)]
+    pub fn hfclkstarted(&self) -> HFCLKSTARTED_R {
+        HFCLKSTARTED_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Write '1' to disable interrupt for event LFCLKSTARTED"]
+    #[inline(always)]
+    pub fn lfclkstarted(&self) -> LFCLKSTARTED_R {
+        LFCLKSTARTED_R::new(((self.bits >> 1) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Write '1' to disable interrupt for event HFCLKSTARTED"]
+    #[inline(always)]
+    pub fn hfclkstarted(&mut self) -> HFCLKSTARTED_W<0> {
+        HFCLKSTARTED_W::new(self)
+    }
+    #[doc = "Bit 1 - Write '1' to disable interrupt for event LFCLKSTARTED"]
+    #[inline(always)]
+    pub fn lfclkstarted(&mut self) -> LFCLKSTARTED_W<1> {
+        LFCLKSTARTED_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Disable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"]
+pub struct INTENCLR_SPEC;
+impl crate::RegisterSpec for INTENCLR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [intenclr::R](R) reader structure"]
+impl crate::Readable for INTENCLR_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"]
+impl crate::Writable for INTENCLR_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets INTENCLR to value 0"]
+impl crate::Resettable for INTENCLR_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9160-pac/src/clock_ns/intenset.rs

@@ -0,0 +1,202 @@
+#[doc = "Register `INTENSET` reader"]
+pub struct R(crate::R<INTENSET_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<INTENSET_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<INTENSET_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<INTENSET_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `INTENSET` writer"]
+pub struct W(crate::W<INTENSET_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<INTENSET_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<INTENSET_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<INTENSET_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `HFCLKSTARTED` reader - Write '1' to enable interrupt for event HFCLKSTARTED"]
+pub type HFCLKSTARTED_R = crate::BitReader<HFCLKSTARTED_A>;
+#[doc = "Write '1' to enable interrupt for event HFCLKSTARTED\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum HFCLKSTARTED_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<HFCLKSTARTED_A> for bool {
+    #[inline(always)]
+    fn from(variant: HFCLKSTARTED_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl HFCLKSTARTED_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> HFCLKSTARTED_A {
+        match self.bits {
+            false => HFCLKSTARTED_A::DISABLED,
+            true => HFCLKSTARTED_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == HFCLKSTARTED_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == HFCLKSTARTED_A::ENABLED
+    }
+}
+#[doc = "Write '1' to enable interrupt for event HFCLKSTARTED\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum HFCLKSTARTED_AW {
+    #[doc = "1: Enable"]
+    SET = 1,
+}
+impl From<HFCLKSTARTED_AW> for bool {
+    #[inline(always)]
+    fn from(variant: HFCLKSTARTED_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `HFCLKSTARTED` writer - Write '1' to enable interrupt for event HFCLKSTARTED"]
+pub type HFCLKSTARTED_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, INTENSET_SPEC, HFCLKSTARTED_AW, O>;
+impl<'a, const O: u8> HFCLKSTARTED_W<'a, O> {
+    #[doc = "Enable"]
+    #[inline(always)]
+    pub fn set(self) -> &'a mut W {
+        self.variant(HFCLKSTARTED_AW::SET)
+    }
+}
+#[doc = "Field `LFCLKSTARTED` reader - Write '1' to enable interrupt for event LFCLKSTARTED"]
+pub type LFCLKSTARTED_R = crate::BitReader<LFCLKSTARTED_A>;
+#[doc = "Write '1' to enable interrupt for event LFCLKSTARTED\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum LFCLKSTARTED_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<LFCLKSTARTED_A> for bool {
+    #[inline(always)]
+    fn from(variant: LFCLKSTARTED_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl LFCLKSTARTED_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> LFCLKSTARTED_A {
+        match self.bits {
+            false => LFCLKSTARTED_A::DISABLED,
+            true => LFCLKSTARTED_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == LFCLKSTARTED_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == LFCLKSTARTED_A::ENABLED
+    }
+}
+#[doc = "Write '1' to enable interrupt for event LFCLKSTARTED\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum LFCLKSTARTED_AW {
+    #[doc = "1: Enable"]
+    SET = 1,
+}
+impl From<LFCLKSTARTED_AW> for bool {
+    #[inline(always)]
+    fn from(variant: LFCLKSTARTED_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `LFCLKSTARTED` writer - Write '1' to enable interrupt for event LFCLKSTARTED"]
+pub type LFCLKSTARTED_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, INTENSET_SPEC, LFCLKSTARTED_AW, O>;
+impl<'a, const O: u8> LFCLKSTARTED_W<'a, O> {
+    #[doc = "Enable"]
+    #[inline(always)]
+    pub fn set(self) -> &'a mut W {
+        self.variant(LFCLKSTARTED_AW::SET)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Write '1' to enable interrupt for event HFCLKSTARTED"]
+    #[inline(always)]
+    pub fn hfclkstarted(&self) -> HFCLKSTARTED_R {
+        HFCLKSTARTED_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Write '1' to enable interrupt for event LFCLKSTARTED"]
+    #[inline(always)]
+    pub fn lfclkstarted(&self) -> LFCLKSTARTED_R {
+        LFCLKSTARTED_R::new(((self.bits >> 1) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Write '1' to enable interrupt for event HFCLKSTARTED"]
+    #[inline(always)]
+    pub fn hfclkstarted(&mut self) -> HFCLKSTARTED_W<0> {
+        HFCLKSTARTED_W::new(self)
+    }
+    #[doc = "Bit 1 - Write '1' to enable interrupt for event LFCLKSTARTED"]
+    #[inline(always)]
+    pub fn lfclkstarted(&mut self) -> LFCLKSTARTED_W<1> {
+        LFCLKSTARTED_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Enable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"]
+pub struct INTENSET_SPEC;
+impl crate::RegisterSpec for INTENSET_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [intenset::R](R) reader structure"]
+impl crate::Readable for INTENSET_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"]
+impl crate::Writable for INTENSET_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets INTENSET to value 0"]
+impl crate::Resettable for INTENSET_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9160-pac/src/clock_ns/intpend.rs

@@ -0,0 +1,115 @@
+#[doc = "Register `INTPEND` reader"]
+pub struct R(crate::R<INTPEND_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<INTPEND_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<INTPEND_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<INTPEND_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `HFCLKSTARTED` reader - Read pending status of interrupt for event HFCLKSTARTED"]
+pub type HFCLKSTARTED_R = crate::BitReader<HFCLKSTARTED_A>;
+#[doc = "Read pending status of interrupt for event HFCLKSTARTED\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum HFCLKSTARTED_A {
+    #[doc = "0: Read: Not pending"]
+    NOT_PENDING = 0,
+    #[doc = "1: Read: Pending"]
+    PENDING = 1,
+}
+impl From<HFCLKSTARTED_A> for bool {
+    #[inline(always)]
+    fn from(variant: HFCLKSTARTED_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl HFCLKSTARTED_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> HFCLKSTARTED_A {
+        match self.bits {
+            false => HFCLKSTARTED_A::NOT_PENDING,
+            true => HFCLKSTARTED_A::PENDING,
+        }
+    }
+    #[doc = "Checks if the value of the field is `NOT_PENDING`"]
+    #[inline(always)]
+    pub fn is_not_pending(&self) -> bool {
+        *self == HFCLKSTARTED_A::NOT_PENDING
+    }
+    #[doc = "Checks if the value of the field is `PENDING`"]
+    #[inline(always)]
+    pub fn is_pending(&self) -> bool {
+        *self == HFCLKSTARTED_A::PENDING
+    }
+}
+#[doc = "Field `LFCLKSTARTED` reader - Read pending status of interrupt for event LFCLKSTARTED"]
+pub type LFCLKSTARTED_R = crate::BitReader<LFCLKSTARTED_A>;
+#[doc = "Read pending status of interrupt for event LFCLKSTARTED\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum LFCLKSTARTED_A {
+    #[doc = "0: Read: Not pending"]
+    NOT_PENDING = 0,
+    #[doc = "1: Read: Pending"]
+    PENDING = 1,
+}
+impl From<LFCLKSTARTED_A> for bool {
+    #[inline(always)]
+    fn from(variant: LFCLKSTARTED_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl LFCLKSTARTED_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> LFCLKSTARTED_A {
+        match self.bits {
+            false => LFCLKSTARTED_A::NOT_PENDING,
+            true => LFCLKSTARTED_A::PENDING,
+        }
+    }
+    #[doc = "Checks if the value of the field is `NOT_PENDING`"]
+    #[inline(always)]
+    pub fn is_not_pending(&self) -> bool {
+        *self == LFCLKSTARTED_A::NOT_PENDING
+    }
+    #[doc = "Checks if the value of the field is `PENDING`"]
+    #[inline(always)]
+    pub fn is_pending(&self) -> bool {
+        *self == LFCLKSTARTED_A::PENDING
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Read pending status of interrupt for event HFCLKSTARTED"]
+    #[inline(always)]
+    pub fn hfclkstarted(&self) -> HFCLKSTARTED_R {
+        HFCLKSTARTED_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Read pending status of interrupt for event LFCLKSTARTED"]
+    #[inline(always)]
+    pub fn lfclkstarted(&self) -> LFCLKSTARTED_R {
+        LFCLKSTARTED_R::new(((self.bits >> 1) & 1) != 0)
+    }
+}
+#[doc = "Pending interrupts\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intpend](index.html) module"]
+pub struct INTPEND_SPEC;
+impl crate::RegisterSpec for INTPEND_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [intpend::R](R) reader structure"]
+impl crate::Readable for INTPEND_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets INTPEND to value 0"]
+impl crate::Resettable for INTPEND_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9160-pac/src/clock_ns/lfclkrun.rs

@@ -0,0 +1,74 @@
+#[doc = "Register `LFCLKRUN` reader"]
+pub struct R(crate::R<LFCLKRUN_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<LFCLKRUN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<LFCLKRUN_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<LFCLKRUN_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `STATUS` reader - LFCLKSTART task triggered or not"]
+pub type STATUS_R = crate::BitReader<STATUS_A>;
+#[doc = "LFCLKSTART task triggered or not\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum STATUS_A {
+    #[doc = "0: Task not triggered"]
+    NOT_TRIGGERED = 0,
+    #[doc = "1: Task triggered"]
+    TRIGGERED = 1,
+}
+impl From<STATUS_A> for bool {
+    #[inline(always)]
+    fn from(variant: STATUS_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl STATUS_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> STATUS_A {
+        match self.bits {
+            false => STATUS_A::NOT_TRIGGERED,
+            true => STATUS_A::TRIGGERED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `NOT_TRIGGERED`"]
+    #[inline(always)]
+    pub fn is_not_triggered(&self) -> bool {
+        *self == STATUS_A::NOT_TRIGGERED
+    }
+    #[doc = "Checks if the value of the field is `TRIGGERED`"]
+    #[inline(always)]
+    pub fn is_triggered(&self) -> bool {
+        *self == STATUS_A::TRIGGERED
+    }
+}
+impl R {
+    #[doc = "Bit 0 - LFCLKSTART task triggered or not"]
+    #[inline(always)]
+    pub fn status(&self) -> STATUS_R {
+        STATUS_R::new((self.bits & 1) != 0)
+    }
+}
+#[doc = "Status indicating that LFCLKSTART task has been triggered\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lfclkrun](index.html) module"]
+pub struct LFCLKRUN_SPEC;
+impl crate::RegisterSpec for LFCLKRUN_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [lfclkrun::R](R) reader structure"]
+impl crate::Readable for LFCLKRUN_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets LFCLKRUN to value 0"]
+impl crate::Resettable for LFCLKRUN_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9160-pac/src/clock_ns/lfclksrc.rs

@@ -0,0 +1,141 @@
+#[doc = "Register `LFCLKSRC` reader"]
+pub struct R(crate::R<LFCLKSRC_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<LFCLKSRC_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<LFCLKSRC_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<LFCLKSRC_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `LFCLKSRC` writer"]
+pub struct W(crate::W<LFCLKSRC_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<LFCLKSRC_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<LFCLKSRC_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<LFCLKSRC_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `SRC` reader - Clock source"]
+pub type SRC_R = crate::FieldReader<u8, SRC_A>;
+#[doc = "Clock source\n\nValue on reset: 1"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum SRC_A {
+    #[doc = "0: Reserved for future use (equals selecting LFRC)"]
+    RFU = 0,
+    #[doc = "1: 32.768 kHz RC oscillator"]
+    LFRC = 1,
+    #[doc = "2: 32.768 kHz crystal oscillator"]
+    LFXO = 2,
+}
+impl From<SRC_A> for u8 {
+    #[inline(always)]
+    fn from(variant: SRC_A) -> Self {
+        variant as _
+    }
+}
+impl SRC_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<SRC_A> {
+        match self.bits {
+            0 => Some(SRC_A::RFU),
+            1 => Some(SRC_A::LFRC),
+            2 => Some(SRC_A::LFXO),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `RFU`"]
+    #[inline(always)]
+    pub fn is_rfu(&self) -> bool {
+        *self == SRC_A::RFU
+    }
+    #[doc = "Checks if the value of the field is `LFRC`"]
+    #[inline(always)]
+    pub fn is_lfrc(&self) -> bool {
+        *self == SRC_A::LFRC
+    }
+    #[doc = "Checks if the value of the field is `LFXO`"]
+    #[inline(always)]
+    pub fn is_lfxo(&self) -> bool {
+        *self == SRC_A::LFXO
+    }
+}
+#[doc = "Field `SRC` writer - Clock source"]
+pub type SRC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, LFCLKSRC_SPEC, u8, SRC_A, 2, O>;
+impl<'a, const O: u8> SRC_W<'a, O> {
+    #[doc = "Reserved for future use (equals selecting LFRC)"]
+    #[inline(always)]
+    pub fn rfu(self) -> &'a mut W {
+        self.variant(SRC_A::RFU)
+    }
+    #[doc = "32.768 kHz RC oscillator"]
+    #[inline(always)]
+    pub fn lfrc(self) -> &'a mut W {
+        self.variant(SRC_A::LFRC)
+    }
+    #[doc = "32.768 kHz crystal oscillator"]
+    #[inline(always)]
+    pub fn lfxo(self) -> &'a mut W {
+        self.variant(SRC_A::LFXO)
+    }
+}
+impl R {
+    #[doc = "Bits 0:1 - Clock source"]
+    #[inline(always)]
+    pub fn src(&self) -> SRC_R {
+        SRC_R::new((self.bits & 3) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:1 - Clock source"]
+    #[inline(always)]
+    pub fn src(&mut self) -> SRC_W<0> {
+        SRC_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Clock source for the LFCLK. LFCLKSTART task starts starts a clock source selected with this register.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lfclksrc](index.html) module"]
+pub struct LFCLKSRC_SPEC;
+impl crate::RegisterSpec for LFCLKSRC_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [lfclksrc::R](R) reader structure"]
+impl crate::Readable for LFCLKSRC_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [lfclksrc::W](W) writer structure"]
+impl crate::Writable for LFCLKSRC_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets LFCLKSRC to value 0x01"]
+impl crate::Resettable for LFCLKSRC_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0x01
+    }
+}

vendor/nrf9160-pac/src/clock_ns/lfclksrccopy.rs

@@ -0,0 +1,84 @@
+#[doc = "Register `LFCLKSRCCOPY` reader"]
+pub struct R(crate::R<LFCLKSRCCOPY_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<LFCLKSRCCOPY_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<LFCLKSRCCOPY_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<LFCLKSRCCOPY_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `SRC` reader - Clock source"]
+pub type SRC_R = crate::FieldReader<u8, SRC_A>;
+#[doc = "Clock source\n\nValue on reset: 1"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum SRC_A {
+    #[doc = "0: Reserved for future use"]
+    RFU = 0,
+    #[doc = "1: 32.768 kHz RC oscillator"]
+    LFRC = 1,
+    #[doc = "2: 32.768 kHz crystal oscillator"]
+    LFXO = 2,
+}
+impl From<SRC_A> for u8 {
+    #[inline(always)]
+    fn from(variant: SRC_A) -> Self {
+        variant as _
+    }
+}
+impl SRC_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<SRC_A> {
+        match self.bits {
+            0 => Some(SRC_A::RFU),
+            1 => Some(SRC_A::LFRC),
+            2 => Some(SRC_A::LFXO),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `RFU`"]
+    #[inline(always)]
+    pub fn is_rfu(&self) -> bool {
+        *self == SRC_A::RFU
+    }
+    #[doc = "Checks if the value of the field is `LFRC`"]
+    #[inline(always)]
+    pub fn is_lfrc(&self) -> bool {
+        *self == SRC_A::LFRC
+    }
+    #[doc = "Checks if the value of the field is `LFXO`"]
+    #[inline(always)]
+    pub fn is_lfxo(&self) -> bool {
+        *self == SRC_A::LFXO
+    }
+}
+impl R {
+    #[doc = "Bits 0:1 - Clock source"]
+    #[inline(always)]
+    pub fn src(&self) -> SRC_R {
+        SRC_R::new((self.bits & 3) as u8)
+    }
+}
+#[doc = "Copy of LFCLKSRC register, set after LFCLKSTART task has been triggered\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lfclksrccopy](index.html) module"]
+pub struct LFCLKSRCCOPY_SPEC;
+impl crate::RegisterSpec for LFCLKSRCCOPY_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [lfclksrccopy::R](R) reader structure"]
+impl crate::Readable for LFCLKSRCCOPY_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets LFCLKSRCCOPY to value 0x01"]
+impl crate::Resettable for LFCLKSRCCOPY_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0x01
+    }
+}

vendor/nrf9160-pac/src/clock_ns/lfclkstat.rs

@@ -0,0 +1,125 @@
+#[doc = "Register `LFCLKSTAT` reader"]
+pub struct R(crate::R<LFCLKSTAT_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<LFCLKSTAT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<LFCLKSTAT_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<LFCLKSTAT_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `SRC` reader - Active clock source"]
+pub type SRC_R = crate::FieldReader<u8, SRC_A>;
+#[doc = "Active clock source\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum SRC_A {
+    #[doc = "0: Reserved for future use"]
+    RFU = 0,
+    #[doc = "1: 32.768 kHz RC oscillator"]
+    LFRC = 1,
+    #[doc = "2: 32.768 kHz crystal oscillator"]
+    LFXO = 2,
+}
+impl From<SRC_A> for u8 {
+    #[inline(always)]
+    fn from(variant: SRC_A) -> Self {
+        variant as _
+    }
+}
+impl SRC_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<SRC_A> {
+        match self.bits {
+            0 => Some(SRC_A::RFU),
+            1 => Some(SRC_A::LFRC),
+            2 => Some(SRC_A::LFXO),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `RFU`"]
+    #[inline(always)]
+    pub fn is_rfu(&self) -> bool {
+        *self == SRC_A::RFU
+    }
+    #[doc = "Checks if the value of the field is `LFRC`"]
+    #[inline(always)]
+    pub fn is_lfrc(&self) -> bool {
+        *self == SRC_A::LFRC
+    }
+    #[doc = "Checks if the value of the field is `LFXO`"]
+    #[inline(always)]
+    pub fn is_lfxo(&self) -> bool {
+        *self == SRC_A::LFXO
+    }
+}
+#[doc = "Field `STATE` reader - LFCLK state"]
+pub type STATE_R = crate::BitReader<STATE_A>;
+#[doc = "LFCLK state\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum STATE_A {
+    #[doc = "0: Requested LFCLK source has not been started or LFCLKSTOP task has been triggered"]
+    NOT_RUNNING = 0,
+    #[doc = "1: Requested LFCLK source has been started (LFCLKSTARTED event has been generated)"]
+    RUNNING = 1,
+}
+impl From<STATE_A> for bool {
+    #[inline(always)]
+    fn from(variant: STATE_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl STATE_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> STATE_A {
+        match self.bits {
+            false => STATE_A::NOT_RUNNING,
+            true => STATE_A::RUNNING,
+        }
+    }
+    #[doc = "Checks if the value of the field is `NOT_RUNNING`"]
+    #[inline(always)]
+    pub fn is_not_running(&self) -> bool {
+        *self == STATE_A::NOT_RUNNING
+    }
+    #[doc = "Checks if the value of the field is `RUNNING`"]
+    #[inline(always)]
+    pub fn is_running(&self) -> bool {
+        *self == STATE_A::RUNNING
+    }
+}
+impl R {
+    #[doc = "Bits 0:1 - Active clock source"]
+    #[inline(always)]
+    pub fn src(&self) -> SRC_R {
+        SRC_R::new((self.bits & 3) as u8)
+    }
+    #[doc = "Bit 16 - LFCLK state"]
+    #[inline(always)]
+    pub fn state(&self) -> STATE_R {
+        STATE_R::new(((self.bits >> 16) & 1) != 0)
+    }
+}
+#[doc = "The register shows which LFCLK source has been requested (SRC) when triggering LFCLKSTART task and if the source has been started (STATE)\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lfclkstat](index.html) module"]
+pub struct LFCLKSTAT_SPEC;
+impl crate::RegisterSpec for LFCLKSTAT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [lfclkstat::R](R) reader structure"]
+impl crate::Readable for LFCLKSTAT_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets LFCLKSTAT to value 0"]
+impl crate::Resettable for LFCLKSTAT_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9160-pac/src/clock_ns/publish_hfclkstarted.rs

@@ -0,0 +1,141 @@
+#[doc = "Register `PUBLISH_HFCLKSTARTED` reader"]
+pub struct R(crate::R<PUBLISH_HFCLKSTARTED_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<PUBLISH_HFCLKSTARTED_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<PUBLISH_HFCLKSTARTED_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<PUBLISH_HFCLKSTARTED_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `PUBLISH_HFCLKSTARTED` writer"]
+pub struct W(crate::W<PUBLISH_HFCLKSTARTED_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<PUBLISH_HFCLKSTARTED_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<PUBLISH_HFCLKSTARTED_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<PUBLISH_HFCLKSTARTED_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `CHIDX` reader - Channel that event HFCLKSTARTED will publish to."]
+pub type CHIDX_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `CHIDX` writer - Channel that event HFCLKSTARTED will publish to."]
+pub type CHIDX_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u32, PUBLISH_HFCLKSTARTED_SPEC, u8, u8, 4, O>;
+#[doc = "Field `EN` reader - "]
+pub type EN_R = crate::BitReader<EN_A>;
+#[doc = "\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum EN_A {
+    #[doc = "0: Disable publishing"]
+    DISABLED = 0,
+    #[doc = "1: Enable publishing"]
+    ENABLED = 1,
+}
+impl From<EN_A> for bool {
+    #[inline(always)]
+    fn from(variant: EN_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl EN_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> EN_A {
+        match self.bits {
+            false => EN_A::DISABLED,
+            true => EN_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == EN_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == EN_A::ENABLED
+    }
+}
+#[doc = "Field `EN` writer - "]
+pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_HFCLKSTARTED_SPEC, EN_A, O>;
+impl<'a, const O: u8> EN_W<'a, O> {
+    #[doc = "Disable publishing"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(EN_A::DISABLED)
+    }
+    #[doc = "Enable publishing"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(EN_A::ENABLED)
+    }
+}
+impl R {
+    #[doc = "Bits 0:3 - Channel that event HFCLKSTARTED will publish to."]
+    #[inline(always)]
+    pub fn chidx(&self) -> CHIDX_R {
+        CHIDX_R::new((self.bits & 0x0f) as u8)
+    }
+    #[doc = "Bit 31"]
+    #[inline(always)]
+    pub fn en(&self) -> EN_R {
+        EN_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:3 - Channel that event HFCLKSTARTED will publish to."]
+    #[inline(always)]
+    pub fn chidx(&mut self) -> CHIDX_W<0> {
+        CHIDX_W::new(self)
+    }
+    #[doc = "Bit 31"]
+    #[inline(always)]
+    pub fn en(&mut self) -> EN_W<31> {
+        EN_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Publish configuration for event HFCLKSTARTED\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_hfclkstarted](index.html) module"]
+pub struct PUBLISH_HFCLKSTARTED_SPEC;
+impl crate::RegisterSpec for PUBLISH_HFCLKSTARTED_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [publish_hfclkstarted::R](R) reader structure"]
+impl crate::Readable for PUBLISH_HFCLKSTARTED_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [publish_hfclkstarted::W](W) writer structure"]
+impl crate::Writable for PUBLISH_HFCLKSTARTED_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets PUBLISH_HFCLKSTARTED to value 0"]
+impl crate::Resettable for PUBLISH_HFCLKSTARTED_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9160-pac/src/clock_ns/publish_lfclkstarted.rs

@@ -0,0 +1,141 @@
+#[doc = "Register `PUBLISH_LFCLKSTARTED` reader"]
+pub struct R(crate::R<PUBLISH_LFCLKSTARTED_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<PUBLISH_LFCLKSTARTED_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<PUBLISH_LFCLKSTARTED_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<PUBLISH_LFCLKSTARTED_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `PUBLISH_LFCLKSTARTED` writer"]
+pub struct W(crate::W<PUBLISH_LFCLKSTARTED_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<PUBLISH_LFCLKSTARTED_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<PUBLISH_LFCLKSTARTED_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<PUBLISH_LFCLKSTARTED_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `CHIDX` reader - Channel that event LFCLKSTARTED will publish to."]
+pub type CHIDX_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `CHIDX` writer - Channel that event LFCLKSTARTED will publish to."]
+pub type CHIDX_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u32, PUBLISH_LFCLKSTARTED_SPEC, u8, u8, 4, O>;
+#[doc = "Field `EN` reader - "]
+pub type EN_R = crate::BitReader<EN_A>;
+#[doc = "\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum EN_A {
+    #[doc = "0: Disable publishing"]
+    DISABLED = 0,
+    #[doc = "1: Enable publishing"]
+    ENABLED = 1,
+}
+impl From<EN_A> for bool {
+    #[inline(always)]
+    fn from(variant: EN_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl EN_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> EN_A {
+        match self.bits {
+            false => EN_A::DISABLED,
+            true => EN_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == EN_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == EN_A::ENABLED
+    }
+}
+#[doc = "Field `EN` writer - "]
+pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_LFCLKSTARTED_SPEC, EN_A, O>;
+impl<'a, const O: u8> EN_W<'a, O> {
+    #[doc = "Disable publishing"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(EN_A::DISABLED)
+    }
+    #[doc = "Enable publishing"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(EN_A::ENABLED)
+    }
+}
+impl R {
+    #[doc = "Bits 0:3 - Channel that event LFCLKSTARTED will publish to."]
+    #[inline(always)]
+    pub fn chidx(&self) -> CHIDX_R {
+        CHIDX_R::new((self.bits & 0x0f) as u8)
+    }
+    #[doc = "Bit 31"]
+    #[inline(always)]
+    pub fn en(&self) -> EN_R {
+        EN_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:3 - Channel that event LFCLKSTARTED will publish to."]
+    #[inline(always)]
+    pub fn chidx(&mut self) -> CHIDX_W<0> {
+        CHIDX_W::new(self)
+    }
+    #[doc = "Bit 31"]
+    #[inline(always)]
+    pub fn en(&mut self) -> EN_W<31> {
+        EN_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Publish configuration for event LFCLKSTARTED\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_lfclkstarted](index.html) module"]
+pub struct PUBLISH_LFCLKSTARTED_SPEC;
+impl crate::RegisterSpec for PUBLISH_LFCLKSTARTED_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [publish_lfclkstarted::R](R) reader structure"]
+impl crate::Readable for PUBLISH_LFCLKSTARTED_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [publish_lfclkstarted::W](W) writer structure"]
+impl crate::Writable for PUBLISH_LFCLKSTARTED_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets PUBLISH_LFCLKSTARTED to value 0"]
+impl crate::Resettable for PUBLISH_LFCLKSTARTED_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9160-pac/src/clock_ns/subscribe_hfclkstart.rs

@@ -0,0 +1,141 @@
+#[doc = "Register `SUBSCRIBE_HFCLKSTART` reader"]
+pub struct R(crate::R<SUBSCRIBE_HFCLKSTART_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<SUBSCRIBE_HFCLKSTART_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<SUBSCRIBE_HFCLKSTART_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<SUBSCRIBE_HFCLKSTART_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `SUBSCRIBE_HFCLKSTART` writer"]
+pub struct W(crate::W<SUBSCRIBE_HFCLKSTART_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<SUBSCRIBE_HFCLKSTART_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<SUBSCRIBE_HFCLKSTART_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<SUBSCRIBE_HFCLKSTART_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `CHIDX` reader - Channel that task HFCLKSTART will subscribe to"]
+pub type CHIDX_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `CHIDX` writer - Channel that task HFCLKSTART will subscribe to"]
+pub type CHIDX_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u32, SUBSCRIBE_HFCLKSTART_SPEC, u8, u8, 4, O>;
+#[doc = "Field `EN` reader - "]
+pub type EN_R = crate::BitReader<EN_A>;
+#[doc = "\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum EN_A {
+    #[doc = "0: Disable subscription"]
+    DISABLED = 0,
+    #[doc = "1: Enable subscription"]
+    ENABLED = 1,
+}
+impl From<EN_A> for bool {
+    #[inline(always)]
+    fn from(variant: EN_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl EN_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> EN_A {
+        match self.bits {
+            false => EN_A::DISABLED,
+            true => EN_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == EN_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == EN_A::ENABLED
+    }
+}
+#[doc = "Field `EN` writer - "]
+pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_HFCLKSTART_SPEC, EN_A, O>;
+impl<'a, const O: u8> EN_W<'a, O> {
+    #[doc = "Disable subscription"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(EN_A::DISABLED)
+    }
+    #[doc = "Enable subscription"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(EN_A::ENABLED)
+    }
+}
+impl R {
+    #[doc = "Bits 0:3 - Channel that task HFCLKSTART will subscribe to"]
+    #[inline(always)]
+    pub fn chidx(&self) -> CHIDX_R {
+        CHIDX_R::new((self.bits & 0x0f) as u8)
+    }
+    #[doc = "Bit 31"]
+    #[inline(always)]
+    pub fn en(&self) -> EN_R {
+        EN_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:3 - Channel that task HFCLKSTART will subscribe to"]
+    #[inline(always)]
+    pub fn chidx(&mut self) -> CHIDX_W<0> {
+        CHIDX_W::new(self)
+    }
+    #[doc = "Bit 31"]
+    #[inline(always)]
+    pub fn en(&mut self) -> EN_W<31> {
+        EN_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Subscribe configuration for task HFCLKSTART\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_hfclkstart](index.html) module"]
+pub struct SUBSCRIBE_HFCLKSTART_SPEC;
+impl crate::RegisterSpec for SUBSCRIBE_HFCLKSTART_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [subscribe_hfclkstart::R](R) reader structure"]
+impl crate::Readable for SUBSCRIBE_HFCLKSTART_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [subscribe_hfclkstart::W](W) writer structure"]
+impl crate::Writable for SUBSCRIBE_HFCLKSTART_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets SUBSCRIBE_HFCLKSTART to value 0"]
+impl crate::Resettable for SUBSCRIBE_HFCLKSTART_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9160-pac/src/clock_ns/subscribe_hfclkstop.rs

@@ -0,0 +1,141 @@
+#[doc = "Register `SUBSCRIBE_HFCLKSTOP` reader"]
+pub struct R(crate::R<SUBSCRIBE_HFCLKSTOP_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<SUBSCRIBE_HFCLKSTOP_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<SUBSCRIBE_HFCLKSTOP_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<SUBSCRIBE_HFCLKSTOP_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `SUBSCRIBE_HFCLKSTOP` writer"]
+pub struct W(crate::W<SUBSCRIBE_HFCLKSTOP_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<SUBSCRIBE_HFCLKSTOP_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<SUBSCRIBE_HFCLKSTOP_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<SUBSCRIBE_HFCLKSTOP_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `CHIDX` reader - Channel that task HFCLKSTOP will subscribe to"]
+pub type CHIDX_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `CHIDX` writer - Channel that task HFCLKSTOP will subscribe to"]
+pub type CHIDX_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u32, SUBSCRIBE_HFCLKSTOP_SPEC, u8, u8, 4, O>;
+#[doc = "Field `EN` reader - "]
+pub type EN_R = crate::BitReader<EN_A>;
+#[doc = "\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum EN_A {
+    #[doc = "0: Disable subscription"]
+    DISABLED = 0,
+    #[doc = "1: Enable subscription"]
+    ENABLED = 1,
+}
+impl From<EN_A> for bool {
+    #[inline(always)]
+    fn from(variant: EN_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl EN_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> EN_A {
+        match self.bits {
+            false => EN_A::DISABLED,
+            true => EN_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == EN_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == EN_A::ENABLED
+    }
+}
+#[doc = "Field `EN` writer - "]
+pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_HFCLKSTOP_SPEC, EN_A, O>;
+impl<'a, const O: u8> EN_W<'a, O> {
+    #[doc = "Disable subscription"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(EN_A::DISABLED)
+    }
+    #[doc = "Enable subscription"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(EN_A::ENABLED)
+    }
+}
+impl R {
+    #[doc = "Bits 0:3 - Channel that task HFCLKSTOP will subscribe to"]
+    #[inline(always)]
+    pub fn chidx(&self) -> CHIDX_R {
+        CHIDX_R::new((self.bits & 0x0f) as u8)
+    }
+    #[doc = "Bit 31"]
+    #[inline(always)]
+    pub fn en(&self) -> EN_R {
+        EN_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:3 - Channel that task HFCLKSTOP will subscribe to"]
+    #[inline(always)]
+    pub fn chidx(&mut self) -> CHIDX_W<0> {
+        CHIDX_W::new(self)
+    }
+    #[doc = "Bit 31"]
+    #[inline(always)]
+    pub fn en(&mut self) -> EN_W<31> {
+        EN_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Subscribe configuration for task HFCLKSTOP\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_hfclkstop](index.html) module"]
+pub struct SUBSCRIBE_HFCLKSTOP_SPEC;
+impl crate::RegisterSpec for SUBSCRIBE_HFCLKSTOP_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [subscribe_hfclkstop::R](R) reader structure"]
+impl crate::Readable for SUBSCRIBE_HFCLKSTOP_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [subscribe_hfclkstop::W](W) writer structure"]
+impl crate::Writable for SUBSCRIBE_HFCLKSTOP_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets SUBSCRIBE_HFCLKSTOP to value 0"]
+impl crate::Resettable for SUBSCRIBE_HFCLKSTOP_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9160-pac/src/clock_ns/subscribe_lfclkstart.rs

@@ -0,0 +1,141 @@
+#[doc = "Register `SUBSCRIBE_LFCLKSTART` reader"]
+pub struct R(crate::R<SUBSCRIBE_LFCLKSTART_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<SUBSCRIBE_LFCLKSTART_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<SUBSCRIBE_LFCLKSTART_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<SUBSCRIBE_LFCLKSTART_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `SUBSCRIBE_LFCLKSTART` writer"]
+pub struct W(crate::W<SUBSCRIBE_LFCLKSTART_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<SUBSCRIBE_LFCLKSTART_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<SUBSCRIBE_LFCLKSTART_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<SUBSCRIBE_LFCLKSTART_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `CHIDX` reader - Channel that task LFCLKSTART will subscribe to"]
+pub type CHIDX_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `CHIDX` writer - Channel that task LFCLKSTART will subscribe to"]
+pub type CHIDX_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u32, SUBSCRIBE_LFCLKSTART_SPEC, u8, u8, 4, O>;
+#[doc = "Field `EN` reader - "]
+pub type EN_R = crate::BitReader<EN_A>;
+#[doc = "\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum EN_A {
+    #[doc = "0: Disable subscription"]
+    DISABLED = 0,
+    #[doc = "1: Enable subscription"]
+    ENABLED = 1,
+}
+impl From<EN_A> for bool {
+    #[inline(always)]
+    fn from(variant: EN_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl EN_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> EN_A {
+        match self.bits {
+            false => EN_A::DISABLED,
+            true => EN_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == EN_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == EN_A::ENABLED
+    }
+}
+#[doc = "Field `EN` writer - "]
+pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_LFCLKSTART_SPEC, EN_A, O>;
+impl<'a, const O: u8> EN_W<'a, O> {
+    #[doc = "Disable subscription"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(EN_A::DISABLED)
+    }
+    #[doc = "Enable subscription"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(EN_A::ENABLED)
+    }
+}
+impl R {
+    #[doc = "Bits 0:3 - Channel that task LFCLKSTART will subscribe to"]
+    #[inline(always)]
+    pub fn chidx(&self) -> CHIDX_R {
+        CHIDX_R::new((self.bits & 0x0f) as u8)
+    }
+    #[doc = "Bit 31"]
+    #[inline(always)]
+    pub fn en(&self) -> EN_R {
+        EN_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:3 - Channel that task LFCLKSTART will subscribe to"]
+    #[inline(always)]
+    pub fn chidx(&mut self) -> CHIDX_W<0> {
+        CHIDX_W::new(self)
+    }
+    #[doc = "Bit 31"]
+    #[inline(always)]
+    pub fn en(&mut self) -> EN_W<31> {
+        EN_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Subscribe configuration for task LFCLKSTART\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_lfclkstart](index.html) module"]
+pub struct SUBSCRIBE_LFCLKSTART_SPEC;
+impl crate::RegisterSpec for SUBSCRIBE_LFCLKSTART_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [subscribe_lfclkstart::R](R) reader structure"]
+impl crate::Readable for SUBSCRIBE_LFCLKSTART_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [subscribe_lfclkstart::W](W) writer structure"]
+impl crate::Writable for SUBSCRIBE_LFCLKSTART_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets SUBSCRIBE_LFCLKSTART to value 0"]
+impl crate::Resettable for SUBSCRIBE_LFCLKSTART_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9160-pac/src/clock_ns/subscribe_lfclkstop.rs

@@ -0,0 +1,141 @@
+#[doc = "Register `SUBSCRIBE_LFCLKSTOP` reader"]
+pub struct R(crate::R<SUBSCRIBE_LFCLKSTOP_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<SUBSCRIBE_LFCLKSTOP_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<SUBSCRIBE_LFCLKSTOP_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<SUBSCRIBE_LFCLKSTOP_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `SUBSCRIBE_LFCLKSTOP` writer"]
+pub struct W(crate::W<SUBSCRIBE_LFCLKSTOP_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<SUBSCRIBE_LFCLKSTOP_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<SUBSCRIBE_LFCLKSTOP_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<SUBSCRIBE_LFCLKSTOP_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `CHIDX` reader - Channel that task LFCLKSTOP will subscribe to"]
+pub type CHIDX_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `CHIDX` writer - Channel that task LFCLKSTOP will subscribe to"]
+pub type CHIDX_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u32, SUBSCRIBE_LFCLKSTOP_SPEC, u8, u8, 4, O>;
+#[doc = "Field `EN` reader - "]
+pub type EN_R = crate::BitReader<EN_A>;
+#[doc = "\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum EN_A {
+    #[doc = "0: Disable subscription"]
+    DISABLED = 0,
+    #[doc = "1: Enable subscription"]
+    ENABLED = 1,
+}
+impl From<EN_A> for bool {
+    #[inline(always)]
+    fn from(variant: EN_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl EN_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> EN_A {
+        match self.bits {
+            false => EN_A::DISABLED,
+            true => EN_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == EN_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == EN_A::ENABLED
+    }
+}
+#[doc = "Field `EN` writer - "]
+pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_LFCLKSTOP_SPEC, EN_A, O>;
+impl<'a, const O: u8> EN_W<'a, O> {
+    #[doc = "Disable subscription"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(EN_A::DISABLED)
+    }
+    #[doc = "Enable subscription"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(EN_A::ENABLED)
+    }
+}
+impl R {
+    #[doc = "Bits 0:3 - Channel that task LFCLKSTOP will subscribe to"]
+    #[inline(always)]
+    pub fn chidx(&self) -> CHIDX_R {
+        CHIDX_R::new((self.bits & 0x0f) as u8)
+    }
+    #[doc = "Bit 31"]
+    #[inline(always)]
+    pub fn en(&self) -> EN_R {
+        EN_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:3 - Channel that task LFCLKSTOP will subscribe to"]
+    #[inline(always)]
+    pub fn chidx(&mut self) -> CHIDX_W<0> {
+        CHIDX_W::new(self)
+    }
+    #[doc = "Bit 31"]
+    #[inline(always)]
+    pub fn en(&mut self) -> EN_W<31> {
+        EN_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Subscribe configuration for task LFCLKSTOP\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_lfclkstop](index.html) module"]
+pub struct SUBSCRIBE_LFCLKSTOP_SPEC;
+impl crate::RegisterSpec for SUBSCRIBE_LFCLKSTOP_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [subscribe_lfclkstop::R](R) reader structure"]
+impl crate::Readable for SUBSCRIBE_LFCLKSTOP_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [subscribe_lfclkstop::W](W) writer structure"]
+impl crate::Writable for SUBSCRIBE_LFCLKSTOP_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets SUBSCRIBE_LFCLKSTOP to value 0"]
+impl crate::Resettable for SUBSCRIBE_LFCLKSTOP_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9160-pac/src/clock_ns/tasks_hfclkstart.rs

@@ -0,0 +1,72 @@
+#[doc = "Register `TASKS_HFCLKSTART` writer"]
+pub struct W(crate::W<TASKS_HFCLKSTART_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<TASKS_HFCLKSTART_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<TASKS_HFCLKSTART_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<TASKS_HFCLKSTART_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Start HFCLK source\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TASKS_HFCLKSTART_AW {
+    #[doc = "1: Trigger task"]
+    TRIGGER = 1,
+}
+impl From<TASKS_HFCLKSTART_AW> for bool {
+    #[inline(always)]
+    fn from(variant: TASKS_HFCLKSTART_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `TASKS_HFCLKSTART` writer - Start HFCLK source"]
+pub type TASKS_HFCLKSTART_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, TASKS_HFCLKSTART_SPEC, TASKS_HFCLKSTART_AW, O>;
+impl<'a, const O: u8> TASKS_HFCLKSTART_W<'a, O> {
+    #[doc = "Trigger task"]
+    #[inline(always)]
+    pub fn trigger(self) -> &'a mut W {
+        self.variant(TASKS_HFCLKSTART_AW::TRIGGER)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Start HFCLK source"]
+    #[inline(always)]
+    pub fn tasks_hfclkstart(&mut self) -> TASKS_HFCLKSTART_W<0> {
+        TASKS_HFCLKSTART_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Start HFCLK source\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_hfclkstart](index.html) module"]
+pub struct TASKS_HFCLKSTART_SPEC;
+impl crate::RegisterSpec for TASKS_HFCLKSTART_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [tasks_hfclkstart::W](W) writer structure"]
+impl crate::Writable for TASKS_HFCLKSTART_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets TASKS_HFCLKSTART to value 0"]
+impl crate::Resettable for TASKS_HFCLKSTART_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9160-pac/src/clock_ns/tasks_hfclkstop.rs

@@ -0,0 +1,72 @@
+#[doc = "Register `TASKS_HFCLKSTOP` writer"]
+pub struct W(crate::W<TASKS_HFCLKSTOP_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<TASKS_HFCLKSTOP_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<TASKS_HFCLKSTOP_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<TASKS_HFCLKSTOP_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Stop HFCLK source\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TASKS_HFCLKSTOP_AW {
+    #[doc = "1: Trigger task"]
+    TRIGGER = 1,
+}
+impl From<TASKS_HFCLKSTOP_AW> for bool {
+    #[inline(always)]
+    fn from(variant: TASKS_HFCLKSTOP_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `TASKS_HFCLKSTOP` writer - Stop HFCLK source"]
+pub type TASKS_HFCLKSTOP_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, TASKS_HFCLKSTOP_SPEC, TASKS_HFCLKSTOP_AW, O>;
+impl<'a, const O: u8> TASKS_HFCLKSTOP_W<'a, O> {
+    #[doc = "Trigger task"]
+    #[inline(always)]
+    pub fn trigger(self) -> &'a mut W {
+        self.variant(TASKS_HFCLKSTOP_AW::TRIGGER)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Stop HFCLK source"]
+    #[inline(always)]
+    pub fn tasks_hfclkstop(&mut self) -> TASKS_HFCLKSTOP_W<0> {
+        TASKS_HFCLKSTOP_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Stop HFCLK source\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_hfclkstop](index.html) module"]
+pub struct TASKS_HFCLKSTOP_SPEC;
+impl crate::RegisterSpec for TASKS_HFCLKSTOP_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [tasks_hfclkstop::W](W) writer structure"]
+impl crate::Writable for TASKS_HFCLKSTOP_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets TASKS_HFCLKSTOP to value 0"]
+impl crate::Resettable for TASKS_HFCLKSTOP_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9160-pac/src/clock_ns/tasks_lfclkstart.rs

@@ -0,0 +1,72 @@
+#[doc = "Register `TASKS_LFCLKSTART` writer"]
+pub struct W(crate::W<TASKS_LFCLKSTART_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<TASKS_LFCLKSTART_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<TASKS_LFCLKSTART_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<TASKS_LFCLKSTART_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Start LFCLK source\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TASKS_LFCLKSTART_AW {
+    #[doc = "1: Trigger task"]
+    TRIGGER = 1,
+}
+impl From<TASKS_LFCLKSTART_AW> for bool {
+    #[inline(always)]
+    fn from(variant: TASKS_LFCLKSTART_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `TASKS_LFCLKSTART` writer - Start LFCLK source"]
+pub type TASKS_LFCLKSTART_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, TASKS_LFCLKSTART_SPEC, TASKS_LFCLKSTART_AW, O>;
+impl<'a, const O: u8> TASKS_LFCLKSTART_W<'a, O> {
+    #[doc = "Trigger task"]
+    #[inline(always)]
+    pub fn trigger(self) -> &'a mut W {
+        self.variant(TASKS_LFCLKSTART_AW::TRIGGER)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Start LFCLK source"]
+    #[inline(always)]
+    pub fn tasks_lfclkstart(&mut self) -> TASKS_LFCLKSTART_W<0> {
+        TASKS_LFCLKSTART_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Start LFCLK source\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_lfclkstart](index.html) module"]
+pub struct TASKS_LFCLKSTART_SPEC;
+impl crate::RegisterSpec for TASKS_LFCLKSTART_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [tasks_lfclkstart::W](W) writer structure"]
+impl crate::Writable for TASKS_LFCLKSTART_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets TASKS_LFCLKSTART to value 0"]
+impl crate::Resettable for TASKS_LFCLKSTART_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9160-pac/src/clock_ns/tasks_lfclkstop.rs

@@ -0,0 +1,72 @@
+#[doc = "Register `TASKS_LFCLKSTOP` writer"]
+pub struct W(crate::W<TASKS_LFCLKSTOP_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<TASKS_LFCLKSTOP_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<TASKS_LFCLKSTOP_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<TASKS_LFCLKSTOP_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Stop LFCLK source\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TASKS_LFCLKSTOP_AW {
+    #[doc = "1: Trigger task"]
+    TRIGGER = 1,
+}
+impl From<TASKS_LFCLKSTOP_AW> for bool {
+    #[inline(always)]
+    fn from(variant: TASKS_LFCLKSTOP_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `TASKS_LFCLKSTOP` writer - Stop LFCLK source"]
+pub type TASKS_LFCLKSTOP_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, TASKS_LFCLKSTOP_SPEC, TASKS_LFCLKSTOP_AW, O>;
+impl<'a, const O: u8> TASKS_LFCLKSTOP_W<'a, O> {
+    #[doc = "Trigger task"]
+    #[inline(always)]
+    pub fn trigger(self) -> &'a mut W {
+        self.variant(TASKS_LFCLKSTOP_AW::TRIGGER)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Stop LFCLK source"]
+    #[inline(always)]
+    pub fn tasks_lfclkstop(&mut self) -> TASKS_LFCLKSTOP_W<0> {
+        TASKS_LFCLKSTOP_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Stop LFCLK source\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_lfclkstop](index.html) module"]
+pub struct TASKS_LFCLKSTOP_SPEC;
+impl crate::RegisterSpec for TASKS_LFCLKSTOP_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [tasks_lfclkstop::W](W) writer structure"]
+impl crate::Writable for TASKS_LFCLKSTOP_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets TASKS_LFCLKSTOP to value 0"]
+impl crate::Resettable for TASKS_LFCLKSTOP_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9160-pac/src/cryptocell_s.rs

@@ -0,0 +1,11 @@
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    _reserved0: [u8; 0x0500],
+    #[doc = "0x500 - Enable CRYPTOCELL subsystem"]
+    pub enable: ENABLE,
+}
+#[doc = "ENABLE (rw) register accessor: an alias for `Reg<ENABLE_SPEC>`"]
+pub type ENABLE = crate::Reg<enable::ENABLE_SPEC>;
+#[doc = "Enable CRYPTOCELL subsystem"]
+pub mod enable;

vendor/nrf9160-pac/src/cryptocell_s/enable.rs

@@ -0,0 +1,126 @@
+#[doc = "Register `ENABLE` reader"]
+pub struct R(crate::R<ENABLE_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<ENABLE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<ENABLE_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<ENABLE_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `ENABLE` writer"]
+pub struct W(crate::W<ENABLE_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<ENABLE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<ENABLE_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<ENABLE_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `ENABLE` reader - Enable or disable the CRYPTOCELL subsystem"]
+pub type ENABLE_R = crate::BitReader<ENABLE_A>;
+#[doc = "Enable or disable the CRYPTOCELL subsystem\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ENABLE_A {
+    #[doc = "0: CRYPTOCELL subsystem disabled"]
+    DISABLED = 0,
+    #[doc = "1: CRYPTOCELL subsystem enabled."]
+    ENABLED = 1,
+}
+impl From<ENABLE_A> for bool {
+    #[inline(always)]
+    fn from(variant: ENABLE_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl ENABLE_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> ENABLE_A {
+        match self.bits {
+            false => ENABLE_A::DISABLED,
+            true => ENABLE_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == ENABLE_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == ENABLE_A::ENABLED
+    }
+}
+#[doc = "Field `ENABLE` writer - Enable or disable the CRYPTOCELL subsystem"]
+pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, ENABLE_SPEC, ENABLE_A, O>;
+impl<'a, const O: u8> ENABLE_W<'a, O> {
+    #[doc = "CRYPTOCELL subsystem disabled"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(ENABLE_A::DISABLED)
+    }
+    #[doc = "CRYPTOCELL subsystem enabled."]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(ENABLE_A::ENABLED)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Enable or disable the CRYPTOCELL subsystem"]
+    #[inline(always)]
+    pub fn enable(&self) -> ENABLE_R {
+        ENABLE_R::new((self.bits & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Enable or disable the CRYPTOCELL subsystem"]
+    #[inline(always)]
+    pub fn enable(&mut self) -> ENABLE_W<0> {
+        ENABLE_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Enable CRYPTOCELL subsystem\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [enable](index.html) module"]
+pub struct ENABLE_SPEC;
+impl crate::RegisterSpec for ENABLE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [enable::R](R) reader structure"]
+impl crate::Readable for ENABLE_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [enable::W](W) writer structure"]
+impl crate::Writable for ENABLE_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets ENABLE to value 0"]
+impl crate::Resettable for ENABLE_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9160-pac/src/ctrl_ap_peri_s.rs

@@ -0,0 +1,20 @@
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    _reserved0: [u8; 0x0400],
+    #[doc = "0x400..0x488 - Unspecified"]
+    pub mailbox: MAILBOX,
+    _reserved1: [u8; 0x78],
+    #[doc = "0x500..0x508 - Unspecified"]
+    pub eraseprotect: ERASEPROTECT,
+}
+#[doc = "Unspecified"]
+pub use mailbox::MAILBOX;
+#[doc = r"Cluster"]
+#[doc = "Unspecified"]
+pub mod mailbox;
+#[doc = "Unspecified"]
+pub use eraseprotect::ERASEPROTECT;
+#[doc = r"Cluster"]
+#[doc = "Unspecified"]
+pub mod eraseprotect;

vendor/nrf9160-pac/src/ctrl_ap_peri_s/eraseprotect.rs

@@ -0,0 +1,16 @@
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct ERASEPROTECT {
+    #[doc = "0x00 - Lock register ERASEPROTECT.DISABLE from being written until next reset"]
+    pub lock: LOCK,
+    #[doc = "0x04 - Disable ERASEPROTECT and perform ERASEALL"]
+    pub disable: DISABLE,
+}
+#[doc = "LOCK (rw) register accessor: an alias for `Reg<LOCK_SPEC>`"]
+pub type LOCK = crate::Reg<lock::LOCK_SPEC>;
+#[doc = "Lock register ERASEPROTECT.DISABLE from being written until next reset"]
+pub mod lock;
+#[doc = "DISABLE (rw) register accessor: an alias for `Reg<DISABLE_SPEC>`"]
+pub type DISABLE = crate::Reg<disable::DISABLE_SPEC>;
+#[doc = "Disable ERASEPROTECT and perform ERASEALL"]
+pub mod disable;

vendor/nrf9160-pac/src/ctrl_ap_peri_s/eraseprotect/disable.rs

@@ -0,0 +1,80 @@
+#[doc = "Register `DISABLE` reader"]
+pub struct R(crate::R<DISABLE_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<DISABLE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<DISABLE_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<DISABLE_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `DISABLE` writer"]
+pub struct W(crate::W<DISABLE_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<DISABLE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<DISABLE_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<DISABLE_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `KEY` reader - The ERASEALL sequence will be initiated if value of KEY fields are non-zero and KEY fields match on both CPU and debugger side"]
+pub type KEY_R = crate::FieldReader<u32, u32>;
+#[doc = "Field `KEY` writer - The ERASEALL sequence will be initiated if value of KEY fields are non-zero and KEY fields match on both CPU and debugger side"]
+pub type KEY_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DISABLE_SPEC, u32, u32, 32, O>;
+impl R {
+    #[doc = "Bits 0:31 - The ERASEALL sequence will be initiated if value of KEY fields are non-zero and KEY fields match on both CPU and debugger side"]
+    #[inline(always)]
+    pub fn key(&self) -> KEY_R {
+        KEY_R::new(self.bits)
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - The ERASEALL sequence will be initiated if value of KEY fields are non-zero and KEY fields match on both CPU and debugger side"]
+    #[inline(always)]
+    pub fn key(&mut self) -> KEY_W<0> {
+        KEY_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Disable ERASEPROTECT and perform ERASEALL\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [disable](index.html) module"]
+pub struct DISABLE_SPEC;
+impl crate::RegisterSpec for DISABLE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [disable::R](R) reader structure"]
+impl crate::Readable for DISABLE_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [disable::W](W) writer structure"]
+impl crate::Writable for DISABLE_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets DISABLE to value 0"]
+impl crate::Resettable for DISABLE_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9160-pac/src/ctrl_ap_peri_s/eraseprotect/lock.rs

@@ -0,0 +1,126 @@
+#[doc = "Register `LOCK` reader"]
+pub struct R(crate::R<LOCK_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<LOCK_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<LOCK_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<LOCK_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `LOCK` writer"]
+pub struct W(crate::W<LOCK_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<LOCK_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<LOCK_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<LOCK_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `LOCK` reader - Lock register ERASEPROTECT.DISABLE from being written until next reset"]
+pub type LOCK_R = crate::BitReader<LOCK_A>;
+#[doc = "Lock register ERASEPROTECT.DISABLE from being written until next reset\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum LOCK_A {
+    #[doc = "0: Register ERASEPROTECT.DISABLE is writeable"]
+    UNLOCKED = 0,
+    #[doc = "1: Register ERASEPROTECT.DISABLE is read-only"]
+    LOCKED = 1,
+}
+impl From<LOCK_A> for bool {
+    #[inline(always)]
+    fn from(variant: LOCK_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl LOCK_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> LOCK_A {
+        match self.bits {
+            false => LOCK_A::UNLOCKED,
+            true => LOCK_A::LOCKED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `UNLOCKED`"]
+    #[inline(always)]
+    pub fn is_unlocked(&self) -> bool {
+        *self == LOCK_A::UNLOCKED
+    }
+    #[doc = "Checks if the value of the field is `LOCKED`"]
+    #[inline(always)]
+    pub fn is_locked(&self) -> bool {
+        *self == LOCK_A::LOCKED
+    }
+}
+#[doc = "Field `LOCK` writer - Lock register ERASEPROTECT.DISABLE from being written until next reset"]
+pub type LOCK_W<'a, const O: u8> = crate::BitWriter<'a, u32, LOCK_SPEC, LOCK_A, O>;
+impl<'a, const O: u8> LOCK_W<'a, O> {
+    #[doc = "Register ERASEPROTECT.DISABLE is writeable"]
+    #[inline(always)]
+    pub fn unlocked(self) -> &'a mut W {
+        self.variant(LOCK_A::UNLOCKED)
+    }
+    #[doc = "Register ERASEPROTECT.DISABLE is read-only"]
+    #[inline(always)]
+    pub fn locked(self) -> &'a mut W {
+        self.variant(LOCK_A::LOCKED)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Lock register ERASEPROTECT.DISABLE from being written until next reset"]
+    #[inline(always)]
+    pub fn lock(&self) -> LOCK_R {
+        LOCK_R::new((self.bits & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Lock register ERASEPROTECT.DISABLE from being written until next reset"]
+    #[inline(always)]
+    pub fn lock(&mut self) -> LOCK_W<0> {
+        LOCK_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Lock register ERASEPROTECT.DISABLE from being written until next reset\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lock](index.html) module"]
+pub struct LOCK_SPEC;
+impl crate::RegisterSpec for LOCK_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [lock::R](R) reader structure"]
+impl crate::Readable for LOCK_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [lock::W](W) writer structure"]
+impl crate::Writable for LOCK_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets LOCK to value 0"]
+impl crate::Resettable for LOCK_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9160-pac/src/ctrl_ap_peri_s/mailbox.rs

@@ -0,0 +1,29 @@
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct MAILBOX {
+    #[doc = "0x00 - Data sent from the debugger to the CPU"]
+    pub rxdata: RXDATA,
+    #[doc = "0x04 - Status to indicate if data sent from the debugger to the CPU has been read"]
+    pub rxstatus: RXSTATUS,
+    _reserved2: [u8; 0x78],
+    #[doc = "0x80 - Data sent from the CPU to the debugger"]
+    pub txdata: TXDATA,
+    #[doc = "0x84 - Status to indicate if data sent from the CPU to the debugger has been read"]
+    pub txstatus: TXSTATUS,
+}
+#[doc = "RXDATA (r) register accessor: an alias for `Reg<RXDATA_SPEC>`"]
+pub type RXDATA = crate::Reg<rxdata::RXDATA_SPEC>;
+#[doc = "Data sent from the debugger to the CPU"]
+pub mod rxdata;
+#[doc = "RXSTATUS (r) register accessor: an alias for `Reg<RXSTATUS_SPEC>`"]
+pub type RXSTATUS = crate::Reg<rxstatus::RXSTATUS_SPEC>;
+#[doc = "Status to indicate if data sent from the debugger to the CPU has been read"]
+pub mod rxstatus;
+#[doc = "TXDATA (rw) register accessor: an alias for `Reg<TXDATA_SPEC>`"]
+pub type TXDATA = crate::Reg<txdata::TXDATA_SPEC>;
+#[doc = "Data sent from the CPU to the debugger"]
+pub mod txdata;
+#[doc = "TXSTATUS (r) register accessor: an alias for `Reg<TXSTATUS_SPEC>`"]
+pub type TXSTATUS = crate::Reg<txstatus::TXSTATUS_SPEC>;
+#[doc = "Status to indicate if data sent from the CPU to the debugger has been read"]
+pub mod txstatus;

vendor/nrf9160-pac/src/ctrl_ap_peri_s/mailbox/rxdata.rs

@@ -0,0 +1,40 @@
+#[doc = "Register `RXDATA` reader"]
+pub struct R(crate::R<RXDATA_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<RXDATA_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<RXDATA_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<RXDATA_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `RXDATA` reader - Data received from debugger"]
+pub type RXDATA_R = crate::FieldReader<u32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - Data received from debugger"]
+    #[inline(always)]
+    pub fn rxdata(&self) -> RXDATA_R {
+        RXDATA_R::new(self.bits)
+    }
+}
+#[doc = "Data sent from the debugger to the CPU\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxdata](index.html) module"]
+pub struct RXDATA_SPEC;
+impl crate::RegisterSpec for RXDATA_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [rxdata::R](R) reader structure"]
+impl crate::Readable for RXDATA_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets RXDATA to value 0"]
+impl crate::Resettable for RXDATA_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9160-pac/src/ctrl_ap_peri_s/mailbox/rxstatus.rs

@@ -0,0 +1,74 @@
+#[doc = "Register `RXSTATUS` reader"]
+pub struct R(crate::R<RXSTATUS_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<RXSTATUS_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<RXSTATUS_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<RXSTATUS_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `RXSTATUS` reader - Status of data in register RXDATA"]
+pub type RXSTATUS_R = crate::BitReader<RXSTATUS_A>;
+#[doc = "Status of data in register RXDATA\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum RXSTATUS_A {
+    #[doc = "0: No data pending in register RXDATA"]
+    NO_DATA_PENDING = 0,
+    #[doc = "1: Data pending in register RXDATA"]
+    DATA_PENDING = 1,
+}
+impl From<RXSTATUS_A> for bool {
+    #[inline(always)]
+    fn from(variant: RXSTATUS_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl RXSTATUS_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> RXSTATUS_A {
+        match self.bits {
+            false => RXSTATUS_A::NO_DATA_PENDING,
+            true => RXSTATUS_A::DATA_PENDING,
+        }
+    }
+    #[doc = "Checks if the value of the field is `NO_DATA_PENDING`"]
+    #[inline(always)]
+    pub fn is_no_data_pending(&self) -> bool {
+        *self == RXSTATUS_A::NO_DATA_PENDING
+    }
+    #[doc = "Checks if the value of the field is `DATA_PENDING`"]
+    #[inline(always)]
+    pub fn is_data_pending(&self) -> bool {
+        *self == RXSTATUS_A::DATA_PENDING
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Status of data in register RXDATA"]
+    #[inline(always)]
+    pub fn rxstatus(&self) -> RXSTATUS_R {
+        RXSTATUS_R::new((self.bits & 1) != 0)
+    }
+}
+#[doc = "Status to indicate if data sent from the debugger to the CPU has been read\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxstatus](index.html) module"]
+pub struct RXSTATUS_SPEC;
+impl crate::RegisterSpec for RXSTATUS_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [rxstatus::R](R) reader structure"]
+impl crate::Readable for RXSTATUS_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets RXSTATUS to value 0"]
+impl crate::Resettable for RXSTATUS_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9160-pac/src/ctrl_ap_peri_s/mailbox/txdata.rs

@@ -0,0 +1,80 @@
+#[doc = "Register `TXDATA` reader"]
+pub struct R(crate::R<TXDATA_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<TXDATA_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<TXDATA_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<TXDATA_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `TXDATA` writer"]
+pub struct W(crate::W<TXDATA_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<TXDATA_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<TXDATA_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<TXDATA_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `TXDATA` reader - Data sent to debugger"]
+pub type TXDATA_R = crate::FieldReader<u32, u32>;
+#[doc = "Field `TXDATA` writer - Data sent to debugger"]
+pub type TXDATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, TXDATA_SPEC, u32, u32, 32, O>;
+impl R {
+    #[doc = "Bits 0:31 - Data sent to debugger"]
+    #[inline(always)]
+    pub fn txdata(&self) -> TXDATA_R {
+        TXDATA_R::new(self.bits)
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Data sent to debugger"]
+    #[inline(always)]
+    pub fn txdata(&mut self) -> TXDATA_W<0> {
+        TXDATA_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Data sent from the CPU to the debugger\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txdata](index.html) module"]
+pub struct TXDATA_SPEC;
+impl crate::RegisterSpec for TXDATA_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [txdata::R](R) reader structure"]
+impl crate::Readable for TXDATA_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [txdata::W](W) writer structure"]
+impl crate::Writable for TXDATA_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets TXDATA to value 0"]
+impl crate::Resettable for TXDATA_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9160-pac/src/ctrl_ap_peri_s/mailbox/txstatus.rs

@@ -0,0 +1,74 @@
+#[doc = "Register `TXSTATUS` reader"]
+pub struct R(crate::R<TXSTATUS_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<TXSTATUS_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<TXSTATUS_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<TXSTATUS_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `TXSTATUS` reader - Status of data in register TXDATA"]
+pub type TXSTATUS_R = crate::BitReader<TXSTATUS_A>;
+#[doc = "Status of data in register TXDATA\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TXSTATUS_A {
+    #[doc = "0: No data pending in register TXDATA"]
+    NO_DATA_PENDING = 0,
+    #[doc = "1: Data pending in register TXDATA"]
+    DATA_PENDING = 1,
+}
+impl From<TXSTATUS_A> for bool {
+    #[inline(always)]
+    fn from(variant: TXSTATUS_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl TXSTATUS_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> TXSTATUS_A {
+        match self.bits {
+            false => TXSTATUS_A::NO_DATA_PENDING,
+            true => TXSTATUS_A::DATA_PENDING,
+        }
+    }
+    #[doc = "Checks if the value of the field is `NO_DATA_PENDING`"]
+    #[inline(always)]
+    pub fn is_no_data_pending(&self) -> bool {
+        *self == TXSTATUS_A::NO_DATA_PENDING
+    }
+    #[doc = "Checks if the value of the field is `DATA_PENDING`"]
+    #[inline(always)]
+    pub fn is_data_pending(&self) -> bool {
+        *self == TXSTATUS_A::DATA_PENDING
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Status of data in register TXDATA"]
+    #[inline(always)]
+    pub fn txstatus(&self) -> TXSTATUS_R {
+        TXSTATUS_R::new((self.bits & 1) != 0)
+    }
+}
+#[doc = "Status to indicate if data sent from the CPU to the debugger has been read\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txstatus](index.html) module"]
+pub struct TXSTATUS_SPEC;
+impl crate::RegisterSpec for TXSTATUS_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [txstatus::R](R) reader structure"]
+impl crate::Readable for TXSTATUS_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets TXSTATUS to value 0"]
+impl crate::Resettable for TXSTATUS_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9160-pac/src/dppic_ns.rs

@@ -0,0 +1,45 @@
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00..0x30 - Channel group tasks"]
+    pub tasks_chg: [TASKS_CHG; 6],
+    _reserved1: [u8; 0x50],
+    #[doc = "0x80..0xb0 - Subscribe configuration for tasks"]
+    pub subscribe_chg: [SUBSCRIBE_CHG; 6],
+    _reserved2: [u8; 0x0450],
+    #[doc = "0x500 - Channel enable register"]
+    pub chen: CHEN,
+    #[doc = "0x504 - Channel enable set register"]
+    pub chenset: CHENSET,
+    #[doc = "0x508 - Channel enable clear register"]
+    pub chenclr: CHENCLR,
+    _reserved5: [u8; 0x02f4],
+    #[doc = "0x800..0x818 - Description collection: Channel group n Note: Writes to this register is ignored if either SUBSCRIBE_CHG\\[n\\].EN/DIS are enabled."]
+    pub chg: [CHG; 6],
+}
+#[doc = "Channel group tasks"]
+pub use tasks_chg::TASKS_CHG;
+#[doc = r"Cluster"]
+#[doc = "Channel group tasks"]
+pub mod tasks_chg;
+#[doc = "Subscribe configuration for tasks"]
+pub use subscribe_chg::SUBSCRIBE_CHG;
+#[doc = r"Cluster"]
+#[doc = "Subscribe configuration for tasks"]
+pub mod subscribe_chg;
+#[doc = "CHEN (rw) register accessor: an alias for `Reg<CHEN_SPEC>`"]
+pub type CHEN = crate::Reg<chen::CHEN_SPEC>;
+#[doc = "Channel enable register"]
+pub mod chen;
+#[doc = "CHENSET (rw) register accessor: an alias for `Reg<CHENSET_SPEC>`"]
+pub type CHENSET = crate::Reg<chenset::CHENSET_SPEC>;
+#[doc = "Channel enable set register"]
+pub mod chenset;
+#[doc = "CHENCLR (rw) register accessor: an alias for `Reg<CHENCLR_SPEC>`"]
+pub type CHENCLR = crate::Reg<chenclr::CHENCLR_SPEC>;
+#[doc = "Channel enable clear register"]
+pub mod chenclr;
+#[doc = "CHG (rw) register accessor: an alias for `Reg<CHG_SPEC>`"]
+pub type CHG = crate::Reg<chg::CHG_SPEC>;
+#[doc = "Description collection: Channel group n Note: Writes to this register is ignored if either SUBSCRIBE_CHG\\[n\\].EN/DIS are enabled."]
+pub mod chg;

vendor/nrf9160-pac/src/dppic_ns/subscribe_chg.rs

@@ -0,0 +1,16 @@
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct SUBSCRIBE_CHG {
+    #[doc = "0x00 - Description cluster: Subscribe configuration for task CHG\\[n\\].EN"]
+    pub en: EN,
+    #[doc = "0x04 - Description cluster: Subscribe configuration for task CHG\\[n\\].DIS"]
+    pub dis: DIS,
+}
+#[doc = "EN (rw) register accessor: an alias for `Reg<EN_SPEC>`"]
+pub type EN = crate::Reg<en::EN_SPEC>;
+#[doc = "Description cluster: Subscribe configuration for task CHG\\[n\\].EN"]
+pub mod en;
+#[doc = "DIS (rw) register accessor: an alias for `Reg<DIS_SPEC>`"]
+pub type DIS = crate::Reg<dis::DIS_SPEC>;
+#[doc = "Description cluster: Subscribe configuration for task CHG\\[n\\].DIS"]
+pub mod dis;

vendor/nrf9160-pac/src/dppic_ns/subscribe_chg/dis.rs

@@ -0,0 +1,140 @@
+#[doc = "Register `DIS` reader"]
+pub struct R(crate::R<DIS_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<DIS_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<DIS_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<DIS_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `DIS` writer"]
+pub struct W(crate::W<DIS_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<DIS_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<DIS_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<DIS_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `CHIDX` reader - Channel that task CHG\\[n\\].DIS will subscribe to"]
+pub type CHIDX_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `CHIDX` writer - Channel that task CHG\\[n\\].DIS will subscribe to"]
+pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIS_SPEC, u8, u8, 4, O>;
+#[doc = "Field `EN` reader - "]
+pub type EN_R = crate::BitReader<EN_A>;
+#[doc = "\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum EN_A {
+    #[doc = "0: Disable subscription"]
+    DISABLED = 0,
+    #[doc = "1: Enable subscription"]
+    ENABLED = 1,
+}
+impl From<EN_A> for bool {
+    #[inline(always)]
+    fn from(variant: EN_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl EN_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> EN_A {
+        match self.bits {
+            false => EN_A::DISABLED,
+            true => EN_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == EN_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == EN_A::ENABLED
+    }
+}
+#[doc = "Field `EN` writer - "]
+pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIS_SPEC, EN_A, O>;
+impl<'a, const O: u8> EN_W<'a, O> {
+    #[doc = "Disable subscription"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(EN_A::DISABLED)
+    }
+    #[doc = "Enable subscription"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(EN_A::ENABLED)
+    }
+}
+impl R {
+    #[doc = "Bits 0:3 - Channel that task CHG\\[n\\].DIS will subscribe to"]
+    #[inline(always)]
+    pub fn chidx(&self) -> CHIDX_R {
+        CHIDX_R::new((self.bits & 0x0f) as u8)
+    }
+    #[doc = "Bit 31"]
+    #[inline(always)]
+    pub fn en(&self) -> EN_R {
+        EN_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:3 - Channel that task CHG\\[n\\].DIS will subscribe to"]
+    #[inline(always)]
+    pub fn chidx(&mut self) -> CHIDX_W<0> {
+        CHIDX_W::new(self)
+    }
+    #[doc = "Bit 31"]
+    #[inline(always)]
+    pub fn en(&mut self) -> EN_W<31> {
+        EN_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Description cluster: Subscribe configuration for task CHG\\[n\\].DIS\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dis](index.html) module"]
+pub struct DIS_SPEC;
+impl crate::RegisterSpec for DIS_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [dis::R](R) reader structure"]
+impl crate::Readable for DIS_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [dis::W](W) writer structure"]
+impl crate::Writable for DIS_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets DIS to value 0"]
+impl crate::Resettable for DIS_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9160-pac/src/dppic_ns/subscribe_chg/en.rs

@@ -0,0 +1,140 @@
+#[doc = "Register `EN` reader"]
+pub struct R(crate::R<EN_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<EN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<EN_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<EN_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `EN` writer"]
+pub struct W(crate::W<EN_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<EN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<EN_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<EN_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `CHIDX` reader - Channel that task CHG\\[n\\].EN will subscribe to"]
+pub type CHIDX_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `CHIDX` writer - Channel that task CHG\\[n\\].EN will subscribe to"]
+pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, EN_SPEC, u8, u8, 4, O>;
+#[doc = "Field `EN` reader - "]
+pub type EN_R = crate::BitReader<EN_A>;
+#[doc = "\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum EN_A {
+    #[doc = "0: Disable subscription"]
+    DISABLED = 0,
+    #[doc = "1: Enable subscription"]
+    ENABLED = 1,
+}
+impl From<EN_A> for bool {
+    #[inline(always)]
+    fn from(variant: EN_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl EN_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> EN_A {
+        match self.bits {
+            false => EN_A::DISABLED,
+            true => EN_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == EN_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == EN_A::ENABLED
+    }
+}
+#[doc = "Field `EN` writer - "]
+pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, EN_SPEC, EN_A, O>;
+impl<'a, const O: u8> EN_W<'a, O> {
+    #[doc = "Disable subscription"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(EN_A::DISABLED)
+    }
+    #[doc = "Enable subscription"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(EN_A::ENABLED)
+    }
+}
+impl R {
+    #[doc = "Bits 0:3 - Channel that task CHG\\[n\\].EN will subscribe to"]
+    #[inline(always)]
+    pub fn chidx(&self) -> CHIDX_R {
+        CHIDX_R::new((self.bits & 0x0f) as u8)
+    }
+    #[doc = "Bit 31"]
+    #[inline(always)]
+    pub fn en(&self) -> EN_R {
+        EN_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:3 - Channel that task CHG\\[n\\].EN will subscribe to"]
+    #[inline(always)]
+    pub fn chidx(&mut self) -> CHIDX_W<0> {
+        CHIDX_W::new(self)
+    }
+    #[doc = "Bit 31"]
+    #[inline(always)]
+    pub fn en(&mut self) -> EN_W<31> {
+        EN_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Description cluster: Subscribe configuration for task CHG\\[n\\].EN\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [en](index.html) module"]
+pub struct EN_SPEC;
+impl crate::RegisterSpec for EN_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [en::R](R) reader structure"]
+impl crate::Readable for EN_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [en::W](W) writer structure"]
+impl crate::Writable for EN_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets EN to value 0"]
+impl crate::Resettable for EN_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9160-pac/src/dppic_ns/tasks_chg.rs

@@ -0,0 +1,16 @@
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct TASKS_CHG {
+    #[doc = "0x00 - Description cluster: Enable channel group n"]
+    pub en: EN,
+    #[doc = "0x04 - Description cluster: Disable channel group n"]
+    pub dis: DIS,
+}
+#[doc = "EN (w) register accessor: an alias for `Reg<EN_SPEC>`"]
+pub type EN = crate::Reg<en::EN_SPEC>;
+#[doc = "Description cluster: Enable channel group n"]
+pub mod en;
+#[doc = "DIS (w) register accessor: an alias for `Reg<DIS_SPEC>`"]
+pub type DIS = crate::Reg<dis::DIS_SPEC>;
+#[doc = "Description cluster: Disable channel group n"]
+pub mod dis;

vendor/nrf9160-pac/src/dppic_ns/tasks_chg/dis.rs

@@ -0,0 +1,71 @@
+#[doc = "Register `DIS` writer"]
+pub struct W(crate::W<DIS_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<DIS_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<DIS_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<DIS_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Disable channel group n\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DIS_AW {
+    #[doc = "1: Trigger task"]
+    TRIGGER = 1,
+}
+impl From<DIS_AW> for bool {
+    #[inline(always)]
+    fn from(variant: DIS_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `DIS` writer - Disable channel group n"]
+pub type DIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIS_SPEC, DIS_AW, O>;
+impl<'a, const O: u8> DIS_W<'a, O> {
+    #[doc = "Trigger task"]
+    #[inline(always)]
+    pub fn trigger(self) -> &'a mut W {
+        self.variant(DIS_AW::TRIGGER)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Disable channel group n"]
+    #[inline(always)]
+    pub fn dis(&mut self) -> DIS_W<0> {
+        DIS_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Description cluster: Disable channel group n\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dis](index.html) module"]
+pub struct DIS_SPEC;
+impl crate::RegisterSpec for DIS_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [dis::W](W) writer structure"]
+impl crate::Writable for DIS_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets DIS to value 0"]
+impl crate::Resettable for DIS_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9160-pac/src/dppic_ns/tasks_chg/en.rs

@@ -0,0 +1,71 @@
+#[doc = "Register `EN` writer"]
+pub struct W(crate::W<EN_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<EN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<EN_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<EN_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Enable channel group n\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum EN_AW {
+    #[doc = "1: Trigger task"]
+    TRIGGER = 1,
+}
+impl From<EN_AW> for bool {
+    #[inline(always)]
+    fn from(variant: EN_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `EN` writer - Enable channel group n"]
+pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, EN_SPEC, EN_AW, O>;
+impl<'a, const O: u8> EN_W<'a, O> {
+    #[doc = "Trigger task"]
+    #[inline(always)]
+    pub fn trigger(self) -> &'a mut W {
+        self.variant(EN_AW::TRIGGER)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Enable channel group n"]
+    #[inline(always)]
+    pub fn en(&mut self) -> EN_W<0> {
+        EN_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Description cluster: Enable channel group n\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [en](index.html) module"]
+pub struct EN_SPEC;
+impl crate::RegisterSpec for EN_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [en::W](W) writer structure"]
+impl crate::Writable for EN_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets EN to value 0"]
+impl crate::Resettable for EN_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9160-pac/src/egu0_ns.rs

@@ -0,0 +1,54 @@
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00..0x40 - Description collection: Trigger n for triggering the corresponding TRIGGERED\\[n\\]
+event"]
+    pub tasks_trigger: [TASKS_TRIGGER; 16],
+    _reserved1: [u8; 0x40],
+    #[doc = "0x80..0xc0 - Description collection: Subscribe configuration for task TRIGGER\\[n\\]"]
+    pub subscribe_trigger: [SUBSCRIBE_TRIGGER; 16],
+    _reserved2: [u8; 0x40],
+    #[doc = "0x100..0x140 - Description collection: Event number n generated by triggering the corresponding TRIGGER\\[n\\]
+task"]
+    pub events_triggered: [EVENTS_TRIGGERED; 16],
+    _reserved3: [u8; 0x40],
+    #[doc = "0x180..0x1c0 - Description collection: Publish configuration for event TRIGGERED\\[n\\]"]
+    pub publish_triggered: [PUBLISH_TRIGGERED; 16],
+    _reserved4: [u8; 0x0140],
+    #[doc = "0x300 - Enable or disable interrupt"]
+    pub inten: INTEN,
+    #[doc = "0x304 - Enable interrupt"]
+    pub intenset: INTENSET,
+    #[doc = "0x308 - Disable interrupt"]
+    pub intenclr: INTENCLR,
+}
+#[doc = "TASKS_TRIGGER (w) register accessor: an alias for `Reg<TASKS_TRIGGER_SPEC>`"]
+pub type TASKS_TRIGGER = crate::Reg<tasks_trigger::TASKS_TRIGGER_SPEC>;
+#[doc = "Description collection: Trigger n for triggering the corresponding TRIGGERED\\[n\\]
+event"]
+pub mod tasks_trigger;
+#[doc = "SUBSCRIBE_TRIGGER (rw) register accessor: an alias for `Reg<SUBSCRIBE_TRIGGER_SPEC>`"]
+pub type SUBSCRIBE_TRIGGER = crate::Reg<subscribe_trigger::SUBSCRIBE_TRIGGER_SPEC>;
+#[doc = "Description collection: Subscribe configuration for task TRIGGER\\[n\\]"]
+pub mod subscribe_trigger;
+#[doc = "EVENTS_TRIGGERED (rw) register accessor: an alias for `Reg<EVENTS_TRIGGERED_SPEC>`"]
+pub type EVENTS_TRIGGERED = crate::Reg<events_triggered::EVENTS_TRIGGERED_SPEC>;
+#[doc = "Description collection: Event number n generated by triggering the corresponding TRIGGER\\[n\\]
+task"]
+pub mod events_triggered;
+#[doc = "PUBLISH_TRIGGERED (rw) register accessor: an alias for `Reg<PUBLISH_TRIGGERED_SPEC>`"]
+pub type PUBLISH_TRIGGERED = crate::Reg<publish_triggered::PUBLISH_TRIGGERED_SPEC>;
+#[doc = "Description collection: Publish configuration for event TRIGGERED\\[n\\]"]
+pub mod publish_triggered;
+#[doc = "INTEN (rw) register accessor: an alias for `Reg<INTEN_SPEC>`"]
+pub type INTEN = crate::Reg<inten::INTEN_SPEC>;
+#[doc = "Enable or disable interrupt"]
+pub mod inten;
+#[doc = "INTENSET (rw) register accessor: an alias for `Reg<INTENSET_SPEC>`"]
+pub type INTENSET = crate::Reg<intenset::INTENSET_SPEC>;
+#[doc = "Enable interrupt"]
+pub mod intenset;
+#[doc = "INTENCLR (rw) register accessor: an alias for `Reg<INTENCLR_SPEC>`"]
+pub type INTENCLR = crate::Reg<intenclr::INTENCLR_SPEC>;
+#[doc = "Disable interrupt"]
+pub mod intenclr;

vendor/nrf9160-pac/src/egu0_ns/events_triggered.rs

@@ -0,0 +1,134 @@
+#[doc = "Register `EVENTS_TRIGGERED[%s]` reader"]
+pub struct R(crate::R<EVENTS_TRIGGERED_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<EVENTS_TRIGGERED_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<EVENTS_TRIGGERED_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<EVENTS_TRIGGERED_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `EVENTS_TRIGGERED[%s]` writer"]
+pub struct W(crate::W<EVENTS_TRIGGERED_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<EVENTS_TRIGGERED_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<EVENTS_TRIGGERED_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<EVENTS_TRIGGERED_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `EVENTS_TRIGGERED` reader - Event number n generated by triggering the corresponding TRIGGER\\[n\\]
+task"]
+pub type EVENTS_TRIGGERED_R = crate::BitReader<EVENTS_TRIGGERED_A>;
+#[doc = "Event number n generated by triggering the corresponding TRIGGER\\[n\\]
+task\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum EVENTS_TRIGGERED_A {
+    #[doc = "0: Event not generated"]
+    NOT_GENERATED = 0,
+    #[doc = "1: Event generated"]
+    GENERATED = 1,
+}
+impl From<EVENTS_TRIGGERED_A> for bool {
+    #[inline(always)]
+    fn from(variant: EVENTS_TRIGGERED_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl EVENTS_TRIGGERED_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> EVENTS_TRIGGERED_A {
+        match self.bits {
+            false => EVENTS_TRIGGERED_A::NOT_GENERATED,
+            true => EVENTS_TRIGGERED_A::GENERATED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `NOT_GENERATED`"]
+    #[inline(always)]
+    pub fn is_not_generated(&self) -> bool {
+        *self == EVENTS_TRIGGERED_A::NOT_GENERATED
+    }
+    #[doc = "Checks if the value of the field is `GENERATED`"]
+    #[inline(always)]
+    pub fn is_generated(&self) -> bool {
+        *self == EVENTS_TRIGGERED_A::GENERATED
+    }
+}
+#[doc = "Field `EVENTS_TRIGGERED` writer - Event number n generated by triggering the corresponding TRIGGER\\[n\\]
+task"]
+pub type EVENTS_TRIGGERED_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, EVENTS_TRIGGERED_SPEC, EVENTS_TRIGGERED_A, O>;
+impl<'a, const O: u8> EVENTS_TRIGGERED_W<'a, O> {
+    #[doc = "Event not generated"]
+    #[inline(always)]
+    pub fn not_generated(self) -> &'a mut W {
+        self.variant(EVENTS_TRIGGERED_A::NOT_GENERATED)
+    }
+    #[doc = "Event generated"]
+    #[inline(always)]
+    pub fn generated(self) -> &'a mut W {
+        self.variant(EVENTS_TRIGGERED_A::GENERATED)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Event number n generated by triggering the corresponding TRIGGER\\[n\\]
+task"]
+    #[inline(always)]
+    pub fn events_triggered(&self) -> EVENTS_TRIGGERED_R {
+        EVENTS_TRIGGERED_R::new((self.bits & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Event number n generated by triggering the corresponding TRIGGER\\[n\\]
+task"]
+    #[inline(always)]
+    pub fn events_triggered(&mut self) -> EVENTS_TRIGGERED_W<0> {
+        EVENTS_TRIGGERED_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Description collection: Event number n generated by triggering the corresponding TRIGGER\\[n\\]
+task\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_triggered](index.html) module"]
+pub struct EVENTS_TRIGGERED_SPEC;
+impl crate::RegisterSpec for EVENTS_TRIGGERED_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [events_triggered::R](R) reader structure"]
+impl crate::Readable for EVENTS_TRIGGERED_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [events_triggered::W](W) writer structure"]
+impl crate::Writable for EVENTS_TRIGGERED_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets EVENTS_TRIGGERED[%s]
+to value 0"]
+impl crate::Resettable for EVENTS_TRIGGERED_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9160-pac/src/egu0_ns/publish_triggered.rs

@@ -0,0 +1,146 @@
+#[doc = "Register `PUBLISH_TRIGGERED[%s]` reader"]
+pub struct R(crate::R<PUBLISH_TRIGGERED_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<PUBLISH_TRIGGERED_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<PUBLISH_TRIGGERED_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<PUBLISH_TRIGGERED_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `PUBLISH_TRIGGERED[%s]` writer"]
+pub struct W(crate::W<PUBLISH_TRIGGERED_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<PUBLISH_TRIGGERED_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<PUBLISH_TRIGGERED_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<PUBLISH_TRIGGERED_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `CHIDX` reader - Channel that event TRIGGERED\\[n\\]
+will publish to."]
+pub type CHIDX_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `CHIDX` writer - Channel that event TRIGGERED\\[n\\]
+will publish to."]
+pub type CHIDX_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u32, PUBLISH_TRIGGERED_SPEC, u8, u8, 4, O>;
+#[doc = "Field `EN` reader - "]
+pub type EN_R = crate::BitReader<EN_A>;
+#[doc = "\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum EN_A {
+    #[doc = "0: Disable publishing"]
+    DISABLED = 0,
+    #[doc = "1: Enable publishing"]
+    ENABLED = 1,
+}
+impl From<EN_A> for bool {
+    #[inline(always)]
+    fn from(variant: EN_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl EN_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> EN_A {
+        match self.bits {
+            false => EN_A::DISABLED,
+            true => EN_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == EN_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == EN_A::ENABLED
+    }
+}
+#[doc = "Field `EN` writer - "]
+pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_TRIGGERED_SPEC, EN_A, O>;
+impl<'a, const O: u8> EN_W<'a, O> {
+    #[doc = "Disable publishing"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(EN_A::DISABLED)
+    }
+    #[doc = "Enable publishing"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(EN_A::ENABLED)
+    }
+}
+impl R {
+    #[doc = "Bits 0:3 - Channel that event TRIGGERED\\[n\\]
+will publish to."]
+    #[inline(always)]
+    pub fn chidx(&self) -> CHIDX_R {
+        CHIDX_R::new((self.bits & 0x0f) as u8)
+    }
+    #[doc = "Bit 31"]
+    #[inline(always)]
+    pub fn en(&self) -> EN_R {
+        EN_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:3 - Channel that event TRIGGERED\\[n\\]
+will publish to."]
+    #[inline(always)]
+    pub fn chidx(&mut self) -> CHIDX_W<0> {
+        CHIDX_W::new(self)
+    }
+    #[doc = "Bit 31"]
+    #[inline(always)]
+    pub fn en(&mut self) -> EN_W<31> {
+        EN_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Description collection: Publish configuration for event TRIGGERED\\[n\\]\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_triggered](index.html) module"]
+pub struct PUBLISH_TRIGGERED_SPEC;
+impl crate::RegisterSpec for PUBLISH_TRIGGERED_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [publish_triggered::R](R) reader structure"]
+impl crate::Readable for PUBLISH_TRIGGERED_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [publish_triggered::W](W) writer structure"]
+impl crate::Writable for PUBLISH_TRIGGERED_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets PUBLISH_TRIGGERED[%s]
+to value 0"]
+impl crate::Resettable for PUBLISH_TRIGGERED_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9160-pac/src/egu0_ns/subscribe_trigger.rs

@@ -0,0 +1,146 @@
+#[doc = "Register `SUBSCRIBE_TRIGGER[%s]` reader"]
+pub struct R(crate::R<SUBSCRIBE_TRIGGER_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<SUBSCRIBE_TRIGGER_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<SUBSCRIBE_TRIGGER_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<SUBSCRIBE_TRIGGER_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `SUBSCRIBE_TRIGGER[%s]` writer"]
+pub struct W(crate::W<SUBSCRIBE_TRIGGER_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<SUBSCRIBE_TRIGGER_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<SUBSCRIBE_TRIGGER_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<SUBSCRIBE_TRIGGER_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `CHIDX` reader - Channel that task TRIGGER\\[n\\]
+will subscribe to"]
+pub type CHIDX_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `CHIDX` writer - Channel that task TRIGGER\\[n\\]
+will subscribe to"]
+pub type CHIDX_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u32, SUBSCRIBE_TRIGGER_SPEC, u8, u8, 4, O>;
+#[doc = "Field `EN` reader - "]
+pub type EN_R = crate::BitReader<EN_A>;
+#[doc = "\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum EN_A {
+    #[doc = "0: Disable subscription"]
+    DISABLED = 0,
+    #[doc = "1: Enable subscription"]
+    ENABLED = 1,
+}
+impl From<EN_A> for bool {
+    #[inline(always)]
+    fn from(variant: EN_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl EN_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> EN_A {
+        match self.bits {
+            false => EN_A::DISABLED,
+            true => EN_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == EN_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == EN_A::ENABLED
+    }
+}
+#[doc = "Field `EN` writer - "]
+pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_TRIGGER_SPEC, EN_A, O>;
+impl<'a, const O: u8> EN_W<'a, O> {
+    #[doc = "Disable subscription"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(EN_A::DISABLED)
+    }
+    #[doc = "Enable subscription"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(EN_A::ENABLED)
+    }
+}
+impl R {
+    #[doc = "Bits 0:3 - Channel that task TRIGGER\\[n\\]
+will subscribe to"]
+    #[inline(always)]
+    pub fn chidx(&self) -> CHIDX_R {
+        CHIDX_R::new((self.bits & 0x0f) as u8)
+    }
+    #[doc = "Bit 31"]
+    #[inline(always)]
+    pub fn en(&self) -> EN_R {
+        EN_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:3 - Channel that task TRIGGER\\[n\\]
+will subscribe to"]
+    #[inline(always)]
+    pub fn chidx(&mut self) -> CHIDX_W<0> {
+        CHIDX_W::new(self)
+    }
+    #[doc = "Bit 31"]
+    #[inline(always)]
+    pub fn en(&mut self) -> EN_W<31> {
+        EN_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Description collection: Subscribe configuration for task TRIGGER\\[n\\]\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_trigger](index.html) module"]
+pub struct SUBSCRIBE_TRIGGER_SPEC;
+impl crate::RegisterSpec for SUBSCRIBE_TRIGGER_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [subscribe_trigger::R](R) reader structure"]
+impl crate::Readable for SUBSCRIBE_TRIGGER_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [subscribe_trigger::W](W) writer structure"]
+impl crate::Writable for SUBSCRIBE_TRIGGER_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets SUBSCRIBE_TRIGGER[%s]
+to value 0"]
+impl crate::Resettable for SUBSCRIBE_TRIGGER_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9160-pac/src/egu0_ns/tasks_trigger.rs

@@ -0,0 +1,77 @@
+#[doc = "Register `TASKS_TRIGGER[%s]` writer"]
+pub struct W(crate::W<TASKS_TRIGGER_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<TASKS_TRIGGER_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<TASKS_TRIGGER_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<TASKS_TRIGGER_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Trigger n for triggering the corresponding TRIGGERED\\[n\\]
+event\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TASKS_TRIGGER_AW {
+    #[doc = "1: Trigger task"]
+    TRIGGER = 1,
+}
+impl From<TASKS_TRIGGER_AW> for bool {
+    #[inline(always)]
+    fn from(variant: TASKS_TRIGGER_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `TASKS_TRIGGER` writer - Trigger n for triggering the corresponding TRIGGERED\\[n\\]
+event"]
+pub type TASKS_TRIGGER_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, TASKS_TRIGGER_SPEC, TASKS_TRIGGER_AW, O>;
+impl<'a, const O: u8> TASKS_TRIGGER_W<'a, O> {
+    #[doc = "Trigger task"]
+    #[inline(always)]
+    pub fn trigger(self) -> &'a mut W {
+        self.variant(TASKS_TRIGGER_AW::TRIGGER)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Trigger n for triggering the corresponding TRIGGERED\\[n\\]
+event"]
+    #[inline(always)]
+    pub fn tasks_trigger(&mut self) -> TASKS_TRIGGER_W<0> {
+        TASKS_TRIGGER_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Description collection: Trigger n for triggering the corresponding TRIGGERED\\[n\\]
+event\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_trigger](index.html) module"]
+pub struct TASKS_TRIGGER_SPEC;
+impl crate::RegisterSpec for TASKS_TRIGGER_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [tasks_trigger::W](W) writer structure"]
+impl crate::Writable for TASKS_TRIGGER_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets TASKS_TRIGGER[%s]
+to value 0"]
+impl crate::Resettable for TASKS_TRIGGER_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9160-pac/src/ficr_s.rs

@@ -0,0 +1,28 @@
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    _reserved0: [u8; 0x0200],
+    #[doc = "0x200..0x22c - Device info"]
+    pub info: INFO,
+    _reserved1: [u8; 0xd4],
+    #[doc = "0x300..0xb00 - Unspecified"]
+    pub trimcnf: [TRIMCNF; 256],
+    _reserved2: [u8; 0x0100],
+    #[doc = "0xc00..0xc20 - NIST800-90B RNG calibration data"]
+    pub trng90b: TRNG90B,
+}
+#[doc = "Device info"]
+pub use info::INFO;
+#[doc = r"Cluster"]
+#[doc = "Device info"]
+pub mod info;
+#[doc = "Unspecified"]
+pub use trimcnf::TRIMCNF;
+#[doc = r"Cluster"]
+#[doc = "Unspecified"]
+pub mod trimcnf;
+#[doc = "NIST800-90B RNG calibration data"]
+pub use trng90b::TRNG90B;
+#[doc = r"Cluster"]
+#[doc = "NIST800-90B RNG calibration data"]
+pub mod trng90b;

vendor/nrf9160-pac/src/ficr_s/info.rs

@@ -0,0 +1,59 @@
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct INFO {
+    _reserved0: [u8; 0x04],
+    #[doc = "0x04..0x0c - Description collection: Device identifier"]
+    pub deviceid: [DEVICEID; 2],
+    #[doc = "0x0c - Part code"]
+    pub part: PART,
+    #[doc = "0x10 - Part Variant, Hardware version and Production configuration"]
+    pub variant: VARIANT,
+    #[doc = "0x14 - Package option"]
+    pub package: PACKAGE,
+    #[doc = "0x18 - RAM variant"]
+    pub ram: RAM,
+    #[doc = "0x1c - Flash variant"]
+    pub flash: FLASH,
+    #[doc = "0x20 - Code memory page size"]
+    pub codepagesize: CODEPAGESIZE,
+    #[doc = "0x24 - Code memory size"]
+    pub codesize: CODESIZE,
+    #[doc = "0x28 - Device type"]
+    pub devicetype: DEVICETYPE,
+}
+#[doc = "DEVICEID (r) register accessor: an alias for `Reg<DEVICEID_SPEC>`"]
+pub type DEVICEID = crate::Reg<deviceid::DEVICEID_SPEC>;
+#[doc = "Description collection: Device identifier"]
+pub mod deviceid;
+#[doc = "PART (r) register accessor: an alias for `Reg<PART_SPEC>`"]
+pub type PART = crate::Reg<part::PART_SPEC>;
+#[doc = "Part code"]
+pub mod part;
+#[doc = "VARIANT (r) register accessor: an alias for `Reg<VARIANT_SPEC>`"]
+pub type VARIANT = crate::Reg<variant::VARIANT_SPEC>;
+#[doc = "Part Variant, Hardware version and Production configuration"]
+pub mod variant;
+#[doc = "PACKAGE (r) register accessor: an alias for `Reg<PACKAGE_SPEC>`"]
+pub type PACKAGE = crate::Reg<package::PACKAGE_SPEC>;
+#[doc = "Package option"]
+pub mod package;
+#[doc = "RAM (r) register accessor: an alias for `Reg<RAM_SPEC>`"]
+pub type RAM = crate::Reg<ram::RAM_SPEC>;
+#[doc = "RAM variant"]
+pub mod ram;
+#[doc = "FLASH (r) register accessor: an alias for `Reg<FLASH_SPEC>`"]
+pub type FLASH = crate::Reg<flash::FLASH_SPEC>;
+#[doc = "Flash variant"]
+pub mod flash;
+#[doc = "CODEPAGESIZE (r) register accessor: an alias for `Reg<CODEPAGESIZE_SPEC>`"]
+pub type CODEPAGESIZE = crate::Reg<codepagesize::CODEPAGESIZE_SPEC>;
+#[doc = "Code memory page size"]
+pub mod codepagesize;
+#[doc = "CODESIZE (r) register accessor: an alias for `Reg<CODESIZE_SPEC>`"]
+pub type CODESIZE = crate::Reg<codesize::CODESIZE_SPEC>;
+#[doc = "Code memory size"]
+pub mod codesize;
+#[doc = "DEVICETYPE (r) register accessor: an alias for `Reg<DEVICETYPE_SPEC>`"]
+pub type DEVICETYPE = crate::Reg<devicetype::DEVICETYPE_SPEC>;
+#[doc = "Device type"]
+pub mod devicetype;

vendor/nrf9160-pac/src/ficr_s/info/codepagesize.rs

@@ -0,0 +1,40 @@
+#[doc = "Register `CODEPAGESIZE` reader"]
+pub struct R(crate::R<CODEPAGESIZE_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<CODEPAGESIZE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<CODEPAGESIZE_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<CODEPAGESIZE_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `CODEPAGESIZE` reader - Code memory page size"]
+pub type CODEPAGESIZE_R = crate::FieldReader<u32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - Code memory page size"]
+    #[inline(always)]
+    pub fn codepagesize(&self) -> CODEPAGESIZE_R {
+        CODEPAGESIZE_R::new(self.bits)
+    }
+}
+#[doc = "Code memory page size\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [codepagesize](index.html) module"]
+pub struct CODEPAGESIZE_SPEC;
+impl crate::RegisterSpec for CODEPAGESIZE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [codepagesize::R](R) reader structure"]
+impl crate::Readable for CODEPAGESIZE_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets CODEPAGESIZE to value 0x1000"]
+impl crate::Resettable for CODEPAGESIZE_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0x1000
+    }
+}

vendor/nrf9160-pac/src/ficr_s/info/codesize.rs

@@ -0,0 +1,40 @@
+#[doc = "Register `CODESIZE` reader"]
+pub struct R(crate::R<CODESIZE_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<CODESIZE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<CODESIZE_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<CODESIZE_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `CODESIZE` reader - Code memory size in number of pages"]
+pub type CODESIZE_R = crate::FieldReader<u32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - Code memory size in number of pages"]
+    #[inline(always)]
+    pub fn codesize(&self) -> CODESIZE_R {
+        CODESIZE_R::new(self.bits)
+    }
+}
+#[doc = "Code memory size\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [codesize](index.html) module"]
+pub struct CODESIZE_SPEC;
+impl crate::RegisterSpec for CODESIZE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [codesize::R](R) reader structure"]
+impl crate::Readable for CODESIZE_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets CODESIZE to value 0x0100"]
+impl crate::Resettable for CODESIZE_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0x0100
+    }
+}

vendor/nrf9160-pac/src/ficr_s/info/deviceid.rs

@@ -0,0 +1,41 @@
+#[doc = "Register `DEVICEID[%s]` reader"]
+pub struct R(crate::R<DEVICEID_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<DEVICEID_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<DEVICEID_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<DEVICEID_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `DEVICEID` reader - 64 bit unique device identifier"]
+pub type DEVICEID_R = crate::FieldReader<u32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - 64 bit unique device identifier"]
+    #[inline(always)]
+    pub fn deviceid(&self) -> DEVICEID_R {
+        DEVICEID_R::new(self.bits)
+    }
+}
+#[doc = "Description collection: Device identifier\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [deviceid](index.html) module"]
+pub struct DEVICEID_SPEC;
+impl crate::RegisterSpec for DEVICEID_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [deviceid::R](R) reader structure"]
+impl crate::Readable for DEVICEID_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets DEVICEID[%s]
+to value 0xffff_ffff"]
+impl crate::Resettable for DEVICEID_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0xffff_ffff
+    }
+}

vendor/nrf9160-pac/src/ficr_s/info/devicetype.rs

@@ -0,0 +1,76 @@
+#[doc = "Register `DEVICETYPE` reader"]
+pub struct R(crate::R<DEVICETYPE_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<DEVICETYPE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<DEVICETYPE_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<DEVICETYPE_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `DEVICETYPE` reader - Device type"]
+pub type DEVICETYPE_R = crate::FieldReader<u32, DEVICETYPE_A>;
+#[doc = "Device type\n\nValue on reset: 4294967295"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u32)]
+pub enum DEVICETYPE_A {
+    #[doc = "0: Device is an physical DIE"]
+    DIE = 0,
+    #[doc = "4294967295: Device is an FPGA"]
+    FPGA = 4294967295,
+}
+impl From<DEVICETYPE_A> for u32 {
+    #[inline(always)]
+    fn from(variant: DEVICETYPE_A) -> Self {
+        variant as _
+    }
+}
+impl DEVICETYPE_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<DEVICETYPE_A> {
+        match self.bits {
+            0 => Some(DEVICETYPE_A::DIE),
+            4294967295 => Some(DEVICETYPE_A::FPGA),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DIE`"]
+    #[inline(always)]
+    pub fn is_die(&self) -> bool {
+        *self == DEVICETYPE_A::DIE
+    }
+    #[doc = "Checks if the value of the field is `FPGA`"]
+    #[inline(always)]
+    pub fn is_fpga(&self) -> bool {
+        *self == DEVICETYPE_A::FPGA
+    }
+}
+impl R {
+    #[doc = "Bits 0:31 - Device type"]
+    #[inline(always)]
+    pub fn devicetype(&self) -> DEVICETYPE_R {
+        DEVICETYPE_R::new(self.bits)
+    }
+}
+#[doc = "Device type\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devicetype](index.html) module"]
+pub struct DEVICETYPE_SPEC;
+impl crate::RegisterSpec for DEVICETYPE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [devicetype::R](R) reader structure"]
+impl crate::Readable for DEVICETYPE_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets DEVICETYPE to value 0xffff_ffff"]
+impl crate::Resettable for DEVICETYPE_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0xffff_ffff
+    }
+}

vendor/nrf9160-pac/src/ficr_s/info/flash.rs

@@ -0,0 +1,68 @@
+#[doc = "Register `FLASH` reader"]
+pub struct R(crate::R<FLASH_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<FLASH_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<FLASH_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<FLASH_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `FLASH` reader - Flash variant"]
+pub type FLASH_R = crate::FieldReader<u32, FLASH_A>;
+#[doc = "Flash variant\n\nValue on reset: 1024"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u32)]
+pub enum FLASH_A {
+    #[doc = "1024: 1 MByte FLASH"]
+    K1024 = 1024,
+}
+impl From<FLASH_A> for u32 {
+    #[inline(always)]
+    fn from(variant: FLASH_A) -> Self {
+        variant as _
+    }
+}
+impl FLASH_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<FLASH_A> {
+        match self.bits {
+            1024 => Some(FLASH_A::K1024),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `K1024`"]
+    #[inline(always)]
+    pub fn is_k1024(&self) -> bool {
+        *self == FLASH_A::K1024
+    }
+}
+impl R {
+    #[doc = "Bits 0:31 - Flash variant"]
+    #[inline(always)]
+    pub fn flash(&self) -> FLASH_R {
+        FLASH_R::new(self.bits)
+    }
+}
+#[doc = "Flash variant\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [flash](index.html) module"]
+pub struct FLASH_SPEC;
+impl crate::RegisterSpec for FLASH_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [flash::R](R) reader structure"]
+impl crate::Readable for FLASH_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets FLASH to value 0x0400"]
+impl crate::Resettable for FLASH_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0x0400
+    }
+}

vendor/nrf9160-pac/src/ficr_s/info/package.rs

@@ -0,0 +1,68 @@
+#[doc = "Register `PACKAGE` reader"]
+pub struct R(crate::R<PACKAGE_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<PACKAGE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<PACKAGE_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<PACKAGE_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `PACKAGE` reader - Package option"]
+pub type PACKAGE_R = crate::FieldReader<u32, PACKAGE_A>;
+#[doc = "Package option\n\nValue on reset: 8192"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u32)]
+pub enum PACKAGE_A {
+    #[doc = "8192: CCxx - 236 ball wlCSP"]
+    CC = 8192,
+}
+impl From<PACKAGE_A> for u32 {
+    #[inline(always)]
+    fn from(variant: PACKAGE_A) -> Self {
+        variant as _
+    }
+}
+impl PACKAGE_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<PACKAGE_A> {
+        match self.bits {
+            8192 => Some(PACKAGE_A::CC),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `CC`"]
+    #[inline(always)]
+    pub fn is_cc(&self) -> bool {
+        *self == PACKAGE_A::CC
+    }
+}
+impl R {
+    #[doc = "Bits 0:31 - Package option"]
+    #[inline(always)]
+    pub fn package(&self) -> PACKAGE_R {
+        PACKAGE_R::new(self.bits)
+    }
+}
+#[doc = "Package option\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [package](index.html) module"]
+pub struct PACKAGE_SPEC;
+impl crate::RegisterSpec for PACKAGE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [package::R](R) reader structure"]
+impl crate::Readable for PACKAGE_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets PACKAGE to value 0x2000"]
+impl crate::Resettable for PACKAGE_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0x2000
+    }
+}

vendor/nrf9160-pac/src/ficr_s/info/part.rs

@@ -0,0 +1,68 @@
+#[doc = "Register `PART` reader"]
+pub struct R(crate::R<PART_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<PART_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<PART_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<PART_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `PART` reader - Part code"]
+pub type PART_R = crate::FieldReader<u32, PART_A>;
+#[doc = "Part code\n\nValue on reset: 37216"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u32)]
+pub enum PART_A {
+    #[doc = "37216: nRF9160"]
+    N9160 = 37216,
+}
+impl From<PART_A> for u32 {
+    #[inline(always)]
+    fn from(variant: PART_A) -> Self {
+        variant as _
+    }
+}
+impl PART_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<PART_A> {
+        match self.bits {
+            37216 => Some(PART_A::N9160),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `N9160`"]
+    #[inline(always)]
+    pub fn is_n9160(&self) -> bool {
+        *self == PART_A::N9160
+    }
+}
+impl R {
+    #[doc = "Bits 0:31 - Part code"]
+    #[inline(always)]
+    pub fn part(&self) -> PART_R {
+        PART_R::new(self.bits)
+    }
+}
+#[doc = "Part code\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [part](index.html) module"]
+pub struct PART_SPEC;
+impl crate::RegisterSpec for PART_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [part::R](R) reader structure"]
+impl crate::Readable for PART_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets PART to value 0x9160"]
+impl crate::Resettable for PART_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0x9160
+    }
+}

vendor/nrf9160-pac/src/ficr_s/info/ram.rs

@@ -0,0 +1,76 @@
+#[doc = "Register `RAM` reader"]
+pub struct R(crate::R<RAM_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<RAM_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<RAM_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<RAM_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `RAM` reader - RAM variant"]
+pub type RAM_R = crate::FieldReader<u32, RAM_A>;
+#[doc = "RAM variant\n\nValue on reset: 256"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u32)]
+pub enum RAM_A {
+    #[doc = "256: 256 kByte RAM"]
+    K256 = 256,
+    #[doc = "4294967295: Unspecified"]
+    UNSPECIFIED = 4294967295,
+}
+impl From<RAM_A> for u32 {
+    #[inline(always)]
+    fn from(variant: RAM_A) -> Self {
+        variant as _
+    }
+}
+impl RAM_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<RAM_A> {
+        match self.bits {
+            256 => Some(RAM_A::K256),
+            4294967295 => Some(RAM_A::UNSPECIFIED),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `K256`"]
+    #[inline(always)]
+    pub fn is_k256(&self) -> bool {
+        *self == RAM_A::K256
+    }
+    #[doc = "Checks if the value of the field is `UNSPECIFIED`"]
+    #[inline(always)]
+    pub fn is_unspecified(&self) -> bool {
+        *self == RAM_A::UNSPECIFIED
+    }
+}
+impl R {
+    #[doc = "Bits 0:31 - RAM variant"]
+    #[inline(always)]
+    pub fn ram(&self) -> RAM_R {
+        RAM_R::new(self.bits)
+    }
+}
+#[doc = "RAM variant\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ram](index.html) module"]
+pub struct RAM_SPEC;
+impl crate::RegisterSpec for RAM_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [ram::R](R) reader structure"]
+impl crate::Readable for RAM_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets RAM to value 0x0100"]
+impl crate::Resettable for RAM_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0x0100
+    }
+}

vendor/nrf9160-pac/src/ficr_s/info/variant.rs

@@ -0,0 +1,76 @@
+#[doc = "Register `VARIANT` reader"]
+pub struct R(crate::R<VARIANT_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<VARIANT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<VARIANT_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<VARIANT_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `VARIANT` reader - Part Variant, Hardware version and Production configuration, encoded as ASCII"]
+pub type VARIANT_R = crate::FieldReader<u32, VARIANT_A>;
+#[doc = "Part Variant, Hardware version and Production configuration, encoded as ASCII\n\nValue on reset: 268435455"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u32)]
+pub enum VARIANT_A {
+    #[doc = "1094795585: AAAA"]
+    AAAA = 1094795585,
+    #[doc = "1094795568: AAA0"]
+    AAA0 = 1094795568,
+}
+impl From<VARIANT_A> for u32 {
+    #[inline(always)]
+    fn from(variant: VARIANT_A) -> Self {
+        variant as _
+    }
+}
+impl VARIANT_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<VARIANT_A> {
+        match self.bits {
+            1094795585 => Some(VARIANT_A::AAAA),
+            1094795568 => Some(VARIANT_A::AAA0),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `AAAA`"]
+    #[inline(always)]
+    pub fn is_aaaa(&self) -> bool {
+        *self == VARIANT_A::AAAA
+    }
+    #[doc = "Checks if the value of the field is `AAA0`"]
+    #[inline(always)]
+    pub fn is_aaa0(&self) -> bool {
+        *self == VARIANT_A::AAA0
+    }
+}
+impl R {
+    #[doc = "Bits 0:31 - Part Variant, Hardware version and Production configuration, encoded as ASCII"]
+    #[inline(always)]
+    pub fn variant(&self) -> VARIANT_R {
+        VARIANT_R::new(self.bits)
+    }
+}
+#[doc = "Part Variant, Hardware version and Production configuration\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [variant](index.html) module"]
+pub struct VARIANT_SPEC;
+impl crate::RegisterSpec for VARIANT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [variant::R](R) reader structure"]
+impl crate::Readable for VARIANT_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets VARIANT to value 0x0fff_ffff"]
+impl crate::Resettable for VARIANT_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0x0fff_ffff
+    }
+}

vendor/nrf9160-pac/src/ficr_s/trimcnf.rs

@@ -0,0 +1,16 @@
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct TRIMCNF {
+    #[doc = "0x00 - Description cluster: Address"]
+    pub addr: ADDR,
+    #[doc = "0x04 - Description cluster: Data"]
+    pub data: DATA,
+}
+#[doc = "ADDR (r) register accessor: an alias for `Reg<ADDR_SPEC>`"]
+pub type ADDR = crate::Reg<addr::ADDR_SPEC>;
+#[doc = "Description cluster: Address"]
+pub mod addr;
+#[doc = "DATA (r) register accessor: an alias for `Reg<DATA_SPEC>`"]
+pub type DATA = crate::Reg<data::DATA_SPEC>;
+#[doc = "Description cluster: Data"]
+pub mod data;

vendor/nrf9160-pac/src/ficr_s/trimcnf/addr.rs

@@ -0,0 +1,40 @@
+#[doc = "Register `ADDR` reader"]
+pub struct R(crate::R<ADDR_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<ADDR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<ADDR_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<ADDR_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `Address` reader - Address"]
+pub type ADDRESS_R = crate::FieldReader<u32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - Address"]
+    #[inline(always)]
+    pub fn address(&self) -> ADDRESS_R {
+        ADDRESS_R::new(self.bits)
+    }
+}
+#[doc = "Description cluster: Address\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"]
+pub struct ADDR_SPEC;
+impl crate::RegisterSpec for ADDR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [addr::R](R) reader structure"]
+impl crate::Readable for ADDR_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets ADDR to value 0xffff_ffff"]
+impl crate::Resettable for ADDR_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0xffff_ffff
+    }
+}

vendor/nrf9160-pac/src/ficr_s/trimcnf/data.rs

@@ -0,0 +1,40 @@
+#[doc = "Register `DATA` reader"]
+pub struct R(crate::R<DATA_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<DATA_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<DATA_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<DATA_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `Data` reader - Data"]
+pub type DATA_R = crate::FieldReader<u32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - Data"]
+    #[inline(always)]
+    pub fn data(&self) -> DATA_R {
+        DATA_R::new(self.bits)
+    }
+}
+#[doc = "Description cluster: Data\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"]
+pub struct DATA_SPEC;
+impl crate::RegisterSpec for DATA_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [data::R](R) reader structure"]
+impl crate::Readable for DATA_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets DATA to value 0xffff_ffff"]
+impl crate::Resettable for DATA_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0xffff_ffff
+    }
+}

vendor/nrf9160-pac/src/ficr_s/trng90b.rs

@@ -0,0 +1,52 @@
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct TRNG90B {
+    #[doc = "0x00 - Amount of bytes for the required entropy bits"]
+    pub bytes: BYTES,
+    #[doc = "0x04 - Repetition counter cutoff"]
+    pub rccutoff: RCCUTOFF,
+    #[doc = "0x08 - Adaptive proportion cutoff"]
+    pub apcutoff: APCUTOFF,
+    #[doc = "0x0c - Amount of bytes for the startup tests"]
+    pub startup: STARTUP,
+    #[doc = "0x10 - Sample count for ring oscillator 1"]
+    pub rosc1: ROSC1,
+    #[doc = "0x14 - Sample count for ring oscillator 2"]
+    pub rosc2: ROSC2,
+    #[doc = "0x18 - Sample count for ring oscillator 3"]
+    pub rosc3: ROSC3,
+    #[doc = "0x1c - Sample count for ring oscillator 4"]
+    pub rosc4: ROSC4,
+}
+#[doc = "BYTES (r) register accessor: an alias for `Reg<BYTES_SPEC>`"]
+pub type BYTES = crate::Reg<bytes::BYTES_SPEC>;
+#[doc = "Amount of bytes for the required entropy bits"]
+pub mod bytes;
+#[doc = "RCCUTOFF (r) register accessor: an alias for `Reg<RCCUTOFF_SPEC>`"]
+pub type RCCUTOFF = crate::Reg<rccutoff::RCCUTOFF_SPEC>;
+#[doc = "Repetition counter cutoff"]
+pub mod rccutoff;
+#[doc = "APCUTOFF (r) register accessor: an alias for `Reg<APCUTOFF_SPEC>`"]
+pub type APCUTOFF = crate::Reg<apcutoff::APCUTOFF_SPEC>;
+#[doc = "Adaptive proportion cutoff"]
+pub mod apcutoff;
+#[doc = "STARTUP (r) register accessor: an alias for `Reg<STARTUP_SPEC>`"]
+pub type STARTUP = crate::Reg<startup::STARTUP_SPEC>;
+#[doc = "Amount of bytes for the startup tests"]
+pub mod startup;
+#[doc = "ROSC1 (r) register accessor: an alias for `Reg<ROSC1_SPEC>`"]
+pub type ROSC1 = crate::Reg<rosc1::ROSC1_SPEC>;
+#[doc = "Sample count for ring oscillator 1"]
+pub mod rosc1;
+#[doc = "ROSC2 (r) register accessor: an alias for `Reg<ROSC2_SPEC>`"]
+pub type ROSC2 = crate::Reg<rosc2::ROSC2_SPEC>;
+#[doc = "Sample count for ring oscillator 2"]
+pub mod rosc2;
+#[doc = "ROSC3 (r) register accessor: an alias for `Reg<ROSC3_SPEC>`"]
+pub type ROSC3 = crate::Reg<rosc3::ROSC3_SPEC>;
+#[doc = "Sample count for ring oscillator 3"]
+pub mod rosc3;
+#[doc = "ROSC4 (r) register accessor: an alias for `Reg<ROSC4_SPEC>`"]
+pub type ROSC4 = crate::Reg<rosc4::ROSC4_SPEC>;
+#[doc = "Sample count for ring oscillator 4"]
+pub mod rosc4;

vendor/nrf9160-pac/src/ficr_s/trng90b/apcutoff.rs

@@ -0,0 +1,40 @@
+#[doc = "Register `APCUTOFF` reader"]
+pub struct R(crate::R<APCUTOFF_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<APCUTOFF_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<APCUTOFF_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<APCUTOFF_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `APCUTOFF` reader - Adaptive proportion cutoff"]
+pub type APCUTOFF_R = crate::FieldReader<u32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - Adaptive proportion cutoff"]
+    #[inline(always)]
+    pub fn apcutoff(&self) -> APCUTOFF_R {
+        APCUTOFF_R::new(self.bits)
+    }
+}
+#[doc = "Adaptive proportion cutoff\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apcutoff](index.html) module"]
+pub struct APCUTOFF_SPEC;
+impl crate::RegisterSpec for APCUTOFF_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [apcutoff::R](R) reader structure"]
+impl crate::Readable for APCUTOFF_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets APCUTOFF to value 0xffff_ffff"]
+impl crate::Resettable for APCUTOFF_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0xffff_ffff
+    }
+}

vendor/nrf9160-pac/src/ficr_s/trng90b/bytes.rs

@@ -0,0 +1,40 @@
+#[doc = "Register `BYTES` reader"]
+pub struct R(crate::R<BYTES_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<BYTES_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<BYTES_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<BYTES_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `BYTES` reader - Amount of bytes for the required entropy bits"]
+pub type BYTES_R = crate::FieldReader<u32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - Amount of bytes for the required entropy bits"]
+    #[inline(always)]
+    pub fn bytes(&self) -> BYTES_R {
+        BYTES_R::new(self.bits)
+    }
+}
+#[doc = "Amount of bytes for the required entropy bits\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bytes](index.html) module"]
+pub struct BYTES_SPEC;
+impl crate::RegisterSpec for BYTES_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [bytes::R](R) reader structure"]
+impl crate::Readable for BYTES_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets BYTES to value 0xffff_ffff"]
+impl crate::Resettable for BYTES_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0xffff_ffff
+    }
+}

vendor/nrf9160-pac/src/ficr_s/trng90b/rccutoff.rs

@@ -0,0 +1,40 @@
+#[doc = "Register `RCCUTOFF` reader"]
+pub struct R(crate::R<RCCUTOFF_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<RCCUTOFF_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<RCCUTOFF_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<RCCUTOFF_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `RCCUTOFF` reader - Repetition counter cutoff"]
+pub type RCCUTOFF_R = crate::FieldReader<u32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - Repetition counter cutoff"]
+    #[inline(always)]
+    pub fn rccutoff(&self) -> RCCUTOFF_R {
+        RCCUTOFF_R::new(self.bits)
+    }
+}
+#[doc = "Repetition counter cutoff\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rccutoff](index.html) module"]
+pub struct RCCUTOFF_SPEC;
+impl crate::RegisterSpec for RCCUTOFF_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [rccutoff::R](R) reader structure"]
+impl crate::Readable for RCCUTOFF_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets RCCUTOFF to value 0xffff_ffff"]
+impl crate::Resettable for RCCUTOFF_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0xffff_ffff
+    }
+}

vendor/nrf9160-pac/src/ficr_s/trng90b/rosc1.rs

@@ -0,0 +1,40 @@
+#[doc = "Register `ROSC1` reader"]
+pub struct R(crate::R<ROSC1_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<ROSC1_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<ROSC1_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<ROSC1_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `ROSC1` reader - Sample count for ring oscillator 1"]
+pub type ROSC1_R = crate::FieldReader<u32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - Sample count for ring oscillator 1"]
+    #[inline(always)]
+    pub fn rosc1(&self) -> ROSC1_R {
+        ROSC1_R::new(self.bits)
+    }
+}
+#[doc = "Sample count for ring oscillator 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rosc1](index.html) module"]
+pub struct ROSC1_SPEC;
+impl crate::RegisterSpec for ROSC1_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [rosc1::R](R) reader structure"]
+impl crate::Readable for ROSC1_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets ROSC1 to value 0xffff_ffff"]
+impl crate::Resettable for ROSC1_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0xffff_ffff
+    }
+}

vendor/nrf9160-pac/src/ficr_s/trng90b/rosc2.rs

@@ -0,0 +1,40 @@
+#[doc = "Register `ROSC2` reader"]
+pub struct R(crate::R<ROSC2_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<ROSC2_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<ROSC2_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<ROSC2_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `ROSC2` reader - Sample count for ring oscillator 2"]
+pub type ROSC2_R = crate::FieldReader<u32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - Sample count for ring oscillator 2"]
+    #[inline(always)]
+    pub fn rosc2(&self) -> ROSC2_R {
+        ROSC2_R::new(self.bits)
+    }
+}
+#[doc = "Sample count for ring oscillator 2\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rosc2](index.html) module"]
+pub struct ROSC2_SPEC;
+impl crate::RegisterSpec for ROSC2_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [rosc2::R](R) reader structure"]
+impl crate::Readable for ROSC2_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets ROSC2 to value 0xffff_ffff"]
+impl crate::Resettable for ROSC2_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0xffff_ffff
+    }
+}

vendor/nrf9160-pac/src/ficr_s/trng90b/rosc3.rs

@@ -0,0 +1,40 @@
+#[doc = "Register `ROSC3` reader"]
+pub struct R(crate::R<ROSC3_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<ROSC3_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<ROSC3_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<ROSC3_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `ROSC3` reader - Sample count for ring oscillator 3"]
+pub type ROSC3_R = crate::FieldReader<u32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - Sample count for ring oscillator 3"]
+    #[inline(always)]
+    pub fn rosc3(&self) -> ROSC3_R {
+        ROSC3_R::new(self.bits)
+    }
+}
+#[doc = "Sample count for ring oscillator 3\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rosc3](index.html) module"]
+pub struct ROSC3_SPEC;
+impl crate::RegisterSpec for ROSC3_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [rosc3::R](R) reader structure"]
+impl crate::Readable for ROSC3_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets ROSC3 to value 0xffff_ffff"]
+impl crate::Resettable for ROSC3_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0xffff_ffff
+    }
+}

vendor/nrf9160-pac/src/ficr_s/trng90b/rosc4.rs

@@ -0,0 +1,40 @@
+#[doc = "Register `ROSC4` reader"]
+pub struct R(crate::R<ROSC4_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<ROSC4_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<ROSC4_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<ROSC4_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `ROSC4` reader - Sample count for ring oscillator 4"]
+pub type ROSC4_R = crate::FieldReader<u32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - Sample count for ring oscillator 4"]
+    #[inline(always)]
+    pub fn rosc4(&self) -> ROSC4_R {
+        ROSC4_R::new(self.bits)
+    }
+}
+#[doc = "Sample count for ring oscillator 4\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rosc4](index.html) module"]
+pub struct ROSC4_SPEC;
+impl crate::RegisterSpec for ROSC4_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [rosc4::R](R) reader structure"]
+impl crate::Readable for ROSC4_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets ROSC4 to value 0xffff_ffff"]
+impl crate::Resettable for ROSC4_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0xffff_ffff
+    }
+}

vendor/nrf9160-pac/src/ficr_s/trng90b/startup.rs

@@ -0,0 +1,40 @@
+#[doc = "Register `STARTUP` reader"]
+pub struct R(crate::R<STARTUP_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<STARTUP_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<STARTUP_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<STARTUP_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Field `STARTUP` reader - Amount of bytes for the startup tests"]
+pub type STARTUP_R = crate::FieldReader<u32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - Amount of bytes for the startup tests"]
+    #[inline(always)]
+    pub fn startup(&self) -> STARTUP_R {
+        STARTUP_R::new(self.bits)
+    }
+}
+#[doc = "Amount of bytes for the startup tests\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [startup](index.html) module"]
+pub struct STARTUP_SPEC;
+impl crate::RegisterSpec for STARTUP_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [startup::R](R) reader structure"]
+impl crate::Readable for STARTUP_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets STARTUP to value 0x0210"]
+impl crate::Resettable for STARTUP_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0x0210
+    }
+}

vendor/nrf9160-pac/src/fpu_ns.rs

@@ -0,0 +1,10 @@
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00 - Unused."]
+    pub unused: UNUSED,
+}
+#[doc = "UNUSED (r) register accessor: an alias for `Reg<UNUSED_SPEC>`"]
+pub type UNUSED = crate::Reg<unused::UNUSED_SPEC>;
+#[doc = "Unused."]
+pub mod unused;

vendor/nrf9160-pac/src/fpu_ns/unused.rs

@@ -0,0 +1,31 @@
+#[doc = "Register `UNUSED` reader"]
+pub struct R(crate::R<UNUSED_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<UNUSED_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<UNUSED_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<UNUSED_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Unused.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [unused](index.html) module"]
+pub struct UNUSED_SPEC;
+impl crate::RegisterSpec for UNUSED_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [unused::R](R) reader structure"]
+impl crate::Readable for UNUSED_SPEC {
+    type Reader = R;
+}
+#[doc = "`reset()` method sets UNUSED to value 0"]
+impl crate::Resettable for UNUSED_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9160-pac/src/generic.rs

@@ -0,0 +1,573 @@
+use core::marker;
+#[doc = " Raw register type"]
+pub trait RegisterSpec {
+    #[doc = " Raw register type (`u8`, `u16`, `u32`, ...)."]
+    type Ux: Copy;
+}
+#[doc = " Trait implemented by readable registers to enable the `read` method."]
+#[doc = ""]
+#[doc = " Registers marked with `Writable` can be also `modify`'ed."]
+pub trait Readable: RegisterSpec {
+    #[doc = " Result from a call to `read` and argument to `modify`."]
+    type Reader: From<R<Self>> + core::ops::Deref<Target = R<Self>>;
+}
+#[doc = " Trait implemented by writeable registers."]
+#[doc = ""]
+#[doc = " This enables the  `write`, `write_with_zero` and `reset` methods."]
+#[doc = ""]
+#[doc = " Registers marked with `Readable` can be also `modify`'ed."]
+pub trait Writable: RegisterSpec {
+    #[doc = " Writer type argument to `write`, et al."]
+    type Writer: From<W<Self>> + core::ops::DerefMut<Target = W<Self>>;
+}
+#[doc = " Reset value of the register."]
+#[doc = ""]
+#[doc = " This value is the initial value for the `write` method. It can also be directly written to the"]
+#[doc = " register by using the `reset` method."]
+pub trait Resettable: RegisterSpec {
+    #[doc = " Reset value of the register."]
+    fn reset_value() -> Self::Ux;
+}
+#[doc = " This structure provides volatile access to registers."]
+#[repr(transparent)]
+pub struct Reg<REG: RegisterSpec> {
+    register: vcell::VolatileCell<REG::Ux>,
+    _marker: marker::PhantomData<REG>,
+}
+unsafe impl<REG: RegisterSpec> Send for Reg<REG> where REG::Ux: Send {}
+impl<REG: RegisterSpec> Reg<REG> {
+    #[doc = " Returns the underlying memory address of register."]
+    #[doc = ""]
+    #[doc = " ```ignore"]
+    #[doc = " let reg_ptr = periph.reg.as_ptr();"]
+    #[doc = " ```"]
+    #[inline(always)]
+    pub fn as_ptr(&self) -> *mut REG::Ux {
+        self.register.as_ptr()
+    }
+}
+impl<REG: Readable> Reg<REG> {
+    #[doc = " Reads the contents of a `Readable` register."]
+    #[doc = ""]
+    #[doc = " You can read the raw contents of a register by using `bits`:"]
+    #[doc = " ```ignore"]
+    #[doc = " let bits = periph.reg.read().bits();"]
+    #[doc = " ```"]
+    #[doc = " or get the content of a particular field of a register:"]
+    #[doc = " ```ignore"]
+    #[doc = " let reader = periph.reg.read();"]
+    #[doc = " let bits = reader.field1().bits();"]
+    #[doc = " let flag = reader.field2().bit_is_set();"]
+    #[doc = " ```"]
+    #[inline(always)]
+    pub fn read(&self) -> REG::Reader {
+        REG::Reader::from(R {
+            bits: self.register.get(),
+            _reg: marker::PhantomData,
+        })
+    }
+}
+impl<REG: Resettable + Writable> Reg<REG> {
+    #[doc = " Writes the reset value to `Writable` register."]
+    #[doc = ""]
+    #[doc = " Resets the register to its initial state."]
+    #[inline(always)]
+    pub fn reset(&self) {
+        self.register.set(REG::reset_value())
+    }
+    #[doc = " Writes bits to a `Writable` register."]
+    #[doc = ""]
+    #[doc = " You can write raw bits into a register:"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.write(|w| unsafe { w.bits(rawbits) });"]
+    #[doc = " ```"]
+    #[doc = " or write only the fields you need:"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.write(|w| w"]
+    #[doc = "     .field1().bits(newfield1bits)"]
+    #[doc = "     .field2().set_bit()"]
+    #[doc = "     .field3().variant(VARIANT)"]
+    #[doc = " );"]
+    #[doc = " ```"]
+    #[doc = " or an alternative way of saying the same:"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.write(|w| {"]
+    #[doc = "     w.field1().bits(newfield1bits);"]
+    #[doc = "     w.field2().set_bit();"]
+    #[doc = "     w.field3().variant(VARIANT)"]
+    #[doc = " });"]
+    #[doc = " ```"]
+    #[doc = " In the latter case, other fields will be set to their reset value."]
+    #[inline(always)]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut REG::Writer) -> &mut W<REG>,
+    {
+        self.register.set(
+            f(&mut REG::Writer::from(W {
+                bits: REG::reset_value(),
+                _reg: marker::PhantomData,
+            }))
+            .bits,
+        );
+    }
+}
+impl<REG: Writable> Reg<REG>
+where
+    REG::Ux: Default,
+{
+    #[doc = " Writes 0 to a `Writable` register."]
+    #[doc = ""]
+    #[doc = " Similar to `write`, but unused bits will contain 0."]
+    #[inline(always)]
+    pub unsafe fn write_with_zero<F>(&self, f: F)
+    where
+        F: FnOnce(&mut REG::Writer) -> &mut W<REG>,
+    {
+        self.register.set(
+            (*f(&mut REG::Writer::from(W {
+                bits: REG::Ux::default(),
+                _reg: marker::PhantomData,
+            })))
+            .bits,
+        );
+    }
+}
+impl<REG: Readable + Writable> Reg<REG> {
+    #[doc = " Modifies the contents of the register by reading and then writing it."]
+    #[doc = ""]
+    #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.modify(|r, w| unsafe { w.bits("]
+    #[doc = "    r.bits() | 3"]
+    #[doc = " ) });"]
+    #[doc = " ```"]
+    #[doc = " or"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.modify(|_, w| w"]
+    #[doc = "     .field1().bits(newfield1bits)"]
+    #[doc = "     .field2().set_bit()"]
+    #[doc = "     .field3().variant(VARIANT)"]
+    #[doc = " );"]
+    #[doc = " ```"]
+    #[doc = " or an alternative way of saying the same:"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.modify(|_, w| {"]
+    #[doc = "     w.field1().bits(newfield1bits);"]
+    #[doc = "     w.field2().set_bit();"]
+    #[doc = "     w.field3().variant(VARIANT)"]
+    #[doc = " });"]
+    #[doc = " ```"]
+    #[doc = " Other fields will have the value they had before the call to `modify`."]
+    #[inline(always)]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&REG::Reader, &'w mut REG::Writer) -> &'w mut W<REG>,
+    {
+        let bits = self.register.get();
+        self.register.set(
+            f(
+                &REG::Reader::from(R {
+                    bits,
+                    _reg: marker::PhantomData,
+                }),
+                &mut REG::Writer::from(W {
+                    bits,
+                    _reg: marker::PhantomData,
+                }),
+            )
+            .bits,
+        );
+    }
+}
+#[doc = " Register reader."]
+#[doc = ""]
+#[doc = " Result of the `read` methods of registers. Also used as a closure argument in the `modify`"]
+#[doc = " method."]
+pub struct R<REG: RegisterSpec + ?Sized> {
+    pub(crate) bits: REG::Ux,
+    _reg: marker::PhantomData<REG>,
+}
+impl<REG: RegisterSpec> R<REG> {
+    #[doc = " Reads raw bits from register."]
+    #[inline(always)]
+    pub fn bits(&self) -> REG::Ux {
+        self.bits
+    }
+}
+impl<REG: RegisterSpec, FI> PartialEq<FI> for R<REG>
+where
+    REG::Ux: PartialEq,
+    FI: Copy + Into<REG::Ux>,
+{
+    #[inline(always)]
+    fn eq(&self, other: &FI) -> bool {
+        self.bits.eq(&(*other).into())
+    }
+}
+#[doc = " Register writer."]
+#[doc = ""]
+#[doc = " Used as an argument to the closures in the `write` and `modify` methods of the register."]
+pub struct W<REG: RegisterSpec + ?Sized> {
+    #[doc = "Writable bits"]
+    pub(crate) bits: REG::Ux,
+    _reg: marker::PhantomData<REG>,
+}
+impl<REG: RegisterSpec> W<REG> {
+    #[doc = " Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+}
+#[doc(hidden)]
+pub struct FieldReaderRaw<U, T> {
+    pub(crate) bits: U,
+    _reg: marker::PhantomData<T>,
+}
+impl<U, FI> FieldReaderRaw<U, FI>
+where
+    U: Copy,
+{
+    #[doc = " Creates a new instance of the reader."]
+    #[allow(unused)]
+    #[inline(always)]
+    pub(crate) fn new(bits: U) -> Self {
+        Self {
+            bits,
+            _reg: marker::PhantomData,
+        }
+    }
+}
+#[doc(hidden)]
+pub struct BitReaderRaw<T> {
+    pub(crate) bits: bool,
+    _reg: marker::PhantomData<T>,
+}
+impl<FI> BitReaderRaw<FI> {
+    #[doc = " Creates a new instance of the reader."]
+    #[allow(unused)]
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        Self {
+            bits,
+            _reg: marker::PhantomData,
+        }
+    }
+}
+#[doc = " Field reader."]
+#[doc = ""]
+#[doc = " Result of the `read` methods of fields."]
+pub type FieldReader<U, FI> = FieldReaderRaw<U, FI>;
+#[doc = " Bit-wise field reader"]
+pub type BitReader<FI> = BitReaderRaw<FI>;
+impl<U, FI> FieldReader<U, FI>
+where
+    U: Copy,
+{
+    #[doc = " Reads raw bits from field."]
+    #[inline(always)]
+    pub fn bits(&self) -> U {
+        self.bits
+    }
+}
+impl<U, FI> PartialEq<FI> for FieldReader<U, FI>
+where
+    U: PartialEq,
+    FI: Copy + Into<U>,
+{
+    #[inline(always)]
+    fn eq(&self, other: &FI) -> bool {
+        self.bits.eq(&(*other).into())
+    }
+}
+impl<FI> PartialEq<FI> for BitReader<FI>
+where
+    FI: Copy + Into<bool>,
+{
+    #[inline(always)]
+    fn eq(&self, other: &FI) -> bool {
+        self.bits.eq(&(*other).into())
+    }
+}
+impl<FI> BitReader<FI> {
+    #[doc = " Value of the field as raw bits."]
+    #[inline(always)]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = " Returns `true` if the bit is clear (0)."]
+    #[inline(always)]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = " Returns `true` if the bit is set (1)."]
+    #[inline(always)]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc(hidden)]
+pub struct Safe;
+#[doc(hidden)]
+pub struct Unsafe;
+#[doc(hidden)]
+pub struct FieldWriterRaw<'a, U, REG, N, FI, Safety, const WI: u8, const O: u8>
+where
+    REG: Writable + RegisterSpec<Ux = U>,
+    FI: Into<N>,
+{
+    pub(crate) w: &'a mut REG::Writer,
+    _field: marker::PhantomData<(N, FI, Safety)>,
+}
+impl<'a, U, REG, N, FI, Safety, const WI: u8, const O: u8>
+    FieldWriterRaw<'a, U, REG, N, FI, Safety, WI, O>
+where
+    REG: Writable + RegisterSpec<Ux = U>,
+    FI: Into<N>,
+{
+    #[doc = " Creates a new instance of the writer"]
+    #[allow(unused)]
+    #[inline(always)]
+    pub(crate) fn new(w: &'a mut REG::Writer) -> Self {
+        Self {
+            w,
+            _field: marker::PhantomData,
+        }
+    }
+}
+#[doc(hidden)]
+pub struct BitWriterRaw<'a, U, REG, FI, M, const O: u8>
+where
+    REG: Writable + RegisterSpec<Ux = U>,
+    FI: Into<bool>,
+{
+    pub(crate) w: &'a mut REG::Writer,
+    _field: marker::PhantomData<(FI, M)>,
+}
+impl<'a, U, REG, FI, M, const O: u8> BitWriterRaw<'a, U, REG, FI, M, O>
+where
+    REG: Writable + RegisterSpec<Ux = U>,
+    FI: Into<bool>,
+{
+    #[doc = " Creates a new instance of the writer"]
+    #[allow(unused)]
+    #[inline(always)]
+    pub(crate) fn new(w: &'a mut REG::Writer) -> Self {
+        Self {
+            w,
+            _field: marker::PhantomData,
+        }
+    }
+}
+#[doc = " Write field Proxy with unsafe `bits`"]
+pub type FieldWriter<'a, U, REG, N, FI, const WI: u8, const O: u8> =
+    FieldWriterRaw<'a, U, REG, N, FI, Unsafe, WI, O>;
+#[doc = " Write field Proxy with safe `bits`"]
+pub type FieldWriterSafe<'a, U, REG, N, FI, const WI: u8, const O: u8> =
+    FieldWriterRaw<'a, U, REG, N, FI, Safe, WI, O>;
+impl<'a, U, REG, N, FI, const WI: u8, const OF: u8> FieldWriter<'a, U, REG, N, FI, WI, OF>
+where
+    REG: Writable + RegisterSpec<Ux = U>,
+    FI: Into<N>,
+{
+    #[doc = " Field width"]
+    pub const WIDTH: u8 = WI;
+    #[doc = " Field offset"]
+    pub const OFFSET: u8 = OF;
+}
+impl<'a, U, REG, N, FI, const WI: u8, const OF: u8> FieldWriterSafe<'a, U, REG, N, FI, WI, OF>
+where
+    REG: Writable + RegisterSpec<Ux = U>,
+    FI: Into<N>,
+{
+    #[doc = " Field width"]
+    pub const WIDTH: u8 = WI;
+    #[doc = " Field offset"]
+    pub const OFFSET: u8 = OF;
+}
+macro_rules! bit_proxy {
+    ($ writer : ident , $ mwv : ident) => {
+        #[doc(hidden)]
+        pub struct $mwv;
+        #[doc = " Bit-wise write field proxy"]
+        pub type $writer<'a, U, REG, FI, const O: u8> = BitWriterRaw<'a, U, REG, FI, $mwv, O>;
+        impl<'a, U, REG, FI, const OF: u8> $writer<'a, U, REG, FI, OF>
+        where
+            REG: Writable + RegisterSpec<Ux = U>,
+            FI: Into<bool>,
+        {
+            #[doc = " Field width"]
+            pub const WIDTH: u8 = 1;
+            #[doc = " Field offset"]
+            pub const OFFSET: u8 = OF;
+        }
+    };
+}
+macro_rules! impl_bit_proxy {
+    ($ writer : ident , $ U : ty) => {
+        impl<'a, REG, FI, const OF: u8> $writer<'a, $U, REG, FI, OF>
+        where
+            REG: Writable + RegisterSpec<Ux = $U>,
+            FI: Into<bool>,
+        {
+            #[doc = " Writes bit to the field"]
+            #[inline(always)]
+            pub fn bit(self, value: bool) -> &'a mut REG::Writer {
+                self.w.bits = (self.w.bits & !(1 << { OF })) | ((<$U>::from(value) & 1) << { OF });
+                self.w
+            }
+            #[doc = " Writes `variant` to the field"]
+            #[inline(always)]
+            pub fn variant(self, variant: FI) -> &'a mut REG::Writer {
+                self.bit(variant.into())
+            }
+        }
+    };
+}
+bit_proxy!(BitWriter, BitM);
+bit_proxy!(BitWriter1S, Bit1S);
+bit_proxy!(BitWriter0C, Bit0C);
+bit_proxy!(BitWriter1C, Bit1C);
+bit_proxy!(BitWriter0S, Bit0S);
+bit_proxy!(BitWriter1T, Bit1T);
+bit_proxy!(BitWriter0T, Bit0T);
+macro_rules! impl_proxy {
+    ($ U : ty) => {
+        impl<'a, REG, N, FI, const WI: u8, const OF: u8> FieldWriter<'a, $U, REG, N, FI, WI, OF>
+        where
+            REG: Writable + RegisterSpec<Ux = $U>,
+            N: Into<$U>,
+            FI: Into<N>,
+        {
+            const MASK: $U = <$U>::MAX >> (<$U>::MAX.leading_ones() as u8 - { WI });
+            #[doc = " Writes raw bits to the field"]
+            #[doc = ""]
+            #[doc = " # Safety"]
+            #[doc = ""]
+            #[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"]
+            #[inline(always)]
+            pub unsafe fn bits(self, value: N) -> &'a mut REG::Writer {
+                self.w.bits = (self.w.bits & !(Self::MASK << { OF }))
+                    | ((value.into() & Self::MASK) << { OF });
+                self.w
+            }
+            #[doc = " Writes `variant` to the field"]
+            #[inline(always)]
+            pub fn variant(self, variant: FI) -> &'a mut REG::Writer {
+                unsafe { self.bits(variant.into()) }
+            }
+        }
+        impl<'a, REG, N, FI, const WI: u8, const OF: u8> FieldWriterSafe<'a, $U, REG, N, FI, WI, OF>
+        where
+            REG: Writable + RegisterSpec<Ux = $U>,
+            N: Into<$U>,
+            FI: Into<N>,
+        {
+            const MASK: $U = <$U>::MAX >> (<$U>::MAX.leading_ones() as u8 - { WI });
+            #[doc = " Writes raw bits to the field"]
+            #[inline(always)]
+            pub fn bits(self, value: N) -> &'a mut REG::Writer {
+                self.w.bits = (self.w.bits & !(Self::MASK << { OF }))
+                    | ((value.into() & Self::MASK) << { OF });
+                self.w
+            }
+            #[doc = " Writes `variant` to the field"]
+            #[inline(always)]
+            pub fn variant(self, variant: FI) -> &'a mut REG::Writer {
+                self.bits(variant.into())
+            }
+        }
+        impl_bit_proxy!(BitWriter, $U);
+        impl_bit_proxy!(BitWriter1S, $U);
+        impl_bit_proxy!(BitWriter0C, $U);
+        impl_bit_proxy!(BitWriter1C, $U);
+        impl_bit_proxy!(BitWriter0S, $U);
+        impl_bit_proxy!(BitWriter1T, $U);
+        impl_bit_proxy!(BitWriter0T, $U);
+        impl<'a, REG, FI, const OF: u8> BitWriter<'a, $U, REG, FI, OF>
+        where
+            REG: Writable + RegisterSpec<Ux = $U>,
+            FI: Into<bool>,
+        {
+            #[doc = " Sets the field bit"]
+            #[inline(always)]
+            pub fn set_bit(self) -> &'a mut REG::Writer {
+                self.bit(true)
+            }
+            #[doc = " Clears the field bit"]
+            #[inline(always)]
+            pub fn clear_bit(self) -> &'a mut REG::Writer {
+                self.bit(false)
+            }
+        }
+        impl<'a, REG, FI, const OF: u8> BitWriter1S<'a, $U, REG, FI, OF>
+        where
+            REG: Writable + RegisterSpec<Ux = $U>,
+            FI: Into<bool>,
+        {
+            #[doc = " Sets the field bit"]
+            #[inline(always)]
+            pub fn set_bit(self) -> &'a mut REG::Writer {
+                self.bit(true)
+            }
+        }
+        impl<'a, REG, FI, const OF: u8> BitWriter0C<'a, $U, REG, FI, OF>
+        where
+            REG: Writable + RegisterSpec<Ux = $U>,
+            FI: Into<bool>,
+        {
+            #[doc = " Clears the field bit"]
+            #[inline(always)]
+            pub fn clear_bit(self) -> &'a mut REG::Writer {
+                self.bit(false)
+            }
+        }
+        impl<'a, REG, FI, const OF: u8> BitWriter1C<'a, $U, REG, FI, OF>
+        where
+            REG: Writable + RegisterSpec<Ux = $U>,
+            FI: Into<bool>,
+        {
+            #[doc = "Clears the field bit by passing one"]
+            #[inline(always)]
+            pub fn clear_bit_by_one(self) -> &'a mut REG::Writer {
+                self.bit(true)
+            }
+        }
+        impl<'a, REG, FI, const OF: u8> BitWriter0S<'a, $U, REG, FI, OF>
+        where
+            REG: Writable + RegisterSpec<Ux = $U>,
+            FI: Into<bool>,
+        {
+            #[doc = "Sets the field bit by passing zero"]
+            #[inline(always)]
+            pub fn set_bit_by_zero(self) -> &'a mut REG::Writer {
+                self.bit(false)
+            }
+        }
+        impl<'a, REG, FI, const OF: u8> BitWriter1T<'a, $U, REG, FI, OF>
+        where
+            REG: Writable + RegisterSpec<Ux = $U>,
+            FI: Into<bool>,
+        {
+            #[doc = "Toggle the field bit by passing one"]
+            #[inline(always)]
+            pub fn toggle_bit(self) -> &'a mut REG::Writer {
+                self.bit(true)
+            }
+        }
+        impl<'a, REG, FI, const OF: u8> BitWriter0T<'a, $U, REG, FI, OF>
+        where
+            REG: Writable + RegisterSpec<Ux = $U>,
+            FI: Into<bool>,
+        {
+            #[doc = "Toggle the field bit by passing zero"]
+            #[inline(always)]
+            pub fn toggle_bit(self) -> &'a mut REG::Writer {
+                self.bit(false)
+            }
+        }
+    };
+}
+impl_proxy!(u32);

vendor/nrf9160-pac/src/gpiote0_s.rs

@@ -0,0 +1,96 @@
+#[doc = r"Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00..0x20 - Description collection: Task for writing to pin specified in CONFIG\\[n\\].PSEL. Action on pin is configured in CONFIG\\[n\\].POLARITY."]
+    pub tasks_out: [TASKS_OUT; 8],
+    _reserved1: [u8; 0x10],
+    #[doc = "0x30..0x50 - Description collection: Task for writing to pin specified in CONFIG\\[n\\].PSEL. Action on pin is to set it high."]
+    pub tasks_set: [TASKS_SET; 8],
+    _reserved2: [u8; 0x10],
+    #[doc = "0x60..0x80 - Description collection: Task for writing to pin specified in CONFIG\\[n\\].PSEL. Action on pin is to set it low."]
+    pub tasks_clr: [TASKS_CLR; 8],
+    #[doc = "0x80..0xa0 - Description collection: Subscribe configuration for task OUT\\[n\\]"]
+    pub subscribe_out: [SUBSCRIBE_OUT; 8],
+    _reserved4: [u8; 0x10],
+    #[doc = "0xb0..0xd0 - Description collection: Subscribe configuration for task SET\\[n\\]"]
+    pub subscribe_set: [SUBSCRIBE_SET; 8],
+    _reserved5: [u8; 0x10],
+    #[doc = "0xe0..0x100 - Description collection: Subscribe configuration for task CLR\\[n\\]"]
+    pub subscribe_clr: [SUBSCRIBE_CLR; 8],
+    #[doc = "0x100..0x120 - Description collection: Event generated from pin specified in CONFIG\\[n\\].PSEL"]
+    pub events_in: [EVENTS_IN; 8],
+    _reserved7: [u8; 0x5c],
+    #[doc = "0x17c - Event generated from multiple input GPIO pins with SENSE mechanism enabled"]
+    pub events_port: EVENTS_PORT,
+    #[doc = "0x180..0x1a0 - Description collection: Publish configuration for event IN\\[n\\]"]
+    pub publish_in: [PUBLISH_IN; 8],
+    _reserved9: [u8; 0x5c],
+    #[doc = "0x1fc - Publish configuration for event PORT"]
+    pub publish_port: PUBLISH_PORT,
+    _reserved10: [u8; 0x0104],
+    #[doc = "0x304 - Enable interrupt"]
+    pub intenset: INTENSET,
+    #[doc = "0x308 - Disable interrupt"]
+    pub intenclr: INTENCLR,
+    _reserved12: [u8; 0x0204],
+    #[doc = "0x510..0x530 - Description collection: Configuration for OUT\\[n\\], SET\\[n\\]
+and CLR\\[n\\]
+tasks and IN\\[n\\]
+event"]
+    pub config: [CONFIG; 8],
+}
+#[doc = "TASKS_OUT (w) register accessor: an alias for `Reg<TASKS_OUT_SPEC>`"]
+pub type TASKS_OUT = crate::Reg<tasks_out::TASKS_OUT_SPEC>;
+#[doc = "Description collection: Task for writing to pin specified in CONFIG\\[n\\].PSEL. Action on pin is configured in CONFIG\\[n\\].POLARITY."]
+pub mod tasks_out;
+#[doc = "TASKS_SET (w) register accessor: an alias for `Reg<TASKS_SET_SPEC>`"]
+pub type TASKS_SET = crate::Reg<tasks_set::TASKS_SET_SPEC>;
+#[doc = "Description collection: Task for writing to pin specified in CONFIG\\[n\\].PSEL. Action on pin is to set it high."]
+pub mod tasks_set;
+#[doc = "TASKS_CLR (w) register accessor: an alias for `Reg<TASKS_CLR_SPEC>`"]
+pub type TASKS_CLR = crate::Reg<tasks_clr::TASKS_CLR_SPEC>;
+#[doc = "Description collection: Task for writing to pin specified in CONFIG\\[n\\].PSEL. Action on pin is to set it low."]
+pub mod tasks_clr;
+#[doc = "SUBSCRIBE_OUT (rw) register accessor: an alias for `Reg<SUBSCRIBE_OUT_SPEC>`"]
+pub type SUBSCRIBE_OUT = crate::Reg<subscribe_out::SUBSCRIBE_OUT_SPEC>;
+#[doc = "Description collection: Subscribe configuration for task OUT\\[n\\]"]
+pub mod subscribe_out;
+#[doc = "SUBSCRIBE_SET (rw) register accessor: an alias for `Reg<SUBSCRIBE_SET_SPEC>`"]
+pub type SUBSCRIBE_SET = crate::Reg<subscribe_set::SUBSCRIBE_SET_SPEC>;
+#[doc = "Description collection: Subscribe configuration for task SET\\[n\\]"]
+pub mod subscribe_set;
+#[doc = "SUBSCRIBE_CLR (rw) register accessor: an alias for `Reg<SUBSCRIBE_CLR_SPEC>`"]
+pub type SUBSCRIBE_CLR = crate::Reg<subscribe_clr::SUBSCRIBE_CLR_SPEC>;
+#[doc = "Description collection: Subscribe configuration for task CLR\\[n\\]"]
+pub mod subscribe_clr;
+#[doc = "EVENTS_IN (rw) register accessor: an alias for `Reg<EVENTS_IN_SPEC>`"]
+pub type EVENTS_IN = crate::Reg<events_in::EVENTS_IN_SPEC>;
+#[doc = "Description collection: Event generated from pin specified in CONFIG\\[n\\].PSEL"]
+pub mod events_in;
+#[doc = "EVENTS_PORT (rw) register accessor: an alias for `Reg<EVENTS_PORT_SPEC>`"]
+pub type EVENTS_PORT = crate::Reg<events_port::EVENTS_PORT_SPEC>;
+#[doc = "Event generated from multiple input GPIO pins with SENSE mechanism enabled"]
+pub mod events_port;
+#[doc = "PUBLISH_IN (rw) register accessor: an alias for `Reg<PUBLISH_IN_SPEC>`"]
+pub type PUBLISH_IN = crate::Reg<publish_in::PUBLISH_IN_SPEC>;
+#[doc = "Description collection: Publish configuration for event IN\\[n\\]"]
+pub mod publish_in;
+#[doc = "PUBLISH_PORT (rw) register accessor: an alias for `Reg<PUBLISH_PORT_SPEC>`"]
+pub type PUBLISH_PORT = crate::Reg<publish_port::PUBLISH_PORT_SPEC>;
+#[doc = "Publish configuration for event PORT"]
+pub mod publish_port;
+#[doc = "INTENSET (rw) register accessor: an alias for `Reg<INTENSET_SPEC>`"]
+pub type INTENSET = crate::Reg<intenset::INTENSET_SPEC>;
+#[doc = "Enable interrupt"]
+pub mod intenset;
+#[doc = "INTENCLR (rw) register accessor: an alias for `Reg<INTENCLR_SPEC>`"]
+pub type INTENCLR = crate::Reg<intenclr::INTENCLR_SPEC>;
+#[doc = "Disable interrupt"]
+pub mod intenclr;
+#[doc = "CONFIG (rw) register accessor: an alias for `Reg<CONFIG_SPEC>`"]
+pub type CONFIG = crate::Reg<config::CONFIG_SPEC>;
+#[doc = "Description collection: Configuration for OUT\\[n\\], SET\\[n\\]
+and CLR\\[n\\]
+tasks and IN\\[n\\]
+event"]
+pub mod config;

vendor/nrf9160-pac/src/gpiote0_s/config.rs

@@ -0,0 +1,344 @@
+#[doc = "Register `CONFIG[%s]` reader"]
+pub struct R(crate::R<CONFIG_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<CONFIG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<CONFIG_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<CONFIG_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `CONFIG[%s]` writer"]
+pub struct W(crate::W<CONFIG_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<CONFIG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<CONFIG_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<CONFIG_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `MODE` reader - Mode"]
+pub type MODE_R = crate::FieldReader<u8, MODE_A>;
+#[doc = "Mode\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum MODE_A {
+    #[doc = "0: Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module."]
+    DISABLED = 0,
+    #[doc = "1: Event mode"]
+    EVENT = 1,
+    #[doc = "3: Task mode"]
+    TASK = 3,
+}
+impl From<MODE_A> for u8 {
+    #[inline(always)]
+    fn from(variant: MODE_A) -> Self {
+        variant as _
+    }
+}
+impl MODE_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<MODE_A> {
+        match self.bits {
+            0 => Some(MODE_A::DISABLED),
+            1 => Some(MODE_A::EVENT),
+            3 => Some(MODE_A::TASK),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == MODE_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `EVENT`"]
+    #[inline(always)]
+    pub fn is_event(&self) -> bool {
+        *self == MODE_A::EVENT
+    }
+    #[doc = "Checks if the value of the field is `TASK`"]
+    #[inline(always)]
+    pub fn is_task(&self) -> bool {
+        *self == MODE_A::TASK
+    }
+}
+#[doc = "Field `MODE` writer - Mode"]
+pub type MODE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CONFIG_SPEC, u8, MODE_A, 2, O>;
+impl<'a, const O: u8> MODE_W<'a, O> {
+    #[doc = "Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module."]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(MODE_A::DISABLED)
+    }
+    #[doc = "Event mode"]
+    #[inline(always)]
+    pub fn event(self) -> &'a mut W {
+        self.variant(MODE_A::EVENT)
+    }
+    #[doc = "Task mode"]
+    #[inline(always)]
+    pub fn task(self) -> &'a mut W {
+        self.variant(MODE_A::TASK)
+    }
+}
+#[doc = "Field `PSEL` reader - GPIO number associated with SET\\[n\\], CLR\\[n\\]
+and OUT\\[n\\]
+tasks and IN\\[n\\]
+event"]
+pub type PSEL_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `PSEL` writer - GPIO number associated with SET\\[n\\], CLR\\[n\\]
+and OUT\\[n\\]
+tasks and IN\\[n\\]
+event"]
+pub type PSEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CONFIG_SPEC, u8, u8, 5, O>;
+#[doc = "Field `POLARITY` reader - When In task mode: Operation to be performed on output when OUT\\[n\\]
+task is triggered. When In event mode: Operation on input that shall trigger IN\\[n\\]
+event."]
+pub type POLARITY_R = crate::FieldReader<u8, POLARITY_A>;
+#[doc = "When In task mode: Operation to be performed on output when OUT\\[n\\]
+task is triggered. When In event mode: Operation on input that shall trigger IN\\[n\\]
+event.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum POLARITY_A {
+    #[doc = "0: Task mode: No effect on pin from OUT\\[n\\]
+task. Event mode: no IN\\[n\\]
+event generated on pin activity."]
+    NONE = 0,
+    #[doc = "1: Task mode: Set pin from OUT\\[n\\]
+task. Event mode: Generate IN\\[n\\]
+event when rising edge on pin."]
+    LO_TO_HI = 1,
+    #[doc = "2: Task mode: Clear pin from OUT\\[n\\]
+task. Event mode: Generate IN\\[n\\]
+event when falling edge on pin."]
+    HI_TO_LO = 2,
+    #[doc = "3: Task mode: Toggle pin from OUT\\[n\\]. Event mode: Generate IN\\[n\\]
+when any change on pin."]
+    TOGGLE = 3,
+}
+impl From<POLARITY_A> for u8 {
+    #[inline(always)]
+    fn from(variant: POLARITY_A) -> Self {
+        variant as _
+    }
+}
+impl POLARITY_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> POLARITY_A {
+        match self.bits {
+            0 => POLARITY_A::NONE,
+            1 => POLARITY_A::LO_TO_HI,
+            2 => POLARITY_A::HI_TO_LO,
+            3 => POLARITY_A::TOGGLE,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `NONE`"]
+    #[inline(always)]
+    pub fn is_none(&self) -> bool {
+        *self == POLARITY_A::NONE
+    }
+    #[doc = "Checks if the value of the field is `LO_TO_HI`"]
+    #[inline(always)]
+    pub fn is_lo_to_hi(&self) -> bool {
+        *self == POLARITY_A::LO_TO_HI
+    }
+    #[doc = "Checks if the value of the field is `HI_TO_LO`"]
+    #[inline(always)]
+    pub fn is_hi_to_lo(&self) -> bool {
+        *self == POLARITY_A::HI_TO_LO
+    }
+    #[doc = "Checks if the value of the field is `TOGGLE`"]
+    #[inline(always)]
+    pub fn is_toggle(&self) -> bool {
+        *self == POLARITY_A::TOGGLE
+    }
+}
+#[doc = "Field `POLARITY` writer - When In task mode: Operation to be performed on output when OUT\\[n\\]
+task is triggered. When In event mode: Operation on input that shall trigger IN\\[n\\]
+event."]
+pub type POLARITY_W<'a, const O: u8> =
+    crate::FieldWriterSafe<'a, u32, CONFIG_SPEC, u8, POLARITY_A, 2, O>;
+impl<'a, const O: u8> POLARITY_W<'a, O> {
+    #[doc = "Task mode: No effect on pin from OUT\\[n\\]
+task. Event mode: no IN\\[n\\]
+event generated on pin activity."]
+    #[inline(always)]
+    pub fn none(self) -> &'a mut W {
+        self.variant(POLARITY_A::NONE)
+    }
+    #[doc = "Task mode: Set pin from OUT\\[n\\]
+task. Event mode: Generate IN\\[n\\]
+event when rising edge on pin."]
+    #[inline(always)]
+    pub fn lo_to_hi(self) -> &'a mut W {
+        self.variant(POLARITY_A::LO_TO_HI)
+    }
+    #[doc = "Task mode: Clear pin from OUT\\[n\\]
+task. Event mode: Generate IN\\[n\\]
+event when falling edge on pin."]
+    #[inline(always)]
+    pub fn hi_to_lo(self) -> &'a mut W {
+        self.variant(POLARITY_A::HI_TO_LO)
+    }
+    #[doc = "Task mode: Toggle pin from OUT\\[n\\]. Event mode: Generate IN\\[n\\]
+when any change on pin."]
+    #[inline(always)]
+    pub fn toggle(self) -> &'a mut W {
+        self.variant(POLARITY_A::TOGGLE)
+    }
+}
+#[doc = "Field `OUTINIT` reader - When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect."]
+pub type OUTINIT_R = crate::BitReader<OUTINIT_A>;
+#[doc = "When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum OUTINIT_A {
+    #[doc = "0: Task mode: Initial value of pin before task triggering is low"]
+    LOW = 0,
+    #[doc = "1: Task mode: Initial value of pin before task triggering is high"]
+    HIGH = 1,
+}
+impl From<OUTINIT_A> for bool {
+    #[inline(always)]
+    fn from(variant: OUTINIT_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl OUTINIT_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> OUTINIT_A {
+        match self.bits {
+            false => OUTINIT_A::LOW,
+            true => OUTINIT_A::HIGH,
+        }
+    }
+    #[doc = "Checks if the value of the field is `LOW`"]
+    #[inline(always)]
+    pub fn is_low(&self) -> bool {
+        *self == OUTINIT_A::LOW
+    }
+    #[doc = "Checks if the value of the field is `HIGH`"]
+    #[inline(always)]
+    pub fn is_high(&self) -> bool {
+        *self == OUTINIT_A::HIGH
+    }
+}
+#[doc = "Field `OUTINIT` writer - When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect."]
+pub type OUTINIT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONFIG_SPEC, OUTINIT_A, O>;
+impl<'a, const O: u8> OUTINIT_W<'a, O> {
+    #[doc = "Task mode: Initial value of pin before task triggering is low"]
+    #[inline(always)]
+    pub fn low(self) -> &'a mut W {
+        self.variant(OUTINIT_A::LOW)
+    }
+    #[doc = "Task mode: Initial value of pin before task triggering is high"]
+    #[inline(always)]
+    pub fn high(self) -> &'a mut W {
+        self.variant(OUTINIT_A::HIGH)
+    }
+}
+impl R {
+    #[doc = "Bits 0:1 - Mode"]
+    #[inline(always)]
+    pub fn mode(&self) -> MODE_R {
+        MODE_R::new((self.bits & 3) as u8)
+    }
+    #[doc = "Bits 8:12 - GPIO number associated with SET\\[n\\], CLR\\[n\\]
+and OUT\\[n\\]
+tasks and IN\\[n\\]
+event"]
+    #[inline(always)]
+    pub fn psel(&self) -> PSEL_R {
+        PSEL_R::new(((self.bits >> 8) & 0x1f) as u8)
+    }
+    #[doc = "Bits 16:17 - When In task mode: Operation to be performed on output when OUT\\[n\\]
+task is triggered. When In event mode: Operation on input that shall trigger IN\\[n\\]
+event."]
+    #[inline(always)]
+    pub fn polarity(&self) -> POLARITY_R {
+        POLARITY_R::new(((self.bits >> 16) & 3) as u8)
+    }
+    #[doc = "Bit 20 - When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect."]
+    #[inline(always)]
+    pub fn outinit(&self) -> OUTINIT_R {
+        OUTINIT_R::new(((self.bits >> 20) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:1 - Mode"]
+    #[inline(always)]
+    pub fn mode(&mut self) -> MODE_W<0> {
+        MODE_W::new(self)
+    }
+    #[doc = "Bits 8:12 - GPIO number associated with SET\\[n\\], CLR\\[n\\]
+and OUT\\[n\\]
+tasks and IN\\[n\\]
+event"]
+    #[inline(always)]
+    pub fn psel(&mut self) -> PSEL_W<8> {
+        PSEL_W::new(self)
+    }
+    #[doc = "Bits 16:17 - When In task mode: Operation to be performed on output when OUT\\[n\\]
+task is triggered. When In event mode: Operation on input that shall trigger IN\\[n\\]
+event."]
+    #[inline(always)]
+    pub fn polarity(&mut self) -> POLARITY_W<16> {
+        POLARITY_W::new(self)
+    }
+    #[doc = "Bit 20 - When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect."]
+    #[inline(always)]
+    pub fn outinit(&mut self) -> OUTINIT_W<20> {
+        OUTINIT_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Description collection: Configuration for OUT\\[n\\], SET\\[n\\]
+and CLR\\[n\\]
+tasks and IN\\[n\\]
+event\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [config](index.html) module"]
+pub struct CONFIG_SPEC;
+impl crate::RegisterSpec for CONFIG_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [config::R](R) reader structure"]
+impl crate::Readable for CONFIG_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [config::W](W) writer structure"]
+impl crate::Writable for CONFIG_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets CONFIG[%s]
+to value 0"]
+impl crate::Resettable for CONFIG_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9160-pac/src/gpiote0_s/events_in.rs

@@ -0,0 +1,127 @@
+#[doc = "Register `EVENTS_IN[%s]` reader"]
+pub struct R(crate::R<EVENTS_IN_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<EVENTS_IN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<EVENTS_IN_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<EVENTS_IN_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `EVENTS_IN[%s]` writer"]
+pub struct W(crate::W<EVENTS_IN_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<EVENTS_IN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<EVENTS_IN_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<EVENTS_IN_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `EVENTS_IN` reader - Event generated from pin specified in CONFIG\\[n\\].PSEL"]
+pub type EVENTS_IN_R = crate::BitReader<EVENTS_IN_A>;
+#[doc = "Event generated from pin specified in CONFIG\\[n\\].PSEL\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum EVENTS_IN_A {
+    #[doc = "0: Event not generated"]
+    NOT_GENERATED = 0,
+    #[doc = "1: Event generated"]
+    GENERATED = 1,
+}
+impl From<EVENTS_IN_A> for bool {
+    #[inline(always)]
+    fn from(variant: EVENTS_IN_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl EVENTS_IN_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> EVENTS_IN_A {
+        match self.bits {
+            false => EVENTS_IN_A::NOT_GENERATED,
+            true => EVENTS_IN_A::GENERATED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `NOT_GENERATED`"]
+    #[inline(always)]
+    pub fn is_not_generated(&self) -> bool {
+        *self == EVENTS_IN_A::NOT_GENERATED
+    }
+    #[doc = "Checks if the value of the field is `GENERATED`"]
+    #[inline(always)]
+    pub fn is_generated(&self) -> bool {
+        *self == EVENTS_IN_A::GENERATED
+    }
+}
+#[doc = "Field `EVENTS_IN` writer - Event generated from pin specified in CONFIG\\[n\\].PSEL"]
+pub type EVENTS_IN_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVENTS_IN_SPEC, EVENTS_IN_A, O>;
+impl<'a, const O: u8> EVENTS_IN_W<'a, O> {
+    #[doc = "Event not generated"]
+    #[inline(always)]
+    pub fn not_generated(self) -> &'a mut W {
+        self.variant(EVENTS_IN_A::NOT_GENERATED)
+    }
+    #[doc = "Event generated"]
+    #[inline(always)]
+    pub fn generated(self) -> &'a mut W {
+        self.variant(EVENTS_IN_A::GENERATED)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Event generated from pin specified in CONFIG\\[n\\].PSEL"]
+    #[inline(always)]
+    pub fn events_in(&self) -> EVENTS_IN_R {
+        EVENTS_IN_R::new((self.bits & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Event generated from pin specified in CONFIG\\[n\\].PSEL"]
+    #[inline(always)]
+    pub fn events_in(&mut self) -> EVENTS_IN_W<0> {
+        EVENTS_IN_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Description collection: Event generated from pin specified in CONFIG\\[n\\].PSEL\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_in](index.html) module"]
+pub struct EVENTS_IN_SPEC;
+impl crate::RegisterSpec for EVENTS_IN_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [events_in::R](R) reader structure"]
+impl crate::Readable for EVENTS_IN_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [events_in::W](W) writer structure"]
+impl crate::Writable for EVENTS_IN_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets EVENTS_IN[%s]
+to value 0"]
+impl crate::Resettable for EVENTS_IN_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9160-pac/src/gpiote0_s/events_port.rs

@@ -0,0 +1,127 @@
+#[doc = "Register `EVENTS_PORT` reader"]
+pub struct R(crate::R<EVENTS_PORT_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<EVENTS_PORT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<EVENTS_PORT_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<EVENTS_PORT_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `EVENTS_PORT` writer"]
+pub struct W(crate::W<EVENTS_PORT_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<EVENTS_PORT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<EVENTS_PORT_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<EVENTS_PORT_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `EVENTS_PORT` reader - Event generated from multiple input GPIO pins with SENSE mechanism enabled"]
+pub type EVENTS_PORT_R = crate::BitReader<EVENTS_PORT_A>;
+#[doc = "Event generated from multiple input GPIO pins with SENSE mechanism enabled\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum EVENTS_PORT_A {
+    #[doc = "0: Event not generated"]
+    NOT_GENERATED = 0,
+    #[doc = "1: Event generated"]
+    GENERATED = 1,
+}
+impl From<EVENTS_PORT_A> for bool {
+    #[inline(always)]
+    fn from(variant: EVENTS_PORT_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl EVENTS_PORT_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> EVENTS_PORT_A {
+        match self.bits {
+            false => EVENTS_PORT_A::NOT_GENERATED,
+            true => EVENTS_PORT_A::GENERATED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `NOT_GENERATED`"]
+    #[inline(always)]
+    pub fn is_not_generated(&self) -> bool {
+        *self == EVENTS_PORT_A::NOT_GENERATED
+    }
+    #[doc = "Checks if the value of the field is `GENERATED`"]
+    #[inline(always)]
+    pub fn is_generated(&self) -> bool {
+        *self == EVENTS_PORT_A::GENERATED
+    }
+}
+#[doc = "Field `EVENTS_PORT` writer - Event generated from multiple input GPIO pins with SENSE mechanism enabled"]
+pub type EVENTS_PORT_W<'a, const O: u8> =
+    crate::BitWriter<'a, u32, EVENTS_PORT_SPEC, EVENTS_PORT_A, O>;
+impl<'a, const O: u8> EVENTS_PORT_W<'a, O> {
+    #[doc = "Event not generated"]
+    #[inline(always)]
+    pub fn not_generated(self) -> &'a mut W {
+        self.variant(EVENTS_PORT_A::NOT_GENERATED)
+    }
+    #[doc = "Event generated"]
+    #[inline(always)]
+    pub fn generated(self) -> &'a mut W {
+        self.variant(EVENTS_PORT_A::GENERATED)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Event generated from multiple input GPIO pins with SENSE mechanism enabled"]
+    #[inline(always)]
+    pub fn events_port(&self) -> EVENTS_PORT_R {
+        EVENTS_PORT_R::new((self.bits & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Event generated from multiple input GPIO pins with SENSE mechanism enabled"]
+    #[inline(always)]
+    pub fn events_port(&mut self) -> EVENTS_PORT_W<0> {
+        EVENTS_PORT_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Event generated from multiple input GPIO pins with SENSE mechanism enabled\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [events_port](index.html) module"]
+pub struct EVENTS_PORT_SPEC;
+impl crate::RegisterSpec for EVENTS_PORT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [events_port::R](R) reader structure"]
+impl crate::Readable for EVENTS_PORT_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [events_port::W](W) writer structure"]
+impl crate::Writable for EVENTS_PORT_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets EVENTS_PORT to value 0"]
+impl crate::Resettable for EVENTS_PORT_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9160-pac/src/gpiote0_s/intenclr.rs

@@ -0,0 +1,669 @@
+#[doc = "Register `INTENCLR` reader"]
+pub struct R(crate::R<INTENCLR_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<INTENCLR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<INTENCLR_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<INTENCLR_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `INTENCLR` writer"]
+pub struct W(crate::W<INTENCLR_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<INTENCLR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<INTENCLR_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<INTENCLR_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `IN0` reader - Write '1' to disable interrupt for event IN\\[0\\]"]
+pub type IN0_R = crate::BitReader<IN0_A>;
+#[doc = "Write '1' to disable interrupt for event IN\\[0\\]\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum IN0_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<IN0_A> for bool {
+    #[inline(always)]
+    fn from(variant: IN0_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl IN0_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> IN0_A {
+        match self.bits {
+            false => IN0_A::DISABLED,
+            true => IN0_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == IN0_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == IN0_A::ENABLED
+    }
+}
+#[doc = "Write '1' to disable interrupt for event IN\\[0\\]\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum IN0_AW {
+    #[doc = "1: Disable"]
+    CLEAR = 1,
+}
+impl From<IN0_AW> for bool {
+    #[inline(always)]
+    fn from(variant: IN0_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `IN0` writer - Write '1' to disable interrupt for event IN\\[0\\]"]
+pub type IN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, IN0_AW, O>;
+impl<'a, const O: u8> IN0_W<'a, O> {
+    #[doc = "Disable"]
+    #[inline(always)]
+    pub fn clear(self) -> &'a mut W {
+        self.variant(IN0_AW::CLEAR)
+    }
+}
+#[doc = "Field `IN1` reader - Write '1' to disable interrupt for event IN\\[1\\]"]
+pub type IN1_R = crate::BitReader<IN1_A>;
+#[doc = "Write '1' to disable interrupt for event IN\\[1\\]\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum IN1_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<IN1_A> for bool {
+    #[inline(always)]
+    fn from(variant: IN1_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl IN1_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> IN1_A {
+        match self.bits {
+            false => IN1_A::DISABLED,
+            true => IN1_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == IN1_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == IN1_A::ENABLED
+    }
+}
+#[doc = "Write '1' to disable interrupt for event IN\\[1\\]\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum IN1_AW {
+    #[doc = "1: Disable"]
+    CLEAR = 1,
+}
+impl From<IN1_AW> for bool {
+    #[inline(always)]
+    fn from(variant: IN1_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `IN1` writer - Write '1' to disable interrupt for event IN\\[1\\]"]
+pub type IN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, IN1_AW, O>;
+impl<'a, const O: u8> IN1_W<'a, O> {
+    #[doc = "Disable"]
+    #[inline(always)]
+    pub fn clear(self) -> &'a mut W {
+        self.variant(IN1_AW::CLEAR)
+    }
+}
+#[doc = "Field `IN2` reader - Write '1' to disable interrupt for event IN\\[2\\]"]
+pub type IN2_R = crate::BitReader<IN2_A>;
+#[doc = "Write '1' to disable interrupt for event IN\\[2\\]\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum IN2_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<IN2_A> for bool {
+    #[inline(always)]
+    fn from(variant: IN2_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl IN2_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> IN2_A {
+        match self.bits {
+            false => IN2_A::DISABLED,
+            true => IN2_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == IN2_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == IN2_A::ENABLED
+    }
+}
+#[doc = "Write '1' to disable interrupt for event IN\\[2\\]\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum IN2_AW {
+    #[doc = "1: Disable"]
+    CLEAR = 1,
+}
+impl From<IN2_AW> for bool {
+    #[inline(always)]
+    fn from(variant: IN2_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `IN2` writer - Write '1' to disable interrupt for event IN\\[2\\]"]
+pub type IN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, IN2_AW, O>;
+impl<'a, const O: u8> IN2_W<'a, O> {
+    #[doc = "Disable"]
+    #[inline(always)]
+    pub fn clear(self) -> &'a mut W {
+        self.variant(IN2_AW::CLEAR)
+    }
+}
+#[doc = "Field `IN3` reader - Write '1' to disable interrupt for event IN\\[3\\]"]
+pub type IN3_R = crate::BitReader<IN3_A>;
+#[doc = "Write '1' to disable interrupt for event IN\\[3\\]\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum IN3_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<IN3_A> for bool {
+    #[inline(always)]
+    fn from(variant: IN3_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl IN3_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> IN3_A {
+        match self.bits {
+            false => IN3_A::DISABLED,
+            true => IN3_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == IN3_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == IN3_A::ENABLED
+    }
+}
+#[doc = "Write '1' to disable interrupt for event IN\\[3\\]\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum IN3_AW {
+    #[doc = "1: Disable"]
+    CLEAR = 1,
+}
+impl From<IN3_AW> for bool {
+    #[inline(always)]
+    fn from(variant: IN3_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `IN3` writer - Write '1' to disable interrupt for event IN\\[3\\]"]
+pub type IN3_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, IN3_AW, O>;
+impl<'a, const O: u8> IN3_W<'a, O> {
+    #[doc = "Disable"]
+    #[inline(always)]
+    pub fn clear(self) -> &'a mut W {
+        self.variant(IN3_AW::CLEAR)
+    }
+}
+#[doc = "Field `IN4` reader - Write '1' to disable interrupt for event IN\\[4\\]"]
+pub type IN4_R = crate::BitReader<IN4_A>;
+#[doc = "Write '1' to disable interrupt for event IN\\[4\\]\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum IN4_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<IN4_A> for bool {
+    #[inline(always)]
+    fn from(variant: IN4_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl IN4_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> IN4_A {
+        match self.bits {
+            false => IN4_A::DISABLED,
+            true => IN4_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == IN4_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == IN4_A::ENABLED
+    }
+}
+#[doc = "Write '1' to disable interrupt for event IN\\[4\\]\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum IN4_AW {
+    #[doc = "1: Disable"]
+    CLEAR = 1,
+}
+impl From<IN4_AW> for bool {
+    #[inline(always)]
+    fn from(variant: IN4_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `IN4` writer - Write '1' to disable interrupt for event IN\\[4\\]"]
+pub type IN4_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, IN4_AW, O>;
+impl<'a, const O: u8> IN4_W<'a, O> {
+    #[doc = "Disable"]
+    #[inline(always)]
+    pub fn clear(self) -> &'a mut W {
+        self.variant(IN4_AW::CLEAR)
+    }
+}
+#[doc = "Field `IN5` reader - Write '1' to disable interrupt for event IN\\[5\\]"]
+pub type IN5_R = crate::BitReader<IN5_A>;
+#[doc = "Write '1' to disable interrupt for event IN\\[5\\]\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum IN5_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<IN5_A> for bool {
+    #[inline(always)]
+    fn from(variant: IN5_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl IN5_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> IN5_A {
+        match self.bits {
+            false => IN5_A::DISABLED,
+            true => IN5_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == IN5_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == IN5_A::ENABLED
+    }
+}
+#[doc = "Write '1' to disable interrupt for event IN\\[5\\]\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum IN5_AW {
+    #[doc = "1: Disable"]
+    CLEAR = 1,
+}
+impl From<IN5_AW> for bool {
+    #[inline(always)]
+    fn from(variant: IN5_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `IN5` writer - Write '1' to disable interrupt for event IN\\[5\\]"]
+pub type IN5_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, IN5_AW, O>;
+impl<'a, const O: u8> IN5_W<'a, O> {
+    #[doc = "Disable"]
+    #[inline(always)]
+    pub fn clear(self) -> &'a mut W {
+        self.variant(IN5_AW::CLEAR)
+    }
+}
+#[doc = "Field `IN6` reader - Write '1' to disable interrupt for event IN\\[6\\]"]
+pub type IN6_R = crate::BitReader<IN6_A>;
+#[doc = "Write '1' to disable interrupt for event IN\\[6\\]\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum IN6_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<IN6_A> for bool {
+    #[inline(always)]
+    fn from(variant: IN6_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl IN6_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> IN6_A {
+        match self.bits {
+            false => IN6_A::DISABLED,
+            true => IN6_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == IN6_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == IN6_A::ENABLED
+    }
+}
+#[doc = "Write '1' to disable interrupt for event IN\\[6\\]\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum IN6_AW {
+    #[doc = "1: Disable"]
+    CLEAR = 1,
+}
+impl From<IN6_AW> for bool {
+    #[inline(always)]
+    fn from(variant: IN6_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `IN6` writer - Write '1' to disable interrupt for event IN\\[6\\]"]
+pub type IN6_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, IN6_AW, O>;
+impl<'a, const O: u8> IN6_W<'a, O> {
+    #[doc = "Disable"]
+    #[inline(always)]
+    pub fn clear(self) -> &'a mut W {
+        self.variant(IN6_AW::CLEAR)
+    }
+}
+#[doc = "Field `IN7` reader - Write '1' to disable interrupt for event IN\\[7\\]"]
+pub type IN7_R = crate::BitReader<IN7_A>;
+#[doc = "Write '1' to disable interrupt for event IN\\[7\\]\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum IN7_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<IN7_A> for bool {
+    #[inline(always)]
+    fn from(variant: IN7_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl IN7_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> IN7_A {
+        match self.bits {
+            false => IN7_A::DISABLED,
+            true => IN7_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == IN7_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == IN7_A::ENABLED
+    }
+}
+#[doc = "Write '1' to disable interrupt for event IN\\[7\\]\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum IN7_AW {
+    #[doc = "1: Disable"]
+    CLEAR = 1,
+}
+impl From<IN7_AW> for bool {
+    #[inline(always)]
+    fn from(variant: IN7_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `IN7` writer - Write '1' to disable interrupt for event IN\\[7\\]"]
+pub type IN7_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, IN7_AW, O>;
+impl<'a, const O: u8> IN7_W<'a, O> {
+    #[doc = "Disable"]
+    #[inline(always)]
+    pub fn clear(self) -> &'a mut W {
+        self.variant(IN7_AW::CLEAR)
+    }
+}
+#[doc = "Field `PORT` reader - Write '1' to disable interrupt for event PORT"]
+pub type PORT_R = crate::BitReader<PORT_A>;
+#[doc = "Write '1' to disable interrupt for event PORT\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum PORT_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<PORT_A> for bool {
+    #[inline(always)]
+    fn from(variant: PORT_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl PORT_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> PORT_A {
+        match self.bits {
+            false => PORT_A::DISABLED,
+            true => PORT_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == PORT_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == PORT_A::ENABLED
+    }
+}
+#[doc = "Write '1' to disable interrupt for event PORT\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum PORT_AW {
+    #[doc = "1: Disable"]
+    CLEAR = 1,
+}
+impl From<PORT_AW> for bool {
+    #[inline(always)]
+    fn from(variant: PORT_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `PORT` writer - Write '1' to disable interrupt for event PORT"]
+pub type PORT_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, PORT_AW, O>;
+impl<'a, const O: u8> PORT_W<'a, O> {
+    #[doc = "Disable"]
+    #[inline(always)]
+    pub fn clear(self) -> &'a mut W {
+        self.variant(PORT_AW::CLEAR)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Write '1' to disable interrupt for event IN\\[0\\]"]
+    #[inline(always)]
+    pub fn in0(&self) -> IN0_R {
+        IN0_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Write '1' to disable interrupt for event IN\\[1\\]"]
+    #[inline(always)]
+    pub fn in1(&self) -> IN1_R {
+        IN1_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Write '1' to disable interrupt for event IN\\[2\\]"]
+    #[inline(always)]
+    pub fn in2(&self) -> IN2_R {
+        IN2_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Write '1' to disable interrupt for event IN\\[3\\]"]
+    #[inline(always)]
+    pub fn in3(&self) -> IN3_R {
+        IN3_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Write '1' to disable interrupt for event IN\\[4\\]"]
+    #[inline(always)]
+    pub fn in4(&self) -> IN4_R {
+        IN4_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - Write '1' to disable interrupt for event IN\\[5\\]"]
+    #[inline(always)]
+    pub fn in5(&self) -> IN5_R {
+        IN5_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - Write '1' to disable interrupt for event IN\\[6\\]"]
+    #[inline(always)]
+    pub fn in6(&self) -> IN6_R {
+        IN6_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - Write '1' to disable interrupt for event IN\\[7\\]"]
+    #[inline(always)]
+    pub fn in7(&self) -> IN7_R {
+        IN7_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 31 - Write '1' to disable interrupt for event PORT"]
+    #[inline(always)]
+    pub fn port(&self) -> PORT_R {
+        PORT_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Write '1' to disable interrupt for event IN\\[0\\]"]
+    #[inline(always)]
+    pub fn in0(&mut self) -> IN0_W<0> {
+        IN0_W::new(self)
+    }
+    #[doc = "Bit 1 - Write '1' to disable interrupt for event IN\\[1\\]"]
+    #[inline(always)]
+    pub fn in1(&mut self) -> IN1_W<1> {
+        IN1_W::new(self)
+    }
+    #[doc = "Bit 2 - Write '1' to disable interrupt for event IN\\[2\\]"]
+    #[inline(always)]
+    pub fn in2(&mut self) -> IN2_W<2> {
+        IN2_W::new(self)
+    }
+    #[doc = "Bit 3 - Write '1' to disable interrupt for event IN\\[3\\]"]
+    #[inline(always)]
+    pub fn in3(&mut self) -> IN3_W<3> {
+        IN3_W::new(self)
+    }
+    #[doc = "Bit 4 - Write '1' to disable interrupt for event IN\\[4\\]"]
+    #[inline(always)]
+    pub fn in4(&mut self) -> IN4_W<4> {
+        IN4_W::new(self)
+    }
+    #[doc = "Bit 5 - Write '1' to disable interrupt for event IN\\[5\\]"]
+    #[inline(always)]
+    pub fn in5(&mut self) -> IN5_W<5> {
+        IN5_W::new(self)
+    }
+    #[doc = "Bit 6 - Write '1' to disable interrupt for event IN\\[6\\]"]
+    #[inline(always)]
+    pub fn in6(&mut self) -> IN6_W<6> {
+        IN6_W::new(self)
+    }
+    #[doc = "Bit 7 - Write '1' to disable interrupt for event IN\\[7\\]"]
+    #[inline(always)]
+    pub fn in7(&mut self) -> IN7_W<7> {
+        IN7_W::new(self)
+    }
+    #[doc = "Bit 31 - Write '1' to disable interrupt for event PORT"]
+    #[inline(always)]
+    pub fn port(&mut self) -> PORT_W<31> {
+        PORT_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Disable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"]
+pub struct INTENCLR_SPEC;
+impl crate::RegisterSpec for INTENCLR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [intenclr::R](R) reader structure"]
+impl crate::Readable for INTENCLR_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"]
+impl crate::Writable for INTENCLR_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets INTENCLR to value 0"]
+impl crate::Resettable for INTENCLR_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9160-pac/src/gpiote0_s/intenset.rs

@@ -0,0 +1,669 @@
+#[doc = "Register `INTENSET` reader"]
+pub struct R(crate::R<INTENSET_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<INTENSET_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<INTENSET_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<INTENSET_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `INTENSET` writer"]
+pub struct W(crate::W<INTENSET_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<INTENSET_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<INTENSET_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<INTENSET_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `IN0` reader - Write '1' to enable interrupt for event IN\\[0\\]"]
+pub type IN0_R = crate::BitReader<IN0_A>;
+#[doc = "Write '1' to enable interrupt for event IN\\[0\\]\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum IN0_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<IN0_A> for bool {
+    #[inline(always)]
+    fn from(variant: IN0_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl IN0_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> IN0_A {
+        match self.bits {
+            false => IN0_A::DISABLED,
+            true => IN0_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == IN0_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == IN0_A::ENABLED
+    }
+}
+#[doc = "Write '1' to enable interrupt for event IN\\[0\\]\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum IN0_AW {
+    #[doc = "1: Enable"]
+    SET = 1,
+}
+impl From<IN0_AW> for bool {
+    #[inline(always)]
+    fn from(variant: IN0_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `IN0` writer - Write '1' to enable interrupt for event IN\\[0\\]"]
+pub type IN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, IN0_AW, O>;
+impl<'a, const O: u8> IN0_W<'a, O> {
+    #[doc = "Enable"]
+    #[inline(always)]
+    pub fn set(self) -> &'a mut W {
+        self.variant(IN0_AW::SET)
+    }
+}
+#[doc = "Field `IN1` reader - Write '1' to enable interrupt for event IN\\[1\\]"]
+pub type IN1_R = crate::BitReader<IN1_A>;
+#[doc = "Write '1' to enable interrupt for event IN\\[1\\]\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum IN1_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<IN1_A> for bool {
+    #[inline(always)]
+    fn from(variant: IN1_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl IN1_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> IN1_A {
+        match self.bits {
+            false => IN1_A::DISABLED,
+            true => IN1_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == IN1_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == IN1_A::ENABLED
+    }
+}
+#[doc = "Write '1' to enable interrupt for event IN\\[1\\]\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum IN1_AW {
+    #[doc = "1: Enable"]
+    SET = 1,
+}
+impl From<IN1_AW> for bool {
+    #[inline(always)]
+    fn from(variant: IN1_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `IN1` writer - Write '1' to enable interrupt for event IN\\[1\\]"]
+pub type IN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, IN1_AW, O>;
+impl<'a, const O: u8> IN1_W<'a, O> {
+    #[doc = "Enable"]
+    #[inline(always)]
+    pub fn set(self) -> &'a mut W {
+        self.variant(IN1_AW::SET)
+    }
+}
+#[doc = "Field `IN2` reader - Write '1' to enable interrupt for event IN\\[2\\]"]
+pub type IN2_R = crate::BitReader<IN2_A>;
+#[doc = "Write '1' to enable interrupt for event IN\\[2\\]\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum IN2_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<IN2_A> for bool {
+    #[inline(always)]
+    fn from(variant: IN2_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl IN2_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> IN2_A {
+        match self.bits {
+            false => IN2_A::DISABLED,
+            true => IN2_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == IN2_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == IN2_A::ENABLED
+    }
+}
+#[doc = "Write '1' to enable interrupt for event IN\\[2\\]\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum IN2_AW {
+    #[doc = "1: Enable"]
+    SET = 1,
+}
+impl From<IN2_AW> for bool {
+    #[inline(always)]
+    fn from(variant: IN2_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `IN2` writer - Write '1' to enable interrupt for event IN\\[2\\]"]
+pub type IN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, IN2_AW, O>;
+impl<'a, const O: u8> IN2_W<'a, O> {
+    #[doc = "Enable"]
+    #[inline(always)]
+    pub fn set(self) -> &'a mut W {
+        self.variant(IN2_AW::SET)
+    }
+}
+#[doc = "Field `IN3` reader - Write '1' to enable interrupt for event IN\\[3\\]"]
+pub type IN3_R = crate::BitReader<IN3_A>;
+#[doc = "Write '1' to enable interrupt for event IN\\[3\\]\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum IN3_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<IN3_A> for bool {
+    #[inline(always)]
+    fn from(variant: IN3_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl IN3_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> IN3_A {
+        match self.bits {
+            false => IN3_A::DISABLED,
+            true => IN3_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == IN3_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == IN3_A::ENABLED
+    }
+}
+#[doc = "Write '1' to enable interrupt for event IN\\[3\\]\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum IN3_AW {
+    #[doc = "1: Enable"]
+    SET = 1,
+}
+impl From<IN3_AW> for bool {
+    #[inline(always)]
+    fn from(variant: IN3_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `IN3` writer - Write '1' to enable interrupt for event IN\\[3\\]"]
+pub type IN3_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, IN3_AW, O>;
+impl<'a, const O: u8> IN3_W<'a, O> {
+    #[doc = "Enable"]
+    #[inline(always)]
+    pub fn set(self) -> &'a mut W {
+        self.variant(IN3_AW::SET)
+    }
+}
+#[doc = "Field `IN4` reader - Write '1' to enable interrupt for event IN\\[4\\]"]
+pub type IN4_R = crate::BitReader<IN4_A>;
+#[doc = "Write '1' to enable interrupt for event IN\\[4\\]\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum IN4_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<IN4_A> for bool {
+    #[inline(always)]
+    fn from(variant: IN4_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl IN4_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> IN4_A {
+        match self.bits {
+            false => IN4_A::DISABLED,
+            true => IN4_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == IN4_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == IN4_A::ENABLED
+    }
+}
+#[doc = "Write '1' to enable interrupt for event IN\\[4\\]\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum IN4_AW {
+    #[doc = "1: Enable"]
+    SET = 1,
+}
+impl From<IN4_AW> for bool {
+    #[inline(always)]
+    fn from(variant: IN4_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `IN4` writer - Write '1' to enable interrupt for event IN\\[4\\]"]
+pub type IN4_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, IN4_AW, O>;
+impl<'a, const O: u8> IN4_W<'a, O> {
+    #[doc = "Enable"]
+    #[inline(always)]
+    pub fn set(self) -> &'a mut W {
+        self.variant(IN4_AW::SET)
+    }
+}
+#[doc = "Field `IN5` reader - Write '1' to enable interrupt for event IN\\[5\\]"]
+pub type IN5_R = crate::BitReader<IN5_A>;
+#[doc = "Write '1' to enable interrupt for event IN\\[5\\]\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum IN5_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<IN5_A> for bool {
+    #[inline(always)]
+    fn from(variant: IN5_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl IN5_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> IN5_A {
+        match self.bits {
+            false => IN5_A::DISABLED,
+            true => IN5_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == IN5_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == IN5_A::ENABLED
+    }
+}
+#[doc = "Write '1' to enable interrupt for event IN\\[5\\]\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum IN5_AW {
+    #[doc = "1: Enable"]
+    SET = 1,
+}
+impl From<IN5_AW> for bool {
+    #[inline(always)]
+    fn from(variant: IN5_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `IN5` writer - Write '1' to enable interrupt for event IN\\[5\\]"]
+pub type IN5_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, IN5_AW, O>;
+impl<'a, const O: u8> IN5_W<'a, O> {
+    #[doc = "Enable"]
+    #[inline(always)]
+    pub fn set(self) -> &'a mut W {
+        self.variant(IN5_AW::SET)
+    }
+}
+#[doc = "Field `IN6` reader - Write '1' to enable interrupt for event IN\\[6\\]"]
+pub type IN6_R = crate::BitReader<IN6_A>;
+#[doc = "Write '1' to enable interrupt for event IN\\[6\\]\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum IN6_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<IN6_A> for bool {
+    #[inline(always)]
+    fn from(variant: IN6_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl IN6_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> IN6_A {
+        match self.bits {
+            false => IN6_A::DISABLED,
+            true => IN6_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == IN6_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == IN6_A::ENABLED
+    }
+}
+#[doc = "Write '1' to enable interrupt for event IN\\[6\\]\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum IN6_AW {
+    #[doc = "1: Enable"]
+    SET = 1,
+}
+impl From<IN6_AW> for bool {
+    #[inline(always)]
+    fn from(variant: IN6_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `IN6` writer - Write '1' to enable interrupt for event IN\\[6\\]"]
+pub type IN6_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, IN6_AW, O>;
+impl<'a, const O: u8> IN6_W<'a, O> {
+    #[doc = "Enable"]
+    #[inline(always)]
+    pub fn set(self) -> &'a mut W {
+        self.variant(IN6_AW::SET)
+    }
+}
+#[doc = "Field `IN7` reader - Write '1' to enable interrupt for event IN\\[7\\]"]
+pub type IN7_R = crate::BitReader<IN7_A>;
+#[doc = "Write '1' to enable interrupt for event IN\\[7\\]\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum IN7_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<IN7_A> for bool {
+    #[inline(always)]
+    fn from(variant: IN7_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl IN7_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> IN7_A {
+        match self.bits {
+            false => IN7_A::DISABLED,
+            true => IN7_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == IN7_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == IN7_A::ENABLED
+    }
+}
+#[doc = "Write '1' to enable interrupt for event IN\\[7\\]\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum IN7_AW {
+    #[doc = "1: Enable"]
+    SET = 1,
+}
+impl From<IN7_AW> for bool {
+    #[inline(always)]
+    fn from(variant: IN7_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `IN7` writer - Write '1' to enable interrupt for event IN\\[7\\]"]
+pub type IN7_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, IN7_AW, O>;
+impl<'a, const O: u8> IN7_W<'a, O> {
+    #[doc = "Enable"]
+    #[inline(always)]
+    pub fn set(self) -> &'a mut W {
+        self.variant(IN7_AW::SET)
+    }
+}
+#[doc = "Field `PORT` reader - Write '1' to enable interrupt for event PORT"]
+pub type PORT_R = crate::BitReader<PORT_A>;
+#[doc = "Write '1' to enable interrupt for event PORT\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum PORT_A {
+    #[doc = "0: Read: Disabled"]
+    DISABLED = 0,
+    #[doc = "1: Read: Enabled"]
+    ENABLED = 1,
+}
+impl From<PORT_A> for bool {
+    #[inline(always)]
+    fn from(variant: PORT_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl PORT_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> PORT_A {
+        match self.bits {
+            false => PORT_A::DISABLED,
+            true => PORT_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == PORT_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == PORT_A::ENABLED
+    }
+}
+#[doc = "Write '1' to enable interrupt for event PORT\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum PORT_AW {
+    #[doc = "1: Enable"]
+    SET = 1,
+}
+impl From<PORT_AW> for bool {
+    #[inline(always)]
+    fn from(variant: PORT_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `PORT` writer - Write '1' to enable interrupt for event PORT"]
+pub type PORT_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, PORT_AW, O>;
+impl<'a, const O: u8> PORT_W<'a, O> {
+    #[doc = "Enable"]
+    #[inline(always)]
+    pub fn set(self) -> &'a mut W {
+        self.variant(PORT_AW::SET)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Write '1' to enable interrupt for event IN\\[0\\]"]
+    #[inline(always)]
+    pub fn in0(&self) -> IN0_R {
+        IN0_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Write '1' to enable interrupt for event IN\\[1\\]"]
+    #[inline(always)]
+    pub fn in1(&self) -> IN1_R {
+        IN1_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Write '1' to enable interrupt for event IN\\[2\\]"]
+    #[inline(always)]
+    pub fn in2(&self) -> IN2_R {
+        IN2_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Write '1' to enable interrupt for event IN\\[3\\]"]
+    #[inline(always)]
+    pub fn in3(&self) -> IN3_R {
+        IN3_R::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Write '1' to enable interrupt for event IN\\[4\\]"]
+    #[inline(always)]
+    pub fn in4(&self) -> IN4_R {
+        IN4_R::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - Write '1' to enable interrupt for event IN\\[5\\]"]
+    #[inline(always)]
+    pub fn in5(&self) -> IN5_R {
+        IN5_R::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - Write '1' to enable interrupt for event IN\\[6\\]"]
+    #[inline(always)]
+    pub fn in6(&self) -> IN6_R {
+        IN6_R::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - Write '1' to enable interrupt for event IN\\[7\\]"]
+    #[inline(always)]
+    pub fn in7(&self) -> IN7_R {
+        IN7_R::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 31 - Write '1' to enable interrupt for event PORT"]
+    #[inline(always)]
+    pub fn port(&self) -> PORT_R {
+        PORT_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Write '1' to enable interrupt for event IN\\[0\\]"]
+    #[inline(always)]
+    pub fn in0(&mut self) -> IN0_W<0> {
+        IN0_W::new(self)
+    }
+    #[doc = "Bit 1 - Write '1' to enable interrupt for event IN\\[1\\]"]
+    #[inline(always)]
+    pub fn in1(&mut self) -> IN1_W<1> {
+        IN1_W::new(self)
+    }
+    #[doc = "Bit 2 - Write '1' to enable interrupt for event IN\\[2\\]"]
+    #[inline(always)]
+    pub fn in2(&mut self) -> IN2_W<2> {
+        IN2_W::new(self)
+    }
+    #[doc = "Bit 3 - Write '1' to enable interrupt for event IN\\[3\\]"]
+    #[inline(always)]
+    pub fn in3(&mut self) -> IN3_W<3> {
+        IN3_W::new(self)
+    }
+    #[doc = "Bit 4 - Write '1' to enable interrupt for event IN\\[4\\]"]
+    #[inline(always)]
+    pub fn in4(&mut self) -> IN4_W<4> {
+        IN4_W::new(self)
+    }
+    #[doc = "Bit 5 - Write '1' to enable interrupt for event IN\\[5\\]"]
+    #[inline(always)]
+    pub fn in5(&mut self) -> IN5_W<5> {
+        IN5_W::new(self)
+    }
+    #[doc = "Bit 6 - Write '1' to enable interrupt for event IN\\[6\\]"]
+    #[inline(always)]
+    pub fn in6(&mut self) -> IN6_W<6> {
+        IN6_W::new(self)
+    }
+    #[doc = "Bit 7 - Write '1' to enable interrupt for event IN\\[7\\]"]
+    #[inline(always)]
+    pub fn in7(&mut self) -> IN7_W<7> {
+        IN7_W::new(self)
+    }
+    #[doc = "Bit 31 - Write '1' to enable interrupt for event PORT"]
+    #[inline(always)]
+    pub fn port(&mut self) -> PORT_W<31> {
+        PORT_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Enable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"]
+pub struct INTENSET_SPEC;
+impl crate::RegisterSpec for INTENSET_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [intenset::R](R) reader structure"]
+impl crate::Readable for INTENSET_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"]
+impl crate::Writable for INTENSET_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets INTENSET to value 0"]
+impl crate::Resettable for INTENSET_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9160-pac/src/gpiote0_s/publish_in.rs

@@ -0,0 +1,145 @@
+#[doc = "Register `PUBLISH_IN[%s]` reader"]
+pub struct R(crate::R<PUBLISH_IN_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<PUBLISH_IN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<PUBLISH_IN_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<PUBLISH_IN_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `PUBLISH_IN[%s]` writer"]
+pub struct W(crate::W<PUBLISH_IN_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<PUBLISH_IN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<PUBLISH_IN_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<PUBLISH_IN_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `CHIDX` reader - Channel that event IN\\[n\\]
+will publish to."]
+pub type CHIDX_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `CHIDX` writer - Channel that event IN\\[n\\]
+will publish to."]
+pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PUBLISH_IN_SPEC, u8, u8, 4, O>;
+#[doc = "Field `EN` reader - "]
+pub type EN_R = crate::BitReader<EN_A>;
+#[doc = "\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum EN_A {
+    #[doc = "0: Disable publishing"]
+    DISABLED = 0,
+    #[doc = "1: Enable publishing"]
+    ENABLED = 1,
+}
+impl From<EN_A> for bool {
+    #[inline(always)]
+    fn from(variant: EN_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl EN_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> EN_A {
+        match self.bits {
+            false => EN_A::DISABLED,
+            true => EN_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == EN_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == EN_A::ENABLED
+    }
+}
+#[doc = "Field `EN` writer - "]
+pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_IN_SPEC, EN_A, O>;
+impl<'a, const O: u8> EN_W<'a, O> {
+    #[doc = "Disable publishing"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(EN_A::DISABLED)
+    }
+    #[doc = "Enable publishing"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(EN_A::ENABLED)
+    }
+}
+impl R {
+    #[doc = "Bits 0:3 - Channel that event IN\\[n\\]
+will publish to."]
+    #[inline(always)]
+    pub fn chidx(&self) -> CHIDX_R {
+        CHIDX_R::new((self.bits & 0x0f) as u8)
+    }
+    #[doc = "Bit 31"]
+    #[inline(always)]
+    pub fn en(&self) -> EN_R {
+        EN_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:3 - Channel that event IN\\[n\\]
+will publish to."]
+    #[inline(always)]
+    pub fn chidx(&mut self) -> CHIDX_W<0> {
+        CHIDX_W::new(self)
+    }
+    #[doc = "Bit 31"]
+    #[inline(always)]
+    pub fn en(&mut self) -> EN_W<31> {
+        EN_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Description collection: Publish configuration for event IN\\[n\\]\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_in](index.html) module"]
+pub struct PUBLISH_IN_SPEC;
+impl crate::RegisterSpec for PUBLISH_IN_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [publish_in::R](R) reader structure"]
+impl crate::Readable for PUBLISH_IN_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [publish_in::W](W) writer structure"]
+impl crate::Writable for PUBLISH_IN_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets PUBLISH_IN[%s]
+to value 0"]
+impl crate::Resettable for PUBLISH_IN_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9160-pac/src/gpiote0_s/publish_port.rs

@@ -0,0 +1,140 @@
+#[doc = "Register `PUBLISH_PORT` reader"]
+pub struct R(crate::R<PUBLISH_PORT_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<PUBLISH_PORT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<PUBLISH_PORT_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<PUBLISH_PORT_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `PUBLISH_PORT` writer"]
+pub struct W(crate::W<PUBLISH_PORT_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<PUBLISH_PORT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<PUBLISH_PORT_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<PUBLISH_PORT_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `CHIDX` reader - Channel that event PORT will publish to."]
+pub type CHIDX_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `CHIDX` writer - Channel that event PORT will publish to."]
+pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PUBLISH_PORT_SPEC, u8, u8, 4, O>;
+#[doc = "Field `EN` reader - "]
+pub type EN_R = crate::BitReader<EN_A>;
+#[doc = "\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum EN_A {
+    #[doc = "0: Disable publishing"]
+    DISABLED = 0,
+    #[doc = "1: Enable publishing"]
+    ENABLED = 1,
+}
+impl From<EN_A> for bool {
+    #[inline(always)]
+    fn from(variant: EN_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl EN_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> EN_A {
+        match self.bits {
+            false => EN_A::DISABLED,
+            true => EN_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == EN_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == EN_A::ENABLED
+    }
+}
+#[doc = "Field `EN` writer - "]
+pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PUBLISH_PORT_SPEC, EN_A, O>;
+impl<'a, const O: u8> EN_W<'a, O> {
+    #[doc = "Disable publishing"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(EN_A::DISABLED)
+    }
+    #[doc = "Enable publishing"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(EN_A::ENABLED)
+    }
+}
+impl R {
+    #[doc = "Bits 0:3 - Channel that event PORT will publish to."]
+    #[inline(always)]
+    pub fn chidx(&self) -> CHIDX_R {
+        CHIDX_R::new((self.bits & 0x0f) as u8)
+    }
+    #[doc = "Bit 31"]
+    #[inline(always)]
+    pub fn en(&self) -> EN_R {
+        EN_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:3 - Channel that event PORT will publish to."]
+    #[inline(always)]
+    pub fn chidx(&mut self) -> CHIDX_W<0> {
+        CHIDX_W::new(self)
+    }
+    #[doc = "Bit 31"]
+    #[inline(always)]
+    pub fn en(&mut self) -> EN_W<31> {
+        EN_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Publish configuration for event PORT\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [publish_port](index.html) module"]
+pub struct PUBLISH_PORT_SPEC;
+impl crate::RegisterSpec for PUBLISH_PORT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [publish_port::R](R) reader structure"]
+impl crate::Readable for PUBLISH_PORT_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [publish_port::W](W) writer structure"]
+impl crate::Writable for PUBLISH_PORT_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets PUBLISH_PORT to value 0"]
+impl crate::Resettable for PUBLISH_PORT_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9160-pac/src/gpiote0_s/subscribe_clr.rs

@@ -0,0 +1,145 @@
+#[doc = "Register `SUBSCRIBE_CLR[%s]` reader"]
+pub struct R(crate::R<SUBSCRIBE_CLR_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<SUBSCRIBE_CLR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<SUBSCRIBE_CLR_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<SUBSCRIBE_CLR_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `SUBSCRIBE_CLR[%s]` writer"]
+pub struct W(crate::W<SUBSCRIBE_CLR_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<SUBSCRIBE_CLR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<SUBSCRIBE_CLR_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<SUBSCRIBE_CLR_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `CHIDX` reader - Channel that task CLR\\[n\\]
+will subscribe to"]
+pub type CHIDX_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `CHIDX` writer - Channel that task CLR\\[n\\]
+will subscribe to"]
+pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SUBSCRIBE_CLR_SPEC, u8, u8, 4, O>;
+#[doc = "Field `EN` reader - "]
+pub type EN_R = crate::BitReader<EN_A>;
+#[doc = "\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum EN_A {
+    #[doc = "0: Disable subscription"]
+    DISABLED = 0,
+    #[doc = "1: Enable subscription"]
+    ENABLED = 1,
+}
+impl From<EN_A> for bool {
+    #[inline(always)]
+    fn from(variant: EN_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl EN_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> EN_A {
+        match self.bits {
+            false => EN_A::DISABLED,
+            true => EN_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == EN_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == EN_A::ENABLED
+    }
+}
+#[doc = "Field `EN` writer - "]
+pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_CLR_SPEC, EN_A, O>;
+impl<'a, const O: u8> EN_W<'a, O> {
+    #[doc = "Disable subscription"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(EN_A::DISABLED)
+    }
+    #[doc = "Enable subscription"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(EN_A::ENABLED)
+    }
+}
+impl R {
+    #[doc = "Bits 0:3 - Channel that task CLR\\[n\\]
+will subscribe to"]
+    #[inline(always)]
+    pub fn chidx(&self) -> CHIDX_R {
+        CHIDX_R::new((self.bits & 0x0f) as u8)
+    }
+    #[doc = "Bit 31"]
+    #[inline(always)]
+    pub fn en(&self) -> EN_R {
+        EN_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:3 - Channel that task CLR\\[n\\]
+will subscribe to"]
+    #[inline(always)]
+    pub fn chidx(&mut self) -> CHIDX_W<0> {
+        CHIDX_W::new(self)
+    }
+    #[doc = "Bit 31"]
+    #[inline(always)]
+    pub fn en(&mut self) -> EN_W<31> {
+        EN_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Description collection: Subscribe configuration for task CLR\\[n\\]\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_clr](index.html) module"]
+pub struct SUBSCRIBE_CLR_SPEC;
+impl crate::RegisterSpec for SUBSCRIBE_CLR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [subscribe_clr::R](R) reader structure"]
+impl crate::Readable for SUBSCRIBE_CLR_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [subscribe_clr::W](W) writer structure"]
+impl crate::Writable for SUBSCRIBE_CLR_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets SUBSCRIBE_CLR[%s]
+to value 0"]
+impl crate::Resettable for SUBSCRIBE_CLR_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9160-pac/src/gpiote0_s/subscribe_out.rs

@@ -0,0 +1,145 @@
+#[doc = "Register `SUBSCRIBE_OUT[%s]` reader"]
+pub struct R(crate::R<SUBSCRIBE_OUT_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<SUBSCRIBE_OUT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<SUBSCRIBE_OUT_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<SUBSCRIBE_OUT_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `SUBSCRIBE_OUT[%s]` writer"]
+pub struct W(crate::W<SUBSCRIBE_OUT_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<SUBSCRIBE_OUT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<SUBSCRIBE_OUT_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<SUBSCRIBE_OUT_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `CHIDX` reader - Channel that task OUT\\[n\\]
+will subscribe to"]
+pub type CHIDX_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `CHIDX` writer - Channel that task OUT\\[n\\]
+will subscribe to"]
+pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SUBSCRIBE_OUT_SPEC, u8, u8, 4, O>;
+#[doc = "Field `EN` reader - "]
+pub type EN_R = crate::BitReader<EN_A>;
+#[doc = "\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum EN_A {
+    #[doc = "0: Disable subscription"]
+    DISABLED = 0,
+    #[doc = "1: Enable subscription"]
+    ENABLED = 1,
+}
+impl From<EN_A> for bool {
+    #[inline(always)]
+    fn from(variant: EN_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl EN_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> EN_A {
+        match self.bits {
+            false => EN_A::DISABLED,
+            true => EN_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == EN_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == EN_A::ENABLED
+    }
+}
+#[doc = "Field `EN` writer - "]
+pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_OUT_SPEC, EN_A, O>;
+impl<'a, const O: u8> EN_W<'a, O> {
+    #[doc = "Disable subscription"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(EN_A::DISABLED)
+    }
+    #[doc = "Enable subscription"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(EN_A::ENABLED)
+    }
+}
+impl R {
+    #[doc = "Bits 0:3 - Channel that task OUT\\[n\\]
+will subscribe to"]
+    #[inline(always)]
+    pub fn chidx(&self) -> CHIDX_R {
+        CHIDX_R::new((self.bits & 0x0f) as u8)
+    }
+    #[doc = "Bit 31"]
+    #[inline(always)]
+    pub fn en(&self) -> EN_R {
+        EN_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:3 - Channel that task OUT\\[n\\]
+will subscribe to"]
+    #[inline(always)]
+    pub fn chidx(&mut self) -> CHIDX_W<0> {
+        CHIDX_W::new(self)
+    }
+    #[doc = "Bit 31"]
+    #[inline(always)]
+    pub fn en(&mut self) -> EN_W<31> {
+        EN_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Description collection: Subscribe configuration for task OUT\\[n\\]\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_out](index.html) module"]
+pub struct SUBSCRIBE_OUT_SPEC;
+impl crate::RegisterSpec for SUBSCRIBE_OUT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [subscribe_out::R](R) reader structure"]
+impl crate::Readable for SUBSCRIBE_OUT_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [subscribe_out::W](W) writer structure"]
+impl crate::Writable for SUBSCRIBE_OUT_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets SUBSCRIBE_OUT[%s]
+to value 0"]
+impl crate::Resettable for SUBSCRIBE_OUT_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9160-pac/src/gpiote0_s/subscribe_set.rs

@@ -0,0 +1,145 @@
+#[doc = "Register `SUBSCRIBE_SET[%s]` reader"]
+pub struct R(crate::R<SUBSCRIBE_SET_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<SUBSCRIBE_SET_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<SUBSCRIBE_SET_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<SUBSCRIBE_SET_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `SUBSCRIBE_SET[%s]` writer"]
+pub struct W(crate::W<SUBSCRIBE_SET_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<SUBSCRIBE_SET_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<SUBSCRIBE_SET_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<SUBSCRIBE_SET_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `CHIDX` reader - Channel that task SET\\[n\\]
+will subscribe to"]
+pub type CHIDX_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `CHIDX` writer - Channel that task SET\\[n\\]
+will subscribe to"]
+pub type CHIDX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SUBSCRIBE_SET_SPEC, u8, u8, 4, O>;
+#[doc = "Field `EN` reader - "]
+pub type EN_R = crate::BitReader<EN_A>;
+#[doc = "\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum EN_A {
+    #[doc = "0: Disable subscription"]
+    DISABLED = 0,
+    #[doc = "1: Enable subscription"]
+    ENABLED = 1,
+}
+impl From<EN_A> for bool {
+    #[inline(always)]
+    fn from(variant: EN_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl EN_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> EN_A {
+        match self.bits {
+            false => EN_A::DISABLED,
+            true => EN_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == EN_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == EN_A::ENABLED
+    }
+}
+#[doc = "Field `EN` writer - "]
+pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SUBSCRIBE_SET_SPEC, EN_A, O>;
+impl<'a, const O: u8> EN_W<'a, O> {
+    #[doc = "Disable subscription"]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(EN_A::DISABLED)
+    }
+    #[doc = "Enable subscription"]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(EN_A::ENABLED)
+    }
+}
+impl R {
+    #[doc = "Bits 0:3 - Channel that task SET\\[n\\]
+will subscribe to"]
+    #[inline(always)]
+    pub fn chidx(&self) -> CHIDX_R {
+        CHIDX_R::new((self.bits & 0x0f) as u8)
+    }
+    #[doc = "Bit 31"]
+    #[inline(always)]
+    pub fn en(&self) -> EN_R {
+        EN_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:3 - Channel that task SET\\[n\\]
+will subscribe to"]
+    #[inline(always)]
+    pub fn chidx(&mut self) -> CHIDX_W<0> {
+        CHIDX_W::new(self)
+    }
+    #[doc = "Bit 31"]
+    #[inline(always)]
+    pub fn en(&mut self) -> EN_W<31> {
+        EN_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Description collection: Subscribe configuration for task SET\\[n\\]\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [subscribe_set](index.html) module"]
+pub struct SUBSCRIBE_SET_SPEC;
+impl crate::RegisterSpec for SUBSCRIBE_SET_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [subscribe_set::R](R) reader structure"]
+impl crate::Readable for SUBSCRIBE_SET_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [subscribe_set::W](W) writer structure"]
+impl crate::Writable for SUBSCRIBE_SET_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets SUBSCRIBE_SET[%s]
+to value 0"]
+impl crate::Resettable for SUBSCRIBE_SET_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9160-pac/src/gpiote0_s/tasks_clr.rs

@@ -0,0 +1,72 @@
+#[doc = "Register `TASKS_CLR[%s]` writer"]
+pub struct W(crate::W<TASKS_CLR_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<TASKS_CLR_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<TASKS_CLR_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<TASKS_CLR_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Task for writing to pin specified in CONFIG\\[n\\].PSEL. Action on pin is to set it low.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TASKS_CLR_AW {
+    #[doc = "1: Trigger task"]
+    TRIGGER = 1,
+}
+impl From<TASKS_CLR_AW> for bool {
+    #[inline(always)]
+    fn from(variant: TASKS_CLR_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `TASKS_CLR` writer - Task for writing to pin specified in CONFIG\\[n\\].PSEL. Action on pin is to set it low."]
+pub type TASKS_CLR_W<'a, const O: u8> = crate::BitWriter<'a, u32, TASKS_CLR_SPEC, TASKS_CLR_AW, O>;
+impl<'a, const O: u8> TASKS_CLR_W<'a, O> {
+    #[doc = "Trigger task"]
+    #[inline(always)]
+    pub fn trigger(self) -> &'a mut W {
+        self.variant(TASKS_CLR_AW::TRIGGER)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Task for writing to pin specified in CONFIG\\[n\\].PSEL. Action on pin is to set it low."]
+    #[inline(always)]
+    pub fn tasks_clr(&mut self) -> TASKS_CLR_W<0> {
+        TASKS_CLR_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Description collection: Task for writing to pin specified in CONFIG\\[n\\].PSEL. Action on pin is to set it low.\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_clr](index.html) module"]
+pub struct TASKS_CLR_SPEC;
+impl crate::RegisterSpec for TASKS_CLR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [tasks_clr::W](W) writer structure"]
+impl crate::Writable for TASKS_CLR_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets TASKS_CLR[%s]
+to value 0"]
+impl crate::Resettable for TASKS_CLR_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9160-pac/src/gpiote0_s/tasks_out.rs

@@ -0,0 +1,72 @@
+#[doc = "Register `TASKS_OUT[%s]` writer"]
+pub struct W(crate::W<TASKS_OUT_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<TASKS_OUT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<TASKS_OUT_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<TASKS_OUT_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Task for writing to pin specified in CONFIG\\[n\\].PSEL. Action on pin is configured in CONFIG\\[n\\].POLARITY.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TASKS_OUT_AW {
+    #[doc = "1: Trigger task"]
+    TRIGGER = 1,
+}
+impl From<TASKS_OUT_AW> for bool {
+    #[inline(always)]
+    fn from(variant: TASKS_OUT_AW) -> Self {
+        variant as u8 != 0
+    }
+}
+#[doc = "Field `TASKS_OUT` writer - Task for writing to pin specified in CONFIG\\[n\\].PSEL. Action on pin is configured in CONFIG\\[n\\].POLARITY."]
+pub type TASKS_OUT_W<'a, const O: u8> = crate::BitWriter<'a, u32, TASKS_OUT_SPEC, TASKS_OUT_AW, O>;
+impl<'a, const O: u8> TASKS_OUT_W<'a, O> {
+    #[doc = "Trigger task"]
+    #[inline(always)]
+    pub fn trigger(self) -> &'a mut W {
+        self.variant(TASKS_OUT_AW::TRIGGER)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Task for writing to pin specified in CONFIG\\[n\\].PSEL. Action on pin is configured in CONFIG\\[n\\].POLARITY."]
+    #[inline(always)]
+    pub fn tasks_out(&mut self) -> TASKS_OUT_W<0> {
+        TASKS_OUT_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Description collection: Task for writing to pin specified in CONFIG\\[n\\].PSEL. Action on pin is configured in CONFIG\\[n\\].POLARITY.\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tasks_out](index.html) module"]
+pub struct TASKS_OUT_SPEC;
+impl crate::RegisterSpec for TASKS_OUT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [tasks_out::W](W) writer structure"]
+impl crate::Writable for TASKS_OUT_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets TASKS_OUT[%s]
+to value 0"]
+impl crate::Resettable for TASKS_OUT_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}