feat: add display UI with splash screen, dashboard, and RSSI sparkline

Implement full SSD1306 OLED display support:
- Splash screen on boot (1.5s) with project name, version, board
- Dashboard showing radio state, config, counters, RSSI/SNR
- RSSI history sparkline (64-sample ring buffer, 2px-wide bars)
- DisplayOn/DisplayOff host commands routed via dedicated channel
- Pure render functions against generic DrawTarget (no hardware coupling)
- Display on/off control bypasses radio task entirely

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>

vendor/nrf9160-pac/src/i2s_ns/config/align.rs

@@ -0,0 +1,126 @@
+#[doc = "Register `ALIGN` reader"]
+pub struct R(crate::R<ALIGN_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<ALIGN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<ALIGN_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<ALIGN_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `ALIGN` writer"]
+pub struct W(crate::W<ALIGN_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<ALIGN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<ALIGN_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<ALIGN_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `ALIGN` reader - Alignment of sample within a frame."]
+pub type ALIGN_R = crate::BitReader<ALIGN_A>;
+#[doc = "Alignment of sample within a frame.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ALIGN_A {
+    #[doc = "0: Left-aligned."]
+    LEFT = 0,
+    #[doc = "1: Right-aligned."]
+    RIGHT = 1,
+}
+impl From<ALIGN_A> for bool {
+    #[inline(always)]
+    fn from(variant: ALIGN_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl ALIGN_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> ALIGN_A {
+        match self.bits {
+            false => ALIGN_A::LEFT,
+            true => ALIGN_A::RIGHT,
+        }
+    }
+    #[doc = "Checks if the value of the field is `LEFT`"]
+    #[inline(always)]
+    pub fn is_left(&self) -> bool {
+        *self == ALIGN_A::LEFT
+    }
+    #[doc = "Checks if the value of the field is `RIGHT`"]
+    #[inline(always)]
+    pub fn is_right(&self) -> bool {
+        *self == ALIGN_A::RIGHT
+    }
+}
+#[doc = "Field `ALIGN` writer - Alignment of sample within a frame."]
+pub type ALIGN_W<'a, const O: u8> = crate::BitWriter<'a, u32, ALIGN_SPEC, ALIGN_A, O>;
+impl<'a, const O: u8> ALIGN_W<'a, O> {
+    #[doc = "Left-aligned."]
+    #[inline(always)]
+    pub fn left(self) -> &'a mut W {
+        self.variant(ALIGN_A::LEFT)
+    }
+    #[doc = "Right-aligned."]
+    #[inline(always)]
+    pub fn right(self) -> &'a mut W {
+        self.variant(ALIGN_A::RIGHT)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Alignment of sample within a frame."]
+    #[inline(always)]
+    pub fn align(&self) -> ALIGN_R {
+        ALIGN_R::new((self.bits & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Alignment of sample within a frame."]
+    #[inline(always)]
+    pub fn align(&mut self) -> ALIGN_W<0> {
+        ALIGN_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Alignment of sample within a frame.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [align](index.html) module"]
+pub struct ALIGN_SPEC;
+impl crate::RegisterSpec for ALIGN_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [align::R](R) reader structure"]
+impl crate::Readable for ALIGN_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [align::W](W) writer structure"]
+impl crate::Writable for ALIGN_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets ALIGN to value 0"]
+impl crate::Resettable for ALIGN_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9160-pac/src/i2s_ns/config/channels.rs

@@ -0,0 +1,142 @@
+#[doc = "Register `CHANNELS` reader"]
+pub struct R(crate::R<CHANNELS_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<CHANNELS_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<CHANNELS_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<CHANNELS_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `CHANNELS` writer"]
+pub struct W(crate::W<CHANNELS_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<CHANNELS_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<CHANNELS_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<CHANNELS_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `CHANNELS` reader - Enable channels."]
+pub type CHANNELS_R = crate::FieldReader<u8, CHANNELS_A>;
+#[doc = "Enable channels.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum CHANNELS_A {
+    #[doc = "0: Stereo."]
+    STEREO = 0,
+    #[doc = "1: Left only."]
+    LEFT = 1,
+    #[doc = "2: Right only."]
+    RIGHT = 2,
+}
+impl From<CHANNELS_A> for u8 {
+    #[inline(always)]
+    fn from(variant: CHANNELS_A) -> Self {
+        variant as _
+    }
+}
+impl CHANNELS_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<CHANNELS_A> {
+        match self.bits {
+            0 => Some(CHANNELS_A::STEREO),
+            1 => Some(CHANNELS_A::LEFT),
+            2 => Some(CHANNELS_A::RIGHT),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `STEREO`"]
+    #[inline(always)]
+    pub fn is_stereo(&self) -> bool {
+        *self == CHANNELS_A::STEREO
+    }
+    #[doc = "Checks if the value of the field is `LEFT`"]
+    #[inline(always)]
+    pub fn is_left(&self) -> bool {
+        *self == CHANNELS_A::LEFT
+    }
+    #[doc = "Checks if the value of the field is `RIGHT`"]
+    #[inline(always)]
+    pub fn is_right(&self) -> bool {
+        *self == CHANNELS_A::RIGHT
+    }
+}
+#[doc = "Field `CHANNELS` writer - Enable channels."]
+pub type CHANNELS_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u32, CHANNELS_SPEC, u8, CHANNELS_A, 2, O>;
+impl<'a, const O: u8> CHANNELS_W<'a, O> {
+    #[doc = "Stereo."]
+    #[inline(always)]
+    pub fn stereo(self) -> &'a mut W {
+        self.variant(CHANNELS_A::STEREO)
+    }
+    #[doc = "Left only."]
+    #[inline(always)]
+    pub fn left(self) -> &'a mut W {
+        self.variant(CHANNELS_A::LEFT)
+    }
+    #[doc = "Right only."]
+    #[inline(always)]
+    pub fn right(self) -> &'a mut W {
+        self.variant(CHANNELS_A::RIGHT)
+    }
+}
+impl R {
+    #[doc = "Bits 0:1 - Enable channels."]
+    #[inline(always)]
+    pub fn channels(&self) -> CHANNELS_R {
+        CHANNELS_R::new((self.bits & 3) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:1 - Enable channels."]
+    #[inline(always)]
+    pub fn channels(&mut self) -> CHANNELS_W<0> {
+        CHANNELS_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Enable channels.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [channels](index.html) module"]
+pub struct CHANNELS_SPEC;
+impl crate::RegisterSpec for CHANNELS_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [channels::R](R) reader structure"]
+impl crate::Readable for CHANNELS_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [channels::W](W) writer structure"]
+impl crate::Writable for CHANNELS_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets CHANNELS to value 0"]
+impl crate::Resettable for CHANNELS_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9160-pac/src/i2s_ns/config/format.rs

@@ -0,0 +1,126 @@
+#[doc = "Register `FORMAT` reader"]
+pub struct R(crate::R<FORMAT_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<FORMAT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<FORMAT_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<FORMAT_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `FORMAT` writer"]
+pub struct W(crate::W<FORMAT_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<FORMAT_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<FORMAT_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<FORMAT_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `FORMAT` reader - Frame format."]
+pub type FORMAT_R = crate::BitReader<FORMAT_A>;
+#[doc = "Frame format.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FORMAT_A {
+    #[doc = "0: Original I2S format."]
+    I2S = 0,
+    #[doc = "1: Alternate (left- or right-aligned) format."]
+    ALIGNED = 1,
+}
+impl From<FORMAT_A> for bool {
+    #[inline(always)]
+    fn from(variant: FORMAT_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl FORMAT_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> FORMAT_A {
+        match self.bits {
+            false => FORMAT_A::I2S,
+            true => FORMAT_A::ALIGNED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `I2S`"]
+    #[inline(always)]
+    pub fn is_i2s(&self) -> bool {
+        *self == FORMAT_A::I2S
+    }
+    #[doc = "Checks if the value of the field is `ALIGNED`"]
+    #[inline(always)]
+    pub fn is_aligned(&self) -> bool {
+        *self == FORMAT_A::ALIGNED
+    }
+}
+#[doc = "Field `FORMAT` writer - Frame format."]
+pub type FORMAT_W<'a, const O: u8> = crate::BitWriter<'a, u32, FORMAT_SPEC, FORMAT_A, O>;
+impl<'a, const O: u8> FORMAT_W<'a, O> {
+    #[doc = "Original I2S format."]
+    #[inline(always)]
+    pub fn i2s(self) -> &'a mut W {
+        self.variant(FORMAT_A::I2S)
+    }
+    #[doc = "Alternate (left- or right-aligned) format."]
+    #[inline(always)]
+    pub fn aligned(self) -> &'a mut W {
+        self.variant(FORMAT_A::ALIGNED)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Frame format."]
+    #[inline(always)]
+    pub fn format(&self) -> FORMAT_R {
+        FORMAT_R::new((self.bits & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Frame format."]
+    #[inline(always)]
+    pub fn format(&mut self) -> FORMAT_W<0> {
+        FORMAT_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Frame format.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [format](index.html) module"]
+pub struct FORMAT_SPEC;
+impl crate::RegisterSpec for FORMAT_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [format::R](R) reader structure"]
+impl crate::Readable for FORMAT_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [format::W](W) writer structure"]
+impl crate::Writable for FORMAT_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets FORMAT to value 0"]
+impl crate::Resettable for FORMAT_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9160-pac/src/i2s_ns/config/mcken.rs

@@ -0,0 +1,126 @@
+#[doc = "Register `MCKEN` reader"]
+pub struct R(crate::R<MCKEN_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<MCKEN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<MCKEN_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<MCKEN_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `MCKEN` writer"]
+pub struct W(crate::W<MCKEN_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<MCKEN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<MCKEN_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<MCKEN_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `MCKEN` reader - Master clock generator enable."]
+pub type MCKEN_R = crate::BitReader<MCKEN_A>;
+#[doc = "Master clock generator enable.\n\nValue on reset: 1"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum MCKEN_A {
+    #[doc = "0: Master clock generator disabled and PSEL.MCK not connected(available as GPIO)."]
+    DISABLED = 0,
+    #[doc = "1: Master clock generator running and MCK output on PSEL.MCK."]
+    ENABLED = 1,
+}
+impl From<MCKEN_A> for bool {
+    #[inline(always)]
+    fn from(variant: MCKEN_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl MCKEN_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> MCKEN_A {
+        match self.bits {
+            false => MCKEN_A::DISABLED,
+            true => MCKEN_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == MCKEN_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == MCKEN_A::ENABLED
+    }
+}
+#[doc = "Field `MCKEN` writer - Master clock generator enable."]
+pub type MCKEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, MCKEN_SPEC, MCKEN_A, O>;
+impl<'a, const O: u8> MCKEN_W<'a, O> {
+    #[doc = "Master clock generator disabled and PSEL.MCK not connected(available as GPIO)."]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(MCKEN_A::DISABLED)
+    }
+    #[doc = "Master clock generator running and MCK output on PSEL.MCK."]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(MCKEN_A::ENABLED)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Master clock generator enable."]
+    #[inline(always)]
+    pub fn mcken(&self) -> MCKEN_R {
+        MCKEN_R::new((self.bits & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Master clock generator enable."]
+    #[inline(always)]
+    pub fn mcken(&mut self) -> MCKEN_W<0> {
+        MCKEN_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Master clock generator enable.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mcken](index.html) module"]
+pub struct MCKEN_SPEC;
+impl crate::RegisterSpec for MCKEN_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [mcken::R](R) reader structure"]
+impl crate::Readable for MCKEN_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [mcken::W](W) writer structure"]
+impl crate::Writable for MCKEN_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets MCKEN to value 0x01"]
+impl crate::Resettable for MCKEN_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0x01
+    }
+}

vendor/nrf9160-pac/src/i2s_ns/config/mckfreq.rs

@@ -0,0 +1,272 @@
+#[doc = "Register `MCKFREQ` reader"]
+pub struct R(crate::R<MCKFREQ_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<MCKFREQ_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<MCKFREQ_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<MCKFREQ_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `MCKFREQ` writer"]
+pub struct W(crate::W<MCKFREQ_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<MCKFREQ_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<MCKFREQ_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<MCKFREQ_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `MCKFREQ` reader - Master clock generator frequency."]
+pub type MCKFREQ_R = crate::FieldReader<u32, MCKFREQ_A>;
+#[doc = "Master clock generator frequency.\n\nValue on reset: 536870912"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u32)]
+pub enum MCKFREQ_A {
+    #[doc = "536870912: 32 MHz / 8 = 4.0 MHz"]
+    _32MDIV8 = 536870912,
+    #[doc = "402653184: 32 MHz / 10 = 3.2 MHz"]
+    _32MDIV10 = 402653184,
+    #[doc = "369098752: 32 MHz / 11 = 2.9090909 MHz"]
+    _32MDIV11 = 369098752,
+    #[doc = "285212672: 32 MHz / 15 = 2.1333333 MHz"]
+    _32MDIV15 = 285212672,
+    #[doc = "268435456: 32 MHz / 16 = 2.0 MHz"]
+    _32MDIV16 = 268435456,
+    #[doc = "201326592: 32 MHz / 21 = 1.5238095"]
+    _32MDIV21 = 201326592,
+    #[doc = "184549376: 32 MHz / 23 = 1.3913043 MHz"]
+    _32MDIV23 = 184549376,
+    #[doc = "142606336: 32 MHz / 30 = 1.0666667 MHz"]
+    _32MDIV30 = 142606336,
+    #[doc = "138412032: 32 MHz / 31 = 1.0322581 MHz"]
+    _32MDIV31 = 138412032,
+    #[doc = "134217728: 32 MHz / 32 = 1.0 MHz"]
+    _32MDIV32 = 134217728,
+    #[doc = "100663296: 32 MHz / 42 = 0.7619048 MHz"]
+    _32MDIV42 = 100663296,
+    #[doc = "68157440: 32 MHz / 63 = 0.5079365 MHz"]
+    _32MDIV63 = 68157440,
+    #[doc = "34340864: 32 MHz / 125 = 0.256 MHz"]
+    _32MDIV125 = 34340864,
+}
+impl From<MCKFREQ_A> for u32 {
+    #[inline(always)]
+    fn from(variant: MCKFREQ_A) -> Self {
+        variant as _
+    }
+}
+impl MCKFREQ_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<MCKFREQ_A> {
+        match self.bits {
+            536870912 => Some(MCKFREQ_A::_32MDIV8),
+            402653184 => Some(MCKFREQ_A::_32MDIV10),
+            369098752 => Some(MCKFREQ_A::_32MDIV11),
+            285212672 => Some(MCKFREQ_A::_32MDIV15),
+            268435456 => Some(MCKFREQ_A::_32MDIV16),
+            201326592 => Some(MCKFREQ_A::_32MDIV21),
+            184549376 => Some(MCKFREQ_A::_32MDIV23),
+            142606336 => Some(MCKFREQ_A::_32MDIV30),
+            138412032 => Some(MCKFREQ_A::_32MDIV31),
+            134217728 => Some(MCKFREQ_A::_32MDIV32),
+            100663296 => Some(MCKFREQ_A::_32MDIV42),
+            68157440 => Some(MCKFREQ_A::_32MDIV63),
+            34340864 => Some(MCKFREQ_A::_32MDIV125),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_32MDIV8`"]
+    #[inline(always)]
+    pub fn is_32mdiv8(&self) -> bool {
+        *self == MCKFREQ_A::_32MDIV8
+    }
+    #[doc = "Checks if the value of the field is `_32MDIV10`"]
+    #[inline(always)]
+    pub fn is_32mdiv10(&self) -> bool {
+        *self == MCKFREQ_A::_32MDIV10
+    }
+    #[doc = "Checks if the value of the field is `_32MDIV11`"]
+    #[inline(always)]
+    pub fn is_32mdiv11(&self) -> bool {
+        *self == MCKFREQ_A::_32MDIV11
+    }
+    #[doc = "Checks if the value of the field is `_32MDIV15`"]
+    #[inline(always)]
+    pub fn is_32mdiv15(&self) -> bool {
+        *self == MCKFREQ_A::_32MDIV15
+    }
+    #[doc = "Checks if the value of the field is `_32MDIV16`"]
+    #[inline(always)]
+    pub fn is_32mdiv16(&self) -> bool {
+        *self == MCKFREQ_A::_32MDIV16
+    }
+    #[doc = "Checks if the value of the field is `_32MDIV21`"]
+    #[inline(always)]
+    pub fn is_32mdiv21(&self) -> bool {
+        *self == MCKFREQ_A::_32MDIV21
+    }
+    #[doc = "Checks if the value of the field is `_32MDIV23`"]
+    #[inline(always)]
+    pub fn is_32mdiv23(&self) -> bool {
+        *self == MCKFREQ_A::_32MDIV23
+    }
+    #[doc = "Checks if the value of the field is `_32MDIV30`"]
+    #[inline(always)]
+    pub fn is_32mdiv30(&self) -> bool {
+        *self == MCKFREQ_A::_32MDIV30
+    }
+    #[doc = "Checks if the value of the field is `_32MDIV31`"]
+    #[inline(always)]
+    pub fn is_32mdiv31(&self) -> bool {
+        *self == MCKFREQ_A::_32MDIV31
+    }
+    #[doc = "Checks if the value of the field is `_32MDIV32`"]
+    #[inline(always)]
+    pub fn is_32mdiv32(&self) -> bool {
+        *self == MCKFREQ_A::_32MDIV32
+    }
+    #[doc = "Checks if the value of the field is `_32MDIV42`"]
+    #[inline(always)]
+    pub fn is_32mdiv42(&self) -> bool {
+        *self == MCKFREQ_A::_32MDIV42
+    }
+    #[doc = "Checks if the value of the field is `_32MDIV63`"]
+    #[inline(always)]
+    pub fn is_32mdiv63(&self) -> bool {
+        *self == MCKFREQ_A::_32MDIV63
+    }
+    #[doc = "Checks if the value of the field is `_32MDIV125`"]
+    #[inline(always)]
+    pub fn is_32mdiv125(&self) -> bool {
+        *self == MCKFREQ_A::_32MDIV125
+    }
+}
+#[doc = "Field `MCKFREQ` writer - Master clock generator frequency."]
+pub type MCKFREQ_W<'a, const O: u8> =
+    crate::FieldWriter<'a, u32, MCKFREQ_SPEC, u32, MCKFREQ_A, 32, O>;
+impl<'a, const O: u8> MCKFREQ_W<'a, O> {
+    #[doc = "32 MHz / 8 = 4.0 MHz"]
+    #[inline(always)]
+    pub fn _32mdiv8(self) -> &'a mut W {
+        self.variant(MCKFREQ_A::_32MDIV8)
+    }
+    #[doc = "32 MHz / 10 = 3.2 MHz"]
+    #[inline(always)]
+    pub fn _32mdiv10(self) -> &'a mut W {
+        self.variant(MCKFREQ_A::_32MDIV10)
+    }
+    #[doc = "32 MHz / 11 = 2.9090909 MHz"]
+    #[inline(always)]
+    pub fn _32mdiv11(self) -> &'a mut W {
+        self.variant(MCKFREQ_A::_32MDIV11)
+    }
+    #[doc = "32 MHz / 15 = 2.1333333 MHz"]
+    #[inline(always)]
+    pub fn _32mdiv15(self) -> &'a mut W {
+        self.variant(MCKFREQ_A::_32MDIV15)
+    }
+    #[doc = "32 MHz / 16 = 2.0 MHz"]
+    #[inline(always)]
+    pub fn _32mdiv16(self) -> &'a mut W {
+        self.variant(MCKFREQ_A::_32MDIV16)
+    }
+    #[doc = "32 MHz / 21 = 1.5238095"]
+    #[inline(always)]
+    pub fn _32mdiv21(self) -> &'a mut W {
+        self.variant(MCKFREQ_A::_32MDIV21)
+    }
+    #[doc = "32 MHz / 23 = 1.3913043 MHz"]
+    #[inline(always)]
+    pub fn _32mdiv23(self) -> &'a mut W {
+        self.variant(MCKFREQ_A::_32MDIV23)
+    }
+    #[doc = "32 MHz / 30 = 1.0666667 MHz"]
+    #[inline(always)]
+    pub fn _32mdiv30(self) -> &'a mut W {
+        self.variant(MCKFREQ_A::_32MDIV30)
+    }
+    #[doc = "32 MHz / 31 = 1.0322581 MHz"]
+    #[inline(always)]
+    pub fn _32mdiv31(self) -> &'a mut W {
+        self.variant(MCKFREQ_A::_32MDIV31)
+    }
+    #[doc = "32 MHz / 32 = 1.0 MHz"]
+    #[inline(always)]
+    pub fn _32mdiv32(self) -> &'a mut W {
+        self.variant(MCKFREQ_A::_32MDIV32)
+    }
+    #[doc = "32 MHz / 42 = 0.7619048 MHz"]
+    #[inline(always)]
+    pub fn _32mdiv42(self) -> &'a mut W {
+        self.variant(MCKFREQ_A::_32MDIV42)
+    }
+    #[doc = "32 MHz / 63 = 0.5079365 MHz"]
+    #[inline(always)]
+    pub fn _32mdiv63(self) -> &'a mut W {
+        self.variant(MCKFREQ_A::_32MDIV63)
+    }
+    #[doc = "32 MHz / 125 = 0.256 MHz"]
+    #[inline(always)]
+    pub fn _32mdiv125(self) -> &'a mut W {
+        self.variant(MCKFREQ_A::_32MDIV125)
+    }
+}
+impl R {
+    #[doc = "Bits 0:31 - Master clock generator frequency."]
+    #[inline(always)]
+    pub fn mckfreq(&self) -> MCKFREQ_R {
+        MCKFREQ_R::new(self.bits)
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Master clock generator frequency."]
+    #[inline(always)]
+    pub fn mckfreq(&mut self) -> MCKFREQ_W<0> {
+        MCKFREQ_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Master clock generator frequency.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mckfreq](index.html) module"]
+pub struct MCKFREQ_SPEC;
+impl crate::RegisterSpec for MCKFREQ_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [mckfreq::R](R) reader structure"]
+impl crate::Readable for MCKFREQ_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [mckfreq::W](W) writer structure"]
+impl crate::Writable for MCKFREQ_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets MCKFREQ to value 0x2000_0000"]
+impl crate::Resettable for MCKFREQ_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0x2000_0000
+    }
+}

vendor/nrf9160-pac/src/i2s_ns/config/mode.rs

@@ -0,0 +1,126 @@
+#[doc = "Register `MODE` reader"]
+pub struct R(crate::R<MODE_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<MODE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<MODE_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<MODE_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `MODE` writer"]
+pub struct W(crate::W<MODE_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<MODE_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<MODE_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<MODE_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `MODE` reader - I2S mode."]
+pub type MODE_R = crate::BitReader<MODE_A>;
+#[doc = "I2S mode.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum MODE_A {
+    #[doc = "0: Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx."]
+    MASTER = 0,
+    #[doc = "1: Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx"]
+    SLAVE = 1,
+}
+impl From<MODE_A> for bool {
+    #[inline(always)]
+    fn from(variant: MODE_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl MODE_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> MODE_A {
+        match self.bits {
+            false => MODE_A::MASTER,
+            true => MODE_A::SLAVE,
+        }
+    }
+    #[doc = "Checks if the value of the field is `MASTER`"]
+    #[inline(always)]
+    pub fn is_master(&self) -> bool {
+        *self == MODE_A::MASTER
+    }
+    #[doc = "Checks if the value of the field is `SLAVE`"]
+    #[inline(always)]
+    pub fn is_slave(&self) -> bool {
+        *self == MODE_A::SLAVE
+    }
+}
+#[doc = "Field `MODE` writer - I2S mode."]
+pub type MODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, MODE_SPEC, MODE_A, O>;
+impl<'a, const O: u8> MODE_W<'a, O> {
+    #[doc = "Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx."]
+    #[inline(always)]
+    pub fn master(self) -> &'a mut W {
+        self.variant(MODE_A::MASTER)
+    }
+    #[doc = "Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx"]
+    #[inline(always)]
+    pub fn slave(self) -> &'a mut W {
+        self.variant(MODE_A::SLAVE)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - I2S mode."]
+    #[inline(always)]
+    pub fn mode(&self) -> MODE_R {
+        MODE_R::new((self.bits & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - I2S mode."]
+    #[inline(always)]
+    pub fn mode(&mut self) -> MODE_W<0> {
+        MODE_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "I2S mode.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mode](index.html) module"]
+pub struct MODE_SPEC;
+impl crate::RegisterSpec for MODE_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [mode::R](R) reader structure"]
+impl crate::Readable for MODE_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [mode::W](W) writer structure"]
+impl crate::Writable for MODE_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets MODE to value 0"]
+impl crate::Resettable for MODE_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9160-pac/src/i2s_ns/config/ratio.rs

@@ -0,0 +1,219 @@
+#[doc = "Register `RATIO` reader"]
+pub struct R(crate::R<RATIO_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<RATIO_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<RATIO_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<RATIO_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `RATIO` writer"]
+pub struct W(crate::W<RATIO_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<RATIO_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<RATIO_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<RATIO_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `RATIO` reader - MCK / LRCK ratio."]
+pub type RATIO_R = crate::FieldReader<u8, RATIO_A>;
+#[doc = "MCK / LRCK ratio.\n\nValue on reset: 6"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum RATIO_A {
+    #[doc = "0: LRCK = MCK / 32"]
+    _32X = 0,
+    #[doc = "1: LRCK = MCK / 48"]
+    _48X = 1,
+    #[doc = "2: LRCK = MCK / 64"]
+    _64X = 2,
+    #[doc = "3: LRCK = MCK / 96"]
+    _96X = 3,
+    #[doc = "4: LRCK = MCK / 128"]
+    _128X = 4,
+    #[doc = "5: LRCK = MCK / 192"]
+    _192X = 5,
+    #[doc = "6: LRCK = MCK / 256"]
+    _256X = 6,
+    #[doc = "7: LRCK = MCK / 384"]
+    _384X = 7,
+    #[doc = "8: LRCK = MCK / 512"]
+    _512X = 8,
+}
+impl From<RATIO_A> for u8 {
+    #[inline(always)]
+    fn from(variant: RATIO_A) -> Self {
+        variant as _
+    }
+}
+impl RATIO_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<RATIO_A> {
+        match self.bits {
+            0 => Some(RATIO_A::_32X),
+            1 => Some(RATIO_A::_48X),
+            2 => Some(RATIO_A::_64X),
+            3 => Some(RATIO_A::_96X),
+            4 => Some(RATIO_A::_128X),
+            5 => Some(RATIO_A::_192X),
+            6 => Some(RATIO_A::_256X),
+            7 => Some(RATIO_A::_384X),
+            8 => Some(RATIO_A::_512X),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_32X`"]
+    #[inline(always)]
+    pub fn is_32x(&self) -> bool {
+        *self == RATIO_A::_32X
+    }
+    #[doc = "Checks if the value of the field is `_48X`"]
+    #[inline(always)]
+    pub fn is_48x(&self) -> bool {
+        *self == RATIO_A::_48X
+    }
+    #[doc = "Checks if the value of the field is `_64X`"]
+    #[inline(always)]
+    pub fn is_64x(&self) -> bool {
+        *self == RATIO_A::_64X
+    }
+    #[doc = "Checks if the value of the field is `_96X`"]
+    #[inline(always)]
+    pub fn is_96x(&self) -> bool {
+        *self == RATIO_A::_96X
+    }
+    #[doc = "Checks if the value of the field is `_128X`"]
+    #[inline(always)]
+    pub fn is_128x(&self) -> bool {
+        *self == RATIO_A::_128X
+    }
+    #[doc = "Checks if the value of the field is `_192X`"]
+    #[inline(always)]
+    pub fn is_192x(&self) -> bool {
+        *self == RATIO_A::_192X
+    }
+    #[doc = "Checks if the value of the field is `_256X`"]
+    #[inline(always)]
+    pub fn is_256x(&self) -> bool {
+        *self == RATIO_A::_256X
+    }
+    #[doc = "Checks if the value of the field is `_384X`"]
+    #[inline(always)]
+    pub fn is_384x(&self) -> bool {
+        *self == RATIO_A::_384X
+    }
+    #[doc = "Checks if the value of the field is `_512X`"]
+    #[inline(always)]
+    pub fn is_512x(&self) -> bool {
+        *self == RATIO_A::_512X
+    }
+}
+#[doc = "Field `RATIO` writer - MCK / LRCK ratio."]
+pub type RATIO_W<'a, const O: u8> = crate::FieldWriter<'a, u32, RATIO_SPEC, u8, RATIO_A, 4, O>;
+impl<'a, const O: u8> RATIO_W<'a, O> {
+    #[doc = "LRCK = MCK / 32"]
+    #[inline(always)]
+    pub fn _32x(self) -> &'a mut W {
+        self.variant(RATIO_A::_32X)
+    }
+    #[doc = "LRCK = MCK / 48"]
+    #[inline(always)]
+    pub fn _48x(self) -> &'a mut W {
+        self.variant(RATIO_A::_48X)
+    }
+    #[doc = "LRCK = MCK / 64"]
+    #[inline(always)]
+    pub fn _64x(self) -> &'a mut W {
+        self.variant(RATIO_A::_64X)
+    }
+    #[doc = "LRCK = MCK / 96"]
+    #[inline(always)]
+    pub fn _96x(self) -> &'a mut W {
+        self.variant(RATIO_A::_96X)
+    }
+    #[doc = "LRCK = MCK / 128"]
+    #[inline(always)]
+    pub fn _128x(self) -> &'a mut W {
+        self.variant(RATIO_A::_128X)
+    }
+    #[doc = "LRCK = MCK / 192"]
+    #[inline(always)]
+    pub fn _192x(self) -> &'a mut W {
+        self.variant(RATIO_A::_192X)
+    }
+    #[doc = "LRCK = MCK / 256"]
+    #[inline(always)]
+    pub fn _256x(self) -> &'a mut W {
+        self.variant(RATIO_A::_256X)
+    }
+    #[doc = "LRCK = MCK / 384"]
+    #[inline(always)]
+    pub fn _384x(self) -> &'a mut W {
+        self.variant(RATIO_A::_384X)
+    }
+    #[doc = "LRCK = MCK / 512"]
+    #[inline(always)]
+    pub fn _512x(self) -> &'a mut W {
+        self.variant(RATIO_A::_512X)
+    }
+}
+impl R {
+    #[doc = "Bits 0:3 - MCK / LRCK ratio."]
+    #[inline(always)]
+    pub fn ratio(&self) -> RATIO_R {
+        RATIO_R::new((self.bits & 0x0f) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:3 - MCK / LRCK ratio."]
+    #[inline(always)]
+    pub fn ratio(&mut self) -> RATIO_W<0> {
+        RATIO_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "MCK / LRCK ratio.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ratio](index.html) module"]
+pub struct RATIO_SPEC;
+impl crate::RegisterSpec for RATIO_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [ratio::R](R) reader structure"]
+impl crate::Readable for RATIO_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [ratio::W](W) writer structure"]
+impl crate::Writable for RATIO_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets RATIO to value 0x06"]
+impl crate::Resettable for RATIO_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0x06
+    }
+}

vendor/nrf9160-pac/src/i2s_ns/config/rxen.rs

@@ -0,0 +1,126 @@
+#[doc = "Register `RXEN` reader"]
+pub struct R(crate::R<RXEN_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<RXEN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<RXEN_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<RXEN_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `RXEN` writer"]
+pub struct W(crate::W<RXEN_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<RXEN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<RXEN_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<RXEN_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `RXEN` reader - Reception (RX) enable."]
+pub type RXEN_R = crate::BitReader<RXEN_A>;
+#[doc = "Reception (RX) enable.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum RXEN_A {
+    #[doc = "0: Reception disabled and now data will be written to the RXD.PTR address."]
+    DISABLED = 0,
+    #[doc = "1: Reception enabled."]
+    ENABLED = 1,
+}
+impl From<RXEN_A> for bool {
+    #[inline(always)]
+    fn from(variant: RXEN_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl RXEN_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> RXEN_A {
+        match self.bits {
+            false => RXEN_A::DISABLED,
+            true => RXEN_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == RXEN_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == RXEN_A::ENABLED
+    }
+}
+#[doc = "Field `RXEN` writer - Reception (RX) enable."]
+pub type RXEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, RXEN_SPEC, RXEN_A, O>;
+impl<'a, const O: u8> RXEN_W<'a, O> {
+    #[doc = "Reception disabled and now data will be written to the RXD.PTR address."]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(RXEN_A::DISABLED)
+    }
+    #[doc = "Reception enabled."]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(RXEN_A::ENABLED)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Reception (RX) enable."]
+    #[inline(always)]
+    pub fn rxen(&self) -> RXEN_R {
+        RXEN_R::new((self.bits & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Reception (RX) enable."]
+    #[inline(always)]
+    pub fn rxen(&mut self) -> RXEN_W<0> {
+        RXEN_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Reception (RX) enable.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxen](index.html) module"]
+pub struct RXEN_SPEC;
+impl crate::RegisterSpec for RXEN_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [rxen::R](R) reader structure"]
+impl crate::Readable for RXEN_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [rxen::W](W) writer structure"]
+impl crate::Writable for RXEN_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets RXEN to value 0"]
+impl crate::Resettable for RXEN_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

vendor/nrf9160-pac/src/i2s_ns/config/swidth.rs

@@ -0,0 +1,141 @@
+#[doc = "Register `SWIDTH` reader"]
+pub struct R(crate::R<SWIDTH_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<SWIDTH_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<SWIDTH_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<SWIDTH_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `SWIDTH` writer"]
+pub struct W(crate::W<SWIDTH_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<SWIDTH_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<SWIDTH_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<SWIDTH_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `SWIDTH` reader - Sample width."]
+pub type SWIDTH_R = crate::FieldReader<u8, SWIDTH_A>;
+#[doc = "Sample width.\n\nValue on reset: 1"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+#[repr(u8)]
+pub enum SWIDTH_A {
+    #[doc = "0: 8 bit."]
+    _8BIT = 0,
+    #[doc = "1: 16 bit."]
+    _16BIT = 1,
+    #[doc = "2: 24 bit."]
+    _24BIT = 2,
+}
+impl From<SWIDTH_A> for u8 {
+    #[inline(always)]
+    fn from(variant: SWIDTH_A) -> Self {
+        variant as _
+    }
+}
+impl SWIDTH_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> Option<SWIDTH_A> {
+        match self.bits {
+            0 => Some(SWIDTH_A::_8BIT),
+            1 => Some(SWIDTH_A::_16BIT),
+            2 => Some(SWIDTH_A::_24BIT),
+            _ => None,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_8BIT`"]
+    #[inline(always)]
+    pub fn is_8bit(&self) -> bool {
+        *self == SWIDTH_A::_8BIT
+    }
+    #[doc = "Checks if the value of the field is `_16BIT`"]
+    #[inline(always)]
+    pub fn is_16bit(&self) -> bool {
+        *self == SWIDTH_A::_16BIT
+    }
+    #[doc = "Checks if the value of the field is `_24BIT`"]
+    #[inline(always)]
+    pub fn is_24bit(&self) -> bool {
+        *self == SWIDTH_A::_24BIT
+    }
+}
+#[doc = "Field `SWIDTH` writer - Sample width."]
+pub type SWIDTH_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SWIDTH_SPEC, u8, SWIDTH_A, 2, O>;
+impl<'a, const O: u8> SWIDTH_W<'a, O> {
+    #[doc = "8 bit."]
+    #[inline(always)]
+    pub fn _8bit(self) -> &'a mut W {
+        self.variant(SWIDTH_A::_8BIT)
+    }
+    #[doc = "16 bit."]
+    #[inline(always)]
+    pub fn _16bit(self) -> &'a mut W {
+        self.variant(SWIDTH_A::_16BIT)
+    }
+    #[doc = "24 bit."]
+    #[inline(always)]
+    pub fn _24bit(self) -> &'a mut W {
+        self.variant(SWIDTH_A::_24BIT)
+    }
+}
+impl R {
+    #[doc = "Bits 0:1 - Sample width."]
+    #[inline(always)]
+    pub fn swidth(&self) -> SWIDTH_R {
+        SWIDTH_R::new((self.bits & 3) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:1 - Sample width."]
+    #[inline(always)]
+    pub fn swidth(&mut self) -> SWIDTH_W<0> {
+        SWIDTH_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Sample width.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [swidth](index.html) module"]
+pub struct SWIDTH_SPEC;
+impl crate::RegisterSpec for SWIDTH_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [swidth::R](R) reader structure"]
+impl crate::Readable for SWIDTH_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [swidth::W](W) writer structure"]
+impl crate::Writable for SWIDTH_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets SWIDTH to value 0x01"]
+impl crate::Resettable for SWIDTH_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0x01
+    }
+}

vendor/nrf9160-pac/src/i2s_ns/config/txen.rs

@@ -0,0 +1,126 @@
+#[doc = "Register `TXEN` reader"]
+pub struct R(crate::R<TXEN_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<TXEN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<TXEN_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<TXEN_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `TXEN` writer"]
+pub struct W(crate::W<TXEN_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<TXEN_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<TXEN_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<TXEN_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `TXEN` reader - Transmission (TX) enable."]
+pub type TXEN_R = crate::BitReader<TXEN_A>;
+#[doc = "Transmission (TX) enable.\n\nValue on reset: 1"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TXEN_A {
+    #[doc = "0: Transmission disabled and now data will be read from the RXD.TXD address."]
+    DISABLED = 0,
+    #[doc = "1: Transmission enabled."]
+    ENABLED = 1,
+}
+impl From<TXEN_A> for bool {
+    #[inline(always)]
+    fn from(variant: TXEN_A) -> Self {
+        variant as u8 != 0
+    }
+}
+impl TXEN_R {
+    #[doc = "Get enumerated values variant"]
+    #[inline(always)]
+    pub fn variant(&self) -> TXEN_A {
+        match self.bits {
+            false => TXEN_A::DISABLED,
+            true => TXEN_A::ENABLED,
+        }
+    }
+    #[doc = "Checks if the value of the field is `DISABLED`"]
+    #[inline(always)]
+    pub fn is_disabled(&self) -> bool {
+        *self == TXEN_A::DISABLED
+    }
+    #[doc = "Checks if the value of the field is `ENABLED`"]
+    #[inline(always)]
+    pub fn is_enabled(&self) -> bool {
+        *self == TXEN_A::ENABLED
+    }
+}
+#[doc = "Field `TXEN` writer - Transmission (TX) enable."]
+pub type TXEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, TXEN_SPEC, TXEN_A, O>;
+impl<'a, const O: u8> TXEN_W<'a, O> {
+    #[doc = "Transmission disabled and now data will be read from the RXD.TXD address."]
+    #[inline(always)]
+    pub fn disabled(self) -> &'a mut W {
+        self.variant(TXEN_A::DISABLED)
+    }
+    #[doc = "Transmission enabled."]
+    #[inline(always)]
+    pub fn enabled(self) -> &'a mut W {
+        self.variant(TXEN_A::ENABLED)
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Transmission (TX) enable."]
+    #[inline(always)]
+    pub fn txen(&self) -> TXEN_R {
+        TXEN_R::new((self.bits & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Transmission (TX) enable."]
+    #[inline(always)]
+    pub fn txen(&mut self) -> TXEN_W<0> {
+        TXEN_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "Transmission (TX) enable.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txen](index.html) module"]
+pub struct TXEN_SPEC;
+impl crate::RegisterSpec for TXEN_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [txen::R](R) reader structure"]
+impl crate::Readable for TXEN_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [txen::W](W) writer structure"]
+impl crate::Writable for TXEN_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets TXEN to value 0x01"]
+impl crate::Resettable for TXEN_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0x01
+    }
+}