feat: add display UI with splash screen, dashboard, and RSSI sparkline

Implement full SSD1306 OLED display support:
- Splash screen on boot (1.5s) with project name, version, board
- Dashboard showing radio state, config, counters, RSSI/SNR
- RSSI history sparkline (64-sample ring buffer, 2px-wide bars)
- DisplayOn/DisplayOff host commands routed via dedicated channel
- Pure render functions against generic DrawTarget (no hardware coupling)
- Display on/off control bypasses radio task entirely

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>

vendor/portable-atomic/src/imp/fallback/mod.rs

@@ -0,0 +1,551 @@
+// SPDX-License-Identifier: Apache-2.0 OR MIT
+
+/*
+Fallback implementation using global locks.
+
+This implementation uses seqlock for global locks.
+
+This is basically based on global locks in crossbeam-utils's `AtomicCell`,
+but seqlock is implemented in a way that does not depend on UB
+(see comments in optimistic_read method in atomic! macro for details).
+
+Note that we cannot use a lock per atomic type, since the in-memory representation of the atomic
+type and the value type must be the same.
+*/
+
+#![cfg_attr(
+    any(
+        all(
+            target_arch = "riscv32",
+            not(any(miri, portable_atomic_sanitize_thread)),
+            any(not(portable_atomic_no_asm), portable_atomic_unstable_asm),
+            not(portable_atomic_no_outline_atomics),
+            any(target_os = "linux", target_os = "android"),
+        ),
+        all(
+            target_arch = "arm",
+            not(any(miri, portable_atomic_sanitize_thread)),
+            any(not(portable_atomic_no_asm), portable_atomic_unstable_asm),
+            any(target_os = "linux", target_os = "android"),
+            any(test, not(any(target_feature = "v6", portable_atomic_target_feature = "v6"))),
+            not(portable_atomic_no_outline_atomics),
+        ),
+    ),
+    allow(dead_code)
+)]
+
+// This module requires CAS and this crate only provides atomics up to 128-bit.
+// I don't believe there are any 16-bit multi-core systems with CAS, and
+// at least no such architecture is currently supported in Rust.
+// 128-bit targets that lack atomic usize CAS also do not reach this module.
+#[cfg(target_pointer_width = "16")]
+compile_error!(
+    "internal error: unreachable since atomics for 16-bit targets can always be provided by disable interrupts"
+);
+#[cfg(target_pointer_width = "128")]
+compile_error!(
+    "internal error: unreachable since 128-bit target either has atomic CAS for the pointer width or does not have CAS"
+);
+
+mod utils;
+
+// Use "wide" sequence lock if the pointer width <= 32 for preventing its counter against wrap
+// around.
+//
+// Some 64-bit architectures have ABI with 32-bit pointer width (e.g., x86_64 X32 ABI,
+// AArch64 ILP32 ABI, mips64 N32 ABI). On those targets, AtomicU64 is available and fast,
+// so use it to implement normal sequence lock and reduce chunks of byte-wise atomic memcpy.
+cfg_has_fast_atomic_64! {
+    mod seq_lock;
+    type AtomicChunk = core::sync::atomic::AtomicU64;
+    type Chunk = u64;
+}
+cfg_no_fast_atomic_64! {
+    #[path = "seq_lock_wide.rs"]
+    mod seq_lock;
+    type AtomicChunk = core::sync::atomic::AtomicU32;
+    type Chunk = u32;
+}
+
+use core::{cell::UnsafeCell, mem, sync::atomic::Ordering};
+
+use self::{
+    seq_lock::{SeqLock, SeqLockWriteGuard},
+    utils::CachePadded,
+};
+#[cfg(portable_atomic_no_strict_provenance)]
+use crate::utils::ptr::PtrExt as _;
+use crate::utils::unlikely;
+
+// Adapted from https://github.com/crossbeam-rs/crossbeam/blob/crossbeam-utils-0.8.21/crossbeam-utils/src/atomic/atomic_cell.rs#L970-L1010.
+#[inline]
+#[must_use]
+fn lock(addr: usize) -> &'static SeqLock {
+    // The number of locks is a prime number because we want to make sure `addr % LEN` gets
+    // dispersed across all locks.
+    const LEN: usize = 67;
+    const L: CachePadded<SeqLock> = CachePadded::new(SeqLock::new());
+    static LOCKS: [CachePadded<SeqLock>; LEN] = [
+        L, L, L, L, L, L, L, L, L, L, L, L, L, L, L, L, L, L, L, L, L, L, L, L, L, L, L, L, L, L,
+        L, L, L, L, L, L, L, L, L, L, L, L, L, L, L, L, L, L, L, L, L, L, L, L, L, L, L, L, L, L,
+        L, L, L, L, L, L, L,
+    ];
+
+    // If the modulus is a constant number, the compiler will use crazy math to transform this into
+    // a sequence of cheap arithmetic operations rather than using the slow modulo instruction.
+    &LOCKS[addr % LEN]
+}
+
+macro_rules! atomic {
+    ($atomic_type:ident, $int_type:ident, $align:literal) => {
+        #[repr(C, align($align))]
+        pub(crate) struct $atomic_type {
+            v: UnsafeCell<$int_type>,
+        }
+
+        impl $atomic_type {
+            const LEN: usize = mem::size_of::<$int_type>() / mem::size_of::<Chunk>();
+
+            #[inline]
+            unsafe fn chunks(&self) -> &[AtomicChunk; Self::LEN] {
+                static_assert!($atomic_type::LEN > 1);
+                static_assert!(mem::size_of::<$int_type>() % mem::size_of::<Chunk>() == 0);
+
+                // SAFETY: the caller must uphold the safety contract for `chunks`.
+                unsafe { &*(self.v.get() as *const $int_type as *const [AtomicChunk; Self::LEN]) }
+            }
+
+            #[inline]
+            fn optimistic_read(&self) -> $int_type {
+                // Using `MaybeUninit<[usize; Self::LEN]>` here doesn't change codegen: https://godbolt.org/z/86f8s733M
+                let mut dst: [Chunk; Self::LEN] = [0; Self::LEN];
+                // SAFETY:
+                // - There are no threads that perform non-atomic concurrent write operations.
+                // - There is no writer that updates the value using atomic operations of different granularity.
+                //
+                // If the atomic operation is not used here, it will cause a data race
+                // when `write` performs concurrent write operation.
+                // Such a data race is sometimes considered virtually unproblematic
+                // in SeqLock implementations:
+                //
+                // - https://github.com/Amanieu/seqlock/issues/2
+                // - https://github.com/crossbeam-rs/crossbeam/blob/crossbeam-utils-0.8.21/crossbeam-utils/src/atomic/atomic_cell.rs#L1063-L1069
+                // - https://rust-lang.zulipchat.com/#narrow/stream/136281-t-lang.2Fwg-unsafe-code-guidelines/topic/avoiding.20UB.20due.20to.20races.20by.20discarding.20result.3F
+                //
+                // However, in our use case, the implementation that loads/stores value as
+                // chunks of usize is enough fast and sound, so we use that implementation.
+                //
+                // See also atomic-memcpy crate, a generic implementation of this pattern:
+                // https://github.com/taiki-e/atomic-memcpy
+                let chunks = unsafe { self.chunks() };
+                for i in 0..Self::LEN {
+                    dst[i] = chunks[i].load(Ordering::Relaxed);
+                }
+                // SAFETY: integers are plain old data types so we can always transmute to them.
+                unsafe { mem::transmute::<[Chunk; Self::LEN], $int_type>(dst) }
+            }
+
+            #[inline]
+            fn read(&self, _guard: &SeqLockWriteGuard<'static>) -> $int_type {
+                // This calls optimistic_read that can return teared value, but the resulting value
+                // is guaranteed not to be teared because we hold the lock to write.
+                self.optimistic_read()
+            }
+
+            #[inline]
+            fn write(&self, val: $int_type, _guard: &SeqLockWriteGuard<'static>) {
+                // SAFETY: integers are plain old data types so we can always transmute them to arrays of integers.
+                let val = unsafe { mem::transmute::<$int_type, [Chunk; Self::LEN]>(val) };
+                // SAFETY:
+                // - The guard guarantees that we hold the lock to write.
+                // - There are no threads that perform non-atomic concurrent read or write operations.
+                //
+                // See optimistic_read for the reason that atomic operations are used here.
+                let chunks = unsafe { self.chunks() };
+                for i in 0..Self::LEN {
+                    chunks[i].store(val[i], Ordering::Relaxed);
+                }
+            }
+        }
+
+        // Send is implicitly implemented.
+        // SAFETY: any data races are prevented by the lock and atomic operation.
+        unsafe impl Sync for $atomic_type {}
+
+        #[cfg(any(
+            test,
+            not(any(
+                all(
+                    target_arch = "x86_64",
+                    not(all(
+                        any(miri, portable_atomic_sanitize_thread),
+                        portable_atomic_no_cmpxchg16b_intrinsic,
+                    )),
+                    any(not(portable_atomic_no_asm), portable_atomic_unstable_asm),
+                    not(portable_atomic_no_outline_atomics),
+                    not(any(target_env = "sgx", miri)),
+                ),
+                all(
+                    target_arch = "powerpc64",
+                    not(portable_atomic_no_asm),
+                    not(portable_atomic_no_outline_atomics),
+                    any(
+                        all(
+                            target_os = "linux",
+                            any(
+                                all(
+                                    target_env = "gnu",
+                                    any(target_endian = "little", not(target_feature = "crt-static")),
+                                ),
+                                all(
+                                    target_env = "musl",
+                                    any(not(target_feature = "crt-static"), feature = "std"),
+                                ),
+                                target_env = "ohos",
+                                all(target_env = "uclibc", not(target_feature = "crt-static")),
+                                portable_atomic_outline_atomics,
+                            ),
+                        ),
+                        target_os = "android",
+                        all(
+                            target_os = "freebsd",
+                            any(
+                                target_endian = "little",
+                                not(target_feature = "crt-static"),
+                                portable_atomic_outline_atomics,
+                            ),
+                        ),
+                        target_os = "openbsd",
+                        all(
+                            target_os = "aix",
+                            not(portable_atomic_pre_llvm_20),
+                            portable_atomic_outline_atomics, // TODO(aix): currently disabled by default
+                        ),
+                    ),
+                    not(any(miri, portable_atomic_sanitize_thread)),
+                ),
+                all(
+                    target_arch = "riscv64",
+                    not(any(miri, portable_atomic_sanitize_thread)),
+                    any(not(portable_atomic_no_asm), portable_atomic_unstable_asm),
+                    not(portable_atomic_no_outline_atomics),
+                    any(target_os = "linux", target_os = "android"),
+                ),
+            )),
+        ))]
+        items!({
+            impl_default_no_fetch_ops!($atomic_type, $int_type);
+            impl_default_bit_opts!($atomic_type, $int_type);
+            impl $atomic_type {
+                #[inline]
+                pub(crate) const fn new(v: $int_type) -> Self {
+                    Self { v: UnsafeCell::new(v) }
+                }
+
+                #[inline]
+                pub(crate) fn is_lock_free() -> bool {
+                    Self::IS_ALWAYS_LOCK_FREE
+                }
+                pub(crate) const IS_ALWAYS_LOCK_FREE: bool = false;
+
+                #[inline]
+                #[cfg_attr(
+                    all(debug_assertions, not(portable_atomic_no_track_caller)),
+                    track_caller
+                )]
+                pub(crate) fn compare_exchange_weak(
+                    &self,
+                    current: $int_type,
+                    new: $int_type,
+                    success: Ordering,
+                    failure: Ordering,
+                ) -> Result<$int_type, $int_type> {
+                    self.compare_exchange(current, new, success, failure)
+                }
+
+                #[inline]
+                pub(crate) fn not(&self, order: Ordering) {
+                    self.fetch_not(order);
+                }
+                #[inline]
+                pub(crate) fn neg(&self, order: Ordering) {
+                    self.fetch_neg(order);
+                }
+
+                #[inline]
+                pub(crate) const fn as_ptr(&self) -> *mut $int_type {
+                    self.v.get()
+                }
+            }
+        });
+        #[cfg_attr(
+            any(
+                all(
+                    target_arch = "x86_64",
+                    not(all(
+                        any(miri, portable_atomic_sanitize_thread),
+                        portable_atomic_no_cmpxchg16b_intrinsic,
+                    )),
+                    any(not(portable_atomic_no_asm), portable_atomic_unstable_asm),
+                    not(portable_atomic_no_outline_atomics),
+                    not(any(target_env = "sgx", miri)),
+                ),
+                all(
+                    target_arch = "powerpc64",
+                    not(portable_atomic_no_asm),
+                    not(portable_atomic_no_outline_atomics),
+                    any(
+                        all(
+                            target_os = "linux",
+                            any(
+                                all(
+                                    target_env = "gnu",
+                                    any(target_endian = "little", not(target_feature = "crt-static")),
+                                ),
+                                all(
+                                    target_env = "musl",
+                                    any(not(target_feature = "crt-static"), feature = "std"),
+                                ),
+                                target_env = "ohos",
+                                all(target_env = "uclibc", not(target_feature = "crt-static")),
+                                portable_atomic_outline_atomics,
+                            ),
+                        ),
+                        target_os = "android",
+                        all(
+                            target_os = "freebsd",
+                            any(
+                                target_endian = "little",
+                                not(target_feature = "crt-static"),
+                                portable_atomic_outline_atomics,
+                            ),
+                        ),
+                        target_os = "openbsd",
+                        all(
+                            target_os = "aix",
+                            not(portable_atomic_pre_llvm_20),
+                            portable_atomic_outline_atomics, // TODO(aix): currently disabled by default
+                        ),
+                    ),
+                    not(any(miri, portable_atomic_sanitize_thread)),
+                ),
+                all(
+                    target_arch = "riscv64",
+                    not(any(miri, portable_atomic_sanitize_thread)),
+                    any(not(portable_atomic_no_asm), portable_atomic_unstable_asm),
+                    not(portable_atomic_no_outline_atomics),
+                    any(target_os = "linux", target_os = "android"),
+                ),
+            ),
+            allow(dead_code)
+        )]
+        impl $atomic_type {
+            #[inline]
+            #[cfg_attr(all(debug_assertions, not(portable_atomic_no_track_caller)), track_caller)]
+            pub(crate) fn load(&self, order: Ordering) -> $int_type {
+                crate::utils::assert_load_ordering(order);
+                let lock = lock(self.v.get().addr());
+
+                // Try doing an optimistic read first.
+                if let Some(stamp) = lock.optimistic_read(order) {
+                    let val = self.optimistic_read();
+
+                    if lock.validate_read(stamp, order) {
+                        return val;
+                    }
+                }
+
+                // Grab a regular write lock so that writers don't starve this load.
+                let guard = lock.write(
+                    Ordering::AcqRel, // we already emit sc fence in optimistic_read if needed
+                );
+                let val = self.read(&guard);
+                // The value hasn't been changed. Drop the guard without incrementing the stamp.
+                guard.abort();
+                val
+            }
+
+            #[inline]
+            #[cfg_attr(all(debug_assertions, not(portable_atomic_no_track_caller)), track_caller)]
+            pub(crate) fn store(&self, val: $int_type, order: Ordering) {
+                crate::utils::assert_store_ordering(order);
+                let guard = lock(self.v.get().addr()).write(order);
+                self.write(val, &guard)
+            }
+
+            #[inline]
+            pub(crate) fn swap(&self, val: $int_type, order: Ordering) -> $int_type {
+                let guard = lock(self.v.get().addr()).write(order);
+                let prev = self.read(&guard);
+                self.write(val, &guard);
+                prev
+            }
+
+            #[inline]
+            #[cfg_attr(all(debug_assertions, not(portable_atomic_no_track_caller)), track_caller)]
+            pub(crate) fn compare_exchange(
+                &self,
+                current: $int_type,
+                new: $int_type,
+                success: Ordering,
+                failure: Ordering,
+            ) -> Result<$int_type, $int_type> {
+                crate::utils::assert_compare_exchange_ordering(success, failure);
+                let order = if unlikely(success == Ordering::SeqCst || failure == Ordering::SeqCst)
+                {
+                    Ordering::SeqCst
+                } else {
+                    Ordering::AcqRel
+                };
+                let guard = lock(self.v.get().addr()).write(order);
+                let prev = self.read(&guard);
+                if prev == current {
+                    self.write(new, &guard);
+                    Ok(prev)
+                } else {
+                    // The value hasn't been changed. Drop the guard without incrementing the stamp.
+                    guard.abort();
+                    Err(prev)
+                }
+            }
+
+            #[inline]
+            pub(crate) fn fetch_add(&self, val: $int_type, order: Ordering) -> $int_type {
+                let guard = lock(self.v.get().addr()).write(order);
+                let prev = self.read(&guard);
+                self.write(prev.wrapping_add(val), &guard);
+                prev
+            }
+
+            #[inline]
+            pub(crate) fn fetch_sub(&self, val: $int_type, order: Ordering) -> $int_type {
+                let guard = lock(self.v.get().addr()).write(order);
+                let prev = self.read(&guard);
+                self.write(prev.wrapping_sub(val), &guard);
+                prev
+            }
+
+            #[inline]
+            pub(crate) fn fetch_and(&self, val: $int_type, order: Ordering) -> $int_type {
+                let guard = lock(self.v.get().addr()).write(order);
+                let prev = self.read(&guard);
+                self.write(prev & val, &guard);
+                prev
+            }
+
+            #[inline]
+            pub(crate) fn fetch_nand(&self, val: $int_type, order: Ordering) -> $int_type {
+                let guard = lock(self.v.get().addr()).write(order);
+                let prev = self.read(&guard);
+                self.write(!(prev & val), &guard);
+                prev
+            }
+
+            #[inline]
+            pub(crate) fn fetch_or(&self, val: $int_type, order: Ordering) -> $int_type {
+                let guard = lock(self.v.get().addr()).write(order);
+                let prev = self.read(&guard);
+                self.write(prev | val, &guard);
+                prev
+            }
+
+            #[inline]
+            pub(crate) fn fetch_xor(&self, val: $int_type, order: Ordering) -> $int_type {
+                let guard = lock(self.v.get().addr()).write(order);
+                let prev = self.read(&guard);
+                self.write(prev ^ val, &guard);
+                prev
+            }
+
+            #[inline]
+            pub(crate) fn fetch_not(&self, order: Ordering) -> $int_type {
+                let guard = lock(self.v.get().addr()).write(order);
+                let prev = self.read(&guard);
+                self.write(!prev, &guard);
+                prev
+            }
+
+            #[inline]
+            pub(crate) fn fetch_neg(&self, order: Ordering) -> $int_type {
+                let guard = lock(self.v.get().addr()).write(order);
+                let prev = self.read(&guard);
+                self.write(prev.wrapping_neg(), &guard);
+                prev
+            }
+        }
+        impl $atomic_type {
+            #[inline]
+            pub(crate) fn fetch_max(&self, val: $int_type, order: Ordering) -> $int_type {
+                let guard = lock(self.v.get().addr()).write(order);
+                let prev = self.read(&guard);
+                self.write(core::cmp::max(prev, val), &guard);
+                prev
+            }
+
+            #[inline]
+            pub(crate) fn fetch_min(&self, val: $int_type, order: Ordering) -> $int_type {
+                let guard = lock(self.v.get().addr()).write(order);
+                let prev = self.read(&guard);
+                self.write(core::cmp::min(prev, val), &guard);
+                prev
+            }
+        }
+    };
+}
+
+#[cfg_attr(
+    portable_atomic_no_cfg_target_has_atomic,
+    cfg(any(
+        test,
+        not(any(
+            not(portable_atomic_no_atomic_64),
+            all(
+                target_arch = "riscv32",
+                not(any(miri, portable_atomic_sanitize_thread)),
+                any(not(portable_atomic_no_asm), portable_atomic_unstable_asm),
+                any(target_feature = "zacas", portable_atomic_target_feature = "zacas"),
+            ),
+        ))
+    ))
+)]
+#[cfg_attr(
+    not(portable_atomic_no_cfg_target_has_atomic),
+    cfg(any(
+        test,
+        not(any(
+            target_has_atomic = "64",
+            all(
+                target_arch = "riscv32",
+                not(any(miri, portable_atomic_sanitize_thread)),
+                any(not(portable_atomic_no_asm), portable_atomic_unstable_asm),
+                any(target_feature = "zacas", portable_atomic_target_feature = "zacas"),
+            ),
+        ))
+    ))
+)]
+cfg_no_fast_atomic_64! {
+    atomic!(AtomicI64, i64, 8);
+    atomic!(AtomicU64, u64, 8);
+}
+
+atomic!(AtomicI128, i128, 16);
+atomic!(AtomicU128, u128, 16);
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    cfg_no_fast_atomic_64! {
+        test_atomic_int!(i64);
+        test_atomic_int!(u64);
+    }
+    test_atomic_int!(i128);
+    test_atomic_int!(u128);
+
+    // load/store/swap implementation is not affected by signedness, so it is
+    // enough to test only unsigned types.
+    cfg_no_fast_atomic_64! {
+        stress_test!(u64);
+    }
+    stress_test!(u128);
+}

vendor/portable-atomic/src/imp/fallback/outline_atomics.rs

@@ -0,0 +1,184 @@
+// SPDX-License-Identifier: Apache-2.0 OR MIT
+
+/*
+Helper for outline-atomics.
+
+On architectures where DW atomics are not supported on older CPUs, we use
+fallback implementation when DW atomic instructions are not supported and
+outline-atomics is enabled.
+
+This module provides helpers to implement them.
+*/
+
+use core::sync::atomic::Ordering;
+
+#[cfg(any(target_arch = "x86_64", target_arch = "powerpc64", target_arch = "riscv64"))]
+pub(crate) type Udw = u128;
+#[cfg(any(target_arch = "x86_64", target_arch = "powerpc64", target_arch = "riscv64"))]
+pub(crate) type AtomicUdw = super::super::super::fallback::AtomicU128;
+#[cfg(any(target_arch = "x86_64", target_arch = "powerpc64", target_arch = "riscv64"))]
+pub(crate) type AtomicIdw = super::super::super::fallback::AtomicI128;
+
+#[cfg(any(target_arch = "arm", target_arch = "riscv32"))]
+pub(crate) type Udw = u64;
+#[cfg(any(target_arch = "arm", target_arch = "riscv32"))]
+pub(crate) type AtomicUdw = super::super::super::fallback::AtomicU64;
+#[cfg(any(target_arch = "arm", target_arch = "riscv32"))]
+pub(crate) type AtomicIdw = super::super::super::fallback::AtomicI64;
+
+// Asserts that the function is called in the correct context.
+macro_rules! debug_assert_outline_atomics {
+    () => {
+        #[cfg(target_arch = "x86_64")]
+        {
+            debug_assert!(!super::detect::detect().cmpxchg16b());
+        }
+        #[cfg(target_arch = "powerpc64")]
+        {
+            debug_assert!(!super::detect::detect().quadword_atomics());
+        }
+        #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
+        {
+            debug_assert!(!super::detect::detect().zacas());
+        }
+        #[cfg(target_arch = "arm")]
+        {
+            debug_assert!(!super::has_kuser_cmpxchg64());
+        }
+    };
+}
+
+#[cold]
+pub(crate) unsafe fn atomic_load(src: *mut Udw, order: Ordering) -> Udw {
+    debug_assert_outline_atomics!();
+    #[allow(clippy::cast_ptr_alignment)]
+    // SAFETY: the caller must uphold the safety contract.
+    unsafe {
+        (*(src as *const AtomicUdw)).load(order)
+    }
+}
+fn_alias! {
+    #[cold]
+    pub(crate) unsafe fn(src: *mut Udw) -> Udw;
+    // fallback's atomic load has at least acquire semantics.
+    #[cfg(not(any(target_arch = "arm", target_arch = "x86_64")))]
+    atomic_load_non_seqcst = atomic_load(Ordering::Acquire);
+    atomic_load_seqcst = atomic_load(Ordering::SeqCst);
+}
+
+#[cfg(not(any(target_arch = "arm", target_arch = "riscv32", target_arch = "riscv64")))]
+#[cold]
+pub(crate) unsafe fn atomic_store(dst: *mut Udw, val: Udw, order: Ordering) {
+    debug_assert_outline_atomics!();
+    #[allow(clippy::cast_ptr_alignment)]
+    // SAFETY: the caller must uphold the safety contract.
+    unsafe {
+        (*(dst as *const AtomicUdw)).store(val, order);
+    }
+}
+#[cfg(not(any(target_arch = "arm", target_arch = "riscv32", target_arch = "riscv64")))]
+fn_alias! {
+    #[cold]
+    pub(crate) unsafe fn(dst: *mut Udw, val: Udw);
+    // fallback's atomic store has at least release semantics.
+    atomic_store_non_seqcst = atomic_store(Ordering::Release);
+    atomic_store_seqcst = atomic_store(Ordering::SeqCst);
+}
+
+#[cold]
+pub(crate) unsafe fn atomic_compare_exchange(
+    dst: *mut Udw,
+    old: Udw,
+    new: Udw,
+    success: Ordering,
+    failure: Ordering,
+) -> (Udw, bool) {
+    debug_assert_outline_atomics!();
+    #[allow(clippy::cast_ptr_alignment)]
+    // SAFETY: the caller must uphold the safety contract.
+    unsafe {
+        match (*(dst as *const AtomicUdw)).compare_exchange(old, new, success, failure) {
+            Ok(v) => (v, true),
+            Err(v) => (v, false),
+        }
+    }
+}
+fn_alias! {
+    #[cold]
+    pub(crate) unsafe fn(dst: *mut Udw, old: Udw, new: Udw) -> (Udw, bool);
+    // fallback's atomic CAS has at least AcqRel semantics.
+    #[cfg(not(any(target_arch = "arm", target_arch = "x86_64")))]
+    atomic_compare_exchange_non_seqcst
+        = atomic_compare_exchange(Ordering::AcqRel, Ordering::Acquire);
+    atomic_compare_exchange_seqcst
+        = atomic_compare_exchange(Ordering::SeqCst, Ordering::SeqCst);
+}
+
+macro_rules! atomic_rmw_3 {
+    (
+        $name:ident($atomic_type:ident::$method_name:ident),
+        $non_seqcst_alias:ident, $seqcst_alias:ident
+    ) => {
+        #[cold]
+        pub(crate) unsafe fn $name(dst: *mut Udw, val: Udw, order: Ordering) -> Udw {
+            debug_assert_outline_atomics!();
+            #[allow(
+                clippy::as_underscore,
+                clippy::cast_possible_wrap,
+                clippy::cast_ptr_alignment,
+                clippy::cast_sign_loss
+            )]
+            // SAFETY: the caller must uphold the safety contract.
+            unsafe {
+                (*(dst as *const $atomic_type)).$method_name(val as _, order) as Udw
+            }
+        }
+        fn_alias! {
+            #[cold]
+            pub(crate) unsafe fn(dst: *mut Udw, val: Udw) -> Udw;
+            // fallback's atomic RMW has at least AcqRel semantics.
+            #[cfg(not(any(target_arch = "arm", target_arch = "x86_64")))]
+            $non_seqcst_alias = $name(Ordering::AcqRel);
+            $seqcst_alias = $name(Ordering::SeqCst);
+        }
+    };
+}
+macro_rules! atomic_rmw_2 {
+    (
+        $name:ident($atomic_type:ident::$method_name:ident),
+        $non_seqcst_alias:ident, $seqcst_alias:ident
+    ) => {
+        #[cold]
+        pub(crate) unsafe fn $name(dst: *mut Udw, order: Ordering) -> Udw {
+            debug_assert_outline_atomics!();
+            #[allow(clippy::cast_ptr_alignment)]
+            // SAFETY: the caller must uphold the safety contract.
+            unsafe {
+                (*(dst as *const $atomic_type)).$method_name(order) as Udw
+            }
+        }
+        fn_alias! {
+            #[cold]
+            pub(crate) unsafe fn(dst: *mut Udw) -> Udw;
+            // fallback's atomic RMW has at least AcqRel semantics.
+            #[cfg(not(any(target_arch = "arm", target_arch = "x86_64")))]
+            $non_seqcst_alias = $name(Ordering::AcqRel);
+            $seqcst_alias = $name(Ordering::SeqCst);
+        }
+    };
+}
+
+atomic_rmw_3!(atomic_swap(AtomicUdw::swap), atomic_swap_non_seqcst, atomic_swap_seqcst);
+atomic_rmw_3!(atomic_add(AtomicUdw::fetch_add), atomic_add_non_seqcst, atomic_add_seqcst);
+atomic_rmw_3!(atomic_sub(AtomicUdw::fetch_sub), atomic_sub_non_seqcst, atomic_sub_seqcst);
+atomic_rmw_3!(atomic_and(AtomicUdw::fetch_and), atomic_and_non_seqcst, atomic_and_seqcst);
+atomic_rmw_3!(atomic_nand(AtomicUdw::fetch_nand), atomic_nand_non_seqcst, atomic_nand_seqcst);
+atomic_rmw_3!(atomic_or(AtomicUdw::fetch_or), atomic_or_non_seqcst, atomic_or_seqcst);
+atomic_rmw_3!(atomic_xor(AtomicUdw::fetch_xor), atomic_xor_non_seqcst, atomic_xor_seqcst);
+atomic_rmw_3!(atomic_max(AtomicIdw::fetch_max), atomic_max_non_seqcst, atomic_max_seqcst);
+atomic_rmw_3!(atomic_umax(AtomicUdw::fetch_max), atomic_umax_non_seqcst, atomic_umax_seqcst);
+atomic_rmw_3!(atomic_min(AtomicIdw::fetch_min), atomic_min_non_seqcst, atomic_min_seqcst);
+atomic_rmw_3!(atomic_umin(AtomicUdw::fetch_min), atomic_umin_non_seqcst, atomic_umin_seqcst);
+
+atomic_rmw_2!(atomic_not(AtomicUdw::fetch_not), atomic_not_non_seqcst, atomic_not_seqcst);
+atomic_rmw_2!(atomic_neg(AtomicUdw::fetch_neg), atomic_neg_non_seqcst, atomic_neg_seqcst);

vendor/portable-atomic/src/imp/fallback/seq_lock.rs

@@ -0,0 +1,191 @@
+// SPDX-License-Identifier: Apache-2.0 OR MIT
+
+// Adapted from https://github.com/crossbeam-rs/crossbeam/blob/crossbeam-utils-0.8.21/crossbeam-utils/src/atomic/seq_lock_wide.rs.
+
+use core::{
+    mem::ManuallyDrop,
+    sync::atomic::{self, AtomicU64, Ordering},
+};
+
+use super::utils::{Backoff, sc_fence};
+#[cfg(portable_atomic_unsafe_assume_privileged)]
+use crate::imp::interrupt::arch as interrupt;
+use crate::utils::unlikely;
+
+pub(super) type State = u64;
+
+const LOCKED: State = 1;
+
+/// A simple stamped lock.
+pub(super) struct SeqLock {
+    /// The current state of the lock.
+    ///
+    /// All bits except the least significant one hold the current stamp. When locked, the state
+    /// equals 1 and doesn't contain a valid stamp.
+    state: AtomicU64,
+}
+
+impl SeqLock {
+    #[inline]
+    pub(super) const fn new() -> Self {
+        Self { state: AtomicU64::new(0) }
+    }
+
+    /// If not locked, returns the current stamp.
+    ///
+    /// This method should be called before optimistic reads.
+    #[inline]
+    pub(super) fn optimistic_read(&self, order: Ordering) -> Option<State> {
+        if unlikely(order == Ordering::SeqCst) {
+            sc_fence();
+        }
+        let state = self.state.load(Ordering::Acquire);
+        if state == LOCKED { None } else { Some(state) }
+    }
+
+    /// Returns `true` if the current stamp is equal to `stamp`.
+    ///
+    /// This method should be called after optimistic reads to check whether they are valid. The
+    /// argument `stamp` should correspond to the one returned by method `optimistic_read`.
+    #[inline]
+    pub(super) fn validate_read(&self, stamp: State, order: Ordering) -> bool {
+        atomic::fence(Ordering::Acquire);
+        let result = self.state.load(Ordering::Relaxed) == stamp;
+        if unlikely(order == Ordering::SeqCst) && result {
+            sc_fence();
+        }
+        result
+    }
+
+    /// Grabs the lock for writing.
+    #[inline]
+    pub(super) fn write(&self, order: Ordering) -> SeqLockWriteGuard<'_> {
+        let emit_sc_fence = order == Ordering::SeqCst;
+        if unlikely(emit_sc_fence) {
+            sc_fence();
+        }
+
+        // Get current interrupt state and disable interrupts when the user
+        // explicitly declares that privileged instructions are available.
+        #[cfg(portable_atomic_unsafe_assume_privileged)]
+        let interrupt_state = interrupt::disable();
+
+        let mut backoff = Backoff::new();
+        loop {
+            let previous = self.state.swap(LOCKED, Ordering::Acquire);
+
+            if previous != LOCKED {
+                atomic::fence(Ordering::Release);
+
+                return SeqLockWriteGuard {
+                    lock: self,
+                    state: previous,
+                    #[cfg(portable_atomic_unsafe_assume_privileged)]
+                    interrupt_state,
+                    emit_sc_fence,
+                };
+            }
+
+            while self.state.load(Ordering::Relaxed) == LOCKED {
+                backoff.snooze();
+            }
+        }
+    }
+}
+
+/// An RAII guard that releases the lock and increments the stamp when dropped.
+#[must_use]
+pub(super) struct SeqLockWriteGuard<'a> {
+    /// The parent lock.
+    lock: &'a SeqLock,
+
+    /// The stamp before locking.
+    state: State,
+
+    /// The interrupt state before disabling.
+    #[cfg(portable_atomic_unsafe_assume_privileged)]
+    interrupt_state: interrupt::State,
+
+    emit_sc_fence: bool,
+}
+
+impl SeqLockWriteGuard<'_> {
+    /// Releases the lock without incrementing the stamp.
+    #[inline]
+    pub(super) fn abort(self) {
+        // We specifically don't want to call drop(), since that's
+        // what increments the stamp.
+        let this = ManuallyDrop::new(self);
+
+        // Restore the stamp.
+        //
+        // Release ordering for synchronizing with `optimistic_read`.
+        this.lock.state.store(this.state, Ordering::Release);
+
+        // Restore interrupt state.
+        // SAFETY: the state was retrieved by the previous `disable`.
+        #[cfg(portable_atomic_unsafe_assume_privileged)]
+        unsafe {
+            interrupt::restore(this.interrupt_state);
+        }
+
+        if unlikely(this.emit_sc_fence) {
+            sc_fence();
+        }
+    }
+}
+
+impl Drop for SeqLockWriteGuard<'_> {
+    #[inline]
+    fn drop(&mut self) {
+        // Release the lock and increment the stamp.
+        //
+        // Release ordering for synchronizing with `optimistic_read`.
+        self.lock.state.store(self.state.wrapping_add(2), Ordering::Release);
+
+        // Restore interrupt state.
+        // SAFETY: the state was retrieved by the previous `disable`.
+        #[cfg(portable_atomic_unsafe_assume_privileged)]
+        unsafe {
+            interrupt::restore(self.interrupt_state);
+        }
+
+        if unlikely(self.emit_sc_fence) {
+            sc_fence();
+        }
+    }
+}
+
+#[cfg(test)]
+mod tests {
+    use super::{Ordering, SeqLock};
+
+    #[test]
+    fn smoke() {
+        for &order in &[Ordering::AcqRel, Ordering::SeqCst] {
+            let lock = SeqLock::new();
+            let before = lock.optimistic_read(order).unwrap();
+            assert!(lock.validate_read(before, order));
+            {
+                let _guard = lock.write(order);
+            }
+            assert!(!lock.validate_read(before, order));
+            let after = lock.optimistic_read(order).unwrap();
+            assert_ne!(before, after);
+        }
+    }
+
+    #[test]
+    fn test_abort() {
+        for &order in &[Ordering::AcqRel, Ordering::SeqCst] {
+            let lock = SeqLock::new();
+            let before = lock.optimistic_read(order).unwrap();
+            {
+                let guard = lock.write(order);
+                guard.abort();
+            }
+            let after = lock.optimistic_read(order).unwrap();
+            assert_eq!(before, after, "aborted write does not update the stamp");
+        }
+    }
+}

vendor/portable-atomic/src/imp/fallback/seq_lock_wide.rs

@@ -0,0 +1,234 @@
+// SPDX-License-Identifier: Apache-2.0 OR MIT
+
+// Adapted from https://github.com/crossbeam-rs/crossbeam/blob/crossbeam-utils-0.8.21/crossbeam-utils/src/atomic/seq_lock_wide.rs.
+
+use core::{
+    mem::ManuallyDrop,
+    sync::atomic::{self, AtomicU32, Ordering},
+};
+
+use super::utils::{Backoff, sc_fence};
+#[cfg(portable_atomic_unsafe_assume_privileged)]
+use crate::imp::interrupt::arch as interrupt;
+use crate::utils::unlikely;
+
+pub(super) type State = u32;
+
+const LOCKED: State = 1;
+
+/// A simple stamped lock.
+///
+/// The state is represented as two `AtomicU32`: `state_hi` for high bits and `state_lo` for low
+/// bits.
+pub(super) struct SeqLock {
+    /// The high bits of the current state of the lock.
+    state_hi: AtomicU32,
+
+    /// The low bits of the current state of the lock.
+    ///
+    /// All bits except the least significant one hold the current stamp. When locked, the state_lo
+    /// equals 1 and doesn't contain a valid stamp.
+    state_lo: AtomicU32,
+}
+
+impl SeqLock {
+    #[inline]
+    pub(super) const fn new() -> Self {
+        Self { state_hi: AtomicU32::new(0), state_lo: AtomicU32::new(0) }
+    }
+
+    /// If not locked, returns the current stamp.
+    ///
+    /// This method should be called before optimistic reads.
+    #[inline]
+    pub(super) fn optimistic_read(&self, order: Ordering) -> Option<(State, State)> {
+        if unlikely(order == Ordering::SeqCst) {
+            sc_fence();
+        }
+        // The acquire loads from `state_hi` and `state_lo` synchronize with the release stores in
+        // `SeqLockWriteGuard::drop` and `SeqLockWriteGuard::abort`.
+        //
+        // As a consequence, we can make sure that (1) all writes within the era of `state_hi - 1`
+        // happens before now; and therefore, (2) if `state_lo` is even, all writes within the
+        // critical section of (`state_hi`, `state_lo`) happens before now.
+        let state_hi = self.state_hi.load(Ordering::Acquire);
+        let state_lo = self.state_lo.load(Ordering::Acquire);
+        if state_lo == LOCKED { None } else { Some((state_hi, state_lo)) }
+    }
+
+    /// Returns `true` if the current stamp is equal to `stamp`.
+    ///
+    /// This method should be called after optimistic reads to check whether they are valid. The
+    /// argument `stamp` should correspond to the one returned by method `optimistic_read`.
+    #[inline]
+    pub(super) fn validate_read(&self, stamp: (State, State), order: Ordering) -> bool {
+        // Thanks to the fence, if we're noticing any modification to the data at the critical
+        // section of `(stamp.0, stamp.1)`, then the critical section's write of 1 to state_lo should be
+        // visible.
+        atomic::fence(Ordering::Acquire);
+
+        // So if `state_lo` coincides with `stamp.1`, then either (1) we're noticing no modification
+        // to the data after the critical section of `(stamp.0, stamp.1)`, or (2) `state_lo` wrapped
+        // around.
+        //
+        // If (2) is the case, the acquire ordering ensures we see the new value of `state_hi`.
+        let state_lo = self.state_lo.load(Ordering::Acquire);
+
+        // If (2) is the case and `state_hi` coincides with `stamp.0`, then `state_hi` also wrapped
+        // around, which we give up to correctly validate the read.
+        let state_hi = self.state_hi.load(Ordering::Relaxed);
+
+        // Except for the case that both `state_hi` and `state_lo` wrapped around, the following
+        // condition implies that we're noticing no modification to the data after the critical
+        // section of `(stamp.0, stamp.1)`.
+        let result = (state_hi, state_lo) == stamp;
+        if unlikely(order == Ordering::SeqCst) && result {
+            sc_fence();
+        }
+        result
+    }
+
+    /// Grabs the lock for writing.
+    #[inline]
+    pub(super) fn write(&self, order: Ordering) -> SeqLockWriteGuard<'_> {
+        let emit_sc_fence = order == Ordering::SeqCst;
+        if unlikely(emit_sc_fence) {
+            sc_fence();
+        }
+
+        // Get current interrupt state and disable interrupts when the user
+        // explicitly declares that privileged instructions are available.
+        #[cfg(portable_atomic_unsafe_assume_privileged)]
+        let interrupt_state = interrupt::disable();
+
+        let mut backoff = Backoff::new();
+        loop {
+            let previous = self.state_lo.swap(LOCKED, Ordering::Acquire);
+
+            if previous != LOCKED {
+                // To synchronize with the acquire fence in `validate_read` via any modification to
+                // the data at the critical section of `(state_hi, previous)`.
+                atomic::fence(Ordering::Release);
+
+                return SeqLockWriteGuard {
+                    lock: self,
+                    state_lo: previous,
+                    #[cfg(portable_atomic_unsafe_assume_privileged)]
+                    interrupt_state,
+                    emit_sc_fence,
+                };
+            }
+
+            while self.state_lo.load(Ordering::Relaxed) == LOCKED {
+                backoff.snooze();
+            }
+        }
+    }
+}
+
+/// An RAII guard that releases the lock and increments the stamp when dropped.
+#[must_use]
+pub(super) struct SeqLockWriteGuard<'a> {
+    /// The parent lock.
+    lock: &'a SeqLock,
+
+    /// The stamp before locking.
+    state_lo: State,
+
+    /// The interrupt state before disabling.
+    #[cfg(portable_atomic_unsafe_assume_privileged)]
+    interrupt_state: interrupt::State,
+
+    emit_sc_fence: bool,
+}
+
+impl SeqLockWriteGuard<'_> {
+    /// Releases the lock without incrementing the stamp.
+    #[inline]
+    pub(super) fn abort(self) {
+        // We specifically don't want to call drop(), since that's
+        // what increments the stamp.
+        let this = ManuallyDrop::new(self);
+
+        // Restore the stamp.
+        //
+        // Release ordering for synchronizing with `optimistic_read`.
+        this.lock.state_lo.store(this.state_lo, Ordering::Release);
+
+        // Restore interrupt state.
+        // SAFETY: the state was retrieved by the previous `disable`.
+        #[cfg(portable_atomic_unsafe_assume_privileged)]
+        unsafe {
+            interrupt::restore(this.interrupt_state);
+        }
+
+        if unlikely(this.emit_sc_fence) {
+            sc_fence();
+        }
+    }
+}
+
+impl Drop for SeqLockWriteGuard<'_> {
+    #[inline]
+    fn drop(&mut self) {
+        let state_lo = self.state_lo.wrapping_add(2);
+
+        // Increase the high bits if the low bits wrap around.
+        //
+        // Release ordering for synchronizing with `optimistic_read`.
+        if state_lo == 0 {
+            let state_hi = self.lock.state_hi.load(Ordering::Relaxed);
+            self.lock.state_hi.store(state_hi.wrapping_add(1), Ordering::Release);
+        }
+
+        // Release the lock and increment the stamp.
+        //
+        // Release ordering for synchronizing with `optimistic_read`.
+        self.lock.state_lo.store(state_lo, Ordering::Release);
+
+        // Restore interrupt state.
+        // SAFETY: the state was retrieved by the previous `disable`.
+        #[cfg(portable_atomic_unsafe_assume_privileged)]
+        unsafe {
+            interrupt::restore(self.interrupt_state);
+        }
+
+        if unlikely(self.emit_sc_fence) {
+            sc_fence();
+        }
+    }
+}
+
+#[cfg(test)]
+mod tests {
+    use super::{Ordering, SeqLock};
+
+    #[test]
+    fn smoke() {
+        for &order in &[Ordering::AcqRel, Ordering::SeqCst] {
+            let lock = SeqLock::new();
+            let before = lock.optimistic_read(order).unwrap();
+            assert!(lock.validate_read(before, order));
+            {
+                let _guard = lock.write(order);
+            }
+            assert!(!lock.validate_read(before, order));
+            let after = lock.optimistic_read(order).unwrap();
+            assert_ne!(before, after);
+        }
+    }
+
+    #[test]
+    fn test_abort() {
+        for &order in &[Ordering::AcqRel, Ordering::SeqCst] {
+            let lock = SeqLock::new();
+            let before = lock.optimistic_read(order).unwrap();
+            {
+                let guard = lock.write(order);
+                guard.abort();
+            }
+            let after = lock.optimistic_read(order).unwrap();
+            assert_eq!(before, after, "aborted write does not update the stamp");
+        }
+    }
+}

vendor/portable-atomic/src/imp/fallback/utils.rs

@@ -0,0 +1,165 @@
+// SPDX-License-Identifier: Apache-2.0 OR MIT
+
+use core::ops;
+
+// Adapted from https://github.com/crossbeam-rs/crossbeam/blob/crossbeam-utils-0.8.21/crossbeam-utils/src/cache_padded.rs.
+/// Pads and aligns a value to the length of a cache line.
+// Starting from Intel's Sandy Bridge, spatial prefetcher is now pulling pairs of 64-byte cache
+// lines at a time, so we have to align to 128 bytes rather than 64.
+//
+// Sources:
+// - https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf
+// - https://github.com/facebook/folly/blob/1b5288e6eea6df074758f877c849b6e73bbb9fbb/folly/lang/Align.h#L107
+//
+// aarch64/arm64ec's big.LITTLE architecture has asymmetric cores and "big" cores have 128-byte cache line size.
+//
+// Sources:
+// - https://www.mono-project.com/news/2016/09/12/arm64-icache/
+//
+// powerpc64 has 128-byte cache line size.
+//
+// Sources:
+// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_ppc64x.go#L9
+// - https://github.com/torvalds/linux/blob/3516bd729358a2a9b090c1905bd2a3fa926e24c6/arch/powerpc/include/asm/cache.h#L26
+#[cfg_attr(
+    any(
+        target_arch = "x86_64",
+        target_arch = "aarch64",
+        target_arch = "arm64ec",
+        target_arch = "powerpc64",
+    ),
+    repr(align(128))
+)]
+// arm, mips, mips64, sparc, and hexagon have 32-byte cache line size.
+//
+// Sources:
+// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_arm.go#L7
+// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mips.go#L7
+// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mipsle.go#L7
+// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mips64x.go#L9
+// - https://github.com/torvalds/linux/blob/3516bd729358a2a9b090c1905bd2a3fa926e24c6/arch/sparc/include/asm/cache.h#L17
+// - https://github.com/torvalds/linux/blob/3516bd729358a2a9b090c1905bd2a3fa926e24c6/arch/hexagon/include/asm/cache.h#L12
+#[cfg_attr(
+    any(
+        target_arch = "arm",
+        target_arch = "mips",
+        target_arch = "mips32r6",
+        target_arch = "mips64",
+        target_arch = "mips64r6",
+        target_arch = "sparc",
+        target_arch = "hexagon",
+    ),
+    repr(align(32))
+)]
+// m68k has 16-byte cache line size.
+//
+// Sources:
+// - https://github.com/torvalds/linux/blob/3516bd729358a2a9b090c1905bd2a3fa926e24c6/arch/m68k/include/asm/cache.h#L9
+#[cfg_attr(target_arch = "m68k", repr(align(16)))]
+// s390x has 256-byte cache line size.
+//
+// Sources:
+// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_s390x.go#L7
+// - https://github.com/torvalds/linux/blob/3516bd729358a2a9b090c1905bd2a3fa926e24c6/arch/s390/include/asm/cache.h#L13
+#[cfg_attr(target_arch = "s390x", repr(align(256)))]
+// x86, wasm, riscv, and sparc64 have 64-byte cache line size.
+//
+// Sources:
+// - https://github.com/golang/go/blob/dda2991c2ea0c5914714469c4defc2562a907230/src/internal/cpu/cpu_x86.go#L9
+// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_wasm.go#L7
+// - https://github.com/torvalds/linux/blob/3516bd729358a2a9b090c1905bd2a3fa926e24c6/arch/riscv/include/asm/cache.h#L10
+// - https://github.com/torvalds/linux/blob/3516bd729358a2a9b090c1905bd2a3fa926e24c6/arch/sparc/include/asm/cache.h#L19
+//
+// All others are assumed to have 64-byte cache line size.
+#[cfg_attr(
+    not(any(
+        target_arch = "x86_64",
+        target_arch = "aarch64",
+        target_arch = "arm64ec",
+        target_arch = "powerpc64",
+        target_arch = "arm",
+        target_arch = "mips",
+        target_arch = "mips32r6",
+        target_arch = "mips64",
+        target_arch = "mips64r6",
+        target_arch = "sparc",
+        target_arch = "hexagon",
+        target_arch = "m68k",
+        target_arch = "s390x",
+    )),
+    repr(align(64))
+)]
+pub(crate) struct CachePadded<T> {
+    value: T,
+}
+
+impl<T> CachePadded<T> {
+    #[inline]
+    pub(crate) const fn new(value: T) -> Self {
+        Self { value }
+    }
+}
+
+impl<T> ops::Deref for CachePadded<T> {
+    type Target = T;
+
+    #[inline]
+    fn deref(&self) -> &Self::Target {
+        &self.value
+    }
+}
+
+// Adapted from https://github.com/crossbeam-rs/crossbeam/blob/crossbeam-utils-0.8.21/crossbeam-utils/src/backoff.rs.
+// Adjusted to reduce spinning.
+/// Performs exponential backoff in spin loops.
+pub(crate) struct Backoff {
+    step: u32,
+}
+
+// https://github.com/oneapi-src/oneTBB/blob/v2021.5.0/include/oneapi/tbb/detail/_utils.h#L46-L48
+const SPIN_LIMIT: u32 = 4;
+
+impl Backoff {
+    #[inline]
+    pub(crate) const fn new() -> Self {
+        Self { step: 0 }
+    }
+
+    #[inline]
+    pub(crate) fn snooze(&mut self) {
+        if self.step <= SPIN_LIMIT {
+            for _ in 0..1 << self.step {
+                #[allow(deprecated)]
+                core::sync::atomic::spin_loop_hint();
+            }
+            self.step += 1;
+        } else {
+            #[cfg(not(feature = "std"))]
+            for _ in 0..1 << self.step {
+                #[allow(deprecated)]
+                core::sync::atomic::spin_loop_hint();
+            }
+
+            #[cfg(feature = "std")]
+            std::thread::yield_now();
+        }
+    }
+}
+
+#[inline]
+pub(crate) fn sc_fence() {
+    cfg_sel!({
+        #[cfg(all(
+            any(target_arch = "x86", target_arch = "x86_64"),
+            not(any(miri, portable_atomic_sanitize_thread)),
+            any(not(portable_atomic_no_asm), portable_atomic_unstable_asm),
+        ))]
+        {
+            crate::imp::x86::sc_fence();
+        }
+        #[cfg(else)]
+        {
+            core::sync::atomic::fence(core::sync::atomic::Ordering::SeqCst);
+        }
+    });
+}