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feat: add display UI with splash screen, dashboard, and RSSI sparkline

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Implement full SSD1306 OLED display support:
- Splash screen on boot (1.5s) with project name, version, board
- Dashboard showing radio state, config, counters, RSSI/SNR
- RSSI history sparkline (64-sample ring buffer, 2px-wide bars)
- DisplayOn/DisplayOff host commands routed via dedicated channel
- Pure render functions against generic DrawTarget (no hardware coupling)
- Display on/off control bypasses radio task entirely

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
This commit is contained in:
swaitsandClaude Opus 4.6 committed 2026-03-29 20:42:54 -06:00
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commit 3102fc747a
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vendor/xtensa-lx/.cargo-checksum.json
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{"files":{".cargo_vcs_info.json":"0b9117238345379b261712e83296f982c896a37b7c3cd424bee84e5e73d2ca46","Cargo.toml":"2bdf67eb3cab4e0ddcfb9a52783ae733f11908810470151ac04e88c21f0c7034","Cargo.toml.orig":"e0ac2e41c344ed1e502c7aa838a1340c7716ddd3384b2dc6f2084e5d43286779","LICENSE-APACHE":"a2dad97420bdc1e465c24ed82e56640cdb700c026ef32f2425902facaff9600b","LICENSE-MIT":"eb7eee5b04db280923c36c4614fa5616aa4550d3cb0afe2061f32b471d9a7fb1","README.md":"03d401e5f113c35fd4b35223179214b52ef3458de18c814e59e137ee7d20c31b","build.rs":"b884e9f04e3f1a4cca61560782e6ee56c1a9b027edf3fadf6e169c3d266734d3","src/interrupt.rs":"82a9d0fb416f54710241fc5b9969582b9684f1f3c60589cd7cedcafa32ef04cb","src/lib.rs":"614c93cfe5063fbb88f3278f8fac59f58701fc6d923cebf7d7ba81db55fa4aec","src/macros.rs":"cb210a1b8a1d14132146378f937390b85badc08811c1270dc715768b1fbccd4d","src/mutex.rs":"1f5d23cdec90c4902b5c73ca7564cd61eb5339d238fbd1c20428b9c32ca865d2","src/timer.rs":"ae52a843dc8d59f8bbb93e794fa61b4543f2f61254c81bc79a522aa6a15d85d2"},"package":"e758f94e1a1f71758f94052a2766dcb12604998eb372b8b2e30576e3ab1ba1e6"}
vendor/xtensa-lx/.cargo_vcs_info.json
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{
"git": {
"sha1": "d6b8224d8a3e426be3564481130d994fe73e2bf6"
},
"path_in_vcs": "xtensa-lx"
}
vendor/xtensa-lx/Cargo.toml
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# THIS FILE IS AUTOMATICALLY GENERATED BY CARGO
#
# When uploading crates to the registry Cargo will automatically
# "normalize" Cargo.toml files for maximal compatibility
# with all versions of Cargo and also rewrite `path` dependencies
# to registry (e.g., crates.io) dependencies.
#
# If you are reading this file be aware that the original Cargo.toml
# will likely look very different (and much more reasonable).
# See Cargo.toml.orig for the original contents.
[package]
edition = "2021"
name = "xtensa-lx"
version = "0.9.0"
links = "xtensa-lx"
description = "Low-level access for Xtensa LX processors and peripherals"
readme = "README.md"
keywords = [
"lx",
"peripheral",
"register",
"xtensa",
]
categories = [
"embedded",
"hardware-support",
"no-std",
]
license = "MIT OR Apache-2.0"
repository = "https://github.com/esp-rs/xtensa-lx"
[package.metadata.docs.rs]
features = ["spin"]
[dependencies.bare-metal]
version = "1.0.0"
[dependencies.mutex-trait]
version = "0.2.0"
[dependencies.spin]
version = "0.9.8"
optional = true
[features]
spin = ["dep:spin"]
vendor/xtensa-lx/LICENSE-APACHE
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Apache License
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http://www.apache.org/licenses/
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vendor/xtensa-lx/LICENSE-MIT
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Copyright 2019-2022 esp-rs
Permission is hereby granted, free of charge, to any
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DEALINGS IN THE SOFTWARE.
vendor/xtensa-lx/README.md
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# `xtensa-lx`
[![Crates.io](https://img.shields.io/crates/v/xtensa-lx?labelColor=1C2C2E&color=C96329&logo=Rust&style=flat-square)](https://crates.io/crates/xtensa-lx)
[![docs.rs](https://img.shields.io/docsrs/xtensa-lx?labelColor=1C2C2E&color=C96329&logo=rust&style=flat-square)](https://docs.rs/xtensa-lx)
![Crates.io](https://img.shields.io/crates/l/xtensa-lx?labelColor=1C2C2E&style=flat-square)
[![Matrix](https://img.shields.io/matrix/esp-rs:matrix.org?label=join%20matrix&labelColor=1C2C2E&color=BEC5C9&logo=matrix&style=flat-square)](https://matrix.to/#/#esp-rs:matrix.org)
Low level access to Xtensa LX processors. This crate currently supports the following CPUs:
| Feature | Supported CPUs |
| --------- | ----------------- |
| `esp32` | ESP32 (_LX6_) |
| `esp32s2` | ESP32-S2 (_LX7_) |
| `esp32s3` | ESP32-S3 (_LX7_) |
## [Documentation](https://docs.rs/crate/xtensa-lx)
## License
Licensed under either of
- Apache License, Version 2.0 ([LICENSE-APACHE](LICENSE-APACHE) or
http://www.apache.org/licenses/LICENSE-2.0)
- MIT license ([LICENSE-MIT](LICENSE-MIT) or http://opensource.org/licenses/MIT)
at your option.
### Contribution
Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the
work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any
additional terms or conditions.
vendor/xtensa-lx/build.rs
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use std::{env, path::PathBuf};
fn main() {
let out_dir = PathBuf::from(env::var("OUT_DIR").unwrap());
println!("cargo:rustc-link-search={}", out_dir.display());
}
vendor/xtensa-lx/src/interrupt.rs
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//! Interrupts
use core::arch::asm;
pub use bare_metal::CriticalSection;
/// Trait for enums of external interrupt numbers.
///
/// This trait should be implemented by a peripheral access crate (PAC)
/// on its enum of available external interrupts for a specific device.
/// Each variant must convert to a u16 of its interrupt number,
/// which is its exception number - 16.
///
/// # Safety
///
/// This trait must only be implemented on enums of device interrupts. Each
/// enum variant must represent a distinct value (no duplicates are permitted),
/// and must always return the same value (do not change at runtime).
///
/// These requirements ensure safe nesting of critical sections.
pub unsafe trait InterruptNumber: Copy {
/// Return the interrupt number associated with this variant.
///
/// See trait documentation for safety requirements.
fn number(self) -> u16;
}
/// Disables all interrupts and return the previous settings
#[inline]
pub fn disable() -> u32 {
unsafe { set_mask(0) }
}
/// Enables all the interrupts
///
/// # Safety
///
/// - Do not call this function inside an `interrupt::free` critical section
#[inline]
pub unsafe fn enable() -> u32 {
set_mask(!0)
}
/// Enables specific interrupts and returns the previous setting
///
/// # Safety
///
/// - Do not call this function inside an `interrupt::free` critical section
#[inline]
pub unsafe fn set_mask(mut mask: u32) -> u32 {
asm!("
xsr {0}, intenable
rsync
",
inout(reg) mask, options(nostack)
);
mask
}
/// Disables specific interrupts and returns the previous settings
#[inline]
pub fn disable_mask(mask: u32) -> u32 {
let mut prev: u32 = 0;
let _dummy: u32;
unsafe {
asm!("
xsr.intenable {0} // get mask and temporarily disable interrupts
and {1}, {1}, {0}
rsync
wsr.intenable {1}
rsync
", inout(reg) prev, inout(reg) !mask => _dummy, options(nostack)
);
}
prev
}
/// Enables specific interrupts and returns the previous setting
///
/// # Safety
///
/// - Do not call this function inside an `interrupt::free` critical section
#[inline]
pub unsafe fn enable_mask(mask: u32) -> u32 {
let mut prev: u32 = 0;
let _dummy: u32;
asm!("
xsr.intenable {0} // get mask and temporarily disable interrupts
or {1}, {1}, {0}
rsync
wsr.intenable {1}
rsync
", inout(reg) prev, inout(reg) mask => _dummy, options(nostack));
prev
}
/// Get current interrupt mask
#[inline]
pub fn get_mask() -> u32 {
let mask: u32;
unsafe { asm!("rsr.intenable {0}", out(reg) mask) };
mask
}
/// Get currently active interrupts
#[inline]
pub fn get() -> u32 {
let mask: u32;
unsafe {
asm!("rsr.interrupt {0}", out(reg) mask, options(nostack));
}
mask
}
/// Set interrupt
///
/// Only valid for software interrupts
#[inline]
pub unsafe fn set(mask: u32) {
asm!("
wsr.intset {0}
rsync
",
in(reg) mask, options(nostack)
);
}
/// Clear interrupt
///
/// Only valid for software and edge-triggered interrupts
#[inline]
pub unsafe fn clear(mask: u32) {
asm!("
wsr.intclear {0}
rsync
",
in(reg) mask, options(nostack)
);
}
/// Get current interrupt level
#[inline]
pub fn get_level() -> u32 {
let ps: u32;
unsafe {
asm!("rsr.ps {0}", out(reg) ps, options(nostack));
};
ps & 0xf
}
/// Execute closure `f` in an interrupt-free context.
///
/// This as also known as a "critical section".
#[inline]
pub fn free<F, R>(f: F) -> R
where
F: FnOnce(&CriticalSection) -> R,
{
// disable interrupts and store old mask
let old_mask = disable();
let r = f(unsafe { &CriticalSection::new() });
// enable previously disable interrupts
unsafe {
enable_mask(old_mask);
}
r
}
vendor/xtensa-lx/src/lib.rs
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#![no_std]
#![allow(asm_sub_register)]
#![feature(asm_experimental_arch)]
use core::arch::asm;
pub mod interrupt;
pub mod mutex;
pub mod timer;
#[macro_use]
mod macros;
/// Move the vector base
#[inline]
pub unsafe fn set_vecbase(base: *const u32) {
asm!("wsr.vecbase {0}", in(reg) base, options(nostack));
}
/// Get the core stack pointer
#[inline(always)]
pub fn get_stack_pointer() -> *const u32 {
let x: *const u32;
unsafe { asm!("mov {0}, sp", out(reg) x, options(nostack)) };
x
}
/// Set the core stack pointer
///
/// *This is highly unsafe!*
/// It should be used with care at e.g. program start or when building a task
/// scheduler
///
/// `stack` pointer to the non-inclusive end of the stack (must be 16-byte
/// aligned)
#[inline(always)]
pub unsafe fn set_stack_pointer(stack: *mut u32) {
// FIXME: this function relies on it getting inlined - if it doesn't inline it
// will try and return from this function using the adress in `a0` which has
// just been trashed... According to https://nnethercote.github.io/perf-book/inlining.html:
// "Inline attributes do not guarantee that a function is inlined or not
// inlined, but in practice, #[inline(always)] will cause inlining in all but
// the most exceptional cases." Is this good enough? Should we rewrite these
// as a macro to guarentee inlining?
// NOTE: modification of the `sp` & `a0` is not typically allowed inside inline
// asm!, but because we *need* to modify it we can do so by ommiting it from
// the clobber
asm!(
"movi a0, 0", // trash return register
"mov sp, {0}", // move stack pointer
in(reg) stack, options(nostack)
);
}
/// Get the core current program counter
#[inline(always)]
pub fn get_program_counter() -> *const u32 {
let x: *const u32;
unsafe {
asm!("
mov {1}, {2}
call0 1f
.align 4
1:
mov {0}, {2}
mov {2}, {1}
", out(reg) x, out(reg) _, out(reg) _, options(nostack))
};
x
}
/// Get the id of the current core
#[inline]
pub fn get_processor_id() -> u32 {
let mut x: u32;
unsafe { asm!("rsr.prid {0}", out(reg) x, options(nostack)) };
x
}
const XDM_OCD_DCR_SET: u32 = 0x10200C;
const DCR_ENABLEOCD: u32 = 0x01;
/// Returns true if a debugger is attached
#[inline]
pub fn is_debugger_attached() -> bool {
let mut x: u32;
unsafe { asm!("rer {0}, {1}", out(reg) x, in(reg) XDM_OCD_DCR_SET, options(nostack)) };
(x & DCR_ENABLEOCD) != 0
}
/// Insert debug breakpoint
#[inline(always)]
pub fn debug_break() {
unsafe { asm!("break 1, 15", options(nostack)) };
}
vendor/xtensa-lx/src/macros.rs
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/// Macro to create a mutable reference to a statically allocated value
///
/// This macro returns a value with type `Option<&'static mut $ty>`.
/// `Some($expr)` will be returned the first time the macro is executed; further
/// calls will return `None`. To avoid `unwrap`ping a `None` variant the caller
/// must ensure that the macro is called from a function that's executed at most
/// once in the whole lifetime of the program.
///
/// # Example
///
/// ``` no_run
/// use xtensa_lx::singleton;
///
/// fn main() {
/// // OK if `main` is executed only once
/// let x: &'static mut bool = singleton!(: bool = false).unwrap();
///
/// let y = alias();
/// // BAD this second call to `alias` will definitively `panic!`
/// let y_alias = alias();
/// }
///
/// fn alias() -> &'static mut bool {
/// singleton!(: bool = false).unwrap()
/// }
/// ```
#[macro_export]
macro_rules! singleton {
(: $ty:ty = $expr:expr) => {
$crate::interrupt::free(|_| {
static mut VAR: Option<$ty> = None;
#[allow(unsafe_code)]
let used = unsafe { VAR.is_some() };
if used {
None
} else {
let expr = $expr;
#[allow(unsafe_code)]
unsafe {
VAR = Some(expr)
}
#[allow(unsafe_code)]
unsafe {
VAR.as_mut()
}
}
})
};
}
vendor/xtensa-lx/src/mutex.rs
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//! A series of Mutex's that also implements the `mutex-trait`.
use core::cell::UnsafeCell;
pub use mutex_trait::{self, Mutex};
/// A spinlock and critical section section based mutex.
#[cfg(feature = "spin")]
#[derive(Default)]
pub struct CriticalSectionSpinLockMutex<T> {
data: spin::Mutex<T>,
}
#[cfg(feature = "spin")]
impl<T> CriticalSectionSpinLockMutex<T> {
/// Create a new mutex
pub const fn new(data: T) -> Self {
CriticalSectionSpinLockMutex {
data: spin::Mutex::new(data),
}
}
}
#[cfg(feature = "spin")]
impl<T> mutex_trait::Mutex for &'_ CriticalSectionSpinLockMutex<T> {
type Data = T;
fn lock<R>(&mut self, f: impl FnOnce(&mut Self::Data) -> R) -> R {
crate::interrupt::free(|_| f(&mut (*self.data.lock())))
}
}
// NOTE A `Mutex` can be used as a channel so the protected data must be `Send`
// to prevent sending non-Sendable stuff (e.g. access tokens) across different
// execution contexts (e.g. interrupts)
#[cfg(feature = "spin")]
unsafe impl<T> Sync for CriticalSectionSpinLockMutex<T> where T: Send {}
/// A Mutex based on critical sections
///
/// # Safety
///
/// **This Mutex is only safe on single-core applications.**
///
/// A `CriticalSection` **is not sufficient** to ensure exclusive access across
/// cores.
#[derive(Default)]
pub struct CriticalSectionMutex<T> {
data: UnsafeCell<T>,
}
impl<T> CriticalSectionMutex<T> {
/// Create a new mutex
pub const fn new(data: T) -> Self {
CriticalSectionMutex {
data: UnsafeCell::new(data),
}
}
}
impl<T> mutex_trait::Mutex for &'_ CriticalSectionMutex<T> {
type Data = T;
fn lock<R>(&mut self, f: impl FnOnce(&mut Self::Data) -> R) -> R {
crate::interrupt::free(|_| f(unsafe { &mut *self.data.get() }))
}
}
// NOTE A `Mutex` can be used as a channel so the protected data must be `Send`
// to prevent sending non-Sendable stuff (e.g. access tokens) across different
// execution contexts (e.g. interrupts)
unsafe impl<T> Sync for CriticalSectionMutex<T> where T: Send {}
/// A spinlock based mutex.
#[cfg(feature = "spin")]
#[derive(Default)]
pub struct SpinLockMutex<T> {
data: spin::Mutex<T>,
}
#[cfg(feature = "spin")]
impl<T> SpinLockMutex<T> {
/// Create a new mutex
pub const fn new(data: T) -> Self {
SpinLockMutex {
data: spin::Mutex::new(data),
}
}
}
#[cfg(feature = "spin")]
impl<T> mutex_trait::Mutex for &'_ SpinLockMutex<T> {
type Data = T;
fn lock<R>(&mut self, f: impl FnOnce(&mut Self::Data) -> R) -> R {
f(&mut (*self.data.lock()))
}
}
// NOTE A `Mutex` can be used as a channel so the protected data must be `Send`
// to prevent sending non-Sendable stuff (e.g. access tokens) across different
// execution contexts (e.g. interrupts)
#[cfg(feature = "spin")]
unsafe impl<T> Sync for SpinLockMutex<T> where T: Send {}
vendor/xtensa-lx/src/timer.rs
Vendored
+90
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@@ -0,0 +1,90 @@
//! Xtensa internal timers
use core::arch::asm;
#[inline]
pub fn get_ccompare0() -> u32 {
let x: u32;
unsafe { asm!("rsr.ccompare0 {0}", out(reg) x, options(nostack)) };
x
}
#[inline]
pub fn get_ccompare1() -> u32 {
let x: u32;
unsafe { asm!("rsr.ccompare1 {0}", out(reg) x, options(nostack)) };
x
}
#[inline]
pub fn get_ccompare2() -> u32 {
let x: u32;
unsafe { asm!("rsr.ccompare2 {0}", out(reg) x, options(nostack)) };
x
}
#[inline]
pub fn get_ccompare3() -> u32 {
let x: u32;
unsafe { asm!("rsr.ccompare3 {0}", out(reg) x, options(nostack)) };
x
}
#[inline]
pub fn set_ccompare0(val: u32) {
unsafe {
asm!("
wsr.ccompare0 {0}
isync
", in(reg) val, options(nostack))
};
}
#[inline]
pub fn set_ccompare1(val: u32) {
unsafe {
asm!("
wsr.ccompare1 {0}
isync
", in(reg) val, options(nostack))
};
}
#[inline]
pub fn set_ccompare2(val: u32) {
unsafe {
asm!("
wsr.ccompare2 {0}
isync
", in(reg) val, options(nostack))
};
}
#[inline]
pub fn set_ccompare3(val: u32) {
unsafe {
asm!("
wsr.ccompare3 {0}
isync
", in(reg) val, options(nostack))
};
}
/// Get the core cycle count
#[inline]
pub fn get_cycle_count() -> u32 {
let x: u32;
unsafe { asm!("rsr.ccount {0}", out(reg) x, options(nostack)) };
x
}
/// cycle accurate delay using the cycle counter register
#[inline]
pub fn delay(clocks: u32) {
let start = get_cycle_count();
loop {
if get_cycle_count().wrapping_sub(start) >= clocks {
break;
}
}
}