#[doc = "Register `INTENCLR` reader"] pub struct R(crate::R); impl core::ops::Deref for R { type Target = crate::R; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl From> for R { #[inline(always)] fn from(reader: crate::R) -> Self { R(reader) } } #[doc = "Register `INTENCLR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `READY` reader - Write '1' to disable interrupt for event READY"] pub type READY_R = crate::BitReader; #[doc = "Write '1' to disable interrupt for event READY\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum READY_A { #[doc = "0: Read: Disabled"] DISABLED = 0, #[doc = "1: Read: Enabled"] ENABLED = 1, } impl From for bool { #[inline(always)] fn from(variant: READY_A) -> Self { variant as u8 != 0 } } impl READY_R { #[doc = "Get enumerated values variant"] #[inline(always)] pub fn variant(&self) -> READY_A { match self.bits { false => READY_A::DISABLED, true => READY_A::ENABLED, } } #[doc = "Checks if the value of the field is `DISABLED`"] #[inline(always)] pub fn is_disabled(&self) -> bool { *self == READY_A::DISABLED } #[doc = "Checks if the value of the field is `ENABLED`"] #[inline(always)] pub fn is_enabled(&self) -> bool { *self == READY_A::ENABLED } } #[doc = "Write '1' to disable interrupt for event READY\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum READY_AW { #[doc = "1: Disable"] CLEAR = 1, } impl From for bool { #[inline(always)] fn from(variant: READY_AW) -> Self { variant as u8 != 0 } } #[doc = "Field `READY` writer - Write '1' to disable interrupt for event READY"] pub type READY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, READY_AW, O>; impl<'a, const O: u8> READY_W<'a, O> { #[doc = "Disable"] #[inline(always)] pub fn clear(self) -> &'a mut W { self.variant(READY_AW::CLEAR) } } impl R { #[doc = "Bit 2 - Write '1' to disable interrupt for event READY"] #[inline(always)] pub fn ready(&self) -> READY_R { READY_R::new(((self.bits >> 2) & 1) != 0) } } impl W { #[doc = "Bit 2 - Write '1' to disable interrupt for event READY"] #[inline(always)] pub fn ready(&mut self) -> READY_W<2> { READY_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Disable interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] pub struct INTENCLR_SPEC; impl crate::RegisterSpec for INTENCLR_SPEC { type Ux = u32; } #[doc = "`read()` method returns [intenclr::R](R) reader structure"] impl crate::Readable for INTENCLR_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] impl crate::Writable for INTENCLR_SPEC { type Writer = W; } #[doc = "`reset()` method sets INTENCLR to value 0"] impl crate::Resettable for INTENCLR_SPEC { #[inline(always)] fn reset_value() -> Self::Ux { 0 } }