swaitsandClaude Opus 4.6
3102fc747a
Implement full SSD1306 OLED display support: - Splash screen on boot (1.5s) with project name, version, board - Dashboard showing radio state, config, counters, RSSI/SNR - RSSI history sparkline (64-sample ring buffer, 2px-wide bars) - DisplayOn/DisplayOff host commands routed via dedicated channel - Pure render functions against generic DrawTarget (no hardware coupling) - Display on/off control bypasses radio task entirely Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
852 lines
32 KiB
Rust
852 lines
32 KiB
Rust
use crate::ral::{
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modify_reg, otg_device, otg_global, otg_global_dieptxfx, otg_pwrclk, read_reg, write_reg,
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};
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use crate::transition::{EndpointConfig, EndpointDescriptor};
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use core::marker::PhantomData;
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use critical_section::{CriticalSection, Mutex};
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use embedded_hal::blocking::delay::DelayMs;
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use usb_device::bus::{PollResult, UsbBusAllocator};
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use usb_device::endpoint::{EndpointAddress, EndpointType};
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use usb_device::{Result, UsbDirection, UsbError};
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use crate::endpoint::{EndpointIn, EndpointOut};
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use crate::endpoint_memory::{EndpointBufferState, EndpointMemoryAllocator};
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use crate::target::UsbRegisters;
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use crate::{PhyType, UsbPeripheral};
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/// USB peripheral driver for STM32 microcontrollers.
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pub struct UsbBus<USB> {
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peripheral: USB,
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regs: Mutex<UsbRegisters>,
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allocator: EndpointAllocator<USB>,
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}
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impl<USB: UsbPeripheral> UsbBus<USB> {
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/// Constructs a new USB peripheral driver.
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pub fn new(peripheral: USB, ep_memory: &'static mut [u32]) -> UsbBusAllocator<Self> {
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let bus = UsbBus {
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peripheral,
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regs: Mutex::new(UsbRegisters::new::<USB>()),
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allocator: EndpointAllocator::new(ep_memory),
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};
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UsbBusAllocator::new(bus)
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}
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pub fn free(self) -> USB {
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self.peripheral
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}
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fn configure_all(&self, cs: CriticalSection<'_>) {
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let regs = self.regs.borrow(cs);
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// Rx FIFO
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// This calculation doesn't correspond to one in a Reference Manual.
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// In fact, the required number of words is higher than indicated in RM.
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// The following numbers are pessimistic and were figured out empirically.
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let rx_fifo_size = if USB::HIGH_SPEED {
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self.allocator.memory_allocator.total_rx_buffer_size_words() + 30
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} else {
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// F429 requires 35+ words for the (EP0[8] + EP2[64]) setup
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// F446 requires 39+ words for the same setup
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self.allocator.memory_allocator.total_rx_buffer_size_words() + 30
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};
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write_reg!(otg_global, regs.global(), GRXFSIZ, rx_fifo_size as u32);
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let mut fifo_top = rx_fifo_size;
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// Tx FIFO #0
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let fifo_size = self.allocator.memory_allocator.tx_fifo_size_words(0);
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#[cfg(feature = "fs")]
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write_reg!(
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otg_global,
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regs.global(),
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DIEPTXF0,
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TX0FD: fifo_size as u32,
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TX0FSA: fifo_top as u32
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);
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#[cfg(feature = "hs")]
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write_reg!(
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otg_global,
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regs.global(),
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GNPTXFSIZ,
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TX0FD: fifo_size as u32,
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TX0FSA: fifo_top as u32
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);
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fifo_top += fifo_size;
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// Tx FIFOs
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for i in 1..USB::ENDPOINT_COUNT {
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let fifo_size = self.allocator.memory_allocator.tx_fifo_size_words(i);
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let dieptxfx = regs.dieptxfx(i);
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write_reg!(
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otg_global_dieptxfx,
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dieptxfx,
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DIEPTXFx,
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INEPTXFD: fifo_size as u32,
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INEPTXSA: fifo_top as u32
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);
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fifo_top += fifo_size;
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}
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assert!(fifo_top as usize <= USB::FIFO_DEPTH_WORDS);
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// Flush Rx & Tx FIFOs
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modify_reg!(otg_global, regs.global(), GRSTCTL, RXFFLSH: 1, TXFFLSH: 1, TXFNUM: 0x10);
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while read_reg!(otg_global, regs.global(), GRSTCTL, RXFFLSH, TXFFLSH) != (0, 0) {}
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for ep in &self.allocator.endpoints_in {
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if let Some(ep) = ep {
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// enabling EP TX interrupt
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modify_reg!(otg_device, regs.device(), DAINTMSK, |v| v
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| (0x0001 << ep.address().index()));
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ep.configure(cs);
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}
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}
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for ep in &self.allocator.endpoints_out {
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if let Some(ep) = ep {
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if ep.address().index() == 0 {
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// enabling RX interrupt from EP0
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modify_reg!(otg_device, regs.device(), DAINTMSK, |v| v | 0x00010000);
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}
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ep.configure(cs);
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}
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}
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}
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fn deconfigure_all(&self, cs: CriticalSection<'_>) {
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let regs = self.regs.borrow(cs);
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// disable interrupts
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modify_reg!(otg_device, regs.device(), DAINTMSK, IEPM: 0, OEPM: 0);
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for ep in &self.allocator.endpoints_in {
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if let Some(ep) = ep {
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ep.deconfigure(cs);
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}
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}
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for ep in &self.allocator.endpoints_out {
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if let Some(ep) = ep {
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ep.deconfigure(cs);
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}
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}
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}
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pub fn force_reset(&self, delay: &mut impl DelayMs<u32>) -> Result<()> {
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critical_section::with(|cs| {
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let regs = self.regs.borrow(cs);
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write_reg!(otg_device, regs.device(), DCTL, SDIS: 1); // Soft disconnect
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delay.delay_ms(3);
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write_reg!(otg_device, regs.device(), DCTL, SDIS: 0); // Soft connect
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delay.delay_ms(3);
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});
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Ok(())
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}
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#[cfg(feature = "hs")]
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/// Reads from a ULPI register in an external ULPI PHY.
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///
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/// Interrupts are disabled for the duration of the function call.
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///
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/// **Panics:** if `phy_type` is not `PhyType::ExternalHighSpeed`.
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///
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/// # Example
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///
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/// ```
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/// # use synopsys_usb_otg::{UsbPeripheral, UsbBus};
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/// fn read_usb_vid_pid<USB: UsbPeripheral>(bus: &UsbBus<USB>) -> (u16, u16) {
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/// let mut vid: u16 = bus.ulpi_read(0x00) as u16;
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/// vid |= (bus.ulpi_read(0x01) as u16) << 8;
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/// let mut pid: u16 = bus.ulpi_read(0x02) as u16;
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/// pid |= (bus.ulpi_read(0x03) as u16) << 8;
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/// (vid, pid)
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/// }
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/// ```
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pub fn ulpi_read(&self, addr: u8) -> core::result::Result<u8, UlpiError> {
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if self.peripheral.phy_type() != PhyType::ExternalHighSpeed {
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panic!("ulpi_read is only supported with external ULPI PHYs");
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}
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critical_section::with(|cs| {
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let regs = self.regs.borrow(cs);
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// Begin ULPI register read transaction
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modify_reg!(otg_global, regs.global(), PHYCR,
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NEW: 1,
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RW: 0,
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ADDR: addr as u32
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);
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// ULPI transactions should take less than 1us. 1000 iterations should be enough even for fast MCUs.
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let mut timeout = 1000;
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while timeout > 0 {
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// Wait for transaction to complete
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if read_reg!(otg_global, regs.global(), PHYCR, DONE) != 0 {
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// Read transaction data
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return Ok((read_reg!(otg_global, regs.global(), PHYCR, DATA) & 0xFF) as u8);
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}
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timeout -= 1;
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}
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Err(UlpiError::Timeout)
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})
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}
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#[cfg(feature = "hs")]
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/// Writes to a ULPI register in an external ULPI PHY.
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///
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/// Interrupts are disabled for the duration of the function call.
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///
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/// **Panics:** if `phy_type` is not `PhyType::ExternalHighSpeed`.
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pub fn ulpi_write(&self, addr: u8, data: u8) -> core::result::Result<(), UlpiError> {
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if self.peripheral.phy_type() != PhyType::ExternalHighSpeed {
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panic!("ulpi_write is only supported with external ULPI PHYs");
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}
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critical_section::with(|cs| {
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let regs = self.regs.borrow(cs);
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// Begin ULPI register write transaction
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modify_reg!(otg_global, regs.global(), PHYCR,
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NEW: 1,
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RW: 1,
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ADDR: addr as u32,
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DATA: data as u32
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);
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// ULPI transactions should take less than 1us. 1000 iterations should be enough even for fast MCUs.
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let mut timeout = 1000;
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while timeout > 0 {
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// Wait for transaction to complete
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if read_reg!(otg_global, regs.global(), PHYCR, DONE) != 0 {
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return Ok(());
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}
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timeout -= 1;
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}
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Err(UlpiError::Timeout)
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})
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}
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}
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#[cfg(feature = "hs")]
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#[derive(Debug)]
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/// Errors that can occur while interfacing with a ULPI PHY.
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pub enum UlpiError {
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/// The action has timed out.
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Timeout,
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}
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pub(crate) struct EndpointAllocator<USB> {
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bitmap_in: u8,
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bitmap_out: u8,
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endpoints_in: [Option<EndpointIn>; 9],
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endpoints_out: [Option<EndpointOut>; 9],
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memory_allocator: EndpointMemoryAllocator<USB>,
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_marker: PhantomData<USB>,
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}
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impl<USB: UsbPeripheral> EndpointAllocator<USB> {
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fn new(memory: &'static mut [u32]) -> Self {
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assert!(USB::ENDPOINT_COUNT <= 9);
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Self {
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bitmap_in: 0,
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bitmap_out: 0,
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// [None; 9] requires Copy
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endpoints_in: [None, None, None, None, None, None, None, None, None],
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endpoints_out: [None, None, None, None, None, None, None, None, None],
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memory_allocator: EndpointMemoryAllocator::new(memory),
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_marker: PhantomData,
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}
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}
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fn alloc_number(bitmap: &mut u8, number: Option<u8>) -> Result<u8> {
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if let Some(number) = number {
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if number as usize >= USB::ENDPOINT_COUNT {
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return Err(UsbError::InvalidEndpoint);
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}
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if *bitmap & (1 << number) == 0 {
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*bitmap |= 1 << number;
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Ok(number)
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} else {
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Err(UsbError::InvalidEndpoint)
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}
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} else {
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// Skip EP0
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for number in 1..USB::ENDPOINT_COUNT {
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if *bitmap & (1 << number) == 0 {
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*bitmap |= 1 << number;
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return Ok(number as u8);
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}
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}
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Err(UsbError::EndpointOverflow)
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}
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}
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fn alloc(
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bitmap: &mut u8,
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config: &EndpointConfig,
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direction: UsbDirection,
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) -> Result<EndpointDescriptor> {
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let number = Self::alloc_number(bitmap, config.number)?;
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let address = EndpointAddress::from_parts(number as usize, direction);
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Ok(EndpointDescriptor {
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address,
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ep_type: config.ep_type,
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max_packet_size: config.max_packet_size,
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interval: config.interval,
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})
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}
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fn alloc_in(&mut self, config: &EndpointConfig) -> Result<EndpointIn> {
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let descr = Self::alloc(&mut self.bitmap_in, config, UsbDirection::In)?;
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self.memory_allocator
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.allocate_tx_buffer(descr.address.index() as u8, descr.max_packet_size as usize)?;
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let ep = EndpointIn::new::<USB>(descr);
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Ok(ep)
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}
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fn alloc_out(&mut self, config: &EndpointConfig) -> Result<EndpointOut> {
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let descr = Self::alloc(&mut self.bitmap_out, config, UsbDirection::Out)?;
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let buffer = self
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.memory_allocator
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.allocate_rx_buffer(descr.max_packet_size as usize)?;
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let ep = EndpointOut::new::<USB>(descr, buffer);
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Ok(ep)
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}
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fn alloc_ep(
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&mut self,
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ep_dir: UsbDirection,
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ep_addr: Option<EndpointAddress>,
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ep_type: EndpointType,
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max_packet_size: u16,
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interval: u8,
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) -> Result<EndpointAddress> {
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let ep_type = unsafe { core::mem::transmute(ep_type) };
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let number = ep_addr.map(|a| a.index() as u8);
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let config = EndpointConfig {
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ep_type,
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max_packet_size,
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interval,
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number,
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pair_of: None,
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};
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match ep_dir {
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UsbDirection::Out => {
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let ep = self.alloc_out(&config)?;
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let address = ep.address();
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self.endpoints_out[address.index()] = Some(ep);
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Ok(address)
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}
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UsbDirection::In => {
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let ep = self.alloc_in(&config)?;
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let address = ep.address();
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self.endpoints_in[address.index()] = Some(ep);
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Ok(address)
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}
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}
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}
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}
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impl<USB: UsbPeripheral> usb_device::bus::UsbBus for UsbBus<USB> {
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fn alloc_ep(
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&mut self,
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ep_dir: UsbDirection,
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ep_addr: Option<EndpointAddress>,
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ep_type: EndpointType,
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max_packet_size: u16,
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interval: u8,
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) -> Result<EndpointAddress> {
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self.allocator
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.alloc_ep(ep_dir, ep_addr, ep_type, max_packet_size, interval)
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}
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fn enable(&mut self) {
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// Enable USB_OTG in RCC
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USB::enable();
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critical_section::with(|cs| {
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let regs = self.regs.borrow(cs);
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let core_id = read_reg!(otg_global, regs.global(), CID);
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// Wait for AHB ready
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while read_reg!(otg_global, regs.global(), GRSTCTL, AHBIDL) == 0 {}
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// Configure OTG as device
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#[cfg(feature = "fs")]
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modify_reg!(otg_global, regs.global(), GUSBCFG,
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SRPCAP: 0, // SRP capability is not enabled
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FDMOD: 1 // Force device mode
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);
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#[cfg(feature = "hs")]
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modify_reg!(otg_global, regs.global(), GUSBCFG,
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SRPCAP: 0, // SRP capability is not enabled
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TOCAL: 0x1,
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FDMOD: 1 // Force device mode
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);
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// Configure USB PHY
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#[cfg(feature = "hs")]
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match self.peripheral.phy_type() {
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PhyType::InternalFullSpeed => {
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// Select FS Embedded PHY
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modify_reg!(otg_global, regs.global(), GUSBCFG, PHYSEL: 1);
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}
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PhyType::InternalHighSpeed => {
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// Turn off PHY
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modify_reg!(otg_global, regs.global(), GCCFG, PWRDWN: 0);
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// Init The UTMI Interface
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modify_reg!(otg_global, regs.global(), GUSBCFG,
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TSDPS: 0,
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ULPIFSLS: 0,
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PHYSEL: 0 // ULPI or UTMI
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);
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// Select VBUS source
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modify_reg!(otg_global, regs.global(), GUSBCFG,
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ULPIEVBUSD: 0,
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ULPIEVBUSI: 0
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);
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// Select UTMI Interace
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//modify_reg!(otg_global, regs.global(), GUSBCFG, ULPISEL: 0);
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modify_reg!(otg_global, regs.global(), GUSBCFG, |r| r & !(1 << 4));
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// This is a secret bit from ST that is not mentioned anywhere except
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// the driver code shipped with STM32CubeIDE.
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//modify_reg!(otg_global, regs.global(), GCCFG, PHYHSEN: 1);
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modify_reg!(otg_global, regs.global(), GCCFG, |r| r | (1 << 23));
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self.peripheral.setup_internal_hs_phy();
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}
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PhyType::ExternalHighSpeed => {
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// Turn off embedded PHY
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modify_reg!(otg_global, regs.global(), GCCFG, PWRDWN: 0);
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// Init The ULPI Interface
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modify_reg!(otg_global, regs.global(), GUSBCFG,
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TSDPS: 0,
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ULPIFSLS: 0,
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PHYSEL: 0 // ULPI or UTMI
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);
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// Select VBUS source
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modify_reg!(otg_global, regs.global(), GUSBCFG,
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ULPIEVBUSD: 0,
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ULPIEVBUSI: 0
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);
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}
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}
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// Perform core soft-reset
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while read_reg!(otg_global, regs.global(), GRSTCTL, AHBIDL) == 0 {}
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modify_reg!(otg_global, regs.global(), GRSTCTL, CSRST: 1);
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while read_reg!(otg_global, regs.global(), GRSTCTL, CSRST) == 1 {}
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if self.peripheral.phy_type() == PhyType::InternalFullSpeed {
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// Activate the USB Transceiver
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modify_reg!(otg_global, regs.global(), GCCFG, PWRDWN: 1);
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}
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// Configuring Vbus sense and SOF output
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match core_id {
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0x0000_1200 | 0x0000_1100 => {
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// F429-like chips have the GCCFG.NOVBUSSENS bit
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//modify_reg!(otg_global, regs.global, GCCFG, NOVBUSSENS: 1);
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modify_reg!(otg_global, regs.global(), GCCFG, |r| r | (1 << 21));
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modify_reg!(otg_global, regs.global(), GCCFG, VBUSASEN: 0, VBUSBSEN: 0, SOFOUTEN: 0);
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}
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0x0000_2000 | 0x0000_2100 | 0x0000_2300 | 0x0000_3000 | 0x0000_3100 => {
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// F446-like chips have the GCCFG.VBDEN bit with the opposite meaning
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//modify_reg!(otg_global, regs.global, GCCFG, VBDEN: 0);
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modify_reg!(otg_global, regs.global(), GCCFG, |r| r & !(1 << 21));
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// Force B-peripheral session
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|
//modify_reg!(otg_global, regs.global, GOTGCTL, BVALOEN: 1, BVALOVAL: 1);
|
|
modify_reg!(otg_global, regs.global(), GOTGCTL, |r| r | (0b11 << 6));
|
|
}
|
|
_ => {}
|
|
}
|
|
|
|
// Enable PHY clock
|
|
write_reg!(otg_pwrclk, regs.pwrclk(), PCGCCTL, 0);
|
|
|
|
// Soft disconnect device
|
|
modify_reg!(otg_device, regs.device(), DCTL, SDIS: 1);
|
|
|
|
// Setup USB speed and frame interval
|
|
let speed = match (USB::HIGH_SPEED, self.peripheral.phy_type()) {
|
|
(false, _) => 0b11,
|
|
(true, PhyType::InternalFullSpeed) => 0b11,
|
|
(true, PhyType::InternalHighSpeed) => 0b00,
|
|
(true, PhyType::ExternalHighSpeed) => 0b00,
|
|
};
|
|
modify_reg!(otg_device, regs.device(), DCFG,
|
|
PFIVL: 0b00,
|
|
DSPD: speed
|
|
);
|
|
#[cfg(feature = "xcvrdly")]
|
|
modify_reg!(otg_device, regs.device(), DCFG, XCVRDLY: 1);
|
|
|
|
// unmask EP interrupts
|
|
write_reg!(otg_device, regs.device(), DIEPMSK, XFRCM: 1);
|
|
|
|
// unmask core interrupts
|
|
write_reg!(otg_global, regs.global(), GINTMSK,
|
|
USBRST: 1, ENUMDNEM: 1,
|
|
USBSUSPM: 1, WUIM: 1,
|
|
IEPINT: 1, RXFLVLM: 1,
|
|
IISOIXFRM: 1
|
|
);
|
|
|
|
// clear pending interrupts
|
|
write_reg!(otg_global, regs.global(), GINTSTS, 0xffffffff);
|
|
|
|
// unmask global interrupt
|
|
modify_reg!(otg_global, regs.global(), GAHBCFG, GINT: 1);
|
|
|
|
// connect(true)
|
|
modify_reg!(otg_device, regs.device(), DCTL, SDIS: 0);
|
|
});
|
|
}
|
|
|
|
fn reset(&self) {
|
|
critical_section::with(|cs| {
|
|
let regs = self.regs.borrow(cs);
|
|
|
|
self.configure_all(cs);
|
|
|
|
modify_reg!(otg_device, regs.device(), DCFG, DAD: 0);
|
|
});
|
|
}
|
|
|
|
fn set_device_address(&self, addr: u8) {
|
|
critical_section::with(|cs| {
|
|
let regs = self.regs.borrow(cs);
|
|
|
|
modify_reg!(otg_device, regs.device(), DCFG, DAD: addr as u32);
|
|
});
|
|
}
|
|
|
|
fn write(&self, ep_addr: EndpointAddress, buf: &[u8]) -> Result<usize> {
|
|
if !ep_addr.is_in() || ep_addr.index() >= USB::ENDPOINT_COUNT {
|
|
return Err(UsbError::InvalidEndpoint);
|
|
}
|
|
if let Some(ep) = &self.allocator.endpoints_in[ep_addr.index()] {
|
|
ep.write(buf).map(|_| buf.len())
|
|
} else {
|
|
Err(UsbError::InvalidEndpoint)
|
|
}
|
|
}
|
|
|
|
fn read(&self, ep_addr: EndpointAddress, buf: &mut [u8]) -> Result<usize> {
|
|
if !ep_addr.is_out() || ep_addr.index() >= USB::ENDPOINT_COUNT {
|
|
return Err(UsbError::InvalidEndpoint);
|
|
}
|
|
|
|
if let Some(ep) = &self.allocator.endpoints_out[ep_addr.index()] {
|
|
ep.read(buf)
|
|
} else {
|
|
Err(UsbError::InvalidEndpoint)
|
|
}
|
|
}
|
|
|
|
fn set_stalled(&self, ep_addr: EndpointAddress, stalled: bool) {
|
|
if ep_addr.index() >= USB::ENDPOINT_COUNT {
|
|
return;
|
|
}
|
|
|
|
let regs = UsbRegisters::new::<USB>();
|
|
crate::endpoint::set_stalled(regs, ep_addr, stalled)
|
|
}
|
|
|
|
fn is_stalled(&self, ep_addr: EndpointAddress) -> bool {
|
|
if ep_addr.index() >= USB::ENDPOINT_COUNT {
|
|
return true;
|
|
}
|
|
|
|
let regs = UsbRegisters::new::<USB>();
|
|
crate::endpoint::is_stalled(regs, ep_addr)
|
|
}
|
|
|
|
fn suspend(&self) {
|
|
// Nothing to do here?
|
|
}
|
|
|
|
fn resume(&self) {
|
|
// Nothing to do here?
|
|
}
|
|
|
|
fn poll(&self) -> PollResult {
|
|
critical_section::with(|cs| {
|
|
let regs = self.regs.borrow(cs);
|
|
|
|
let core_id = read_reg!(otg_global, regs.global(), CID);
|
|
|
|
let (wakeup, suspend, enum_done, reset, iep, rxflvl, iisoixfr) = read_reg!(
|
|
otg_global,
|
|
regs.global(),
|
|
GINTSTS,
|
|
WKUPINT,
|
|
USBSUSP,
|
|
ENUMDNE,
|
|
USBRST,
|
|
IEPINT,
|
|
RXFLVL,
|
|
IISOIXFR
|
|
);
|
|
|
|
if reset != 0 {
|
|
write_reg!(otg_global, regs.global(), GINTSTS, USBRST: 1);
|
|
|
|
self.deconfigure_all(cs);
|
|
|
|
// Flush RX
|
|
modify_reg!(otg_global, regs.global(), GRSTCTL, RXFFLSH: 1);
|
|
while read_reg!(otg_global, regs.global(), GRSTCTL, RXFFLSH) == 1 {}
|
|
}
|
|
|
|
if enum_done != 0 {
|
|
write_reg!(otg_global, regs.global(), GINTSTS, ENUMDNE: 1);
|
|
|
|
let speed = read_reg!(otg_device, regs.device(), DSTS, ENUMSPD);
|
|
|
|
// Compute and update TRDT
|
|
let mut trdt = 0;
|
|
match speed {
|
|
0b00 => {
|
|
// High speed
|
|
|
|
// From RM0431 (F72xx), RM0090 (F429), RM0390 (F446)
|
|
if self.peripheral.ahb_frequency_hz() >= 30_000_000 {
|
|
trdt = 0x9;
|
|
} else {
|
|
panic!("AHB frequency is too low")
|
|
}
|
|
}
|
|
0b01 | 0b11 => {
|
|
// Full speed
|
|
|
|
// From RM0431 (F72xx), RM0090 (F429)
|
|
#[cfg(not(feature = "esp32sx"))]
|
|
let _trdt = match self.peripheral.ahb_frequency_hz() {
|
|
0..=14_199_999 => panic!("AHB frequency is too low"),
|
|
14_200_000..=14_999_999 => 0xF,
|
|
15_000_000..=15_999_999 => 0xE,
|
|
16_000_000..=17_199_999 => 0xD,
|
|
17_200_000..=18_499_999 => 0xC,
|
|
18_500_000..=19_999_999 => 0xB,
|
|
20_000_000..=21_799_999 => 0xA,
|
|
21_800_000..=23_999_999 => 0x9,
|
|
24_000_000..=27_499_999 => 0x8,
|
|
27_500_000..=31_999_999 => 0x7, // 27.7..32 in code from CubeIDE
|
|
32_000_000..=u32::MAX => 0x6,
|
|
};
|
|
|
|
#[cfg(feature = "esp32sx")]
|
|
let _trdt = 5;
|
|
|
|
trdt = trdt;
|
|
}
|
|
_ => unimplemented!(),
|
|
}
|
|
modify_reg!(otg_global, regs.global(), GUSBCFG, TRDT: trdt);
|
|
|
|
PollResult::Reset
|
|
} else if wakeup != 0 {
|
|
// Clear the interrupt
|
|
write_reg!(otg_global, regs.global(), GINTSTS, WKUPINT: 1);
|
|
|
|
PollResult::Resume
|
|
} else if suspend != 0 {
|
|
write_reg!(otg_global, regs.global(), GINTSTS, USBSUSP: 1);
|
|
|
|
PollResult::Suspend
|
|
} else if iisoixfr != 0 {
|
|
use crate::ral::endpoint_in;
|
|
|
|
// Incomplete isochronous IN transfer; see
|
|
// RM0383 Rev 3 pp797 "Incomplete isochronous IN data transfers"
|
|
write_reg!(otg_global, regs.global(), GINTSTS, IISOIXFR: 1);
|
|
|
|
let in_endpoints = self
|
|
.allocator
|
|
.endpoints_in
|
|
.iter()
|
|
.flatten()
|
|
.map(|ep| ep.address().index());
|
|
|
|
let mut iep: u16 = 0;
|
|
|
|
for epnum in in_endpoints {
|
|
let ep_regs = regs.endpoint_in(epnum);
|
|
|
|
// Filter out non-isochronous endpoints
|
|
if read_reg!(endpoint_in, ep_regs, DIEPCTL, EPTYP) & 0x11 != 0x01 {
|
|
continue;
|
|
}
|
|
|
|
// RM0383 states that the NAK bit in DIEPINT is set when a
|
|
// zero length packet is transmitted due to unavailability
|
|
// of data in the Tx FIFO.
|
|
// However, this bit is not defined in the RAL and
|
|
// by checking several STM32 RMs, it's even unclear
|
|
// if it actually exists on OTG_FS peripherals.
|
|
// While testing with macOS, the bit was never set.
|
|
// Therefore, an alternative method is used to check if
|
|
// an endpoint is affected.
|
|
// TODO: investigate if this check works correctly and
|
|
// does not affect other isochronous IN endpoints by mistake.
|
|
if read_reg!(endpoint_in, ep_regs, DIEPCTL, NAKSTS) == 1 {
|
|
continue;
|
|
}
|
|
|
|
// Set NAK
|
|
modify_reg!(endpoint_in, ep_regs, DIEPCTL, SNAK: 1);
|
|
while read_reg!(endpoint_in, ep_regs, DIEPINT, INEPNE) == 0 {}
|
|
|
|
// Disable the endpoint
|
|
modify_reg!(endpoint_in, ep_regs, DIEPCTL, SNAK: 1, EPDIS: 1);
|
|
while read_reg!(endpoint_in, ep_regs, DIEPINT, EPDISD) == 0 {}
|
|
modify_reg!(endpoint_in, ep_regs, DIEPINT, EPDISD: 1);
|
|
|
|
// Flush the TX FIFO
|
|
modify_reg!(otg_global, regs.global(), GRSTCTL, TXFNUM: epnum as u32, TXFFLSH: 1);
|
|
while read_reg!(otg_global, regs.global(), GRSTCTL, TXFFLSH) == 1 {}
|
|
|
|
iep |= 1 << epnum;
|
|
}
|
|
|
|
PollResult::Data {
|
|
ep_out: 0,
|
|
ep_in_complete: iep,
|
|
ep_setup: 0,
|
|
}
|
|
} else {
|
|
let mut ep_out = 0;
|
|
let mut ep_in_complete = 0;
|
|
let mut ep_setup = 0;
|
|
|
|
use crate::ral::{endpoint_in, endpoint_out};
|
|
|
|
// RXFLVL & IEPINT flags are read-only, there is no need to clear them
|
|
if rxflvl != 0 {
|
|
let (epnum, data_size, status) =
|
|
read_reg!(otg_global, regs.global(), GRXSTSR, EPNUM, BCNT, PKTSTS);
|
|
match status {
|
|
0x02 => {
|
|
// OUT received
|
|
ep_out |= 1 << epnum;
|
|
}
|
|
0x06 => {
|
|
// SETUP received
|
|
// flushing TX if something stuck in control endpoint
|
|
let ep = regs.endpoint_in(epnum as usize);
|
|
if read_reg!(endpoint_in, ep, DIEPTSIZ, PKTCNT) != 0 {
|
|
modify_reg!(otg_global, regs.global(), GRSTCTL, TXFNUM: epnum, TXFFLSH: 1);
|
|
while read_reg!(otg_global, regs.global(), GRSTCTL, TXFFLSH) == 1 {}
|
|
}
|
|
ep_setup |= 1 << epnum;
|
|
}
|
|
0x03 | 0x04 => {
|
|
// OUT completed | SETUP completed
|
|
// Re-enable the endpoint, F429-like chips only
|
|
if core_id == 0x4f54_400a
|
|
|| core_id == 0x0000_1200
|
|
|| core_id == 0x0000_1100
|
|
{
|
|
let ep = regs.endpoint_out(epnum as usize);
|
|
modify_reg!(endpoint_out, ep, DOEPCTL, CNAK: 1, EPENA: 1);
|
|
}
|
|
read_reg!(otg_global, regs.global(), GRXSTSP); // pop GRXSTSP
|
|
}
|
|
_ => {
|
|
read_reg!(otg_global, regs.global(), GRXSTSP); // pop GRXSTSP
|
|
}
|
|
}
|
|
|
|
if status == 0x02 || status == 0x06 {
|
|
if let Some(ep) = &self.allocator.endpoints_out[epnum as usize] {
|
|
let mut buffer = ep.buffer.borrow_ref_mut(cs);
|
|
if buffer.state() == EndpointBufferState::Empty {
|
|
read_reg!(otg_global, regs.global(), GRXSTSP); // pop GRXSTSP
|
|
|
|
let is_setup = status == 0x06;
|
|
buffer
|
|
.fill_from_fifo(*regs, data_size as u16, is_setup)
|
|
.ok();
|
|
|
|
// Re-enable the endpoint, F446-like chips only
|
|
if core_id == 0x4f54_400a
|
|
|| core_id == 0x0000_2000
|
|
|| core_id == 0x0000_2100
|
|
|| core_id == 0x0000_2300
|
|
|| core_id == 0x0000_3000
|
|
|| core_id == 0x0000_3100
|
|
{
|
|
let ep = regs.endpoint_out(epnum as usize);
|
|
modify_reg!(endpoint_out, ep, DOEPCTL, CNAK: 1, EPENA: 1);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
if iep != 0 {
|
|
for ep in &self.allocator.endpoints_in {
|
|
if let Some(ep) = ep {
|
|
let ep_regs = regs.endpoint_in(ep.address().index());
|
|
if read_reg!(endpoint_in, ep_regs, DIEPINT, XFRC) != 0 {
|
|
write_reg!(endpoint_in, ep_regs, DIEPINT, XFRC: 1);
|
|
ep_in_complete |= 1 << ep.address().index();
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
for ep in &self.allocator.endpoints_out {
|
|
if let Some(ep) = ep {
|
|
match ep.buffer_state() {
|
|
EndpointBufferState::DataOut => {
|
|
ep_out |= 1 << ep.address().index();
|
|
}
|
|
EndpointBufferState::DataSetup => {
|
|
ep_setup |= 1 << ep.address().index();
|
|
}
|
|
EndpointBufferState::Empty => {}
|
|
}
|
|
}
|
|
}
|
|
|
|
if (ep_in_complete | ep_out | ep_setup) != 0 {
|
|
PollResult::Data {
|
|
ep_out,
|
|
ep_in_complete,
|
|
ep_setup,
|
|
}
|
|
} else {
|
|
PollResult::None
|
|
}
|
|
}
|
|
})
|
|
}
|
|
|
|
const QUIRK_SET_ADDRESS_BEFORE_STATUS: bool = true;
|
|
}
|