swaitsandClaude Opus 4.6
3102fc747a
Implement full SSD1306 OLED display support: - Splash screen on boot (1.5s) with project name, version, board - Dashboard showing radio state, config, counters, RSSI/SNR - RSSI history sparkline (64-sample ring buffer, 2px-wide bars) - DisplayOn/DisplayOff host commands routed via dedicated channel - Pure render functions against generic DrawTarget (no hardware coupling) - Display on/off control bypasses radio task entirely Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
33 lines
1.3 KiB
Rust
33 lines
1.3 KiB
Rust
#[doc = "Register `INT_CLR` writer"]
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pub type W = crate::W<INT_CLR_SPEC>;
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#[doc = "Field `INT_CLR` writer - Set this bit to 1 to clear AES interrupt."]
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pub type INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
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#[cfg(feature = "impl-register-debug")]
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impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
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fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
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write!(f, "(not readable)")
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}
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}
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impl W {
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#[doc = "Bit 0 - Set this bit to 1 to clear AES interrupt."]
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#[inline(always)]
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pub fn int_clr(&mut self) -> INT_CLR_W<INT_CLR_SPEC> {
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INT_CLR_W::new(self, 0)
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}
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}
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#[doc = "AES Interrupt clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
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pub struct INT_CLR_SPEC;
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impl crate::RegisterSpec for INT_CLR_SPEC {
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type Ux = u32;
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}
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#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
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impl crate::Writable for INT_CLR_SPEC {
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type Safety = crate::Unsafe;
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const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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}
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#[doc = "`reset()` method sets INT_CLR to value 0"]
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impl crate::Resettable for INT_CLR_SPEC {
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const RESET_VALUE: u32 = 0;
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}
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