swaitsandClaude Opus 4.6
3102fc747a
Implement full SSD1306 OLED display support: - Splash screen on boot (1.5s) with project name, version, board - Dashboard showing radio state, config, counters, RSSI/SNR - RSSI history sparkline (64-sample ring buffer, 2px-wide bars) - DisplayOn/DisplayOff host commands routed via dedicated channel - Pure render functions against generic DrawTarget (no hardware coupling) - Display on/off control bypasses radio task entirely Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
48 lines
2.4 KiB
Rust
48 lines
2.4 KiB
Rust
#[doc = "Register `CACHE_MMU_OWNER` reader"]
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pub type R = crate::R<CACHE_MMU_OWNER_SPEC>;
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#[doc = "Register `CACHE_MMU_OWNER` writer"]
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pub type W = crate::W<CACHE_MMU_OWNER_SPEC>;
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#[doc = "Field `CACHE_MMU_OWNER` reader - The bits are used to specify the owner of MMU.bit0: icache, bit1: dcache, bit2: dma, bit3: reserved."]
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pub type CACHE_MMU_OWNER_R = crate::FieldReader<u32>;
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#[doc = "Field `CACHE_MMU_OWNER` writer - The bits are used to specify the owner of MMU.bit0: icache, bit1: dcache, bit2: dma, bit3: reserved."]
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pub type CACHE_MMU_OWNER_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
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impl R {
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#[doc = "Bits 0:23 - The bits are used to specify the owner of MMU.bit0: icache, bit1: dcache, bit2: dma, bit3: reserved."]
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#[inline(always)]
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pub fn cache_mmu_owner(&self) -> CACHE_MMU_OWNER_R {
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CACHE_MMU_OWNER_R::new(self.bits & 0x00ff_ffff)
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}
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}
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#[cfg(feature = "impl-register-debug")]
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impl core::fmt::Debug for R {
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fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
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f.debug_struct("CACHE_MMU_OWNER")
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.field("cache_mmu_owner", &self.cache_mmu_owner())
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.finish()
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}
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}
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impl W {
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#[doc = "Bits 0:23 - The bits are used to specify the owner of MMU.bit0: icache, bit1: dcache, bit2: dma, bit3: reserved."]
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#[inline(always)]
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pub fn cache_mmu_owner(&mut self) -> CACHE_MMU_OWNER_W<CACHE_MMU_OWNER_SPEC> {
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CACHE_MMU_OWNER_W::new(self, 0)
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}
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}
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#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_mmu_owner::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_mmu_owner::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
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pub struct CACHE_MMU_OWNER_SPEC;
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impl crate::RegisterSpec for CACHE_MMU_OWNER_SPEC {
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type Ux = u32;
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}
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#[doc = "`read()` method returns [`cache_mmu_owner::R`](R) reader structure"]
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impl crate::Readable for CACHE_MMU_OWNER_SPEC {}
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#[doc = "`write(|w| ..)` method takes [`cache_mmu_owner::W`](W) writer structure"]
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impl crate::Writable for CACHE_MMU_OWNER_SPEC {
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type Safety = crate::Unsafe;
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const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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}
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#[doc = "`reset()` method sets CACHE_MMU_OWNER to value 0"]
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impl crate::Resettable for CACHE_MMU_OWNER_SPEC {
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const RESET_VALUE: u32 = 0;
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}
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