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donglora/vendor/esp32s3/src/extmem/cache_request.rs
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swaitsandClaude Opus 4.6 3102fc747a feat: add display UI with splash screen, dashboard, and RSSI sparkline
Implement full SSD1306 OLED display support:
- Splash screen on boot (1.5s) with project name, version, board
- Dashboard showing radio state, config, counters, RSSI/SNR
- RSSI history sparkline (64-sample ring buffer, 2px-wide bars)
- DisplayOn/DisplayOff host commands routed via dedicated channel
- Pure render functions against generic DrawTarget (no hardware coupling)
- Display on/off control bypasses radio task entirely

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
2026-03-29 20:42:54 -06:00

48 lines
2.2 KiB
Rust

#[doc = "Register `CACHE_REQUEST` reader"]
pub type R = crate::R<CACHE_REQUEST_SPEC>;
#[doc = "Register `CACHE_REQUEST` writer"]
pub type W = crate::W<CACHE_REQUEST_SPEC>;
#[doc = "Field `BYPASS` reader - The bit is used to disable request recording which could cause performance issue"]
pub type BYPASS_R = crate::BitReader;
#[doc = "Field `BYPASS` writer - The bit is used to disable request recording which could cause performance issue"]
pub type BYPASS_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - The bit is used to disable request recording which could cause performance issue"]
#[inline(always)]
pub fn bypass(&self) -> BYPASS_R {
BYPASS_R::new((self.bits & 1) != 0)
}
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("CACHE_REQUEST")
.field("bypass", &self.bypass())
.finish()
}
}
impl W {
#[doc = "Bit 0 - The bit is used to disable request recording which could cause performance issue"]
#[inline(always)]
pub fn bypass(&mut self) -> BYPASS_W<CACHE_REQUEST_SPEC> {
BYPASS_W::new(self, 0)
}
}
#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`cache_request::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_request::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CACHE_REQUEST_SPEC;
impl crate::RegisterSpec for CACHE_REQUEST_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [`cache_request::R`](R) reader structure"]
impl crate::Readable for CACHE_REQUEST_SPEC {}
#[doc = "`write(|w| ..)` method takes [`cache_request::W`](W) writer structure"]
impl crate::Writable for CACHE_REQUEST_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CACHE_REQUEST to value 0"]
impl crate::Resettable for CACHE_REQUEST_SPEC {
const RESET_VALUE: u32 = 0;
}