swaitsandClaude Opus 4.6
3102fc747a
Implement full SSD1306 OLED display support: - Splash screen on boot (1.5s) with project name, version, board - Dashboard showing radio state, config, counters, RSSI/SNR - RSSI history sparkline (64-sample ring buffer, 2px-wide bars) - DisplayOn/DisplayOff host commands routed via dedicated channel - Pure render functions against generic DrawTarget (no hardware coupling) - Display on/off control bypasses radio task entirely Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
48 lines
2.0 KiB
Rust
48 lines
2.0 KiB
Rust
#[doc = "Register `CLOCK_GATE` reader"]
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pub type R = crate::R<CLOCK_GATE_SPEC>;
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#[doc = "Register `CLOCK_GATE` writer"]
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pub type W = crate::W<CLOCK_GATE_SPEC>;
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#[doc = "Field `CLK_EN` reader - ******* Description ***********"]
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pub type CLK_EN_R = crate::BitReader;
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#[doc = "Field `CLK_EN` writer - ******* Description ***********"]
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pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
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impl R {
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#[doc = "Bit 0 - ******* Description ***********"]
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#[inline(always)]
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pub fn clk_en(&self) -> CLK_EN_R {
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CLK_EN_R::new((self.bits & 1) != 0)
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}
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}
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#[cfg(feature = "impl-register-debug")]
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impl core::fmt::Debug for R {
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fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
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f.debug_struct("CLOCK_GATE")
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.field("clk_en", &self.clk_en())
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.finish()
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}
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}
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impl W {
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#[doc = "Bit 0 - ******* Description ***********"]
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#[inline(always)]
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pub fn clk_en(&mut self) -> CLK_EN_W<CLOCK_GATE_SPEC> {
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CLK_EN_W::new(self, 0)
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}
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}
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#[doc = "******* Description ***********\n\nYou can [`read`](crate::Reg::read) this register and get [`clock_gate::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clock_gate::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
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pub struct CLOCK_GATE_SPEC;
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impl crate::RegisterSpec for CLOCK_GATE_SPEC {
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type Ux = u32;
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}
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#[doc = "`read()` method returns [`clock_gate::R`](R) reader structure"]
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impl crate::Readable for CLOCK_GATE_SPEC {}
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#[doc = "`write(|w| ..)` method takes [`clock_gate::W`](W) writer structure"]
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impl crate::Writable for CLOCK_GATE_SPEC {
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type Safety = crate::Unsafe;
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const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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}
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#[doc = "`reset()` method sets CLOCK_GATE to value 0x01"]
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impl crate::Resettable for CLOCK_GATE_SPEC {
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const RESET_VALUE: u32 = 0x01;
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}
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