swaitsandClaude Opus 4.6
3102fc747a
Implement full SSD1306 OLED display support: - Splash screen on boot (1.5s) with project name, version, board - Dashboard showing radio state, config, counters, RSSI/SNR - RSSI history sparkline (64-sample ring buffer, 2px-wide bars) - DisplayOn/DisplayOff host commands routed via dedicated channel - Pure render functions against generic DrawTarget (no hardware coupling) - Display on/off control bypasses radio task entirely Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
111 lines
4.8 KiB
Rust
111 lines
4.8 KiB
Rust
#[doc = "Register `JFIFO_ST` reader"]
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pub type R = crate::R<JFIFO_ST_SPEC>;
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#[doc = "Register `JFIFO_ST` writer"]
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pub type W = crate::W<JFIFO_ST_SPEC>;
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#[doc = "Field `IN_FIFO_CNT` reader - JTAT in fifo counter."]
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pub type IN_FIFO_CNT_R = crate::FieldReader;
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#[doc = "Field `IN_FIFO_EMPTY` reader - 1: JTAG in fifo is empty."]
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pub type IN_FIFO_EMPTY_R = crate::BitReader;
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#[doc = "Field `IN_FIFO_FULL` reader - 1: JTAG in fifo is full."]
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pub type IN_FIFO_FULL_R = crate::BitReader;
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#[doc = "Field `OUT_FIFO_CNT` reader - JTAT out fifo counter."]
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pub type OUT_FIFO_CNT_R = crate::FieldReader;
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#[doc = "Field `OUT_FIFO_EMPTY` reader - 1: JTAG out fifo is empty."]
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pub type OUT_FIFO_EMPTY_R = crate::BitReader;
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#[doc = "Field `OUT_FIFO_FULL` reader - 1: JTAG out fifo is full."]
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pub type OUT_FIFO_FULL_R = crate::BitReader;
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#[doc = "Field `IN_FIFO_RESET` reader - Write 1 to reset JTAG in fifo."]
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pub type IN_FIFO_RESET_R = crate::BitReader;
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#[doc = "Field `IN_FIFO_RESET` writer - Write 1 to reset JTAG in fifo."]
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pub type IN_FIFO_RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `OUT_FIFO_RESET` reader - Write 1 to reset JTAG out fifo."]
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pub type OUT_FIFO_RESET_R = crate::BitReader;
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#[doc = "Field `OUT_FIFO_RESET` writer - Write 1 to reset JTAG out fifo."]
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pub type OUT_FIFO_RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
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impl R {
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#[doc = "Bits 0:1 - JTAT in fifo counter."]
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#[inline(always)]
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pub fn in_fifo_cnt(&self) -> IN_FIFO_CNT_R {
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IN_FIFO_CNT_R::new((self.bits & 3) as u8)
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}
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#[doc = "Bit 2 - 1: JTAG in fifo is empty."]
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#[inline(always)]
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pub fn in_fifo_empty(&self) -> IN_FIFO_EMPTY_R {
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IN_FIFO_EMPTY_R::new(((self.bits >> 2) & 1) != 0)
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}
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#[doc = "Bit 3 - 1: JTAG in fifo is full."]
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#[inline(always)]
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pub fn in_fifo_full(&self) -> IN_FIFO_FULL_R {
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IN_FIFO_FULL_R::new(((self.bits >> 3) & 1) != 0)
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}
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#[doc = "Bits 4:5 - JTAT out fifo counter."]
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#[inline(always)]
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pub fn out_fifo_cnt(&self) -> OUT_FIFO_CNT_R {
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OUT_FIFO_CNT_R::new(((self.bits >> 4) & 3) as u8)
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}
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#[doc = "Bit 6 - 1: JTAG out fifo is empty."]
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#[inline(always)]
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pub fn out_fifo_empty(&self) -> OUT_FIFO_EMPTY_R {
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OUT_FIFO_EMPTY_R::new(((self.bits >> 6) & 1) != 0)
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}
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#[doc = "Bit 7 - 1: JTAG out fifo is full."]
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#[inline(always)]
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pub fn out_fifo_full(&self) -> OUT_FIFO_FULL_R {
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OUT_FIFO_FULL_R::new(((self.bits >> 7) & 1) != 0)
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}
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#[doc = "Bit 8 - Write 1 to reset JTAG in fifo."]
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#[inline(always)]
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pub fn in_fifo_reset(&self) -> IN_FIFO_RESET_R {
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IN_FIFO_RESET_R::new(((self.bits >> 8) & 1) != 0)
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}
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#[doc = "Bit 9 - Write 1 to reset JTAG out fifo."]
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#[inline(always)]
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pub fn out_fifo_reset(&self) -> OUT_FIFO_RESET_R {
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OUT_FIFO_RESET_R::new(((self.bits >> 9) & 1) != 0)
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}
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}
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#[cfg(feature = "impl-register-debug")]
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impl core::fmt::Debug for R {
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fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
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f.debug_struct("JFIFO_ST")
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.field("in_fifo_cnt", &self.in_fifo_cnt())
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.field("in_fifo_empty", &self.in_fifo_empty())
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.field("in_fifo_full", &self.in_fifo_full())
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.field("out_fifo_cnt", &self.out_fifo_cnt())
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.field("out_fifo_empty", &self.out_fifo_empty())
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.field("out_fifo_full", &self.out_fifo_full())
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.field("in_fifo_reset", &self.in_fifo_reset())
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.field("out_fifo_reset", &self.out_fifo_reset())
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.finish()
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}
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}
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impl W {
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#[doc = "Bit 8 - Write 1 to reset JTAG in fifo."]
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#[inline(always)]
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pub fn in_fifo_reset(&mut self) -> IN_FIFO_RESET_W<JFIFO_ST_SPEC> {
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IN_FIFO_RESET_W::new(self, 8)
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}
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#[doc = "Bit 9 - Write 1 to reset JTAG out fifo."]
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#[inline(always)]
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pub fn out_fifo_reset(&mut self) -> OUT_FIFO_RESET_W<JFIFO_ST_SPEC> {
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OUT_FIFO_RESET_W::new(self, 9)
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}
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}
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#[doc = "USB-JTAG FIFO status\n\nYou can [`read`](crate::Reg::read) this register and get [`jfifo_st::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`jfifo_st::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
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pub struct JFIFO_ST_SPEC;
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impl crate::RegisterSpec for JFIFO_ST_SPEC {
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type Ux = u32;
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}
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#[doc = "`read()` method returns [`jfifo_st::R`](R) reader structure"]
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impl crate::Readable for JFIFO_ST_SPEC {}
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#[doc = "`write(|w| ..)` method takes [`jfifo_st::W`](W) writer structure"]
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impl crate::Writable for JFIFO_ST_SPEC {
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type Safety = crate::Unsafe;
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const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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}
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#[doc = "`reset()` method sets JFIFO_ST to value 0x44"]
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impl crate::Resettable for JFIFO_ST_SPEC {
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const RESET_VALUE: u32 = 0x44;
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}
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