swaitsandClaude Opus 4.6
3102fc747a
Implement full SSD1306 OLED display support: - Splash screen on boot (1.5s) with project name, version, board - Dashboard showing radio state, config, counters, RSSI/SNR - RSSI history sparkline (64-sample ring buffer, 2px-wide bars) - DisplayOn/DisplayOff host commands routed via dedicated channel - Pure render functions against generic DrawTarget (no hardware coupling) - Display on/off control bypasses radio task entirely Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
654 lines
18 KiB
Rust
654 lines
18 KiB
Rust
//! mstatus register
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pub use super::misa::XLEN;
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use crate::bits::{bf_extract, bf_insert};
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/// mstatus register
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#[derive(Clone, Copy, Debug)]
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pub struct Mstatus {
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bits: usize,
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}
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impl From<usize> for Mstatus {
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#[inline]
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fn from(bits: usize) -> Self {
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Self { bits }
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}
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}
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/// Additional extension state
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#[derive(Copy, Clone, Debug, Eq, PartialEq)]
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pub enum XS {
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/// All off
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AllOff = 0,
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/// None dirty or clean, some on
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NoneDirtyOrClean = 1,
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/// None dirty, some clean
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NoneDirtySomeClean = 2,
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/// Some dirty
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SomeDirty = 3,
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}
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/// Floating-point extension state
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#[derive(Copy, Clone, Debug, Eq, PartialEq)]
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pub enum FS {
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Off = 0,
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Initial = 1,
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Clean = 2,
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Dirty = 3,
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}
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/// Vector extension state
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#[derive(Copy, Clone, Debug, Eq, PartialEq)]
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pub enum VS {
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Off = 0,
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Initial = 1,
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Clean = 2,
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Dirty = 3,
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}
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/// Machine Previous Privilege Mode
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#[derive(Copy, Clone, Debug, Eq, PartialEq)]
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pub enum MPP {
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Machine = 3,
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Supervisor = 1,
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User = 0,
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}
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/// Supervisor Previous Privilege Mode
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#[derive(Copy, Clone, Debug, Eq, PartialEq)]
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pub enum SPP {
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Supervisor = 1,
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User = 0,
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}
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/// Non-instruction-fetch memory endianness
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#[derive(Copy, Clone, Debug, Eq, PartialEq)]
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pub enum Endianness {
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BigEndian = 1,
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LittleEndian = 0,
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}
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impl From<bool> for Endianness {
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fn from(value: bool) -> Self {
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match value {
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true => Self::BigEndian,
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false => Self::LittleEndian,
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}
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}
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}
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impl Mstatus {
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/// Returns the contents of the register as raw bits
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#[inline]
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pub fn bits(&self) -> usize {
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self.bits
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}
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/// Supervisor Interrupt Enable
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#[inline]
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pub fn sie(&self) -> bool {
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bf_extract(self.bits, 1, 1) != 0
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}
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/// Update Supervisor Interrupt Enable
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///
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/// Note this updates a previously read [`Mstatus`] value, but does not
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/// affect the mstatus CSR itself. See [`set_sie`]/[`clear_sie`] to directly
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/// update the CSR.
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#[inline]
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pub fn set_sie(&mut self, sie: bool) {
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self.bits = bf_insert(self.bits, 1, 1, sie as usize);
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}
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/// Machine Interrupt Enable
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#[inline]
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pub fn mie(&self) -> bool {
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bf_extract(self.bits, 3, 1) != 0
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}
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/// Update Machine Interrupt Enable
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///
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/// Note this updates a previously read [`Mstatus`] value, but does not
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/// affect the mstatus CSR itself. See [`set_mie`]/[`clear_mie`] to directly
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/// update the CSR.
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#[inline]
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pub fn set_mie(&mut self, mie: bool) {
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self.bits = bf_insert(self.bits, 3, 1, mie as usize);
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}
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/// Supervisor Previous Interrupt Enable
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#[inline]
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pub fn spie(&self) -> bool {
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bf_extract(self.bits, 5, 1) != 0
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}
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/// Update Supervisor Previous Interrupt Enable
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///
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/// Note this updates a previously read [`Mstatus`] value, but does not
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/// affect the mstatus CSR itself. See [`set_spie`]` to directly update the
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/// CSR.
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#[inline]
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pub fn set_spie(&mut self, spie: bool) {
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self.bits = bf_insert(self.bits, 5, 1, spie as usize);
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}
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/// U-mode non-instruction-fetch memory endianness
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#[inline]
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pub fn ube(&self) -> Endianness {
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Endianness::from(bf_extract(self.bits, 6, 1) != 0)
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}
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/// Update U-mode non-instruction-fetch memory endianness
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///
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/// Note this updates a previously read [`Mstatus`] value, but does not
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/// affect the mstatus CSR itself. See [`set_ube`] to directly update the
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/// CSR.
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#[inline]
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pub fn set_ube(&mut self, endianness: Endianness) {
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self.bits = bf_insert(self.bits, 6, 1, endianness as usize);
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}
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/// Machine Previous Interrupt Enable
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#[inline]
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pub fn mpie(&self) -> bool {
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bf_extract(self.bits, 7, 1) != 0
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}
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/// Update Machine Previous Interrupt Enable
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///
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/// Note this updates a previously read [`Mstatus`] value, but does not
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/// affect the mstatus CSR itself. See [`set_mpie`] to directly update the
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/// CSR.
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#[inline]
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pub fn set_mpie(&mut self, mpie: bool) {
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self.bits = bf_insert(self.bits, 7, 1, mpie as usize);
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}
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/// Supervisor Previous Privilege Mode
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#[inline]
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pub fn spp(&self) -> SPP {
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match bf_extract(self.bits, 8, 1) != 0 {
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true => SPP::Supervisor,
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false => SPP::User,
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}
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}
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/// Update Supervisor Previous Privilege Mode
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///
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/// Note this updates a previously read [`Mstatus`] value, but does not
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/// affect the mstatus CSR itself. See [`set_spp`] to directly update the
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/// CSR.
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#[inline]
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pub fn set_spp(&mut self, spp: SPP) {
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self.bits = bf_insert(self.bits, 8, 1, spp as usize);
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}
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/// Machine Previous Privilege Mode
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#[inline]
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pub fn mpp(&self) -> MPP {
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let mpp = bf_extract(self.bits, 11, 2); // bits 11-12
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match mpp {
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0b00 => MPP::User,
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0b01 => MPP::Supervisor,
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0b11 => MPP::Machine,
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_ => unreachable!(),
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}
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}
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/// Update Machine Previous Privilege Mode
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///
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/// Note this updates a previously read [`Mstatus`] value, but does not
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/// affect the mstatus CSR itself. See [`set_mpp`] to directly update the
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/// CSR.
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#[inline]
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pub fn set_mpp(&mut self, mpp: MPP) {
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self.bits = bf_insert(self.bits, 11, 2, mpp as usize);
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}
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/// Floating-point extension state
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///
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/// Encodes the status of the floating-point unit, including the CSR `fcsr`
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/// and floating-point data registers `f0–f31`.
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#[inline]
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pub fn fs(&self) -> FS {
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let fs = bf_extract(self.bits, 13, 2); // bits 13-14
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match fs {
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0b00 => FS::Off,
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0b01 => FS::Initial,
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0b10 => FS::Clean,
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0b11 => FS::Dirty,
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_ => unreachable!(),
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}
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}
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/// Vector extension state
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#[inline]
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pub fn vs(&self) -> VS {
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let fs = bf_extract(self.bits, 9, 2); // bits 9-10
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match fs {
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0b00 => VS::Off,
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0b01 => VS::Initial,
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0b10 => VS::Clean,
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0b11 => VS::Dirty,
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_ => unreachable!(),
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}
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}
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/// Update Floating-point extension state
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///
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/// Note this updates a previously read [`Mstatus`] value, but does not
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/// affect the mstatus CSR itself. See [`set_fs`] to directly update the
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/// CSR.
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#[inline]
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pub fn set_fs(&mut self, fs: FS) {
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self.bits = bf_insert(self.bits, 13, 2, fs as usize);
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}
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/// Update vector extension state
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///
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/// Note this updates a previously read [`Mstatus`] value, but does not
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/// affect the mstatus CSR itself. See [`set_vs`] to directly update the
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/// CSR.
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#[inline]
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pub fn set_vs(&mut self, vs: VS) {
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self.bits = bf_insert(self.bits, 9, 2, vs as usize);
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}
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/// Additional extension state
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///
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/// Encodes the status of additional user-mode extensions and associated
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/// state.
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#[inline]
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pub fn xs(&self) -> XS {
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let xs = bf_extract(self.bits, 15, 2); // bits 15-16
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match xs {
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0b00 => XS::AllOff,
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0b01 => XS::NoneDirtyOrClean,
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0b10 => XS::NoneDirtySomeClean,
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0b11 => XS::SomeDirty,
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_ => unreachable!(),
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}
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}
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/// Update Additional extension state
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///
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/// Note this updates a previously read [`Mstatus`] value, but does not
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/// affect the mstatus CSR itself.
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#[inline]
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pub fn set_xs(&mut self, xs: XS) {
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self.bits = bf_insert(self.bits, 15, 2, xs as usize);
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}
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/// Modify Memory PRiVilege
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#[inline]
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pub fn mprv(&self) -> bool {
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bf_extract(self.bits, 17, 1) != 0
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}
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/// Update Modify Memory PRiVilege
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///
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/// Note this updates a previously read [`Mstatus`] value, but does not
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/// affect the mstatus CSR itself. See [`set_mprv`]/[`clear_mprv`] to
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/// directly update the CSR.
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#[inline]
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pub fn set_mprv(&mut self, mprv: bool) {
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self.bits = bf_insert(self.bits, 17, 1, mprv as usize);
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}
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/// Permit Supervisor User Memory access
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#[inline]
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pub fn sum(&self) -> bool {
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bf_extract(self.bits, 18, 1) != 0
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}
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/// Update Permit Supervisor User Memory access
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///
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/// Note this updates a previously read [`Mstatus`] value, but does not
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/// affect the mstatus CSR itself. See [`set_sum`]/[`clear_sum`] to directly
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/// update the CSR.
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#[inline]
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pub fn set_sum(&mut self, sum: bool) {
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self.bits = bf_insert(self.bits, 18, 1, sum as usize);
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}
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/// Make eXecutable Readable
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#[inline]
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pub fn mxr(&self) -> bool {
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bf_extract(self.bits, 19, 1) != 0
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}
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/// Update Make eXecutable Readable
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///
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/// Note this updates a previously read [`Mstatus`] value, but does not affect
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/// the mstatus CSR itself. See [`set_mxr`]/[`clear_mxr`] to directly update
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/// the CSR.
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#[inline]
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pub fn set_mxr(&mut self, mxr: bool) {
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self.bits = bf_insert(self.bits, 19, 1, mxr as usize);
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}
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/// Trap Virtual Memory
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///
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/// If this bit is set, reads or writes to `satp` CSR or execute `sfence.vma`
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/// instruction when in S-mode will raise an illegal instruction exception.
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///
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/// TVM is hard-wired to 0 when S-mode is not supported.
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#[inline]
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pub fn tvm(&self) -> bool {
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bf_extract(self.bits, 20, 1) != 0
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}
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/// Update Trap Virtual Memory
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///
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/// Note this updates a previously read [`Mstatus`] value, but does not
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/// affect the mstatus CSR itself. See [`set_tvm`]/[`clear_tvm`] to directly
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/// update the CSR.
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#[inline]
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pub fn set_tvm(&mut self, tvm: bool) {
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self.bits = bf_insert(self.bits, 20, 1, tvm as usize);
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}
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/// Timeout Wait
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///
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/// Indicates that if WFI instruction should be intercepted.
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///
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/// If this bit is set, when WFI is executed in S-mode, and it does not complete
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/// within an implementation specific, bounded time limit, the WFI instruction will cause
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/// an illegal instruction trap; or could always cause trap then the time limit is zero.
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///
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/// TW is hard-wired to 0 when S-mode is not supported.
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#[inline]
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pub fn tw(&self) -> bool {
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bf_extract(self.bits, 21, 1) != 0
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}
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/// Update Timeout Wait
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///
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/// Note this updates a previously read [`Mstatus`] value, but does not
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/// affect the mstatus CSR itself. See [`set_tw`]/[`clear_tw`] to directly
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/// update the CSR.
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#[inline]
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pub fn set_tw(&mut self, tw: bool) {
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self.bits = bf_insert(self.bits, 21, 1, tw as usize);
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}
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/// Trap SRET
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///
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/// Indicates that if SRET instruction should be trapped to raise illegal
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/// instruction exception.
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///
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/// If S-mode is not supported, TSR bit is hard-wired to 0.
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#[inline]
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pub fn tsr(&self) -> bool {
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bf_extract(self.bits, 22, 1) != 0
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}
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/// Update Trap SRET
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///
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/// Note this updates a previously read [`Mstatus`] value, but does not
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/// affect the mstatus CSR itself. See [`set_tsr`]/[`clear_tsr`] to directly
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/// update the CSR.
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#[inline]
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pub fn set_tsr(&mut self, tsr: bool) {
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self.bits = bf_insert(self.bits, 22, 1, tsr as usize);
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}
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/// Effective xlen in U-mode (i.e., `UXLEN`).
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///
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/// In RISCV-32, UXL does not exist, and `UXLEN` is always [`XLEN::XLEN32`].
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#[inline]
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pub fn uxl(&self) -> XLEN {
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match () {
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#[cfg(riscv32)]
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() => XLEN::XLEN32,
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#[cfg(not(riscv32))]
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() => XLEN::from(bf_extract(self.bits, 32, 2) as u8),
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}
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}
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/// Update Effective xlen in U-mode (i.e., `UXLEN`).
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///
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/// Note this updates a previously read [`Mstatus`] value, but does not
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/// affect the mstatus CSR itself.
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#[inline]
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pub fn set_uxl(&mut self, uxl: XLEN) {
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#[cfg(not(riscv32))]
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{
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self.bits = bf_insert(self.bits, 32, 2, uxl as usize);
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}
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}
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/// Effective xlen in S-mode (i.e., `SXLEN`).
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///
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/// In RISCV-32, SXL does not exist, and SXLEN is always [`XLEN::XLEN32`].
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#[inline]
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pub fn sxl(&self) -> XLEN {
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match () {
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#[cfg(riscv32)]
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() => XLEN::XLEN32,
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#[cfg(not(riscv32))]
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() => XLEN::from(bf_extract(self.bits, 34, 2) as u8),
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}
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}
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/// Update Effective xlen in S-mode (i.e., `SXLEN`).
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///
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/// Note this updates a previously read [`Mstatus`] value, but does not
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/// affect the mstatus CSR itself.
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#[inline]
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pub fn set_sxl(&mut self, sxl: XLEN) {
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#[cfg(not(riscv32))]
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{
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self.bits = bf_insert(self.bits, 34, 2, sxl as usize);
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}
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}
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/// S-mode non-instruction-fetch memory endianness.
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///
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/// In RISCV-32, this field is read from the [`crate::register::mstatush`] register.
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pub fn sbe(&self) -> Endianness {
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match () {
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#[cfg(riscv32)]
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() => super::mstatush::read().sbe(),
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#[cfg(not(riscv32))]
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() => Endianness::from(bf_extract(self.bits, 36, 1) != 0),
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}
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}
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/// Update S-mode non-instruction-fetch memory endianness
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///
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/// Note this updates a previously read [`Mstatus`] value, but does not
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/// affect the mstatus CSR itself. See [`set_sbe`] to directly update the
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/// CSR.
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#[inline]
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pub fn set_sbe(&mut self, endianness: Endianness) {
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#[cfg(not(riscv32))]
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{
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self.bits = bf_insert(self.bits, 36, 1, endianness as usize);
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}
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}
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/// M-mode non-instruction-fetch memory endianness
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///
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/// In RISCV-32, this field is read from the [`crate::register::mstatush`] register
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pub fn mbe(&self) -> Endianness {
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match () {
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#[cfg(riscv32)]
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() => super::mstatush::read().mbe(),
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#[cfg(not(riscv32))]
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() => Endianness::from(bf_extract(self.bits, 37, 1) != 0),
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}
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}
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/// Update M-mode non-instruction-fetch memory endianness
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///
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/// Note this updates a previously read [`Mstatus`] value, but does not
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/// affect the mstatus CSR itself. See [`set_mbe`] to directly update the
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/// CSR.
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#[inline]
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pub fn set_mbe(&mut self, endianness: Endianness) {
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#[cfg(not(riscv32))]
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{
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self.bits = bf_insert(self.bits, 37, 1, endianness as usize);
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}
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}
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/// Whether either the FS field or XS field signals the presence of some dirty state
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#[inline]
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pub fn sd(&self) -> bool {
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bf_extract(self.bits, usize::BITS as usize - 1, 1) != 0
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}
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/// Update whether either the FS field or XS field signals the presence of
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/// some dirty state
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///
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/// Note this updates a previously read [`Mstatus`] value, but does not
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/// affect the mstatus CSR itself.
|
||
#[inline]
|
||
pub fn set_sd(&mut self, sd: bool) {
|
||
self.bits = bf_insert(self.bits, usize::BITS as usize - 1, 1, sd as usize);
|
||
}
|
||
}
|
||
|
||
read_csr_as!(Mstatus, 0x300);
|
||
write_csr_as!(Mstatus, 0x300);
|
||
set!(0x300);
|
||
clear!(0x300);
|
||
|
||
set_clear_csr!(
|
||
/// User Interrupt Enable
|
||
, set_uie, clear_uie, 1 << 0);
|
||
set_clear_csr!(
|
||
/// Supervisor Interrupt Enable
|
||
, set_sie, clear_sie, 1 << 1);
|
||
set_clear_csr!(
|
||
/// Machine Interrupt Enable
|
||
, set_mie, clear_mie, 1 << 3);
|
||
set_csr!(
|
||
/// User Previous Interrupt Enable
|
||
, set_upie, 1 << 4);
|
||
set_csr!(
|
||
/// Supervisor Previous Interrupt Enable
|
||
, set_spie, 1 << 5);
|
||
set_csr!(
|
||
/// Machine Previous Interrupt Enable
|
||
, set_mpie, 1 << 7);
|
||
set_clear_csr!(
|
||
/// Modify Memory PRiVilege
|
||
, set_mprv, clear_mprv, 1 << 17);
|
||
set_clear_csr!(
|
||
/// Permit Supervisor User Memory access
|
||
, set_sum, clear_sum, 1 << 18);
|
||
set_clear_csr!(
|
||
/// Make eXecutable Readable
|
||
, set_mxr, clear_mxr, 1 << 19);
|
||
set_clear_csr!(
|
||
/// Trap Virtual Memory
|
||
, set_tvm, clear_tvm, 1 << 20);
|
||
set_clear_csr!(
|
||
/// Timeout Wait
|
||
, set_tw, clear_tw, 1 << 21);
|
||
set_clear_csr!(
|
||
/// Trap SRET
|
||
, set_tsr, clear_tsr, 1 << 22);
|
||
|
||
/// Set U-mode non-instruction-fetch memory endianness
|
||
#[inline]
|
||
pub unsafe fn set_ube(endianness: Endianness) {
|
||
match endianness {
|
||
Endianness::BigEndian => _set(1 << 6),
|
||
Endianness::LittleEndian => _clear(1 << 6),
|
||
}
|
||
}
|
||
|
||
/// Supervisor Previous Privilege Mode
|
||
#[inline]
|
||
pub unsafe fn set_spp(spp: SPP) {
|
||
match spp {
|
||
SPP::Supervisor => _set(1 << 8),
|
||
SPP::User => _clear(1 << 8),
|
||
}
|
||
}
|
||
|
||
/// Machine Previous Privilege Mode
|
||
#[inline]
|
||
pub unsafe fn set_mpp(mpp: MPP) {
|
||
let mut value = _read();
|
||
value &= !(0x3 << 11); // clear previous value
|
||
value |= (mpp as usize) << 11;
|
||
_write(value);
|
||
}
|
||
|
||
/// Floating-point extension state
|
||
#[inline]
|
||
pub unsafe fn set_fs(fs: FS) {
|
||
let mut value = _read();
|
||
value &= !(0x3 << 13); // clear previous value
|
||
value |= (fs as usize) << 13;
|
||
_write(value);
|
||
}
|
||
|
||
/// Vector extension state
|
||
#[inline]
|
||
pub unsafe fn set_vs(vs: VS) {
|
||
let mut value = _read();
|
||
value &= !(0x3 << 9); // clear previous value
|
||
value |= (vs as usize) << 9;
|
||
_write(value);
|
||
}
|
||
|
||
/// Set S-mode non-instruction-fetch memory endianness
|
||
///
|
||
/// # Note
|
||
///
|
||
/// In RISCV-32, this function calls [`crate::register::mstatush::set_sbe`]
|
||
#[inline]
|
||
pub unsafe fn set_sbe(endianness: Endianness) {
|
||
match () {
|
||
#[cfg(riscv32)]
|
||
() => super::mstatush::set_sbe(endianness),
|
||
#[cfg(not(riscv32))]
|
||
() => match endianness {
|
||
Endianness::BigEndian => _set(1 << 36),
|
||
Endianness::LittleEndian => _clear(1 << 36),
|
||
},
|
||
}
|
||
}
|
||
|
||
/// Set M-mode non-instruction-fetch memory endianness
|
||
///
|
||
/// # Note
|
||
///
|
||
/// In RISCV-32, this function calls [`crate::register::mstatush::set_mbe`]
|
||
#[inline]
|
||
pub unsafe fn set_mbe(endianness: Endianness) {
|
||
match () {
|
||
#[cfg(riscv32)]
|
||
() => super::mstatush::set_mbe(endianness),
|
||
#[cfg(not(riscv32))]
|
||
() => match endianness {
|
||
Endianness::BigEndian => _set(1 << 37),
|
||
Endianness::LittleEndian => _clear(1 << 37),
|
||
},
|
||
}
|
||
}
|
||
|
||
#[cfg(test)]
|
||
mod test {
|
||
use super::*;
|
||
|
||
#[test]
|
||
fn test_mpp() {
|
||
let mut mstatus = Mstatus { bits: 0 };
|
||
mstatus.set_mpp(MPP::User);
|
||
assert_eq!(mstatus.mpp(), MPP::User);
|
||
mstatus.set_mpp(MPP::Machine);
|
||
assert_eq!(mstatus.mpp(), MPP::Machine);
|
||
mstatus.set_mpp(MPP::Supervisor);
|
||
assert_eq!(mstatus.mpp(), MPP::Supervisor);
|
||
}
|
||
}
|