swaitsandClaude Opus 4.6
3102fc747a
Implement full SSD1306 OLED display support: - Splash screen on boot (1.5s) with project name, version, board - Dashboard showing radio state, config, counters, RSSI/SNR - RSSI history sparkline (64-sample ring buffer, 2px-wide bars) - DisplayOn/DisplayOff host commands routed via dedicated channel - Pure render functions against generic DrawTarget (no hardware coupling) - Display on/off control bypasses radio task entirely Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
93 lines
4.6 KiB
Rust
93 lines
4.6 KiB
Rust
#[doc = "Register `RX_CLKM_CONF` reader"]
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pub type R = crate::R<RX_CLKM_CONF_SPEC>;
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#[doc = "Register `RX_CLKM_CONF` writer"]
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pub type W = crate::W<RX_CLKM_CONF_SPEC>;
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#[doc = "Field `RX_CLKM_DIV_NUM` reader - Integral I2S clock divider value"]
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pub type RX_CLKM_DIV_NUM_R = crate::FieldReader;
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#[doc = "Field `RX_CLKM_DIV_NUM` writer - Integral I2S clock divider value"]
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pub type RX_CLKM_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
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#[doc = "Field `RX_CLK_ACTIVE` reader - I2S Rx module clock enable signal."]
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pub type RX_CLK_ACTIVE_R = crate::BitReader;
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#[doc = "Field `RX_CLK_ACTIVE` writer - I2S Rx module clock enable signal."]
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pub type RX_CLK_ACTIVE_W<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `RX_CLK_SEL` reader - Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in."]
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pub type RX_CLK_SEL_R = crate::FieldReader;
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#[doc = "Field `RX_CLK_SEL` writer - Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in."]
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pub type RX_CLK_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
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#[doc = "Field `MCLK_SEL` reader - 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MCLK_OUT."]
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pub type MCLK_SEL_R = crate::BitReader;
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#[doc = "Field `MCLK_SEL` writer - 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MCLK_OUT."]
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pub type MCLK_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
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impl R {
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#[doc = "Bits 0:7 - Integral I2S clock divider value"]
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#[inline(always)]
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pub fn rx_clkm_div_num(&self) -> RX_CLKM_DIV_NUM_R {
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RX_CLKM_DIV_NUM_R::new((self.bits & 0xff) as u8)
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}
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#[doc = "Bit 26 - I2S Rx module clock enable signal."]
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#[inline(always)]
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pub fn rx_clk_active(&self) -> RX_CLK_ACTIVE_R {
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RX_CLK_ACTIVE_R::new(((self.bits >> 26) & 1) != 0)
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}
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#[doc = "Bits 27:28 - Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in."]
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#[inline(always)]
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pub fn rx_clk_sel(&self) -> RX_CLK_SEL_R {
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RX_CLK_SEL_R::new(((self.bits >> 27) & 3) as u8)
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}
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#[doc = "Bit 29 - 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MCLK_OUT."]
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#[inline(always)]
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pub fn mclk_sel(&self) -> MCLK_SEL_R {
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MCLK_SEL_R::new(((self.bits >> 29) & 1) != 0)
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}
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}
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#[cfg(feature = "impl-register-debug")]
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impl core::fmt::Debug for R {
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fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
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f.debug_struct("RX_CLKM_CONF")
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.field("rx_clkm_div_num", &self.rx_clkm_div_num())
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.field("rx_clk_active", &self.rx_clk_active())
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.field("rx_clk_sel", &self.rx_clk_sel())
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.field("mclk_sel", &self.mclk_sel())
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.finish()
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}
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}
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impl W {
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#[doc = "Bits 0:7 - Integral I2S clock divider value"]
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#[inline(always)]
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pub fn rx_clkm_div_num(&mut self) -> RX_CLKM_DIV_NUM_W<RX_CLKM_CONF_SPEC> {
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RX_CLKM_DIV_NUM_W::new(self, 0)
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}
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#[doc = "Bit 26 - I2S Rx module clock enable signal."]
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#[inline(always)]
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pub fn rx_clk_active(&mut self) -> RX_CLK_ACTIVE_W<RX_CLKM_CONF_SPEC> {
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RX_CLK_ACTIVE_W::new(self, 26)
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}
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#[doc = "Bits 27:28 - Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in."]
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#[inline(always)]
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pub fn rx_clk_sel(&mut self) -> RX_CLK_SEL_W<RX_CLKM_CONF_SPEC> {
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RX_CLK_SEL_W::new(self, 27)
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}
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#[doc = "Bit 29 - 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MCLK_OUT."]
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#[inline(always)]
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pub fn mclk_sel(&mut self) -> MCLK_SEL_W<RX_CLKM_CONF_SPEC> {
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MCLK_SEL_W::new(self, 29)
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}
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}
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#[doc = "I2S RX clock configure register\n\nYou can [`read`](crate::Reg::read) this register and get [`rx_clkm_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx_clkm_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
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pub struct RX_CLKM_CONF_SPEC;
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impl crate::RegisterSpec for RX_CLKM_CONF_SPEC {
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type Ux = u32;
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}
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#[doc = "`read()` method returns [`rx_clkm_conf::R`](R) reader structure"]
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impl crate::Readable for RX_CLKM_CONF_SPEC {}
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#[doc = "`write(|w| ..)` method takes [`rx_clkm_conf::W`](W) writer structure"]
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impl crate::Writable for RX_CLKM_CONF_SPEC {
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type Safety = crate::Unsafe;
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const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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}
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#[doc = "`reset()` method sets RX_CLKM_CONF to value 0x02"]
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impl crate::Resettable for RX_CLKM_CONF_SPEC {
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const RESET_VALUE: u32 = 0x02;
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}
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