swaitsandClaude Opus 4.6
3102fc747a
Implement full SSD1306 OLED display support: - Splash screen on boot (1.5s) with project name, version, board - Dashboard showing radio state, config, counters, RSSI/SNR - RSSI history sparkline (64-sample ring buffer, 2px-wide bars) - DisplayOn/DisplayOff host commands routed via dedicated channel - Pure render functions against generic DrawTarget (no hardware coupling) - Display on/off control bypasses radio task entirely Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
559 lines
18 KiB
Rust
559 lines
18 KiB
Rust
//! # Debug Assistant (ASSIST_DEBUG)
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//!
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//! ## Overview
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//! Debug Assistant is an auxiliary module that features a set of functions to
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//! help locate bugs and issues during software debugging. It includes
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//! capabilities such as monitoring stack pointer (SP), monitoring memory
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//! regions, and handling interrupts related to debugging.
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//!
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//!
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//! ## Configuration
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//! While all the targets support program counter (PC) logging it's API is not
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//! exposed here. Instead the ROM bootloader will always enable it and print the
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//! last seen PC (e.g. _Saved PC:0x42002ff2_). Make sure the reset was triggered
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//! by a TIMG watchdog. Not an RTC or SWD watchdog.
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//!
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//! ## Examples
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//! Visit the [Debug Assist] example for an example of using the Debug
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//! Assistant.
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//!
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//! [Debug Assist]: https://github.com/esp-rs/esp-hal/blob/main/examples/src/bin/debug_assist.rs
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//!
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//! ## Implementation State
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//! - Bus write access logging is not available via this API
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//! - This driver has only blocking API
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use crate::{
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interrupt::InterruptHandler,
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peripheral::{Peripheral, PeripheralRef},
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peripherals::{Interrupt, ASSIST_DEBUG},
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InterruptConfigurable,
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};
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/// The debug assist driver instance.
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pub struct DebugAssist<'d> {
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debug_assist: PeripheralRef<'d, ASSIST_DEBUG>,
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}
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impl<'d> DebugAssist<'d> {
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/// Create a new instance in [crate::Blocking] mode.
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pub fn new(debug_assist: impl Peripheral<P = ASSIST_DEBUG> + 'd) -> Self {
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crate::into_ref!(debug_assist);
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// NOTE: We should enable the debug assist, however, it's always enabled in ROM
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// code already.
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DebugAssist { debug_assist }
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}
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}
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impl crate::private::Sealed for DebugAssist<'_> {}
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impl InterruptConfigurable for DebugAssist<'_> {
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fn set_interrupt_handler(&mut self, handler: InterruptHandler) {
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for core in crate::Cpu::other() {
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crate::interrupt::disable(core, Interrupt::ASSIST_DEBUG);
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}
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unsafe { crate::interrupt::bind_interrupt(Interrupt::ASSIST_DEBUG, handler.handler()) };
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unwrap!(crate::interrupt::enable(
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Interrupt::ASSIST_DEBUG,
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handler.priority()
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));
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}
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}
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#[cfg(assist_debug_sp_monitor)]
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impl DebugAssist<'_> {
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/// Enable SP monitoring on main core. When the SP exceeds the
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/// `lower_bound` or `upper_bound` threshold, the module will record the PC
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/// pointer and generate an interrupt.
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pub fn enable_sp_monitor(&mut self, lower_bound: u32, upper_bound: u32) {
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self.debug_assist
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.core_0_sp_min()
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.write(|w| unsafe { w.core_0_sp_min().bits(lower_bound) });
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self.debug_assist
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.core_0_sp_max()
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.write(|w| unsafe { w.core_0_sp_max().bits(upper_bound) });
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self.debug_assist.core_0_montr_ena().modify(|_, w| {
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w.core_0_sp_spill_min_ena()
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.set_bit()
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.core_0_sp_spill_max_ena()
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.set_bit()
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});
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self.clear_sp_monitor_interrupt();
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self.debug_assist.core_0_intr_ena().modify(|_, w| {
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w.core_0_sp_spill_max_intr_ena()
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.set_bit()
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.core_0_sp_spill_min_intr_ena()
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.set_bit()
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});
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}
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/// Disable SP monitoring on main core.
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pub fn disable_sp_monitor(&mut self) {
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self.debug_assist.core_0_intr_ena().modify(|_, w| {
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w.core_0_sp_spill_max_intr_ena()
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.clear_bit()
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.core_0_sp_spill_min_intr_ena()
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.clear_bit()
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});
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self.debug_assist.core_0_montr_ena().modify(|_, w| {
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w.core_0_sp_spill_min_ena()
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.clear_bit()
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.core_0_sp_spill_max_ena()
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.clear_bit()
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});
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}
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/// Clear SP monitoring interrupt on main core.
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pub fn clear_sp_monitor_interrupt(&mut self) {
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self.debug_assist.core_0_intr_clr().write(|w| {
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w.core_0_sp_spill_max_clr()
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.set_bit()
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.core_0_sp_spill_min_clr()
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.set_bit()
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});
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}
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/// Check, if SP monitoring interrupt is set on main core.
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pub fn is_sp_monitor_interrupt_set(&self) -> bool {
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self.debug_assist
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.core_0_intr_raw()
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.read()
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.core_0_sp_spill_max_raw()
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.bit_is_set()
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|| self
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.debug_assist
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.core_0_intr_raw()
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.read()
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.core_0_sp_spill_min_raw()
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.bit_is_set()
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}
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/// Get SP monitoring PC value on main core.
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pub fn sp_monitor_pc(&self) -> u32 {
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self.debug_assist
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.core_0_sp_pc()
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.read()
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.core_0_sp_pc()
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.bits()
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}
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}
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#[cfg(all(assist_debug_sp_monitor, multi_core))]
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impl<'d> DebugAssist<'d> {
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/// Enable SP monitoring on secondary core. When the SP exceeds the
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/// `lower_bound` or `upper_bound` threshold, the module will record the PC
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/// pointer and generate an interrupt.
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pub fn enable_core1_sp_monitor(&mut self, lower_bound: u32, upper_bound: u32) {
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self.debug_assist
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.core_1_sp_min
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.write(|w| w.core_1_sp_min().bits(lower_bound));
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self.debug_assist
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.core_1_sp_max
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.write(|w| w.core_1_sp_max().bits(upper_bound));
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self.debug_assist.core_1_montr_ena.modify(|_, w| {
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w.core_1_sp_spill_min_ena()
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.set_bit()
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.core_1_sp_spill_max_ena()
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.set_bit()
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});
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self.clear_core1_sp_monitor_interrupt();
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self.debug_assist.core_1_intr_ena.modify(|_, w| {
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w.core_1_sp_spill_max_intr_ena()
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.set_bit()
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.core_1_sp_spill_min_intr_ena()
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.set_bit()
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});
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}
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/// Disable SP monitoring on secondary core.
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pub fn disable_core1_sp_monitor(&mut self) {
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self.debug_assist.core_1_intr_ena.modify(|_, w| {
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w.core_1_sp_spill_max_intr_ena()
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.clear_bit()
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.core_1_sp_spill_min_intr_ena()
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.clear_bit()
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});
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self.debug_assist.core_1_montr_ena.modify(|_, w| {
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w.core_1_sp_spill_min_ena()
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.clear_bit()
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.core_1_sp_spill_max_ena()
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.clear_bit()
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});
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}
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/// Clear SP monitoring interrupt on secondary core.
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pub fn clear_core1_sp_monitor_interrupt(&mut self) {
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self.debug_assist.core_1_intr_clr.write(|w| {
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w.core_1_sp_spill_max_clr()
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.set_bit()
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.core_1_sp_spill_min_clr()
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.set_bit()
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});
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}
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/// Check, if SP monitoring interrupt is set on secondary core.
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pub fn is_core1_sp_monitor_interrupt_set(&self) -> bool {
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self.debug_assist
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.core_1_intr_raw
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.read()
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.core_1_sp_spill_max_raw()
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.bit_is_set()
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|| self
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.debug_assist
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.core_1_intr_raw
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.read()
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.core_1_sp_spill_min_raw()
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.bit_is_set()
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}
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/// Get SP monitoring PC value on secondary core.
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pub fn core1_sp_monitor_pc(&self) -> u32 {
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self.debug_assist.core_1_sp_pc.read().core_1_sp_pc().bits()
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}
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}
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#[cfg(assist_debug_region_monitor)]
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impl DebugAssist<'_> {
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/// Enable region monitoring of read/write performed by the main CPU in a
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/// certain memory region0. Whenever the bus reads or writes in the
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/// specified memory region, an interrupt will be triggered. Two memory
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/// regions (region0, region1) can be monitored at the same time.
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pub fn enable_region0_monitor(
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&mut self,
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lower_bound: u32,
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upper_bound: u32,
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reads: bool,
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writes: bool,
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) {
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self.debug_assist
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.core_0_area_dram0_0_min()
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.write(|w| unsafe { w.core_0_area_dram0_0_min().bits(lower_bound) });
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self.debug_assist
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.core_0_area_dram0_0_max()
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.write(|w| unsafe { w.core_0_area_dram0_0_max().bits(upper_bound) });
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self.debug_assist.core_0_montr_ena().modify(|_, w| {
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w.core_0_area_dram0_0_rd_ena()
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.bit(reads)
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.core_0_area_dram0_0_wr_ena()
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.bit(writes)
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});
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self.clear_region0_monitor_interrupt();
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self.debug_assist.core_0_intr_ena().modify(|_, w| {
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w.core_0_area_dram0_0_rd_intr_ena()
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.set_bit()
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.core_0_area_dram0_0_wr_intr_ena()
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.set_bit()
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});
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}
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/// Disable region0 monitoring on main core.
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pub fn disable_region0_monitor(&mut self) {
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self.debug_assist.core_0_intr_ena().modify(|_, w| {
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w.core_0_area_dram0_0_rd_intr_ena()
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.clear_bit()
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.core_0_area_dram0_0_wr_intr_ena()
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.clear_bit()
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});
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self.debug_assist.core_0_montr_ena().modify(|_, w| {
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w.core_0_area_dram0_0_rd_ena()
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.clear_bit()
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.core_0_area_dram0_0_wr_ena()
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.clear_bit()
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});
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}
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/// Clear region0 monitoring interrupt on main core.
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pub fn clear_region0_monitor_interrupt(&mut self) {
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self.debug_assist.core_0_intr_clr().write(|w| {
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w.core_0_area_dram0_0_rd_clr()
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.set_bit()
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.core_0_area_dram0_0_wr_clr()
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.set_bit()
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});
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}
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/// Check, if region0 monitoring interrupt is set on main core.
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pub fn is_region0_monitor_interrupt_set(&self) -> bool {
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self.debug_assist
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.core_0_intr_raw()
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.read()
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.core_0_area_dram0_0_rd_raw()
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.bit_is_set()
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|| self
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.debug_assist
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.core_0_intr_raw()
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.read()
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.core_0_area_dram0_0_wr_raw()
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.bit_is_set()
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}
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/// Enable region monitoring of read/write performed by the main CPU in a
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/// certain memory region1. Whenever the bus reads or writes in the
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/// specified memory region, an interrupt will be triggered.
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pub fn enable_region1_monitor(
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&mut self,
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lower_bound: u32,
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upper_bound: u32,
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reads: bool,
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writes: bool,
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) {
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self.debug_assist
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.core_0_area_dram0_1_min()
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.write(|w| unsafe { w.core_0_area_dram0_1_min().bits(lower_bound) });
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self.debug_assist
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.core_0_area_dram0_1_max()
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.write(|w| unsafe { w.core_0_area_dram0_1_max().bits(upper_bound) });
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self.debug_assist.core_0_montr_ena().modify(|_, w| {
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w.core_0_area_dram0_1_rd_ena()
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.bit(reads)
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.core_0_area_dram0_1_wr_ena()
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.bit(writes)
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});
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self.clear_region1_monitor_interrupt();
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self.debug_assist.core_0_intr_ena().modify(|_, w| {
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w.core_0_area_dram0_1_rd_intr_ena()
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.set_bit()
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.core_0_area_dram0_1_wr_intr_ena()
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.set_bit()
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});
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}
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/// Disable region1 monitoring on main core.
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pub fn disable_region1_monitor(&mut self) {
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self.debug_assist.core_0_intr_ena().modify(|_, w| {
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w.core_0_area_dram0_1_rd_intr_ena()
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.clear_bit()
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.core_0_area_dram0_1_wr_intr_ena()
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.clear_bit()
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});
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self.debug_assist.core_0_montr_ena().modify(|_, w| {
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w.core_0_area_dram0_1_rd_ena()
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.clear_bit()
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.core_0_area_dram0_1_wr_ena()
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.clear_bit()
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});
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}
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/// Clear region1 monitoring interrupt on main core.
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pub fn clear_region1_monitor_interrupt(&mut self) {
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self.debug_assist.core_0_intr_clr().write(|w| {
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w.core_0_area_dram0_1_rd_clr()
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.set_bit()
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.core_0_area_dram0_1_wr_clr()
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.set_bit()
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});
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}
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/// Check, if region1 monitoring interrupt is set on main core.
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pub fn is_region1_monitor_interrupt_set(&self) -> bool {
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self.debug_assist
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.core_0_intr_raw()
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.read()
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.core_0_area_dram0_1_rd_raw()
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.bit_is_set()
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|| self
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.debug_assist
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.core_0_intr_raw()
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.read()
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.core_0_area_dram0_1_wr_raw()
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.bit_is_set()
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}
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/// Get region monitoring PC value on main core.
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pub fn region_monitor_pc(&self) -> u32 {
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self.debug_assist
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.core_0_area_pc()
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.read()
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.core_0_area_pc()
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.bits()
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}
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}
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#[cfg(all(assist_debug_region_monitor, multi_core))]
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impl<'d> DebugAssist<'d> {
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/// Enable region monitoring of read/write performed by the secondary CPU in
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/// a certain memory region0. Whenever the bus reads or writes in the
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/// specified memory region, an interrupt will be triggered.
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pub fn enable_core1_region0_monitor(
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&mut self,
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lower_bound: u32,
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upper_bound: u32,
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reads: bool,
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writes: bool,
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) {
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self.debug_assist
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.core_1_area_dram0_0_min()
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.write(|w| unsafe { w.core_1_area_dram0_0_min().bits(lower_bound) });
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self.debug_assist
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.core_1_area_dram0_0_max()
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.write(|w| unsafe { w.core_1_area_dram0_0_max().bits(upper_bound) });
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self.debug_assist.core_1_montr_ena().modify(|_, w| {
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w.core_1_area_dram0_0_rd_ena()
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.bit(reads)
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.core_1_area_dram0_0_wr_ena()
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.bit(writes)
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});
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self.clear_core1_region0_monitor_interrupt();
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self.debug_assist.core_1_intr_ena().modify(|_, w| {
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w.core_1_area_dram0_0_rd_intr_ena()
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.set_bit()
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.core_1_area_dram0_0_wr_intr_ena()
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.set_bit()
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});
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}
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/// Disable region0 monitoring on secondary core.
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pub fn disable_core1_region0_monitor(&mut self) {
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self.debug_assist.core_1_intr_ena().modify(|_, w| {
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w.core_1_area_dram0_0_rd_intr_ena()
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.clear_bit()
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.core_1_area_dram0_0_wr_intr_ena()
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.clear_bit()
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});
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self.debug_assist.core_1_montr_ena().modify(|_, w| {
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w.core_1_area_dram0_0_rd_ena()
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.clear_bit()
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.core_1_area_dram0_0_wr_ena()
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.clear_bit()
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});
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}
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/// Clear region0 monitoring interrupt on secondary core.
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pub fn clear_core1_region0_monitor_interrupt(&mut self) {
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self.debug_assist.core_1_intr_clr().write(|w| {
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w.core_1_area_dram0_0_rd_clr()
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.set_bit()
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.core_1_area_dram0_0_wr_clr()
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.set_bit()
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});
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}
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/// Check, if region0 monitoring interrupt is set on secondary core.
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pub fn is_core1_region0_monitor_interrupt_set(&self) -> bool {
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self.debug_assist
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.core_1_intr_raw()
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.read()
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.core_1_area_dram0_0_rd_raw()
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.bit_is_set()
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|| self
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.debug_assist
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.core_1_intr_raw()
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.read()
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.core_1_area_dram0_0_wr_raw()
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.bit_is_set()
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}
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/// Enable region monitoring of read/write performed by the secondary CPU in
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/// a certain memory region1. Whenever the bus reads or writes in the
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/// specified memory region, an interrupt will be triggered.
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pub fn enable_core1_region1_monitor(
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&mut self,
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lower_bound: u32,
|
|
upper_bound: u32,
|
|
reads: bool,
|
|
writes: bool,
|
|
) {
|
|
self.debug_assist
|
|
.core_1_area_dram0_1_min()
|
|
.write(|w| unsafe { w.core_1_area_dram0_1_min().bits(lower_bound) });
|
|
|
|
self.debug_assist
|
|
.core_1_area_dram0_1_max()
|
|
.write(|w| unsafe { w.core_1_area_dram0_1_max().bits(upper_bound) });
|
|
|
|
self.debug_assist.core_1_montr_ena().modify(|_, w| {
|
|
w.core_1_area_dram0_1_rd_ena()
|
|
.bit(reads)
|
|
.core_1_area_dram0_1_wr_ena()
|
|
.bit(writes)
|
|
});
|
|
|
|
self.clear_core1_region1_monitor_interrupt();
|
|
|
|
self.debug_assist.core_1_intr_ena().modify(|_, w| {
|
|
w.core_1_area_dram0_1_rd_intr_ena()
|
|
.set_bit()
|
|
.core_1_area_dram0_1_wr_intr_ena()
|
|
.set_bit()
|
|
});
|
|
}
|
|
|
|
/// Disable region1 monitoring on secondary core.
|
|
pub fn disable_core1_region1_monitor(&mut self) {
|
|
self.debug_assist.core_1_intr_ena().modify(|_, w| {
|
|
w.core_1_area_dram0_1_rd_intr_ena()
|
|
.clear_bit()
|
|
.core_1_area_dram0_1_wr_intr_ena()
|
|
.clear_bit()
|
|
});
|
|
|
|
self.debug_assist.core_1_montr_ena().modify(|_, w| {
|
|
w.core_1_area_dram0_1_rd_ena()
|
|
.clear_bit()
|
|
.core_1_area_dram0_1_wr_ena()
|
|
.clear_bit()
|
|
});
|
|
}
|
|
|
|
/// Clear region1 monitoring interrupt on secondary core.
|
|
pub fn clear_core1_region1_monitor_interrupt(&mut self) {
|
|
self.debug_assist.core_1_intr_clr().write(|w| {
|
|
w.core_1_area_dram0_1_rd_clr()
|
|
.set_bit()
|
|
.core_1_area_dram0_1_wr_clr()
|
|
.set_bit()
|
|
});
|
|
}
|
|
|
|
/// Check, if region1 monitoring interrupt is set on secondary core.
|
|
pub fn is_core1_region1_monitor_interrupt_set(&self) -> bool {
|
|
self.debug_assist
|
|
.core_1_intr_raw()
|
|
.read()
|
|
.core_1_area_dram0_1_rd_raw()
|
|
.bit_is_set()
|
|
|| self
|
|
.debug_assist
|
|
.core_1_intr_raw()
|
|
.read()
|
|
.core_1_area_dram0_1_wr_raw()
|
|
.bit_is_set()
|
|
}
|
|
|
|
/// Get region monitoring PC value on secondary core.
|
|
pub fn core1_region_monitor_pc(&self) -> u32 {
|
|
self.debug_assist
|
|
.core_1_area_pc()
|
|
.read()
|
|
.core_1_area_pc()
|
|
.bits()
|
|
}
|
|
}
|