swaitsandClaude Opus 4.6
3102fc747a
Implement full SSD1306 OLED display support: - Splash screen on boot (1.5s) with project name, version, board - Dashboard showing radio state, config, counters, RSSI/SNR - RSSI history sparkline (64-sample ring buffer, 2px-wide bars) - DisplayOn/DisplayOff host commands routed via dedicated channel - Pure render functions against generic DrawTarget (no hardware coupling) - Display on/off control bypasses radio task entirely Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
84 lines
2.6 KiB
Rust
84 lines
2.6 KiB
Rust
//! # Time
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//!
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//! The `time` module offers a way to get the system now.
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/// Represents a duration of time.
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///
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/// The resolution is 1 microsecond, represented as a 64-bit unsigned integer.
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pub type Duration = fugit::Duration<u64, 1, 1_000_000>;
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/// Represents an instant in time.
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///
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/// The resolution is 1 microsecond, represented as a 64-bit unsigned integer.
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pub type Instant = fugit::Instant<u64, 1, 1_000_000>;
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/// Provides time since system start in microseconds precision.
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///
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/// The counter won’t measure time in sleep-mode.
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///
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/// The timer will wrap after
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#[cfg_attr(esp32, doc = "36_558 years")]
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#[cfg_attr(esp32s2, doc = "7_311 years")]
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#[cfg_attr(not(any(esp32, esp32s2)), doc = "more than 7 years")]
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pub fn now() -> Instant {
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#[cfg(esp32)]
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let (ticks, div) = {
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// on ESP32 use LACT
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let tg0 = unsafe { crate::peripherals::TIMG0::steal() };
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tg0.lactupdate().write(|w| unsafe { w.update().bits(1) });
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// The peripheral doesn't have a bit to indicate that the update is done, so we
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// poll the lower 32 bit part of the counter until it changes, or a timeout
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// expires.
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let lo_initial = tg0.lactlo().read().bits();
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let mut div = tg0.lactconfig().read().divider().bits();
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let lo = loop {
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let lo = tg0.lactlo().read().bits();
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if lo != lo_initial || div == 0 {
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break lo;
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}
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div -= 1;
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};
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let hi = tg0.lacthi().read().bits();
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let ticks = (hi as u64) << 32u64 | lo as u64;
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(ticks, 16)
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};
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#[cfg(not(esp32))]
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let (ticks, div) = {
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// otherwise use SYSTIMER
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let ticks = crate::timer::systimer::SystemTimer::now();
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(
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ticks,
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(crate::timer::systimer::SystemTimer::ticks_per_second() / 1_000_000),
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)
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};
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Instant::from_ticks(ticks / div)
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}
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#[cfg(esp32)]
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pub(crate) fn time_init() {
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let apb = crate::Clocks::get().apb_clock.to_Hz();
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// we assume 80MHz APB clock source - there is no way to configure it in a
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// different way currently
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assert_eq!(apb, 80_000_000u32);
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let tg0 = unsafe { crate::peripherals::TIMG0::steal() };
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tg0.lactconfig().write(|w| unsafe { w.bits(0) });
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tg0.lactalarmhi().write(|w| unsafe { w.bits(u32::MAX) });
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tg0.lactalarmlo().write(|w| unsafe { w.bits(u32::MAX) });
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tg0.lactload().write(|w| unsafe { w.load().bits(1) });
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// 16 MHz counter
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tg0.lactconfig()
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.modify(|_, w| unsafe { w.divider().bits((apb / 16_000_000u32) as u16) });
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tg0.lactconfig().modify(|_, w| {
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w.increase().bit(true);
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w.autoreload().bit(true);
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w.en().bit(true)
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});
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}
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